1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 2010-2013, by Broadcom, Inc. 24 * All Rights Reserved. 25 */ 26 27 /* 28 * Copyright (c) 2002, 2010, Oracle and/or its affiliates. 29 * All rights reserved. 30 * Copyright 2016 Nexenta Systems, Inc. All rights reserved. 31 */ 32 33 #include "bge_impl.h" 34 35 #define PIO_ADDR(bgep, offset) ((void *)((caddr_t)(bgep)->io_regs+(offset))) 36 #define APE_ADDR(bgep, offset) ((void *)((caddr_t)(bgep)->ape_regs+(offset))) 37 38 /* 39 * Future features ... ? 40 */ 41 #define BGE_CFG_IO8 1 /* 8/16-bit cfg space BIS/BIC */ 42 #define BGE_IND_IO32 1 /* indirect access code */ 43 #define BGE_SEE_IO32 1 /* SEEPROM access code */ 44 #define BGE_FLASH_IO32 1 /* FLASH access code */ 45 46 /* 47 * BGE MSI tunable: 48 * 49 * By default MSI is enabled on all supported platforms but it is disabled 50 * for some Broadcom chips due to known MSI hardware issues. Currently MSI 51 * is enabled only for 5714C A2 and 5715C A2 broadcom chips. 52 */ 53 boolean_t bge_enable_msi = B_TRUE; 54 55 /* 56 * PCI-X/PCI-E relaxed ordering tunable for OS/Nexus driver 57 */ 58 boolean_t bge_relaxed_ordering = B_TRUE; 59 60 /* 61 * Patchable globals: 62 * 63 * bge_autorecover 64 * Enables/disables automatic recovery after fault detection 65 * 66 * bge_mlcr_default 67 * Value to program into the MLCR; controls the chip's GPIO pins 68 * 69 * bge_dma_{rd,wr}prio 70 * Relative priorities of DMA reads & DMA writes respectively. 71 * These may each be patched to any value 0-3. Equal values 72 * will give "fair" (round-robin) arbitration for PCI access. 73 * Unequal values will give one or the other function priority. 74 * 75 * bge_dma_rwctrl 76 * Value to put in the Read/Write DMA control register. See 77 * the Broadcom PRM for things you can fiddle with in this 78 * register ... 79 * 80 * bge_{tx,rx}_{count,ticks}_{norm,intr} 81 * Send/receive interrupt coalescing parameters. Counts are 82 * #s of descriptors, ticks are in microseconds. *norm* values 83 * apply between status updates/interrupts; the *intr* values 84 * refer to the 'during-interrupt' versions - see the PRM. 85 * 86 * NOTE: these values have been determined by measurement. They 87 * differ significantly from the values recommended in the PRM. 88 */ 89 static uint32_t bge_autorecover = 1; 90 static uint32_t bge_mlcr_default_5714 = MLCR_DEFAULT_5714; 91 92 static uint32_t bge_dma_rdprio = 1; 93 static uint32_t bge_dma_wrprio = 0; 94 static uint32_t bge_dma_rwctrl = PDRWCR_VAR_DEFAULT; 95 static uint32_t bge_dma_rwctrl_5721 = PDRWCR_VAR_5721; 96 static uint32_t bge_dma_rwctrl_5714 = PDRWCR_VAR_5714; 97 static uint32_t bge_dma_rwctrl_5715 = PDRWCR_VAR_5715; 98 99 uint32_t bge_rx_ticks_norm = 128; 100 uint32_t bge_tx_ticks_norm = 512; 101 uint32_t bge_rx_count_norm = 8; 102 uint32_t bge_tx_count_norm = 128; 103 104 static uint32_t bge_rx_ticks_intr = 128; 105 static uint32_t bge_tx_ticks_intr = 0; /* 8 for FJ2+ !?!? */ 106 static uint32_t bge_rx_count_intr = 2; 107 static uint32_t bge_tx_count_intr = 0; 108 109 /* 110 * Memory pool configuration parameters. 111 * 112 * These are generally specific to each member of the chip family, since 113 * each one may have a different memory size/configuration. 114 * 115 * Setting the mbuf pool length for a specific type of chip to 0 inhibits 116 * the driver from programming the various registers; instead they are left 117 * at their hardware defaults. This is the preferred option for later chips 118 * (5705+), whereas the older chips *required* these registers to be set, 119 * since the h/w default was 0 ;-( 120 */ 121 static uint32_t bge_mbuf_pool_base = MBUF_POOL_BASE_DEFAULT; 122 static uint32_t bge_mbuf_pool_base_5704 = MBUF_POOL_BASE_5704; 123 static uint32_t bge_mbuf_pool_base_5705 = MBUF_POOL_BASE_5705; 124 static uint32_t bge_mbuf_pool_base_5721 = MBUF_POOL_BASE_5721; 125 static uint32_t bge_mbuf_pool_len = MBUF_POOL_LENGTH_DEFAULT; 126 static uint32_t bge_mbuf_pool_len_5704 = MBUF_POOL_LENGTH_5704; 127 static uint32_t bge_mbuf_pool_len_5705 = 0; /* use h/w default */ 128 static uint32_t bge_mbuf_pool_len_5721 = 0; 129 130 /* 131 * Various high and low water marks, thresholds, etc ... 132 * 133 * Note: these are taken from revision 7 of the PRM, and some are different 134 * from both the values in earlier PRMs *and* those determined experimentally 135 * and used in earlier versions of this driver ... 136 */ 137 static uint32_t bge_mbuf_hi_water = MBUF_HIWAT_DEFAULT; 138 static uint32_t bge_mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_DEFAULT; 139 static uint32_t bge_mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_DEFAULT; 140 141 static uint32_t bge_dmad_lo_water = DMAD_POOL_LOWAT_DEFAULT; 142 static uint32_t bge_dmad_hi_water = DMAD_POOL_HIWAT_DEFAULT; 143 static uint32_t bge_lowat_recv_frames = LOWAT_MAX_RECV_FRAMES_DEFAULT; 144 145 static uint32_t bge_replenish_std = STD_RCV_BD_REPLENISH_DEFAULT; 146 static uint32_t bge_replenish_mini = MINI_RCV_BD_REPLENISH_DEFAULT; 147 static uint32_t bge_replenish_jumbo = JUMBO_RCV_BD_REPLENISH_DEFAULT; 148 149 static uint32_t bge_watchdog_count = 1 << 16; 150 static uint16_t bge_dma_miss_limit = 20; 151 152 static uint32_t bge_stop_start_on_sync = 0; 153 154 /* 155 * bge_intr_max_loop controls the maximum loop number within bge_intr. 156 * When loading NIC with heavy network traffic, it is useful. 157 * Increasing this value could have positive effect to throughput, 158 * but it might also increase ticks of a bge ISR stick on CPU, which might 159 * lead to bad UI interactive experience. So tune this with caution. 160 */ 161 static int bge_intr_max_loop = 1; 162 163 /* 164 * ========== Low-level chip & ring buffer manipulation ========== 165 */ 166 167 #define BGE_DBG BGE_DBG_REGS /* debug flag for this code */ 168 169 170 /* 171 * Config space read-modify-write routines 172 */ 173 174 #if BGE_CFG_IO8 175 176 static void bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits); 177 #pragma inline(bge_cfg_clr16) 178 179 static void 180 bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits) 181 { 182 uint16_t regval; 183 184 BGE_TRACE(("bge_cfg_clr16($%p, 0x%lx, 0x%x)", 185 (void *)bgep, regno, bits)); 186 187 regval = pci_config_get16(bgep->cfg_handle, regno); 188 189 BGE_DEBUG(("bge_cfg_clr16($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 190 (void *)bgep, regno, bits, regval, regval & ~bits)); 191 192 regval &= ~bits; 193 pci_config_put16(bgep->cfg_handle, regno, regval); 194 } 195 196 #endif /* BGE_CFG_IO8 */ 197 198 static void bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 199 #pragma inline(bge_cfg_clr32) 200 201 static void 202 bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 203 { 204 uint32_t regval; 205 206 BGE_TRACE(("bge_cfg_clr32($%p, 0x%lx, 0x%x)", 207 (void *)bgep, regno, bits)); 208 209 regval = pci_config_get32(bgep->cfg_handle, regno); 210 211 BGE_DEBUG(("bge_cfg_clr32($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 212 (void *)bgep, regno, bits, regval, regval & ~bits)); 213 214 regval &= ~bits; 215 pci_config_put32(bgep->cfg_handle, regno, regval); 216 } 217 218 #if BGE_IND_IO32 219 220 /* 221 * Indirect access to registers & RISC scratchpads, using config space 222 * accesses only. 223 * 224 * This isn't currently used, but someday we might want to use it for 225 * restoring the Subsystem Device/Vendor registers (which aren't directly 226 * writable in Config Space), or for downloading firmware into the RISCs 227 * 228 * In any case there are endian issues to be resolved before this code is 229 * enabled; the bizarre way that bytes get twisted by this chip AND by 230 * the PCI bridge in SPARC systems mean that we shouldn't enable it until 231 * it's been thoroughly tested for all access sizes on all supported 232 * architectures (SPARC *and* x86!). 233 */ 234 uint32_t bge_ind_get32(bge_t *bgep, bge_regno_t regno); 235 #pragma inline(bge_ind_get32) 236 237 uint32_t 238 bge_ind_get32(bge_t *bgep, bge_regno_t regno) 239 { 240 uint32_t val; 241 242 BGE_TRACE(("bge_ind_get32($%p, 0x%lx)", (void *)bgep, regno)); 243 244 #ifdef __sparc 245 if (DEVICE_5717_SERIES_CHIPSETS(bgep) || 246 DEVICE_5725_SERIES_CHIPSETS(bgep) || 247 DEVICE_57765_SERIES_CHIPSETS(bgep)) { 248 regno = LE_32(regno); 249 } 250 #endif 251 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 252 val = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_RIADR); 253 254 BGE_DEBUG(("bge_ind_get32($%p, 0x%lx) => 0x%x", 255 (void *)bgep, regno, val)); 256 257 val = LE_32(val); 258 259 return (val); 260 } 261 262 void bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val); 263 #pragma inline(bge_ind_put32) 264 265 void 266 bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val) 267 { 268 BGE_TRACE(("bge_ind_put32($%p, 0x%lx, 0x%x)", 269 (void *)bgep, regno, val)); 270 271 val = LE_32(val); 272 #ifdef __sparc 273 if (DEVICE_5717_SERIES_CHIPSETS(bgep) || 274 DEVICE_5725_SERIES_CHIPSETS(bgep) || 275 DEVICE_57765_SERIES_CHIPSETS(bgep)) { 276 regno = LE_32(regno); 277 } 278 #endif 279 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 280 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIADR, val); 281 } 282 283 #endif /* BGE_IND_IO32 */ 284 285 #if BGE_DEBUGGING 286 287 static void bge_pci_check(bge_t *bgep); 288 #pragma no_inline(bge_pci_check) 289 290 static void 291 bge_pci_check(bge_t *bgep) 292 { 293 uint16_t pcistatus; 294 295 pcistatus = pci_config_get16(bgep->cfg_handle, PCI_CONF_STAT); 296 if ((pcistatus & (PCI_STAT_R_MAST_AB | PCI_STAT_R_TARG_AB)) != 0) 297 BGE_DEBUG(("bge_pci_check($%p): PCI status 0x%x", 298 (void *)bgep, pcistatus)); 299 } 300 301 #endif /* BGE_DEBUGGING */ 302 303 /* 304 * Perform first-stage chip (re-)initialisation, using only config-space 305 * accesses: 306 * 307 * + Read the vendor/device/revision/subsystem/cache-line-size registers, 308 * returning the data in the structure pointed to by <idp>. 309 * + Configure the target-mode endianness (swap) options. 310 * + Disable interrupts and enable Memory Space accesses. 311 * + Enable or disable Bus Mastering according to the <enable_dma> flag. 312 * 313 * This sequence is adapted from Broadcom document 570X-PG102-R, 314 * page 102, steps 1-3, 6-8 and 11-13. The omitted parts of the sequence 315 * are 4 and 5 (Reset Core and wait) which are handled elsewhere. 316 * 317 * This function MUST be called before any non-config-space accesses 318 * are made; on this first call <enable_dma> is B_FALSE, and it 319 * effectively performs steps 3-1(!) of the initialisation sequence 320 * (the rest are not required but should be harmless). 321 * 322 * It MUST also be called after a chip reset, as this disables 323 * Memory Space cycles! In this case, <enable_dma> is B_TRUE, and 324 * it is effectively performing steps 6-8. 325 */ 326 void bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma); 327 #pragma no_inline(bge_chip_cfg_init) 328 329 void 330 bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma) 331 { 332 ddi_acc_handle_t handle; 333 uint16_t command; 334 uint32_t mhcr; 335 uint32_t prodid; 336 uint32_t pci_state; 337 uint16_t value16; 338 int i; 339 340 BGE_TRACE(("bge_chip_cfg_init($%p, $%p, %d)", 341 (void *)bgep, (void *)cidp, enable_dma)); 342 343 /* 344 * Step 3: save PCI cache line size and subsystem vendor ID 345 * 346 * Read all the config-space registers that characterise the 347 * chip, specifically vendor/device/revision/subsystem vendor 348 * and subsystem device id. We expect (but don't check) that 349 * (vendor == VENDOR_ID_BROADCOM) && (device == DEVICE_ID_5704) 350 * 351 * Also save all bus-transaction related registers (cache-line 352 * size, bus-grant/latency parameters, etc). Some of these are 353 * cleared by reset, so we'll have to restore them later. This 354 * comes from the Broadcom document 570X-PG102-R ... 355 * 356 * Note: Broadcom document 570X-PG102-R seems to be in error 357 * here w.r.t. the offsets of the Subsystem Vendor ID and 358 * Subsystem (Device) ID registers, which are the opposite way 359 * round according to the PCI standard. For good measure, we 360 * save/restore both anyway. 361 */ 362 handle = bgep->cfg_handle; 363 364 /* 365 * For some chipsets (e.g., BCM5718), if MHCR_ENABLE_ENDIAN_BYTE_SWAP 366 * has been set in PCI_CONF_COMM already, we need to write the 367 * byte-swapped value to it. So we just write zero first for simplicity. 368 */ 369 cidp->device = pci_config_get16(handle, PCI_CONF_DEVID); 370 if (DEVICE_5717_SERIES_CHIPSETS(bgep) || 371 DEVICE_5725_SERIES_CHIPSETS(bgep) || 372 DEVICE_57765_SERIES_CHIPSETS(bgep)) { 373 pci_config_put32(handle, PCI_CONF_BGE_MHCR, 0); 374 } 375 376 mhcr = pci_config_get32(handle, PCI_CONF_BGE_MHCR); 377 cidp->asic_rev = (mhcr & MHCR_CHIP_REV_MASK); 378 cidp->asic_rev_prod_id = 0; 379 if ((cidp->asic_rev & 0xf0000000) == CHIP_ASIC_REV_USE_PROD_ID_REG) { 380 prodid = CHIP_ASIC_REV_PROD_ID_REG; 381 if (DEVICE_5717_SERIES_CHIPSETS(bgep) || 382 DEVICE_5725_SERIES_CHIPSETS(bgep)) { 383 prodid = CHIP_ASIC_REV_PROD_ID_GEN2_REG; 384 } else if (DEVICE_57765_SERIES_CHIPSETS(bgep)) { 385 prodid = CHIP_ASIC_REV_PROD_ID_GEN15_REG; 386 } 387 cidp->asic_rev_prod_id = pci_config_get32(handle, prodid); 388 } 389 390 cidp->businfo = pci_config_get32(handle, PCI_CONF_BGE_PCISTATE); 391 cidp->command = pci_config_get16(handle, PCI_CONF_COMM); 392 393 cidp->vendor = pci_config_get16(handle, PCI_CONF_VENID); 394 cidp->subven = pci_config_get16(handle, PCI_CONF_SUBVENID); 395 cidp->subdev = pci_config_get16(handle, PCI_CONF_SUBSYSID); 396 cidp->revision = pci_config_get8(handle, PCI_CONF_REVID); 397 cidp->clsize = pci_config_get8(handle, PCI_CONF_CACHE_LINESZ); 398 cidp->latency = pci_config_get8(handle, PCI_CONF_LATENCY_TIMER); 399 400 /* 5717 C0 is treated just like 5720 A0 */ 401 if (pci_config_get16(bgep->cfg_handle, PCI_CONF_DEVID) == 402 DEVICE_ID_5717_C0) { 403 cidp->device = DEVICE_ID_5720; 404 } 405 406 BGE_DEBUG(("bge_chip_cfg_init: %s bus is %s and %s; #INTA is %s", 407 cidp->businfo & PCISTATE_BUS_IS_PCI ? "PCI" : "PCI-X", 408 cidp->businfo & PCISTATE_BUS_IS_FAST ? "fast" : "slow", 409 cidp->businfo & PCISTATE_BUS_IS_32_BIT ? "narrow" : "wide", 410 cidp->businfo & PCISTATE_INTA_STATE ? "high" : "low")); 411 BGE_DEBUG(("bge_chip_cfg_init: vendor 0x%x device 0x%x revision 0x%x", 412 cidp->vendor, cidp->device, cidp->revision)); 413 BGE_DEBUG(("bge_chip_cfg_init: subven 0x%x subdev 0x%x asic_rev 0x%x", 414 cidp->subven, cidp->subdev, cidp->asic_rev)); 415 BGE_DEBUG(("bge_chip_cfg_init: clsize %d latency %d command 0x%x", 416 cidp->clsize, cidp->latency, cidp->command)); 417 418 /* 419 * Step 2 (also step 6): disable and clear interrupts. 420 * Steps 11-13: configure PIO endianness options, and enable 421 * indirect register access. We'll also select any other 422 * options controlled by the MHCR (e.g. tagged status, mask 423 * interrupt mode) at this stage ... 424 * 425 * Note: internally, the chip is 64-bit and BIG-endian, but 426 * since it talks to the host over a (LITTLE-endian) PCI bus, 427 * it normally swaps bytes around at the PCI interface. 428 * However, the PCI host bridge on SPARC systems normally 429 * swaps the byte lanes around too, since SPARCs are also 430 * BIG-endian. So it turns out that on SPARC, the right 431 * option is to tell the chip to swap (and the host bridge 432 * will swap back again), whereas on x86 we ask the chip 433 * NOT to swap, so the natural little-endianness of the 434 * PCI bus is assumed. Then the only thing that doesn't 435 * automatically work right is access to an 8-byte register 436 * by a little-endian host; but we don't want to set the 437 * MHCR_ENABLE_REGISTER_WORD_SWAP bit because then 4-byte 438 * accesses don't go where expected ;-( So we live with 439 * that, and perform word-swaps in software in the few cases 440 * where a chip register is defined as an 8-byte value -- 441 * see the code below for details ... 442 * 443 * Note: the meaning of the 'MASK_INTERRUPT_MODE' bit isn't 444 * very clear in the register description in the PRM, but 445 * Broadcom document 570X-PG104-R page 248 explains a little 446 * more (under "Broadcom Mask Mode"). The bit changes the way 447 * the MASK_PCI_INT_OUTPUT bit works: with MASK_INTERRUPT_MODE 448 * clear, the chip interprets MASK_PCI_INT_OUTPUT in the same 449 * way as the 5700 did, which isn't very convenient. Setting 450 * the MASK_INTERRUPT_MODE bit makes the MASK_PCI_INT_OUTPUT 451 * bit do just what its name says -- MASK the PCI #INTA output 452 * (i.e. deassert the signal at the pin) leaving all internal 453 * state unchanged. This is much more convenient for our 454 * interrupt handler, so we set MASK_INTERRUPT_MODE here. 455 * 456 * Note: the inconvenient semantics of the interrupt mailbox 457 * (nonzero disables and acknowledges/clears the interrupt, 458 * zero enables AND CLEARS it) would make race conditions 459 * likely in the interrupt handler: 460 * 461 * (1) acknowledge & disable interrupts 462 * (2) while (more to do) 463 * process packets 464 * (3) enable interrupts -- also clears pending 465 * 466 * If the chip received more packets and internally generated 467 * an interrupt between the check at (2) and the mbox write 468 * at (3), this interrupt would be lost :-( 469 * 470 * The best way to avoid this is to use TAGGED STATUS mode, 471 * where the chip includes a unique tag in each status block 472 * update, and the host, when re-enabling interrupts, passes 473 * the last tag it saw back to the chip; then the chip can 474 * see whether the host is truly up to date, and regenerate 475 * its interrupt if not. 476 */ 477 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 478 MHCR_ENABLE_PCI_STATE_RW | 479 MHCR_ENABLE_TAGGED_STATUS_MODE | 480 MHCR_MASK_INTERRUPT_MODE | 481 MHCR_CLEAR_INTERRUPT_INTA; 482 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 483 mhcr |= MHCR_MASK_PCI_INT_OUTPUT; 484 485 #ifdef _BIG_ENDIAN 486 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 487 #endif /* _BIG_ENDIAN */ 488 pci_config_put32(handle, PCI_CONF_BGE_MHCR, mhcr); 489 490 #ifdef BGE_IPMI_ASF 491 bgep->asf_wordswapped = B_FALSE; 492 #endif 493 494 pci_state = (PCISTATE_EXT_ROM_ENABLE | PCISTATE_EXT_ROM_RETRY); 495 /* allow reads and writes to the APE register and memory space */ 496 if (bgep->ape_enabled) { 497 pci_state |= PCISTATE_ALLOW_APE_CTLSPC_WR | 498 PCISTATE_ALLOW_APE_SHMEM_WR | PCISTATE_ALLOW_APE_PSPACE_WR; 499 } 500 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_PCISTATE, pci_state); 501 502 /* 503 * Step 1 (also step 7): Enable PCI Memory Space accesses 504 * Disable Memory Write/Invalidate 505 * Enable or disable Bus Mastering 506 * 507 * Note that all other bits are taken from the original value saved 508 * the first time through here, rather than from the current register 509 * value, 'cos that will have been cleared by a soft RESET since. 510 * In this way we preserve the OBP/nexus-parent's preferred settings 511 * of the parity-error and system-error enable bits across multiple 512 * chip RESETs. 513 */ 514 command = bgep->chipid.command | PCI_COMM_MAE; 515 command &= ~(PCI_COMM_ME|PCI_COMM_MEMWR_INVAL); 516 if (enable_dma) 517 command |= PCI_COMM_ME; 518 /* 519 * on BCM5714 revision A0, false parity error gets generated 520 * due to a logic bug. Provide a workaround by disabling parity 521 * error. 522 */ 523 if (((cidp->device == DEVICE_ID_5714C) || 524 (cidp->device == DEVICE_ID_5714S)) && 525 (cidp->revision == REVISION_ID_5714_A0)) { 526 command &= ~PCI_COMM_PARITY_DETECT; 527 } 528 pci_config_put16(handle, PCI_CONF_COMM, command); 529 530 /* 531 * On some PCI-E device, there were instances when 532 * the device was still link training. 533 */ 534 if (bgep->chipid.pci_type == BGE_PCI_E) { 535 i = 0; 536 value16 = pci_config_get16(handle, PCI_CONF_COMM); 537 while ((value16 != command) && (i < 100)) { 538 drv_usecwait(200); 539 value16 = pci_config_get16(handle, PCI_CONF_COMM); 540 ++i; 541 } 542 } 543 544 /* 545 * Clear any remaining error status bits 546 */ 547 pci_config_put16(handle, PCI_CONF_STAT, ~0); 548 549 /* 550 * Do following if and only if the device is NOT BCM5714C OR 551 * BCM5715C 552 */ 553 if (!((cidp->device == DEVICE_ID_5714C) || 554 (cidp->device == DEVICE_ID_5715C))) { 555 /* 556 * Make sure these indirect-access registers are sane 557 * rather than random after power-up or reset 558 */ 559 pci_config_put32(handle, PCI_CONF_BGE_RIAAR, 0); 560 pci_config_put32(handle, PCI_CONF_BGE_MWBAR, 0); 561 } 562 /* 563 * Step 8: Disable PCI-X/PCI-E Relaxed Ordering 564 */ 565 bge_cfg_clr16(bgep, PCIX_CONF_COMM, PCIX_COMM_RELAXED); 566 567 if (cidp->pci_type == BGE_PCI_E) { 568 if (DEVICE_5723_SERIES_CHIPSETS(bgep)) { 569 bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL_5723, 570 DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED); 571 } else if (DEVICE_5717_SERIES_CHIPSETS(bgep) || 572 DEVICE_5725_SERIES_CHIPSETS(bgep) || 573 DEVICE_57765_SERIES_CHIPSETS(bgep)) { 574 bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL_5717, 575 DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED); 576 } else { 577 bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL, 578 DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED); 579 } 580 } 581 } 582 583 #ifdef __amd64 584 /* 585 * Distinguish CPU types 586 * 587 * These use to distinguish AMD64 or Intel EM64T of CPU running mode. 588 * If CPU runs on Intel EM64T mode,the 64bit operation cannot works fine 589 * for PCI-Express based network interface card. This is the work-around 590 * for those nics. 591 */ 592 static boolean_t bge_get_em64t_type(void); 593 #pragma inline(bge_get_em64t_type) 594 595 static boolean_t 596 bge_get_em64t_type(void) 597 { 598 599 return (x86_vendor == X86_VENDOR_Intel); 600 } 601 #endif 602 603 /* 604 * Operating register get/set access routines 605 */ 606 607 uint32_t bge_reg_get32(bge_t *bgep, bge_regno_t regno); 608 #pragma inline(bge_reg_get32) 609 610 uint32_t 611 bge_reg_get32(bge_t *bgep, bge_regno_t regno) 612 { 613 BGE_TRACE(("bge_reg_get32($%p, 0x%lx)", 614 (void *)bgep, regno)); 615 616 return (ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno))); 617 } 618 619 void bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data); 620 #pragma inline(bge_reg_put32) 621 622 void 623 bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data) 624 { 625 BGE_TRACE(("bge_reg_put32($%p, 0x%lx, 0x%x)", 626 (void *)bgep, regno, data)); 627 628 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), data); 629 BGE_PCICHK(bgep); 630 } 631 632 void bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 633 #pragma inline(bge_reg_set32) 634 635 void 636 bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 637 { 638 uint32_t regval; 639 640 BGE_TRACE(("bge_reg_set32($%p, 0x%lx, 0x%x)", 641 (void *)bgep, regno, bits)); 642 643 regval = bge_reg_get32(bgep, regno); 644 regval |= bits; 645 bge_reg_put32(bgep, regno, regval); 646 } 647 648 void bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 649 #pragma inline(bge_reg_clr32) 650 651 void 652 bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 653 { 654 uint32_t regval; 655 656 BGE_TRACE(("bge_reg_clr32($%p, 0x%lx, 0x%x)", 657 (void *)bgep, regno, bits)); 658 659 regval = bge_reg_get32(bgep, regno); 660 regval &= ~bits; 661 bge_reg_put32(bgep, regno, regval); 662 } 663 664 static uint64_t bge_reg_get64(bge_t *bgep, bge_regno_t regno); 665 #pragma inline(bge_reg_get64) 666 667 static uint64_t 668 bge_reg_get64(bge_t *bgep, bge_regno_t regno) 669 { 670 uint64_t regval; 671 672 #ifdef __amd64 673 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || 674 bge_get_em64t_type() || 675 DEVICE_5717_SERIES_CHIPSETS(bgep) || 676 DEVICE_5725_SERIES_CHIPSETS(bgep) || 677 DEVICE_57765_SERIES_CHIPSETS(bgep)) { 678 regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4)); 679 regval <<= 32; 680 regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 681 } else { 682 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 683 } 684 #elif defined(__sparc) 685 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || 686 DEVICE_5717_SERIES_CHIPSETS(bgep) || 687 DEVICE_5725_SERIES_CHIPSETS(bgep) || 688 DEVICE_57765_SERIES_CHIPSETS(bgep)) { 689 regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 690 regval <<= 32; 691 regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4)); 692 } else { 693 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 694 } 695 #else 696 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 697 #endif 698 699 #ifdef _LITTLE_ENDIAN 700 regval = (regval >> 32) | (regval << 32); 701 #endif /* _LITTLE_ENDIAN */ 702 703 BGE_TRACE(("bge_reg_get64($%p, 0x%lx) = 0x%016llx", 704 (void *)bgep, regno, regval)); 705 706 return (regval); 707 } 708 709 static void bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data); 710 #pragma inline(bge_reg_put64) 711 712 static void 713 bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data) 714 { 715 BGE_TRACE(("bge_reg_put64($%p, 0x%lx, 0x%016llx)", 716 (void *)bgep, regno, data)); 717 718 #ifdef _LITTLE_ENDIAN 719 data = ((data >> 32) | (data << 32)); 720 #endif /* _LITTLE_ENDIAN */ 721 722 #ifdef __amd64 723 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || 724 bge_get_em64t_type() || 725 DEVICE_5717_SERIES_CHIPSETS(bgep) || 726 DEVICE_5725_SERIES_CHIPSETS(bgep) || 727 DEVICE_57765_SERIES_CHIPSETS(bgep)) { 728 ddi_put32(bgep->io_handle, 729 PIO_ADDR(bgep, regno), (uint32_t)data); 730 BGE_PCICHK(bgep); 731 ddi_put32(bgep->io_handle, 732 PIO_ADDR(bgep, regno + 4), (uint32_t)(data >> 32)); 733 734 } else { 735 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 736 } 737 #elif defined(__sparc) 738 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || 739 DEVICE_5717_SERIES_CHIPSETS(bgep) || 740 DEVICE_5725_SERIES_CHIPSETS(bgep) || 741 DEVICE_57765_SERIES_CHIPSETS(bgep)) { 742 ddi_put32(bgep->io_handle, 743 PIO_ADDR(bgep, regno + 4), (uint32_t)data); 744 BGE_PCICHK(bgep); 745 ddi_put32(bgep->io_handle, 746 PIO_ADDR(bgep, regno), (uint32_t)(data >> 32)); 747 } else { 748 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 749 } 750 #else 751 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 752 #endif 753 754 BGE_PCICHK(bgep); 755 } 756 757 /* 758 * The DDI doesn't provide get/put functions for 128 bit data 759 * so we put RCBs out as two 64-bit chunks instead. 760 */ 761 static void bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 762 #pragma inline(bge_reg_putrcb) 763 764 static void 765 bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 766 { 767 uint64_t *p; 768 769 BGE_TRACE(("bge_reg_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 770 (void *)bgep, addr, rcbp->host_ring_addr, 771 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 772 773 ASSERT((addr % sizeof (*rcbp)) == 0); 774 775 p = (void *)rcbp; 776 bge_reg_put64(bgep, addr, *p++); 777 bge_reg_put64(bgep, addr+8, *p); 778 } 779 780 void bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data); 781 #pragma inline(bge_mbx_put) 782 783 void 784 bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data) 785 { 786 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) 787 regno += INTERRUPT_LP_MBOX_0_REG - INTERRUPT_MBOX_0_REG + 4; 788 789 BGE_TRACE(("bge_mbx_put($%p, 0x%lx, 0x%016llx)", 790 (void *)bgep, regno, data)); 791 792 /* 793 * Mailbox registers are nominally 64 bits on the 5701, but 794 * the MSW isn't used. On the 5703, they're only 32 bits 795 * anyway. So here we just write the lower(!) 32 bits - 796 * remembering that the chip is big-endian, even though the 797 * PCI bus is little-endian ... 798 */ 799 #ifdef _BIG_ENDIAN 800 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno+4), (uint32_t)data); 801 #else 802 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), (uint32_t)data); 803 #endif /* _BIG_ENDIAN */ 804 BGE_PCICHK(bgep); 805 } 806 807 uint32_t bge_mbx_get(bge_t *bgep, bge_regno_t regno); 808 #pragma inline(bge_mbx_get) 809 810 uint32_t 811 bge_mbx_get(bge_t *bgep, bge_regno_t regno) 812 { 813 uint32_t val32; 814 815 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) 816 regno += INTERRUPT_LP_MBOX_0_REG - INTERRUPT_MBOX_0_REG + 4; 817 818 BGE_TRACE(("bge_mbx_get($%p, 0x%lx)", 819 (void *)bgep, regno)); 820 821 #ifdef _BIG_ENDIAN 822 val32 = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno+4)); 823 #else 824 val32 = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 825 #endif /* _BIG_ENDIAN */ 826 BGE_PCICHK(bgep); 827 828 BGE_DEBUG(("bge_mbx_get($%p, 0x%lx) => 0x%08x", 829 (void *)bgep, regno, val32)); 830 831 return (val32); 832 } 833 834 835 #if BGE_DEBUGGING 836 837 void bge_led_mark(bge_t *bgep); 838 #pragma no_inline(bge_led_mark) 839 840 void 841 bge_led_mark(bge_t *bgep) 842 { 843 uint32_t led_ctrl = LED_CONTROL_OVERRIDE_LINK | 844 LED_CONTROL_1000MBPS_LED | 845 LED_CONTROL_100MBPS_LED | 846 LED_CONTROL_10MBPS_LED; 847 848 /* 849 * Blink all three LINK LEDs on simultaneously, then all off, 850 * then restore to automatic hardware control. This is used 851 * in laboratory testing to trigger a logic analyser or scope. 852 */ 853 bge_reg_set32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 854 led_ctrl ^= LED_CONTROL_OVERRIDE_LINK; 855 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 856 led_ctrl = LED_CONTROL_OVERRIDE_LINK; 857 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 858 } 859 860 #endif /* BGE_DEBUGGING */ 861 862 /* 863 * NIC on-chip memory access routines 864 * 865 * Only 32K of NIC memory is visible at a time, controlled by the 866 * Memory Window Base Address Register (in PCI config space). Once 867 * this is set, the 32K region of NIC-local memory that it refers 868 * to can be directly addressed in the upper 32K of the 64K of PCI 869 * memory space used for the device. 870 */ 871 872 static void bge_nic_setwin(bge_t *bgep, bge_regno_t base); 873 #pragma inline(bge_nic_setwin) 874 875 static void 876 bge_nic_setwin(bge_t *bgep, bge_regno_t base) 877 { 878 chip_id_t *cidp; 879 880 BGE_TRACE(("bge_nic_setwin($%p, 0x%lx)", 881 (void *)bgep, base)); 882 883 ASSERT((base & MWBAR_GRANULE_MASK) == 0); 884 885 /* 886 * Don't do repeated zero data writes, 887 * if the device is BCM5714C/15C. 888 */ 889 cidp = &bgep->chipid; 890 if ((cidp->device == DEVICE_ID_5714C) || 891 (cidp->device == DEVICE_ID_5715C)) { 892 if (bgep->lastWriteZeroData && (base == (bge_regno_t)0)) 893 return; 894 /* Adjust lastWriteZeroData */ 895 bgep->lastWriteZeroData = ((base == (bge_regno_t)0) ? 896 B_TRUE : B_FALSE); 897 } 898 #ifdef __sparc 899 if (DEVICE_5717_SERIES_CHIPSETS(bgep) || 900 DEVICE_5725_SERIES_CHIPSETS(bgep) || 901 DEVICE_57765_SERIES_CHIPSETS(bgep)) { 902 base = LE_32(base); 903 } 904 #endif 905 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, base); 906 } 907 908 static uint32_t bge_nic_get32(bge_t *bgep, bge_regno_t addr); 909 #pragma inline(bge_nic_get32) 910 911 static uint32_t 912 bge_nic_get32(bge_t *bgep, bge_regno_t addr) 913 { 914 uint32_t data; 915 916 #if defined(BGE_IPMI_ASF) && !defined(__sparc) 917 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 918 /* workaround for word swap error */ 919 if (addr & 4) 920 addr = addr - 4; 921 else 922 addr = addr + 4; 923 } 924 #endif 925 926 #ifdef __sparc 927 data = bge_nic_read32(bgep, addr); 928 #else 929 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 930 addr &= MWBAR_GRANULE_MASK; 931 addr += NIC_MEM_WINDOW_OFFSET; 932 933 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 934 #endif 935 936 BGE_TRACE(("bge_nic_get32($%p, 0x%lx) = 0x%08x", 937 (void *)bgep, addr, data)); 938 939 return (data); 940 } 941 942 void bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data); 943 #pragma inline(bge_nic_put32) 944 945 void 946 bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data) 947 { 948 BGE_TRACE(("bge_nic_put32($%p, 0x%lx, 0x%08x)", 949 (void *)bgep, addr, data)); 950 951 #if defined(BGE_IPMI_ASF) && !defined(__sparc) 952 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 953 /* workaround for word swap error */ 954 if (addr & 4) 955 addr = addr - 4; 956 else 957 addr = addr + 4; 958 } 959 #endif 960 961 #ifdef __sparc 962 if (DEVICE_5717_SERIES_CHIPSETS(bgep) || 963 DEVICE_5725_SERIES_CHIPSETS(bgep) || 964 DEVICE_57765_SERIES_CHIPSETS(bgep)) { 965 addr = LE_32(addr); 966 } 967 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr); 968 data = LE_32(data); 969 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR, data); 970 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0); 971 #else 972 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 973 addr &= MWBAR_GRANULE_MASK; 974 addr += NIC_MEM_WINDOW_OFFSET; 975 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), data); 976 BGE_PCICHK(bgep); 977 #endif 978 } 979 980 static uint64_t bge_nic_get64(bge_t *bgep, bge_regno_t addr); 981 #pragma inline(bge_nic_get64) 982 983 static uint64_t 984 bge_nic_get64(bge_t *bgep, bge_regno_t addr) 985 { 986 uint64_t data; 987 988 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 989 addr &= MWBAR_GRANULE_MASK; 990 addr += NIC_MEM_WINDOW_OFFSET; 991 992 #ifdef __amd64 993 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || 994 bge_get_em64t_type() || 995 DEVICE_5717_SERIES_CHIPSETS(bgep) || 996 DEVICE_5725_SERIES_CHIPSETS(bgep) || 997 DEVICE_57765_SERIES_CHIPSETS(bgep)) { 998 data = ddi_get32(bgep->io_handle, 999 PIO_ADDR(bgep, addr + 4)); 1000 data <<= 32; 1001 data |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 1002 } else { 1003 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 1004 } 1005 #elif defined(__sparc) 1006 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || 1007 DEVICE_5717_SERIES_CHIPSETS(bgep) || 1008 DEVICE_5725_SERIES_CHIPSETS(bgep) || 1009 DEVICE_57765_SERIES_CHIPSETS(bgep)) { 1010 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 1011 data <<= 32; 1012 data |= ddi_get32(bgep->io_handle, 1013 PIO_ADDR(bgep, addr + 4)); 1014 } else { 1015 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 1016 } 1017 #else 1018 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 1019 #endif 1020 1021 BGE_TRACE(("bge_nic_get64($%p, 0x%lx) = 0x%016llx", 1022 (void *)bgep, addr, data)); 1023 1024 return (data); 1025 } 1026 1027 static void bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data); 1028 #pragma inline(bge_nic_put64) 1029 1030 static void 1031 bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data) 1032 { 1033 BGE_TRACE(("bge_nic_put64($%p, 0x%lx, 0x%016llx)", 1034 (void *)bgep, addr, data)); 1035 1036 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 1037 addr &= MWBAR_GRANULE_MASK; 1038 addr += NIC_MEM_WINDOW_OFFSET; 1039 1040 #ifdef __amd64 1041 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || 1042 bge_get_em64t_type() || 1043 DEVICE_5717_SERIES_CHIPSETS(bgep) || 1044 DEVICE_5725_SERIES_CHIPSETS(bgep) || 1045 DEVICE_57765_SERIES_CHIPSETS(bgep)) { 1046 ddi_put32(bgep->io_handle, 1047 PIO_ADDR(bgep, addr + 4), (uint32_t)data); 1048 BGE_PCICHK(bgep); 1049 ddi_put32(bgep->io_handle, 1050 PIO_ADDR(bgep, addr), (uint32_t)(data >> 32)); 1051 } else { 1052 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 1053 } 1054 #elif defined(__sparc) 1055 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || 1056 DEVICE_5717_SERIES_CHIPSETS(bgep) || 1057 DEVICE_5725_SERIES_CHIPSETS(bgep) || 1058 DEVICE_57765_SERIES_CHIPSETS(bgep)) { 1059 ddi_put32(bgep->io_handle, 1060 PIO_ADDR(bgep, addr + 4), (uint32_t)data); 1061 BGE_PCICHK(bgep); 1062 ddi_put32(bgep->io_handle, 1063 PIO_ADDR(bgep, addr), (uint32_t)(data >> 32)); 1064 } else { 1065 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 1066 } 1067 #else 1068 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 1069 #endif 1070 1071 BGE_PCICHK(bgep); 1072 } 1073 1074 /* 1075 * The DDI doesn't provide get/put functions for 128 bit data 1076 * so we put RCBs out as two 64-bit chunks instead. 1077 */ 1078 static void bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 1079 #pragma inline(bge_nic_putrcb) 1080 1081 static void 1082 bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 1083 { 1084 uint64_t *p; 1085 1086 BGE_TRACE(("bge_nic_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 1087 (void *)bgep, addr, rcbp->host_ring_addr, 1088 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 1089 1090 ASSERT((addr % sizeof (*rcbp)) == 0); 1091 1092 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 1093 addr &= MWBAR_GRANULE_MASK; 1094 addr += NIC_MEM_WINDOW_OFFSET; 1095 1096 p = (void *)rcbp; 1097 #ifdef __amd64 1098 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || 1099 bge_get_em64t_type() || 1100 DEVICE_5717_SERIES_CHIPSETS(bgep) || 1101 DEVICE_5725_SERIES_CHIPSETS(bgep) || 1102 DEVICE_57765_SERIES_CHIPSETS(bgep)) { 1103 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), 1104 (uint32_t)(*p)); 1105 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4), 1106 (uint32_t)(*p++ >> 32)); 1107 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8), 1108 (uint32_t)(*p)); 1109 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12), 1110 (uint32_t)(*p >> 32)); 1111 1112 } else { 1113 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 1114 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr+8), *p); 1115 } 1116 #elif defined(__sparc) 1117 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || 1118 DEVICE_5717_SERIES_CHIPSETS(bgep) || 1119 DEVICE_5725_SERIES_CHIPSETS(bgep) || 1120 DEVICE_57765_SERIES_CHIPSETS(bgep)) { 1121 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4), 1122 (uint32_t)(*p)); 1123 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), 1124 (uint32_t)(*p++ >> 32)); 1125 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12), 1126 (uint32_t)(*p)); 1127 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8), 1128 (uint32_t)(*p >> 32)); 1129 } else { 1130 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 1131 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p); 1132 } 1133 #else 1134 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 1135 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p); 1136 #endif 1137 1138 BGE_PCICHK(bgep); 1139 } 1140 1141 static void bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes); 1142 #pragma inline(bge_nic_zero) 1143 1144 static void 1145 bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes) 1146 { 1147 BGE_TRACE(("bge_nic_zero($%p, 0x%lx, 0x%x)", 1148 (void *)bgep, addr, nbytes)); 1149 1150 ASSERT((addr & ~MWBAR_GRANULE_MASK) == 1151 ((addr+nbytes) & ~MWBAR_GRANULE_MASK)); 1152 1153 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 1154 addr &= MWBAR_GRANULE_MASK; 1155 addr += NIC_MEM_WINDOW_OFFSET; 1156 1157 (void) ddi_device_zero(bgep->io_handle, PIO_ADDR(bgep, addr), 1158 nbytes, 1, DDI_DATA_SZ08_ACC); 1159 BGE_PCICHK(bgep); 1160 } 1161 1162 /* 1163 * MII (PHY) register get/set access routines 1164 * 1165 * These use the chip's MII auto-access method, controlled by the 1166 * MII Communication register at 0x044c, so the CPU doesn't have 1167 * to fiddle with the individual bits. 1168 */ 1169 1170 #undef BGE_DBG 1171 #define BGE_DBG BGE_DBG_MII /* debug flag for this code */ 1172 1173 static uint16_t bge_mii_access(bge_t *bgep, bge_regno_t regno, 1174 uint16_t data, uint32_t cmd); 1175 #pragma no_inline(bge_mii_access) 1176 1177 static uint16_t 1178 bge_mii_access(bge_t *bgep, bge_regno_t regno, uint16_t data, uint32_t cmd) 1179 { 1180 uint32_t timeout; 1181 uint32_t regval1; 1182 uint32_t regval2; 1183 1184 BGE_TRACE(("bge_mii_access($%p, 0x%lx, 0x%x, 0x%x)", 1185 (void *)bgep, regno, data, cmd)); 1186 1187 ASSERT(mutex_owned(bgep->genlock)); 1188 1189 /* 1190 * Assemble the command ... 1191 */ 1192 cmd |= data << MI_COMMS_DATA_SHIFT; 1193 cmd |= regno << MI_COMMS_REGISTER_SHIFT; 1194 cmd |= bgep->phy_mii_addr << MI_COMMS_ADDRESS_SHIFT; 1195 cmd |= MI_COMMS_START; 1196 1197 /* 1198 * Wait for any command already in progress ... 1199 * 1200 * Note: this *shouldn't* ever find that there is a command 1201 * in progress, because we already hold the <genlock> mutex. 1202 * Nonetheless, we have sometimes seen the MI_COMMS_START 1203 * bit set here -- it seems that the chip can initiate MII 1204 * accesses internally, even with polling OFF. 1205 */ 1206 regval1 = regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1207 for (timeout = 100; ; ) { 1208 if ((regval2 & MI_COMMS_START) == 0) { 1209 bge_reg_put32(bgep, MI_COMMS_REG, cmd); 1210 break; 1211 } 1212 if (--timeout == 0) 1213 break; 1214 drv_usecwait(10); 1215 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1216 } 1217 1218 if (timeout == 0) 1219 return ((uint16_t)~0u); 1220 1221 if (timeout != 100) 1222 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1223 "MI_COMMS_START set for %d us; 0x%x->0x%x", 1224 cmd, 10*(100-timeout), regval1, regval2)); 1225 1226 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1227 for (timeout = 1000; ; ) { 1228 if ((regval1 & MI_COMMS_START) == 0) 1229 break; 1230 if (--timeout == 0) 1231 break; 1232 drv_usecwait(10); 1233 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1234 } 1235 1236 /* 1237 * Drop out early if the READ FAILED bit is set -- this chip 1238 * could be a 5703/4S, with a SerDes instead of a PHY! 1239 */ 1240 if (regval2 & MI_COMMS_READ_FAILED) 1241 return ((uint16_t)~0u); 1242 1243 if (timeout == 0) 1244 return ((uint16_t)~0u); 1245 1246 /* 1247 * The PRM says to wait 5us after seeing the START bit clear 1248 * and then re-read the register to get the final value of the 1249 * data field, in order to avoid a race condition where the 1250 * START bit is clear but the data field isn't yet valid. 1251 * 1252 * Note: we don't actually seem to be encounter this race; 1253 * except when the START bit is seen set again (see below), 1254 * the data field doesn't change during this 5us interval. 1255 */ 1256 drv_usecwait(5); 1257 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1258 1259 /* 1260 * Unfortunately, when following the PRMs instructions above, 1261 * we have occasionally seen the START bit set again(!) in the 1262 * value read after the 5us delay. This seems to be due to the 1263 * chip autonomously starting another MII access internally. 1264 * In such cases, the command/data/etc fields relate to the 1265 * internal command, rather than the one that we thought had 1266 * just finished. So in this case, we fall back to returning 1267 * the data from the original read that showed START clear. 1268 */ 1269 if (regval2 & MI_COMMS_START) { 1270 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1271 "MI_COMMS_START set after transaction; 0x%x->0x%x", 1272 cmd, regval1, regval2)); 1273 regval2 = regval1; 1274 } 1275 1276 if (regval2 & MI_COMMS_START) 1277 return ((uint16_t)~0u); 1278 1279 if (regval2 & MI_COMMS_READ_FAILED) 1280 return ((uint16_t)~0u); 1281 1282 return ((regval2 & MI_COMMS_DATA_MASK) >> MI_COMMS_DATA_SHIFT); 1283 } 1284 1285 uint16_t bge_mii_get16(bge_t *bgep, bge_regno_t regno); 1286 #pragma no_inline(bge_mii_get16) 1287 1288 uint16_t 1289 bge_mii_get16(bge_t *bgep, bge_regno_t regno) 1290 { 1291 BGE_TRACE(("bge_mii_get16($%p, 0x%lx)", 1292 (void *)bgep, regno)); 1293 1294 ASSERT(mutex_owned(bgep->genlock)); 1295 1296 if (DEVICE_5906_SERIES_CHIPSETS(bgep) && ((regno == MII_AUX_CONTROL) || 1297 (regno == MII_MSCONTROL))) 1298 return (0); 1299 1300 return (bge_mii_access(bgep, regno, 0, MI_COMMS_COMMAND_READ)); 1301 } 1302 1303 void bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data); 1304 #pragma no_inline(bge_mii_put16) 1305 1306 void 1307 bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data) 1308 { 1309 BGE_TRACE(("bge_mii_put16($%p, 0x%lx, 0x%x)", 1310 (void *)bgep, regno, data)); 1311 1312 ASSERT(mutex_owned(bgep->genlock)); 1313 1314 if (DEVICE_5906_SERIES_CHIPSETS(bgep) && ((regno == MII_AUX_CONTROL) || 1315 (regno == MII_MSCONTROL))) 1316 return; 1317 1318 (void) bge_mii_access(bgep, regno, data, MI_COMMS_COMMAND_WRITE); 1319 } 1320 1321 uint16_t 1322 bge_phydsp_read(bge_t *bgep, bge_regno_t regno) 1323 { 1324 BGE_TRACE(("bge_phydsp_read($%p, 0x%lx)", 1325 (void *)bgep, regno)); 1326 1327 ASSERT(mutex_owned(bgep->genlock)); 1328 1329 bge_mii_put16(bgep, MII_DSP_ADDRESS, regno); 1330 return bge_mii_get16(bgep, MII_DSP_RW_PORT); 1331 } 1332 1333 #pragma no_inline(bge_phydsp_write) 1334 1335 void 1336 bge_phydsp_write(bge_t *bgep, bge_regno_t regno, uint16_t data) 1337 { 1338 BGE_TRACE(("bge_phydsp_write($%p, 0x%lx, 0x%x)", 1339 (void *)bgep, regno, data)); 1340 1341 ASSERT(mutex_owned(bgep->genlock)); 1342 1343 bge_mii_put16(bgep, MII_DSP_ADDRESS, regno); 1344 bge_mii_put16(bgep, MII_DSP_RW_PORT, data); 1345 } 1346 1347 #undef BGE_DBG 1348 #define BGE_DBG BGE_DBG_SEEPROM /* debug flag for this code */ 1349 1350 #if BGE_SEE_IO32 || BGE_FLASH_IO32 1351 1352 /* 1353 * Basic SEEPROM get/set access routine 1354 * 1355 * This uses the chip's SEEPROM auto-access method, controlled by the 1356 * Serial EEPROM Address/Data Registers at 0x6838/683c, so the CPU 1357 * doesn't have to fiddle with the individual bits. 1358 * 1359 * The caller should hold <genlock> and *also* have already acquired 1360 * the right to access the SEEPROM, via bge_nvmem_acquire() above. 1361 * 1362 * Return value: 1363 * 0 on success, 1364 * ENODATA on access timeout (maybe retryable: device may just be busy) 1365 * EPROTO on other h/w or s/w errors. 1366 * 1367 * <*dp> is an input to a SEEPROM_ACCESS_WRITE operation, or an output 1368 * from a (successful) SEEPROM_ACCESS_READ. 1369 */ 1370 static int bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1371 uint32_t *dp); 1372 #pragma no_inline(bge_seeprom_access) 1373 1374 static int 1375 bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1376 { 1377 uint32_t tries; 1378 uint32_t regval; 1379 1380 ASSERT(mutex_owned(bgep->genlock)); 1381 1382 /* 1383 * On the newer chips that support both SEEPROM & Flash, we need 1384 * to specifically enable SEEPROM access (Flash is the default). 1385 * On older chips, we don't; SEEPROM is the only NVtype supported, 1386 * and the NVM control registers don't exist ... 1387 */ 1388 switch (bgep->chipid.nvtype) { 1389 case BGE_NVTYPE_NONE: 1390 case BGE_NVTYPE_UNKNOWN: 1391 _NOTE(NOTREACHED) 1392 case BGE_NVTYPE_SEEPROM: 1393 break; 1394 1395 case BGE_NVTYPE_LEGACY_SEEPROM: 1396 case BGE_NVTYPE_UNBUFFERED_FLASH: 1397 case BGE_NVTYPE_BUFFERED_FLASH: 1398 default: 1399 bge_reg_set32(bgep, NVM_CONFIG1_REG, 1400 NVM_CFG1_LEGACY_SEEPROM_MODE); 1401 break; 1402 } 1403 1404 /* 1405 * Check there's no command in progress. 1406 * 1407 * Note: this *shouldn't* ever find that there is a command 1408 * in progress, because we already hold the <genlock> mutex. 1409 * Also, to ensure we don't have a conflict with the chip's 1410 * internal firmware or a process accessing the same (shared) 1411 * SEEPROM through the other port of a 5704, we've already 1412 * been through the "software arbitration" protocol. 1413 * So this is just a final consistency check: we shouldn't 1414 * see EITHER the START bit (command started but not complete) 1415 * OR the COMPLETE bit (command completed but not cleared). 1416 */ 1417 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1418 if (regval & SEEPROM_ACCESS_START) 1419 return (EPROTO); 1420 if (regval & SEEPROM_ACCESS_COMPLETE) 1421 return (EPROTO); 1422 1423 /* 1424 * Assemble the command ... 1425 */ 1426 cmd |= addr & SEEPROM_ACCESS_ADDRESS_MASK; 1427 addr >>= SEEPROM_ACCESS_ADDRESS_SIZE; 1428 addr <<= SEEPROM_ACCESS_DEVID_SHIFT; 1429 cmd |= addr & SEEPROM_ACCESS_DEVID_MASK; 1430 cmd |= SEEPROM_ACCESS_START; 1431 cmd |= SEEPROM_ACCESS_COMPLETE; 1432 cmd |= regval & SEEPROM_ACCESS_HALFCLOCK_MASK; 1433 1434 bge_reg_put32(bgep, SERIAL_EEPROM_DATA_REG, *dp); 1435 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, cmd); 1436 1437 /* 1438 * By observation, a successful access takes ~20us on a 5703/4, 1439 * but apparently much longer (up to 1000us) on the obsolescent 1440 * BCM5700/BCM5701. We want to be sure we don't get any false 1441 * timeouts here; but OTOH, we don't want a bogus access to lock 1442 * out interrupts for longer than necessary. So we'll allow up 1443 * to 1000us ... 1444 */ 1445 for (tries = 0; tries < 1000; ++tries) { 1446 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1447 if (regval & SEEPROM_ACCESS_COMPLETE) 1448 break; 1449 drv_usecwait(1); 1450 } 1451 1452 if (regval & SEEPROM_ACCESS_COMPLETE) { 1453 /* 1454 * All OK; read the SEEPROM data register, then write back 1455 * the value read from the address register in order to 1456 * clear the <complete> bit and leave the SEEPROM access 1457 * state machine idle, ready for the next access ... 1458 */ 1459 BGE_DEBUG(("bge_seeprom_access: complete after %d us", tries)); 1460 *dp = bge_reg_get32(bgep, SERIAL_EEPROM_DATA_REG); 1461 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, regval); 1462 return (0); 1463 } 1464 1465 /* 1466 * Hmm ... what happened here? 1467 * 1468 * Most likely, the user addressed a non-existent SEEPROM. Or 1469 * maybe the SEEPROM was busy internally (e.g. processing a write) 1470 * and didn't respond to being addressed. Either way, it's left 1471 * the SEEPROM access state machine wedged. So we'll reset it 1472 * before we leave, so it's ready for next time ... 1473 */ 1474 BGE_DEBUG(("bge_seeprom_access: timed out after %d us", tries)); 1475 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 1476 return (ENODATA); 1477 } 1478 1479 /* 1480 * Basic Flash get/set access routine 1481 * 1482 * These use the chip's Flash auto-access method, controlled by the 1483 * Flash Access Registers at 0x7000-701c, so the CPU doesn't have to 1484 * fiddle with the individual bits. 1485 * 1486 * The caller should hold <genlock> and *also* have already acquired 1487 * the right to access the Flash, via bge_nvmem_acquire() above. 1488 * 1489 * Return value: 1490 * 0 on success, 1491 * ENODATA on access timeout (maybe retryable: device may just be busy) 1492 * ENODEV if the NVmem device is missing or otherwise unusable 1493 * 1494 * <*dp> is an input to a NVM_FLASH_CMD_WR operation, or an output 1495 * from a (successful) NVM_FLASH_CMD_RD. 1496 */ 1497 static int bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1498 uint32_t *dp); 1499 #pragma no_inline(bge_flash_access) 1500 1501 static int 1502 bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1503 { 1504 uint32_t tries; 1505 uint32_t regval; 1506 1507 ASSERT(mutex_owned(bgep->genlock)); 1508 1509 /* 1510 * On the newer chips that support both SEEPROM & Flash, we need 1511 * to specifically disable SEEPROM access while accessing Flash. 1512 * The older chips don't support Flash, and the NVM registers don't 1513 * exist, so we shouldn't be here at all! 1514 */ 1515 switch (bgep->chipid.nvtype) { 1516 case BGE_NVTYPE_NONE: 1517 case BGE_NVTYPE_UNKNOWN: 1518 _NOTE(NOTREACHED) 1519 case BGE_NVTYPE_SEEPROM: 1520 return (ENODEV); 1521 1522 case BGE_NVTYPE_LEGACY_SEEPROM: 1523 case BGE_NVTYPE_UNBUFFERED_FLASH: 1524 case BGE_NVTYPE_BUFFERED_FLASH: 1525 default: 1526 bge_reg_clr32(bgep, NVM_CONFIG1_REG, 1527 NVM_CFG1_LEGACY_SEEPROM_MODE); 1528 break; 1529 } 1530 1531 /* 1532 * Assemble the command ... 1533 */ 1534 addr &= NVM_FLASH_ADDR_MASK; 1535 cmd |= NVM_FLASH_CMD_DOIT; 1536 cmd |= NVM_FLASH_CMD_FIRST; 1537 cmd |= NVM_FLASH_CMD_LAST; 1538 cmd |= NVM_FLASH_CMD_DONE; 1539 1540 bge_reg_put32(bgep, NVM_FLASH_WRITE_REG, *dp); 1541 bge_reg_put32(bgep, NVM_FLASH_ADDR_REG, addr); 1542 bge_reg_put32(bgep, NVM_FLASH_CMD_REG, cmd); 1543 1544 /* 1545 * Allow up to 1000ms ... 1546 */ 1547 for (tries = 0; tries < 1000; ++tries) { 1548 regval = bge_reg_get32(bgep, NVM_FLASH_CMD_REG); 1549 if (regval & NVM_FLASH_CMD_DONE) 1550 break; 1551 drv_usecwait(1); 1552 } 1553 1554 if (regval & NVM_FLASH_CMD_DONE) { 1555 /* 1556 * All OK; read the data from the Flash read register 1557 */ 1558 BGE_DEBUG(("bge_flash_access: complete after %d us", tries)); 1559 *dp = bge_reg_get32(bgep, NVM_FLASH_READ_REG); 1560 return (0); 1561 } 1562 1563 /* 1564 * Hmm ... what happened here? 1565 * 1566 * Most likely, the user addressed a non-existent Flash. Or 1567 * maybe the Flash was busy internally (e.g. processing a write) 1568 * and didn't respond to being addressed. Either way, there's 1569 * nothing we can here ... 1570 */ 1571 BGE_DEBUG(("bge_flash_access: timed out after %d us", tries)); 1572 return (ENODATA); 1573 } 1574 1575 /* 1576 * The next two functions regulate access to the NVram (if fitted). 1577 * 1578 * On a 5704 (dual core) chip, there's only one SEEPROM and one Flash 1579 * (SPI) interface, but they can be accessed through either port. These 1580 * are managed by different instance of this driver and have no software 1581 * state in common. 1582 * 1583 * In addition (and even on a single core chip) the chip's internal 1584 * firmware can access the SEEPROM/Flash, most notably after a RESET 1585 * when it may download code to run internally. 1586 * 1587 * So we need to arbitrate between these various software agents. For 1588 * this purpose, the chip provides the Software Arbitration Register, 1589 * which implements hardware(!) arbitration. 1590 * 1591 * This functionality didn't exist on older (5700/5701) chips, so there's 1592 * nothing we can do by way of arbitration on those; also, if there's no 1593 * SEEPROM/Flash fitted (or we couldn't determine what type), there's also 1594 * nothing to do. 1595 * 1596 * The internal firmware appears to use Request 0, which is the highest 1597 * priority. So we'd like to use Request 2, leaving one higher and one 1598 * lower for any future developments ... but apparently this doesn't 1599 * always work. So for now, the code uses Request 1 ;-( 1600 */ 1601 1602 #define NVM_READ_REQ NVM_READ_REQ1 1603 #define NVM_RESET_REQ NVM_RESET_REQ1 1604 #define NVM_SET_REQ NVM_SET_REQ1 1605 1606 static void bge_nvmem_relinquish(bge_t *bgep); 1607 #pragma no_inline(bge_nvmem_relinquish) 1608 1609 static void 1610 bge_nvmem_relinquish(bge_t *bgep) 1611 { 1612 ASSERT(mutex_owned(bgep->genlock)); 1613 1614 switch (bgep->chipid.nvtype) { 1615 case BGE_NVTYPE_NONE: 1616 case BGE_NVTYPE_UNKNOWN: 1617 _NOTE(NOTREACHED) 1618 return; 1619 1620 case BGE_NVTYPE_SEEPROM: 1621 /* 1622 * No arbitration performed, no release needed 1623 */ 1624 return; 1625 1626 case BGE_NVTYPE_LEGACY_SEEPROM: 1627 case BGE_NVTYPE_UNBUFFERED_FLASH: 1628 case BGE_NVTYPE_BUFFERED_FLASH: 1629 default: 1630 break; 1631 } 1632 1633 /* 1634 * Our own request should be present (whether or not granted) ... 1635 */ 1636 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1637 1638 /* 1639 * ... this will make it go away. 1640 */ 1641 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_RESET_REQ); 1642 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1643 } 1644 1645 /* 1646 * Arbitrate for access to the NVmem, if necessary 1647 * 1648 * Return value: 1649 * 0 on success 1650 * EAGAIN if the device is in use (retryable) 1651 * ENODEV if the NVmem device is missing or otherwise unusable 1652 */ 1653 static int bge_nvmem_acquire(bge_t *bgep); 1654 #pragma no_inline(bge_nvmem_acquire) 1655 1656 static int 1657 bge_nvmem_acquire(bge_t *bgep) 1658 { 1659 uint32_t regval; 1660 uint32_t tries; 1661 1662 ASSERT(mutex_owned(bgep->genlock)); 1663 1664 switch (bgep->chipid.nvtype) { 1665 case BGE_NVTYPE_NONE: 1666 case BGE_NVTYPE_UNKNOWN: 1667 /* 1668 * Access denied: no (recognisable) device fitted 1669 */ 1670 return (ENODEV); 1671 1672 case BGE_NVTYPE_SEEPROM: 1673 /* 1674 * Access granted: no arbitration needed (or possible) 1675 */ 1676 return (0); 1677 1678 case BGE_NVTYPE_LEGACY_SEEPROM: 1679 case BGE_NVTYPE_UNBUFFERED_FLASH: 1680 case BGE_NVTYPE_BUFFERED_FLASH: 1681 default: 1682 /* 1683 * Access conditional: conduct arbitration protocol 1684 */ 1685 break; 1686 } 1687 1688 /* 1689 * We're holding the per-port mutex <genlock>, so no-one other 1690 * thread can be attempting to access the NVmem through *this* 1691 * port. But it could be in use by the *other* port (of a 5704), 1692 * or by the chip's internal firmware, so we have to go through 1693 * the full (hardware) arbitration protocol ... 1694 * 1695 * Note that *because* we're holding <genlock>, the interrupt handler 1696 * won't be able to progress. So we're only willing to spin for a 1697 * fairly short time. Specifically: 1698 * 1699 * We *must* wait long enough for the hardware to resolve all 1700 * requests and determine the winner. Fortunately, this is 1701 * "almost instantaneous", even as observed by GHz CPUs. 1702 * 1703 * A successful access by another Solaris thread (via either 1704 * port) typically takes ~20us. So waiting a bit longer than 1705 * that will give a good chance of success, if the other user 1706 * *is* another thread on the other port. 1707 * 1708 * However, the internal firmware can hold on to the NVmem 1709 * for *much* longer: at least 10 milliseconds just after a 1710 * RESET, and maybe even longer if the NVmem actually contains 1711 * code to download and run on the internal CPUs. 1712 * 1713 * So, we'll allow 50us; if that's not enough then it's up to the 1714 * caller to retry later (hence the choice of return code EAGAIN). 1715 */ 1716 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1717 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_SET_REQ); 1718 1719 for (tries = 0; tries < 50; ++tries) { 1720 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1721 if (regval & NVM_WON_REQ1) 1722 break; 1723 drv_usecwait(1); 1724 } 1725 1726 if (regval & NVM_WON_REQ1) { 1727 BGE_DEBUG(("bge_nvmem_acquire: won after %d us", tries)); 1728 return (0); 1729 } 1730 1731 /* 1732 * Somebody else must be accessing the NVmem, so abandon our 1733 * attempt take control of it. The caller can try again later ... 1734 */ 1735 BGE_DEBUG(("bge_nvmem_acquire: lost after %d us", tries)); 1736 bge_nvmem_relinquish(bgep); 1737 return (EAGAIN); 1738 } 1739 1740 /* 1741 * This code assumes that the GPIO1 bit has been wired up to the NVmem 1742 * write protect line in such a way that the NVmem is protected when 1743 * GPIO1 is an input, or is an output but driven high. Thus, to make the 1744 * NVmem writable we have to change GPIO1 to an output AND drive it low. 1745 * 1746 * Note: there's only one set of GPIO pins on a 5704, even though they 1747 * can be accessed through either port. So the chip has to resolve what 1748 * happens if the two ports program a single pin differently ... the rule 1749 * it uses is that if the ports disagree about the *direction* of a pin, 1750 * "output" wins over "input", but if they disagree about its *value* as 1751 * an output, then the pin is TRISTATED instead! In such a case, no-one 1752 * wins, and the external signal does whatever the external circuitry 1753 * defines as the default -- which we've assumed is the PROTECTED state. 1754 * So, we always change GPIO1 back to being an *input* whenever we're not 1755 * specifically using it to unprotect the NVmem. This allows either port 1756 * to update the NVmem, although obviously only one at a time! 1757 * 1758 * The caller should hold <genlock> and *also* have already acquired the 1759 * right to access the NVmem, via bge_nvmem_acquire() above. 1760 */ 1761 static void bge_nvmem_protect(bge_t *bgep, boolean_t protect); 1762 #pragma inline(bge_nvmem_protect) 1763 1764 static void 1765 bge_nvmem_protect(bge_t *bgep, boolean_t protect) 1766 { 1767 uint32_t regval; 1768 1769 ASSERT(mutex_owned(bgep->genlock)); 1770 1771 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 1772 if (protect) { 1773 regval |= MLCR_MISC_PINS_OUTPUT_1; 1774 regval &= ~MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1775 } else { 1776 regval &= ~MLCR_MISC_PINS_OUTPUT_1; 1777 regval |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1778 } 1779 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, regval); 1780 } 1781 1782 /* 1783 * Now put it all together ... 1784 * 1785 * Try to acquire control of the NVmem; if successful, then: 1786 * unprotect it (if we want to write to it) 1787 * perform the requested access 1788 * reprotect it (after a write) 1789 * relinquish control 1790 * 1791 * Return value: 1792 * 0 on success, 1793 * EAGAIN if the device is in use (retryable) 1794 * ENODATA on access timeout (maybe retryable: device may just be busy) 1795 * ENODEV if the NVmem device is missing or otherwise unusable 1796 * EPROTO on other h/w or s/w errors. 1797 */ 1798 static int 1799 bge_nvmem_rw32(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1800 { 1801 int err; 1802 1803 if ((err = bge_nvmem_acquire(bgep)) == 0) { 1804 switch (cmd) { 1805 case BGE_SEE_READ: 1806 err = bge_seeprom_access(bgep, 1807 SEEPROM_ACCESS_READ, addr, dp); 1808 break; 1809 1810 case BGE_SEE_WRITE: 1811 bge_nvmem_protect(bgep, B_FALSE); 1812 err = bge_seeprom_access(bgep, 1813 SEEPROM_ACCESS_WRITE, addr, dp); 1814 bge_nvmem_protect(bgep, B_TRUE); 1815 break; 1816 1817 case BGE_FLASH_READ: 1818 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1819 DEVICE_5723_SERIES_CHIPSETS(bgep) || 1820 DEVICE_5717_SERIES_CHIPSETS(bgep) || 1821 DEVICE_5725_SERIES_CHIPSETS(bgep) || 1822 DEVICE_5714_SERIES_CHIPSETS(bgep) || 1823 DEVICE_57765_SERIES_CHIPSETS(bgep)) { 1824 bge_reg_set32(bgep, NVM_ACCESS_REG, 1825 NVM_ACCESS_ENABLE); 1826 } 1827 err = bge_flash_access(bgep, 1828 NVM_FLASH_CMD_RD, addr, dp); 1829 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1830 DEVICE_5723_SERIES_CHIPSETS(bgep) || 1831 DEVICE_5717_SERIES_CHIPSETS(bgep) || 1832 DEVICE_5725_SERIES_CHIPSETS(bgep) || 1833 DEVICE_5714_SERIES_CHIPSETS(bgep) || 1834 DEVICE_57765_SERIES_CHIPSETS(bgep)) { 1835 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1836 NVM_ACCESS_ENABLE); 1837 } 1838 break; 1839 1840 case BGE_FLASH_WRITE: 1841 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1842 DEVICE_5723_SERIES_CHIPSETS(bgep) || 1843 DEVICE_5717_SERIES_CHIPSETS(bgep) || 1844 DEVICE_5725_SERIES_CHIPSETS(bgep) || 1845 DEVICE_5714_SERIES_CHIPSETS(bgep) || 1846 DEVICE_57765_SERIES_CHIPSETS(bgep)) { 1847 bge_reg_set32(bgep, NVM_ACCESS_REG, 1848 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1849 } 1850 bge_nvmem_protect(bgep, B_FALSE); 1851 err = bge_flash_access(bgep, 1852 NVM_FLASH_CMD_WR, addr, dp); 1853 bge_nvmem_protect(bgep, B_TRUE); 1854 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1855 DEVICE_5723_SERIES_CHIPSETS(bgep) || 1856 DEVICE_5717_SERIES_CHIPSETS(bgep) || 1857 DEVICE_5725_SERIES_CHIPSETS(bgep) || 1858 DEVICE_5714_SERIES_CHIPSETS(bgep) || 1859 DEVICE_57765_SERIES_CHIPSETS(bgep)) { 1860 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1861 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1862 } 1863 1864 break; 1865 1866 default: 1867 _NOTE(NOTREACHED) 1868 break; 1869 } 1870 bge_nvmem_relinquish(bgep); 1871 } 1872 1873 BGE_DEBUG(("bge_nvmem_rw32: err %d", err)); 1874 return (err); 1875 } 1876 1877 static uint32_t 1878 bge_nvmem_access_cmd(bge_t *bgep, boolean_t read) 1879 { 1880 switch (bgep->chipid.nvtype) { 1881 case BGE_NVTYPE_NONE: 1882 case BGE_NVTYPE_UNKNOWN: 1883 default: 1884 return 0; 1885 1886 case BGE_NVTYPE_SEEPROM: 1887 case BGE_NVTYPE_LEGACY_SEEPROM: 1888 return (read ? BGE_SEE_READ : BGE_SEE_WRITE); 1889 1890 case BGE_NVTYPE_UNBUFFERED_FLASH: 1891 case BGE_NVTYPE_BUFFERED_FLASH: 1892 return (read ? BGE_FLASH_READ : BGE_FLASH_WRITE); 1893 } 1894 } 1895 1896 1897 int 1898 bge_nvmem_read32(bge_t *bgep, bge_regno_t addr, uint32_t *dp) 1899 { 1900 return (bge_nvmem_rw32(bgep, bge_nvmem_access_cmd(bgep, B_TRUE), 1901 addr, dp)); 1902 } 1903 1904 1905 int 1906 bge_nvmem_write32(bge_t *bgep, bge_regno_t addr, uint32_t *dp) 1907 { 1908 return (bge_nvmem_rw32(bgep, bge_nvmem_access_cmd(bgep, B_FALSE), 1909 addr, dp)); 1910 } 1911 1912 1913 /* 1914 * Attempt to get a MAC address from the SEEPROM or Flash, if any 1915 */ 1916 static uint64_t bge_get_nvmac(bge_t *bgep); 1917 #pragma no_inline(bge_get_nvmac) 1918 1919 static uint64_t 1920 bge_get_nvmac(bge_t *bgep) 1921 { 1922 uint32_t mac_high; 1923 uint32_t mac_low; 1924 uint32_t addr; 1925 uint32_t cmd; 1926 uint64_t mac; 1927 1928 BGE_TRACE(("bge_get_nvmac($%p)", 1929 (void *)bgep)); 1930 1931 switch (bgep->chipid.nvtype) { 1932 case BGE_NVTYPE_NONE: 1933 case BGE_NVTYPE_UNKNOWN: 1934 default: 1935 return (0ULL); 1936 1937 case BGE_NVTYPE_SEEPROM: 1938 case BGE_NVTYPE_LEGACY_SEEPROM: 1939 cmd = BGE_SEE_READ; 1940 break; 1941 1942 case BGE_NVTYPE_UNBUFFERED_FLASH: 1943 case BGE_NVTYPE_BUFFERED_FLASH: 1944 cmd = BGE_FLASH_READ; 1945 break; 1946 } 1947 1948 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) 1949 addr = NVMEM_DATA_MAC_ADDRESS_5906; 1950 else 1951 addr = NVMEM_DATA_MAC_ADDRESS; 1952 1953 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_high)) 1954 return (0ULL); 1955 addr += 4; 1956 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_low)) 1957 return (0ULL); 1958 1959 /* 1960 * The Broadcom chip is natively BIG-endian, so that's how the 1961 * MAC address is represented in NVmem. We may need to swap it 1962 * around on a little-endian host ... 1963 */ 1964 #ifdef _BIG_ENDIAN 1965 mac = mac_high; 1966 mac = mac << 32; 1967 mac |= mac_low; 1968 #else 1969 mac = BGE_BSWAP_32(mac_high); 1970 mac = mac << 32; 1971 mac |= BGE_BSWAP_32(mac_low); 1972 #endif /* _BIG_ENDIAN */ 1973 1974 return (mac); 1975 } 1976 1977 #else /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1978 1979 /* 1980 * Dummy version for when we're not supporting NVmem access 1981 */ 1982 static uint64_t bge_get_nvmac(bge_t *bgep); 1983 #pragma inline(bge_get_nvmac) 1984 1985 static uint64_t 1986 bge_get_nvmac(bge_t *bgep) 1987 { 1988 _NOTE(ARGUNUSED(bgep)) 1989 return (0ULL); 1990 } 1991 1992 #endif /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1993 1994 /* 1995 * Determine the type of NVmem that is (or may be) attached to this chip, 1996 */ 1997 static enum bge_nvmem_type bge_nvmem_id(bge_t *bgep); 1998 #pragma no_inline(bge_nvmem_id) 1999 2000 static enum bge_nvmem_type 2001 bge_nvmem_id(bge_t *bgep) 2002 { 2003 enum bge_nvmem_type nvtype; 2004 uint32_t config1; 2005 2006 BGE_TRACE(("bge_nvmem_id($%p)", 2007 (void *)bgep)); 2008 2009 switch (bgep->chipid.device) { 2010 default: 2011 /* 2012 * We shouldn't get here; it means we don't recognise 2013 * the chip, which means we don't know how to determine 2014 * what sort of NVmem (if any) it has. So we'll say 2015 * NONE, to disable the NVmem access code ... 2016 */ 2017 nvtype = BGE_NVTYPE_NONE; 2018 break; 2019 2020 case DEVICE_ID_5700: 2021 case DEVICE_ID_5700x: 2022 case DEVICE_ID_5701: 2023 /* 2024 * These devices support *only* SEEPROMs 2025 */ 2026 nvtype = BGE_NVTYPE_SEEPROM; 2027 break; 2028 2029 case DEVICE_ID_5702: 2030 case DEVICE_ID_5702fe: 2031 case DEVICE_ID_5703C: 2032 case DEVICE_ID_5703S: 2033 case DEVICE_ID_5704C: 2034 case DEVICE_ID_5704S: 2035 case DEVICE_ID_5704: 2036 case DEVICE_ID_5705M: 2037 case DEVICE_ID_5705C: 2038 case DEVICE_ID_5705_2: 2039 case DEVICE_ID_5717: 2040 case DEVICE_ID_5718: 2041 case DEVICE_ID_5719: 2042 case DEVICE_ID_5720: 2043 case DEVICE_ID_5724: 2044 case DEVICE_ID_5725: 2045 case DEVICE_ID_5727: 2046 case DEVICE_ID_57780: 2047 case DEVICE_ID_5780: 2048 case DEVICE_ID_5782: 2049 case DEVICE_ID_5785: 2050 case DEVICE_ID_5787: 2051 case DEVICE_ID_5787M: 2052 case DEVICE_ID_5788: 2053 case DEVICE_ID_5789: 2054 case DEVICE_ID_5751: 2055 case DEVICE_ID_5751M: 2056 case DEVICE_ID_5752: 2057 case DEVICE_ID_5752M: 2058 case DEVICE_ID_5754: 2059 case DEVICE_ID_5755: 2060 case DEVICE_ID_5755M: 2061 case DEVICE_ID_5756M: 2062 case DEVICE_ID_5721: 2063 case DEVICE_ID_5722: 2064 case DEVICE_ID_5723: 2065 case DEVICE_ID_5761: 2066 case DEVICE_ID_5761E: 2067 case DEVICE_ID_5764: 2068 case DEVICE_ID_5714C: 2069 case DEVICE_ID_5714S: 2070 case DEVICE_ID_5715C: 2071 case DEVICE_ID_5715S: 2072 case DEVICE_ID_57761: 2073 case DEVICE_ID_57762: 2074 case DEVICE_ID_57765: 2075 case DEVICE_ID_57766: 2076 case DEVICE_ID_57781: 2077 case DEVICE_ID_57782: 2078 case DEVICE_ID_57785: 2079 case DEVICE_ID_57786: 2080 case DEVICE_ID_57791: 2081 case DEVICE_ID_57795: 2082 config1 = bge_reg_get32(bgep, NVM_CONFIG1_REG); 2083 if (config1 & NVM_CFG1_FLASH_MODE) 2084 if (config1 & NVM_CFG1_BUFFERED_MODE) 2085 nvtype = BGE_NVTYPE_BUFFERED_FLASH; 2086 else 2087 nvtype = BGE_NVTYPE_UNBUFFERED_FLASH; 2088 else 2089 nvtype = BGE_NVTYPE_LEGACY_SEEPROM; 2090 break; 2091 case DEVICE_ID_5906: 2092 case DEVICE_ID_5906M: 2093 nvtype = BGE_NVTYPE_BUFFERED_FLASH; 2094 break; 2095 } 2096 2097 return (nvtype); 2098 } 2099 2100 #undef BGE_DBG 2101 #define BGE_DBG BGE_DBG_APE /* debug flag for this code */ 2102 2103 uint32_t bge_ape_get32(bge_t *bgep, bge_regno_t regno); 2104 #pragma inline(bge_ape_get32) 2105 2106 uint32_t 2107 bge_ape_get32(bge_t *bgep, bge_regno_t regno) 2108 { 2109 BGE_TRACE(("bge_ape_get32($%p, 0x%lx)", 2110 (void *)bgep, regno)); 2111 2112 return (ddi_get32(bgep->ape_handle, APE_ADDR(bgep, regno))); 2113 } 2114 2115 void bge_ape_put32(bge_t *bgep, bge_regno_t regno, uint32_t data); 2116 #pragma inline(bge_ape_put32) 2117 2118 void 2119 bge_ape_put32(bge_t *bgep, bge_regno_t regno, uint32_t data) 2120 { 2121 BGE_TRACE(("bge_ape_put32($%p, 0x%lx, 0x%x)", 2122 (void *)bgep, regno, data)); 2123 2124 ddi_put32(bgep->ape_handle, APE_ADDR(bgep, regno), data); 2125 BGE_PCICHK(bgep); 2126 } 2127 2128 void 2129 bge_ape_lock_init(bge_t *bgep) 2130 { 2131 int i; 2132 uint32_t regbase; 2133 uint32_t bit; 2134 2135 BGE_TRACE(("bge_ape_lock_init($%p)", (void *)bgep)); 2136 2137 if (bgep->chipid.device == DEVICE_ID_5761) 2138 regbase = BGE_APE_LOCK_GRANT; 2139 else 2140 regbase = BGE_APE_PER_LOCK_GRANT; 2141 2142 /* Make sure the driver hasn't any stale locks. */ 2143 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) { 2144 switch (i) { 2145 case BGE_APE_LOCK_PHY0: 2146 case BGE_APE_LOCK_PHY1: 2147 case BGE_APE_LOCK_PHY2: 2148 case BGE_APE_LOCK_PHY3: 2149 bit = APE_LOCK_GRANT_DRIVER; 2150 break; 2151 default: 2152 if (!bgep->pci_func) 2153 bit = APE_LOCK_GRANT_DRIVER; 2154 else 2155 bit = 1 << bgep->pci_func; 2156 } 2157 bge_ape_put32(bgep, regbase + 4 * i, bit); 2158 } 2159 } 2160 2161 static int 2162 bge_ape_lock(bge_t *bgep, int locknum) 2163 { 2164 int i, off; 2165 int ret = 0; 2166 uint32_t status; 2167 uint32_t req; 2168 uint32_t gnt; 2169 uint32_t bit; 2170 2171 BGE_TRACE(("bge_ape_lock($%p, 0x%x)", (void *)bgep, locknum)); 2172 2173 if (!bgep->ape_enabled) 2174 return (0); 2175 2176 switch (locknum) { 2177 case BGE_APE_LOCK_GPIO: 2178 if (bgep->chipid.device == DEVICE_ID_5761) 2179 return (0); 2180 /* FALLTHROUGH */ 2181 case BGE_APE_LOCK_GRC: 2182 case BGE_APE_LOCK_MEM: 2183 if (!bgep->pci_func) 2184 bit = APE_LOCK_REQ_DRIVER; 2185 else 2186 bit = 1 << bgep->pci_func; 2187 break; 2188 case BGE_APE_LOCK_PHY0: 2189 case BGE_APE_LOCK_PHY1: 2190 case BGE_APE_LOCK_PHY2: 2191 case BGE_APE_LOCK_PHY3: 2192 bit = APE_LOCK_REQ_DRIVER; 2193 break; 2194 default: 2195 return (-1); 2196 } 2197 2198 if (bgep->chipid.device == DEVICE_ID_5761) { 2199 req = BGE_APE_LOCK_REQ; 2200 gnt = BGE_APE_LOCK_GRANT; 2201 } else { 2202 req = BGE_APE_PER_LOCK_REQ; 2203 gnt = BGE_APE_PER_LOCK_GRANT; 2204 } 2205 2206 off = 4 * locknum; 2207 2208 bge_ape_put32(bgep, req + off, bit); 2209 2210 /* Wait for up to 1 millisecond to acquire lock. */ 2211 for (i = 0; i < 100; i++) { 2212 status = bge_ape_get32(bgep, gnt + off); 2213 if (status == bit) 2214 break; 2215 drv_usecwait(10); 2216 } 2217 2218 if (status != bit) { 2219 /* Revoke the lock request. */ 2220 bge_ape_put32(bgep, gnt + off, bit); 2221 ret = -1; 2222 } 2223 2224 return (ret); 2225 } 2226 2227 static void 2228 bge_ape_unlock(bge_t *bgep, int locknum) 2229 { 2230 uint32_t gnt; 2231 uint32_t bit; 2232 2233 BGE_TRACE(("bge_ape_unlock($%p, 0x%x)", (void *)bgep, locknum)); 2234 2235 if (!bgep->ape_enabled) 2236 return; 2237 2238 switch (locknum) { 2239 case BGE_APE_LOCK_GPIO: 2240 if (bgep->chipid.device == DEVICE_ID_5761) 2241 return; 2242 /* FALLTHROUGH */ 2243 case BGE_APE_LOCK_GRC: 2244 case BGE_APE_LOCK_MEM: 2245 if (!bgep->pci_func) 2246 bit = APE_LOCK_GRANT_DRIVER; 2247 else 2248 bit = 1 << bgep->pci_func; 2249 break; 2250 case BGE_APE_LOCK_PHY0: 2251 case BGE_APE_LOCK_PHY1: 2252 case BGE_APE_LOCK_PHY2: 2253 case BGE_APE_LOCK_PHY3: 2254 bit = APE_LOCK_GRANT_DRIVER; 2255 break; 2256 default: 2257 return; 2258 } 2259 2260 if (bgep->chipid.device == DEVICE_ID_5761) 2261 gnt = BGE_APE_LOCK_GRANT; 2262 else 2263 gnt = BGE_APE_PER_LOCK_GRANT; 2264 2265 bge_ape_put32(bgep, gnt + 4 * locknum, bit); 2266 } 2267 2268 /* wait for pending event to finish, if successful returns with MEM locked */ 2269 static int 2270 bge_ape_event_lock(bge_t *bgep, uint32_t timeout_us) 2271 { 2272 uint32_t apedata; 2273 2274 BGE_TRACE(("bge_ape_event_lock($%p, %d)", (void *)bgep, timeout_us)); 2275 2276 ASSERT(timeout_us > 0); 2277 2278 while (timeout_us) { 2279 if (bge_ape_lock(bgep, BGE_APE_LOCK_MEM)) 2280 return (-1); 2281 2282 apedata = bge_ape_get32(bgep, BGE_APE_EVENT_STATUS); 2283 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) 2284 break; 2285 2286 bge_ape_unlock(bgep, BGE_APE_LOCK_MEM); 2287 2288 drv_usecwait(10); 2289 timeout_us -= (timeout_us > 10) ? 10 : timeout_us; 2290 } 2291 2292 return (timeout_us ? 0 : -1); 2293 } 2294 2295 /* wait for pending event to finish, returns non-zero if not finished */ 2296 static int 2297 bge_ape_wait_for_event(bge_t *bgep, uint32_t timeout_us) 2298 { 2299 uint32_t i; 2300 uint32_t apedata; 2301 2302 BGE_TRACE(("bge_ape_wait_for_event($%p, %d)", (void *)bgep, timeout_us)); 2303 2304 ASSERT(timeout_us > 0); 2305 2306 for (i = 0; i < timeout_us / 10; i++) { 2307 apedata = bge_ape_get32(bgep, BGE_APE_EVENT_STATUS); 2308 2309 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) 2310 break; 2311 2312 drv_usecwait(10); 2313 } 2314 2315 return (i == timeout_us / 10); 2316 } 2317 2318 int 2319 bge_ape_scratchpad_read(bge_t *bgep, uint32_t *data, uint32_t base_off, 2320 uint32_t lenToRead) 2321 { 2322 int err; 2323 uint32_t i; 2324 uint32_t bufoff; 2325 uint32_t msgoff; 2326 uint32_t maxlen; 2327 uint32_t apedata; 2328 2329 BGE_TRACE(("bge_ape_scratchpad_read($%p, %p, 0x%0x, %d)", 2330 (void *)bgep, (void*)data, base_off, lenToRead)); 2331 2332 if (!bgep->ape_has_ncsi) 2333 return (0); 2334 2335 apedata = bge_ape_get32(bgep, BGE_APE_SEG_SIG); 2336 if (apedata != APE_SEG_SIG_MAGIC) 2337 return (-1); 2338 2339 apedata = bge_ape_get32(bgep, BGE_APE_FW_STATUS); 2340 if (!(apedata & APE_FW_STATUS_READY)) 2341 return (-1); 2342 2343 bufoff = (bge_ape_get32(bgep, BGE_APE_SEG_MSG_BUF_OFF) + 2344 BGE_APE_SHMEM_BASE); 2345 msgoff = bufoff + 2 * sizeof(uint32_t); 2346 maxlen = bge_ape_get32(bgep, BGE_APE_SEG_MSG_BUF_LEN); 2347 2348 while (lenToRead) { 2349 uint32_t transferLen; 2350 2351 /* Cap xfer sizes to scratchpad limits. */ 2352 transferLen = (lenToRead > maxlen) ? maxlen : lenToRead; 2353 lenToRead -= transferLen; 2354 2355 apedata = bge_ape_get32(bgep, BGE_APE_FW_STATUS); 2356 if (!(apedata & APE_FW_STATUS_READY)) 2357 return (-1); 2358 2359 /* Wait for up to 1 millisecond for APE to service previous event. */ 2360 err = bge_ape_event_lock(bgep, 1000); 2361 if (err) 2362 return (err); 2363 2364 apedata = (APE_EVENT_STATUS_DRIVER_EVNT | 2365 APE_EVENT_STATUS_SCRTCHPD_READ | 2366 APE_EVENT_STATUS_EVENT_PENDING); 2367 bge_ape_put32(bgep, BGE_APE_EVENT_STATUS, apedata); 2368 2369 bge_ape_put32(bgep, bufoff, base_off); 2370 bge_ape_put32(bgep, bufoff + sizeof(uint32_t), transferLen); 2371 2372 bge_ape_unlock(bgep, BGE_APE_LOCK_MEM); 2373 bge_ape_put32(bgep, BGE_APE_EVENT, APE_EVENT_1); 2374 2375 base_off += transferLen; 2376 2377 if (bge_ape_wait_for_event(bgep, 30000)) 2378 return (-1); 2379 2380 for (i = 0; transferLen; i += 4, transferLen -= 4) { 2381 uint32_t val = bge_ape_get32(bgep, msgoff + i); 2382 memcpy(data, &val, sizeof(uint32_t)); 2383 data++; 2384 } 2385 } 2386 2387 return (0); 2388 } 2389 2390 int 2391 bge_ape_scratchpad_write(bge_t *bgep, uint32_t dstoff, uint32_t *data, 2392 uint32_t lenToWrite) 2393 { 2394 int err; 2395 uint32_t i; 2396 uint32_t bufoff; 2397 uint32_t msgoff; 2398 uint32_t maxlen; 2399 uint32_t apedata; 2400 2401 BGE_TRACE(("bge_ape_scratchpad_write($%p, %d, %p, %d)", 2402 (void *)bgep, dstoff, data, lenToWrite)); 2403 2404 if (!bgep->ape_has_ncsi) 2405 return (0); 2406 2407 apedata = bge_ape_get32(bgep, BGE_APE_SEG_SIG); 2408 if (apedata != APE_SEG_SIG_MAGIC) 2409 return (-1); 2410 2411 apedata = bge_ape_get32(bgep, BGE_APE_FW_STATUS); 2412 if (!(apedata & APE_FW_STATUS_READY)) 2413 return (-1); 2414 2415 bufoff = (bge_ape_get32(bgep, BGE_APE_SEG_MSG_BUF_OFF) + 2416 BGE_APE_SHMEM_BASE); 2417 msgoff = bufoff + 2 * sizeof(uint32_t); 2418 maxlen = bge_ape_get32(bgep, BGE_APE_SEG_MSG_BUF_LEN); 2419 2420 while (lenToWrite) { 2421 uint32_t transferLen; 2422 2423 /* Cap xfer sizes to scratchpad limits. */ 2424 transferLen = (lenToWrite > maxlen) ? maxlen : lenToWrite; 2425 lenToWrite -= transferLen; 2426 2427 /* Wait for up to 1 millisecond for 2428 * APE to service previous event. 2429 */ 2430 err = bge_ape_event_lock(bgep, 1000); 2431 if (err) 2432 return (err); 2433 2434 bge_ape_put32(bgep, bufoff, dstoff); 2435 bge_ape_put32(bgep, bufoff + sizeof(uint32_t), transferLen); 2436 apedata = msgoff; 2437 2438 dstoff += transferLen; 2439 2440 for (i = 0; transferLen; i += 4, transferLen -= 4) { 2441 bge_ape_put32(bgep, apedata, *data++); 2442 apedata += sizeof(uint32_t); 2443 } 2444 2445 apedata = (APE_EVENT_STATUS_DRIVER_EVNT | 2446 APE_EVENT_STATUS_SCRTCHPD_WRITE | 2447 APE_EVENT_STATUS_EVENT_PENDING); 2448 bge_ape_put32(bgep, BGE_APE_EVENT_STATUS, apedata); 2449 2450 bge_ape_unlock(bgep, BGE_APE_LOCK_MEM); 2451 bge_ape_put32(bgep, BGE_APE_EVENT, APE_EVENT_1); 2452 } 2453 2454 return (0); 2455 } 2456 2457 static int 2458 bge_ape_send_event(bge_t *bgep, uint32_t event) 2459 { 2460 int err; 2461 uint32_t apedata; 2462 2463 BGE_TRACE(("bge_ape_send_event($%p, %d)", (void *)bgep, event)); 2464 2465 apedata = bge_ape_get32(bgep, BGE_APE_SEG_SIG); 2466 if (apedata != APE_SEG_SIG_MAGIC) 2467 return (-1); 2468 2469 apedata = bge_ape_get32(bgep, BGE_APE_FW_STATUS); 2470 if (!(apedata & APE_FW_STATUS_READY)) 2471 return (-1); 2472 2473 /* Wait for up to 1 millisecond for APE to service previous event. */ 2474 err = bge_ape_event_lock(bgep, 1000); 2475 if (err) 2476 return (err); 2477 2478 bge_ape_put32(bgep, BGE_APE_EVENT_STATUS, 2479 event | APE_EVENT_STATUS_EVENT_PENDING); 2480 2481 bge_ape_unlock(bgep, BGE_APE_LOCK_MEM); 2482 bge_ape_put32(bgep, BGE_APE_EVENT, APE_EVENT_1); 2483 2484 return 0; 2485 } 2486 2487 static void 2488 bge_ape_driver_state_change(bge_t *bgep, int mode) 2489 { 2490 uint32_t event; 2491 uint32_t apedata; 2492 2493 BGE_TRACE(("bge_ape_driver_state_change($%p, %d)", 2494 (void *)bgep, mode)); 2495 2496 if (!bgep->ape_enabled) 2497 return; 2498 2499 switch (mode) { 2500 case BGE_INIT_RESET: 2501 bge_ape_put32(bgep, BGE_APE_HOST_SEG_SIG, 2502 APE_HOST_SEG_SIG_MAGIC); 2503 bge_ape_put32(bgep, BGE_APE_HOST_SEG_LEN, 2504 APE_HOST_SEG_LEN_MAGIC); 2505 apedata = bge_ape_get32(bgep, BGE_APE_HOST_INIT_COUNT); 2506 bge_ape_put32(bgep, BGE_APE_HOST_INIT_COUNT, ++apedata); 2507 bge_ape_put32(bgep, BGE_APE_HOST_DRIVER_ID, 2508 APE_HOST_DRIVER_ID_MAGIC(1, 0)); 2509 bge_ape_put32(bgep, BGE_APE_HOST_BEHAVIOR, 2510 APE_HOST_BEHAV_NO_PHYLOCK); 2511 bge_ape_put32(bgep, BGE_APE_HOST_DRVR_STATE, 2512 BGE_APE_HOST_DRVR_STATE_START); 2513 2514 event = APE_EVENT_STATUS_STATE_START; 2515 break; 2516 case BGE_SHUTDOWN_RESET: 2517 /* With the interface we are currently using, 2518 * APE does not track driver state. Wiping 2519 * out the HOST SEGMENT SIGNATURE forces 2520 * the APE to assume OS absent status. 2521 */ 2522 bge_ape_put32(bgep, BGE_APE_HOST_SEG_SIG, 0x0); 2523 2524 #if 0 2525 if (WOL supported) { 2526 bge_ape_put32(bgep, BGE_APE_HOST_WOL_SPEED, 2527 BGE_APE_HOST_WOL_SPEED_AUTO); 2528 apedata = BGE_APE_HOST_DRVR_STATE_WOL; 2529 } else 2530 #endif 2531 apedata = BGE_APE_HOST_DRVR_STATE_UNLOAD; 2532 2533 bge_ape_put32(bgep, BGE_APE_HOST_DRVR_STATE, apedata); 2534 2535 event = APE_EVENT_STATUS_STATE_UNLOAD; 2536 break; 2537 case BGE_SUSPEND_RESET: 2538 event = APE_EVENT_STATUS_STATE_SUSPEND; 2539 break; 2540 default: 2541 return; 2542 } 2543 2544 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE; 2545 2546 bge_ape_send_event(bgep, event); 2547 } 2548 2549 #undef BGE_DBG 2550 #define BGE_DBG BGE_DBG_CHIP /* debug flag for this code */ 2551 2552 static void 2553 bge_init_recv_rule(bge_t *bgep) 2554 { 2555 bge_recv_rule_t *rulep = bgep->recv_rules; 2556 uint32_t i; 2557 2558 /* 2559 * Initialize receive rule registers. 2560 * Note that rules may persist across each bge_m_start/stop() call. 2561 */ 2562 for (i = 0; i < RECV_RULES_NUM_MAX; i++, rulep++) { 2563 bge_reg_put32(bgep, RECV_RULE_MASK_REG(i), rulep->mask_value); 2564 bge_reg_put32(bgep, RECV_RULE_CONTROL_REG(i), rulep->control); 2565 } 2566 } 2567 2568 /* 2569 * Using the values captured by bge_chip_cfg_init(), and additional probes 2570 * as required, characterise the chip fully: determine the label by which 2571 * to refer to this chip, the correct settings for various registers, and 2572 * of course whether the device and/or subsystem are supported! 2573 */ 2574 int bge_chip_id_init(bge_t *bgep); 2575 #pragma no_inline(bge_chip_id_init) 2576 2577 int 2578 bge_chip_id_init(bge_t *bgep) 2579 { 2580 char buf[MAXPATHLEN]; /* any risk of stack overflow? */ 2581 boolean_t dev_ok; 2582 chip_id_t *cidp; 2583 uint32_t subid; 2584 char *devname; 2585 char *sysname; 2586 int *ids; 2587 int err; 2588 uint_t i; 2589 2590 dev_ok = B_FALSE; 2591 cidp = &bgep->chipid; 2592 2593 /* 2594 * Check the PCI device ID to determine the generic chip type and 2595 * select parameters that depend on this. 2596 * 2597 * Note: because the SPARC platforms in general don't fit the 2598 * SEEPROM 'behind' the chip, the PCI revision ID register reads 2599 * as zero - which is why we use <asic_rev> rather than <revision> 2600 * below ... 2601 * 2602 * Note: in general we can't distinguish between the Copper/SerDes 2603 * versions by ID alone, as some Copper devices (e.g. some but not 2604 * all 5703Cs) have the same ID as the SerDes equivalents. So we 2605 * treat them the same here, and the MII code works out the media 2606 * type later on ... 2607 */ 2608 cidp->mbuf_base = bge_mbuf_pool_base; 2609 cidp->mbuf_length = bge_mbuf_pool_len; 2610 cidp->recv_slots = BGE_RECV_SLOTS_USED; 2611 cidp->bge_dma_rwctrl = bge_dma_rwctrl; 2612 cidp->pci_type = BGE_PCI_X; 2613 cidp->statistic_type = BGE_STAT_BLK; 2614 cidp->mbuf_lo_water_rdma = bge_mbuf_lo_water_rdma; 2615 cidp->mbuf_lo_water_rmac = bge_mbuf_lo_water_rmac; 2616 cidp->mbuf_hi_water = bge_mbuf_hi_water; 2617 cidp->rx_ticks_norm = bge_rx_ticks_norm; 2618 cidp->rx_count_norm = bge_rx_count_norm; 2619 cidp->tx_ticks_norm = bge_tx_ticks_norm; 2620 cidp->tx_count_norm = bge_tx_count_norm; 2621 cidp->mask_pci_int = MHCR_MASK_PCI_INT_OUTPUT; 2622 2623 if (cidp->rx_rings == 0 || cidp->rx_rings > BGE_RECV_RINGS_MAX) 2624 cidp->rx_rings = BGE_RECV_RINGS_DEFAULT; 2625 if (cidp->tx_rings == 0 || cidp->tx_rings > BGE_SEND_RINGS_MAX) 2626 cidp->tx_rings = BGE_SEND_RINGS_DEFAULT; 2627 2628 cidp->msi_enabled = B_FALSE; 2629 2630 switch (cidp->device) { 2631 case DEVICE_ID_5717: 2632 case DEVICE_ID_5718: 2633 case DEVICE_ID_5719: 2634 case DEVICE_ID_5720: 2635 case DEVICE_ID_5724: 2636 case DEVICE_ID_5725: 2637 case DEVICE_ID_5727: 2638 case DEVICE_ID_57761: 2639 case DEVICE_ID_57762: 2640 case DEVICE_ID_57765: 2641 case DEVICE_ID_57766: 2642 case DEVICE_ID_57781: 2643 case DEVICE_ID_57782: 2644 case DEVICE_ID_57785: 2645 case DEVICE_ID_57786: 2646 case DEVICE_ID_57791: 2647 case DEVICE_ID_57795: 2648 if (cidp->device == DEVICE_ID_5717) { 2649 cidp->chip_label = 5717; 2650 } else if (cidp->device == DEVICE_ID_5718) { 2651 cidp->chip_label = 5718; 2652 } else if (cidp->device == DEVICE_ID_5719) { 2653 cidp->chip_label = 5719; 2654 } else if (cidp->device == DEVICE_ID_5720) { 2655 if (pci_config_get16(bgep->cfg_handle, PCI_CONF_DEVID) == 2656 DEVICE_ID_5717_C0) { 2657 cidp->chip_label = 5717; 2658 } else { 2659 cidp->chip_label = 5720; 2660 } 2661 } else if (cidp->device == DEVICE_ID_5724) { 2662 cidp->chip_label = 5724; 2663 } else if (cidp->device == DEVICE_ID_5725) { 2664 cidp->chip_label = 5725; 2665 } else if (cidp->device == DEVICE_ID_5727) { 2666 cidp->chip_label = 5727; 2667 } else if (cidp->device == DEVICE_ID_57761) { 2668 cidp->chip_label = 57761; 2669 } else if (cidp->device == DEVICE_ID_57762) { 2670 cidp->chip_label = 57762; 2671 } else if (cidp->device == DEVICE_ID_57765) { 2672 cidp->chip_label = 57765; 2673 } else if (cidp->device == DEVICE_ID_57766) { 2674 cidp->chip_label = 57766; 2675 } else if (cidp->device == DEVICE_ID_57781) { 2676 cidp->chip_label = 57781; 2677 } else if (cidp->device == DEVICE_ID_57782) { 2678 cidp->chip_label = 57782; 2679 } else if (cidp->device == DEVICE_ID_57785) { 2680 cidp->chip_label = 57785; 2681 } else if (cidp->device == DEVICE_ID_57786) { 2682 cidp->chip_label = 57786; 2683 } else if (cidp->device == DEVICE_ID_57791) { 2684 cidp->chip_label = 57791; 2685 } else if (cidp->device == DEVICE_ID_57795) { 2686 cidp->chip_label = 57795; 2687 } 2688 2689 cidp->msi_enabled = bge_enable_msi; 2690 #ifdef __sparc 2691 cidp->mask_pci_int = LE_32(MHCR_MASK_PCI_INT_OUTPUT); 2692 #endif 2693 cidp->bge_dma_rwctrl = LE_32(PDRWCR_VAR_5717); 2694 cidp->pci_type = BGE_PCI_E; 2695 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2696 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5717; 2697 cidp->mbuf_hi_water = MBUF_HIWAT_5717; 2698 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2699 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2700 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2701 if (DEVICE_57765_SERIES_CHIPSETS(bgep)) { 2702 cidp->bge_mlcr_default = MLCR_DEFAULT_57765; 2703 } else { 2704 cidp->bge_mlcr_default = MLCR_DEFAULT_5717; 2705 } 2706 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2707 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2708 cidp->statistic_type = BGE_STAT_REG; 2709 dev_ok = B_TRUE; 2710 break; 2711 2712 case DEVICE_ID_5700: 2713 case DEVICE_ID_5700x: 2714 cidp->chip_label = 5700; 2715 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2716 break; 2717 2718 case DEVICE_ID_5701: 2719 cidp->chip_label = 5701; 2720 dev_ok = B_TRUE; 2721 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2722 break; 2723 2724 case DEVICE_ID_5702: 2725 case DEVICE_ID_5702fe: 2726 cidp->chip_label = 5702; 2727 dev_ok = B_TRUE; 2728 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2729 cidp->pci_type = BGE_PCI; 2730 break; 2731 2732 case DEVICE_ID_5703C: 2733 case DEVICE_ID_5703S: 2734 case DEVICE_ID_5703: 2735 /* 2736 * Revision A0 of the 5703/5793 had various errata 2737 * that we can't or don't work around, so it's not 2738 * supported, but all later versions are 2739 */ 2740 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5793 : 5703; 2741 if (bgep->chipid.asic_rev != MHCR_CHIP_REV_5703_A0) 2742 dev_ok = B_TRUE; 2743 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2744 break; 2745 2746 case DEVICE_ID_5704C: 2747 case DEVICE_ID_5704S: 2748 case DEVICE_ID_5704: 2749 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5794 : 5704; 2750 cidp->mbuf_base = bge_mbuf_pool_base_5704; 2751 cidp->mbuf_length = bge_mbuf_pool_len_5704; 2752 dev_ok = B_TRUE; 2753 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2754 break; 2755 2756 case DEVICE_ID_5705C: 2757 case DEVICE_ID_5705M: 2758 case DEVICE_ID_5705MA3: 2759 case DEVICE_ID_5705F: 2760 case DEVICE_ID_5705_2: 2761 case DEVICE_ID_5754: 2762 if (cidp->device == DEVICE_ID_5754) { 2763 cidp->chip_label = 5754; 2764 cidp->pci_type = BGE_PCI_E; 2765 } else { 2766 cidp->chip_label = 5705; 2767 cidp->pci_type = BGE_PCI; 2768 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2769 } 2770 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2771 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2772 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2773 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2774 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2775 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2776 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2777 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2778 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2779 cidp->statistic_type = BGE_STAT_REG; 2780 dev_ok = B_TRUE; 2781 break; 2782 2783 case DEVICE_ID_5906: 2784 case DEVICE_ID_5906M: 2785 cidp->chip_label = 5906; 2786 cidp->pci_type = BGE_PCI_E; 2787 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5906; 2788 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5906; 2789 cidp->mbuf_hi_water = MBUF_HIWAT_5906; 2790 cidp->mbuf_base = bge_mbuf_pool_base; 2791 cidp->mbuf_length = bge_mbuf_pool_len; 2792 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2793 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2794 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2795 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2796 cidp->statistic_type = BGE_STAT_REG; 2797 dev_ok = B_TRUE; 2798 break; 2799 2800 case DEVICE_ID_5753: 2801 cidp->chip_label = 5753; 2802 cidp->pci_type = BGE_PCI_E; 2803 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2804 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2805 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2806 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2807 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2808 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2809 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2810 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2811 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2812 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2813 cidp->statistic_type = BGE_STAT_REG; 2814 dev_ok = B_TRUE; 2815 break; 2816 2817 case DEVICE_ID_5755: 2818 case DEVICE_ID_5755M: 2819 cidp->chip_label = 5755; 2820 cidp->pci_type = BGE_PCI_E; 2821 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2822 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2823 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2824 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2825 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2826 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2827 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2828 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2829 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2830 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2831 if (cidp->device == DEVICE_ID_5755M) 2832 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2833 cidp->statistic_type = BGE_STAT_REG; 2834 dev_ok = B_TRUE; 2835 break; 2836 2837 case DEVICE_ID_5756M: 2838 /* 2839 * This is nearly identical to the 5755M. 2840 * (Actually reports the 5755 chip ID.) 2841 */ 2842 cidp->chip_label = 5756; 2843 cidp->pci_type = BGE_PCI_E; 2844 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2845 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2846 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2847 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2848 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2849 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2850 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2851 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2852 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2853 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2854 cidp->statistic_type = BGE_STAT_REG; 2855 dev_ok = B_TRUE; 2856 break; 2857 2858 case DEVICE_ID_5787: 2859 case DEVICE_ID_5787M: 2860 cidp->chip_label = 5787; 2861 cidp->pci_type = BGE_PCI_E; 2862 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2863 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2864 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2865 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2866 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2867 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2868 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2869 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2870 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2871 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2872 cidp->statistic_type = BGE_STAT_REG; 2873 dev_ok = B_TRUE; 2874 break; 2875 2876 case DEVICE_ID_5723: 2877 case DEVICE_ID_5761: 2878 case DEVICE_ID_5761E: 2879 case DEVICE_ID_57780: 2880 cidp->msi_enabled = bge_enable_msi; 2881 /* 2882 * We don't use MSI for BCM5764 and BCM5785, as the 2883 * status block may fail to update when the network 2884 * traffic is heavy. 2885 */ 2886 /* FALLTHRU */ 2887 case DEVICE_ID_5785: 2888 case DEVICE_ID_5764: 2889 if (cidp->device == DEVICE_ID_5723) 2890 cidp->chip_label = 5723; 2891 else if (cidp->device == DEVICE_ID_5764) 2892 cidp->chip_label = 5764; 2893 else if (cidp->device == DEVICE_ID_5785) 2894 cidp->chip_label = 5785; 2895 else if (cidp->device == DEVICE_ID_57780) 2896 cidp->chip_label = 57780; 2897 else 2898 cidp->chip_label = 5761; 2899 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2900 cidp->pci_type = BGE_PCI_E; 2901 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2902 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2903 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2904 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2905 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2906 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2907 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2908 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2909 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2910 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2911 cidp->statistic_type = BGE_STAT_REG; 2912 dev_ok = B_TRUE; 2913 break; 2914 2915 /* PCI-X device, identical to 5714 */ 2916 case DEVICE_ID_5780: 2917 cidp->chip_label = 5780; 2918 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2919 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2920 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2921 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2922 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2923 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2924 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2925 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2926 cidp->statistic_type = BGE_STAT_REG; 2927 dev_ok = B_TRUE; 2928 break; 2929 2930 case DEVICE_ID_5782: 2931 /* 2932 * Apart from the label, we treat this as a 5705(?) 2933 */ 2934 cidp->chip_label = 5782; 2935 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2936 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2937 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2938 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2939 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2940 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2941 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2942 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2943 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2944 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2945 cidp->statistic_type = BGE_STAT_REG; 2946 dev_ok = B_TRUE; 2947 break; 2948 2949 case DEVICE_ID_5788: 2950 /* 2951 * Apart from the label, we treat this as a 5705(?) 2952 */ 2953 cidp->chip_label = 5788; 2954 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2955 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2956 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2957 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2958 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2959 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2960 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2961 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2962 cidp->statistic_type = BGE_STAT_REG; 2963 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2964 dev_ok = B_TRUE; 2965 break; 2966 2967 case DEVICE_ID_5714C: 2968 if (cidp->revision >= REVISION_ID_5714_A2) 2969 cidp->msi_enabled = bge_enable_msi; 2970 /* FALLTHRU */ 2971 case DEVICE_ID_5714S: 2972 cidp->chip_label = 5714; 2973 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2974 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2975 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2976 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2977 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2978 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2979 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5714; 2980 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2981 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2982 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2983 cidp->pci_type = BGE_PCI_E; 2984 cidp->statistic_type = BGE_STAT_REG; 2985 dev_ok = B_TRUE; 2986 break; 2987 2988 case DEVICE_ID_5715C: 2989 case DEVICE_ID_5715S: 2990 cidp->chip_label = 5715; 2991 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2992 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2993 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2994 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2995 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2996 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2997 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5715; 2998 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2999 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 3000 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 3001 cidp->pci_type = BGE_PCI_E; 3002 cidp->statistic_type = BGE_STAT_REG; 3003 if (cidp->revision >= REVISION_ID_5715_A2) 3004 cidp->msi_enabled = bge_enable_msi; 3005 dev_ok = B_TRUE; 3006 break; 3007 3008 case DEVICE_ID_5721: 3009 cidp->chip_label = 5721; 3010 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 3011 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 3012 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 3013 cidp->mbuf_base = bge_mbuf_pool_base_5721; 3014 cidp->mbuf_length = bge_mbuf_pool_len_5721; 3015 cidp->recv_slots = BGE_RECV_SLOTS_5721; 3016 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 3017 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 3018 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 3019 cidp->pci_type = BGE_PCI_E; 3020 cidp->statistic_type = BGE_STAT_REG; 3021 cidp->flags |= CHIP_FLAG_NO_JUMBO; 3022 dev_ok = B_TRUE; 3023 break; 3024 3025 case DEVICE_ID_5722: 3026 cidp->chip_label = 5722; 3027 cidp->pci_type = BGE_PCI_E; 3028 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 3029 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 3030 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 3031 cidp->mbuf_base = bge_mbuf_pool_base_5705; 3032 cidp->mbuf_length = bge_mbuf_pool_len_5705; 3033 cidp->recv_slots = BGE_RECV_SLOTS_5705; 3034 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 3035 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 3036 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 3037 cidp->flags |= CHIP_FLAG_NO_JUMBO; 3038 cidp->statistic_type = BGE_STAT_REG; 3039 dev_ok = B_TRUE; 3040 break; 3041 3042 case DEVICE_ID_5751: 3043 case DEVICE_ID_5751M: 3044 cidp->chip_label = 5751; 3045 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 3046 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 3047 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 3048 cidp->mbuf_base = bge_mbuf_pool_base_5721; 3049 cidp->mbuf_length = bge_mbuf_pool_len_5721; 3050 cidp->recv_slots = BGE_RECV_SLOTS_5721; 3051 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 3052 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 3053 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 3054 cidp->pci_type = BGE_PCI_E; 3055 cidp->statistic_type = BGE_STAT_REG; 3056 cidp->flags |= CHIP_FLAG_NO_JUMBO; 3057 dev_ok = B_TRUE; 3058 break; 3059 3060 case DEVICE_ID_5752: 3061 case DEVICE_ID_5752M: 3062 cidp->chip_label = 5752; 3063 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 3064 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 3065 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 3066 cidp->mbuf_base = bge_mbuf_pool_base_5721; 3067 cidp->mbuf_length = bge_mbuf_pool_len_5721; 3068 cidp->recv_slots = BGE_RECV_SLOTS_5721; 3069 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 3070 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 3071 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 3072 cidp->pci_type = BGE_PCI_E; 3073 cidp->statistic_type = BGE_STAT_REG; 3074 cidp->flags |= CHIP_FLAG_NO_JUMBO; 3075 dev_ok = B_TRUE; 3076 break; 3077 3078 case DEVICE_ID_5789: 3079 cidp->chip_label = 5789; 3080 cidp->mbuf_base = bge_mbuf_pool_base_5721; 3081 cidp->mbuf_length = bge_mbuf_pool_len_5721; 3082 cidp->recv_slots = BGE_RECV_SLOTS_5721; 3083 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 3084 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 3085 cidp->tx_rings = BGE_RECV_RINGS_MAX_5705; 3086 cidp->pci_type = BGE_PCI_E; 3087 cidp->statistic_type = BGE_STAT_REG; 3088 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 3089 cidp->flags |= CHIP_FLAG_NO_JUMBO; 3090 cidp->msi_enabled = B_TRUE; 3091 dev_ok = B_TRUE; 3092 break; 3093 3094 } 3095 3096 /* 3097 * Setup the default jumbo parameter. 3098 */ 3099 cidp->ethmax_size = ETHERMAX; 3100 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_DEFAULT; 3101 cidp->std_buf_size = BGE_STD_BUFF_SIZE; 3102 3103 /* 3104 * If jumbo is enabled and this kind of chipset supports jumbo feature, 3105 * setup below jumbo specific parameters. 3106 * 3107 * For BCM5714/5715, there is only one standard receive ring. So the 3108 * std buffer size should be set to BGE_JUMBO_BUFF_SIZE when jumbo 3109 * feature is enabled. 3110 * 3111 * For the BCM5718 family we hijack the standard receive ring for 3112 * the jumboframe traffic, keeps it simple. 3113 */ 3114 if (!(cidp->flags & CHIP_FLAG_NO_JUMBO) && 3115 (cidp->default_mtu > BGE_DEFAULT_MTU)) { 3116 if (DEVICE_5714_SERIES_CHIPSETS(bgep) || 3117 DEVICE_5717_SERIES_CHIPSETS(bgep) || 3118 DEVICE_5725_SERIES_CHIPSETS(bgep) || 3119 DEVICE_57765_SERIES_CHIPSETS(bgep)) { 3120 cidp->mbuf_lo_water_rdma = 3121 RDMA_MBUF_LOWAT_5714_JUMBO; 3122 cidp->mbuf_lo_water_rmac = 3123 MAC_RX_MBUF_LOWAT_5714_JUMBO; 3124 cidp->mbuf_hi_water = MBUF_HIWAT_5714_JUMBO; 3125 cidp->jumbo_slots = 0; 3126 cidp->std_buf_size = BGE_JUMBO_BUFF_SIZE; 3127 } else { 3128 cidp->mbuf_lo_water_rdma = 3129 RDMA_MBUF_LOWAT_JUMBO; 3130 cidp->mbuf_lo_water_rmac = 3131 MAC_RX_MBUF_LOWAT_JUMBO; 3132 cidp->mbuf_hi_water = MBUF_HIWAT_JUMBO; 3133 cidp->jumbo_slots = BGE_JUMBO_SLOTS_USED; 3134 } 3135 cidp->recv_jumbo_size = BGE_JUMBO_BUFF_SIZE; 3136 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_JUMBO; 3137 cidp->ethmax_size = cidp->default_mtu + 3138 sizeof (struct ether_header); 3139 } 3140 3141 /* 3142 * Identify the NV memory type: SEEPROM or Flash? 3143 */ 3144 cidp->nvtype = bge_nvmem_id(bgep); 3145 3146 /* 3147 * Now check what we've discovered: is this truly a supported 3148 * chip on (the motherboard of) a supported platform? 3149 * 3150 * Possible problems here: 3151 * 1) it's a completely unheard-of chip 3152 * 2) it's a recognised but unsupported chip (e.g. 5701, 5703C-A0) 3153 * 3) it's a chip we would support if it were on the motherboard 3154 * of a Sun platform, but this one isn't ;-( 3155 */ 3156 if (cidp->chip_label == 0) 3157 bge_problem(bgep, 3158 "Device 'pci%04x,%04x' not recognized (%d?)", 3159 cidp->vendor, cidp->device, cidp->device); 3160 else if (!dev_ok) 3161 bge_problem(bgep, 3162 "Device 'pci%04x,%04x' (%d) revision %d not supported", 3163 cidp->vendor, cidp->device, cidp->chip_label, 3164 cidp->revision); 3165 else 3166 cidp->flags |= CHIP_FLAG_SUPPORTED; 3167 3168 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 3169 return (EIO); 3170 3171 return (0); 3172 } 3173 3174 void 3175 bge_chip_msi_trig(bge_t *bgep) 3176 { 3177 uint32_t regval; 3178 3179 regval = bgep->param_msi_cnt<<4; 3180 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, regval); 3181 BGE_DEBUG(("bge_chip_msi_trig:data = %d", regval)); 3182 } 3183 3184 /* 3185 * Various registers that control the chip's internal engines (state 3186 * machines) have a <reset> and <enable> bits (fortunately, in the 3187 * same place in each such register :-). 3188 * 3189 * To reset the state machine, the <reset> bit must be written with 1; 3190 * it will then read back as 1 while the reset is in progress, but 3191 * self-clear to 0 when the reset completes. 3192 * 3193 * To enable a state machine, one must set the <enable> bit, which 3194 * will continue to read back as 0 until the state machine is running. 3195 * 3196 * To disable a state machine, the <enable> bit must be cleared, but 3197 * it will continue to read back as 1 until the state machine actually 3198 * stops. 3199 * 3200 * This routine implements polling for completion of a reset, enable 3201 * or disable operation, returning B_TRUE on success (bit reached the 3202 * required state) or B_FALSE on timeout (200*100us == 20ms). 3203 */ 3204 static boolean_t bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 3205 uint32_t mask, uint32_t val); 3206 #pragma no_inline(bge_chip_poll_engine) 3207 3208 static boolean_t 3209 bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 3210 uint32_t mask, uint32_t val) 3211 { 3212 uint32_t regval; 3213 uint32_t n; 3214 3215 BGE_TRACE(("bge_chip_poll_engine($%p, 0x%lx, 0x%x, 0x%x)", 3216 (void *)bgep, regno, mask, val)); 3217 3218 for (n = 200; n; --n) { 3219 regval = bge_reg_get32(bgep, regno); 3220 if ((regval & mask) == val) 3221 return (B_TRUE); 3222 drv_usecwait(100); 3223 } 3224 3225 bge_problem(bgep, "bge_chip_poll_engine failed: regno = 0x%lx", regno); 3226 bge_fm_ereport(bgep, DDI_FM_DEVICE_NO_RESPONSE); 3227 return (B_FALSE); 3228 } 3229 3230 /* 3231 * Various registers that control the chip's internal engines (state 3232 * machines) have a <reset> bit (fortunately, in the same place in 3233 * each such register :-). To reset the state machine, this bit must 3234 * be written with 1; it will then read back as 1 while the reset is 3235 * in progress, but self-clear to 0 when the reset completes. 3236 * 3237 * This code sets the bit, then polls for it to read back as zero. 3238 * The return value is B_TRUE on success (reset bit cleared itself), 3239 * or B_FALSE if the state machine didn't recover :( 3240 * 3241 * NOTE: the Core reset is similar to other resets, except that we 3242 * can't poll for completion, since the Core reset disables memory 3243 * access! So we just have to assume that it will all complete in 3244 * 100us. See Broadcom document 570X-PG102-R, p102, steps 4-5. 3245 */ 3246 static boolean_t bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno); 3247 #pragma no_inline(bge_chip_reset_engine) 3248 3249 static boolean_t 3250 bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno) 3251 { 3252 uint32_t regval; 3253 uint16_t val16; 3254 uint32_t val32; 3255 uint32_t mhcr; 3256 3257 regval = bge_reg_get32(bgep, regno); 3258 3259 BGE_TRACE(("bge_chip_reset_engine($%p, 0x%lx)", 3260 (void *)bgep, regno)); 3261 BGE_DEBUG(("bge_chip_reset_engine: 0x%lx before reset = 0x%08x", 3262 regno, regval)); 3263 3264 regval |= STATE_MACHINE_RESET_BIT; 3265 3266 switch (regno) { 3267 case MISC_CONFIG_REG: 3268 /* 3269 * BCM5714/5721/5751 pcie chip special case. In order to avoid 3270 * resetting PCIE block and bringing PCIE link down, bit 29 3271 * in the register needs to be set first, and then set it again 3272 * while the reset bit is written. 3273 * See:P500 of 57xx-PG102-RDS.pdf. 3274 */ 3275 if (DEVICE_5705_SERIES_CHIPSETS(bgep) || 3276 DEVICE_5717_SERIES_CHIPSETS(bgep) || 3277 DEVICE_5725_SERIES_CHIPSETS(bgep) || 3278 DEVICE_5721_SERIES_CHIPSETS(bgep) || 3279 DEVICE_5723_SERIES_CHIPSETS(bgep) || 3280 DEVICE_5714_SERIES_CHIPSETS(bgep) || 3281 DEVICE_5906_SERIES_CHIPSETS(bgep) || 3282 DEVICE_57765_SERIES_CHIPSETS(bgep)) { 3283 regval |= MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE; 3284 if (bgep->chipid.pci_type == BGE_PCI_E) { 3285 if (bgep->chipid.asic_rev == 3286 MHCR_CHIP_REV_5751_A0 || 3287 bgep->chipid.asic_rev == 3288 MHCR_CHIP_REV_5721_A0 || 3289 bgep->chipid.asic_rev == 3290 MHCR_CHIP_REV_5755_A0) { 3291 val32 = bge_reg_get32(bgep, 3292 PHY_TEST_CTRL_REG); 3293 if (val32 == (PHY_PCIE_SCRAM_MODE | 3294 PHY_PCIE_LTASS_MODE)) 3295 bge_reg_put32(bgep, 3296 PHY_TEST_CTRL_REG, 3297 PHY_PCIE_SCRAM_MODE); 3298 val32 = pci_config_get32 3299 (bgep->cfg_handle, 3300 PCI_CONF_BGE_CLKCTL); 3301 val32 |= CLKCTL_PCIE_A0_FIX; 3302 pci_config_put32(bgep->cfg_handle, 3303 PCI_CONF_BGE_CLKCTL, val32); 3304 } 3305 bge_reg_set32(bgep, regno, 3306 MISC_CONFIG_GRC_RESET_DISABLE); 3307 regval |= MISC_CONFIG_GRC_RESET_DISABLE; 3308 } 3309 } 3310 3311 /* 3312 * Special case - causes Core reset 3313 * 3314 * On SPARC v9 we want to ensure that we don't start 3315 * timing until the I/O access has actually reached 3316 * the chip, otherwise we might make the next access 3317 * too early. And we can't just force the write out 3318 * by following it with a read (even to config space) 3319 * because that would cause the fault we're trying 3320 * to avoid. Hence the need for membar_sync() here. 3321 */ 3322 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), regval); 3323 #ifdef __sparcv9 3324 membar_sync(); 3325 #endif /* __sparcv9 */ 3326 /* 3327 * On some platforms,system need about 300us for 3328 * link setup. 3329 */ 3330 drv_usecwait(300); 3331 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) { 3332 bge_reg_set32(bgep, VCPU_STATUS_REG, VCPU_DRV_RESET); 3333 bge_reg_clr32( 3334 bgep, VCPU_EXT_CTL, VCPU_EXT_CTL_HALF); 3335 } 3336 3337 if (bgep->chipid.pci_type == BGE_PCI_E) { 3338 /* PCI-E device need more reset time */ 3339 drv_usecwait(120000); 3340 3341 /* 3342 * (re)Disable interrupts as the bit can be reset after a 3343 * core clock reset. 3344 */ 3345 mhcr = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MHCR); 3346 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, 3347 mhcr | MHCR_MASK_PCI_INT_OUTPUT); 3348 3349 /* Set PCIE max payload size and clear error status. */ 3350 if ((bgep->chipid.chip_label == 5721) || 3351 (bgep->chipid.chip_label == 5751) || 3352 (bgep->chipid.chip_label == 5752) || 3353 (bgep->chipid.chip_label == 5789) || 3354 (bgep->chipid.chip_label == 5906)) { 3355 pci_config_put16(bgep->cfg_handle, 3356 PCI_CONF_DEV_CTRL, READ_REQ_SIZE_MAX); 3357 pci_config_put16(bgep->cfg_handle, 3358 PCI_CONF_DEV_STUS, DEVICE_ERROR_STUS); 3359 } 3360 3361 if ((bgep->chipid.chip_label == 5723) || 3362 (bgep->chipid.chip_label == 5761)) { 3363 pci_config_put16(bgep->cfg_handle, 3364 PCI_CONF_DEV_CTRL_5723, READ_REQ_SIZE_MAX); 3365 pci_config_put16(bgep->cfg_handle, 3366 PCI_CONF_DEV_STUS_5723, DEVICE_ERROR_STUS); 3367 } 3368 3369 if (DEVICE_5717_SERIES_CHIPSETS(bgep) || 3370 DEVICE_5725_SERIES_CHIPSETS(bgep) || 3371 DEVICE_57765_SERIES_CHIPSETS(bgep)) { 3372 val16 = pci_config_get16(bgep->cfg_handle, 3373 PCI_CONF_DEV_CTRL_5717); 3374 val16 &= ~READ_REQ_SIZE_MASK; 3375 val16 |= READ_REQ_SIZE_2K; 3376 pci_config_put16(bgep->cfg_handle, 3377 PCI_CONF_DEV_CTRL_5717, val16); 3378 } 3379 } 3380 3381 BGE_PCICHK(bgep); 3382 return (B_TRUE); 3383 3384 default: 3385 bge_reg_put32(bgep, regno, regval); 3386 return (bge_chip_poll_engine(bgep, regno, 3387 STATE_MACHINE_RESET_BIT, 0)); 3388 } 3389 } 3390 3391 /* 3392 * Various registers that control the chip's internal engines (state 3393 * machines) have an <enable> bit (fortunately, in the same place in 3394 * each such register :-). To stop the state machine, this bit must 3395 * be written with 0, then polled to see when the state machine has 3396 * actually stopped. 3397 * 3398 * The return value is B_TRUE on success (enable bit cleared), or 3399 * B_FALSE if the state machine didn't stop :( 3400 */ 3401 static boolean_t bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, 3402 uint32_t morebits); 3403 #pragma no_inline(bge_chip_disable_engine) 3404 3405 static boolean_t 3406 bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 3407 { 3408 uint32_t regval; 3409 3410 BGE_TRACE(("bge_chip_disable_engine($%p, 0x%lx, 0x%x)", 3411 (void *)bgep, regno, morebits)); 3412 3413 switch (regno) { 3414 case FTQ_RESET_REG: 3415 /* 3416 * For Schumacher's bugfix CR6490108 3417 */ 3418 #ifdef BGE_IPMI_ASF 3419 #ifdef BGE_NETCONSOLE 3420 if (bgep->asf_enabled) 3421 return (B_TRUE); 3422 #endif 3423 #endif 3424 /* 3425 * Not quite like the others; it doesn't 3426 * have an <enable> bit, but instead we 3427 * have to set and then clear all the bits 3428 */ 3429 bge_reg_put32(bgep, regno, ~(uint32_t)0); 3430 drv_usecwait(100); 3431 bge_reg_put32(bgep, regno, 0); 3432 return (B_TRUE); 3433 3434 default: 3435 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3436 break; 3437 } 3438 3439 if ((regno == RCV_LIST_SELECTOR_MODE_REG) || 3440 (regno == DMA_COMPLETION_MODE_REG) || 3441 (regno == MBUF_CLUSTER_FREE_MODE_REG) || 3442 (regno == BUFFER_MANAGER_MODE_REG) || 3443 (regno == MEMORY_ARBITER_MODE_REG)) { 3444 return B_TRUE; 3445 } 3446 3447 break; 3448 } 3449 3450 regval = bge_reg_get32(bgep, regno); 3451 regval &= ~STATE_MACHINE_ENABLE_BIT; 3452 regval &= ~morebits; 3453 bge_reg_put32(bgep, regno, regval); 3454 3455 return bge_chip_poll_engine(bgep, regno, STATE_MACHINE_ENABLE_BIT, 0); 3456 } 3457 3458 /* 3459 * Various registers that control the chip's internal engines (state 3460 * machines) have an <enable> bit (fortunately, in the same place in 3461 * each such register :-). To start the state machine, this bit must 3462 * be written with 1, then polled to see when the state machine has 3463 * actually started. 3464 * 3465 * The return value is B_TRUE on success (enable bit set), or 3466 * B_FALSE if the state machine didn't start :( 3467 */ 3468 static boolean_t bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, 3469 uint32_t morebits); 3470 #pragma no_inline(bge_chip_enable_engine) 3471 3472 static boolean_t 3473 bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 3474 { 3475 uint32_t regval; 3476 3477 BGE_TRACE(("bge_chip_enable_engine($%p, 0x%lx, 0x%x)", 3478 (void *)bgep, regno, morebits)); 3479 3480 switch (regno) { 3481 case FTQ_RESET_REG: 3482 #ifdef BGE_IPMI_ASF 3483 #ifdef BGE_NETCONSOLE 3484 if (bgep->asf_enabled) 3485 return (B_TRUE); 3486 #endif 3487 #endif 3488 /* 3489 * Not quite like the others; it doesn't 3490 * have an <enable> bit, but instead we 3491 * have to set and then clear all the bits 3492 */ 3493 bge_reg_put32(bgep, regno, ~(uint32_t)0); 3494 drv_usecwait(100); 3495 bge_reg_put32(bgep, regno, 0); 3496 return (B_TRUE); 3497 3498 default: 3499 regval = bge_reg_get32(bgep, regno); 3500 regval |= STATE_MACHINE_ENABLE_BIT; 3501 regval |= morebits; 3502 bge_reg_put32(bgep, regno, regval); 3503 return (bge_chip_poll_engine(bgep, regno, 3504 STATE_MACHINE_ENABLE_BIT, STATE_MACHINE_ENABLE_BIT)); 3505 } 3506 } 3507 3508 /* 3509 * Reprogram the Ethernet, Transmit, and Receive MAC 3510 * modes to match the param_* variables 3511 */ 3512 void bge_sync_mac_modes(bge_t *bgep); 3513 #pragma no_inline(bge_sync_mac_modes) 3514 3515 void 3516 bge_sync_mac_modes(bge_t *bgep) 3517 { 3518 uint32_t macmode; 3519 uint32_t regval; 3520 3521 ASSERT(mutex_owned(bgep->genlock)); 3522 3523 /* 3524 * Reprogram the Ethernet MAC mode ... 3525 */ 3526 macmode = regval = bge_reg_get32(bgep, ETHERNET_MAC_MODE_REG); 3527 macmode &= ~ETHERNET_MODE_LINK_POLARITY; 3528 macmode &= ~ETHERNET_MODE_PORTMODE_MASK; 3529 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 3530 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) { 3531 if (DEVICE_5717_SERIES_CHIPSETS(bgep) || 3532 DEVICE_5725_SERIES_CHIPSETS(bgep) || 3533 DEVICE_5714_SERIES_CHIPSETS(bgep) || 3534 DEVICE_57765_SERIES_CHIPSETS(bgep)) 3535 macmode |= ETHERNET_MODE_PORTMODE_GMII; 3536 else 3537 macmode |= ETHERNET_MODE_PORTMODE_TBI; 3538 } else if (bgep->param_link_speed == 10 || 3539 bgep->param_link_speed == 100) 3540 macmode |= ETHERNET_MODE_PORTMODE_MII; 3541 else 3542 macmode |= ETHERNET_MODE_PORTMODE_GMII; 3543 if (bgep->param_link_duplex == LINK_DUPLEX_HALF) 3544 macmode |= ETHERNET_MODE_HALF_DUPLEX; 3545 else 3546 macmode &= ~ETHERNET_MODE_HALF_DUPLEX; 3547 if (bgep->param_loop_mode == BGE_LOOP_INTERNAL_MAC) 3548 macmode |= ETHERNET_MODE_MAC_LOOPBACK; 3549 else 3550 macmode &= ~ETHERNET_MODE_MAC_LOOPBACK; 3551 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, macmode); 3552 BGE_DEBUG(("bge_sync_mac_modes($%p) Ethernet MAC mode 0x%x => 0x%x", 3553 (void *)bgep, regval, macmode)); 3554 3555 /* 3556 * ... the Transmit MAC mode ... 3557 */ 3558 macmode = regval = bge_reg_get32(bgep, TRANSMIT_MAC_MODE_REG); 3559 if (bgep->param_link_tx_pause) 3560 macmode |= TRANSMIT_MODE_FLOW_CONTROL; 3561 else 3562 macmode &= ~TRANSMIT_MODE_FLOW_CONTROL; 3563 bge_reg_put32(bgep, TRANSMIT_MAC_MODE_REG, macmode); 3564 BGE_DEBUG(("bge_sync_mac_modes($%p) Transmit MAC mode 0x%x => 0x%x", 3565 (void *)bgep, regval, macmode)); 3566 3567 /* 3568 * ... and the Receive MAC mode 3569 */ 3570 macmode = regval = bge_reg_get32(bgep, RECEIVE_MAC_MODE_REG); 3571 if (bgep->param_link_rx_pause) 3572 macmode |= RECEIVE_MODE_FLOW_CONTROL; 3573 else 3574 macmode &= ~RECEIVE_MODE_FLOW_CONTROL; 3575 bge_reg_put32(bgep, RECEIVE_MAC_MODE_REG, macmode); 3576 BGE_DEBUG(("bge_sync_mac_modes($%p) Receive MAC mode 0x%x => 0x%x", 3577 (void *)bgep, regval, macmode)); 3578 3579 /* 3580 * For BCM5785, we need to configure the link status in the MI Status 3581 * register with a write command when auto-polling is disabled. 3582 */ 3583 if (bgep->chipid.device == DEVICE_ID_5785) 3584 if (bgep->param_link_speed == 10) 3585 bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK 3586 | MI_STATUS_10MBPS); 3587 else 3588 bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK); 3589 } 3590 3591 /* 3592 * bge_chip_sync() -- program the chip with the unicast MAC address, 3593 * the multicast hash table, the required level of promiscuity, and 3594 * the current loopback mode ... 3595 */ 3596 #ifdef BGE_IPMI_ASF 3597 int bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive); 3598 #else 3599 int bge_chip_sync(bge_t *bgep); 3600 #endif 3601 #pragma no_inline(bge_chip_sync) 3602 3603 int 3604 #ifdef BGE_IPMI_ASF 3605 bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive) 3606 #else 3607 bge_chip_sync(bge_t *bgep) 3608 #endif 3609 { 3610 void (*opfn)(bge_t *bgep, bge_regno_t reg, uint32_t bits); 3611 boolean_t promisc; 3612 uint64_t macaddr; 3613 uint32_t fill = 0; 3614 int i, j; 3615 int retval = DDI_SUCCESS; 3616 3617 BGE_TRACE(("bge_chip_sync($%p)", 3618 (void *)bgep)); 3619 3620 ASSERT(mutex_owned(bgep->genlock)); 3621 3622 promisc = B_FALSE; 3623 fill = ~(uint32_t)0; 3624 3625 if (bgep->promisc) 3626 promisc = B_TRUE; 3627 else 3628 fill = (uint32_t)0; 3629 3630 /* 3631 * If the TX/RX MAC engines are already running, we should stop 3632 * them (and reset the RX engine) before changing the parameters. 3633 * If they're not running, this will have no effect ... 3634 * 3635 * NOTE: this is currently disabled by default because stopping 3636 * and restarting the Tx engine may cause an outgoing packet in 3637 * transit to be truncated. Also, stopping and restarting the 3638 * Rx engine seems to not work correctly on the 5705. Testing 3639 * has not (yet!) revealed any problems with NOT stopping and 3640 * restarting these engines (and Broadcom say their drivers don't 3641 * do this), but if it is found to cause problems, this variable 3642 * can be patched to re-enable the old behaviour ... 3643 */ 3644 if (bge_stop_start_on_sync) { 3645 #ifdef BGE_IPMI_ASF 3646 if (!bgep->asf_enabled) { 3647 if (!bge_chip_disable_engine(bgep, 3648 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG)) 3649 retval = DDI_FAILURE; 3650 } else { 3651 if (!bge_chip_disable_engine(bgep, 3652 RECEIVE_MAC_MODE_REG, 0)) 3653 retval = DDI_FAILURE; 3654 } 3655 #else 3656 if (!bge_chip_disable_engine(bgep, RECEIVE_MAC_MODE_REG, 3657 RECEIVE_MODE_KEEP_VLAN_TAG)) 3658 retval = DDI_FAILURE; 3659 #endif 3660 if (!bge_chip_disable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 3661 retval = DDI_FAILURE; 3662 if (!bge_chip_reset_engine(bgep, RECEIVE_MAC_MODE_REG)) 3663 retval = DDI_FAILURE; 3664 } 3665 3666 /* 3667 * Reprogram the hashed multicast address table ... 3668 */ 3669 for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i) 3670 bge_reg_put32(bgep, MAC_HASH_REG(i), 0); 3671 3672 for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i) 3673 bge_reg_put32(bgep, MAC_HASH_REG(i), 3674 bgep->mcast_hash[i] | fill); 3675 3676 #ifdef BGE_IPMI_ASF 3677 if (!bgep->asf_enabled || !asf_keeplive) { 3678 #endif 3679 /* 3680 * Transform the MAC address(es) from host to chip format, then 3681 * reprogram the transmit random backoff seed and the unicast 3682 * MAC address(es) ... 3683 */ 3684 for (j = 0; j < MAC_ADDRESS_REGS_MAX; j++) { 3685 for (i = 0, macaddr = 0ull; 3686 i < ETHERADDRL; ++i) { 3687 macaddr <<= 8; 3688 macaddr |= bgep->curr_addr[j].addr[i]; 3689 } 3690 fill += (macaddr >> 16) + (macaddr & 0xffffffff); 3691 bge_reg_put64(bgep, MAC_ADDRESS_REG(j), macaddr); 3692 3693 BGE_DEBUG(("bge_chip_sync($%p) " 3694 "setting MAC address %012llx", 3695 (void *)bgep, macaddr)); 3696 } 3697 #ifdef BGE_IPMI_ASF 3698 } 3699 #endif 3700 /* 3701 * Set random seed of backoff interval 3702 * - Writing zero means no backoff interval 3703 */ 3704 fill = ((fill >> 20) + (fill >> 10) + fill) & 0x3ff; 3705 if (fill == 0) 3706 fill = 1; 3707 bge_reg_put32(bgep, MAC_TX_RANDOM_BACKOFF_REG, fill); 3708 3709 /* 3710 * Set or clear the PROMISCUOUS mode bit 3711 */ 3712 opfn = promisc ? bge_reg_set32 : bge_reg_clr32; 3713 (*opfn)(bgep, RECEIVE_MAC_MODE_REG, RECEIVE_MODE_PROMISCUOUS); 3714 3715 /* 3716 * Sync the rest of the MAC modes too ... 3717 */ 3718 bge_sync_mac_modes(bgep); 3719 3720 /* 3721 * Restart RX/TX MAC engines if required ... 3722 */ 3723 if (bgep->bge_chip_state == BGE_CHIP_RUNNING) { 3724 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 3725 retval = DDI_FAILURE; 3726 #ifdef BGE_IPMI_ASF 3727 if (!bgep->asf_enabled) { 3728 if (!bge_chip_enable_engine(bgep, 3729 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG)) 3730 retval = DDI_FAILURE; 3731 } else { 3732 if (!bge_chip_enable_engine(bgep, 3733 RECEIVE_MAC_MODE_REG, 0)) 3734 retval = DDI_FAILURE; 3735 } 3736 #else 3737 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 3738 RECEIVE_MODE_KEEP_VLAN_TAG)) 3739 retval = DDI_FAILURE; 3740 #endif 3741 } 3742 return (retval); 3743 } 3744 3745 #ifndef __sparc 3746 static bge_regno_t quiesce_regs[] = { 3747 READ_DMA_MODE_REG, 3748 DMA_COMPLETION_MODE_REG, 3749 WRITE_DMA_MODE_REG, 3750 BGE_REGNO_NONE 3751 }; 3752 3753 void bge_chip_stop_nonblocking(bge_t *bgep); 3754 #pragma no_inline(bge_chip_stop_nonblocking) 3755 3756 /* 3757 * This function is called by bge_quiesce(). We 3758 * turn off all the DMA engines here. 3759 */ 3760 void 3761 bge_chip_stop_nonblocking(bge_t *bgep) 3762 { 3763 bge_regno_t *rbp; 3764 3765 /* 3766 * Flag that no more activity may be initiated 3767 */ 3768 bgep->progress &= ~PROGRESS_READY; 3769 3770 rbp = quiesce_regs; 3771 while (*rbp != BGE_REGNO_NONE) { 3772 (void) bge_chip_disable_engine(bgep, *rbp, 0); 3773 ++rbp; 3774 } 3775 3776 bgep->bge_chip_state = BGE_CHIP_STOPPED; 3777 } 3778 3779 #endif 3780 3781 /* 3782 * bge_chip_stop() -- stop all chip processing 3783 * 3784 * If the <fault> parameter is B_TRUE, we're stopping the chip because 3785 * we've detected a problem internally; otherwise, this is a normal 3786 * (clean) stop (at user request i.e. the last STREAM has been closed). 3787 */ 3788 void bge_chip_stop(bge_t *bgep, boolean_t fault); 3789 #pragma no_inline(bge_chip_stop) 3790 3791 void 3792 bge_chip_stop(bge_t *bgep, boolean_t fault) 3793 { 3794 bge_regno_t regno; 3795 bge_regno_t *rbp; 3796 boolean_t ok = B_TRUE; 3797 3798 BGE_TRACE(("bge_chip_stop($%p)", 3799 (void *)bgep)); 3800 3801 ASSERT(mutex_owned(bgep->genlock)); 3802 3803 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, 3804 (pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MHCR) | 3805 MHCR_MASK_PCI_INT_OUTPUT)); 3806 3807 ok &= bge_chip_disable_engine(bgep, RECEIVE_MAC_MODE_REG, 0); 3808 ok &= bge_chip_disable_engine(bgep, RCV_BD_INITIATOR_MODE_REG, 0); 3809 ok &= bge_chip_disable_engine(bgep, RCV_LIST_PLACEMENT_MODE_REG, 0); 3810 ok &= bge_chip_disable_engine(bgep, RCV_LIST_SELECTOR_MODE_REG, 0); 3811 ok &= bge_chip_disable_engine(bgep, RCV_DATA_BD_INITIATOR_MODE_REG, 0); 3812 ok &= bge_chip_disable_engine(bgep, RCV_DATA_COMPLETION_MODE_REG, 0); 3813 ok &= bge_chip_disable_engine(bgep, RCV_BD_COMPLETION_MODE_REG, 0); 3814 3815 ok &= bge_chip_disable_engine(bgep, SEND_BD_SELECTOR_MODE_REG, 0); 3816 ok &= bge_chip_disable_engine(bgep, SEND_BD_INITIATOR_MODE_REG, 0); 3817 ok &= bge_chip_disable_engine(bgep, SEND_DATA_INITIATOR_MODE_REG, 0); 3818 ok &= bge_chip_disable_engine(bgep, READ_DMA_MODE_REG, 0); 3819 ok &= bge_chip_disable_engine(bgep, SEND_DATA_COMPLETION_MODE_REG, 0); 3820 ok &= bge_chip_disable_engine(bgep, DMA_COMPLETION_MODE_REG, 0); 3821 ok &= bge_chip_disable_engine(bgep, SEND_BD_COMPLETION_MODE_REG, 0); 3822 ok &= bge_chip_disable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0); 3823 3824 bge_reg_clr32(bgep, ETHERNET_MAC_MODE_REG, ETHERNET_MODE_ENABLE_TDE); 3825 drv_usecwait(40); 3826 3827 ok &= bge_chip_disable_engine(bgep, HOST_COALESCE_MODE_REG, 0); 3828 ok &= bge_chip_disable_engine(bgep, WRITE_DMA_MODE_REG, 0); 3829 ok &= bge_chip_disable_engine(bgep, MBUF_CLUSTER_FREE_MODE_REG, 0); 3830 ok &= bge_chip_disable_engine(bgep, FTQ_RESET_REG, 0); 3831 ok &= bge_chip_disable_engine(bgep, BUFFER_MANAGER_MODE_REG, 0); 3832 ok &= bge_chip_disable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0); 3833 ok &= bge_chip_disable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0); 3834 3835 if (!ok && !fault) 3836 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 3837 3838 /* 3839 * Finally, disable (all) MAC events & clear the MAC status 3840 */ 3841 bge_reg_put32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 0); 3842 bge_reg_put32(bgep, ETHERNET_MAC_STATUS_REG, ~0); 3843 3844 /* 3845 * if we're stopping the chip because of a detected fault then do 3846 * appropriate actions 3847 */ 3848 if (fault) { 3849 if (bgep->bge_chip_state != BGE_CHIP_FAULT) { 3850 bgep->bge_chip_state = BGE_CHIP_FAULT; 3851 if (!bgep->manual_reset) 3852 ddi_fm_service_impact(bgep->devinfo, 3853 DDI_SERVICE_LOST); 3854 if (bgep->bge_dma_error) { 3855 /* 3856 * need to free buffers in case the fault was 3857 * due to a memory error in a buffer - got to 3858 * do a fair bit of tidying first 3859 */ 3860 if (bgep->progress & PROGRESS_KSTATS) { 3861 bge_fini_kstats(bgep); 3862 bgep->progress &= ~PROGRESS_KSTATS; 3863 } 3864 if (bgep->progress & PROGRESS_INTR) { 3865 bge_intr_disable(bgep); 3866 rw_enter(bgep->errlock, RW_WRITER); 3867 bge_fini_rings(bgep); 3868 rw_exit(bgep->errlock); 3869 bgep->progress &= ~PROGRESS_INTR; 3870 } 3871 if (bgep->progress & PROGRESS_BUFS) { 3872 bge_free_bufs(bgep); 3873 bgep->progress &= ~PROGRESS_BUFS; 3874 } 3875 bgep->bge_dma_error = B_FALSE; 3876 } 3877 } 3878 } else 3879 bgep->bge_chip_state = BGE_CHIP_STOPPED; 3880 } 3881 3882 /* 3883 * Poll for completion of chip's ROM firmware; also, at least on the 3884 * first time through, find and return the hardware MAC address, if any. 3885 */ 3886 static uint64_t bge_poll_firmware(bge_t *bgep); 3887 #pragma no_inline(bge_poll_firmware) 3888 3889 static uint64_t 3890 bge_poll_firmware(bge_t *bgep) 3891 { 3892 uint64_t magic; 3893 uint64_t mac; 3894 uint32_t gen, val; 3895 uint32_t i; 3896 3897 /* 3898 * Step 19: poll for firmware completion (GENCOMM port set 3899 * to the ones complement of T3_MAGIC_NUMBER). 3900 * 3901 * While we're at it, we also read the MAC address register; 3902 * at some stage the firmware will load this with the 3903 * factory-set value. 3904 * 3905 * When both the magic number and the MAC address are set, 3906 * we're done; but we impose a time limit of one second 3907 * (1000*1000us) in case the firmware fails in some fashion 3908 * or the SEEPROM that provides that MAC address isn't fitted. 3909 * 3910 * After the first time through (chip state != INITIAL), we 3911 * don't need the MAC address to be set (we've already got it 3912 * or not, from the first time), so we don't wait for it, but 3913 * we still have to wait for the T3_MAGIC_NUMBER. 3914 * 3915 * Note: the magic number is only a 32-bit quantity, but the NIC 3916 * memory is 64-bit (and big-endian) internally. Addressing the 3917 * GENCOMM word as "the upper half of a 64-bit quantity" makes 3918 * it work correctly on both big- and little-endian hosts. 3919 */ 3920 if (MHCR_CHIP_ASIC_REV(bgep) == MHCR_CHIP_ASIC_REV_5906) { 3921 for (i = 0; i < 1000; ++i) { 3922 drv_usecwait(1000); 3923 val = bge_reg_get32(bgep, VCPU_STATUS_REG); 3924 if (val & VCPU_INIT_DONE) 3925 break; 3926 } 3927 BGE_DEBUG(("bge_poll_firmware($%p): return after %d loops", 3928 (void *)bgep, i)); 3929 mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0)); 3930 } else { 3931 for (i = 0; i < 1000; ++i) { 3932 drv_usecwait(1000); 3933 gen = bge_nic_get64(bgep, NIC_MEM_GENCOMM) >> 32; 3934 if (i == 0 && DEVICE_5704_SERIES_CHIPSETS(bgep)) 3935 drv_usecwait(100000); 3936 mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0)); 3937 #ifdef BGE_IPMI_ASF 3938 if (!bgep->asf_enabled) { 3939 #endif 3940 if (gen != ~T3_MAGIC_NUMBER) 3941 continue; 3942 #ifdef BGE_IPMI_ASF 3943 } 3944 #endif 3945 if (mac != 0ULL) 3946 break; 3947 if (bgep->bge_chip_state != BGE_CHIP_INITIAL) 3948 break; 3949 } 3950 } 3951 3952 magic = bge_nic_get64(bgep, NIC_MEM_GENCOMM); 3953 BGE_DEBUG(("bge_poll_firmware($%p): PXE magic 0x%x after %d loops", 3954 (void *)bgep, gen, i)); 3955 BGE_DEBUG(("bge_poll_firmware: MAC %016llx, GENCOMM %016llx", 3956 mac, magic)); 3957 3958 return (mac); 3959 } 3960 3961 /* 3962 * Maximum times of trying to get the NVRAM access lock 3963 * by calling bge_nvmem_acquire() 3964 */ 3965 #define MAX_TRY_NVMEM_ACQUIRE 10000 3966 3967 #ifdef BGE_IPMI_ASF 3968 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode); 3969 #else 3970 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma); 3971 #endif 3972 #pragma no_inline(bge_chip_reset) 3973 3974 int 3975 #ifdef BGE_IPMI_ASF 3976 bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode) 3977 #else 3978 bge_chip_reset(bge_t *bgep, boolean_t enable_dma) 3979 #endif 3980 { 3981 chip_id_t chipid; 3982 uint64_t mac; 3983 uint64_t magic; 3984 uint32_t tmp; 3985 uint32_t mhcr_base; 3986 uint32_t mhcr; 3987 uint32_t sx0; 3988 uint32_t i, tries; 3989 #ifdef BGE_IPMI_ASF 3990 uint32_t mailbox; 3991 #endif 3992 int retval = DDI_SUCCESS; 3993 3994 BGE_TRACE(("bge_chip_reset($%p, %d)", 3995 (void *)bgep, enable_dma)); 3996 3997 ASSERT(mutex_owned(bgep->genlock)); 3998 3999 BGE_DEBUG(("bge_chip_reset($%p, %d): current state is %d", 4000 (void *)bgep, enable_dma, bgep->bge_chip_state)); 4001 4002 /* 4003 * Do we need to stop the chip cleanly before resetting? 4004 */ 4005 switch (bgep->bge_chip_state) { 4006 default: 4007 _NOTE(NOTREACHED) 4008 return (DDI_FAILURE); 4009 4010 case BGE_CHIP_INITIAL: 4011 case BGE_CHIP_STOPPED: 4012 case BGE_CHIP_RESET: 4013 break; 4014 4015 case BGE_CHIP_RUNNING: 4016 case BGE_CHIP_ERROR: 4017 case BGE_CHIP_FAULT: 4018 bge_chip_stop(bgep, B_FALSE); 4019 break; 4020 } 4021 4022 mhcr_base = MHCR_ENABLE_INDIRECT_ACCESS | 4023 MHCR_ENABLE_PCI_STATE_RW | 4024 MHCR_ENABLE_TAGGED_STATUS_MODE | 4025 MHCR_MASK_INTERRUPT_MODE | 4026 MHCR_MASK_PCI_INT_OUTPUT | 4027 MHCR_CLEAR_INTERRUPT_INTA; 4028 4029 #ifdef BGE_IPMI_ASF 4030 if (bgep->asf_enabled) { 4031 mhcr = mhcr_base; 4032 #ifdef _BIG_ENDIAN 4033 mhcr |= (MHCR_ENABLE_ENDIAN_WORD_SWAP | 4034 MHCR_ENABLE_ENDIAN_BYTE_SWAP); 4035 #endif 4036 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr); 4037 4038 bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG, 4039 bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG) | 4040 MEMORY_ARBITER_ENABLE); 4041 4042 if (asf_mode == ASF_MODE_INIT) { 4043 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 4044 } else if (asf_mode == ASF_MODE_SHUTDOWN) { 4045 bge_asf_pre_reset_operations(bgep, BGE_SHUTDOWN_RESET); 4046 } 4047 } 4048 #endif 4049 4050 /* 4051 * Adapted from Broadcom document 570X-PG102-R, pp 102-116. 4052 * Updated to reflect Broadcom document 570X-PG104-R, pp 146-159. 4053 * 4054 * Before reset Core clock,it is 4055 * also required to initialize the Memory Arbiter as specified in step9 4056 * and Misc Host Control Register as specified in step-13 4057 * Step 4-5: reset Core clock & wait for completion 4058 * Steps 6-8: are done by bge_chip_cfg_init() 4059 * put the T3_MAGIC_NUMBER into the GENCOMM port before reset 4060 */ 4061 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 4062 retval = DDI_FAILURE; 4063 4064 mhcr = mhcr_base; 4065 #ifdef _BIG_ENDIAN 4066 mhcr |= (MHCR_ENABLE_ENDIAN_WORD_SWAP | 4067 MHCR_ENABLE_ENDIAN_BYTE_SWAP); 4068 #endif 4069 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr); 4070 4071 #ifdef BGE_IPMI_ASF 4072 if (bgep->asf_enabled) 4073 bgep->asf_wordswapped = B_FALSE; 4074 #endif 4075 /* 4076 * NVRAM Corruption Workaround 4077 */ 4078 for (tries = 0; tries < MAX_TRY_NVMEM_ACQUIRE; tries++) 4079 if (bge_nvmem_acquire(bgep) != EAGAIN) 4080 break; 4081 if (tries >= MAX_TRY_NVMEM_ACQUIRE) 4082 BGE_DEBUG(("%s: fail to acquire nvram lock", 4083 bgep->ifname)); 4084 4085 bge_ape_lock(bgep, BGE_APE_LOCK_GRC); 4086 4087 #ifdef BGE_IPMI_ASF 4088 if (!bgep->asf_enabled) { 4089 #endif 4090 magic = (uint64_t)T3_MAGIC_NUMBER << 32; 4091 bge_nic_put64(bgep, NIC_MEM_GENCOMM, magic); 4092 #ifdef BGE_IPMI_ASF 4093 } 4094 #endif 4095 4096 if (DEVICE_5717_SERIES_CHIPSETS(bgep) || 4097 DEVICE_5725_SERIES_CHIPSETS(bgep) || 4098 DEVICE_57765_SERIES_CHIPSETS(bgep)) { 4099 bge_reg_set32(bgep, FAST_BOOT_PC, 0); 4100 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 4101 retval = DDI_FAILURE; 4102 } 4103 4104 mhcr = mhcr_base; 4105 #ifdef _BIG_ENDIAN 4106 mhcr |= (MHCR_ENABLE_ENDIAN_WORD_SWAP | 4107 MHCR_ENABLE_ENDIAN_BYTE_SWAP); 4108 #endif 4109 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr); 4110 4111 if (!bge_chip_reset_engine(bgep, MISC_CONFIG_REG)) 4112 retval = DDI_FAILURE; 4113 4114 bge_chip_cfg_init(bgep, &chipid, enable_dma); 4115 4116 /* 4117 * Step 8a: This may belong elsewhere, but BCM5721 needs 4118 * a bit set to avoid a fifo overflow/underflow bug. 4119 */ 4120 if ((bgep->chipid.chip_label == 5721) || 4121 (bgep->chipid.chip_label == 5751) || 4122 (bgep->chipid.chip_label == 5752) || 4123 (bgep->chipid.chip_label == 5755) || 4124 (bgep->chipid.chip_label == 5756) || 4125 (bgep->chipid.chip_label == 5789) || 4126 (bgep->chipid.chip_label == 5906)) 4127 bge_reg_set32(bgep, TLP_CONTROL_REG, TLP_DATA_FIFO_PROTECT); 4128 4129 /* 4130 * In the 57765 family of devices we need to work around an apparent 4131 * transmit hang by dorking with the PCIe serdes training clocks. 4132 */ 4133 if (DEVICE_57765_SERIES_CHIPSETS(bgep) && 4134 (CHIP_ASIC_REV_PROD_ID(bgep) >> 8) != CHIP_ASIC_REV_57765_AX) { 4135 tmp = bge_reg_get32(bgep, CPMU_PADRNG_CTL_REG); 4136 tmp |= CPMU_PADRNG_CTL_RDIV2; 4137 bge_reg_set32(bgep, CPMU_PADRNG_CTL_REG, tmp); 4138 } 4139 4140 4141 /* 4142 * Step 9: enable MAC memory arbiter,bit30 and bit31 of 5714/5715 should 4143 * not be changed. 4144 */ 4145 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 4146 retval = DDI_FAILURE; 4147 4148 /* 4149 * Steps 10-11: configure PIO endianness options and 4150 * enable indirect register access -- already done 4151 * Steps 12-13: enable writing to the PCI state & clock 4152 * control registers -- not required; we aren't going to 4153 * use those features. 4154 * Steps 14-15: Configure DMA endianness options. See 4155 * the comments on the setting of the MHCR above. 4156 */ 4157 tmp = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME; 4158 #ifdef _BIG_ENDIAN 4159 tmp |= (MODE_WORD_SWAP_NONFRAME | MODE_BYTE_SWAP_NONFRAME); 4160 #endif 4161 #ifdef BGE_IPMI_ASF 4162 if (bgep->asf_enabled) 4163 tmp |= MODE_HOST_STACK_UP; 4164 #endif 4165 bge_reg_put32(bgep, MODE_CONTROL_REG, tmp); 4166 4167 #ifdef BGE_IPMI_ASF 4168 if (bgep->asf_enabled) { 4169 #ifdef __sparc 4170 bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG, 4171 MEMORY_ARBITER_ENABLE | 4172 bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG)); 4173 #endif 4174 4175 #ifdef BGE_NETCONSOLE 4176 if (!bgep->asf_newhandshake) { 4177 if ((asf_mode == ASF_MODE_INIT) || 4178 (asf_mode == ASF_MODE_POST_INIT)) { 4179 bge_asf_post_reset_old_mode(bgep, 4180 BGE_INIT_RESET); 4181 } else { 4182 bge_asf_post_reset_old_mode(bgep, 4183 BGE_SHUTDOWN_RESET); 4184 } 4185 } 4186 #endif 4187 4188 /* Wait for NVRAM init */ 4189 i = 0; 4190 drv_usecwait(5000); 4191 mailbox = bge_nic_get32(bgep, BGE_FIRMWARE_MAILBOX); 4192 4193 while ((mailbox != (uint32_t) 4194 ~BGE_MAGIC_NUM_FIRMWARE_INIT_DONE) && 4195 (i < 10000)) { 4196 drv_usecwait(100); 4197 mailbox = bge_nic_get32(bgep, 4198 BGE_FIRMWARE_MAILBOX); 4199 i++; 4200 } 4201 4202 #ifndef BGE_NETCONSOLE 4203 if (!bgep->asf_newhandshake) { 4204 if ((asf_mode == ASF_MODE_INIT) || 4205 (asf_mode == ASF_MODE_POST_INIT)) { 4206 4207 bge_asf_post_reset_old_mode(bgep, 4208 BGE_INIT_RESET); 4209 } else { 4210 bge_asf_post_reset_old_mode(bgep, 4211 BGE_SHUTDOWN_RESET); 4212 } 4213 } 4214 #endif 4215 } 4216 #endif 4217 4218 bge_ape_unlock(bgep, BGE_APE_LOCK_GRC); 4219 4220 /* 4221 * Steps 16-17: poll for firmware completion 4222 */ 4223 mac = bge_poll_firmware(bgep); 4224 4225 if (bgep->chipid.device == DEVICE_ID_5720) { 4226 tmp = bge_reg_get32(bgep, CPMU_CLCK_ORIDE_REG); 4227 bge_reg_put32(bgep, CPMU_CLCK_ORIDE_REG, 4228 (tmp & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN)); 4229 } 4230 4231 /* 4232 * Step 18: enable external memory -- doesn't apply. 4233 * 4234 * However we take the opportunity to set the MLCR anyway, as 4235 * this register also controls the SEEPROM auto-access method 4236 * which we may want to use later ... 4237 * 4238 * The proper value here depends on the way the chip is wired 4239 * into the circuit board, as this register *also* controls which 4240 * of the "Miscellaneous I/O" pins are driven as outputs and the 4241 * values driven onto those pins! 4242 * 4243 * See also step 74 in the PRM ... 4244 */ 4245 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, 4246 bgep->chipid.bge_mlcr_default); 4247 4248 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 4249 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 4250 tmp = bge_reg_get32(bgep, SERDES_RX_CONTROL); 4251 tmp |= SERDES_RX_CONTROL_SIG_DETECT; 4252 bge_reg_put32(bgep, SERDES_RX_CONTROL, tmp); 4253 } 4254 4255 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 4256 4257 /* 4258 * Step 20: clear the Ethernet MAC mode register 4259 */ 4260 if (bgep->ape_enabled) 4261 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, 4262 ETHERNET_MODE_APE_TX_EN | ETHERNET_MODE_APE_RX_EN); 4263 else 4264 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, 0); 4265 4266 /* 4267 * Step 21: restore cache-line-size, latency timer, and 4268 * subsystem ID registers to their original values (not 4269 * those read into the local structure <chipid>, 'cos 4270 * that was after they were cleared by the RESET). 4271 * 4272 * Note: the Subsystem Vendor/Device ID registers are not 4273 * directly writable in config space, so we use the shadow 4274 * copy in "Page Zero" of register space to restore them 4275 * both in one go ... 4276 */ 4277 pci_config_put8(bgep->cfg_handle, PCI_CONF_CACHE_LINESZ, 4278 bgep->chipid.clsize); 4279 pci_config_put8(bgep->cfg_handle, PCI_CONF_LATENCY_TIMER, 4280 bgep->chipid.latency); 4281 bge_reg_put32(bgep, PCI_CONF_SUBVENID, 4282 (bgep->chipid.subdev << 16) | bgep->chipid.subven); 4283 4284 /* 4285 * The SEND INDEX registers should be reset to zero by the 4286 * global chip reset; if they're not, there'll be trouble 4287 * later on. 4288 */ 4289 sx0 = bge_reg_get32(bgep, NIC_DIAG_SEND_INDEX_REG(0)); 4290 if (sx0 != 0) { 4291 BGE_REPORT((bgep, "SEND INDEX - device didn't RESET")); 4292 bge_fm_ereport(bgep, DDI_FM_DEVICE_INVAL_STATE); 4293 retval = DDI_FAILURE; 4294 } 4295 4296 /* Enable MSI code */ 4297 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 4298 bge_reg_set32(bgep, MSI_MODE_REG, 4299 MSI_PRI_HIGHEST|MSI_MSI_ENABLE|MSI_ERROR_ATTENTION); 4300 4301 /* 4302 * On the first time through, save the factory-set MAC address 4303 * (if any). If bge_poll_firmware() above didn't return one 4304 * (from a chip register) consider looking in the attached NV 4305 * memory device, if any. Once we have it, we save it in both 4306 * register-image (64-bit) and byte-array forms. All-zero and 4307 * all-one addresses are not valid, and we refuse to stash those. 4308 */ 4309 if (bgep->bge_chip_state == BGE_CHIP_INITIAL) { 4310 if (mac == 0ULL) 4311 mac = bge_get_nvmac(bgep); 4312 if (mac != 0ULL && mac != ~0ULL) { 4313 bgep->chipid.hw_mac_addr = mac; 4314 for (i = ETHERADDRL; i-- != 0; ) { 4315 bgep->chipid.vendor_addr.addr[i] = (uchar_t)mac; 4316 mac >>= 8; 4317 } 4318 bgep->chipid.vendor_addr.set = B_TRUE; 4319 } 4320 } 4321 4322 #ifdef BGE_IPMI_ASF 4323 if (bgep->asf_enabled && bgep->asf_newhandshake) { 4324 if (asf_mode != ASF_MODE_NONE) { 4325 if ((asf_mode == ASF_MODE_INIT) || 4326 (asf_mode == ASF_MODE_POST_INIT)) { 4327 4328 bge_asf_post_reset_new_mode(bgep, 4329 BGE_INIT_RESET); 4330 } else { 4331 bge_asf_post_reset_new_mode(bgep, 4332 BGE_SHUTDOWN_RESET); 4333 } 4334 } 4335 } 4336 #endif 4337 4338 /* 4339 * Record the new state 4340 */ 4341 bgep->chip_resets += 1; 4342 bgep->bge_chip_state = BGE_CHIP_RESET; 4343 return (retval); 4344 } 4345 4346 /* 4347 * bge_chip_start() -- start the chip transmitting and/or receiving, 4348 * including enabling interrupts 4349 */ 4350 int bge_chip_start(bge_t *bgep, boolean_t reset_phys); 4351 #pragma no_inline(bge_chip_start) 4352 4353 void 4354 bge_chip_coalesce_update(bge_t *bgep) 4355 { 4356 bge_reg_put32(bgep, SEND_COALESCE_MAX_BD_REG, 4357 bgep->chipid.tx_count_norm); 4358 bge_reg_put32(bgep, SEND_COALESCE_TICKS_REG, 4359 bgep->chipid.tx_ticks_norm); 4360 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, 4361 bgep->chipid.rx_count_norm); 4362 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, 4363 bgep->chipid.rx_ticks_norm); 4364 } 4365 4366 int 4367 bge_chip_start(bge_t *bgep, boolean_t reset_phys) 4368 { 4369 uint32_t coalmode; 4370 uint32_t ledctl; 4371 uint32_t mtu; 4372 uint32_t maxring; 4373 uint32_t stats_mask; 4374 uint32_t dma_wrprio; 4375 uint64_t ring; 4376 uint32_t reg; 4377 uint32_t regval; 4378 uint32_t mhcr; 4379 int retval = DDI_SUCCESS; 4380 int i; 4381 4382 BGE_TRACE(("bge_chip_start($%p)", 4383 (void *)bgep)); 4384 4385 ASSERT(mutex_owned(bgep->genlock)); 4386 ASSERT(bgep->bge_chip_state == BGE_CHIP_RESET); 4387 4388 /* Initialize EEE, enable MAC control of LPI */ 4389 bge_eee_init(bgep); 4390 4391 if (bgep->ape_enabled) { 4392 /* 4393 * Allow reads and writes to the 4394 * APE register and memory space. 4395 */ 4396 regval = pci_config_get32(bgep->cfg_handle, 4397 PCI_CONF_BGE_PCISTATE); 4398 regval |= PCISTATE_ALLOW_APE_CTLSPC_WR | 4399 PCISTATE_ALLOW_APE_SHMEM_WR | PCISTATE_ALLOW_APE_PSPACE_WR; 4400 pci_config_put32(bgep->cfg_handle, 4401 PCI_CONF_BGE_PCISTATE, regval); 4402 } 4403 4404 /* 4405 * Taken from Broadcom document 570X-PG102-R, pp 102-116. 4406 * The document specifies 95 separate steps to fully 4407 * initialise the chip!!!! 4408 * 4409 * The reset code above has already got us as far as step 4410 * 21, so we continue with ... 4411 * 4412 * Step 22: clear the MAC statistics block 4413 * (0x0300-0x0aff in NIC-local memory) 4414 */ 4415 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 4416 bge_nic_zero(bgep, NIC_MEM_STATISTICS, 4417 NIC_MEM_STATISTICS_SIZE); 4418 4419 /* 4420 * Step 23: clear the status block (in host memory) 4421 */ 4422 DMA_ZERO(bgep->status_block); 4423 4424 /* 4425 * Step 24: set DMA read/write control register 4426 */ 4427 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_PDRWCR, 4428 bgep->chipid.bge_dma_rwctrl); 4429 4430 /* 4431 * Step 25: Configure DMA endianness -- already done (16/17) 4432 * Step 26: Configure Host-Based Send Rings 4433 * Step 27: Indicate Host Stack Up 4434 */ 4435 bge_reg_set32(bgep, MODE_CONTROL_REG, 4436 MODE_HOST_SEND_BDS | 4437 MODE_HOST_STACK_UP); 4438 4439 if (DEVICE_5717_SERIES_CHIPSETS(bgep) || 4440 DEVICE_5725_SERIES_CHIPSETS(bgep) || 4441 DEVICE_57765_SERIES_CHIPSETS(bgep)) { 4442 reg = (CHIP_ASIC_REV(bgep) == CHIP_ASIC_REV_5762) 4443 ? RDMA_RSRV_CTRL_REG2 : RDMA_RSRV_CTRL_REG; 4444 regval = bge_reg_get32(bgep, reg); 4445 if ((bgep->chipid.device == DEVICE_ID_5719) || 4446 (bgep->chipid.device == DEVICE_ID_5720) || 4447 (CHIP_ASIC_REV(bgep) == CHIP_ASIC_REV_5762)) { 4448 regval &= ~(RDMA_RSRV_CTRL_TXMRGN_MASK | 4449 RDMA_RSRV_CTRL_FIFO_LWM_MASK | 4450 RDMA_RSRV_CTRL_FIFO_HWM_MASK); 4451 regval |= (RDMA_RSRV_CTRL_TXMRGN_320B | 4452 RDMA_RSRV_CTRL_FIFO_LWM_1_5K | 4453 RDMA_RSRV_CTRL_FIFO_HWM_1_5K); 4454 } 4455 /* Enable the DMA FIFO Overrun fix. */ 4456 bge_reg_put32(bgep, reg, 4457 (regval | RDMA_RSRV_CTRL_FIFO_OFLW_FIX)); 4458 4459 if ((CHIP_ASIC_REV(bgep) == CHIP_ASIC_REV_5719) || 4460 (CHIP_ASIC_REV(bgep) == CHIP_ASIC_REV_5720) || 4461 (CHIP_ASIC_REV(bgep) == CHIP_ASIC_REV_5762)) { 4462 reg = (CHIP_ASIC_REV(bgep) == CHIP_ASIC_REV_5762) 4463 ? RDMA_CORR_CTRL_REG2 : RDMA_CORR_CTRL_REG; 4464 regval = bge_reg_get32(bgep, reg); 4465 bge_reg_put32(bgep, reg, (regval | 4466 RDMA_CORR_CTRL_BLEN_BD_4K | 4467 RDMA_CORR_CTRL_BLEN_LSO_4K)); 4468 } 4469 } 4470 4471 /* 4472 * Step 28: Configure checksum options: 4473 * Solaris supports the hardware default checksum options. 4474 * 4475 * Workaround for Incorrect pseudo-header checksum calculation. 4476 */ 4477 if (bgep->chipid.flags & CHIP_FLAG_PARTIAL_CSUM) 4478 bge_reg_set32(bgep, MODE_CONTROL_REG, 4479 MODE_SEND_NO_PSEUDO_HDR_CSUM); 4480 4481 /* 4482 * Step 29: configure Timer Prescaler. The value is always the 4483 * same: the Core Clock frequency in MHz (66), minus 1, shifted 4484 * into bits 7-1. Don't set bit 0, 'cos that's the RESET bit 4485 * for the whole chip! 4486 */ 4487 regval = bge_reg_get32(bgep, MISC_CONFIG_REG); 4488 regval = (regval & 0xffffff00) | MISC_CONFIG_DEFAULT; 4489 bge_reg_put32(bgep, MISC_CONFIG_REG, regval); 4490 4491 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) { 4492 drv_usecwait(40); 4493 /* put PHY into ready state */ 4494 bge_reg_clr32(bgep, MISC_CONFIG_REG, MISC_CONFIG_EPHY_IDDQ); 4495 (void) bge_reg_get32(bgep, MISC_CONFIG_REG); /* flush */ 4496 drv_usecwait(40); 4497 } 4498 4499 /* 4500 * Steps 30-31: Configure MAC local memory pool & DMA pool registers 4501 * 4502 * If the mbuf_length is specified as 0, we just leave these at 4503 * their hardware defaults, rather than explicitly setting them. 4504 * As the Broadcom HRM,driver better not change the parameters 4505 * when the chipsets is 5705/5788/5721/5751/5714 and 5715. 4506 */ 4507 if ((bgep->chipid.mbuf_length != 0) && 4508 (DEVICE_5704_SERIES_CHIPSETS(bgep))) { 4509 bge_reg_put32(bgep, MBUF_POOL_BASE_REG, 4510 bgep->chipid.mbuf_base); 4511 bge_reg_put32(bgep, MBUF_POOL_LENGTH_REG, 4512 bgep->chipid.mbuf_length); 4513 bge_reg_put32(bgep, DMAD_POOL_BASE_REG, 4514 DMAD_POOL_BASE_DEFAULT); 4515 bge_reg_put32(bgep, DMAD_POOL_LENGTH_REG, 4516 DMAD_POOL_LENGTH_DEFAULT); 4517 } 4518 4519 /* 4520 * Step 32: configure MAC memory pool watermarks 4521 */ 4522 bge_reg_put32(bgep, RDMA_MBUF_LOWAT_REG, 4523 bgep->chipid.mbuf_lo_water_rdma); 4524 bge_reg_put32(bgep, MAC_RX_MBUF_LOWAT_REG, 4525 bgep->chipid.mbuf_lo_water_rmac); 4526 bge_reg_put32(bgep, MBUF_HIWAT_REG, 4527 bgep->chipid.mbuf_hi_water); 4528 4529 /* 4530 * Step 33: configure DMA resource watermarks 4531 */ 4532 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 4533 bge_reg_put32(bgep, DMAD_POOL_LOWAT_REG, 4534 bge_dmad_lo_water); 4535 bge_reg_put32(bgep, DMAD_POOL_HIWAT_REG, 4536 bge_dmad_hi_water); 4537 } 4538 bge_reg_put32(bgep, LOWAT_MAX_RECV_FRAMES_REG, bge_lowat_recv_frames); 4539 4540 /* 4541 * Steps 34-36: enable buffer manager & internal h/w queues 4542 */ 4543 regval = STATE_MACHINE_ATTN_ENABLE_BIT; 4544 if (bgep->chipid.device == DEVICE_ID_5719) 4545 regval |= BUFFER_MANAGER_MODE_NO_TX_UNDERRUN; 4546 if (DEVICE_5717_SERIES_CHIPSETS(bgep) || 4547 DEVICE_5725_SERIES_CHIPSETS(bgep) || 4548 DEVICE_57765_SERIES_CHIPSETS(bgep)) 4549 regval |= BUFFER_MANAGER_MODE_MBLOW_ATTN_ENABLE; 4550 if (!bge_chip_enable_engine(bgep, BUFFER_MANAGER_MODE_REG, regval)) 4551 retval = DDI_FAILURE; 4552 4553 if (!bge_chip_enable_engine(bgep, FTQ_RESET_REG, 0)) 4554 retval = DDI_FAILURE; 4555 4556 /* 4557 * Steps 37-39: initialise Receive Buffer (Producer) RCBs 4558 */ 4559 if (DEVICE_5717_SERIES_CHIPSETS(bgep) || 4560 DEVICE_5725_SERIES_CHIPSETS(bgep) || 4561 DEVICE_57765_SERIES_CHIPSETS(bgep)) { 4562 buff_ring_t *brp = &bgep->buff[BGE_STD_BUFF_RING]; 4563 bge_reg_put64(bgep, STD_RCV_BD_RING_RCB_REG, 4564 brp->desc.cookie.dmac_laddress); 4565 bge_reg_put32(bgep, STD_RCV_BD_RING_RCB_REG + 8, 4566 (brp->desc.nslots) << 16 | brp->buf[0].size << 2); 4567 if (DEVICE_57765_SERIES_CHIPSETS(bgep)) { 4568 bge_reg_put32(bgep, STD_RCV_BD_RING_RCB_REG + 0xc, 4569 NIC_MEM_SHADOW_BUFF_STD); 4570 } else { 4571 bge_reg_put32(bgep, STD_RCV_BD_RING_RCB_REG + 0xc, 4572 NIC_MEM_SHADOW_BUFF_STD_5717); 4573 } 4574 } else { 4575 bge_reg_putrcb(bgep, STD_RCV_BD_RING_RCB_REG, 4576 &bgep->buff[BGE_STD_BUFF_RING].hw_rcb); 4577 } 4578 4579 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 4580 bge_reg_putrcb(bgep, JUMBO_RCV_BD_RING_RCB_REG, 4581 &bgep->buff[BGE_JUMBO_BUFF_RING].hw_rcb); 4582 bge_reg_putrcb(bgep, MINI_RCV_BD_RING_RCB_REG, 4583 &bgep->buff[BGE_MINI_BUFF_RING].hw_rcb); 4584 } 4585 4586 /* 4587 * Step 40: set Receive Buffer Descriptor Ring replenish thresholds 4588 */ 4589 bge_reg_put32(bgep, STD_RCV_BD_REPLENISH_REG, bge_replenish_std); 4590 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 4591 bge_reg_put32(bgep, JUMBO_RCV_BD_REPLENISH_REG, 4592 bge_replenish_jumbo); 4593 bge_reg_put32(bgep, MINI_RCV_BD_REPLENISH_REG, 4594 bge_replenish_mini); 4595 } 4596 4597 /* 4598 * Steps 41-43: clear Send Ring Producer Indices and initialise 4599 * Send Producer Rings (0x0100-0x01ff in NIC-local memory) 4600 */ 4601 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4602 maxring = BGE_SEND_RINGS_MAX; 4603 else 4604 maxring = BGE_SEND_RINGS_MAX_5705; 4605 for (ring = 0; ring < maxring; ++ring) { 4606 bge_mbx_put(bgep, SEND_RING_HOST_INDEX_REG(ring), 0); 4607 bge_mbx_put(bgep, SEND_RING_NIC_INDEX_REG(ring), 0); 4608 bge_nic_putrcb(bgep, NIC_MEM_SEND_RING(ring), 4609 &bgep->send[ring].hw_rcb); 4610 } 4611 4612 /* 4613 * Steps 44-45: initialise Receive Return Rings 4614 * (0x0200-0x02ff in NIC-local memory) 4615 */ 4616 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4617 maxring = BGE_RECV_RINGS_MAX; 4618 else 4619 maxring = BGE_RECV_RINGS_MAX_5705; 4620 for (ring = 0; ring < maxring; ++ring) 4621 bge_nic_putrcb(bgep, NIC_MEM_RECV_RING(ring), 4622 &bgep->recv[ring].hw_rcb); 4623 4624 /* 4625 * Step 46: initialise Receive Buffer (Producer) Ring indexes 4626 */ 4627 bge_mbx_put(bgep, RECV_STD_PROD_INDEX_REG, 0); 4628 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 4629 bge_mbx_put(bgep, RECV_JUMBO_PROD_INDEX_REG, 0); 4630 bge_mbx_put(bgep, RECV_MINI_PROD_INDEX_REG, 0); 4631 } 4632 /* 4633 * Step 47: configure the MAC unicast address 4634 * Step 48: configure the random backoff seed 4635 * Step 96: set up multicast filters 4636 */ 4637 #ifdef BGE_IPMI_ASF 4638 if (bge_chip_sync(bgep, B_FALSE) == DDI_FAILURE) 4639 #else 4640 if (bge_chip_sync(bgep) == DDI_FAILURE) 4641 #endif 4642 retval = DDI_FAILURE; 4643 4644 /* 4645 * Step 49: configure the MTU 4646 */ 4647 mtu = bgep->chipid.ethmax_size+ETHERFCSL+VLAN_TAGSZ; 4648 bge_reg_put32(bgep, MAC_RX_MTU_SIZE_REG, mtu); 4649 4650 /* 4651 * Step 50: configure the IPG et al 4652 */ 4653 bge_reg_put32(bgep, MAC_TX_LENGTHS_REG, MAC_TX_LENGTHS_DEFAULT); 4654 4655 /* 4656 * Step 51: configure the default Rx Return Ring 4657 */ 4658 bge_reg_put32(bgep, RCV_RULES_CONFIG_REG, RCV_RULES_CONFIG_DEFAULT); 4659 4660 /* 4661 * Steps 52-54: configure Receive List Placement, 4662 * and enable Receive List Placement Statistics 4663 */ 4664 bge_reg_put32(bgep, RCV_LP_CONFIG_REG, 4665 RCV_LP_CONFIG(bgep->chipid.rx_rings)); 4666 switch (MHCR_CHIP_ASIC_REV(bgep)) { 4667 case MHCR_CHIP_ASIC_REV_5700: 4668 case MHCR_CHIP_ASIC_REV_5701: 4669 case MHCR_CHIP_ASIC_REV_5703: 4670 case MHCR_CHIP_ASIC_REV_5704: 4671 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, ~0); 4672 break; 4673 case MHCR_CHIP_ASIC_REV_5705: 4674 break; 4675 default: 4676 stats_mask = bge_reg_get32(bgep, RCV_LP_STATS_ENABLE_MASK_REG); 4677 stats_mask &= ~RCV_LP_STATS_DISABLE_MACTQ; 4678 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, stats_mask); 4679 break; 4680 } 4681 bge_reg_set32(bgep, RCV_LP_STATS_CONTROL_REG, RCV_LP_STATS_ENABLE); 4682 4683 if (bgep->chipid.rx_rings > 1) 4684 bge_init_recv_rule(bgep); 4685 4686 /* 4687 * Steps 55-56: enable Send Data Initiator Statistics 4688 */ 4689 bge_reg_put32(bgep, SEND_INIT_STATS_ENABLE_MASK_REG, ~0); 4690 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 4691 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 4692 SEND_INIT_STATS_ENABLE | SEND_INIT_STATS_FASTER); 4693 } else { 4694 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 4695 SEND_INIT_STATS_ENABLE); 4696 } 4697 /* 4698 * Steps 57-58: stop (?) the Host Coalescing Engine 4699 */ 4700 if (!bge_chip_disable_engine(bgep, HOST_COALESCE_MODE_REG, ~0)) 4701 retval = DDI_FAILURE; 4702 4703 /* 4704 * Steps 59-62: initialise Host Coalescing parameters 4705 */ 4706 bge_chip_coalesce_update(bgep); 4707 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 4708 bge_reg_put32(bgep, SEND_COALESCE_INT_BD_REG, 4709 bge_tx_count_intr); 4710 bge_reg_put32(bgep, SEND_COALESCE_INT_TICKS_REG, 4711 bge_tx_ticks_intr); 4712 bge_reg_put32(bgep, RCV_COALESCE_INT_BD_REG, 4713 bge_rx_count_intr); 4714 bge_reg_put32(bgep, RCV_COALESCE_INT_TICKS_REG, 4715 bge_rx_ticks_intr); 4716 } 4717 4718 /* 4719 * Steps 63-64: initialise status block & statistics 4720 * host memory addresses 4721 * The statistic block does not exist in some chipsets 4722 * Step 65: initialise Statistics Coalescing Tick Counter 4723 */ 4724 bge_reg_put64(bgep, STATUS_BLOCK_HOST_ADDR_REG, 4725 bgep->status_block.cookie.dmac_laddress); 4726 4727 /* 4728 * Steps 66-67: initialise status block & statistics 4729 * NIC-local memory addresses 4730 */ 4731 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 4732 bge_reg_put64(bgep, STATISTICS_HOST_ADDR_REG, 4733 bgep->statistics.cookie.dmac_laddress); 4734 bge_reg_put32(bgep, STATISTICS_TICKS_REG, 4735 STATISTICS_TICKS_DEFAULT); 4736 bge_reg_put32(bgep, STATUS_BLOCK_BASE_ADDR_REG, 4737 NIC_MEM_STATUS_BLOCK); 4738 bge_reg_put32(bgep, STATISTICS_BASE_ADDR_REG, 4739 NIC_MEM_STATISTICS); 4740 } 4741 4742 /* 4743 * Steps 68-71: start the Host Coalescing Engine, the Receive BD 4744 * Completion Engine, the Receive List Placement Engine, and the 4745 * Receive List selector.Pay attention:0x3400 is not exist in BCM5714 4746 * and BCM5715. 4747 */ 4748 4749 if (bgep->chipid.device == DEVICE_ID_5719) { 4750 for (i = 0; i < BGE_NUM_RDMA_CHANNELS; i++) { 4751 if (bge_reg_get32(bgep, (BGE_RDMA_LENGTH + (i << 2))) > 4752 bgep->chipid.default_mtu) 4753 break; 4754 } 4755 if (i < BGE_NUM_RDMA_CHANNELS) { 4756 regval = bge_reg_get32(bgep, RDMA_CORR_CTRL_REG); 4757 regval |= RDMA_CORR_CTRL_TX_LENGTH_WA; 4758 bge_reg_put32(bgep, RDMA_CORR_CTRL_REG, regval); 4759 bgep->rdma_length_bug_on_5719 = B_TRUE; 4760 } 4761 } 4762 4763 if (bgep->chipid.tx_rings <= COALESCE_64_BYTE_RINGS && 4764 bgep->chipid.rx_rings <= COALESCE_64_BYTE_RINGS) 4765 coalmode = COALESCE_64_BYTE_STATUS; 4766 else 4767 coalmode = 0; 4768 if (DEVICE_5717_SERIES_CHIPSETS(bgep) || 4769 DEVICE_5725_SERIES_CHIPSETS(bgep) || 4770 DEVICE_57765_SERIES_CHIPSETS(bgep)) 4771 coalmode = COALESCE_CLR_TICKS_RX; 4772 if (!bge_chip_enable_engine(bgep, HOST_COALESCE_MODE_REG, coalmode)) 4773 retval = DDI_FAILURE; 4774 if (!bge_chip_enable_engine(bgep, RCV_BD_COMPLETION_MODE_REG, 4775 STATE_MACHINE_ATTN_ENABLE_BIT)) 4776 retval = DDI_FAILURE; 4777 if (!bge_chip_enable_engine(bgep, RCV_LIST_PLACEMENT_MODE_REG, 0)) 4778 retval = DDI_FAILURE; 4779 4780 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4781 if (!bge_chip_enable_engine(bgep, RCV_LIST_SELECTOR_MODE_REG, 4782 STATE_MACHINE_ATTN_ENABLE_BIT)) 4783 retval = DDI_FAILURE; 4784 4785 /* 4786 * Step 72: Enable MAC DMA engines 4787 * Step 73: Clear & enable MAC statistics 4788 */ 4789 if (bgep->ape_enabled) { 4790 /* XXX put32 instead of set32 ? */ 4791 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, 4792 ETHERNET_MODE_APE_TX_EN | ETHERNET_MODE_APE_RX_EN); 4793 } 4794 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 4795 ETHERNET_MODE_ENABLE_FHDE | 4796 ETHERNET_MODE_ENABLE_RDE | 4797 ETHERNET_MODE_ENABLE_TDE); 4798 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 4799 ETHERNET_MODE_ENABLE_TX_STATS | 4800 ETHERNET_MODE_ENABLE_RX_STATS | 4801 ETHERNET_MODE_CLEAR_TX_STATS | 4802 ETHERNET_MODE_CLEAR_RX_STATS); 4803 4804 drv_usecwait(140); 4805 4806 if (bgep->ape_enabled) { 4807 /* Write our heartbeat update interval to APE. */ 4808 bge_ape_put32(bgep, BGE_APE_HOST_HEARTBEAT_INT_MS, 4809 APE_HOST_HEARTBEAT_INT_DISABLE); 4810 } 4811 4812 /* 4813 * Step 74: configure the MLCR (Miscellaneous Local Control 4814 * Register); not required, as we set up the MLCR in step 10 4815 * (part of the reset code) above. 4816 * 4817 * Step 75: clear Interrupt Mailbox 0 4818 */ 4819 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 0); 4820 4821 /* 4822 * Steps 76-87: Gentlemen, start your engines ... 4823 * 4824 * Enable the DMA Completion Engine, the Write DMA Engine, 4825 * the Read DMA Engine, Receive Data Completion Engine, 4826 * the MBuf Cluster Free Engine, the Send Data Completion Engine, 4827 * the Send BD Completion Engine, the Receive BD Initiator Engine, 4828 * the Receive Data Initiator Engine, the Send Data Initiator Engine, 4829 * the Send BD Initiator Engine, and the Send BD Selector Engine. 4830 * 4831 * Beware exhaust fumes? 4832 */ 4833 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4834 if (!bge_chip_enable_engine(bgep, DMA_COMPLETION_MODE_REG, 0)) 4835 retval = DDI_FAILURE; 4836 dma_wrprio = (bge_dma_wrprio << DMA_PRIORITY_SHIFT) | 4837 ALL_DMA_ATTN_BITS; 4838 /* the 5723 check here covers all newer chip families (OK) */ 4839 if ((MHCR_CHIP_ASIC_REV(bgep) == MHCR_CHIP_ASIC_REV_5755) || 4840 (MHCR_CHIP_ASIC_REV(bgep) == MHCR_CHIP_ASIC_REV_5723) || 4841 (MHCR_CHIP_ASIC_REV(bgep) == MHCR_CHIP_ASIC_REV_5906)) { 4842 dma_wrprio |= DMA_STATUS_TAG_FIX_CQ12384; 4843 } 4844 if (!bge_chip_enable_engine(bgep, WRITE_DMA_MODE_REG, 4845 dma_wrprio)) 4846 retval = DDI_FAILURE; 4847 4848 drv_usecwait(40); 4849 4850 /* 4851 * These chipsets no longer use the rdprio logic (bits 31:30 are 4852 * reserved). 4853 */ 4854 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || 4855 DEVICE_5717_SERIES_CHIPSETS(bgep) || 4856 DEVICE_5725_SERIES_CHIPSETS(bgep)) 4857 bge_dma_rdprio = 0; 4858 if (!bge_chip_enable_engine(bgep, READ_DMA_MODE_REG, 4859 (bge_dma_rdprio << DMA_PRIORITY_SHIFT) | ALL_DMA_ATTN_BITS)) 4860 retval = DDI_FAILURE; 4861 4862 drv_usecwait(40); 4863 4864 if (!bge_chip_enable_engine(bgep, RCV_DATA_COMPLETION_MODE_REG, 4865 STATE_MACHINE_ATTN_ENABLE_BIT)) 4866 retval = DDI_FAILURE; 4867 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4868 if (!bge_chip_enable_engine(bgep, 4869 MBUF_CLUSTER_FREE_MODE_REG, 0)) 4870 retval = DDI_FAILURE; 4871 if (!bge_chip_enable_engine(bgep, SEND_DATA_COMPLETION_MODE_REG, 0)) 4872 retval = DDI_FAILURE; 4873 if (!bge_chip_enable_engine(bgep, SEND_BD_COMPLETION_MODE_REG, 4874 STATE_MACHINE_ATTN_ENABLE_BIT)) 4875 retval = DDI_FAILURE; 4876 if (!bge_chip_enable_engine(bgep, RCV_BD_INITIATOR_MODE_REG, 4877 RCV_BD_DISABLED_RING_ATTN)) 4878 retval = DDI_FAILURE; 4879 if (!bge_chip_enable_engine(bgep, RCV_DATA_BD_INITIATOR_MODE_REG, 4880 RCV_DATA_BD_ILL_RING_ATTN)) 4881 retval = DDI_FAILURE; 4882 if (!bge_chip_enable_engine(bgep, SEND_DATA_INITIATOR_MODE_REG, 0)) 4883 retval = DDI_FAILURE; 4884 if (!bge_chip_enable_engine(bgep, SEND_BD_INITIATOR_MODE_REG, 4885 STATE_MACHINE_ATTN_ENABLE_BIT)) 4886 retval = DDI_FAILURE; 4887 if (!bge_chip_enable_engine(bgep, SEND_BD_SELECTOR_MODE_REG, 4888 STATE_MACHINE_ATTN_ENABLE_BIT)) 4889 retval = DDI_FAILURE; 4890 4891 drv_usecwait(40); 4892 4893 /* 4894 * Step 88: download firmware -- doesn't apply 4895 * Steps 89-90: enable Transmit & Receive MAC Engines 4896 */ 4897 regval = 0; 4898 if (DEVICE_5717_SERIES_CHIPSETS(bgep) || 4899 DEVICE_57765_SERIES_CHIPSETS(bgep)) { 4900 regval |= TRANSMIT_MODE_MBUF_LOCKUP_FIX; 4901 } 4902 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, regval)) 4903 retval = DDI_FAILURE; 4904 4905 drv_usecwait(100); 4906 4907 #ifdef BGE_IPMI_ASF 4908 if (!bgep->asf_enabled) { 4909 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 4910 RECEIVE_MODE_KEEP_VLAN_TAG)) 4911 retval = DDI_FAILURE; 4912 } else { 4913 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 0)) 4914 retval = DDI_FAILURE; 4915 } 4916 #else 4917 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 4918 RECEIVE_MODE_KEEP_VLAN_TAG)) 4919 retval = DDI_FAILURE; 4920 #endif 4921 4922 drv_usecwait(100); 4923 4924 /* 4925 * Step 91: disable auto-polling of PHY status 4926 */ 4927 bge_reg_put32(bgep, MI_MODE_REG, MI_MODE_DEFAULT); 4928 4929 /* 4930 * Step 92: configure D0 power state (not required) 4931 * Step 93: initialise LED control register () 4932 */ 4933 ledctl = LED_CONTROL_DEFAULT; 4934 switch (bgep->chipid.device) { 4935 case DEVICE_ID_5700: 4936 case DEVICE_ID_5700x: 4937 case DEVICE_ID_5701: 4938 /* 4939 * Switch to 5700 (MAC) mode on these older chips 4940 */ 4941 ledctl &= ~LED_CONTROL_LED_MODE_MASK; 4942 ledctl |= LED_CONTROL_LED_MODE_5700; 4943 break; 4944 4945 default: 4946 break; 4947 } 4948 bge_reg_put32(bgep, ETHERNET_MAC_LED_CONTROL_REG, ledctl); 4949 4950 /* 4951 * Step 94: activate link 4952 */ 4953 bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK); 4954 4955 /* 4956 * Step 95: set up physical layer (PHY/SerDes) 4957 * restart autoneg (if required) 4958 */ 4959 if (reset_phys) 4960 { 4961 if (bge_phys_update(bgep) == DDI_FAILURE) 4962 retval = DDI_FAILURE; 4963 /* forcing a mac link update here */ 4964 bge_phys_check(bgep); 4965 bgep->link_state = (bgep->param_link_up) ? LINK_STATE_UP : 4966 LINK_STATE_DOWN; 4967 bge_sync_mac_modes(bgep); 4968 mac_link_update(bgep->mh, bgep->link_state); 4969 } 4970 4971 /* 4972 * Extra step (DSG): hand over all the Receive Buffers to the chip 4973 */ 4974 for (ring = 0; ring < BGE_BUFF_RINGS_USED; ++ring) 4975 bge_mbx_put(bgep, bgep->buff[ring].chip_mbx_reg, 4976 bgep->buff[ring].rf_next); 4977 4978 /* 4979 * MSI bits:The least significant MSI 16-bit word. 4980 * ISR will be triggered different. 4981 */ 4982 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 4983 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 0x70); 4984 4985 /* 4986 * Extra step (DSG): select which interrupts are enabled 4987 * 4988 * Program the Ethernet MAC engine to signal attention on 4989 * Link Change events, then enable interrupts on MAC, DMA, 4990 * and FLOW attention signals. 4991 */ 4992 bge_reg_set32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 4993 ETHERNET_EVENT_LINK_INT | 4994 ETHERNET_STATUS_PCS_ERROR_INT); 4995 #ifdef BGE_IPMI_ASF 4996 if (bgep->asf_enabled) { 4997 bge_reg_set32(bgep, MODE_CONTROL_REG, 4998 MODE_INT_ON_FLOW_ATTN | 4999 MODE_INT_ON_DMA_ATTN | 5000 MODE_HOST_STACK_UP| 5001 MODE_INT_ON_MAC_ATTN); 5002 } else { 5003 #endif 5004 bge_reg_set32(bgep, MODE_CONTROL_REG, 5005 MODE_INT_ON_FLOW_ATTN | 5006 MODE_INT_ON_DMA_ATTN | 5007 MODE_INT_ON_MAC_ATTN); 5008 #ifdef BGE_IPMI_ASF 5009 } 5010 #endif 5011 5012 if (DEVICE_5717_SERIES_CHIPSETS(bgep) || 5013 DEVICE_5725_SERIES_CHIPSETS(bgep) || 5014 DEVICE_57765_SERIES_CHIPSETS(bgep)) { 5015 bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL_5717, 5016 DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED); 5017 #if 0 5018 mhcr = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MHCR); 5019 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, 5020 (mhcr | MHCR_TLP_MINOR_ERR_TOLERANCE)); 5021 #endif 5022 } 5023 5024 /* 5025 * Step 97: enable PCI interrupts!!! 5026 */ 5027 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 5028 bge_cfg_clr32(bgep, PCI_CONF_BGE_MHCR, 5029 bgep->chipid.mask_pci_int); 5030 5031 /* 5032 * All done! 5033 */ 5034 bgep->bge_chip_state = BGE_CHIP_RUNNING; 5035 return (retval); 5036 } 5037 5038 5039 /* 5040 * ========== Hardware interrupt handler ========== 5041 */ 5042 5043 #undef BGE_DBG 5044 #define BGE_DBG BGE_DBG_INT /* debug flag for this code */ 5045 5046 /* 5047 * Sync the status block, then atomically clear the specified bits in 5048 * the <flags-and-tag> field of the status block. 5049 * the <flags> word of the status block, returning the value of the 5050 * <tag> and the <flags> before the bits were cleared. 5051 */ 5052 static int bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags); 5053 #pragma inline(bge_status_sync) 5054 5055 static int 5056 bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags) 5057 { 5058 bge_status_t *bsp; 5059 int retval; 5060 5061 BGE_TRACE(("bge_status_sync($%p, 0x%llx)", 5062 (void *)bgep, bits)); 5063 5064 ASSERT(bgep->bge_guard == BGE_GUARD); 5065 5066 DMA_SYNC(bgep->status_block, DDI_DMA_SYNC_FORKERNEL); 5067 retval = bge_check_dma_handle(bgep, bgep->status_block.dma_hdl); 5068 if (retval != DDI_FM_OK) 5069 return (retval); 5070 5071 bsp = DMA_VPTR(bgep->status_block); 5072 *flags = bge_atomic_clr64(&bsp->flags_n_tag, bits); 5073 5074 BGE_DEBUG(("bge_status_sync($%p, 0x%llx) returning 0x%llx", 5075 (void *)bgep, bits, *flags)); 5076 5077 return (retval); 5078 } 5079 5080 void bge_wake_factotum(bge_t *bgep); 5081 #pragma inline(bge_wake_factotum) 5082 5083 void 5084 bge_wake_factotum(bge_t *bgep) 5085 { 5086 mutex_enter(bgep->softintrlock); 5087 if (bgep->factotum_flag == 0) { 5088 bgep->factotum_flag = 1; 5089 ddi_trigger_softintr(bgep->factotum_id); 5090 } 5091 mutex_exit(bgep->softintrlock); 5092 } 5093 5094 static void 5095 bge_intr_error_handler(bge_t *bgep) 5096 { 5097 uint32_t flow; 5098 uint32_t rdma; 5099 uint32_t wdma; 5100 uint32_t tmac; 5101 uint32_t rmac; 5102 uint32_t rxrs; 5103 uint32_t emac; 5104 uint32_t msis; 5105 uint32_t txrs = 0; 5106 5107 ASSERT(mutex_owned(bgep->genlock)); 5108 5109 /* 5110 * Read all the registers that show the possible 5111 * reasons for the ERROR bit to be asserted 5112 */ 5113 flow = bge_reg_get32(bgep, FLOW_ATTN_REG); 5114 rdma = bge_reg_get32(bgep, READ_DMA_STATUS_REG); 5115 wdma = bge_reg_get32(bgep, WRITE_DMA_STATUS_REG); 5116 tmac = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 5117 rmac = bge_reg_get32(bgep, RECEIVE_MAC_STATUS_REG); 5118 rxrs = bge_reg_get32(bgep, RX_RISC_STATE_REG); 5119 emac = bge_reg_get32(bgep, ETHERNET_MAC_STATUS_REG); 5120 msis = bge_reg_get32(bgep, MSI_STATUS_REG); 5121 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 5122 txrs = bge_reg_get32(bgep, TX_RISC_STATE_REG); 5123 5124 BGE_DEBUG(("factotum($%p) flow 0x%x rdma 0x%x wdma 0x%x emac 0x%x msis 0x%x", 5125 (void *)bgep, flow, rdma, wdma, emac, msis)); 5126 BGE_DEBUG(("factotum($%p) tmac 0x%x rmac 0x%x rxrs 0x%08x txrs 0x%08x", 5127 (void *)bgep, tmac, rmac, rxrs, txrs)); 5128 5129 /* 5130 * For now, just clear all the errors ... 5131 */ 5132 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 5133 bge_reg_put32(bgep, TX_RISC_STATE_REG, ~0); 5134 bge_reg_put32(bgep, RX_RISC_STATE_REG, ~0); 5135 bge_reg_put32(bgep, RECEIVE_MAC_STATUS_REG, ~0); 5136 bge_reg_put32(bgep, WRITE_DMA_STATUS_REG, ~0); 5137 bge_reg_put32(bgep, READ_DMA_STATUS_REG, ~0); 5138 bge_reg_put32(bgep, FLOW_ATTN_REG, ~0); 5139 } 5140 5141 /* 5142 * bge_intr() -- handle chip interrupts 5143 */ 5144 uint_t bge_intr(caddr_t arg1, caddr_t arg2); 5145 #pragma no_inline(bge_intr) 5146 5147 uint_t 5148 bge_intr(caddr_t arg1, caddr_t arg2) 5149 { 5150 bge_t *bgep = (void *)arg1; /* private device info */ 5151 bge_status_t *bsp; 5152 uint64_t flags; 5153 uint32_t regval; 5154 uint_t result; 5155 int retval, loop_cnt = 0; 5156 5157 BGE_TRACE(("bge_intr($%p) ($%p)", arg1, arg2)); 5158 5159 /* 5160 * GLD v2 checks that s/w setup is complete before passing 5161 * interrupts to this routine, thus eliminating the old 5162 * (and well-known) race condition around ddi_add_intr() 5163 */ 5164 ASSERT(bgep->progress & PROGRESS_HWINT); 5165 5166 result = DDI_INTR_UNCLAIMED; 5167 mutex_enter(bgep->genlock); 5168 5169 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) { 5170 /* 5171 * Check whether chip's says it's asserting #INTA; 5172 * if not, don't process or claim the interrupt. 5173 * 5174 * Note that the PCI signal is active low, so the 5175 * bit is *zero* when the interrupt is asserted. 5176 */ 5177 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 5178 if (!(DEVICE_5717_SERIES_CHIPSETS(bgep) || 5179 DEVICE_5725_SERIES_CHIPSETS(bgep) || 5180 DEVICE_57765_SERIES_CHIPSETS(bgep)) && 5181 (regval & MLCR_INTA_STATE)) { 5182 if (bge_check_acc_handle(bgep, bgep->io_handle) 5183 != DDI_FM_OK) 5184 goto chip_stop; 5185 mutex_exit(bgep->genlock); 5186 return (result); 5187 } 5188 5189 /* 5190 * Block further PCI interrupts ... 5191 */ 5192 bge_reg_set32(bgep, PCI_CONF_BGE_MHCR, 5193 bgep->chipid.mask_pci_int); 5194 5195 } else { 5196 /* 5197 * Check MSI status 5198 */ 5199 regval = bge_reg_get32(bgep, MSI_STATUS_REG); 5200 if (regval & MSI_ERROR_ATTENTION) { 5201 BGE_REPORT((bgep, "msi error attention," 5202 " status=0x%x", regval)); 5203 bge_reg_put32(bgep, MSI_STATUS_REG, regval); 5204 } 5205 } 5206 5207 result = DDI_INTR_CLAIMED; 5208 5209 BGE_DEBUG(("bge_intr($%p) ($%p) regval 0x%08x", arg1, arg2, regval)); 5210 5211 /* 5212 * Sync the status block and grab the flags-n-tag from it. 5213 * We count the number of interrupts where there doesn't 5214 * seem to have been a DMA update of the status block; if 5215 * it *has* been updated, the counter will be cleared in 5216 * the while() loop below ... 5217 */ 5218 bgep->missed_dmas += 1; 5219 bsp = DMA_VPTR(bgep->status_block); 5220 for (loop_cnt = 0; loop_cnt < bge_intr_max_loop; loop_cnt++) { 5221 if (bgep->bge_chip_state != BGE_CHIP_RUNNING) { 5222 /* 5223 * bge_chip_stop() may have freed dma area etc 5224 * while we were in this interrupt handler - 5225 * better not call bge_status_sync() 5226 */ 5227 (void) bge_check_acc_handle(bgep, 5228 bgep->io_handle); 5229 mutex_exit(bgep->genlock); 5230 return (DDI_INTR_CLAIMED); 5231 } 5232 5233 retval = bge_status_sync(bgep, STATUS_FLAG_UPDATED | 5234 STATUS_FLAG_LINK_CHANGED | STATUS_FLAG_ERROR, &flags); 5235 if (retval != DDI_FM_OK) { 5236 bgep->bge_dma_error = B_TRUE; 5237 goto chip_stop; 5238 } 5239 5240 if (!(flags & STATUS_FLAG_UPDATED)) 5241 break; 5242 5243 /* 5244 * Tell the chip that we're processing the interrupt 5245 */ 5246 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 5247 INTERRUPT_MBOX_DISABLE(flags)); 5248 if (bge_check_acc_handle(bgep, bgep->io_handle) != 5249 DDI_FM_OK) 5250 goto chip_stop; 5251 5252 if (flags & STATUS_FLAG_LINK_CHANGED) { 5253 BGE_DEBUG(("bge_intr($%p) ($%p) link event", arg1, arg2)); 5254 if (bge_phys_check(bgep)) { 5255 bgep->link_state = bgep->param_link_up ? 5256 LINK_STATE_UP : LINK_STATE_DOWN; 5257 bge_sync_mac_modes(bgep); 5258 mac_link_update(bgep->mh, bgep->link_state); 5259 } 5260 5261 if (bge_check_acc_handle(bgep, bgep->io_handle) != 5262 DDI_FM_OK) 5263 goto chip_stop; 5264 } 5265 5266 if (flags & STATUS_FLAG_ERROR) { 5267 bge_intr_error_handler(bgep); 5268 5269 if (bge_check_acc_handle(bgep, bgep->io_handle) != 5270 DDI_FM_OK) 5271 goto chip_stop; 5272 } 5273 5274 /* 5275 * Drop the mutex while we: 5276 * Receive any newly-arrived packets 5277 * Recycle any newly-finished send buffers 5278 */ 5279 bgep->bge_intr_running = B_TRUE; 5280 mutex_exit(bgep->genlock); 5281 bge_receive(bgep, bsp); 5282 (void) bge_recycle(bgep, bsp); 5283 mutex_enter(bgep->genlock); 5284 bgep->bge_intr_running = B_FALSE; 5285 5286 /* 5287 * Tell the chip we've finished processing, and 5288 * give it the tag that we got from the status 5289 * block earlier, so that it knows just how far 5290 * we've gone. If it's got more for us to do, 5291 * it will now update the status block and try 5292 * to assert an interrupt (but we've got the 5293 * #INTA blocked at present). If we see the 5294 * update, we'll loop around to do some more. 5295 * Eventually we'll get out of here ... 5296 */ 5297 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 5298 INTERRUPT_MBOX_ENABLE(flags)); 5299 if (bgep->chipid.pci_type == BGE_PCI_E) 5300 (void) bge_mbx_get(bgep, INTERRUPT_MBOX_0_REG); 5301 bgep->missed_dmas = 0; 5302 } 5303 5304 if (bgep->missed_dmas) { 5305 /* 5306 * Probably due to the internal status tag not 5307 * being reset. Force a status block update now; 5308 * this should ensure that we get an update and 5309 * a new interrupt. After that, we should be in 5310 * sync again ... 5311 */ 5312 BGE_REPORT((bgep, "interrupt: flags 0x%llx - " 5313 "not updated?", flags)); 5314 bgep->missed_updates++; 5315 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 5316 COALESCE_NOW); 5317 5318 if (bgep->missed_dmas >= bge_dma_miss_limit) { 5319 /* 5320 * If this happens multiple times in a row, 5321 * it means DMA is just not working. Maybe 5322 * the chip's failed, or maybe there's a 5323 * problem on the PCI bus or in the host-PCI 5324 * bridge (Tomatillo). 5325 * 5326 * At all events, we want to stop further 5327 * interrupts and let the recovery code take 5328 * over to see whether anything can be done 5329 * about it ... 5330 */ 5331 bge_fm_ereport(bgep, 5332 DDI_FM_DEVICE_BADINT_LIMIT); 5333 goto chip_stop; 5334 } 5335 } 5336 5337 /* 5338 * Reenable assertion of #INTA, unless there's a DMA fault 5339 */ 5340 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) { 5341 bge_reg_clr32(bgep, PCI_CONF_BGE_MHCR, 5342 bgep->chipid.mask_pci_int); 5343 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != 5344 DDI_FM_OK) 5345 goto chip_stop; 5346 } 5347 5348 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5349 goto chip_stop; 5350 5351 mutex_exit(bgep->genlock); 5352 return (result); 5353 5354 chip_stop: 5355 5356 #ifdef BGE_IPMI_ASF 5357 if (bgep->asf_enabled && bgep->asf_status == ASF_STAT_RUN) { 5358 /* 5359 * We must stop ASF heart beat before 5360 * bge_chip_stop(), otherwise some 5361 * computers (ex. IBM HS20 blade 5362 * server) may crash. 5363 */ 5364 bge_asf_update_status(bgep); 5365 bge_asf_stop_timer(bgep); 5366 bgep->asf_status = ASF_STAT_STOP; 5367 5368 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 5369 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 5370 } 5371 #endif 5372 bge_chip_stop(bgep, B_TRUE); 5373 (void) bge_check_acc_handle(bgep, bgep->io_handle); 5374 mutex_exit(bgep->genlock); 5375 return (result); 5376 } 5377 5378 /* 5379 * ========== Factotum, implemented as a softint handler ========== 5380 */ 5381 5382 #undef BGE_DBG 5383 #define BGE_DBG BGE_DBG_FACT /* debug flag for this code */ 5384 5385 /* 5386 * Factotum routine to check for Tx stall, using the 'watchdog' counter 5387 */ 5388 static boolean_t bge_factotum_stall_check(bge_t *bgep); 5389 #pragma no_inline(bge_factotum_stall_check) 5390 5391 static boolean_t 5392 bge_factotum_stall_check(bge_t *bgep) 5393 { 5394 uint32_t dogval; 5395 bge_status_t *bsp; 5396 uint64_t now = gethrtime(); 5397 5398 if ((now - bgep->timestamp) < BGE_CYCLIC_PERIOD) 5399 return (B_FALSE); 5400 5401 bgep->timestamp = now; 5402 5403 ASSERT(mutex_owned(bgep->genlock)); 5404 5405 /* 5406 * Specific check for Tx stall ... 5407 * 5408 * The 'watchdog' counter is incremented whenever a packet 5409 * is queued, reset to 1 when some (but not all) buffers 5410 * are reclaimed, reset to 0 (disabled) when all buffers 5411 * are reclaimed, and shifted left here. If it exceeds the 5412 * threshold value, the chip is assumed to have stalled and 5413 * is put into the ERROR state. The factotum will then reset 5414 * it on the next pass. 5415 * 5416 * All of which should ensure that we don't get into a state 5417 * where packets are left pending indefinitely! 5418 */ 5419 dogval = bge_atomic_shl32(&bgep->watchdog, 1); 5420 bsp = DMA_VPTR(bgep->status_block); 5421 if (dogval < bge_watchdog_count || bge_recycle(bgep, bsp)) 5422 return (B_FALSE); 5423 5424 #if !defined(BGE_NETCONSOLE) 5425 BGE_REPORT((bgep, "Tx stall detected, watchdog code 0x%x", dogval)); 5426 #endif 5427 bge_fm_ereport(bgep, DDI_FM_DEVICE_STALL); 5428 return (B_TRUE); 5429 } 5430 5431 /* 5432 * The factotum is woken up when there's something to do that we'd rather 5433 * not do from inside a hardware interrupt handler or high-level cyclic. 5434 * Its main task is to reset & restart the chip after an error. 5435 */ 5436 uint_t bge_chip_factotum(caddr_t arg); 5437 #pragma no_inline(bge_chip_factotum) 5438 5439 uint_t 5440 bge_chip_factotum(caddr_t arg) 5441 { 5442 bge_t *bgep; 5443 uint_t result; 5444 boolean_t error; 5445 int dma_state; 5446 5447 bgep = (void *)arg; 5448 5449 BGE_TRACE(("bge_chip_factotum($%p)", (void *)bgep)); 5450 5451 mutex_enter(bgep->softintrlock); 5452 if (bgep->factotum_flag == 0) { 5453 mutex_exit(bgep->softintrlock); 5454 return (DDI_INTR_UNCLAIMED); 5455 } 5456 bgep->factotum_flag = 0; 5457 mutex_exit(bgep->softintrlock); 5458 5459 result = DDI_INTR_CLAIMED; 5460 error = B_FALSE; 5461 5462 mutex_enter(bgep->genlock); 5463 switch (bgep->bge_chip_state) { 5464 default: 5465 break; 5466 5467 case BGE_CHIP_RUNNING: 5468 5469 if (bgep->chipid.device == DEVICE_ID_5700) { 5470 if (bge_phys_check(bgep)) { 5471 bgep->link_state = (bgep->param_link_up) ? 5472 LINK_STATE_UP : LINK_STATE_DOWN; 5473 bge_sync_mac_modes(bgep); 5474 mac_link_update(bgep->mh, bgep->link_state); 5475 } 5476 } 5477 5478 error = bge_factotum_stall_check(bgep); 5479 if (dma_state != DDI_FM_OK) { 5480 bgep->bge_dma_error = B_TRUE; 5481 error = B_TRUE; 5482 } 5483 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5484 error = B_TRUE; 5485 if (error) 5486 bgep->bge_chip_state = BGE_CHIP_ERROR; 5487 break; 5488 5489 case BGE_CHIP_ERROR: 5490 error = B_TRUE; 5491 break; 5492 5493 case BGE_CHIP_FAULT: 5494 /* 5495 * Fault detected, time to reset ... 5496 */ 5497 if (bge_autorecover) { 5498 if (!(bgep->progress & PROGRESS_BUFS)) { 5499 /* 5500 * if we can't allocate the ring buffers, 5501 * try later 5502 */ 5503 if (bge_alloc_bufs(bgep) != DDI_SUCCESS) { 5504 mutex_exit(bgep->genlock); 5505 return (result); 5506 } 5507 bgep->progress |= PROGRESS_BUFS; 5508 } 5509 if (!(bgep->progress & PROGRESS_INTR)) { 5510 bge_init_rings(bgep); 5511 bge_intr_enable(bgep); 5512 bgep->progress |= PROGRESS_INTR; 5513 } 5514 if (!(bgep->progress & PROGRESS_KSTATS)) { 5515 bge_init_kstats(bgep, 5516 ddi_get_instance(bgep->devinfo)); 5517 bgep->progress |= PROGRESS_KSTATS; 5518 } 5519 5520 BGE_REPORT((bgep, "automatic recovery activated")); 5521 5522 if (bge_restart(bgep, B_FALSE) != DDI_SUCCESS) { 5523 bgep->bge_chip_state = BGE_CHIP_ERROR; 5524 error = B_TRUE; 5525 } 5526 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != 5527 DDI_FM_OK) { 5528 bgep->bge_chip_state = BGE_CHIP_ERROR; 5529 error = B_TRUE; 5530 } 5531 if (bge_check_acc_handle(bgep, bgep->io_handle) != 5532 DDI_FM_OK) { 5533 bgep->bge_chip_state = BGE_CHIP_ERROR; 5534 error = B_TRUE; 5535 } 5536 if (error == B_FALSE) { 5537 #ifdef BGE_IPMI_ASF 5538 if (bgep->asf_enabled && 5539 bgep->asf_status != ASF_STAT_RUN) { 5540 bgep->asf_timeout_id = timeout( 5541 bge_asf_heartbeat, (void *)bgep, 5542 drv_usectohz( 5543 BGE_ASF_HEARTBEAT_INTERVAL)); 5544 bgep->asf_status = ASF_STAT_RUN; 5545 } 5546 #endif 5547 if (!bgep->manual_reset) { 5548 ddi_fm_service_impact(bgep->devinfo, 5549 DDI_SERVICE_RESTORED); 5550 } 5551 } 5552 } 5553 break; 5554 } 5555 5556 /* 5557 * If an error is detected, stop the chip now, marking it as 5558 * faulty, so that it will be reset next time through ... 5559 * 5560 * Note that if intr_running is set, then bge_intr() has dropped 5561 * genlock to call bge_receive/bge_recycle. Can't stop the chip at 5562 * this point so have to wait until the next time the factotum runs. 5563 */ 5564 if (error && !bgep->bge_intr_running) { 5565 #ifdef BGE_IPMI_ASF 5566 if (bgep->asf_enabled && (bgep->asf_status == ASF_STAT_RUN)) { 5567 /* 5568 * We must stop ASF heart beat before bge_chip_stop(), 5569 * otherwise some computers (ex. IBM HS20 blade server) 5570 * may crash. 5571 */ 5572 bge_asf_update_status(bgep); 5573 bge_asf_stop_timer(bgep); 5574 bgep->asf_status = ASF_STAT_STOP; 5575 5576 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 5577 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 5578 } 5579 #endif 5580 bge_chip_stop(bgep, B_TRUE); 5581 (void) bge_check_acc_handle(bgep, bgep->io_handle); 5582 } 5583 mutex_exit(bgep->genlock); 5584 5585 return (result); 5586 } 5587 5588 /* 5589 * High-level cyclic handler 5590 * 5591 * This routine schedules a (low-level) softint callback to the 5592 * factotum, and prods the chip to update the status block (which 5593 * will cause a hardware interrupt when complete). 5594 */ 5595 void bge_chip_cyclic(void *arg); 5596 #pragma no_inline(bge_chip_cyclic) 5597 5598 void 5599 bge_chip_cyclic(void *arg) 5600 { 5601 bge_t *bgep; 5602 uint32_t regval; 5603 5604 bgep = arg; 5605 5606 switch (bgep->bge_chip_state) { 5607 default: 5608 return; 5609 5610 case BGE_CHIP_RUNNING: 5611 5612 /* XXX I really don't like this forced interrupt... */ 5613 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, COALESCE_NOW); 5614 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5615 ddi_fm_service_impact(bgep->devinfo, 5616 DDI_SERVICE_UNAFFECTED); 5617 5618 break; 5619 5620 case BGE_CHIP_FAULT: 5621 case BGE_CHIP_ERROR: 5622 5623 break; 5624 } 5625 5626 mutex_enter(bgep->genlock); 5627 5628 if (bgep->eee_lpi_wait && !--bgep->eee_lpi_wait) { 5629 BGE_DEBUG(("eee cyclic, lpi enabled")); 5630 bge_eee_enable(bgep); 5631 } 5632 5633 if (bgep->rdma_length_bug_on_5719) { 5634 if ((bge_reg_get32(bgep, STAT_IFHCOUT_UPKGS_REG) + 5635 bge_reg_get32(bgep, STAT_IFHCOUT_MPKGS_REG) + 5636 bge_reg_get32(bgep, STAT_IFHCOUT_BPKGS_REG)) > 5637 BGE_NUM_RDMA_CHANNELS) { 5638 regval = bge_reg_get32(bgep, RDMA_CORR_CTRL_REG); 5639 regval &= ~RDMA_CORR_CTRL_TX_LENGTH_WA; 5640 bge_reg_put32(bgep, RDMA_CORR_CTRL_REG, regval); 5641 bgep->rdma_length_bug_on_5719 = B_FALSE; 5642 } 5643 } 5644 5645 mutex_exit(bgep->genlock); 5646 5647 bge_wake_factotum(bgep); 5648 5649 } 5650 5651 5652 /* 5653 * ========== Ioctl subfunctions ========== 5654 */ 5655 5656 #undef BGE_DBG 5657 #define BGE_DBG BGE_DBG_PPIO /* debug flag for this code */ 5658 5659 #if BGE_DEBUGGING || BGE_DO_PPIO 5660 5661 static void bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 5662 #pragma no_inline(bge_chip_peek_cfg) 5663 5664 static void 5665 bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 5666 { 5667 uint64_t regval; 5668 uint64_t regno; 5669 5670 BGE_TRACE(("bge_chip_peek_cfg($%p, $%p)", 5671 (void *)bgep, (void *)ppd)); 5672 5673 regno = ppd->pp_acc_offset; 5674 5675 switch (ppd->pp_acc_size) { 5676 case 1: 5677 regval = pci_config_get8(bgep->cfg_handle, regno); 5678 break; 5679 5680 case 2: 5681 regval = pci_config_get16(bgep->cfg_handle, regno); 5682 break; 5683 5684 case 4: 5685 regval = pci_config_get32(bgep->cfg_handle, regno); 5686 break; 5687 5688 case 8: 5689 regval = pci_config_get64(bgep->cfg_handle, regno); 5690 break; 5691 } 5692 5693 ppd->pp_acc_data = regval; 5694 } 5695 5696 static void bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 5697 #pragma no_inline(bge_chip_poke_cfg) 5698 5699 static void 5700 bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 5701 { 5702 uint64_t regval; 5703 uint64_t regno; 5704 5705 BGE_TRACE(("bge_chip_poke_cfg($%p, $%p)", 5706 (void *)bgep, (void *)ppd)); 5707 5708 regno = ppd->pp_acc_offset; 5709 regval = ppd->pp_acc_data; 5710 5711 switch (ppd->pp_acc_size) { 5712 case 1: 5713 pci_config_put8(bgep->cfg_handle, regno, regval); 5714 break; 5715 5716 case 2: 5717 pci_config_put16(bgep->cfg_handle, regno, regval); 5718 break; 5719 5720 case 4: 5721 pci_config_put32(bgep->cfg_handle, regno, regval); 5722 break; 5723 5724 case 8: 5725 pci_config_put64(bgep->cfg_handle, regno, regval); 5726 break; 5727 } 5728 } 5729 5730 static void bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd); 5731 #pragma no_inline(bge_chip_peek_reg) 5732 5733 static void 5734 bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd) 5735 { 5736 uint64_t regval; 5737 void *regaddr; 5738 5739 BGE_TRACE(("bge_chip_peek_reg($%p, $%p)", 5740 (void *)bgep, (void *)ppd)); 5741 5742 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 5743 5744 switch (ppd->pp_acc_size) { 5745 case 1: 5746 regval = ddi_get8(bgep->io_handle, regaddr); 5747 break; 5748 5749 case 2: 5750 regval = ddi_get16(bgep->io_handle, regaddr); 5751 break; 5752 5753 case 4: 5754 regval = ddi_get32(bgep->io_handle, regaddr); 5755 break; 5756 5757 case 8: 5758 regval = ddi_get64(bgep->io_handle, regaddr); 5759 break; 5760 } 5761 5762 ppd->pp_acc_data = regval; 5763 } 5764 5765 static void bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd); 5766 #pragma no_inline(bge_chip_peek_reg) 5767 5768 static void 5769 bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd) 5770 { 5771 uint64_t regval; 5772 void *regaddr; 5773 5774 BGE_TRACE(("bge_chip_poke_reg($%p, $%p)", 5775 (void *)bgep, (void *)ppd)); 5776 5777 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 5778 regval = ppd->pp_acc_data; 5779 5780 switch (ppd->pp_acc_size) { 5781 case 1: 5782 ddi_put8(bgep->io_handle, regaddr, regval); 5783 break; 5784 5785 case 2: 5786 ddi_put16(bgep->io_handle, regaddr, regval); 5787 break; 5788 5789 case 4: 5790 ddi_put32(bgep->io_handle, regaddr, regval); 5791 break; 5792 5793 case 8: 5794 ddi_put64(bgep->io_handle, regaddr, regval); 5795 break; 5796 } 5797 BGE_PCICHK(bgep); 5798 } 5799 5800 static void bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd); 5801 #pragma no_inline(bge_chip_peek_nic) 5802 5803 static void 5804 bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd) 5805 { 5806 uint64_t regoff; 5807 uint64_t regval; 5808 void *regaddr; 5809 5810 BGE_TRACE(("bge_chip_peek_nic($%p, $%p)", 5811 (void *)bgep, (void *)ppd)); 5812 5813 regoff = ppd->pp_acc_offset; 5814 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 5815 regoff &= MWBAR_GRANULE_MASK; 5816 regoff += NIC_MEM_WINDOW_OFFSET; 5817 regaddr = PIO_ADDR(bgep, regoff); 5818 5819 switch (ppd->pp_acc_size) { 5820 case 1: 5821 regval = ddi_get8(bgep->io_handle, regaddr); 5822 break; 5823 5824 case 2: 5825 regval = ddi_get16(bgep->io_handle, regaddr); 5826 break; 5827 5828 case 4: 5829 regval = ddi_get32(bgep->io_handle, regaddr); 5830 break; 5831 5832 case 8: 5833 regval = ddi_get64(bgep->io_handle, regaddr); 5834 break; 5835 } 5836 5837 ppd->pp_acc_data = regval; 5838 } 5839 5840 static void bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd); 5841 #pragma no_inline(bge_chip_poke_nic) 5842 5843 static void 5844 bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd) 5845 { 5846 uint64_t regoff; 5847 uint64_t regval; 5848 void *regaddr; 5849 5850 BGE_TRACE(("bge_chip_poke_nic($%p, $%p)", 5851 (void *)bgep, (void *)ppd)); 5852 5853 regoff = ppd->pp_acc_offset; 5854 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 5855 regoff &= MWBAR_GRANULE_MASK; 5856 regoff += NIC_MEM_WINDOW_OFFSET; 5857 regaddr = PIO_ADDR(bgep, regoff); 5858 regval = ppd->pp_acc_data; 5859 5860 switch (ppd->pp_acc_size) { 5861 case 1: 5862 ddi_put8(bgep->io_handle, regaddr, regval); 5863 break; 5864 5865 case 2: 5866 ddi_put16(bgep->io_handle, regaddr, regval); 5867 break; 5868 5869 case 4: 5870 ddi_put32(bgep->io_handle, regaddr, regval); 5871 break; 5872 5873 case 8: 5874 ddi_put64(bgep->io_handle, regaddr, regval); 5875 break; 5876 } 5877 BGE_PCICHK(bgep); 5878 } 5879 5880 static void bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd); 5881 #pragma no_inline(bge_chip_peek_mii) 5882 5883 static void 5884 bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd) 5885 { 5886 BGE_TRACE(("bge_chip_peek_mii($%p, $%p)", 5887 (void *)bgep, (void *)ppd)); 5888 5889 ppd->pp_acc_data = bge_mii_get16(bgep, ppd->pp_acc_offset/2); 5890 } 5891 5892 static void bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd); 5893 #pragma no_inline(bge_chip_poke_mii) 5894 5895 static void 5896 bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd) 5897 { 5898 BGE_TRACE(("bge_chip_poke_mii($%p, $%p)", 5899 (void *)bgep, (void *)ppd)); 5900 5901 bge_mii_put16(bgep, ppd->pp_acc_offset/2, ppd->pp_acc_data); 5902 } 5903 5904 #if BGE_SEE_IO32 5905 5906 static void bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 5907 #pragma no_inline(bge_chip_peek_seeprom) 5908 5909 static void 5910 bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 5911 { 5912 uint32_t data; 5913 int err; 5914 5915 BGE_TRACE(("bge_chip_peek_seeprom($%p, $%p)", 5916 (void *)bgep, (void *)ppd)); 5917 5918 err = bge_nvmem_rw32(bgep, BGE_SEE_READ, ppd->pp_acc_offset, &data); 5919 ppd->pp_acc_data = err ? ~0ull : data; 5920 } 5921 5922 static void bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 5923 #pragma no_inline(bge_chip_poke_seeprom) 5924 5925 static void 5926 bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 5927 { 5928 uint32_t data; 5929 5930 BGE_TRACE(("bge_chip_poke_seeprom($%p, $%p)", 5931 (void *)bgep, (void *)ppd)); 5932 5933 data = ppd->pp_acc_data; 5934 (void) bge_nvmem_rw32(bgep, BGE_SEE_WRITE, ppd->pp_acc_offset, &data); 5935 } 5936 #endif /* BGE_SEE_IO32 */ 5937 5938 #if BGE_FLASH_IO32 5939 5940 static void bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd); 5941 #pragma no_inline(bge_chip_peek_flash) 5942 5943 static void 5944 bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd) 5945 { 5946 uint32_t data; 5947 int err; 5948 5949 BGE_TRACE(("bge_chip_peek_flash($%p, $%p)", 5950 (void *)bgep, (void *)ppd)); 5951 5952 err = bge_nvmem_rw32(bgep, BGE_FLASH_READ, ppd->pp_acc_offset, &data); 5953 ppd->pp_acc_data = err ? ~0ull : data; 5954 } 5955 5956 static void bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd); 5957 #pragma no_inline(bge_chip_poke_flash) 5958 5959 static void 5960 bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd) 5961 { 5962 uint32_t data; 5963 5964 BGE_TRACE(("bge_chip_poke_flash($%p, $%p)", 5965 (void *)bgep, (void *)ppd)); 5966 5967 data = ppd->pp_acc_data; 5968 (void) bge_nvmem_rw32(bgep, BGE_FLASH_WRITE, 5969 ppd->pp_acc_offset, &data); 5970 } 5971 #endif /* BGE_FLASH_IO32 */ 5972 5973 static void bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd); 5974 #pragma no_inline(bge_chip_peek_mem) 5975 5976 static void 5977 bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd) 5978 { 5979 uint64_t regval; 5980 void *vaddr; 5981 5982 BGE_TRACE(("bge_chip_peek_bge($%p, $%p)", 5983 (void *)bgep, (void *)ppd)); 5984 5985 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 5986 5987 switch (ppd->pp_acc_size) { 5988 case 1: 5989 regval = *(uint8_t *)vaddr; 5990 break; 5991 5992 case 2: 5993 regval = *(uint16_t *)vaddr; 5994 break; 5995 5996 case 4: 5997 regval = *(uint32_t *)vaddr; 5998 break; 5999 6000 case 8: 6001 regval = *(uint64_t *)vaddr; 6002 break; 6003 } 6004 6005 BGE_DEBUG(("bge_chip_peek_mem($%p, $%p) peeked 0x%llx from $%p", 6006 (void *)bgep, (void *)ppd, regval, vaddr)); 6007 6008 ppd->pp_acc_data = regval; 6009 } 6010 6011 static void bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd); 6012 #pragma no_inline(bge_chip_poke_mem) 6013 6014 static void 6015 bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd) 6016 { 6017 uint64_t regval; 6018 void *vaddr; 6019 6020 BGE_TRACE(("bge_chip_poke_mem($%p, $%p)", 6021 (void *)bgep, (void *)ppd)); 6022 6023 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 6024 regval = ppd->pp_acc_data; 6025 6026 BGE_DEBUG(("bge_chip_poke_mem($%p, $%p) poking 0x%llx at $%p", 6027 (void *)bgep, (void *)ppd, regval, vaddr)); 6028 6029 switch (ppd->pp_acc_size) { 6030 case 1: 6031 *(uint8_t *)vaddr = (uint8_t)regval; 6032 break; 6033 6034 case 2: 6035 *(uint16_t *)vaddr = (uint16_t)regval; 6036 break; 6037 6038 case 4: 6039 *(uint32_t *)vaddr = (uint32_t)regval; 6040 break; 6041 6042 case 8: 6043 *(uint64_t *)vaddr = (uint64_t)regval; 6044 break; 6045 } 6046 } 6047 6048 static enum ioc_reply bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 6049 struct iocblk *iocp); 6050 #pragma no_inline(bge_pp_ioctl) 6051 6052 static enum ioc_reply 6053 bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 6054 { 6055 void (*ppfn)(bge_t *bgep, bge_peekpoke_t *ppd); 6056 bge_peekpoke_t *ppd; 6057 dma_area_t *areap; 6058 uint64_t sizemask; 6059 uint64_t mem_va; 6060 uint64_t maxoff; 6061 boolean_t peek; 6062 6063 switch (cmd) { 6064 default: 6065 /* NOTREACHED */ 6066 bge_error(bgep, "bge_pp_ioctl: invalid cmd 0x%x", cmd); 6067 return (IOC_INVAL); 6068 6069 case BGE_PEEK: 6070 peek = B_TRUE; 6071 break; 6072 6073 case BGE_POKE: 6074 peek = B_FALSE; 6075 break; 6076 } 6077 6078 /* 6079 * Validate format of ioctl 6080 */ 6081 if (iocp->ioc_count != sizeof (bge_peekpoke_t)) 6082 return (IOC_INVAL); 6083 if (mp->b_cont == NULL) 6084 return (IOC_INVAL); 6085 ppd = (void *)mp->b_cont->b_rptr; 6086 6087 /* 6088 * Validate request parameters 6089 */ 6090 switch (ppd->pp_acc_space) { 6091 default: 6092 return (IOC_INVAL); 6093 6094 case BGE_PP_SPACE_CFG: 6095 /* 6096 * Config space 6097 */ 6098 sizemask = 8|4|2|1; 6099 mem_va = 0; 6100 maxoff = PCI_CONF_HDR_SIZE; 6101 ppfn = peek ? bge_chip_peek_cfg : bge_chip_poke_cfg; 6102 break; 6103 6104 case BGE_PP_SPACE_REG: 6105 /* 6106 * Memory-mapped I/O space 6107 */ 6108 sizemask = 8|4|2|1; 6109 mem_va = 0; 6110 maxoff = RIAAR_REGISTER_MAX; 6111 ppfn = peek ? bge_chip_peek_reg : bge_chip_poke_reg; 6112 break; 6113 6114 case BGE_PP_SPACE_NIC: 6115 /* 6116 * NIC on-chip memory 6117 */ 6118 sizemask = 8|4|2|1; 6119 mem_va = 0; 6120 maxoff = MWBAR_ONCHIP_MAX; 6121 ppfn = peek ? bge_chip_peek_nic : bge_chip_poke_nic; 6122 break; 6123 6124 case BGE_PP_SPACE_MII: 6125 /* 6126 * PHY's MII registers 6127 * NB: all PHY registers are two bytes, but the 6128 * addresses increment in ones (word addressing). 6129 * So we scale the address here, then undo the 6130 * transformation inside the peek/poke functions. 6131 */ 6132 ppd->pp_acc_offset *= 2; 6133 sizemask = 2; 6134 mem_va = 0; 6135 maxoff = (MII_MAXREG+1)*2; 6136 ppfn = peek ? bge_chip_peek_mii : bge_chip_poke_mii; 6137 break; 6138 6139 #if BGE_SEE_IO32 6140 case BGE_PP_SPACE_SEEPROM: 6141 /* 6142 * Attached SEEPROM(s), if any. 6143 * NB: we use the high-order bits of the 'address' as 6144 * a device select to accommodate multiple SEEPROMS, 6145 * If each one is the maximum size (64kbytes), this 6146 * makes them appear contiguous. Otherwise, there may 6147 * be holes in the mapping. ENxS doesn't have any 6148 * SEEPROMs anyway ... 6149 */ 6150 sizemask = 4; 6151 mem_va = 0; 6152 maxoff = SEEPROM_DEV_AND_ADDR_MASK; 6153 ppfn = peek ? bge_chip_peek_seeprom : bge_chip_poke_seeprom; 6154 break; 6155 #endif /* BGE_SEE_IO32 */ 6156 6157 #if BGE_FLASH_IO32 6158 case BGE_PP_SPACE_FLASH: 6159 /* 6160 * Attached Flash device (if any); a maximum of one device 6161 * is currently supported. But it can be up to 1MB (unlike 6162 * the 64k limit on SEEPROMs) so why would you need more ;-) 6163 */ 6164 sizemask = 4; 6165 mem_va = 0; 6166 maxoff = NVM_FLASH_ADDR_MASK; 6167 ppfn = peek ? bge_chip_peek_flash : bge_chip_poke_flash; 6168 break; 6169 #endif /* BGE_FLASH_IO32 */ 6170 6171 case BGE_PP_SPACE_BGE: 6172 /* 6173 * BGE data structure! 6174 */ 6175 sizemask = 8|4|2|1; 6176 mem_va = (uintptr_t)bgep; 6177 maxoff = sizeof (*bgep); 6178 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 6179 break; 6180 6181 case BGE_PP_SPACE_STATUS: 6182 case BGE_PP_SPACE_STATISTICS: 6183 case BGE_PP_SPACE_TXDESC: 6184 case BGE_PP_SPACE_TXBUFF: 6185 case BGE_PP_SPACE_RXDESC: 6186 case BGE_PP_SPACE_RXBUFF: 6187 /* 6188 * Various DMA_AREAs 6189 */ 6190 switch (ppd->pp_acc_space) { 6191 case BGE_PP_SPACE_TXDESC: 6192 areap = &bgep->tx_desc; 6193 break; 6194 case BGE_PP_SPACE_TXBUFF: 6195 areap = &bgep->tx_buff[0]; 6196 break; 6197 case BGE_PP_SPACE_RXDESC: 6198 areap = &bgep->rx_desc[0]; 6199 break; 6200 case BGE_PP_SPACE_RXBUFF: 6201 areap = &bgep->rx_buff[0]; 6202 break; 6203 case BGE_PP_SPACE_STATUS: 6204 areap = &bgep->status_block; 6205 break; 6206 case BGE_PP_SPACE_STATISTICS: 6207 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 6208 areap = &bgep->statistics; 6209 break; 6210 } 6211 6212 sizemask = 8|4|2|1; 6213 mem_va = (uintptr_t)areap->mem_va; 6214 maxoff = areap->alength; 6215 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 6216 break; 6217 } 6218 6219 switch (ppd->pp_acc_size) { 6220 default: 6221 return (IOC_INVAL); 6222 6223 case 8: 6224 case 4: 6225 case 2: 6226 case 1: 6227 if ((ppd->pp_acc_size & sizemask) == 0) 6228 return (IOC_INVAL); 6229 break; 6230 } 6231 6232 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 6233 return (IOC_INVAL); 6234 6235 if (ppd->pp_acc_offset >= maxoff) 6236 return (IOC_INVAL); 6237 6238 if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff) 6239 return (IOC_INVAL); 6240 6241 /* 6242 * All OK - go do it! 6243 */ 6244 ppd->pp_acc_offset += mem_va; 6245 (*ppfn)(bgep, ppd); 6246 return (peek ? IOC_REPLY : IOC_ACK); 6247 } 6248 6249 static enum ioc_reply bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 6250 struct iocblk *iocp); 6251 #pragma no_inline(bge_diag_ioctl) 6252 6253 static enum ioc_reply 6254 bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 6255 { 6256 ASSERT(mutex_owned(bgep->genlock)); 6257 6258 switch (cmd) { 6259 default: 6260 /* NOTREACHED */ 6261 bge_error(bgep, "bge_diag_ioctl: invalid cmd 0x%x", cmd); 6262 return (IOC_INVAL); 6263 6264 case BGE_DIAG: 6265 /* 6266 * Currently a no-op 6267 */ 6268 return (IOC_ACK); 6269 6270 case BGE_PEEK: 6271 case BGE_POKE: 6272 return (bge_pp_ioctl(bgep, cmd, mp, iocp)); 6273 6274 case BGE_PHY_RESET: 6275 return (IOC_RESTART_ACK); 6276 6277 case BGE_SOFT_RESET: 6278 case BGE_HARD_RESET: 6279 /* 6280 * Reset and reinitialise the 570x hardware 6281 */ 6282 bgep->bge_chip_state = BGE_CHIP_FAULT; 6283 ddi_trigger_softintr(bgep->factotum_id); 6284 (void) bge_restart(bgep, cmd == BGE_HARD_RESET); 6285 return (IOC_ACK); 6286 } 6287 6288 /* NOTREACHED */ 6289 } 6290 6291 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 6292 6293 static enum ioc_reply bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 6294 struct iocblk *iocp); 6295 #pragma no_inline(bge_mii_ioctl) 6296 6297 static enum ioc_reply 6298 bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 6299 { 6300 struct bge_mii_rw *miirwp; 6301 6302 /* 6303 * Validate format of ioctl 6304 */ 6305 if (iocp->ioc_count != sizeof (struct bge_mii_rw)) 6306 return (IOC_INVAL); 6307 if (mp->b_cont == NULL) 6308 return (IOC_INVAL); 6309 miirwp = (void *)mp->b_cont->b_rptr; 6310 6311 /* 6312 * Validate request parameters ... 6313 */ 6314 if (miirwp->mii_reg > MII_MAXREG) 6315 return (IOC_INVAL); 6316 6317 switch (cmd) { 6318 default: 6319 /* NOTREACHED */ 6320 bge_error(bgep, "bge_mii_ioctl: invalid cmd 0x%x", cmd); 6321 return (IOC_INVAL); 6322 6323 case BGE_MII_READ: 6324 miirwp->mii_data = bge_mii_get16(bgep, miirwp->mii_reg); 6325 return (IOC_REPLY); 6326 6327 case BGE_MII_WRITE: 6328 bge_mii_put16(bgep, miirwp->mii_reg, miirwp->mii_data); 6329 return (IOC_ACK); 6330 } 6331 6332 /* NOTREACHED */ 6333 } 6334 6335 #if BGE_SEE_IO32 6336 6337 static enum ioc_reply bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 6338 struct iocblk *iocp); 6339 #pragma no_inline(bge_see_ioctl) 6340 6341 static enum ioc_reply 6342 bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 6343 { 6344 struct bge_see_rw *seerwp; 6345 6346 /* 6347 * Validate format of ioctl 6348 */ 6349 if (iocp->ioc_count != sizeof (struct bge_see_rw)) 6350 return (IOC_INVAL); 6351 if (mp->b_cont == NULL) 6352 return (IOC_INVAL); 6353 seerwp = (void *)mp->b_cont->b_rptr; 6354 6355 /* 6356 * Validate request parameters ... 6357 */ 6358 if (seerwp->see_addr & ~SEEPROM_DEV_AND_ADDR_MASK) 6359 return (IOC_INVAL); 6360 6361 switch (cmd) { 6362 default: 6363 /* NOTREACHED */ 6364 bge_error(bgep, "bge_see_ioctl: invalid cmd 0x%x", cmd); 6365 return (IOC_INVAL); 6366 6367 case BGE_SEE_READ: 6368 case BGE_SEE_WRITE: 6369 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 6370 seerwp->see_addr, &seerwp->see_data); 6371 return (IOC_REPLY); 6372 } 6373 6374 /* NOTREACHED */ 6375 } 6376 6377 #endif /* BGE_SEE_IO32 */ 6378 6379 #if BGE_FLASH_IO32 6380 6381 static enum ioc_reply bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 6382 struct iocblk *iocp); 6383 #pragma no_inline(bge_flash_ioctl) 6384 6385 static enum ioc_reply 6386 bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 6387 { 6388 struct bge_flash_rw *flashrwp; 6389 6390 /* 6391 * Validate format of ioctl 6392 */ 6393 if (iocp->ioc_count != sizeof (struct bge_flash_rw)) 6394 return (IOC_INVAL); 6395 if (mp->b_cont == NULL) 6396 return (IOC_INVAL); 6397 flashrwp = (void *)mp->b_cont->b_rptr; 6398 6399 /* 6400 * Validate request parameters ... 6401 */ 6402 if (flashrwp->flash_addr & ~NVM_FLASH_ADDR_MASK) 6403 return (IOC_INVAL); 6404 6405 switch (cmd) { 6406 default: 6407 /* NOTREACHED */ 6408 bge_error(bgep, "bge_flash_ioctl: invalid cmd 0x%x", cmd); 6409 return (IOC_INVAL); 6410 6411 case BGE_FLASH_READ: 6412 case BGE_FLASH_WRITE: 6413 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 6414 flashrwp->flash_addr, &flashrwp->flash_data); 6415 return (IOC_REPLY); 6416 } 6417 6418 /* NOTREACHED */ 6419 } 6420 6421 #endif /* BGE_FLASH_IO32 */ 6422 6423 enum ioc_reply bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, 6424 struct iocblk *iocp); 6425 #pragma no_inline(bge_chip_ioctl) 6426 6427 enum ioc_reply 6428 bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 6429 { 6430 int cmd; 6431 6432 BGE_TRACE(("bge_chip_ioctl($%p, $%p, $%p, $%p)", 6433 (void *)bgep, (void *)wq, (void *)mp, (void *)iocp)); 6434 6435 ASSERT(mutex_owned(bgep->genlock)); 6436 6437 cmd = iocp->ioc_cmd; 6438 switch (cmd) { 6439 default: 6440 /* NOTREACHED */ 6441 bge_error(bgep, "bge_chip_ioctl: invalid cmd 0x%x", cmd); 6442 return (IOC_INVAL); 6443 6444 case BGE_DIAG: 6445 case BGE_PEEK: 6446 case BGE_POKE: 6447 case BGE_PHY_RESET: 6448 case BGE_SOFT_RESET: 6449 case BGE_HARD_RESET: 6450 #if BGE_DEBUGGING || BGE_DO_PPIO 6451 return (bge_diag_ioctl(bgep, cmd, mp, iocp)); 6452 #else 6453 return (IOC_INVAL); 6454 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 6455 6456 case BGE_MII_READ: 6457 case BGE_MII_WRITE: 6458 return (bge_mii_ioctl(bgep, cmd, mp, iocp)); 6459 6460 #if BGE_SEE_IO32 6461 case BGE_SEE_READ: 6462 case BGE_SEE_WRITE: 6463 return (bge_see_ioctl(bgep, cmd, mp, iocp)); 6464 #endif /* BGE_SEE_IO32 */ 6465 6466 #if BGE_FLASH_IO32 6467 case BGE_FLASH_READ: 6468 case BGE_FLASH_WRITE: 6469 return (bge_flash_ioctl(bgep, cmd, mp, iocp)); 6470 #endif /* BGE_FLASH_IO32 */ 6471 } 6472 6473 /* NOTREACHED */ 6474 } 6475 6476 /* ARGSUSED */ 6477 void 6478 bge_chip_blank(void *arg, time_t ticks, uint_t count, int flag) 6479 { 6480 recv_ring_t *rrp = arg; 6481 bge_t *bgep = rrp->bgep; 6482 6483 mutex_enter(bgep->genlock); 6484 rrp->poll_flag = flag; 6485 #ifdef NOT_YET 6486 /* 6487 * XXX-Sunay: Since most broadcom cards support only one 6488 * interrupt but multiple rx rings, we can't disable the 6489 * physical interrupt. This need to be done via capability 6490 * negotiation depending on the NIC. 6491 */ 6492 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, ticks); 6493 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, count); 6494 #endif 6495 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 6496 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 6497 mutex_exit(bgep->genlock); 6498 } 6499 6500 #ifdef BGE_IPMI_ASF 6501 6502 uint32_t 6503 bge_nic_read32(bge_t *bgep, bge_regno_t addr) 6504 { 6505 uint32_t data; 6506 6507 #ifndef __sparc 6508 if (!bgep->asf_wordswapped) { 6509 /* a workaround word swap error */ 6510 if (addr & 4) 6511 addr = addr - 4; 6512 else 6513 addr = addr + 4; 6514 } 6515 #else 6516 if (DEVICE_5717_SERIES_CHIPSETS(bgep) || 6517 DEVICE_5725_SERIES_CHIPSETS(bgep) || 6518 DEVICE_57765_SERIES_CHIPSETS(bgep)) { 6519 addr = LE_32(addr); 6520 } 6521 #endif 6522 6523 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr); 6524 data = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR); 6525 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0); 6526 6527 data = LE_32(data); 6528 6529 BGE_DEBUG(("bge_nic_read32($%p, 0x%x) => 0x%x", 6530 (void *)bgep, addr, data)); 6531 6532 return (data); 6533 } 6534 6535 void 6536 bge_asf_update_status(bge_t *bgep) 6537 { 6538 uint32_t event; 6539 6540 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_ALIVE); 6541 bge_nic_put32(bgep, BGE_CMD_LENGTH_MAILBOX, 4); 6542 bge_nic_put32(bgep, BGE_CMD_DATA_MAILBOX, 3); 6543 6544 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 6545 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 6546 } 6547 6548 6549 /* 6550 * The driver is supposed to notify ASF that the OS is still running 6551 * every three seconds, otherwise the management server may attempt 6552 * to reboot the machine. If it hasn't actually failed, this is 6553 * not a desirable result. However, this isn't running as a real-time 6554 * thread, and even if it were, it might not be able to generate the 6555 * heartbeat in a timely manner due to system load. As it isn't a 6556 * significant strain on the machine, we will set the interval to half 6557 * of the required value. 6558 */ 6559 void 6560 bge_asf_heartbeat(void *arg) 6561 { 6562 bge_t *bgep = (bge_t *)arg; 6563 6564 mutex_enter(bgep->genlock); 6565 bge_asf_update_status((bge_t *)bgep); 6566 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 6567 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 6568 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) 6569 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 6570 mutex_exit(bgep->genlock); 6571 ((bge_t *)bgep)->asf_timeout_id = timeout(bge_asf_heartbeat, bgep, 6572 drv_usectohz(BGE_ASF_HEARTBEAT_INTERVAL)); 6573 } 6574 6575 6576 void 6577 bge_asf_stop_timer(bge_t *bgep) 6578 { 6579 timeout_id_t tmp_id = 0; 6580 6581 while ((bgep->asf_timeout_id != 0) && 6582 (tmp_id != bgep->asf_timeout_id)) { 6583 tmp_id = bgep->asf_timeout_id; 6584 (void) untimeout(tmp_id); 6585 } 6586 bgep->asf_timeout_id = 0; 6587 } 6588 6589 6590 6591 /* 6592 * This function should be placed at the earliest position of bge_attach(). 6593 */ 6594 void 6595 bge_asf_get_config(bge_t *bgep) 6596 { 6597 uint32_t nicsig; 6598 uint32_t niccfg; 6599 6600 bgep->asf_enabled = B_FALSE; 6601 6602 /* No ASF if APE present. */ 6603 if (bgep->ape_enabled) 6604 return; 6605 6606 nicsig = bge_nic_read32(bgep, BGE_NIC_DATA_SIG_ADDR); 6607 if (nicsig == BGE_NIC_DATA_SIG) { 6608 niccfg = bge_nic_read32(bgep, BGE_NIC_DATA_NIC_CFG_ADDR); 6609 if (niccfg & BGE_NIC_CFG_ENABLE_ASF) 6610 /* 6611 * Here, we don't consider BAXTER, because BGE haven't 6612 * supported BAXTER (that is 5752). Also, as I know, 6613 * BAXTER doesn't support ASF feature. 6614 */ 6615 bgep->asf_enabled = B_TRUE; 6616 else 6617 bgep->asf_enabled = B_FALSE; 6618 } else 6619 bgep->asf_enabled = B_FALSE; 6620 } 6621 6622 6623 void 6624 bge_asf_pre_reset_operations(bge_t *bgep, uint32_t mode) 6625 { 6626 uint32_t tries; 6627 uint32_t event; 6628 6629 ASSERT(bgep->asf_enabled); 6630 6631 /* Issues "pause firmware" command and wait for ACK */ 6632 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_PAUSE_FW); 6633 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 6634 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 6635 6636 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 6637 tries = 0; 6638 while ((event & RRER_ASF_EVENT) && (tries < 100)) { 6639 drv_usecwait(1); 6640 tries ++; 6641 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 6642 } 6643 6644 bge_nic_put32(bgep, BGE_FIRMWARE_MAILBOX, 6645 BGE_MAGIC_NUM_FIRMWARE_INIT_DONE); 6646 6647 if (bgep->asf_newhandshake) { 6648 switch (mode) { 6649 case BGE_INIT_RESET: 6650 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 6651 BGE_DRV_STATE_START); 6652 break; 6653 case BGE_SHUTDOWN_RESET: 6654 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 6655 BGE_DRV_STATE_UNLOAD); 6656 break; 6657 case BGE_SUSPEND_RESET: 6658 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 6659 BGE_DRV_STATE_SUSPEND); 6660 break; 6661 default: 6662 break; 6663 } 6664 } 6665 6666 if (mode == BGE_INIT_RESET || 6667 mode == BGE_SUSPEND_RESET) 6668 bge_ape_driver_state_change(bgep, mode); 6669 } 6670 6671 6672 void 6673 bge_asf_post_reset_old_mode(bge_t *bgep, uint32_t mode) 6674 { 6675 switch (mode) { 6676 case BGE_INIT_RESET: 6677 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 6678 BGE_DRV_STATE_START); 6679 break; 6680 case BGE_SHUTDOWN_RESET: 6681 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 6682 BGE_DRV_STATE_UNLOAD); 6683 break; 6684 case BGE_SUSPEND_RESET: 6685 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 6686 BGE_DRV_STATE_SUSPEND); 6687 break; 6688 default: 6689 break; 6690 } 6691 } 6692 6693 6694 void 6695 bge_asf_post_reset_new_mode(bge_t *bgep, uint32_t mode) 6696 { 6697 switch (mode) { 6698 case BGE_INIT_RESET: 6699 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 6700 BGE_DRV_STATE_START_DONE); 6701 break; 6702 case BGE_SHUTDOWN_RESET: 6703 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 6704 BGE_DRV_STATE_UNLOAD_DONE); 6705 break; 6706 default: 6707 break; 6708 } 6709 6710 if (mode == BGE_SHUTDOWN_RESET) 6711 bge_ape_driver_state_change(bgep, mode); 6712 } 6713 6714 #endif /* BGE_IPMI_ASF */ 6715