1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 2010-2013, by Broadcom, Inc. 24 * All Rights Reserved. 25 */ 26 27 /* 28 * Copyright (c) 2002, 2010, Oracle and/or its affiliates. 29 * All rights reserved. 30 */ 31 32 #include "bge_impl.h" 33 34 #define PIO_ADDR(bgep, offset) ((void *)((caddr_t)(bgep)->io_regs+(offset))) 35 #define APE_ADDR(bgep, offset) ((void *)((caddr_t)(bgep)->ape_regs+(offset))) 36 37 /* 38 * Future features ... ? 39 */ 40 #define BGE_CFG_IO8 1 /* 8/16-bit cfg space BIS/BIC */ 41 #define BGE_IND_IO32 1 /* indirect access code */ 42 #define BGE_SEE_IO32 1 /* SEEPROM access code */ 43 #define BGE_FLASH_IO32 1 /* FLASH access code */ 44 45 /* 46 * BGE MSI tunable: 47 * 48 * By default MSI is enabled on all supported platforms but it is disabled 49 * for some Broadcom chips due to known MSI hardware issues. Currently MSI 50 * is enabled only for 5714C A2 and 5715C A2 broadcom chips. 51 */ 52 boolean_t bge_enable_msi = B_TRUE; 53 54 /* 55 * PCI-X/PCI-E relaxed ordering tunable for OS/Nexus driver 56 */ 57 boolean_t bge_relaxed_ordering = B_TRUE; 58 59 /* 60 * Patchable globals: 61 * 62 * bge_autorecover 63 * Enables/disables automatic recovery after fault detection 64 * 65 * bge_mlcr_default 66 * Value to program into the MLCR; controls the chip's GPIO pins 67 * 68 * bge_dma_{rd,wr}prio 69 * Relative priorities of DMA reads & DMA writes respectively. 70 * These may each be patched to any value 0-3. Equal values 71 * will give "fair" (round-robin) arbitration for PCI access. 72 * Unequal values will give one or the other function priority. 73 * 74 * bge_dma_rwctrl 75 * Value to put in the Read/Write DMA control register. See 76 * the Broadcom PRM for things you can fiddle with in this 77 * register ... 78 * 79 * bge_{tx,rx}_{count,ticks}_{norm,intr} 80 * Send/receive interrupt coalescing parameters. Counts are 81 * #s of descriptors, ticks are in microseconds. *norm* values 82 * apply between status updates/interrupts; the *intr* values 83 * refer to the 'during-interrupt' versions - see the PRM. 84 * 85 * NOTE: these values have been determined by measurement. They 86 * differ significantly from the values recommended in the PRM. 87 */ 88 static uint32_t bge_autorecover = 1; 89 static uint32_t bge_mlcr_default_5714 = MLCR_DEFAULT_5714; 90 91 static uint32_t bge_dma_rdprio = 1; 92 static uint32_t bge_dma_wrprio = 0; 93 static uint32_t bge_dma_rwctrl = PDRWCR_VAR_DEFAULT; 94 static uint32_t bge_dma_rwctrl_5721 = PDRWCR_VAR_5721; 95 static uint32_t bge_dma_rwctrl_5714 = PDRWCR_VAR_5714; 96 static uint32_t bge_dma_rwctrl_5715 = PDRWCR_VAR_5715; 97 98 uint32_t bge_rx_ticks_norm = 128; 99 uint32_t bge_tx_ticks_norm = 512; 100 uint32_t bge_rx_count_norm = 8; 101 uint32_t bge_tx_count_norm = 128; 102 103 static uint32_t bge_rx_ticks_intr = 128; 104 static uint32_t bge_tx_ticks_intr = 0; /* 8 for FJ2+ !?!? */ 105 static uint32_t bge_rx_count_intr = 2; 106 static uint32_t bge_tx_count_intr = 0; 107 108 /* 109 * Memory pool configuration parameters. 110 * 111 * These are generally specific to each member of the chip family, since 112 * each one may have a different memory size/configuration. 113 * 114 * Setting the mbuf pool length for a specific type of chip to 0 inhibits 115 * the driver from programming the various registers; instead they are left 116 * at their hardware defaults. This is the preferred option for later chips 117 * (5705+), whereas the older chips *required* these registers to be set, 118 * since the h/w default was 0 ;-( 119 */ 120 static uint32_t bge_mbuf_pool_base = MBUF_POOL_BASE_DEFAULT; 121 static uint32_t bge_mbuf_pool_base_5704 = MBUF_POOL_BASE_5704; 122 static uint32_t bge_mbuf_pool_base_5705 = MBUF_POOL_BASE_5705; 123 static uint32_t bge_mbuf_pool_base_5721 = MBUF_POOL_BASE_5721; 124 static uint32_t bge_mbuf_pool_len = MBUF_POOL_LENGTH_DEFAULT; 125 static uint32_t bge_mbuf_pool_len_5704 = MBUF_POOL_LENGTH_5704; 126 static uint32_t bge_mbuf_pool_len_5705 = 0; /* use h/w default */ 127 static uint32_t bge_mbuf_pool_len_5721 = 0; 128 129 /* 130 * Various high and low water marks, thresholds, etc ... 131 * 132 * Note: these are taken from revision 7 of the PRM, and some are different 133 * from both the values in earlier PRMs *and* those determined experimentally 134 * and used in earlier versions of this driver ... 135 */ 136 static uint32_t bge_mbuf_hi_water = MBUF_HIWAT_DEFAULT; 137 static uint32_t bge_mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_DEFAULT; 138 static uint32_t bge_mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_DEFAULT; 139 140 static uint32_t bge_dmad_lo_water = DMAD_POOL_LOWAT_DEFAULT; 141 static uint32_t bge_dmad_hi_water = DMAD_POOL_HIWAT_DEFAULT; 142 static uint32_t bge_lowat_recv_frames = LOWAT_MAX_RECV_FRAMES_DEFAULT; 143 144 static uint32_t bge_replenish_std = STD_RCV_BD_REPLENISH_DEFAULT; 145 static uint32_t bge_replenish_mini = MINI_RCV_BD_REPLENISH_DEFAULT; 146 static uint32_t bge_replenish_jumbo = JUMBO_RCV_BD_REPLENISH_DEFAULT; 147 148 static uint32_t bge_watchdog_count = 1 << 16; 149 static uint16_t bge_dma_miss_limit = 20; 150 151 static uint32_t bge_stop_start_on_sync = 0; 152 153 /* 154 * bge_intr_max_loop controls the maximum loop number within bge_intr. 155 * When loading NIC with heavy network traffic, it is useful. 156 * Increasing this value could have positive effect to throughput, 157 * but it might also increase ticks of a bge ISR stick on CPU, which might 158 * lead to bad UI interactive experience. So tune this with caution. 159 */ 160 static int bge_intr_max_loop = 1; 161 162 /* 163 * ========== Low-level chip & ring buffer manipulation ========== 164 */ 165 166 #define BGE_DBG BGE_DBG_REGS /* debug flag for this code */ 167 168 169 /* 170 * Config space read-modify-write routines 171 */ 172 173 #if BGE_CFG_IO8 174 175 static void bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits); 176 #pragma inline(bge_cfg_clr16) 177 178 static void 179 bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits) 180 { 181 uint16_t regval; 182 183 BGE_TRACE(("bge_cfg_clr16($%p, 0x%lx, 0x%x)", 184 (void *)bgep, regno, bits)); 185 186 regval = pci_config_get16(bgep->cfg_handle, regno); 187 188 BGE_DEBUG(("bge_cfg_clr16($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 189 (void *)bgep, regno, bits, regval, regval & ~bits)); 190 191 regval &= ~bits; 192 pci_config_put16(bgep->cfg_handle, regno, regval); 193 } 194 195 #endif /* BGE_CFG_IO8 */ 196 197 static void bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 198 #pragma inline(bge_cfg_clr32) 199 200 static void 201 bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 202 { 203 uint32_t regval; 204 205 BGE_TRACE(("bge_cfg_clr32($%p, 0x%lx, 0x%x)", 206 (void *)bgep, regno, bits)); 207 208 regval = pci_config_get32(bgep->cfg_handle, regno); 209 210 BGE_DEBUG(("bge_cfg_clr32($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 211 (void *)bgep, regno, bits, regval, regval & ~bits)); 212 213 regval &= ~bits; 214 pci_config_put32(bgep->cfg_handle, regno, regval); 215 } 216 217 #if BGE_IND_IO32 218 219 /* 220 * Indirect access to registers & RISC scratchpads, using config space 221 * accesses only. 222 * 223 * This isn't currently used, but someday we might want to use it for 224 * restoring the Subsystem Device/Vendor registers (which aren't directly 225 * writable in Config Space), or for downloading firmware into the RISCs 226 * 227 * In any case there are endian issues to be resolved before this code is 228 * enabled; the bizarre way that bytes get twisted by this chip AND by 229 * the PCI bridge in SPARC systems mean that we shouldn't enable it until 230 * it's been thoroughly tested for all access sizes on all supported 231 * architectures (SPARC *and* x86!). 232 */ 233 uint32_t bge_ind_get32(bge_t *bgep, bge_regno_t regno); 234 #pragma inline(bge_ind_get32) 235 236 uint32_t 237 bge_ind_get32(bge_t *bgep, bge_regno_t regno) 238 { 239 uint32_t val; 240 241 BGE_TRACE(("bge_ind_get32($%p, 0x%lx)", (void *)bgep, regno)); 242 243 #ifdef __sparc 244 if (DEVICE_5717_SERIES_CHIPSETS(bgep) || 245 DEVICE_5725_SERIES_CHIPSETS(bgep)) { 246 regno = LE_32(regno); 247 } 248 #endif 249 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 250 val = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_RIADR); 251 252 BGE_DEBUG(("bge_ind_get32($%p, 0x%lx) => 0x%x", 253 (void *)bgep, regno, val)); 254 255 val = LE_32(val); 256 257 return (val); 258 } 259 260 void bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val); 261 #pragma inline(bge_ind_put32) 262 263 void 264 bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val) 265 { 266 BGE_TRACE(("bge_ind_put32($%p, 0x%lx, 0x%x)", 267 (void *)bgep, regno, val)); 268 269 val = LE_32(val); 270 #ifdef __sparc 271 if (DEVICE_5717_SERIES_CHIPSETS(bgep) || 272 DEVICE_5725_SERIES_CHIPSETS(bgep)) { 273 regno = LE_32(regno); 274 } 275 #endif 276 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 277 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIADR, val); 278 } 279 280 #endif /* BGE_IND_IO32 */ 281 282 #if BGE_DEBUGGING 283 284 static void bge_pci_check(bge_t *bgep); 285 #pragma no_inline(bge_pci_check) 286 287 static void 288 bge_pci_check(bge_t *bgep) 289 { 290 uint16_t pcistatus; 291 292 pcistatus = pci_config_get16(bgep->cfg_handle, PCI_CONF_STAT); 293 if ((pcistatus & (PCI_STAT_R_MAST_AB | PCI_STAT_R_TARG_AB)) != 0) 294 BGE_DEBUG(("bge_pci_check($%p): PCI status 0x%x", 295 (void *)bgep, pcistatus)); 296 } 297 298 #endif /* BGE_DEBUGGING */ 299 300 /* 301 * Perform first-stage chip (re-)initialisation, using only config-space 302 * accesses: 303 * 304 * + Read the vendor/device/revision/subsystem/cache-line-size registers, 305 * returning the data in the structure pointed to by <idp>. 306 * + Configure the target-mode endianness (swap) options. 307 * + Disable interrupts and enable Memory Space accesses. 308 * + Enable or disable Bus Mastering according to the <enable_dma> flag. 309 * 310 * This sequence is adapted from Broadcom document 570X-PG102-R, 311 * page 102, steps 1-3, 6-8 and 11-13. The omitted parts of the sequence 312 * are 4 and 5 (Reset Core and wait) which are handled elsewhere. 313 * 314 * This function MUST be called before any non-config-space accesses 315 * are made; on this first call <enable_dma> is B_FALSE, and it 316 * effectively performs steps 3-1(!) of the initialisation sequence 317 * (the rest are not required but should be harmless). 318 * 319 * It MUST also be called after a chip reset, as this disables 320 * Memory Space cycles! In this case, <enable_dma> is B_TRUE, and 321 * it is effectively performing steps 6-8. 322 */ 323 void bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma); 324 #pragma no_inline(bge_chip_cfg_init) 325 326 void 327 bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma) 328 { 329 ddi_acc_handle_t handle; 330 uint16_t command; 331 uint32_t mhcr; 332 uint32_t prodid; 333 uint32_t pci_state; 334 uint16_t value16; 335 int i; 336 337 BGE_TRACE(("bge_chip_cfg_init($%p, $%p, %d)", 338 (void *)bgep, (void *)cidp, enable_dma)); 339 340 /* 341 * Step 3: save PCI cache line size and subsystem vendor ID 342 * 343 * Read all the config-space registers that characterise the 344 * chip, specifically vendor/device/revision/subsystem vendor 345 * and subsystem device id. We expect (but don't check) that 346 * (vendor == VENDOR_ID_BROADCOM) && (device == DEVICE_ID_5704) 347 * 348 * Also save all bus-transaction related registers (cache-line 349 * size, bus-grant/latency parameters, etc). Some of these are 350 * cleared by reset, so we'll have to restore them later. This 351 * comes from the Broadcom document 570X-PG102-R ... 352 * 353 * Note: Broadcom document 570X-PG102-R seems to be in error 354 * here w.r.t. the offsets of the Subsystem Vendor ID and 355 * Subsystem (Device) ID registers, which are the opposite way 356 * round according to the PCI standard. For good measure, we 357 * save/restore both anyway. 358 */ 359 handle = bgep->cfg_handle; 360 361 /* 362 * For some chipsets (e.g., BCM5718), if MHCR_ENABLE_ENDIAN_BYTE_SWAP 363 * has been set in PCI_CONF_COMM already, we need to write the 364 * byte-swapped value to it. So we just write zero first for simplicity. 365 */ 366 cidp->device = pci_config_get16(handle, PCI_CONF_DEVID); 367 if (DEVICE_5717_SERIES_CHIPSETS(bgep) || 368 DEVICE_5725_SERIES_CHIPSETS(bgep)) { 369 pci_config_put32(handle, PCI_CONF_BGE_MHCR, 0); 370 } 371 372 mhcr = pci_config_get32(handle, PCI_CONF_BGE_MHCR); 373 cidp->asic_rev = (mhcr & MHCR_CHIP_REV_MASK); 374 cidp->asic_rev_prod_id = 0; 375 if ((cidp->asic_rev & 0xf0000000) == CHIP_ASIC_REV_USE_PROD_ID_REG) { 376 prodid = CHIP_ASIC_REV_PROD_ID_REG; 377 if (DEVICE_5717_SERIES_CHIPSETS(bgep) || 378 DEVICE_5725_SERIES_CHIPSETS(bgep)) { 379 prodid = CHIP_ASIC_REV_PROD_ID_GEN2_REG; 380 } 381 cidp->asic_rev_prod_id = pci_config_get32(handle, prodid); 382 } 383 384 cidp->businfo = pci_config_get32(handle, PCI_CONF_BGE_PCISTATE); 385 cidp->command = pci_config_get16(handle, PCI_CONF_COMM); 386 387 cidp->vendor = pci_config_get16(handle, PCI_CONF_VENID); 388 cidp->subven = pci_config_get16(handle, PCI_CONF_SUBVENID); 389 cidp->subdev = pci_config_get16(handle, PCI_CONF_SUBSYSID); 390 cidp->revision = pci_config_get8(handle, PCI_CONF_REVID); 391 cidp->clsize = pci_config_get8(handle, PCI_CONF_CACHE_LINESZ); 392 cidp->latency = pci_config_get8(handle, PCI_CONF_LATENCY_TIMER); 393 394 /* 5717 C0 is treated just like 5720 A0 */ 395 if (pci_config_get16(bgep->cfg_handle, PCI_CONF_DEVID) == 396 DEVICE_ID_5717_C0) { 397 cidp->device = DEVICE_ID_5720; 398 } 399 400 BGE_DEBUG(("bge_chip_cfg_init: %s bus is %s and %s; #INTA is %s", 401 cidp->businfo & PCISTATE_BUS_IS_PCI ? "PCI" : "PCI-X", 402 cidp->businfo & PCISTATE_BUS_IS_FAST ? "fast" : "slow", 403 cidp->businfo & PCISTATE_BUS_IS_32_BIT ? "narrow" : "wide", 404 cidp->businfo & PCISTATE_INTA_STATE ? "high" : "low")); 405 BGE_DEBUG(("bge_chip_cfg_init: vendor 0x%x device 0x%x revision 0x%x", 406 cidp->vendor, cidp->device, cidp->revision)); 407 BGE_DEBUG(("bge_chip_cfg_init: subven 0x%x subdev 0x%x asic_rev 0x%x", 408 cidp->subven, cidp->subdev, cidp->asic_rev)); 409 BGE_DEBUG(("bge_chip_cfg_init: clsize %d latency %d command 0x%x", 410 cidp->clsize, cidp->latency, cidp->command)); 411 412 /* 413 * Step 2 (also step 6): disable and clear interrupts. 414 * Steps 11-13: configure PIO endianness options, and enable 415 * indirect register access. We'll also select any other 416 * options controlled by the MHCR (e.g. tagged status, mask 417 * interrupt mode) at this stage ... 418 * 419 * Note: internally, the chip is 64-bit and BIG-endian, but 420 * since it talks to the host over a (LITTLE-endian) PCI bus, 421 * it normally swaps bytes around at the PCI interface. 422 * However, the PCI host bridge on SPARC systems normally 423 * swaps the byte lanes around too, since SPARCs are also 424 * BIG-endian. So it turns out that on SPARC, the right 425 * option is to tell the chip to swap (and the host bridge 426 * will swap back again), whereas on x86 we ask the chip 427 * NOT to swap, so the natural little-endianness of the 428 * PCI bus is assumed. Then the only thing that doesn't 429 * automatically work right is access to an 8-byte register 430 * by a little-endian host; but we don't want to set the 431 * MHCR_ENABLE_REGISTER_WORD_SWAP bit because then 4-byte 432 * accesses don't go where expected ;-( So we live with 433 * that, and perform word-swaps in software in the few cases 434 * where a chip register is defined as an 8-byte value -- 435 * see the code below for details ... 436 * 437 * Note: the meaning of the 'MASK_INTERRUPT_MODE' bit isn't 438 * very clear in the register description in the PRM, but 439 * Broadcom document 570X-PG104-R page 248 explains a little 440 * more (under "Broadcom Mask Mode"). The bit changes the way 441 * the MASK_PCI_INT_OUTPUT bit works: with MASK_INTERRUPT_MODE 442 * clear, the chip interprets MASK_PCI_INT_OUTPUT in the same 443 * way as the 5700 did, which isn't very convenient. Setting 444 * the MASK_INTERRUPT_MODE bit makes the MASK_PCI_INT_OUTPUT 445 * bit do just what its name says -- MASK the PCI #INTA output 446 * (i.e. deassert the signal at the pin) leaving all internal 447 * state unchanged. This is much more convenient for our 448 * interrupt handler, so we set MASK_INTERRUPT_MODE here. 449 * 450 * Note: the inconvenient semantics of the interrupt mailbox 451 * (nonzero disables and acknowledges/clears the interrupt, 452 * zero enables AND CLEARS it) would make race conditions 453 * likely in the interrupt handler: 454 * 455 * (1) acknowledge & disable interrupts 456 * (2) while (more to do) 457 * process packets 458 * (3) enable interrupts -- also clears pending 459 * 460 * If the chip received more packets and internally generated 461 * an interrupt between the check at (2) and the mbox write 462 * at (3), this interrupt would be lost :-( 463 * 464 * The best way to avoid this is to use TAGGED STATUS mode, 465 * where the chip includes a unique tag in each status block 466 * update, and the host, when re-enabling interrupts, passes 467 * the last tag it saw back to the chip; then the chip can 468 * see whether the host is truly up to date, and regenerate 469 * its interrupt if not. 470 */ 471 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 472 MHCR_ENABLE_PCI_STATE_RW | 473 MHCR_ENABLE_TAGGED_STATUS_MODE | 474 MHCR_MASK_INTERRUPT_MODE | 475 MHCR_CLEAR_INTERRUPT_INTA; 476 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 477 mhcr |= MHCR_MASK_PCI_INT_OUTPUT; 478 479 #ifdef _BIG_ENDIAN 480 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 481 #endif /* _BIG_ENDIAN */ 482 pci_config_put32(handle, PCI_CONF_BGE_MHCR, mhcr); 483 484 #ifdef BGE_IPMI_ASF 485 bgep->asf_wordswapped = B_FALSE; 486 #endif 487 488 pci_state = (PCISTATE_EXT_ROM_ENABLE | PCISTATE_EXT_ROM_RETRY); 489 /* allow reads and writes to the APE register and memory space */ 490 if (bgep->ape_enabled) { 491 pci_state |= PCISTATE_ALLOW_APE_CTLSPC_WR | 492 PCISTATE_ALLOW_APE_SHMEM_WR | PCISTATE_ALLOW_APE_PSPACE_WR; 493 } 494 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_PCISTATE, pci_state); 495 496 /* 497 * Step 1 (also step 7): Enable PCI Memory Space accesses 498 * Disable Memory Write/Invalidate 499 * Enable or disable Bus Mastering 500 * 501 * Note that all other bits are taken from the original value saved 502 * the first time through here, rather than from the current register 503 * value, 'cos that will have been cleared by a soft RESET since. 504 * In this way we preserve the OBP/nexus-parent's preferred settings 505 * of the parity-error and system-error enable bits across multiple 506 * chip RESETs. 507 */ 508 command = bgep->chipid.command | PCI_COMM_MAE; 509 command &= ~(PCI_COMM_ME|PCI_COMM_MEMWR_INVAL); 510 if (enable_dma) 511 command |= PCI_COMM_ME; 512 /* 513 * on BCM5714 revision A0, false parity error gets generated 514 * due to a logic bug. Provide a workaround by disabling parity 515 * error. 516 */ 517 if (((cidp->device == DEVICE_ID_5714C) || 518 (cidp->device == DEVICE_ID_5714S)) && 519 (cidp->revision == REVISION_ID_5714_A0)) { 520 command &= ~PCI_COMM_PARITY_DETECT; 521 } 522 pci_config_put16(handle, PCI_CONF_COMM, command); 523 524 /* 525 * On some PCI-E device, there were instances when 526 * the device was still link training. 527 */ 528 if (bgep->chipid.pci_type == BGE_PCI_E) { 529 i = 0; 530 value16 = pci_config_get16(handle, PCI_CONF_COMM); 531 while ((value16 != command) && (i < 100)) { 532 drv_usecwait(200); 533 value16 = pci_config_get16(handle, PCI_CONF_COMM); 534 ++i; 535 } 536 } 537 538 /* 539 * Clear any remaining error status bits 540 */ 541 pci_config_put16(handle, PCI_CONF_STAT, ~0); 542 543 /* 544 * Do following if and only if the device is NOT BCM5714C OR 545 * BCM5715C 546 */ 547 if (!((cidp->device == DEVICE_ID_5714C) || 548 (cidp->device == DEVICE_ID_5715C))) { 549 /* 550 * Make sure these indirect-access registers are sane 551 * rather than random after power-up or reset 552 */ 553 pci_config_put32(handle, PCI_CONF_BGE_RIAAR, 0); 554 pci_config_put32(handle, PCI_CONF_BGE_MWBAR, 0); 555 } 556 /* 557 * Step 8: Disable PCI-X/PCI-E Relaxed Ordering 558 */ 559 bge_cfg_clr16(bgep, PCIX_CONF_COMM, PCIX_COMM_RELAXED); 560 561 if (cidp->pci_type == BGE_PCI_E) { 562 if (DEVICE_5723_SERIES_CHIPSETS(bgep)) { 563 bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL_5723, 564 DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED); 565 } else if (DEVICE_5717_SERIES_CHIPSETS(bgep) || 566 DEVICE_5725_SERIES_CHIPSETS(bgep)) { 567 bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL_5717, 568 DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED); 569 } else { 570 bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL, 571 DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED); 572 } 573 } 574 } 575 576 #ifdef __amd64 577 /* 578 * Distinguish CPU types 579 * 580 * These use to distinguish AMD64 or Intel EM64T of CPU running mode. 581 * If CPU runs on Intel EM64T mode,the 64bit operation cannot works fine 582 * for PCI-Express based network interface card. This is the work-around 583 * for those nics. 584 */ 585 static boolean_t bge_get_em64t_type(void); 586 #pragma inline(bge_get_em64t_type) 587 588 static boolean_t 589 bge_get_em64t_type(void) 590 { 591 592 return (x86_vendor == X86_VENDOR_Intel); 593 } 594 #endif 595 596 /* 597 * Operating register get/set access routines 598 */ 599 600 uint32_t bge_reg_get32(bge_t *bgep, bge_regno_t regno); 601 #pragma inline(bge_reg_get32) 602 603 uint32_t 604 bge_reg_get32(bge_t *bgep, bge_regno_t regno) 605 { 606 BGE_TRACE(("bge_reg_get32($%p, 0x%lx)", 607 (void *)bgep, regno)); 608 609 return (ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno))); 610 } 611 612 void bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data); 613 #pragma inline(bge_reg_put32) 614 615 void 616 bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data) 617 { 618 BGE_TRACE(("bge_reg_put32($%p, 0x%lx, 0x%x)", 619 (void *)bgep, regno, data)); 620 621 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), data); 622 BGE_PCICHK(bgep); 623 } 624 625 void bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 626 #pragma inline(bge_reg_set32) 627 628 void 629 bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 630 { 631 uint32_t regval; 632 633 BGE_TRACE(("bge_reg_set32($%p, 0x%lx, 0x%x)", 634 (void *)bgep, regno, bits)); 635 636 regval = bge_reg_get32(bgep, regno); 637 regval |= bits; 638 bge_reg_put32(bgep, regno, regval); 639 } 640 641 void bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 642 #pragma inline(bge_reg_clr32) 643 644 void 645 bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 646 { 647 uint32_t regval; 648 649 BGE_TRACE(("bge_reg_clr32($%p, 0x%lx, 0x%x)", 650 (void *)bgep, regno, bits)); 651 652 regval = bge_reg_get32(bgep, regno); 653 regval &= ~bits; 654 bge_reg_put32(bgep, regno, regval); 655 } 656 657 static uint64_t bge_reg_get64(bge_t *bgep, bge_regno_t regno); 658 #pragma inline(bge_reg_get64) 659 660 static uint64_t 661 bge_reg_get64(bge_t *bgep, bge_regno_t regno) 662 { 663 uint64_t regval; 664 665 #ifdef __amd64 666 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || 667 bge_get_em64t_type() || 668 DEVICE_5717_SERIES_CHIPSETS(bgep) || 669 DEVICE_5725_SERIES_CHIPSETS(bgep)) { 670 regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4)); 671 regval <<= 32; 672 regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 673 } else { 674 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 675 } 676 #elif defined(__sparc) 677 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || 678 DEVICE_5717_SERIES_CHIPSETS(bgep) || 679 DEVICE_5725_SERIES_CHIPSETS(bgep)) { 680 regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 681 regval <<= 32; 682 regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4)); 683 } else { 684 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 685 } 686 #else 687 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 688 #endif 689 690 #ifdef _LITTLE_ENDIAN 691 regval = (regval >> 32) | (regval << 32); 692 #endif /* _LITTLE_ENDIAN */ 693 694 BGE_TRACE(("bge_reg_get64($%p, 0x%lx) = 0x%016llx", 695 (void *)bgep, regno, regval)); 696 697 return (regval); 698 } 699 700 static void bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data); 701 #pragma inline(bge_reg_put64) 702 703 static void 704 bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data) 705 { 706 BGE_TRACE(("bge_reg_put64($%p, 0x%lx, 0x%016llx)", 707 (void *)bgep, regno, data)); 708 709 #ifdef _LITTLE_ENDIAN 710 data = ((data >> 32) | (data << 32)); 711 #endif /* _LITTLE_ENDIAN */ 712 713 #ifdef __amd64 714 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || 715 bge_get_em64t_type() || 716 DEVICE_5717_SERIES_CHIPSETS(bgep) || 717 DEVICE_5725_SERIES_CHIPSETS(bgep)) { 718 ddi_put32(bgep->io_handle, 719 PIO_ADDR(bgep, regno), (uint32_t)data); 720 BGE_PCICHK(bgep); 721 ddi_put32(bgep->io_handle, 722 PIO_ADDR(bgep, regno + 4), (uint32_t)(data >> 32)); 723 724 } else { 725 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 726 } 727 #elif defined(__sparc) 728 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || 729 DEVICE_5717_SERIES_CHIPSETS(bgep) || 730 DEVICE_5725_SERIES_CHIPSETS(bgep)) { 731 ddi_put32(bgep->io_handle, 732 PIO_ADDR(bgep, regno + 4), (uint32_t)data); 733 BGE_PCICHK(bgep); 734 ddi_put32(bgep->io_handle, 735 PIO_ADDR(bgep, regno), (uint32_t)(data >> 32)); 736 } else { 737 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 738 } 739 #else 740 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 741 #endif 742 743 BGE_PCICHK(bgep); 744 } 745 746 /* 747 * The DDI doesn't provide get/put functions for 128 bit data 748 * so we put RCBs out as two 64-bit chunks instead. 749 */ 750 static void bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 751 #pragma inline(bge_reg_putrcb) 752 753 static void 754 bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 755 { 756 uint64_t *p; 757 758 BGE_TRACE(("bge_reg_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 759 (void *)bgep, addr, rcbp->host_ring_addr, 760 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 761 762 ASSERT((addr % sizeof (*rcbp)) == 0); 763 764 p = (void *)rcbp; 765 bge_reg_put64(bgep, addr, *p++); 766 bge_reg_put64(bgep, addr+8, *p); 767 } 768 769 void bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data); 770 #pragma inline(bge_mbx_put) 771 772 void 773 bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data) 774 { 775 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) 776 regno += INTERRUPT_LP_MBOX_0_REG - INTERRUPT_MBOX_0_REG + 4; 777 778 BGE_TRACE(("bge_mbx_put($%p, 0x%lx, 0x%016llx)", 779 (void *)bgep, regno, data)); 780 781 /* 782 * Mailbox registers are nominally 64 bits on the 5701, but 783 * the MSW isn't used. On the 5703, they're only 32 bits 784 * anyway. So here we just write the lower(!) 32 bits - 785 * remembering that the chip is big-endian, even though the 786 * PCI bus is little-endian ... 787 */ 788 #ifdef _BIG_ENDIAN 789 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno+4), (uint32_t)data); 790 #else 791 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), (uint32_t)data); 792 #endif /* _BIG_ENDIAN */ 793 BGE_PCICHK(bgep); 794 } 795 796 uint32_t bge_mbx_get(bge_t *bgep, bge_regno_t regno); 797 #pragma inline(bge_mbx_get) 798 799 uint32_t 800 bge_mbx_get(bge_t *bgep, bge_regno_t regno) 801 { 802 uint32_t val32; 803 804 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) 805 regno += INTERRUPT_LP_MBOX_0_REG - INTERRUPT_MBOX_0_REG + 4; 806 807 BGE_TRACE(("bge_mbx_get($%p, 0x%lx)", 808 (void *)bgep, regno)); 809 810 #ifdef _BIG_ENDIAN 811 val32 = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno+4)); 812 #else 813 val32 = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 814 #endif /* _BIG_ENDIAN */ 815 BGE_PCICHK(bgep); 816 817 BGE_DEBUG(("bge_mbx_get($%p, 0x%lx) => 0x%08x", 818 (void *)bgep, regno, val32)); 819 820 return (val32); 821 } 822 823 824 #if BGE_DEBUGGING 825 826 void bge_led_mark(bge_t *bgep); 827 #pragma no_inline(bge_led_mark) 828 829 void 830 bge_led_mark(bge_t *bgep) 831 { 832 uint32_t led_ctrl = LED_CONTROL_OVERRIDE_LINK | 833 LED_CONTROL_1000MBPS_LED | 834 LED_CONTROL_100MBPS_LED | 835 LED_CONTROL_10MBPS_LED; 836 837 /* 838 * Blink all three LINK LEDs on simultaneously, then all off, 839 * then restore to automatic hardware control. This is used 840 * in laboratory testing to trigger a logic analyser or scope. 841 */ 842 bge_reg_set32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 843 led_ctrl ^= LED_CONTROL_OVERRIDE_LINK; 844 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 845 led_ctrl = LED_CONTROL_OVERRIDE_LINK; 846 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 847 } 848 849 #endif /* BGE_DEBUGGING */ 850 851 /* 852 * NIC on-chip memory access routines 853 * 854 * Only 32K of NIC memory is visible at a time, controlled by the 855 * Memory Window Base Address Register (in PCI config space). Once 856 * this is set, the 32K region of NIC-local memory that it refers 857 * to can be directly addressed in the upper 32K of the 64K of PCI 858 * memory space used for the device. 859 */ 860 861 static void bge_nic_setwin(bge_t *bgep, bge_regno_t base); 862 #pragma inline(bge_nic_setwin) 863 864 static void 865 bge_nic_setwin(bge_t *bgep, bge_regno_t base) 866 { 867 chip_id_t *cidp; 868 869 BGE_TRACE(("bge_nic_setwin($%p, 0x%lx)", 870 (void *)bgep, base)); 871 872 ASSERT((base & MWBAR_GRANULE_MASK) == 0); 873 874 /* 875 * Don't do repeated zero data writes, 876 * if the device is BCM5714C/15C. 877 */ 878 cidp = &bgep->chipid; 879 if ((cidp->device == DEVICE_ID_5714C) || 880 (cidp->device == DEVICE_ID_5715C)) { 881 if (bgep->lastWriteZeroData && (base == (bge_regno_t)0)) 882 return; 883 /* Adjust lastWriteZeroData */ 884 bgep->lastWriteZeroData = ((base == (bge_regno_t)0) ? 885 B_TRUE : B_FALSE); 886 } 887 #ifdef __sparc 888 if (DEVICE_5717_SERIES_CHIPSETS(bgep) || 889 DEVICE_5725_SERIES_CHIPSETS(bgep)) { 890 base = LE_32(base); 891 } 892 #endif 893 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, base); 894 } 895 896 static uint32_t bge_nic_get32(bge_t *bgep, bge_regno_t addr); 897 #pragma inline(bge_nic_get32) 898 899 static uint32_t 900 bge_nic_get32(bge_t *bgep, bge_regno_t addr) 901 { 902 uint32_t data; 903 904 #if defined(BGE_IPMI_ASF) && !defined(__sparc) 905 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 906 /* workaround for word swap error */ 907 if (addr & 4) 908 addr = addr - 4; 909 else 910 addr = addr + 4; 911 } 912 #endif 913 914 #ifdef __sparc 915 data = bge_nic_read32(bgep, addr); 916 #else 917 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 918 addr &= MWBAR_GRANULE_MASK; 919 addr += NIC_MEM_WINDOW_OFFSET; 920 921 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 922 #endif 923 924 BGE_TRACE(("bge_nic_get32($%p, 0x%lx) = 0x%08x", 925 (void *)bgep, addr, data)); 926 927 return (data); 928 } 929 930 void bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data); 931 #pragma inline(bge_nic_put32) 932 933 void 934 bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data) 935 { 936 BGE_TRACE(("bge_nic_put32($%p, 0x%lx, 0x%08x)", 937 (void *)bgep, addr, data)); 938 939 #if defined(BGE_IPMI_ASF) && !defined(__sparc) 940 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 941 /* workaround for word swap error */ 942 if (addr & 4) 943 addr = addr - 4; 944 else 945 addr = addr + 4; 946 } 947 #endif 948 949 #ifdef __sparc 950 if (DEVICE_5717_SERIES_CHIPSETS(bgep) || 951 DEVICE_5725_SERIES_CHIPSETS(bgep)) { 952 addr = LE_32(addr); 953 } 954 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr); 955 data = LE_32(data); 956 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR, data); 957 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0); 958 #else 959 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 960 addr &= MWBAR_GRANULE_MASK; 961 addr += NIC_MEM_WINDOW_OFFSET; 962 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), data); 963 BGE_PCICHK(bgep); 964 #endif 965 } 966 967 static uint64_t bge_nic_get64(bge_t *bgep, bge_regno_t addr); 968 #pragma inline(bge_nic_get64) 969 970 static uint64_t 971 bge_nic_get64(bge_t *bgep, bge_regno_t addr) 972 { 973 uint64_t data; 974 975 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 976 addr &= MWBAR_GRANULE_MASK; 977 addr += NIC_MEM_WINDOW_OFFSET; 978 979 #ifdef __amd64 980 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || 981 bge_get_em64t_type() || 982 DEVICE_5717_SERIES_CHIPSETS(bgep) || 983 DEVICE_5725_SERIES_CHIPSETS(bgep)) { 984 data = ddi_get32(bgep->io_handle, 985 PIO_ADDR(bgep, addr + 4)); 986 data <<= 32; 987 data |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 988 } else { 989 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 990 } 991 #elif defined(__sparc) 992 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || 993 DEVICE_5717_SERIES_CHIPSETS(bgep) || 994 DEVICE_5725_SERIES_CHIPSETS(bgep)) { 995 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 996 data <<= 32; 997 data |= ddi_get32(bgep->io_handle, 998 PIO_ADDR(bgep, addr + 4)); 999 } else { 1000 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 1001 } 1002 #else 1003 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 1004 #endif 1005 1006 BGE_TRACE(("bge_nic_get64($%p, 0x%lx) = 0x%016llx", 1007 (void *)bgep, addr, data)); 1008 1009 return (data); 1010 } 1011 1012 static void bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data); 1013 #pragma inline(bge_nic_put64) 1014 1015 static void 1016 bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data) 1017 { 1018 BGE_TRACE(("bge_nic_put64($%p, 0x%lx, 0x%016llx)", 1019 (void *)bgep, addr, data)); 1020 1021 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 1022 addr &= MWBAR_GRANULE_MASK; 1023 addr += NIC_MEM_WINDOW_OFFSET; 1024 1025 #ifdef __amd64 1026 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || 1027 bge_get_em64t_type() || 1028 DEVICE_5717_SERIES_CHIPSETS(bgep) || 1029 DEVICE_5725_SERIES_CHIPSETS(bgep)) { 1030 ddi_put32(bgep->io_handle, 1031 PIO_ADDR(bgep, addr + 4), (uint32_t)data); 1032 BGE_PCICHK(bgep); 1033 ddi_put32(bgep->io_handle, 1034 PIO_ADDR(bgep, addr), (uint32_t)(data >> 32)); 1035 } else { 1036 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 1037 } 1038 #elif defined(__sparc) 1039 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || 1040 DEVICE_5717_SERIES_CHIPSETS(bgep) || 1041 DEVICE_5725_SERIES_CHIPSETS(bgep)) { 1042 ddi_put32(bgep->io_handle, 1043 PIO_ADDR(bgep, addr + 4), (uint32_t)data); 1044 BGE_PCICHK(bgep); 1045 ddi_put32(bgep->io_handle, 1046 PIO_ADDR(bgep, addr), (uint32_t)(data >> 32)); 1047 } else { 1048 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 1049 } 1050 #else 1051 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 1052 #endif 1053 1054 BGE_PCICHK(bgep); 1055 } 1056 1057 /* 1058 * The DDI doesn't provide get/put functions for 128 bit data 1059 * so we put RCBs out as two 64-bit chunks instead. 1060 */ 1061 static void bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 1062 #pragma inline(bge_nic_putrcb) 1063 1064 static void 1065 bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 1066 { 1067 uint64_t *p; 1068 1069 BGE_TRACE(("bge_nic_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 1070 (void *)bgep, addr, rcbp->host_ring_addr, 1071 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 1072 1073 ASSERT((addr % sizeof (*rcbp)) == 0); 1074 1075 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 1076 addr &= MWBAR_GRANULE_MASK; 1077 addr += NIC_MEM_WINDOW_OFFSET; 1078 1079 p = (void *)rcbp; 1080 #ifdef __amd64 1081 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || 1082 bge_get_em64t_type() || 1083 DEVICE_5717_SERIES_CHIPSETS(bgep) || 1084 DEVICE_5725_SERIES_CHIPSETS(bgep)) { 1085 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), 1086 (uint32_t)(*p)); 1087 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4), 1088 (uint32_t)(*p++ >> 32)); 1089 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8), 1090 (uint32_t)(*p)); 1091 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12), 1092 (uint32_t)(*p >> 32)); 1093 1094 } else { 1095 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 1096 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr+8), *p); 1097 } 1098 #elif defined(__sparc) 1099 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || 1100 DEVICE_5717_SERIES_CHIPSETS(bgep) || 1101 DEVICE_5725_SERIES_CHIPSETS(bgep)) { 1102 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4), 1103 (uint32_t)(*p)); 1104 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), 1105 (uint32_t)(*p++ >> 32)); 1106 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12), 1107 (uint32_t)(*p)); 1108 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8), 1109 (uint32_t)(*p >> 32)); 1110 } else { 1111 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 1112 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p); 1113 } 1114 #else 1115 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 1116 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p); 1117 #endif 1118 1119 BGE_PCICHK(bgep); 1120 } 1121 1122 static void bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes); 1123 #pragma inline(bge_nic_zero) 1124 1125 static void 1126 bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes) 1127 { 1128 BGE_TRACE(("bge_nic_zero($%p, 0x%lx, 0x%x)", 1129 (void *)bgep, addr, nbytes)); 1130 1131 ASSERT((addr & ~MWBAR_GRANULE_MASK) == 1132 ((addr+nbytes) & ~MWBAR_GRANULE_MASK)); 1133 1134 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 1135 addr &= MWBAR_GRANULE_MASK; 1136 addr += NIC_MEM_WINDOW_OFFSET; 1137 1138 (void) ddi_device_zero(bgep->io_handle, PIO_ADDR(bgep, addr), 1139 nbytes, 1, DDI_DATA_SZ08_ACC); 1140 BGE_PCICHK(bgep); 1141 } 1142 1143 /* 1144 * MII (PHY) register get/set access routines 1145 * 1146 * These use the chip's MII auto-access method, controlled by the 1147 * MII Communication register at 0x044c, so the CPU doesn't have 1148 * to fiddle with the individual bits. 1149 */ 1150 1151 #undef BGE_DBG 1152 #define BGE_DBG BGE_DBG_MII /* debug flag for this code */ 1153 1154 static uint16_t bge_mii_access(bge_t *bgep, bge_regno_t regno, 1155 uint16_t data, uint32_t cmd); 1156 #pragma no_inline(bge_mii_access) 1157 1158 static uint16_t 1159 bge_mii_access(bge_t *bgep, bge_regno_t regno, uint16_t data, uint32_t cmd) 1160 { 1161 uint32_t timeout; 1162 uint32_t regval1; 1163 uint32_t regval2; 1164 1165 BGE_TRACE(("bge_mii_access($%p, 0x%lx, 0x%x, 0x%x)", 1166 (void *)bgep, regno, data, cmd)); 1167 1168 ASSERT(mutex_owned(bgep->genlock)); 1169 1170 /* 1171 * Assemble the command ... 1172 */ 1173 cmd |= data << MI_COMMS_DATA_SHIFT; 1174 cmd |= regno << MI_COMMS_REGISTER_SHIFT; 1175 cmd |= bgep->phy_mii_addr << MI_COMMS_ADDRESS_SHIFT; 1176 cmd |= MI_COMMS_START; 1177 1178 /* 1179 * Wait for any command already in progress ... 1180 * 1181 * Note: this *shouldn't* ever find that there is a command 1182 * in progress, because we already hold the <genlock> mutex. 1183 * Nonetheless, we have sometimes seen the MI_COMMS_START 1184 * bit set here -- it seems that the chip can initiate MII 1185 * accesses internally, even with polling OFF. 1186 */ 1187 regval1 = regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1188 for (timeout = 100; ; ) { 1189 if ((regval2 & MI_COMMS_START) == 0) { 1190 bge_reg_put32(bgep, MI_COMMS_REG, cmd); 1191 break; 1192 } 1193 if (--timeout == 0) 1194 break; 1195 drv_usecwait(10); 1196 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1197 } 1198 1199 if (timeout == 0) 1200 return ((uint16_t)~0u); 1201 1202 if (timeout != 100) 1203 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1204 "MI_COMMS_START set for %d us; 0x%x->0x%x", 1205 cmd, 10*(100-timeout), regval1, regval2)); 1206 1207 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1208 for (timeout = 1000; ; ) { 1209 if ((regval1 & MI_COMMS_START) == 0) 1210 break; 1211 if (--timeout == 0) 1212 break; 1213 drv_usecwait(10); 1214 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1215 } 1216 1217 /* 1218 * Drop out early if the READ FAILED bit is set -- this chip 1219 * could be a 5703/4S, with a SerDes instead of a PHY! 1220 */ 1221 if (regval2 & MI_COMMS_READ_FAILED) 1222 return ((uint16_t)~0u); 1223 1224 if (timeout == 0) 1225 return ((uint16_t)~0u); 1226 1227 /* 1228 * The PRM says to wait 5us after seeing the START bit clear 1229 * and then re-read the register to get the final value of the 1230 * data field, in order to avoid a race condition where the 1231 * START bit is clear but the data field isn't yet valid. 1232 * 1233 * Note: we don't actually seem to be encounter this race; 1234 * except when the START bit is seen set again (see below), 1235 * the data field doesn't change during this 5us interval. 1236 */ 1237 drv_usecwait(5); 1238 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1239 1240 /* 1241 * Unfortunately, when following the PRMs instructions above, 1242 * we have occasionally seen the START bit set again(!) in the 1243 * value read after the 5us delay. This seems to be due to the 1244 * chip autonomously starting another MII access internally. 1245 * In such cases, the command/data/etc fields relate to the 1246 * internal command, rather than the one that we thought had 1247 * just finished. So in this case, we fall back to returning 1248 * the data from the original read that showed START clear. 1249 */ 1250 if (regval2 & MI_COMMS_START) { 1251 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1252 "MI_COMMS_START set after transaction; 0x%x->0x%x", 1253 cmd, regval1, regval2)); 1254 regval2 = regval1; 1255 } 1256 1257 if (regval2 & MI_COMMS_START) 1258 return ((uint16_t)~0u); 1259 1260 if (regval2 & MI_COMMS_READ_FAILED) 1261 return ((uint16_t)~0u); 1262 1263 return ((regval2 & MI_COMMS_DATA_MASK) >> MI_COMMS_DATA_SHIFT); 1264 } 1265 1266 uint16_t bge_mii_get16(bge_t *bgep, bge_regno_t regno); 1267 #pragma no_inline(bge_mii_get16) 1268 1269 uint16_t 1270 bge_mii_get16(bge_t *bgep, bge_regno_t regno) 1271 { 1272 BGE_TRACE(("bge_mii_get16($%p, 0x%lx)", 1273 (void *)bgep, regno)); 1274 1275 ASSERT(mutex_owned(bgep->genlock)); 1276 1277 if (DEVICE_5906_SERIES_CHIPSETS(bgep) && ((regno == MII_AUX_CONTROL) || 1278 (regno == MII_MSCONTROL))) 1279 return (0); 1280 1281 return (bge_mii_access(bgep, regno, 0, MI_COMMS_COMMAND_READ)); 1282 } 1283 1284 void bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data); 1285 #pragma no_inline(bge_mii_put16) 1286 1287 void 1288 bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data) 1289 { 1290 BGE_TRACE(("bge_mii_put16($%p, 0x%lx, 0x%x)", 1291 (void *)bgep, regno, data)); 1292 1293 ASSERT(mutex_owned(bgep->genlock)); 1294 1295 if (DEVICE_5906_SERIES_CHIPSETS(bgep) && ((regno == MII_AUX_CONTROL) || 1296 (regno == MII_MSCONTROL))) 1297 return; 1298 1299 (void) bge_mii_access(bgep, regno, data, MI_COMMS_COMMAND_WRITE); 1300 } 1301 1302 uint16_t 1303 bge_phydsp_read(bge_t *bgep, bge_regno_t regno) 1304 { 1305 BGE_TRACE(("bge_phydsp_read($%p, 0x%lx)", 1306 (void *)bgep, regno)); 1307 1308 ASSERT(mutex_owned(bgep->genlock)); 1309 1310 bge_mii_put16(bgep, MII_DSP_ADDRESS, regno); 1311 return bge_mii_get16(bgep, MII_DSP_RW_PORT); 1312 } 1313 1314 #pragma no_inline(bge_phydsp_write) 1315 1316 void 1317 bge_phydsp_write(bge_t *bgep, bge_regno_t regno, uint16_t data) 1318 { 1319 BGE_TRACE(("bge_phydsp_write($%p, 0x%lx, 0x%x)", 1320 (void *)bgep, regno, data)); 1321 1322 ASSERT(mutex_owned(bgep->genlock)); 1323 1324 bge_mii_put16(bgep, MII_DSP_ADDRESS, regno); 1325 bge_mii_put16(bgep, MII_DSP_RW_PORT, data); 1326 } 1327 1328 #undef BGE_DBG 1329 #define BGE_DBG BGE_DBG_SEEPROM /* debug flag for this code */ 1330 1331 #if BGE_SEE_IO32 || BGE_FLASH_IO32 1332 1333 /* 1334 * Basic SEEPROM get/set access routine 1335 * 1336 * This uses the chip's SEEPROM auto-access method, controlled by the 1337 * Serial EEPROM Address/Data Registers at 0x6838/683c, so the CPU 1338 * doesn't have to fiddle with the individual bits. 1339 * 1340 * The caller should hold <genlock> and *also* have already acquired 1341 * the right to access the SEEPROM, via bge_nvmem_acquire() above. 1342 * 1343 * Return value: 1344 * 0 on success, 1345 * ENODATA on access timeout (maybe retryable: device may just be busy) 1346 * EPROTO on other h/w or s/w errors. 1347 * 1348 * <*dp> is an input to a SEEPROM_ACCESS_WRITE operation, or an output 1349 * from a (successful) SEEPROM_ACCESS_READ. 1350 */ 1351 static int bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1352 uint32_t *dp); 1353 #pragma no_inline(bge_seeprom_access) 1354 1355 static int 1356 bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1357 { 1358 uint32_t tries; 1359 uint32_t regval; 1360 1361 ASSERT(mutex_owned(bgep->genlock)); 1362 1363 /* 1364 * On the newer chips that support both SEEPROM & Flash, we need 1365 * to specifically enable SEEPROM access (Flash is the default). 1366 * On older chips, we don't; SEEPROM is the only NVtype supported, 1367 * and the NVM control registers don't exist ... 1368 */ 1369 switch (bgep->chipid.nvtype) { 1370 case BGE_NVTYPE_NONE: 1371 case BGE_NVTYPE_UNKNOWN: 1372 _NOTE(NOTREACHED) 1373 case BGE_NVTYPE_SEEPROM: 1374 break; 1375 1376 case BGE_NVTYPE_LEGACY_SEEPROM: 1377 case BGE_NVTYPE_UNBUFFERED_FLASH: 1378 case BGE_NVTYPE_BUFFERED_FLASH: 1379 default: 1380 bge_reg_set32(bgep, NVM_CONFIG1_REG, 1381 NVM_CFG1_LEGACY_SEEPROM_MODE); 1382 break; 1383 } 1384 1385 /* 1386 * Check there's no command in progress. 1387 * 1388 * Note: this *shouldn't* ever find that there is a command 1389 * in progress, because we already hold the <genlock> mutex. 1390 * Also, to ensure we don't have a conflict with the chip's 1391 * internal firmware or a process accessing the same (shared) 1392 * SEEPROM through the other port of a 5704, we've already 1393 * been through the "software arbitration" protocol. 1394 * So this is just a final consistency check: we shouldn't 1395 * see EITHER the START bit (command started but not complete) 1396 * OR the COMPLETE bit (command completed but not cleared). 1397 */ 1398 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1399 if (regval & SEEPROM_ACCESS_START) 1400 return (EPROTO); 1401 if (regval & SEEPROM_ACCESS_COMPLETE) 1402 return (EPROTO); 1403 1404 /* 1405 * Assemble the command ... 1406 */ 1407 cmd |= addr & SEEPROM_ACCESS_ADDRESS_MASK; 1408 addr >>= SEEPROM_ACCESS_ADDRESS_SIZE; 1409 addr <<= SEEPROM_ACCESS_DEVID_SHIFT; 1410 cmd |= addr & SEEPROM_ACCESS_DEVID_MASK; 1411 cmd |= SEEPROM_ACCESS_START; 1412 cmd |= SEEPROM_ACCESS_COMPLETE; 1413 cmd |= regval & SEEPROM_ACCESS_HALFCLOCK_MASK; 1414 1415 bge_reg_put32(bgep, SERIAL_EEPROM_DATA_REG, *dp); 1416 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, cmd); 1417 1418 /* 1419 * By observation, a successful access takes ~20us on a 5703/4, 1420 * but apparently much longer (up to 1000us) on the obsolescent 1421 * BCM5700/BCM5701. We want to be sure we don't get any false 1422 * timeouts here; but OTOH, we don't want a bogus access to lock 1423 * out interrupts for longer than necessary. So we'll allow up 1424 * to 1000us ... 1425 */ 1426 for (tries = 0; tries < 1000; ++tries) { 1427 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1428 if (regval & SEEPROM_ACCESS_COMPLETE) 1429 break; 1430 drv_usecwait(1); 1431 } 1432 1433 if (regval & SEEPROM_ACCESS_COMPLETE) { 1434 /* 1435 * All OK; read the SEEPROM data register, then write back 1436 * the value read from the address register in order to 1437 * clear the <complete> bit and leave the SEEPROM access 1438 * state machine idle, ready for the next access ... 1439 */ 1440 BGE_DEBUG(("bge_seeprom_access: complete after %d us", tries)); 1441 *dp = bge_reg_get32(bgep, SERIAL_EEPROM_DATA_REG); 1442 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, regval); 1443 return (0); 1444 } 1445 1446 /* 1447 * Hmm ... what happened here? 1448 * 1449 * Most likely, the user addressed a non-existent SEEPROM. Or 1450 * maybe the SEEPROM was busy internally (e.g. processing a write) 1451 * and didn't respond to being addressed. Either way, it's left 1452 * the SEEPROM access state machine wedged. So we'll reset it 1453 * before we leave, so it's ready for next time ... 1454 */ 1455 BGE_DEBUG(("bge_seeprom_access: timed out after %d us", tries)); 1456 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 1457 return (ENODATA); 1458 } 1459 1460 /* 1461 * Basic Flash get/set access routine 1462 * 1463 * These use the chip's Flash auto-access method, controlled by the 1464 * Flash Access Registers at 0x7000-701c, so the CPU doesn't have to 1465 * fiddle with the individual bits. 1466 * 1467 * The caller should hold <genlock> and *also* have already acquired 1468 * the right to access the Flash, via bge_nvmem_acquire() above. 1469 * 1470 * Return value: 1471 * 0 on success, 1472 * ENODATA on access timeout (maybe retryable: device may just be busy) 1473 * ENODEV if the NVmem device is missing or otherwise unusable 1474 * 1475 * <*dp> is an input to a NVM_FLASH_CMD_WR operation, or an output 1476 * from a (successful) NVM_FLASH_CMD_RD. 1477 */ 1478 static int bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1479 uint32_t *dp); 1480 #pragma no_inline(bge_flash_access) 1481 1482 static int 1483 bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1484 { 1485 uint32_t tries; 1486 uint32_t regval; 1487 1488 ASSERT(mutex_owned(bgep->genlock)); 1489 1490 /* 1491 * On the newer chips that support both SEEPROM & Flash, we need 1492 * to specifically disable SEEPROM access while accessing Flash. 1493 * The older chips don't support Flash, and the NVM registers don't 1494 * exist, so we shouldn't be here at all! 1495 */ 1496 switch (bgep->chipid.nvtype) { 1497 case BGE_NVTYPE_NONE: 1498 case BGE_NVTYPE_UNKNOWN: 1499 _NOTE(NOTREACHED) 1500 case BGE_NVTYPE_SEEPROM: 1501 return (ENODEV); 1502 1503 case BGE_NVTYPE_LEGACY_SEEPROM: 1504 case BGE_NVTYPE_UNBUFFERED_FLASH: 1505 case BGE_NVTYPE_BUFFERED_FLASH: 1506 default: 1507 bge_reg_clr32(bgep, NVM_CONFIG1_REG, 1508 NVM_CFG1_LEGACY_SEEPROM_MODE); 1509 break; 1510 } 1511 1512 /* 1513 * Assemble the command ... 1514 */ 1515 addr &= NVM_FLASH_ADDR_MASK; 1516 cmd |= NVM_FLASH_CMD_DOIT; 1517 cmd |= NVM_FLASH_CMD_FIRST; 1518 cmd |= NVM_FLASH_CMD_LAST; 1519 cmd |= NVM_FLASH_CMD_DONE; 1520 1521 bge_reg_put32(bgep, NVM_FLASH_WRITE_REG, *dp); 1522 bge_reg_put32(bgep, NVM_FLASH_ADDR_REG, addr); 1523 bge_reg_put32(bgep, NVM_FLASH_CMD_REG, cmd); 1524 1525 /* 1526 * Allow up to 1000ms ... 1527 */ 1528 for (tries = 0; tries < 1000; ++tries) { 1529 regval = bge_reg_get32(bgep, NVM_FLASH_CMD_REG); 1530 if (regval & NVM_FLASH_CMD_DONE) 1531 break; 1532 drv_usecwait(1); 1533 } 1534 1535 if (regval & NVM_FLASH_CMD_DONE) { 1536 /* 1537 * All OK; read the data from the Flash read register 1538 */ 1539 BGE_DEBUG(("bge_flash_access: complete after %d us", tries)); 1540 *dp = bge_reg_get32(bgep, NVM_FLASH_READ_REG); 1541 return (0); 1542 } 1543 1544 /* 1545 * Hmm ... what happened here? 1546 * 1547 * Most likely, the user addressed a non-existent Flash. Or 1548 * maybe the Flash was busy internally (e.g. processing a write) 1549 * and didn't respond to being addressed. Either way, there's 1550 * nothing we can here ... 1551 */ 1552 BGE_DEBUG(("bge_flash_access: timed out after %d us", tries)); 1553 return (ENODATA); 1554 } 1555 1556 /* 1557 * The next two functions regulate access to the NVram (if fitted). 1558 * 1559 * On a 5704 (dual core) chip, there's only one SEEPROM and one Flash 1560 * (SPI) interface, but they can be accessed through either port. These 1561 * are managed by different instance of this driver and have no software 1562 * state in common. 1563 * 1564 * In addition (and even on a single core chip) the chip's internal 1565 * firmware can access the SEEPROM/Flash, most notably after a RESET 1566 * when it may download code to run internally. 1567 * 1568 * So we need to arbitrate between these various software agents. For 1569 * this purpose, the chip provides the Software Arbitration Register, 1570 * which implements hardware(!) arbitration. 1571 * 1572 * This functionality didn't exist on older (5700/5701) chips, so there's 1573 * nothing we can do by way of arbitration on those; also, if there's no 1574 * SEEPROM/Flash fitted (or we couldn't determine what type), there's also 1575 * nothing to do. 1576 * 1577 * The internal firmware appears to use Request 0, which is the highest 1578 * priority. So we'd like to use Request 2, leaving one higher and one 1579 * lower for any future developments ... but apparently this doesn't 1580 * always work. So for now, the code uses Request 1 ;-( 1581 */ 1582 1583 #define NVM_READ_REQ NVM_READ_REQ1 1584 #define NVM_RESET_REQ NVM_RESET_REQ1 1585 #define NVM_SET_REQ NVM_SET_REQ1 1586 1587 static void bge_nvmem_relinquish(bge_t *bgep); 1588 #pragma no_inline(bge_nvmem_relinquish) 1589 1590 static void 1591 bge_nvmem_relinquish(bge_t *bgep) 1592 { 1593 ASSERT(mutex_owned(bgep->genlock)); 1594 1595 switch (bgep->chipid.nvtype) { 1596 case BGE_NVTYPE_NONE: 1597 case BGE_NVTYPE_UNKNOWN: 1598 _NOTE(NOTREACHED) 1599 return; 1600 1601 case BGE_NVTYPE_SEEPROM: 1602 /* 1603 * No arbitration performed, no release needed 1604 */ 1605 return; 1606 1607 case BGE_NVTYPE_LEGACY_SEEPROM: 1608 case BGE_NVTYPE_UNBUFFERED_FLASH: 1609 case BGE_NVTYPE_BUFFERED_FLASH: 1610 default: 1611 break; 1612 } 1613 1614 /* 1615 * Our own request should be present (whether or not granted) ... 1616 */ 1617 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1618 1619 /* 1620 * ... this will make it go away. 1621 */ 1622 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_RESET_REQ); 1623 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1624 } 1625 1626 /* 1627 * Arbitrate for access to the NVmem, if necessary 1628 * 1629 * Return value: 1630 * 0 on success 1631 * EAGAIN if the device is in use (retryable) 1632 * ENODEV if the NVmem device is missing or otherwise unusable 1633 */ 1634 static int bge_nvmem_acquire(bge_t *bgep); 1635 #pragma no_inline(bge_nvmem_acquire) 1636 1637 static int 1638 bge_nvmem_acquire(bge_t *bgep) 1639 { 1640 uint32_t regval; 1641 uint32_t tries; 1642 1643 ASSERT(mutex_owned(bgep->genlock)); 1644 1645 switch (bgep->chipid.nvtype) { 1646 case BGE_NVTYPE_NONE: 1647 case BGE_NVTYPE_UNKNOWN: 1648 /* 1649 * Access denied: no (recognisable) device fitted 1650 */ 1651 return (ENODEV); 1652 1653 case BGE_NVTYPE_SEEPROM: 1654 /* 1655 * Access granted: no arbitration needed (or possible) 1656 */ 1657 return (0); 1658 1659 case BGE_NVTYPE_LEGACY_SEEPROM: 1660 case BGE_NVTYPE_UNBUFFERED_FLASH: 1661 case BGE_NVTYPE_BUFFERED_FLASH: 1662 default: 1663 /* 1664 * Access conditional: conduct arbitration protocol 1665 */ 1666 break; 1667 } 1668 1669 /* 1670 * We're holding the per-port mutex <genlock>, so no-one other 1671 * thread can be attempting to access the NVmem through *this* 1672 * port. But it could be in use by the *other* port (of a 5704), 1673 * or by the chip's internal firmware, so we have to go through 1674 * the full (hardware) arbitration protocol ... 1675 * 1676 * Note that *because* we're holding <genlock>, the interrupt handler 1677 * won't be able to progress. So we're only willing to spin for a 1678 * fairly short time. Specifically: 1679 * 1680 * We *must* wait long enough for the hardware to resolve all 1681 * requests and determine the winner. Fortunately, this is 1682 * "almost instantaneous", even as observed by GHz CPUs. 1683 * 1684 * A successful access by another Solaris thread (via either 1685 * port) typically takes ~20us. So waiting a bit longer than 1686 * that will give a good chance of success, if the other user 1687 * *is* another thread on the other port. 1688 * 1689 * However, the internal firmware can hold on to the NVmem 1690 * for *much* longer: at least 10 milliseconds just after a 1691 * RESET, and maybe even longer if the NVmem actually contains 1692 * code to download and run on the internal CPUs. 1693 * 1694 * So, we'll allow 50us; if that's not enough then it's up to the 1695 * caller to retry later (hence the choice of return code EAGAIN). 1696 */ 1697 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1698 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_SET_REQ); 1699 1700 for (tries = 0; tries < 50; ++tries) { 1701 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1702 if (regval & NVM_WON_REQ1) 1703 break; 1704 drv_usecwait(1); 1705 } 1706 1707 if (regval & NVM_WON_REQ1) { 1708 BGE_DEBUG(("bge_nvmem_acquire: won after %d us", tries)); 1709 return (0); 1710 } 1711 1712 /* 1713 * Somebody else must be accessing the NVmem, so abandon our 1714 * attempt take control of it. The caller can try again later ... 1715 */ 1716 BGE_DEBUG(("bge_nvmem_acquire: lost after %d us", tries)); 1717 bge_nvmem_relinquish(bgep); 1718 return (EAGAIN); 1719 } 1720 1721 /* 1722 * This code assumes that the GPIO1 bit has been wired up to the NVmem 1723 * write protect line in such a way that the NVmem is protected when 1724 * GPIO1 is an input, or is an output but driven high. Thus, to make the 1725 * NVmem writable we have to change GPIO1 to an output AND drive it low. 1726 * 1727 * Note: there's only one set of GPIO pins on a 5704, even though they 1728 * can be accessed through either port. So the chip has to resolve what 1729 * happens if the two ports program a single pin differently ... the rule 1730 * it uses is that if the ports disagree about the *direction* of a pin, 1731 * "output" wins over "input", but if they disagree about its *value* as 1732 * an output, then the pin is TRISTATED instead! In such a case, no-one 1733 * wins, and the external signal does whatever the external circuitry 1734 * defines as the default -- which we've assumed is the PROTECTED state. 1735 * So, we always change GPIO1 back to being an *input* whenever we're not 1736 * specifically using it to unprotect the NVmem. This allows either port 1737 * to update the NVmem, although obviously only one at a time! 1738 * 1739 * The caller should hold <genlock> and *also* have already acquired the 1740 * right to access the NVmem, via bge_nvmem_acquire() above. 1741 */ 1742 static void bge_nvmem_protect(bge_t *bgep, boolean_t protect); 1743 #pragma inline(bge_nvmem_protect) 1744 1745 static void 1746 bge_nvmem_protect(bge_t *bgep, boolean_t protect) 1747 { 1748 uint32_t regval; 1749 1750 ASSERT(mutex_owned(bgep->genlock)); 1751 1752 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 1753 if (protect) { 1754 regval |= MLCR_MISC_PINS_OUTPUT_1; 1755 regval &= ~MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1756 } else { 1757 regval &= ~MLCR_MISC_PINS_OUTPUT_1; 1758 regval |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1759 } 1760 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, regval); 1761 } 1762 1763 /* 1764 * Now put it all together ... 1765 * 1766 * Try to acquire control of the NVmem; if successful, then: 1767 * unprotect it (if we want to write to it) 1768 * perform the requested access 1769 * reprotect it (after a write) 1770 * relinquish control 1771 * 1772 * Return value: 1773 * 0 on success, 1774 * EAGAIN if the device is in use (retryable) 1775 * ENODATA on access timeout (maybe retryable: device may just be busy) 1776 * ENODEV if the NVmem device is missing or otherwise unusable 1777 * EPROTO on other h/w or s/w errors. 1778 */ 1779 static int 1780 bge_nvmem_rw32(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1781 { 1782 int err; 1783 1784 if ((err = bge_nvmem_acquire(bgep)) == 0) { 1785 switch (cmd) { 1786 case BGE_SEE_READ: 1787 err = bge_seeprom_access(bgep, 1788 SEEPROM_ACCESS_READ, addr, dp); 1789 break; 1790 1791 case BGE_SEE_WRITE: 1792 bge_nvmem_protect(bgep, B_FALSE); 1793 err = bge_seeprom_access(bgep, 1794 SEEPROM_ACCESS_WRITE, addr, dp); 1795 bge_nvmem_protect(bgep, B_TRUE); 1796 break; 1797 1798 case BGE_FLASH_READ: 1799 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1800 DEVICE_5723_SERIES_CHIPSETS(bgep) || 1801 DEVICE_5717_SERIES_CHIPSETS(bgep) || 1802 DEVICE_5725_SERIES_CHIPSETS(bgep) || 1803 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1804 bge_reg_set32(bgep, NVM_ACCESS_REG, 1805 NVM_ACCESS_ENABLE); 1806 } 1807 err = bge_flash_access(bgep, 1808 NVM_FLASH_CMD_RD, addr, dp); 1809 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1810 DEVICE_5723_SERIES_CHIPSETS(bgep) || 1811 DEVICE_5717_SERIES_CHIPSETS(bgep) || 1812 DEVICE_5725_SERIES_CHIPSETS(bgep) || 1813 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1814 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1815 NVM_ACCESS_ENABLE); 1816 } 1817 break; 1818 1819 case BGE_FLASH_WRITE: 1820 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1821 DEVICE_5723_SERIES_CHIPSETS(bgep) || 1822 DEVICE_5717_SERIES_CHIPSETS(bgep) || 1823 DEVICE_5725_SERIES_CHIPSETS(bgep) || 1824 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1825 bge_reg_set32(bgep, NVM_ACCESS_REG, 1826 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1827 } 1828 bge_nvmem_protect(bgep, B_FALSE); 1829 err = bge_flash_access(bgep, 1830 NVM_FLASH_CMD_WR, addr, dp); 1831 bge_nvmem_protect(bgep, B_TRUE); 1832 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1833 DEVICE_5723_SERIES_CHIPSETS(bgep) || 1834 DEVICE_5717_SERIES_CHIPSETS(bgep) || 1835 DEVICE_5725_SERIES_CHIPSETS(bgep) || 1836 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1837 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1838 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1839 } 1840 1841 break; 1842 1843 default: 1844 _NOTE(NOTREACHED) 1845 break; 1846 } 1847 bge_nvmem_relinquish(bgep); 1848 } 1849 1850 BGE_DEBUG(("bge_nvmem_rw32: err %d", err)); 1851 return (err); 1852 } 1853 1854 static uint32_t 1855 bge_nvmem_access_cmd(bge_t *bgep, boolean_t read) 1856 { 1857 switch (bgep->chipid.nvtype) { 1858 case BGE_NVTYPE_NONE: 1859 case BGE_NVTYPE_UNKNOWN: 1860 default: 1861 return 0; 1862 1863 case BGE_NVTYPE_SEEPROM: 1864 case BGE_NVTYPE_LEGACY_SEEPROM: 1865 return (read ? BGE_SEE_READ : BGE_SEE_WRITE); 1866 1867 case BGE_NVTYPE_UNBUFFERED_FLASH: 1868 case BGE_NVTYPE_BUFFERED_FLASH: 1869 return (read ? BGE_FLASH_READ : BGE_FLASH_WRITE); 1870 } 1871 } 1872 1873 1874 int 1875 bge_nvmem_read32(bge_t *bgep, bge_regno_t addr, uint32_t *dp) 1876 { 1877 return (bge_nvmem_rw32(bgep, bge_nvmem_access_cmd(bgep, B_TRUE), 1878 addr, dp)); 1879 } 1880 1881 1882 int 1883 bge_nvmem_write32(bge_t *bgep, bge_regno_t addr, uint32_t *dp) 1884 { 1885 return (bge_nvmem_rw32(bgep, bge_nvmem_access_cmd(bgep, B_FALSE), 1886 addr, dp)); 1887 } 1888 1889 1890 /* 1891 * Attempt to get a MAC address from the SEEPROM or Flash, if any 1892 */ 1893 static uint64_t bge_get_nvmac(bge_t *bgep); 1894 #pragma no_inline(bge_get_nvmac) 1895 1896 static uint64_t 1897 bge_get_nvmac(bge_t *bgep) 1898 { 1899 uint32_t mac_high; 1900 uint32_t mac_low; 1901 uint32_t addr; 1902 uint32_t cmd; 1903 uint64_t mac; 1904 1905 BGE_TRACE(("bge_get_nvmac($%p)", 1906 (void *)bgep)); 1907 1908 switch (bgep->chipid.nvtype) { 1909 case BGE_NVTYPE_NONE: 1910 case BGE_NVTYPE_UNKNOWN: 1911 default: 1912 return (0ULL); 1913 1914 case BGE_NVTYPE_SEEPROM: 1915 case BGE_NVTYPE_LEGACY_SEEPROM: 1916 cmd = BGE_SEE_READ; 1917 break; 1918 1919 case BGE_NVTYPE_UNBUFFERED_FLASH: 1920 case BGE_NVTYPE_BUFFERED_FLASH: 1921 cmd = BGE_FLASH_READ; 1922 break; 1923 } 1924 1925 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) 1926 addr = NVMEM_DATA_MAC_ADDRESS_5906; 1927 else 1928 addr = NVMEM_DATA_MAC_ADDRESS; 1929 1930 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_high)) 1931 return (0ULL); 1932 addr += 4; 1933 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_low)) 1934 return (0ULL); 1935 1936 /* 1937 * The Broadcom chip is natively BIG-endian, so that's how the 1938 * MAC address is represented in NVmem. We may need to swap it 1939 * around on a little-endian host ... 1940 */ 1941 #ifdef _BIG_ENDIAN 1942 mac = mac_high; 1943 mac = mac << 32; 1944 mac |= mac_low; 1945 #else 1946 mac = BGE_BSWAP_32(mac_high); 1947 mac = mac << 32; 1948 mac |= BGE_BSWAP_32(mac_low); 1949 #endif /* _BIG_ENDIAN */ 1950 1951 return (mac); 1952 } 1953 1954 #else /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1955 1956 /* 1957 * Dummy version for when we're not supporting NVmem access 1958 */ 1959 static uint64_t bge_get_nvmac(bge_t *bgep); 1960 #pragma inline(bge_get_nvmac) 1961 1962 static uint64_t 1963 bge_get_nvmac(bge_t *bgep) 1964 { 1965 _NOTE(ARGUNUSED(bgep)) 1966 return (0ULL); 1967 } 1968 1969 #endif /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1970 1971 /* 1972 * Determine the type of NVmem that is (or may be) attached to this chip, 1973 */ 1974 static enum bge_nvmem_type bge_nvmem_id(bge_t *bgep); 1975 #pragma no_inline(bge_nvmem_id) 1976 1977 static enum bge_nvmem_type 1978 bge_nvmem_id(bge_t *bgep) 1979 { 1980 enum bge_nvmem_type nvtype; 1981 uint32_t config1; 1982 1983 BGE_TRACE(("bge_nvmem_id($%p)", 1984 (void *)bgep)); 1985 1986 switch (bgep->chipid.device) { 1987 default: 1988 /* 1989 * We shouldn't get here; it means we don't recognise 1990 * the chip, which means we don't know how to determine 1991 * what sort of NVmem (if any) it has. So we'll say 1992 * NONE, to disable the NVmem access code ... 1993 */ 1994 nvtype = BGE_NVTYPE_NONE; 1995 break; 1996 1997 case DEVICE_ID_5700: 1998 case DEVICE_ID_5700x: 1999 case DEVICE_ID_5701: 2000 /* 2001 * These devices support *only* SEEPROMs 2002 */ 2003 nvtype = BGE_NVTYPE_SEEPROM; 2004 break; 2005 2006 case DEVICE_ID_5702: 2007 case DEVICE_ID_5702fe: 2008 case DEVICE_ID_5703C: 2009 case DEVICE_ID_5703S: 2010 case DEVICE_ID_5704C: 2011 case DEVICE_ID_5704S: 2012 case DEVICE_ID_5704: 2013 case DEVICE_ID_5705M: 2014 case DEVICE_ID_5705C: 2015 case DEVICE_ID_5705_2: 2016 case DEVICE_ID_5717: 2017 case DEVICE_ID_5718: 2018 case DEVICE_ID_5719: 2019 case DEVICE_ID_5720: 2020 case DEVICE_ID_5724: 2021 case DEVICE_ID_5725: 2022 case DEVICE_ID_5727: 2023 case DEVICE_ID_57780: 2024 case DEVICE_ID_5780: 2025 case DEVICE_ID_5782: 2026 case DEVICE_ID_5785: 2027 case DEVICE_ID_5787: 2028 case DEVICE_ID_5787M: 2029 case DEVICE_ID_5788: 2030 case DEVICE_ID_5789: 2031 case DEVICE_ID_5751: 2032 case DEVICE_ID_5751M: 2033 case DEVICE_ID_5752: 2034 case DEVICE_ID_5752M: 2035 case DEVICE_ID_5754: 2036 case DEVICE_ID_5755: 2037 case DEVICE_ID_5755M: 2038 case DEVICE_ID_5756M: 2039 case DEVICE_ID_5721: 2040 case DEVICE_ID_5722: 2041 case DEVICE_ID_5723: 2042 case DEVICE_ID_5761: 2043 case DEVICE_ID_5761E: 2044 case DEVICE_ID_5764: 2045 case DEVICE_ID_5714C: 2046 case DEVICE_ID_5714S: 2047 case DEVICE_ID_5715C: 2048 case DEVICE_ID_5715S: 2049 config1 = bge_reg_get32(bgep, NVM_CONFIG1_REG); 2050 if (config1 & NVM_CFG1_FLASH_MODE) 2051 if (config1 & NVM_CFG1_BUFFERED_MODE) 2052 nvtype = BGE_NVTYPE_BUFFERED_FLASH; 2053 else 2054 nvtype = BGE_NVTYPE_UNBUFFERED_FLASH; 2055 else 2056 nvtype = BGE_NVTYPE_LEGACY_SEEPROM; 2057 break; 2058 case DEVICE_ID_5906: 2059 case DEVICE_ID_5906M: 2060 nvtype = BGE_NVTYPE_BUFFERED_FLASH; 2061 break; 2062 } 2063 2064 return (nvtype); 2065 } 2066 2067 #undef BGE_DBG 2068 #define BGE_DBG BGE_DBG_APE /* debug flag for this code */ 2069 2070 uint32_t bge_ape_get32(bge_t *bgep, bge_regno_t regno); 2071 #pragma inline(bge_ape_get32) 2072 2073 uint32_t 2074 bge_ape_get32(bge_t *bgep, bge_regno_t regno) 2075 { 2076 BGE_TRACE(("bge_ape_get32($%p, 0x%lx)", 2077 (void *)bgep, regno)); 2078 2079 return (ddi_get32(bgep->ape_handle, APE_ADDR(bgep, regno))); 2080 } 2081 2082 void bge_ape_put32(bge_t *bgep, bge_regno_t regno, uint32_t data); 2083 #pragma inline(bge_ape_put32) 2084 2085 void 2086 bge_ape_put32(bge_t *bgep, bge_regno_t regno, uint32_t data) 2087 { 2088 BGE_TRACE(("bge_ape_put32($%p, 0x%lx, 0x%x)", 2089 (void *)bgep, regno, data)); 2090 2091 ddi_put32(bgep->ape_handle, APE_ADDR(bgep, regno), data); 2092 BGE_PCICHK(bgep); 2093 } 2094 2095 void 2096 bge_ape_lock_init(bge_t *bgep) 2097 { 2098 int i; 2099 uint32_t regbase; 2100 uint32_t bit; 2101 2102 BGE_TRACE(("bge_ape_lock_init($%p)", (void *)bgep)); 2103 2104 if (bgep->chipid.device == DEVICE_ID_5761) 2105 regbase = BGE_APE_LOCK_GRANT; 2106 else 2107 regbase = BGE_APE_PER_LOCK_GRANT; 2108 2109 /* Make sure the driver hasn't any stale locks. */ 2110 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) { 2111 switch (i) { 2112 case BGE_APE_LOCK_PHY0: 2113 case BGE_APE_LOCK_PHY1: 2114 case BGE_APE_LOCK_PHY2: 2115 case BGE_APE_LOCK_PHY3: 2116 bit = APE_LOCK_GRANT_DRIVER; 2117 break; 2118 default: 2119 if (!bgep->pci_func) 2120 bit = APE_LOCK_GRANT_DRIVER; 2121 else 2122 bit = 1 << bgep->pci_func; 2123 } 2124 bge_ape_put32(bgep, regbase + 4 * i, bit); 2125 } 2126 } 2127 2128 static int 2129 bge_ape_lock(bge_t *bgep, int locknum) 2130 { 2131 int i, off; 2132 int ret = 0; 2133 uint32_t status; 2134 uint32_t req; 2135 uint32_t gnt; 2136 uint32_t bit; 2137 2138 BGE_TRACE(("bge_ape_lock($%p, 0x%x)", (void *)bgep, locknum)); 2139 2140 if (!bgep->ape_enabled) 2141 return (0); 2142 2143 switch (locknum) { 2144 case BGE_APE_LOCK_GPIO: 2145 if (bgep->chipid.device == DEVICE_ID_5761) 2146 return (0); 2147 case BGE_APE_LOCK_GRC: 2148 case BGE_APE_LOCK_MEM: 2149 if (!bgep->pci_func) 2150 bit = APE_LOCK_REQ_DRIVER; 2151 else 2152 bit = 1 << bgep->pci_func; 2153 break; 2154 case BGE_APE_LOCK_PHY0: 2155 case BGE_APE_LOCK_PHY1: 2156 case BGE_APE_LOCK_PHY2: 2157 case BGE_APE_LOCK_PHY3: 2158 bit = APE_LOCK_REQ_DRIVER; 2159 break; 2160 default: 2161 return (-1); 2162 } 2163 2164 if (bgep->chipid.device == DEVICE_ID_5761) { 2165 req = BGE_APE_LOCK_REQ; 2166 gnt = BGE_APE_LOCK_GRANT; 2167 } else { 2168 req = BGE_APE_PER_LOCK_REQ; 2169 gnt = BGE_APE_PER_LOCK_GRANT; 2170 } 2171 2172 off = 4 * locknum; 2173 2174 bge_ape_put32(bgep, req + off, bit); 2175 2176 /* Wait for up to 1 millisecond to acquire lock. */ 2177 for (i = 0; i < 100; i++) { 2178 status = bge_ape_get32(bgep, gnt + off); 2179 if (status == bit) 2180 break; 2181 drv_usecwait(10); 2182 } 2183 2184 if (status != bit) { 2185 /* Revoke the lock request. */ 2186 bge_ape_put32(bgep, gnt + off, bit); 2187 ret = -1; 2188 } 2189 2190 return (ret); 2191 } 2192 2193 static void 2194 bge_ape_unlock(bge_t *bgep, int locknum) 2195 { 2196 uint32_t gnt; 2197 uint32_t bit; 2198 2199 BGE_TRACE(("bge_ape_unlock($%p, 0x%x)", (void *)bgep, locknum)); 2200 2201 if (!bgep->ape_enabled) 2202 return; 2203 2204 switch (locknum) { 2205 case BGE_APE_LOCK_GPIO: 2206 if (bgep->chipid.device == DEVICE_ID_5761) 2207 return; 2208 case BGE_APE_LOCK_GRC: 2209 case BGE_APE_LOCK_MEM: 2210 if (!bgep->pci_func) 2211 bit = APE_LOCK_GRANT_DRIVER; 2212 else 2213 bit = 1 << bgep->pci_func; 2214 break; 2215 case BGE_APE_LOCK_PHY0: 2216 case BGE_APE_LOCK_PHY1: 2217 case BGE_APE_LOCK_PHY2: 2218 case BGE_APE_LOCK_PHY3: 2219 bit = APE_LOCK_GRANT_DRIVER; 2220 break; 2221 default: 2222 return; 2223 } 2224 2225 if (bgep->chipid.device == DEVICE_ID_5761) 2226 gnt = BGE_APE_LOCK_GRANT; 2227 else 2228 gnt = BGE_APE_PER_LOCK_GRANT; 2229 2230 bge_ape_put32(bgep, gnt + 4 * locknum, bit); 2231 } 2232 2233 /* wait for pending event to finish, if successful returns with MEM locked */ 2234 static int 2235 bge_ape_event_lock(bge_t *bgep, uint32_t timeout_us) 2236 { 2237 uint32_t apedata; 2238 2239 BGE_TRACE(("bge_ape_event_lock($%p, %d)", (void *)bgep, timeout_us)); 2240 2241 ASSERT(timeout_us > 0); 2242 2243 while (timeout_us) { 2244 if (bge_ape_lock(bgep, BGE_APE_LOCK_MEM)) 2245 return (-1); 2246 2247 apedata = bge_ape_get32(bgep, BGE_APE_EVENT_STATUS); 2248 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) 2249 break; 2250 2251 bge_ape_unlock(bgep, BGE_APE_LOCK_MEM); 2252 2253 drv_usecwait(10); 2254 timeout_us -= (timeout_us > 10) ? 10 : timeout_us; 2255 } 2256 2257 return (timeout_us ? 0 : -1); 2258 } 2259 2260 /* wait for pending event to finish, returns non-zero if not finished */ 2261 static int 2262 bge_ape_wait_for_event(bge_t *bgep, uint32_t timeout_us) 2263 { 2264 uint32_t i; 2265 uint32_t apedata; 2266 2267 BGE_TRACE(("bge_ape_wait_for_event($%p, %d)", (void *)bgep, timeout_us)); 2268 2269 ASSERT(timeout_us > 0); 2270 2271 for (i = 0; i < timeout_us / 10; i++) { 2272 apedata = bge_ape_get32(bgep, BGE_APE_EVENT_STATUS); 2273 2274 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) 2275 break; 2276 2277 drv_usecwait(10); 2278 } 2279 2280 return (i == timeout_us / 10); 2281 } 2282 2283 int 2284 bge_ape_scratchpad_read(bge_t *bgep, uint32_t *data, uint32_t base_off, 2285 uint32_t lenToRead) 2286 { 2287 int err; 2288 uint32_t i; 2289 uint32_t bufoff; 2290 uint32_t msgoff; 2291 uint32_t maxlen; 2292 uint32_t apedata; 2293 2294 BGE_TRACE(("bge_ape_scratchpad_read($%p, %p, 0x%0x, %d)", 2295 (void *)bgep, (void*)data, base_off, lenToRead)); 2296 2297 if (!bgep->ape_has_ncsi) 2298 return (0); 2299 2300 apedata = bge_ape_get32(bgep, BGE_APE_SEG_SIG); 2301 if (apedata != APE_SEG_SIG_MAGIC) 2302 return (-1); 2303 2304 apedata = bge_ape_get32(bgep, BGE_APE_FW_STATUS); 2305 if (!(apedata & APE_FW_STATUS_READY)) 2306 return (-1); 2307 2308 bufoff = (bge_ape_get32(bgep, BGE_APE_SEG_MSG_BUF_OFF) + 2309 BGE_APE_SHMEM_BASE); 2310 msgoff = bufoff + 2 * sizeof(uint32_t); 2311 maxlen = bge_ape_get32(bgep, BGE_APE_SEG_MSG_BUF_LEN); 2312 2313 while (lenToRead) { 2314 uint32_t transferLen; 2315 2316 /* Cap xfer sizes to scratchpad limits. */ 2317 transferLen = (lenToRead > maxlen) ? maxlen : lenToRead; 2318 lenToRead -= transferLen; 2319 2320 apedata = bge_ape_get32(bgep, BGE_APE_FW_STATUS); 2321 if (!(apedata & APE_FW_STATUS_READY)) 2322 return (-1); 2323 2324 /* Wait for up to 1 millisecond for APE to service previous event. */ 2325 err = bge_ape_event_lock(bgep, 1000); 2326 if (err) 2327 return (err); 2328 2329 apedata = (APE_EVENT_STATUS_DRIVER_EVNT | 2330 APE_EVENT_STATUS_SCRTCHPD_READ | 2331 APE_EVENT_STATUS_EVENT_PENDING); 2332 bge_ape_put32(bgep, BGE_APE_EVENT_STATUS, apedata); 2333 2334 bge_ape_put32(bgep, bufoff, base_off); 2335 bge_ape_put32(bgep, bufoff + sizeof(uint32_t), transferLen); 2336 2337 bge_ape_unlock(bgep, BGE_APE_LOCK_MEM); 2338 bge_ape_put32(bgep, BGE_APE_EVENT, APE_EVENT_1); 2339 2340 base_off += transferLen; 2341 2342 if (bge_ape_wait_for_event(bgep, 30000)) 2343 return (-1); 2344 2345 for (i = 0; transferLen; i += 4, transferLen -= 4) { 2346 uint32_t val = bge_ape_get32(bgep, msgoff + i); 2347 memcpy(data, &val, sizeof(uint32_t)); 2348 data++; 2349 } 2350 } 2351 2352 return (0); 2353 } 2354 2355 int 2356 bge_ape_scratchpad_write(bge_t *bgep, uint32_t dstoff, uint32_t *data, 2357 uint32_t lenToWrite) 2358 { 2359 int err; 2360 uint32_t i; 2361 uint32_t bufoff; 2362 uint32_t msgoff; 2363 uint32_t maxlen; 2364 uint32_t apedata; 2365 2366 BGE_TRACE(("bge_ape_scratchpad_write($%p, %d, %p, %d)", 2367 (void *)bgep, dstoff, data, lenToWrite)); 2368 2369 if (!bgep->ape_has_ncsi) 2370 return (0); 2371 2372 apedata = bge_ape_get32(bgep, BGE_APE_SEG_SIG); 2373 if (apedata != APE_SEG_SIG_MAGIC) 2374 return (-1); 2375 2376 apedata = bge_ape_get32(bgep, BGE_APE_FW_STATUS); 2377 if (!(apedata & APE_FW_STATUS_READY)) 2378 return (-1); 2379 2380 bufoff = (bge_ape_get32(bgep, BGE_APE_SEG_MSG_BUF_OFF) + 2381 BGE_APE_SHMEM_BASE); 2382 msgoff = bufoff + 2 * sizeof(uint32_t); 2383 maxlen = bge_ape_get32(bgep, BGE_APE_SEG_MSG_BUF_LEN); 2384 2385 while (lenToWrite) { 2386 uint32_t transferLen; 2387 2388 /* Cap xfer sizes to scratchpad limits. */ 2389 transferLen = (lenToWrite > maxlen) ? maxlen : lenToWrite; 2390 lenToWrite -= transferLen; 2391 2392 /* Wait for up to 1 millisecond for 2393 * APE to service previous event. 2394 */ 2395 err = bge_ape_event_lock(bgep, 1000); 2396 if (err) 2397 return (err); 2398 2399 bge_ape_put32(bgep, bufoff, dstoff); 2400 bge_ape_put32(bgep, bufoff + sizeof(uint32_t), transferLen); 2401 apedata = msgoff; 2402 2403 dstoff += transferLen; 2404 2405 for (i = 0; transferLen; i += 4, transferLen -= 4) { 2406 bge_ape_put32(bgep, apedata, *data++); 2407 apedata += sizeof(uint32_t); 2408 } 2409 2410 apedata = (APE_EVENT_STATUS_DRIVER_EVNT | 2411 APE_EVENT_STATUS_SCRTCHPD_WRITE | 2412 APE_EVENT_STATUS_EVENT_PENDING); 2413 bge_ape_put32(bgep, BGE_APE_EVENT_STATUS, apedata); 2414 2415 bge_ape_unlock(bgep, BGE_APE_LOCK_MEM); 2416 bge_ape_put32(bgep, BGE_APE_EVENT, APE_EVENT_1); 2417 } 2418 2419 return (0); 2420 } 2421 2422 static int 2423 bge_ape_send_event(bge_t *bgep, uint32_t event) 2424 { 2425 int err; 2426 uint32_t apedata; 2427 2428 BGE_TRACE(("bge_ape_send_event($%p, %d)", (void *)bgep, event)); 2429 2430 apedata = bge_ape_get32(bgep, BGE_APE_SEG_SIG); 2431 if (apedata != APE_SEG_SIG_MAGIC) 2432 return (-1); 2433 2434 apedata = bge_ape_get32(bgep, BGE_APE_FW_STATUS); 2435 if (!(apedata & APE_FW_STATUS_READY)) 2436 return (-1); 2437 2438 /* Wait for up to 1 millisecond for APE to service previous event. */ 2439 err = bge_ape_event_lock(bgep, 1000); 2440 if (err) 2441 return (err); 2442 2443 bge_ape_put32(bgep, BGE_APE_EVENT_STATUS, 2444 event | APE_EVENT_STATUS_EVENT_PENDING); 2445 2446 bge_ape_unlock(bgep, BGE_APE_LOCK_MEM); 2447 bge_ape_put32(bgep, BGE_APE_EVENT, APE_EVENT_1); 2448 2449 return 0; 2450 } 2451 2452 static void 2453 bge_ape_driver_state_change(bge_t *bgep, int mode) 2454 { 2455 uint32_t event; 2456 uint32_t apedata; 2457 2458 BGE_TRACE(("bge_ape_driver_state_change($%p, %d)", 2459 (void *)bgep, mode)); 2460 2461 if (!bgep->ape_enabled) 2462 return; 2463 2464 switch (mode) { 2465 case BGE_INIT_RESET: 2466 bge_ape_put32(bgep, BGE_APE_HOST_SEG_SIG, 2467 APE_HOST_SEG_SIG_MAGIC); 2468 bge_ape_put32(bgep, BGE_APE_HOST_SEG_LEN, 2469 APE_HOST_SEG_LEN_MAGIC); 2470 apedata = bge_ape_get32(bgep, BGE_APE_HOST_INIT_COUNT); 2471 bge_ape_put32(bgep, BGE_APE_HOST_INIT_COUNT, ++apedata); 2472 bge_ape_put32(bgep, BGE_APE_HOST_DRIVER_ID, 2473 APE_HOST_DRIVER_ID_MAGIC(1, 0)); 2474 bge_ape_put32(bgep, BGE_APE_HOST_BEHAVIOR, 2475 APE_HOST_BEHAV_NO_PHYLOCK); 2476 bge_ape_put32(bgep, BGE_APE_HOST_DRVR_STATE, 2477 BGE_APE_HOST_DRVR_STATE_START); 2478 2479 event = APE_EVENT_STATUS_STATE_START; 2480 break; 2481 case BGE_SHUTDOWN_RESET: 2482 /* With the interface we are currently using, 2483 * APE does not track driver state. Wiping 2484 * out the HOST SEGMENT SIGNATURE forces 2485 * the APE to assume OS absent status. 2486 */ 2487 bge_ape_put32(bgep, BGE_APE_HOST_SEG_SIG, 0x0); 2488 2489 #if 0 2490 if (WOL supported) { 2491 bge_ape_put32(bgep, BGE_APE_HOST_WOL_SPEED, 2492 BGE_APE_HOST_WOL_SPEED_AUTO); 2493 apedata = BGE_APE_HOST_DRVR_STATE_WOL; 2494 } else 2495 #endif 2496 apedata = BGE_APE_HOST_DRVR_STATE_UNLOAD; 2497 2498 bge_ape_put32(bgep, BGE_APE_HOST_DRVR_STATE, apedata); 2499 2500 event = APE_EVENT_STATUS_STATE_UNLOAD; 2501 break; 2502 case BGE_SUSPEND_RESET: 2503 event = APE_EVENT_STATUS_STATE_SUSPEND; 2504 break; 2505 default: 2506 return; 2507 } 2508 2509 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE; 2510 2511 bge_ape_send_event(bgep, event); 2512 } 2513 2514 #undef BGE_DBG 2515 #define BGE_DBG BGE_DBG_CHIP /* debug flag for this code */ 2516 2517 static void 2518 bge_init_recv_rule(bge_t *bgep) 2519 { 2520 bge_recv_rule_t *rulep = bgep->recv_rules; 2521 uint32_t i; 2522 2523 /* 2524 * Initialize receive rule registers. 2525 * Note that rules may persist across each bge_m_start/stop() call. 2526 */ 2527 for (i = 0; i < RECV_RULES_NUM_MAX; i++, rulep++) { 2528 bge_reg_put32(bgep, RECV_RULE_MASK_REG(i), rulep->mask_value); 2529 bge_reg_put32(bgep, RECV_RULE_CONTROL_REG(i), rulep->control); 2530 } 2531 } 2532 2533 /* 2534 * Using the values captured by bge_chip_cfg_init(), and additional probes 2535 * as required, characterise the chip fully: determine the label by which 2536 * to refer to this chip, the correct settings for various registers, and 2537 * of course whether the device and/or subsystem are supported! 2538 */ 2539 int bge_chip_id_init(bge_t *bgep); 2540 #pragma no_inline(bge_chip_id_init) 2541 2542 int 2543 bge_chip_id_init(bge_t *bgep) 2544 { 2545 char buf[MAXPATHLEN]; /* any risk of stack overflow? */ 2546 boolean_t dev_ok; 2547 chip_id_t *cidp; 2548 uint32_t subid; 2549 char *devname; 2550 char *sysname; 2551 int *ids; 2552 int err; 2553 uint_t i; 2554 2555 dev_ok = B_FALSE; 2556 cidp = &bgep->chipid; 2557 2558 /* 2559 * Check the PCI device ID to determine the generic chip type and 2560 * select parameters that depend on this. 2561 * 2562 * Note: because the SPARC platforms in general don't fit the 2563 * SEEPROM 'behind' the chip, the PCI revision ID register reads 2564 * as zero - which is why we use <asic_rev> rather than <revision> 2565 * below ... 2566 * 2567 * Note: in general we can't distinguish between the Copper/SerDes 2568 * versions by ID alone, as some Copper devices (e.g. some but not 2569 * all 5703Cs) have the same ID as the SerDes equivalents. So we 2570 * treat them the same here, and the MII code works out the media 2571 * type later on ... 2572 */ 2573 cidp->mbuf_base = bge_mbuf_pool_base; 2574 cidp->mbuf_length = bge_mbuf_pool_len; 2575 cidp->recv_slots = BGE_RECV_SLOTS_USED; 2576 cidp->bge_dma_rwctrl = bge_dma_rwctrl; 2577 cidp->pci_type = BGE_PCI_X; 2578 cidp->statistic_type = BGE_STAT_BLK; 2579 cidp->mbuf_lo_water_rdma = bge_mbuf_lo_water_rdma; 2580 cidp->mbuf_lo_water_rmac = bge_mbuf_lo_water_rmac; 2581 cidp->mbuf_hi_water = bge_mbuf_hi_water; 2582 cidp->rx_ticks_norm = bge_rx_ticks_norm; 2583 cidp->rx_count_norm = bge_rx_count_norm; 2584 cidp->tx_ticks_norm = bge_tx_ticks_norm; 2585 cidp->tx_count_norm = bge_tx_count_norm; 2586 cidp->mask_pci_int = MHCR_MASK_PCI_INT_OUTPUT; 2587 2588 if (cidp->rx_rings == 0 || cidp->rx_rings > BGE_RECV_RINGS_MAX) 2589 cidp->rx_rings = BGE_RECV_RINGS_DEFAULT; 2590 if (cidp->tx_rings == 0 || cidp->tx_rings > BGE_SEND_RINGS_MAX) 2591 cidp->tx_rings = BGE_SEND_RINGS_DEFAULT; 2592 2593 cidp->msi_enabled = B_FALSE; 2594 2595 switch (cidp->device) { 2596 case DEVICE_ID_5717: 2597 case DEVICE_ID_5718: 2598 case DEVICE_ID_5719: 2599 case DEVICE_ID_5720: 2600 case DEVICE_ID_5724: 2601 case DEVICE_ID_5725: 2602 case DEVICE_ID_5727: 2603 if (cidp->device == DEVICE_ID_5717) { 2604 cidp->chip_label = 5717; 2605 } else if (cidp->device == DEVICE_ID_5718) { 2606 cidp->chip_label = 5718; 2607 } else if (cidp->device == DEVICE_ID_5719) { 2608 cidp->chip_label = 5719; 2609 } else if (cidp->device == DEVICE_ID_5720) { 2610 if (pci_config_get16(bgep->cfg_handle, PCI_CONF_DEVID) == 2611 DEVICE_ID_5717_C0) { 2612 cidp->chip_label = 5717; 2613 } else { 2614 cidp->chip_label = 5720; 2615 } 2616 } else if (cidp->device == DEVICE_ID_5724) { 2617 cidp->chip_label = 5724; 2618 } else if (cidp->device == DEVICE_ID_5725) { 2619 cidp->chip_label = 5725; 2620 } else /* (cidp->device == DEVICE_ID_5727) */ { 2621 cidp->chip_label = 5727; 2622 } 2623 cidp->msi_enabled = bge_enable_msi; 2624 #ifdef __sparc 2625 cidp->mask_pci_int = LE_32(MHCR_MASK_PCI_INT_OUTPUT); 2626 #endif 2627 cidp->bge_dma_rwctrl = LE_32(PDRWCR_VAR_5717); 2628 cidp->pci_type = BGE_PCI_E; 2629 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2630 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5717; 2631 cidp->mbuf_hi_water = MBUF_HIWAT_5717; 2632 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2633 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2634 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2635 cidp->bge_mlcr_default = MLCR_DEFAULT_5717; 2636 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2637 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2638 cidp->statistic_type = BGE_STAT_REG; 2639 dev_ok = B_TRUE; 2640 break; 2641 2642 case DEVICE_ID_5700: 2643 case DEVICE_ID_5700x: 2644 cidp->chip_label = 5700; 2645 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2646 break; 2647 2648 case DEVICE_ID_5701: 2649 cidp->chip_label = 5701; 2650 dev_ok = B_TRUE; 2651 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2652 break; 2653 2654 case DEVICE_ID_5702: 2655 case DEVICE_ID_5702fe: 2656 cidp->chip_label = 5702; 2657 dev_ok = B_TRUE; 2658 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2659 cidp->pci_type = BGE_PCI; 2660 break; 2661 2662 case DEVICE_ID_5703C: 2663 case DEVICE_ID_5703S: 2664 case DEVICE_ID_5703: 2665 /* 2666 * Revision A0 of the 5703/5793 had various errata 2667 * that we can't or don't work around, so it's not 2668 * supported, but all later versions are 2669 */ 2670 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5793 : 5703; 2671 if (bgep->chipid.asic_rev != MHCR_CHIP_REV_5703_A0) 2672 dev_ok = B_TRUE; 2673 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2674 break; 2675 2676 case DEVICE_ID_5704C: 2677 case DEVICE_ID_5704S: 2678 case DEVICE_ID_5704: 2679 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5794 : 5704; 2680 cidp->mbuf_base = bge_mbuf_pool_base_5704; 2681 cidp->mbuf_length = bge_mbuf_pool_len_5704; 2682 dev_ok = B_TRUE; 2683 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2684 break; 2685 2686 case DEVICE_ID_5705C: 2687 case DEVICE_ID_5705M: 2688 case DEVICE_ID_5705MA3: 2689 case DEVICE_ID_5705F: 2690 case DEVICE_ID_5705_2: 2691 case DEVICE_ID_5754: 2692 if (cidp->device == DEVICE_ID_5754) { 2693 cidp->chip_label = 5754; 2694 cidp->pci_type = BGE_PCI_E; 2695 } else { 2696 cidp->chip_label = 5705; 2697 cidp->pci_type = BGE_PCI; 2698 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2699 } 2700 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2701 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2702 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2703 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2704 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2705 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2706 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2707 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2708 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2709 cidp->statistic_type = BGE_STAT_REG; 2710 dev_ok = B_TRUE; 2711 break; 2712 2713 case DEVICE_ID_5906: 2714 case DEVICE_ID_5906M: 2715 cidp->chip_label = 5906; 2716 cidp->pci_type = BGE_PCI_E; 2717 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5906; 2718 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5906; 2719 cidp->mbuf_hi_water = MBUF_HIWAT_5906; 2720 cidp->mbuf_base = bge_mbuf_pool_base; 2721 cidp->mbuf_length = bge_mbuf_pool_len; 2722 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2723 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2724 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2725 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2726 cidp->statistic_type = BGE_STAT_REG; 2727 dev_ok = B_TRUE; 2728 break; 2729 2730 case DEVICE_ID_5753: 2731 cidp->chip_label = 5753; 2732 cidp->pci_type = BGE_PCI_E; 2733 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2734 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2735 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2736 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2737 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2738 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2739 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2740 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2741 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2742 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2743 cidp->statistic_type = BGE_STAT_REG; 2744 dev_ok = B_TRUE; 2745 break; 2746 2747 case DEVICE_ID_5755: 2748 case DEVICE_ID_5755M: 2749 cidp->chip_label = 5755; 2750 cidp->pci_type = BGE_PCI_E; 2751 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2752 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2753 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2754 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2755 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2756 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2757 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2758 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2759 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2760 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2761 if (cidp->device == DEVICE_ID_5755M) 2762 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2763 cidp->statistic_type = BGE_STAT_REG; 2764 dev_ok = B_TRUE; 2765 break; 2766 2767 case DEVICE_ID_5756M: 2768 /* 2769 * This is nearly identical to the 5755M. 2770 * (Actually reports the 5755 chip ID.) 2771 */ 2772 cidp->chip_label = 5756; 2773 cidp->pci_type = BGE_PCI_E; 2774 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2775 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2776 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2777 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2778 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2779 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2780 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2781 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2782 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2783 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2784 cidp->statistic_type = BGE_STAT_REG; 2785 dev_ok = B_TRUE; 2786 break; 2787 2788 case DEVICE_ID_5787: 2789 case DEVICE_ID_5787M: 2790 cidp->chip_label = 5787; 2791 cidp->pci_type = BGE_PCI_E; 2792 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2793 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2794 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2795 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2796 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2797 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2798 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2799 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2800 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2801 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2802 cidp->statistic_type = BGE_STAT_REG; 2803 dev_ok = B_TRUE; 2804 break; 2805 2806 case DEVICE_ID_5723: 2807 case DEVICE_ID_5761: 2808 case DEVICE_ID_5761E: 2809 case DEVICE_ID_57780: 2810 cidp->msi_enabled = bge_enable_msi; 2811 /* 2812 * We don't use MSI for BCM5764 and BCM5785, as the 2813 * status block may fail to update when the network 2814 * traffic is heavy. 2815 */ 2816 /* FALLTHRU */ 2817 case DEVICE_ID_5785: 2818 case DEVICE_ID_5764: 2819 if (cidp->device == DEVICE_ID_5723) 2820 cidp->chip_label = 5723; 2821 else if (cidp->device == DEVICE_ID_5764) 2822 cidp->chip_label = 5764; 2823 else if (cidp->device == DEVICE_ID_5785) 2824 cidp->chip_label = 5785; 2825 else if (cidp->device == DEVICE_ID_57780) 2826 cidp->chip_label = 57780; 2827 else 2828 cidp->chip_label = 5761; 2829 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2830 cidp->pci_type = BGE_PCI_E; 2831 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2832 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2833 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2834 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2835 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2836 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2837 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2838 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2839 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2840 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2841 cidp->statistic_type = BGE_STAT_REG; 2842 dev_ok = B_TRUE; 2843 break; 2844 2845 /* PCI-X device, identical to 5714 */ 2846 case DEVICE_ID_5780: 2847 cidp->chip_label = 5780; 2848 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2849 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2850 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2851 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2852 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2853 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2854 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2855 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2856 cidp->statistic_type = BGE_STAT_REG; 2857 dev_ok = B_TRUE; 2858 break; 2859 2860 case DEVICE_ID_5782: 2861 /* 2862 * Apart from the label, we treat this as a 5705(?) 2863 */ 2864 cidp->chip_label = 5782; 2865 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2866 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2867 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2868 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2869 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2870 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2871 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2872 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2873 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2874 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2875 cidp->statistic_type = BGE_STAT_REG; 2876 dev_ok = B_TRUE; 2877 break; 2878 2879 case DEVICE_ID_5788: 2880 /* 2881 * Apart from the label, we treat this as a 5705(?) 2882 */ 2883 cidp->chip_label = 5788; 2884 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2885 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2886 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2887 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2888 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2889 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2890 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2891 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2892 cidp->statistic_type = BGE_STAT_REG; 2893 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2894 dev_ok = B_TRUE; 2895 break; 2896 2897 case DEVICE_ID_5714C: 2898 if (cidp->revision >= REVISION_ID_5714_A2) 2899 cidp->msi_enabled = bge_enable_msi; 2900 /* FALLTHRU */ 2901 case DEVICE_ID_5714S: 2902 cidp->chip_label = 5714; 2903 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2904 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2905 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2906 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2907 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2908 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2909 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5714; 2910 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2911 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2912 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2913 cidp->pci_type = BGE_PCI_E; 2914 cidp->statistic_type = BGE_STAT_REG; 2915 dev_ok = B_TRUE; 2916 break; 2917 2918 case DEVICE_ID_5715C: 2919 case DEVICE_ID_5715S: 2920 cidp->chip_label = 5715; 2921 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2922 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2923 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2924 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2925 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2926 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2927 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5715; 2928 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2929 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2930 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2931 cidp->pci_type = BGE_PCI_E; 2932 cidp->statistic_type = BGE_STAT_REG; 2933 if (cidp->revision >= REVISION_ID_5715_A2) 2934 cidp->msi_enabled = bge_enable_msi; 2935 dev_ok = B_TRUE; 2936 break; 2937 2938 case DEVICE_ID_5721: 2939 cidp->chip_label = 5721; 2940 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2941 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2942 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2943 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2944 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2945 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2946 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2947 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2948 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2949 cidp->pci_type = BGE_PCI_E; 2950 cidp->statistic_type = BGE_STAT_REG; 2951 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2952 dev_ok = B_TRUE; 2953 break; 2954 2955 case DEVICE_ID_5722: 2956 cidp->chip_label = 5722; 2957 cidp->pci_type = BGE_PCI_E; 2958 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2959 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2960 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2961 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2962 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2963 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2964 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2965 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2966 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2967 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2968 cidp->statistic_type = BGE_STAT_REG; 2969 dev_ok = B_TRUE; 2970 break; 2971 2972 case DEVICE_ID_5751: 2973 case DEVICE_ID_5751M: 2974 cidp->chip_label = 5751; 2975 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2976 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2977 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2978 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2979 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2980 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2981 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2982 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2983 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2984 cidp->pci_type = BGE_PCI_E; 2985 cidp->statistic_type = BGE_STAT_REG; 2986 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2987 dev_ok = B_TRUE; 2988 break; 2989 2990 case DEVICE_ID_5752: 2991 case DEVICE_ID_5752M: 2992 cidp->chip_label = 5752; 2993 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2994 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2995 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2996 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2997 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2998 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2999 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 3000 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 3001 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 3002 cidp->pci_type = BGE_PCI_E; 3003 cidp->statistic_type = BGE_STAT_REG; 3004 cidp->flags |= CHIP_FLAG_NO_JUMBO; 3005 dev_ok = B_TRUE; 3006 break; 3007 3008 case DEVICE_ID_5789: 3009 cidp->chip_label = 5789; 3010 cidp->mbuf_base = bge_mbuf_pool_base_5721; 3011 cidp->mbuf_length = bge_mbuf_pool_len_5721; 3012 cidp->recv_slots = BGE_RECV_SLOTS_5721; 3013 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 3014 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 3015 cidp->tx_rings = BGE_RECV_RINGS_MAX_5705; 3016 cidp->pci_type = BGE_PCI_E; 3017 cidp->statistic_type = BGE_STAT_REG; 3018 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 3019 cidp->flags |= CHIP_FLAG_NO_JUMBO; 3020 cidp->msi_enabled = B_TRUE; 3021 dev_ok = B_TRUE; 3022 break; 3023 3024 } 3025 3026 /* 3027 * Setup the default jumbo parameter. 3028 */ 3029 cidp->ethmax_size = ETHERMAX; 3030 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_DEFAULT; 3031 cidp->std_buf_size = BGE_STD_BUFF_SIZE; 3032 3033 /* 3034 * If jumbo is enabled and this kind of chipset supports jumbo feature, 3035 * setup below jumbo specific parameters. 3036 * 3037 * For BCM5714/5715, there is only one standard receive ring. So the 3038 * std buffer size should be set to BGE_JUMBO_BUFF_SIZE when jumbo 3039 * feature is enabled. 3040 * 3041 * For the BCM5718 family we hijack the standard receive ring for 3042 * the jumboframe traffic, keeps it simple. 3043 */ 3044 if (!(cidp->flags & CHIP_FLAG_NO_JUMBO) && 3045 (cidp->default_mtu > BGE_DEFAULT_MTU)) { 3046 if (DEVICE_5714_SERIES_CHIPSETS(bgep) || 3047 DEVICE_5717_SERIES_CHIPSETS(bgep) || 3048 DEVICE_5725_SERIES_CHIPSETS(bgep)) { 3049 cidp->mbuf_lo_water_rdma = 3050 RDMA_MBUF_LOWAT_5714_JUMBO; 3051 cidp->mbuf_lo_water_rmac = 3052 MAC_RX_MBUF_LOWAT_5714_JUMBO; 3053 cidp->mbuf_hi_water = MBUF_HIWAT_5714_JUMBO; 3054 cidp->jumbo_slots = 0; 3055 cidp->std_buf_size = BGE_JUMBO_BUFF_SIZE; 3056 } else { 3057 cidp->mbuf_lo_water_rdma = 3058 RDMA_MBUF_LOWAT_JUMBO; 3059 cidp->mbuf_lo_water_rmac = 3060 MAC_RX_MBUF_LOWAT_JUMBO; 3061 cidp->mbuf_hi_water = MBUF_HIWAT_JUMBO; 3062 cidp->jumbo_slots = BGE_JUMBO_SLOTS_USED; 3063 } 3064 cidp->recv_jumbo_size = BGE_JUMBO_BUFF_SIZE; 3065 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_JUMBO; 3066 cidp->ethmax_size = cidp->default_mtu + 3067 sizeof (struct ether_header); 3068 } 3069 3070 /* 3071 * Identify the NV memory type: SEEPROM or Flash? 3072 */ 3073 cidp->nvtype = bge_nvmem_id(bgep); 3074 3075 /* 3076 * Now check what we've discovered: is this truly a supported 3077 * chip on (the motherboard of) a supported platform? 3078 * 3079 * Possible problems here: 3080 * 1) it's a completely unheard-of chip 3081 * 2) it's a recognised but unsupported chip (e.g. 5701, 5703C-A0) 3082 * 3) it's a chip we would support if it were on the motherboard 3083 * of a Sun platform, but this one isn't ;-( 3084 */ 3085 if (cidp->chip_label == 0) 3086 bge_problem(bgep, 3087 "Device 'pci%04x,%04x' not recognized (%d?)", 3088 cidp->vendor, cidp->device, cidp->device); 3089 else if (!dev_ok) 3090 bge_problem(bgep, 3091 "Device 'pci%04x,%04x' (%d) revision %d not supported", 3092 cidp->vendor, cidp->device, cidp->chip_label, 3093 cidp->revision); 3094 else 3095 cidp->flags |= CHIP_FLAG_SUPPORTED; 3096 3097 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 3098 return (EIO); 3099 3100 return (0); 3101 } 3102 3103 void 3104 bge_chip_msi_trig(bge_t *bgep) 3105 { 3106 uint32_t regval; 3107 3108 regval = bgep->param_msi_cnt<<4; 3109 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, regval); 3110 BGE_DEBUG(("bge_chip_msi_trig:data = %d", regval)); 3111 } 3112 3113 /* 3114 * Various registers that control the chip's internal engines (state 3115 * machines) have a <reset> and <enable> bits (fortunately, in the 3116 * same place in each such register :-). 3117 * 3118 * To reset the state machine, the <reset> bit must be written with 1; 3119 * it will then read back as 1 while the reset is in progress, but 3120 * self-clear to 0 when the reset completes. 3121 * 3122 * To enable a state machine, one must set the <enable> bit, which 3123 * will continue to read back as 0 until the state machine is running. 3124 * 3125 * To disable a state machine, the <enable> bit must be cleared, but 3126 * it will continue to read back as 1 until the state machine actually 3127 * stops. 3128 * 3129 * This routine implements polling for completion of a reset, enable 3130 * or disable operation, returning B_TRUE on success (bit reached the 3131 * required state) or B_FALSE on timeout (200*100us == 20ms). 3132 */ 3133 static boolean_t bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 3134 uint32_t mask, uint32_t val); 3135 #pragma no_inline(bge_chip_poll_engine) 3136 3137 static boolean_t 3138 bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 3139 uint32_t mask, uint32_t val) 3140 { 3141 uint32_t regval; 3142 uint32_t n; 3143 3144 BGE_TRACE(("bge_chip_poll_engine($%p, 0x%lx, 0x%x, 0x%x)", 3145 (void *)bgep, regno, mask, val)); 3146 3147 for (n = 200; n; --n) { 3148 regval = bge_reg_get32(bgep, regno); 3149 if ((regval & mask) == val) 3150 return (B_TRUE); 3151 drv_usecwait(100); 3152 } 3153 3154 bge_problem(bgep, "bge_chip_poll_engine failed: regno = 0x%lx", regno); 3155 bge_fm_ereport(bgep, DDI_FM_DEVICE_NO_RESPONSE); 3156 return (B_FALSE); 3157 } 3158 3159 /* 3160 * Various registers that control the chip's internal engines (state 3161 * machines) have a <reset> bit (fortunately, in the same place in 3162 * each such register :-). To reset the state machine, this bit must 3163 * be written with 1; it will then read back as 1 while the reset is 3164 * in progress, but self-clear to 0 when the reset completes. 3165 * 3166 * This code sets the bit, then polls for it to read back as zero. 3167 * The return value is B_TRUE on success (reset bit cleared itself), 3168 * or B_FALSE if the state machine didn't recover :( 3169 * 3170 * NOTE: the Core reset is similar to other resets, except that we 3171 * can't poll for completion, since the Core reset disables memory 3172 * access! So we just have to assume that it will all complete in 3173 * 100us. See Broadcom document 570X-PG102-R, p102, steps 4-5. 3174 */ 3175 static boolean_t bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno); 3176 #pragma no_inline(bge_chip_reset_engine) 3177 3178 static boolean_t 3179 bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno) 3180 { 3181 uint32_t regval; 3182 uint16_t val16; 3183 uint32_t val32; 3184 uint32_t mhcr; 3185 3186 regval = bge_reg_get32(bgep, regno); 3187 3188 BGE_TRACE(("bge_chip_reset_engine($%p, 0x%lx)", 3189 (void *)bgep, regno)); 3190 BGE_DEBUG(("bge_chip_reset_engine: 0x%lx before reset = 0x%08x", 3191 regno, regval)); 3192 3193 regval |= STATE_MACHINE_RESET_BIT; 3194 3195 switch (regno) { 3196 case MISC_CONFIG_REG: 3197 /* 3198 * BCM5714/5721/5751 pcie chip special case. In order to avoid 3199 * resetting PCIE block and bringing PCIE link down, bit 29 3200 * in the register needs to be set first, and then set it again 3201 * while the reset bit is written. 3202 * See:P500 of 57xx-PG102-RDS.pdf. 3203 */ 3204 if (DEVICE_5705_SERIES_CHIPSETS(bgep) || 3205 DEVICE_5717_SERIES_CHIPSETS(bgep) || 3206 DEVICE_5725_SERIES_CHIPSETS(bgep) || 3207 DEVICE_5721_SERIES_CHIPSETS(bgep) || 3208 DEVICE_5723_SERIES_CHIPSETS(bgep) || 3209 DEVICE_5714_SERIES_CHIPSETS(bgep) || 3210 DEVICE_5906_SERIES_CHIPSETS(bgep)) { 3211 regval |= MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE; 3212 if (bgep->chipid.pci_type == BGE_PCI_E) { 3213 if (bgep->chipid.asic_rev == 3214 MHCR_CHIP_REV_5751_A0 || 3215 bgep->chipid.asic_rev == 3216 MHCR_CHIP_REV_5721_A0 || 3217 bgep->chipid.asic_rev == 3218 MHCR_CHIP_REV_5755_A0) { 3219 val32 = bge_reg_get32(bgep, 3220 PHY_TEST_CTRL_REG); 3221 if (val32 == (PHY_PCIE_SCRAM_MODE | 3222 PHY_PCIE_LTASS_MODE)) 3223 bge_reg_put32(bgep, 3224 PHY_TEST_CTRL_REG, 3225 PHY_PCIE_SCRAM_MODE); 3226 val32 = pci_config_get32 3227 (bgep->cfg_handle, 3228 PCI_CONF_BGE_CLKCTL); 3229 val32 |= CLKCTL_PCIE_A0_FIX; 3230 pci_config_put32(bgep->cfg_handle, 3231 PCI_CONF_BGE_CLKCTL, val32); 3232 } 3233 bge_reg_set32(bgep, regno, 3234 MISC_CONFIG_GRC_RESET_DISABLE); 3235 regval |= MISC_CONFIG_GRC_RESET_DISABLE; 3236 } 3237 } 3238 3239 /* 3240 * Special case - causes Core reset 3241 * 3242 * On SPARC v9 we want to ensure that we don't start 3243 * timing until the I/O access has actually reached 3244 * the chip, otherwise we might make the next access 3245 * too early. And we can't just force the write out 3246 * by following it with a read (even to config space) 3247 * because that would cause the fault we're trying 3248 * to avoid. Hence the need for membar_sync() here. 3249 */ 3250 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), regval); 3251 #ifdef __sparcv9 3252 membar_sync(); 3253 #endif /* __sparcv9 */ 3254 /* 3255 * On some platforms,system need about 300us for 3256 * link setup. 3257 */ 3258 drv_usecwait(300); 3259 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) { 3260 bge_reg_set32(bgep, VCPU_STATUS_REG, VCPU_DRV_RESET); 3261 bge_reg_clr32( 3262 bgep, VCPU_EXT_CTL, VCPU_EXT_CTL_HALF); 3263 } 3264 3265 if (bgep->chipid.pci_type == BGE_PCI_E) { 3266 /* PCI-E device need more reset time */ 3267 drv_usecwait(120000); 3268 3269 /* 3270 * (re)Disable interrupts as the bit can be reset after a 3271 * core clock reset. 3272 */ 3273 mhcr = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MHCR); 3274 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, 3275 mhcr | MHCR_MASK_PCI_INT_OUTPUT); 3276 3277 /* Set PCIE max payload size and clear error status. */ 3278 if ((bgep->chipid.chip_label == 5721) || 3279 (bgep->chipid.chip_label == 5751) || 3280 (bgep->chipid.chip_label == 5752) || 3281 (bgep->chipid.chip_label == 5789) || 3282 (bgep->chipid.chip_label == 5906)) { 3283 pci_config_put16(bgep->cfg_handle, 3284 PCI_CONF_DEV_CTRL, READ_REQ_SIZE_MAX); 3285 pci_config_put16(bgep->cfg_handle, 3286 PCI_CONF_DEV_STUS, DEVICE_ERROR_STUS); 3287 } 3288 3289 if ((bgep->chipid.chip_label == 5723) || 3290 (bgep->chipid.chip_label == 5761)) { 3291 pci_config_put16(bgep->cfg_handle, 3292 PCI_CONF_DEV_CTRL_5723, READ_REQ_SIZE_MAX); 3293 pci_config_put16(bgep->cfg_handle, 3294 PCI_CONF_DEV_STUS_5723, DEVICE_ERROR_STUS); 3295 } 3296 3297 if (DEVICE_5717_SERIES_CHIPSETS(bgep) || 3298 DEVICE_5725_SERIES_CHIPSETS(bgep)) { 3299 val16 = pci_config_get16(bgep->cfg_handle, 3300 PCI_CONF_DEV_CTRL_5717); 3301 val16 &= ~READ_REQ_SIZE_MASK; 3302 val16 |= READ_REQ_SIZE_2K; 3303 pci_config_put16(bgep->cfg_handle, 3304 PCI_CONF_DEV_CTRL_5717, val16); 3305 } 3306 } 3307 3308 BGE_PCICHK(bgep); 3309 return (B_TRUE); 3310 3311 default: 3312 bge_reg_put32(bgep, regno, regval); 3313 return (bge_chip_poll_engine(bgep, regno, 3314 STATE_MACHINE_RESET_BIT, 0)); 3315 } 3316 } 3317 3318 /* 3319 * Various registers that control the chip's internal engines (state 3320 * machines) have an <enable> bit (fortunately, in the same place in 3321 * each such register :-). To stop the state machine, this bit must 3322 * be written with 0, then polled to see when the state machine has 3323 * actually stopped. 3324 * 3325 * The return value is B_TRUE on success (enable bit cleared), or 3326 * B_FALSE if the state machine didn't stop :( 3327 */ 3328 static boolean_t bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, 3329 uint32_t morebits); 3330 #pragma no_inline(bge_chip_disable_engine) 3331 3332 static boolean_t 3333 bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 3334 { 3335 uint32_t regval; 3336 3337 BGE_TRACE(("bge_chip_disable_engine($%p, 0x%lx, 0x%x)", 3338 (void *)bgep, regno, morebits)); 3339 3340 switch (regno) { 3341 case FTQ_RESET_REG: 3342 /* 3343 * For Schumacher's bugfix CR6490108 3344 */ 3345 #ifdef BGE_IPMI_ASF 3346 #ifdef BGE_NETCONSOLE 3347 if (bgep->asf_enabled) 3348 return (B_TRUE); 3349 #endif 3350 #endif 3351 /* 3352 * Not quite like the others; it doesn't 3353 * have an <enable> bit, but instead we 3354 * have to set and then clear all the bits 3355 */ 3356 bge_reg_put32(bgep, regno, ~(uint32_t)0); 3357 drv_usecwait(100); 3358 bge_reg_put32(bgep, regno, 0); 3359 return (B_TRUE); 3360 3361 default: 3362 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3363 break; 3364 } 3365 3366 if ((regno == RCV_LIST_SELECTOR_MODE_REG) || 3367 (regno == DMA_COMPLETION_MODE_REG) || 3368 (regno == MBUF_CLUSTER_FREE_MODE_REG) || 3369 (regno == BUFFER_MANAGER_MODE_REG) || 3370 (regno == MEMORY_ARBITER_MODE_REG)) { 3371 return B_TRUE; 3372 } 3373 3374 break; 3375 } 3376 3377 regval = bge_reg_get32(bgep, regno); 3378 regval &= ~STATE_MACHINE_ENABLE_BIT; 3379 regval &= ~morebits; 3380 bge_reg_put32(bgep, regno, regval); 3381 3382 return bge_chip_poll_engine(bgep, regno, STATE_MACHINE_ENABLE_BIT, 0); 3383 } 3384 3385 /* 3386 * Various registers that control the chip's internal engines (state 3387 * machines) have an <enable> bit (fortunately, in the same place in 3388 * each such register :-). To start the state machine, this bit must 3389 * be written with 1, then polled to see when the state machine has 3390 * actually started. 3391 * 3392 * The return value is B_TRUE on success (enable bit set), or 3393 * B_FALSE if the state machine didn't start :( 3394 */ 3395 static boolean_t bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, 3396 uint32_t morebits); 3397 #pragma no_inline(bge_chip_enable_engine) 3398 3399 static boolean_t 3400 bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 3401 { 3402 uint32_t regval; 3403 3404 BGE_TRACE(("bge_chip_enable_engine($%p, 0x%lx, 0x%x)", 3405 (void *)bgep, regno, morebits)); 3406 3407 switch (regno) { 3408 case FTQ_RESET_REG: 3409 #ifdef BGE_IPMI_ASF 3410 #ifdef BGE_NETCONSOLE 3411 if (bgep->asf_enabled) 3412 return (B_TRUE); 3413 #endif 3414 #endif 3415 /* 3416 * Not quite like the others; it doesn't 3417 * have an <enable> bit, but instead we 3418 * have to set and then clear all the bits 3419 */ 3420 bge_reg_put32(bgep, regno, ~(uint32_t)0); 3421 drv_usecwait(100); 3422 bge_reg_put32(bgep, regno, 0); 3423 return (B_TRUE); 3424 3425 default: 3426 regval = bge_reg_get32(bgep, regno); 3427 regval |= STATE_MACHINE_ENABLE_BIT; 3428 regval |= morebits; 3429 bge_reg_put32(bgep, regno, regval); 3430 return (bge_chip_poll_engine(bgep, regno, 3431 STATE_MACHINE_ENABLE_BIT, STATE_MACHINE_ENABLE_BIT)); 3432 } 3433 } 3434 3435 /* 3436 * Reprogram the Ethernet, Transmit, and Receive MAC 3437 * modes to match the param_* variables 3438 */ 3439 void bge_sync_mac_modes(bge_t *bgep); 3440 #pragma no_inline(bge_sync_mac_modes) 3441 3442 void 3443 bge_sync_mac_modes(bge_t *bgep) 3444 { 3445 uint32_t macmode; 3446 uint32_t regval; 3447 3448 ASSERT(mutex_owned(bgep->genlock)); 3449 3450 /* 3451 * Reprogram the Ethernet MAC mode ... 3452 */ 3453 macmode = regval = bge_reg_get32(bgep, ETHERNET_MAC_MODE_REG); 3454 macmode &= ~ETHERNET_MODE_LINK_POLARITY; 3455 macmode &= ~ETHERNET_MODE_PORTMODE_MASK; 3456 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 3457 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) { 3458 if (DEVICE_5717_SERIES_CHIPSETS(bgep) || 3459 DEVICE_5725_SERIES_CHIPSETS(bgep) || 3460 DEVICE_5714_SERIES_CHIPSETS(bgep)) 3461 macmode |= ETHERNET_MODE_PORTMODE_GMII; 3462 else 3463 macmode |= ETHERNET_MODE_PORTMODE_TBI; 3464 } else if (bgep->param_link_speed == 10 || 3465 bgep->param_link_speed == 100) 3466 macmode |= ETHERNET_MODE_PORTMODE_MII; 3467 else 3468 macmode |= ETHERNET_MODE_PORTMODE_GMII; 3469 if (bgep->param_link_duplex == LINK_DUPLEX_HALF) 3470 macmode |= ETHERNET_MODE_HALF_DUPLEX; 3471 else 3472 macmode &= ~ETHERNET_MODE_HALF_DUPLEX; 3473 if (bgep->param_loop_mode == BGE_LOOP_INTERNAL_MAC) 3474 macmode |= ETHERNET_MODE_MAC_LOOPBACK; 3475 else 3476 macmode &= ~ETHERNET_MODE_MAC_LOOPBACK; 3477 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, macmode); 3478 BGE_DEBUG(("bge_sync_mac_modes($%p) Ethernet MAC mode 0x%x => 0x%x", 3479 (void *)bgep, regval, macmode)); 3480 3481 /* 3482 * ... the Transmit MAC mode ... 3483 */ 3484 macmode = regval = bge_reg_get32(bgep, TRANSMIT_MAC_MODE_REG); 3485 if (bgep->param_link_tx_pause) 3486 macmode |= TRANSMIT_MODE_FLOW_CONTROL; 3487 else 3488 macmode &= ~TRANSMIT_MODE_FLOW_CONTROL; 3489 bge_reg_put32(bgep, TRANSMIT_MAC_MODE_REG, macmode); 3490 BGE_DEBUG(("bge_sync_mac_modes($%p) Transmit MAC mode 0x%x => 0x%x", 3491 (void *)bgep, regval, macmode)); 3492 3493 /* 3494 * ... and the Receive MAC mode 3495 */ 3496 macmode = regval = bge_reg_get32(bgep, RECEIVE_MAC_MODE_REG); 3497 if (bgep->param_link_rx_pause) 3498 macmode |= RECEIVE_MODE_FLOW_CONTROL; 3499 else 3500 macmode &= ~RECEIVE_MODE_FLOW_CONTROL; 3501 bge_reg_put32(bgep, RECEIVE_MAC_MODE_REG, macmode); 3502 BGE_DEBUG(("bge_sync_mac_modes($%p) Receive MAC mode 0x%x => 0x%x", 3503 (void *)bgep, regval, macmode)); 3504 3505 /* 3506 * For BCM5785, we need to configure the link status in the MI Status 3507 * register with a write command when auto-polling is disabled. 3508 */ 3509 if (bgep->chipid.device == DEVICE_ID_5785) 3510 if (bgep->param_link_speed == 10) 3511 bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK 3512 | MI_STATUS_10MBPS); 3513 else 3514 bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK); 3515 } 3516 3517 /* 3518 * bge_chip_sync() -- program the chip with the unicast MAC address, 3519 * the multicast hash table, the required level of promiscuity, and 3520 * the current loopback mode ... 3521 */ 3522 #ifdef BGE_IPMI_ASF 3523 int bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive); 3524 #else 3525 int bge_chip_sync(bge_t *bgep); 3526 #endif 3527 #pragma no_inline(bge_chip_sync) 3528 3529 int 3530 #ifdef BGE_IPMI_ASF 3531 bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive) 3532 #else 3533 bge_chip_sync(bge_t *bgep) 3534 #endif 3535 { 3536 void (*opfn)(bge_t *bgep, bge_regno_t reg, uint32_t bits); 3537 boolean_t promisc; 3538 uint64_t macaddr; 3539 uint32_t fill = 0; 3540 int i, j; 3541 int retval = DDI_SUCCESS; 3542 3543 BGE_TRACE(("bge_chip_sync($%p)", 3544 (void *)bgep)); 3545 3546 ASSERT(mutex_owned(bgep->genlock)); 3547 3548 promisc = B_FALSE; 3549 fill = ~(uint32_t)0; 3550 3551 if (bgep->promisc) 3552 promisc = B_TRUE; 3553 else 3554 fill = (uint32_t)0; 3555 3556 /* 3557 * If the TX/RX MAC engines are already running, we should stop 3558 * them (and reset the RX engine) before changing the parameters. 3559 * If they're not running, this will have no effect ... 3560 * 3561 * NOTE: this is currently disabled by default because stopping 3562 * and restarting the Tx engine may cause an outgoing packet in 3563 * transit to be truncated. Also, stopping and restarting the 3564 * Rx engine seems to not work correctly on the 5705. Testing 3565 * has not (yet!) revealed any problems with NOT stopping and 3566 * restarting these engines (and Broadcom say their drivers don't 3567 * do this), but if it is found to cause problems, this variable 3568 * can be patched to re-enable the old behaviour ... 3569 */ 3570 if (bge_stop_start_on_sync) { 3571 #ifdef BGE_IPMI_ASF 3572 if (!bgep->asf_enabled) { 3573 if (!bge_chip_disable_engine(bgep, 3574 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG)) 3575 retval = DDI_FAILURE; 3576 } else { 3577 if (!bge_chip_disable_engine(bgep, 3578 RECEIVE_MAC_MODE_REG, 0)) 3579 retval = DDI_FAILURE; 3580 } 3581 #else 3582 if (!bge_chip_disable_engine(bgep, RECEIVE_MAC_MODE_REG, 3583 RECEIVE_MODE_KEEP_VLAN_TAG)) 3584 retval = DDI_FAILURE; 3585 #endif 3586 if (!bge_chip_disable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 3587 retval = DDI_FAILURE; 3588 if (!bge_chip_reset_engine(bgep, RECEIVE_MAC_MODE_REG)) 3589 retval = DDI_FAILURE; 3590 } 3591 3592 /* 3593 * Reprogram the hashed multicast address table ... 3594 */ 3595 for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i) 3596 bge_reg_put32(bgep, MAC_HASH_REG(i), 0); 3597 3598 for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i) 3599 bge_reg_put32(bgep, MAC_HASH_REG(i), 3600 bgep->mcast_hash[i] | fill); 3601 3602 #ifdef BGE_IPMI_ASF 3603 if (!bgep->asf_enabled || !asf_keeplive) { 3604 #endif 3605 /* 3606 * Transform the MAC address(es) from host to chip format, then 3607 * reprogram the transmit random backoff seed and the unicast 3608 * MAC address(es) ... 3609 */ 3610 for (j = 0; j < MAC_ADDRESS_REGS_MAX; j++) { 3611 for (i = 0, macaddr = 0ull; 3612 i < ETHERADDRL; ++i) { 3613 macaddr <<= 8; 3614 macaddr |= bgep->curr_addr[j].addr[i]; 3615 } 3616 fill += (macaddr >> 16) + (macaddr & 0xffffffff); 3617 bge_reg_put64(bgep, MAC_ADDRESS_REG(j), macaddr); 3618 3619 BGE_DEBUG(("bge_chip_sync($%p) " 3620 "setting MAC address %012llx", 3621 (void *)bgep, macaddr)); 3622 } 3623 #ifdef BGE_IPMI_ASF 3624 } 3625 #endif 3626 /* 3627 * Set random seed of backoff interval 3628 * - Writing zero means no backoff interval 3629 */ 3630 fill = ((fill >> 20) + (fill >> 10) + fill) & 0x3ff; 3631 if (fill == 0) 3632 fill = 1; 3633 bge_reg_put32(bgep, MAC_TX_RANDOM_BACKOFF_REG, fill); 3634 3635 /* 3636 * Set or clear the PROMISCUOUS mode bit 3637 */ 3638 opfn = promisc ? bge_reg_set32 : bge_reg_clr32; 3639 (*opfn)(bgep, RECEIVE_MAC_MODE_REG, RECEIVE_MODE_PROMISCUOUS); 3640 3641 /* 3642 * Sync the rest of the MAC modes too ... 3643 */ 3644 bge_sync_mac_modes(bgep); 3645 3646 /* 3647 * Restart RX/TX MAC engines if required ... 3648 */ 3649 if (bgep->bge_chip_state == BGE_CHIP_RUNNING) { 3650 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 3651 retval = DDI_FAILURE; 3652 #ifdef BGE_IPMI_ASF 3653 if (!bgep->asf_enabled) { 3654 if (!bge_chip_enable_engine(bgep, 3655 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG)) 3656 retval = DDI_FAILURE; 3657 } else { 3658 if (!bge_chip_enable_engine(bgep, 3659 RECEIVE_MAC_MODE_REG, 0)) 3660 retval = DDI_FAILURE; 3661 } 3662 #else 3663 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 3664 RECEIVE_MODE_KEEP_VLAN_TAG)) 3665 retval = DDI_FAILURE; 3666 #endif 3667 } 3668 return (retval); 3669 } 3670 3671 #ifndef __sparc 3672 static bge_regno_t quiesce_regs[] = { 3673 READ_DMA_MODE_REG, 3674 DMA_COMPLETION_MODE_REG, 3675 WRITE_DMA_MODE_REG, 3676 BGE_REGNO_NONE 3677 }; 3678 3679 void bge_chip_stop_nonblocking(bge_t *bgep); 3680 #pragma no_inline(bge_chip_stop_nonblocking) 3681 3682 /* 3683 * This function is called by bge_quiesce(). We 3684 * turn off all the DMA engines here. 3685 */ 3686 void 3687 bge_chip_stop_nonblocking(bge_t *bgep) 3688 { 3689 bge_regno_t *rbp; 3690 3691 /* 3692 * Flag that no more activity may be initiated 3693 */ 3694 bgep->progress &= ~PROGRESS_READY; 3695 3696 rbp = quiesce_regs; 3697 while (*rbp != BGE_REGNO_NONE) { 3698 (void) bge_chip_disable_engine(bgep, *rbp, 0); 3699 ++rbp; 3700 } 3701 3702 bgep->bge_chip_state = BGE_CHIP_STOPPED; 3703 } 3704 3705 #endif 3706 3707 /* 3708 * bge_chip_stop() -- stop all chip processing 3709 * 3710 * If the <fault> parameter is B_TRUE, we're stopping the chip because 3711 * we've detected a problem internally; otherwise, this is a normal 3712 * (clean) stop (at user request i.e. the last STREAM has been closed). 3713 */ 3714 void bge_chip_stop(bge_t *bgep, boolean_t fault); 3715 #pragma no_inline(bge_chip_stop) 3716 3717 void 3718 bge_chip_stop(bge_t *bgep, boolean_t fault) 3719 { 3720 bge_regno_t regno; 3721 bge_regno_t *rbp; 3722 boolean_t ok = B_TRUE; 3723 3724 BGE_TRACE(("bge_chip_stop($%p)", 3725 (void *)bgep)); 3726 3727 ASSERT(mutex_owned(bgep->genlock)); 3728 3729 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, 3730 (pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MHCR) | 3731 MHCR_MASK_PCI_INT_OUTPUT)); 3732 3733 ok &= bge_chip_disable_engine(bgep, RECEIVE_MAC_MODE_REG, 0); 3734 ok &= bge_chip_disable_engine(bgep, RCV_BD_INITIATOR_MODE_REG, 0); 3735 ok &= bge_chip_disable_engine(bgep, RCV_LIST_PLACEMENT_MODE_REG, 0); 3736 ok &= bge_chip_disable_engine(bgep, RCV_LIST_SELECTOR_MODE_REG, 0); 3737 ok &= bge_chip_disable_engine(bgep, RCV_DATA_BD_INITIATOR_MODE_REG, 0); 3738 ok &= bge_chip_disable_engine(bgep, RCV_DATA_COMPLETION_MODE_REG, 0); 3739 ok &= bge_chip_disable_engine(bgep, RCV_BD_COMPLETION_MODE_REG, 0); 3740 3741 ok &= bge_chip_disable_engine(bgep, SEND_BD_SELECTOR_MODE_REG, 0); 3742 ok &= bge_chip_disable_engine(bgep, SEND_BD_INITIATOR_MODE_REG, 0); 3743 ok &= bge_chip_disable_engine(bgep, SEND_DATA_INITIATOR_MODE_REG, 0); 3744 ok &= bge_chip_disable_engine(bgep, READ_DMA_MODE_REG, 0); 3745 ok &= bge_chip_disable_engine(bgep, SEND_DATA_COMPLETION_MODE_REG, 0); 3746 ok &= bge_chip_disable_engine(bgep, DMA_COMPLETION_MODE_REG, 0); 3747 ok &= bge_chip_disable_engine(bgep, SEND_BD_COMPLETION_MODE_REG, 0); 3748 ok &= bge_chip_disable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0); 3749 3750 bge_reg_clr32(bgep, ETHERNET_MAC_MODE_REG, ETHERNET_MODE_ENABLE_TDE); 3751 drv_usecwait(40); 3752 3753 ok &= bge_chip_disable_engine(bgep, HOST_COALESCE_MODE_REG, 0); 3754 ok &= bge_chip_disable_engine(bgep, WRITE_DMA_MODE_REG, 0); 3755 ok &= bge_chip_disable_engine(bgep, MBUF_CLUSTER_FREE_MODE_REG, 0); 3756 ok &= bge_chip_disable_engine(bgep, FTQ_RESET_REG, 0); 3757 ok &= bge_chip_disable_engine(bgep, BUFFER_MANAGER_MODE_REG, 0); 3758 ok &= bge_chip_disable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0); 3759 ok &= bge_chip_disable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0); 3760 3761 if (!ok && !fault) 3762 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 3763 3764 /* 3765 * Finally, disable (all) MAC events & clear the MAC status 3766 */ 3767 bge_reg_put32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 0); 3768 bge_reg_put32(bgep, ETHERNET_MAC_STATUS_REG, ~0); 3769 3770 /* 3771 * if we're stopping the chip because of a detected fault then do 3772 * appropriate actions 3773 */ 3774 if (fault) { 3775 if (bgep->bge_chip_state != BGE_CHIP_FAULT) { 3776 bgep->bge_chip_state = BGE_CHIP_FAULT; 3777 if (!bgep->manual_reset) 3778 ddi_fm_service_impact(bgep->devinfo, 3779 DDI_SERVICE_LOST); 3780 if (bgep->bge_dma_error) { 3781 /* 3782 * need to free buffers in case the fault was 3783 * due to a memory error in a buffer - got to 3784 * do a fair bit of tidying first 3785 */ 3786 if (bgep->progress & PROGRESS_KSTATS) { 3787 bge_fini_kstats(bgep); 3788 bgep->progress &= ~PROGRESS_KSTATS; 3789 } 3790 if (bgep->progress & PROGRESS_INTR) { 3791 bge_intr_disable(bgep); 3792 rw_enter(bgep->errlock, RW_WRITER); 3793 bge_fini_rings(bgep); 3794 rw_exit(bgep->errlock); 3795 bgep->progress &= ~PROGRESS_INTR; 3796 } 3797 if (bgep->progress & PROGRESS_BUFS) { 3798 bge_free_bufs(bgep); 3799 bgep->progress &= ~PROGRESS_BUFS; 3800 } 3801 bgep->bge_dma_error = B_FALSE; 3802 } 3803 } 3804 } else 3805 bgep->bge_chip_state = BGE_CHIP_STOPPED; 3806 } 3807 3808 /* 3809 * Poll for completion of chip's ROM firmware; also, at least on the 3810 * first time through, find and return the hardware MAC address, if any. 3811 */ 3812 static uint64_t bge_poll_firmware(bge_t *bgep); 3813 #pragma no_inline(bge_poll_firmware) 3814 3815 static uint64_t 3816 bge_poll_firmware(bge_t *bgep) 3817 { 3818 uint64_t magic; 3819 uint64_t mac; 3820 uint32_t gen, val; 3821 uint32_t i; 3822 3823 /* 3824 * Step 19: poll for firmware completion (GENCOMM port set 3825 * to the ones complement of T3_MAGIC_NUMBER). 3826 * 3827 * While we're at it, we also read the MAC address register; 3828 * at some stage the firmware will load this with the 3829 * factory-set value. 3830 * 3831 * When both the magic number and the MAC address are set, 3832 * we're done; but we impose a time limit of one second 3833 * (1000*1000us) in case the firmware fails in some fashion 3834 * or the SEEPROM that provides that MAC address isn't fitted. 3835 * 3836 * After the first time through (chip state != INITIAL), we 3837 * don't need the MAC address to be set (we've already got it 3838 * or not, from the first time), so we don't wait for it, but 3839 * we still have to wait for the T3_MAGIC_NUMBER. 3840 * 3841 * Note: the magic number is only a 32-bit quantity, but the NIC 3842 * memory is 64-bit (and big-endian) internally. Addressing the 3843 * GENCOMM word as "the upper half of a 64-bit quantity" makes 3844 * it work correctly on both big- and little-endian hosts. 3845 */ 3846 if (MHCR_CHIP_ASIC_REV(bgep) == MHCR_CHIP_ASIC_REV_5906) { 3847 for (i = 0; i < 1000; ++i) { 3848 drv_usecwait(1000); 3849 val = bge_reg_get32(bgep, VCPU_STATUS_REG); 3850 if (val & VCPU_INIT_DONE) 3851 break; 3852 } 3853 BGE_DEBUG(("bge_poll_firmware($%p): return after %d loops", 3854 (void *)bgep, i)); 3855 mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0)); 3856 } else { 3857 for (i = 0; i < 1000; ++i) { 3858 drv_usecwait(1000); 3859 gen = bge_nic_get64(bgep, NIC_MEM_GENCOMM) >> 32; 3860 if (i == 0 && DEVICE_5704_SERIES_CHIPSETS(bgep)) 3861 drv_usecwait(100000); 3862 mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0)); 3863 #ifdef BGE_IPMI_ASF 3864 if (!bgep->asf_enabled) { 3865 #endif 3866 if (gen != ~T3_MAGIC_NUMBER) 3867 continue; 3868 #ifdef BGE_IPMI_ASF 3869 } 3870 #endif 3871 if (mac != 0ULL) 3872 break; 3873 if (bgep->bge_chip_state != BGE_CHIP_INITIAL) 3874 break; 3875 } 3876 } 3877 3878 magic = bge_nic_get64(bgep, NIC_MEM_GENCOMM); 3879 BGE_DEBUG(("bge_poll_firmware($%p): PXE magic 0x%x after %d loops", 3880 (void *)bgep, gen, i)); 3881 BGE_DEBUG(("bge_poll_firmware: MAC %016llx, GENCOMM %016llx", 3882 mac, magic)); 3883 3884 return (mac); 3885 } 3886 3887 /* 3888 * Maximum times of trying to get the NVRAM access lock 3889 * by calling bge_nvmem_acquire() 3890 */ 3891 #define MAX_TRY_NVMEM_ACQUIRE 10000 3892 3893 #ifdef BGE_IPMI_ASF 3894 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode); 3895 #else 3896 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma); 3897 #endif 3898 #pragma no_inline(bge_chip_reset) 3899 3900 int 3901 #ifdef BGE_IPMI_ASF 3902 bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode) 3903 #else 3904 bge_chip_reset(bge_t *bgep, boolean_t enable_dma) 3905 #endif 3906 { 3907 chip_id_t chipid; 3908 uint64_t mac; 3909 uint64_t magic; 3910 uint32_t tmp; 3911 uint32_t mhcr_base; 3912 uint32_t mhcr; 3913 uint32_t sx0; 3914 uint32_t i, tries; 3915 #ifdef BGE_IPMI_ASF 3916 uint32_t mailbox; 3917 #endif 3918 int retval = DDI_SUCCESS; 3919 3920 BGE_TRACE(("bge_chip_reset($%p, %d)", 3921 (void *)bgep, enable_dma)); 3922 3923 ASSERT(mutex_owned(bgep->genlock)); 3924 3925 BGE_DEBUG(("bge_chip_reset($%p, %d): current state is %d", 3926 (void *)bgep, enable_dma, bgep->bge_chip_state)); 3927 3928 /* 3929 * Do we need to stop the chip cleanly before resetting? 3930 */ 3931 switch (bgep->bge_chip_state) { 3932 default: 3933 _NOTE(NOTREACHED) 3934 return (DDI_FAILURE); 3935 3936 case BGE_CHIP_INITIAL: 3937 case BGE_CHIP_STOPPED: 3938 case BGE_CHIP_RESET: 3939 break; 3940 3941 case BGE_CHIP_RUNNING: 3942 case BGE_CHIP_ERROR: 3943 case BGE_CHIP_FAULT: 3944 bge_chip_stop(bgep, B_FALSE); 3945 break; 3946 } 3947 3948 mhcr_base = MHCR_ENABLE_INDIRECT_ACCESS | 3949 MHCR_ENABLE_PCI_STATE_RW | 3950 MHCR_ENABLE_TAGGED_STATUS_MODE | 3951 MHCR_MASK_INTERRUPT_MODE | 3952 MHCR_MASK_PCI_INT_OUTPUT | 3953 MHCR_CLEAR_INTERRUPT_INTA; 3954 3955 #ifdef BGE_IPMI_ASF 3956 if (bgep->asf_enabled) { 3957 mhcr = mhcr_base; 3958 #ifdef _BIG_ENDIAN 3959 mhcr |= (MHCR_ENABLE_ENDIAN_WORD_SWAP | 3960 MHCR_ENABLE_ENDIAN_BYTE_SWAP); 3961 #endif 3962 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr); 3963 3964 bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG, 3965 bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG) | 3966 MEMORY_ARBITER_ENABLE); 3967 3968 if (asf_mode == ASF_MODE_INIT) { 3969 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 3970 } else if (asf_mode == ASF_MODE_SHUTDOWN) { 3971 bge_asf_pre_reset_operations(bgep, BGE_SHUTDOWN_RESET); 3972 } 3973 } 3974 #endif 3975 3976 /* 3977 * Adapted from Broadcom document 570X-PG102-R, pp 102-116. 3978 * Updated to reflect Broadcom document 570X-PG104-R, pp 146-159. 3979 * 3980 * Before reset Core clock,it is 3981 * also required to initialize the Memory Arbiter as specified in step9 3982 * and Misc Host Control Register as specified in step-13 3983 * Step 4-5: reset Core clock & wait for completion 3984 * Steps 6-8: are done by bge_chip_cfg_init() 3985 * put the T3_MAGIC_NUMBER into the GENCOMM port before reset 3986 */ 3987 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 3988 retval = DDI_FAILURE; 3989 3990 mhcr = mhcr_base; 3991 #ifdef _BIG_ENDIAN 3992 mhcr |= (MHCR_ENABLE_ENDIAN_WORD_SWAP | 3993 MHCR_ENABLE_ENDIAN_BYTE_SWAP); 3994 #endif 3995 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr); 3996 3997 #ifdef BGE_IPMI_ASF 3998 if (bgep->asf_enabled) 3999 bgep->asf_wordswapped = B_FALSE; 4000 #endif 4001 /* 4002 * NVRAM Corruption Workaround 4003 */ 4004 for (tries = 0; tries < MAX_TRY_NVMEM_ACQUIRE; tries++) 4005 if (bge_nvmem_acquire(bgep) != EAGAIN) 4006 break; 4007 if (tries >= MAX_TRY_NVMEM_ACQUIRE) 4008 BGE_DEBUG(("%s: fail to acquire nvram lock", 4009 bgep->ifname)); 4010 4011 bge_ape_lock(bgep, BGE_APE_LOCK_GRC); 4012 4013 #ifdef BGE_IPMI_ASF 4014 if (!bgep->asf_enabled) { 4015 #endif 4016 magic = (uint64_t)T3_MAGIC_NUMBER << 32; 4017 bge_nic_put64(bgep, NIC_MEM_GENCOMM, magic); 4018 #ifdef BGE_IPMI_ASF 4019 } 4020 #endif 4021 4022 if (DEVICE_5717_SERIES_CHIPSETS(bgep) || 4023 DEVICE_5725_SERIES_CHIPSETS(bgep)) { 4024 bge_reg_set32(bgep, FAST_BOOT_PC, 0); 4025 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 4026 retval = DDI_FAILURE; 4027 } 4028 4029 mhcr = mhcr_base; 4030 #ifdef _BIG_ENDIAN 4031 mhcr |= (MHCR_ENABLE_ENDIAN_WORD_SWAP | 4032 MHCR_ENABLE_ENDIAN_BYTE_SWAP); 4033 #endif 4034 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr); 4035 4036 if (!bge_chip_reset_engine(bgep, MISC_CONFIG_REG)) 4037 retval = DDI_FAILURE; 4038 4039 bge_chip_cfg_init(bgep, &chipid, enable_dma); 4040 4041 /* 4042 * Step 8a: This may belong elsewhere, but BCM5721 needs 4043 * a bit set to avoid a fifo overflow/underflow bug. 4044 */ 4045 if ((bgep->chipid.chip_label == 5721) || 4046 (bgep->chipid.chip_label == 5751) || 4047 (bgep->chipid.chip_label == 5752) || 4048 (bgep->chipid.chip_label == 5755) || 4049 (bgep->chipid.chip_label == 5756) || 4050 (bgep->chipid.chip_label == 5789) || 4051 (bgep->chipid.chip_label == 5906)) 4052 bge_reg_set32(bgep, TLP_CONTROL_REG, TLP_DATA_FIFO_PROTECT); 4053 4054 /* 4055 * Step 9: enable MAC memory arbiter,bit30 and bit31 of 5714/5715 should 4056 * not be changed. 4057 */ 4058 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 4059 retval = DDI_FAILURE; 4060 4061 /* 4062 * Steps 10-11: configure PIO endianness options and 4063 * enable indirect register access -- already done 4064 * Steps 12-13: enable writing to the PCI state & clock 4065 * control registers -- not required; we aren't going to 4066 * use those features. 4067 * Steps 14-15: Configure DMA endianness options. See 4068 * the comments on the setting of the MHCR above. 4069 */ 4070 tmp = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME; 4071 #ifdef _BIG_ENDIAN 4072 tmp |= (MODE_WORD_SWAP_NONFRAME | MODE_BYTE_SWAP_NONFRAME); 4073 #endif 4074 #ifdef BGE_IPMI_ASF 4075 if (bgep->asf_enabled) 4076 tmp |= MODE_HOST_STACK_UP; 4077 #endif 4078 bge_reg_put32(bgep, MODE_CONTROL_REG, tmp); 4079 4080 #ifdef BGE_IPMI_ASF 4081 if (bgep->asf_enabled) { 4082 #ifdef __sparc 4083 bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG, 4084 MEMORY_ARBITER_ENABLE | 4085 bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG)); 4086 #endif 4087 4088 #ifdef BGE_NETCONSOLE 4089 if (!bgep->asf_newhandshake) { 4090 if ((asf_mode == ASF_MODE_INIT) || 4091 (asf_mode == ASF_MODE_POST_INIT)) { 4092 bge_asf_post_reset_old_mode(bgep, 4093 BGE_INIT_RESET); 4094 } else { 4095 bge_asf_post_reset_old_mode(bgep, 4096 BGE_SHUTDOWN_RESET); 4097 } 4098 } 4099 #endif 4100 4101 /* Wait for NVRAM init */ 4102 i = 0; 4103 drv_usecwait(5000); 4104 mailbox = bge_nic_get32(bgep, BGE_FIRMWARE_MAILBOX); 4105 4106 while ((mailbox != (uint32_t) 4107 ~BGE_MAGIC_NUM_FIRMWARE_INIT_DONE) && 4108 (i < 10000)) { 4109 drv_usecwait(100); 4110 mailbox = bge_nic_get32(bgep, 4111 BGE_FIRMWARE_MAILBOX); 4112 i++; 4113 } 4114 4115 #ifndef BGE_NETCONSOLE 4116 if (!bgep->asf_newhandshake) { 4117 if ((asf_mode == ASF_MODE_INIT) || 4118 (asf_mode == ASF_MODE_POST_INIT)) { 4119 4120 bge_asf_post_reset_old_mode(bgep, 4121 BGE_INIT_RESET); 4122 } else { 4123 bge_asf_post_reset_old_mode(bgep, 4124 BGE_SHUTDOWN_RESET); 4125 } 4126 } 4127 #endif 4128 } 4129 #endif 4130 4131 bge_ape_unlock(bgep, BGE_APE_LOCK_GRC); 4132 4133 /* 4134 * Steps 16-17: poll for firmware completion 4135 */ 4136 mac = bge_poll_firmware(bgep); 4137 4138 if (bgep->chipid.device == DEVICE_ID_5720) { 4139 tmp = bge_reg_get32(bgep, CPMU_CLCK_ORIDE_REG); 4140 bge_reg_put32(bgep, CPMU_CLCK_ORIDE_REG, 4141 (tmp & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN)); 4142 } 4143 4144 /* 4145 * Step 18: enable external memory -- doesn't apply. 4146 * 4147 * However we take the opportunity to set the MLCR anyway, as 4148 * this register also controls the SEEPROM auto-access method 4149 * which we may want to use later ... 4150 * 4151 * The proper value here depends on the way the chip is wired 4152 * into the circuit board, as this register *also* controls which 4153 * of the "Miscellaneous I/O" pins are driven as outputs and the 4154 * values driven onto those pins! 4155 * 4156 * See also step 74 in the PRM ... 4157 */ 4158 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, 4159 bgep->chipid.bge_mlcr_default); 4160 4161 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 4162 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 4163 tmp = bge_reg_get32(bgep, SERDES_RX_CONTROL); 4164 tmp |= SERDES_RX_CONTROL_SIG_DETECT; 4165 bge_reg_put32(bgep, SERDES_RX_CONTROL, tmp); 4166 } 4167 4168 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 4169 4170 /* 4171 * Step 20: clear the Ethernet MAC mode register 4172 */ 4173 if (bgep->ape_enabled) 4174 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, 4175 ETHERNET_MODE_APE_TX_EN | ETHERNET_MODE_APE_RX_EN); 4176 else 4177 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, 0); 4178 4179 /* 4180 * Step 21: restore cache-line-size, latency timer, and 4181 * subsystem ID registers to their original values (not 4182 * those read into the local structure <chipid>, 'cos 4183 * that was after they were cleared by the RESET). 4184 * 4185 * Note: the Subsystem Vendor/Device ID registers are not 4186 * directly writable in config space, so we use the shadow 4187 * copy in "Page Zero" of register space to restore them 4188 * both in one go ... 4189 */ 4190 pci_config_put8(bgep->cfg_handle, PCI_CONF_CACHE_LINESZ, 4191 bgep->chipid.clsize); 4192 pci_config_put8(bgep->cfg_handle, PCI_CONF_LATENCY_TIMER, 4193 bgep->chipid.latency); 4194 bge_reg_put32(bgep, PCI_CONF_SUBVENID, 4195 (bgep->chipid.subdev << 16) | bgep->chipid.subven); 4196 4197 /* 4198 * The SEND INDEX registers should be reset to zero by the 4199 * global chip reset; if they're not, there'll be trouble 4200 * later on. 4201 */ 4202 sx0 = bge_reg_get32(bgep, NIC_DIAG_SEND_INDEX_REG(0)); 4203 if (sx0 != 0) { 4204 BGE_REPORT((bgep, "SEND INDEX - device didn't RESET")); 4205 bge_fm_ereport(bgep, DDI_FM_DEVICE_INVAL_STATE); 4206 retval = DDI_FAILURE; 4207 } 4208 4209 /* Enable MSI code */ 4210 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 4211 bge_reg_set32(bgep, MSI_MODE_REG, 4212 MSI_PRI_HIGHEST|MSI_MSI_ENABLE|MSI_ERROR_ATTENTION); 4213 4214 /* 4215 * On the first time through, save the factory-set MAC address 4216 * (if any). If bge_poll_firmware() above didn't return one 4217 * (from a chip register) consider looking in the attached NV 4218 * memory device, if any. Once we have it, we save it in both 4219 * register-image (64-bit) and byte-array forms. All-zero and 4220 * all-one addresses are not valid, and we refuse to stash those. 4221 */ 4222 if (bgep->bge_chip_state == BGE_CHIP_INITIAL) { 4223 if (mac == 0ULL) 4224 mac = bge_get_nvmac(bgep); 4225 if (mac != 0ULL && mac != ~0ULL) { 4226 bgep->chipid.hw_mac_addr = mac; 4227 for (i = ETHERADDRL; i-- != 0; ) { 4228 bgep->chipid.vendor_addr.addr[i] = (uchar_t)mac; 4229 mac >>= 8; 4230 } 4231 bgep->chipid.vendor_addr.set = B_TRUE; 4232 } 4233 } 4234 4235 #ifdef BGE_IPMI_ASF 4236 if (bgep->asf_enabled && bgep->asf_newhandshake) { 4237 if (asf_mode != ASF_MODE_NONE) { 4238 if ((asf_mode == ASF_MODE_INIT) || 4239 (asf_mode == ASF_MODE_POST_INIT)) { 4240 4241 bge_asf_post_reset_new_mode(bgep, 4242 BGE_INIT_RESET); 4243 } else { 4244 bge_asf_post_reset_new_mode(bgep, 4245 BGE_SHUTDOWN_RESET); 4246 } 4247 } 4248 } 4249 #endif 4250 4251 /* 4252 * Record the new state 4253 */ 4254 bgep->chip_resets += 1; 4255 bgep->bge_chip_state = BGE_CHIP_RESET; 4256 return (retval); 4257 } 4258 4259 /* 4260 * bge_chip_start() -- start the chip transmitting and/or receiving, 4261 * including enabling interrupts 4262 */ 4263 int bge_chip_start(bge_t *bgep, boolean_t reset_phys); 4264 #pragma no_inline(bge_chip_start) 4265 4266 void 4267 bge_chip_coalesce_update(bge_t *bgep) 4268 { 4269 bge_reg_put32(bgep, SEND_COALESCE_MAX_BD_REG, 4270 bgep->chipid.tx_count_norm); 4271 bge_reg_put32(bgep, SEND_COALESCE_TICKS_REG, 4272 bgep->chipid.tx_ticks_norm); 4273 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, 4274 bgep->chipid.rx_count_norm); 4275 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, 4276 bgep->chipid.rx_ticks_norm); 4277 } 4278 4279 int 4280 bge_chip_start(bge_t *bgep, boolean_t reset_phys) 4281 { 4282 uint32_t coalmode; 4283 uint32_t ledctl; 4284 uint32_t mtu; 4285 uint32_t maxring; 4286 uint32_t stats_mask; 4287 uint32_t dma_wrprio; 4288 uint64_t ring; 4289 uint32_t reg; 4290 uint32_t regval; 4291 uint32_t mhcr; 4292 int retval = DDI_SUCCESS; 4293 int i; 4294 4295 BGE_TRACE(("bge_chip_start($%p)", 4296 (void *)bgep)); 4297 4298 ASSERT(mutex_owned(bgep->genlock)); 4299 ASSERT(bgep->bge_chip_state == BGE_CHIP_RESET); 4300 4301 /* Initialize EEE, enable MAC control of LPI */ 4302 bge_eee_init(bgep); 4303 4304 if (bgep->ape_enabled) { 4305 /* 4306 * Allow reads and writes to the 4307 * APE register and memory space. 4308 */ 4309 regval = pci_config_get32(bgep->cfg_handle, 4310 PCI_CONF_BGE_PCISTATE); 4311 regval |= PCISTATE_ALLOW_APE_CTLSPC_WR | 4312 PCISTATE_ALLOW_APE_SHMEM_WR | PCISTATE_ALLOW_APE_PSPACE_WR; 4313 pci_config_put32(bgep->cfg_handle, 4314 PCI_CONF_BGE_PCISTATE, regval); 4315 } 4316 4317 /* 4318 * Taken from Broadcom document 570X-PG102-R, pp 102-116. 4319 * The document specifies 95 separate steps to fully 4320 * initialise the chip!!!! 4321 * 4322 * The reset code above has already got us as far as step 4323 * 21, so we continue with ... 4324 * 4325 * Step 22: clear the MAC statistics block 4326 * (0x0300-0x0aff in NIC-local memory) 4327 */ 4328 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 4329 bge_nic_zero(bgep, NIC_MEM_STATISTICS, 4330 NIC_MEM_STATISTICS_SIZE); 4331 4332 /* 4333 * Step 23: clear the status block (in host memory) 4334 */ 4335 DMA_ZERO(bgep->status_block); 4336 4337 /* 4338 * Step 24: set DMA read/write control register 4339 */ 4340 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_PDRWCR, 4341 bgep->chipid.bge_dma_rwctrl); 4342 4343 /* 4344 * Step 25: Configure DMA endianness -- already done (16/17) 4345 * Step 26: Configure Host-Based Send Rings 4346 * Step 27: Indicate Host Stack Up 4347 */ 4348 bge_reg_set32(bgep, MODE_CONTROL_REG, 4349 MODE_HOST_SEND_BDS | 4350 MODE_HOST_STACK_UP); 4351 4352 if (DEVICE_5717_SERIES_CHIPSETS(bgep) || 4353 DEVICE_5725_SERIES_CHIPSETS(bgep)) { 4354 reg = (CHIP_ASIC_REV(bgep) == CHIP_ASIC_REV_5762) 4355 ? RDMA_RSRV_CTRL_REG2 : RDMA_RSRV_CTRL_REG; 4356 regval = bge_reg_get32(bgep, reg); 4357 if ((bgep->chipid.device == DEVICE_ID_5719) || 4358 (bgep->chipid.device == DEVICE_ID_5720) || 4359 (CHIP_ASIC_REV(bgep) == CHIP_ASIC_REV_5762)) { 4360 regval &= ~(RDMA_RSRV_CTRL_TXMRGN_MASK | 4361 RDMA_RSRV_CTRL_FIFO_LWM_MASK | 4362 RDMA_RSRV_CTRL_FIFO_HWM_MASK); 4363 regval |= (RDMA_RSRV_CTRL_TXMRGN_320B | 4364 RDMA_RSRV_CTRL_FIFO_LWM_1_5K | 4365 RDMA_RSRV_CTRL_FIFO_HWM_1_5K); 4366 } 4367 /* Enable the DMA FIFO Overrun fix. */ 4368 bge_reg_put32(bgep, reg, 4369 (regval | RDMA_RSRV_CTRL_FIFO_OFLW_FIX)); 4370 4371 if ((CHIP_ASIC_REV(bgep) == CHIP_ASIC_REV_5719) || 4372 (CHIP_ASIC_REV(bgep) == CHIP_ASIC_REV_5720) || 4373 (CHIP_ASIC_REV(bgep) == CHIP_ASIC_REV_5762)) { 4374 reg = (CHIP_ASIC_REV(bgep) == CHIP_ASIC_REV_5762) 4375 ? RDMA_CORR_CTRL_REG2 : RDMA_CORR_CTRL_REG; 4376 regval = bge_reg_get32(bgep, reg); 4377 bge_reg_put32(bgep, reg, (regval | 4378 RDMA_CORR_CTRL_BLEN_BD_4K | 4379 RDMA_CORR_CTRL_BLEN_LSO_4K)); 4380 } 4381 } 4382 4383 /* 4384 * Step 28: Configure checksum options: 4385 * Solaris supports the hardware default checksum options. 4386 * 4387 * Workaround for Incorrect pseudo-header checksum calculation. 4388 */ 4389 if (bgep->chipid.flags & CHIP_FLAG_PARTIAL_CSUM) 4390 bge_reg_set32(bgep, MODE_CONTROL_REG, 4391 MODE_SEND_NO_PSEUDO_HDR_CSUM); 4392 4393 /* 4394 * Step 29: configure Timer Prescaler. The value is always the 4395 * same: the Core Clock frequency in MHz (66), minus 1, shifted 4396 * into bits 7-1. Don't set bit 0, 'cos that's the RESET bit 4397 * for the whole chip! 4398 */ 4399 regval = bge_reg_get32(bgep, MISC_CONFIG_REG); 4400 regval = (regval & 0xffffff00) | MISC_CONFIG_DEFAULT; 4401 bge_reg_put32(bgep, MISC_CONFIG_REG, regval); 4402 4403 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) { 4404 drv_usecwait(40); 4405 /* put PHY into ready state */ 4406 bge_reg_clr32(bgep, MISC_CONFIG_REG, MISC_CONFIG_EPHY_IDDQ); 4407 (void) bge_reg_get32(bgep, MISC_CONFIG_REG); /* flush */ 4408 drv_usecwait(40); 4409 } 4410 4411 /* 4412 * Steps 30-31: Configure MAC local memory pool & DMA pool registers 4413 * 4414 * If the mbuf_length is specified as 0, we just leave these at 4415 * their hardware defaults, rather than explicitly setting them. 4416 * As the Broadcom HRM,driver better not change the parameters 4417 * when the chipsets is 5705/5788/5721/5751/5714 and 5715. 4418 */ 4419 if ((bgep->chipid.mbuf_length != 0) && 4420 (DEVICE_5704_SERIES_CHIPSETS(bgep))) { 4421 bge_reg_put32(bgep, MBUF_POOL_BASE_REG, 4422 bgep->chipid.mbuf_base); 4423 bge_reg_put32(bgep, MBUF_POOL_LENGTH_REG, 4424 bgep->chipid.mbuf_length); 4425 bge_reg_put32(bgep, DMAD_POOL_BASE_REG, 4426 DMAD_POOL_BASE_DEFAULT); 4427 bge_reg_put32(bgep, DMAD_POOL_LENGTH_REG, 4428 DMAD_POOL_LENGTH_DEFAULT); 4429 } 4430 4431 /* 4432 * Step 32: configure MAC memory pool watermarks 4433 */ 4434 bge_reg_put32(bgep, RDMA_MBUF_LOWAT_REG, 4435 bgep->chipid.mbuf_lo_water_rdma); 4436 bge_reg_put32(bgep, MAC_RX_MBUF_LOWAT_REG, 4437 bgep->chipid.mbuf_lo_water_rmac); 4438 bge_reg_put32(bgep, MBUF_HIWAT_REG, 4439 bgep->chipid.mbuf_hi_water); 4440 4441 /* 4442 * Step 33: configure DMA resource watermarks 4443 */ 4444 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 4445 bge_reg_put32(bgep, DMAD_POOL_LOWAT_REG, 4446 bge_dmad_lo_water); 4447 bge_reg_put32(bgep, DMAD_POOL_HIWAT_REG, 4448 bge_dmad_hi_water); 4449 } 4450 bge_reg_put32(bgep, LOWAT_MAX_RECV_FRAMES_REG, bge_lowat_recv_frames); 4451 4452 /* 4453 * Steps 34-36: enable buffer manager & internal h/w queues 4454 */ 4455 regval = STATE_MACHINE_ATTN_ENABLE_BIT; 4456 if (bgep->chipid.device == DEVICE_ID_5719) 4457 regval |= BUFFER_MANAGER_MODE_NO_TX_UNDERRUN; 4458 if (DEVICE_5717_SERIES_CHIPSETS(bgep) || 4459 DEVICE_5725_SERIES_CHIPSETS(bgep)) 4460 regval |= BUFFER_MANAGER_MODE_MBLOW_ATTN_ENABLE; 4461 if (!bge_chip_enable_engine(bgep, BUFFER_MANAGER_MODE_REG, regval)) 4462 retval = DDI_FAILURE; 4463 4464 if (!bge_chip_enable_engine(bgep, FTQ_RESET_REG, 0)) 4465 retval = DDI_FAILURE; 4466 4467 /* 4468 * Steps 37-39: initialise Receive Buffer (Producer) RCBs 4469 */ 4470 if (DEVICE_5717_SERIES_CHIPSETS(bgep) || 4471 DEVICE_5725_SERIES_CHIPSETS(bgep)) { 4472 buff_ring_t *brp = &bgep->buff[BGE_STD_BUFF_RING]; 4473 bge_reg_put64(bgep, STD_RCV_BD_RING_RCB_REG, 4474 brp->desc.cookie.dmac_laddress); 4475 bge_reg_put32(bgep, STD_RCV_BD_RING_RCB_REG + 8, 4476 (brp->desc.nslots) << 16 | brp->buf[0].size << 2); 4477 bge_reg_put32(bgep, STD_RCV_BD_RING_RCB_REG + 0xc, 4478 NIC_MEM_SHADOW_BUFF_STD_5717); 4479 } else 4480 bge_reg_putrcb(bgep, STD_RCV_BD_RING_RCB_REG, 4481 &bgep->buff[BGE_STD_BUFF_RING].hw_rcb); 4482 4483 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 4484 bge_reg_putrcb(bgep, JUMBO_RCV_BD_RING_RCB_REG, 4485 &bgep->buff[BGE_JUMBO_BUFF_RING].hw_rcb); 4486 bge_reg_putrcb(bgep, MINI_RCV_BD_RING_RCB_REG, 4487 &bgep->buff[BGE_MINI_BUFF_RING].hw_rcb); 4488 } 4489 4490 /* 4491 * Step 40: set Receive Buffer Descriptor Ring replenish thresholds 4492 */ 4493 bge_reg_put32(bgep, STD_RCV_BD_REPLENISH_REG, bge_replenish_std); 4494 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 4495 bge_reg_put32(bgep, JUMBO_RCV_BD_REPLENISH_REG, 4496 bge_replenish_jumbo); 4497 bge_reg_put32(bgep, MINI_RCV_BD_REPLENISH_REG, 4498 bge_replenish_mini); 4499 } 4500 4501 /* 4502 * Steps 41-43: clear Send Ring Producer Indices and initialise 4503 * Send Producer Rings (0x0100-0x01ff in NIC-local memory) 4504 */ 4505 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4506 maxring = BGE_SEND_RINGS_MAX; 4507 else 4508 maxring = BGE_SEND_RINGS_MAX_5705; 4509 for (ring = 0; ring < maxring; ++ring) { 4510 bge_mbx_put(bgep, SEND_RING_HOST_INDEX_REG(ring), 0); 4511 bge_mbx_put(bgep, SEND_RING_NIC_INDEX_REG(ring), 0); 4512 bge_nic_putrcb(bgep, NIC_MEM_SEND_RING(ring), 4513 &bgep->send[ring].hw_rcb); 4514 } 4515 4516 /* 4517 * Steps 44-45: initialise Receive Return Rings 4518 * (0x0200-0x02ff in NIC-local memory) 4519 */ 4520 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4521 maxring = BGE_RECV_RINGS_MAX; 4522 else 4523 maxring = BGE_RECV_RINGS_MAX_5705; 4524 for (ring = 0; ring < maxring; ++ring) 4525 bge_nic_putrcb(bgep, NIC_MEM_RECV_RING(ring), 4526 &bgep->recv[ring].hw_rcb); 4527 4528 /* 4529 * Step 46: initialise Receive Buffer (Producer) Ring indexes 4530 */ 4531 bge_mbx_put(bgep, RECV_STD_PROD_INDEX_REG, 0); 4532 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 4533 bge_mbx_put(bgep, RECV_JUMBO_PROD_INDEX_REG, 0); 4534 bge_mbx_put(bgep, RECV_MINI_PROD_INDEX_REG, 0); 4535 } 4536 /* 4537 * Step 47: configure the MAC unicast address 4538 * Step 48: configure the random backoff seed 4539 * Step 96: set up multicast filters 4540 */ 4541 #ifdef BGE_IPMI_ASF 4542 if (bge_chip_sync(bgep, B_FALSE) == DDI_FAILURE) 4543 #else 4544 if (bge_chip_sync(bgep) == DDI_FAILURE) 4545 #endif 4546 retval = DDI_FAILURE; 4547 4548 /* 4549 * Step 49: configure the MTU 4550 */ 4551 mtu = bgep->chipid.ethmax_size+ETHERFCSL+VLAN_TAGSZ; 4552 bge_reg_put32(bgep, MAC_RX_MTU_SIZE_REG, mtu); 4553 4554 /* 4555 * Step 50: configure the IPG et al 4556 */ 4557 bge_reg_put32(bgep, MAC_TX_LENGTHS_REG, MAC_TX_LENGTHS_DEFAULT); 4558 4559 /* 4560 * Step 51: configure the default Rx Return Ring 4561 */ 4562 bge_reg_put32(bgep, RCV_RULES_CONFIG_REG, RCV_RULES_CONFIG_DEFAULT); 4563 4564 /* 4565 * Steps 52-54: configure Receive List Placement, 4566 * and enable Receive List Placement Statistics 4567 */ 4568 bge_reg_put32(bgep, RCV_LP_CONFIG_REG, 4569 RCV_LP_CONFIG(bgep->chipid.rx_rings)); 4570 switch (MHCR_CHIP_ASIC_REV(bgep)) { 4571 case MHCR_CHIP_ASIC_REV_5700: 4572 case MHCR_CHIP_ASIC_REV_5701: 4573 case MHCR_CHIP_ASIC_REV_5703: 4574 case MHCR_CHIP_ASIC_REV_5704: 4575 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, ~0); 4576 break; 4577 case MHCR_CHIP_ASIC_REV_5705: 4578 break; 4579 default: 4580 stats_mask = bge_reg_get32(bgep, RCV_LP_STATS_ENABLE_MASK_REG); 4581 stats_mask &= ~RCV_LP_STATS_DISABLE_MACTQ; 4582 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, stats_mask); 4583 break; 4584 } 4585 bge_reg_set32(bgep, RCV_LP_STATS_CONTROL_REG, RCV_LP_STATS_ENABLE); 4586 4587 if (bgep->chipid.rx_rings > 1) 4588 bge_init_recv_rule(bgep); 4589 4590 /* 4591 * Steps 55-56: enable Send Data Initiator Statistics 4592 */ 4593 bge_reg_put32(bgep, SEND_INIT_STATS_ENABLE_MASK_REG, ~0); 4594 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 4595 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 4596 SEND_INIT_STATS_ENABLE | SEND_INIT_STATS_FASTER); 4597 } else { 4598 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 4599 SEND_INIT_STATS_ENABLE); 4600 } 4601 /* 4602 * Steps 57-58: stop (?) the Host Coalescing Engine 4603 */ 4604 if (!bge_chip_disable_engine(bgep, HOST_COALESCE_MODE_REG, ~0)) 4605 retval = DDI_FAILURE; 4606 4607 /* 4608 * Steps 59-62: initialise Host Coalescing parameters 4609 */ 4610 bge_chip_coalesce_update(bgep); 4611 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 4612 bge_reg_put32(bgep, SEND_COALESCE_INT_BD_REG, 4613 bge_tx_count_intr); 4614 bge_reg_put32(bgep, SEND_COALESCE_INT_TICKS_REG, 4615 bge_tx_ticks_intr); 4616 bge_reg_put32(bgep, RCV_COALESCE_INT_BD_REG, 4617 bge_rx_count_intr); 4618 bge_reg_put32(bgep, RCV_COALESCE_INT_TICKS_REG, 4619 bge_rx_ticks_intr); 4620 } 4621 4622 /* 4623 * Steps 63-64: initialise status block & statistics 4624 * host memory addresses 4625 * The statistic block does not exist in some chipsets 4626 * Step 65: initialise Statistics Coalescing Tick Counter 4627 */ 4628 bge_reg_put64(bgep, STATUS_BLOCK_HOST_ADDR_REG, 4629 bgep->status_block.cookie.dmac_laddress); 4630 4631 /* 4632 * Steps 66-67: initialise status block & statistics 4633 * NIC-local memory addresses 4634 */ 4635 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 4636 bge_reg_put64(bgep, STATISTICS_HOST_ADDR_REG, 4637 bgep->statistics.cookie.dmac_laddress); 4638 bge_reg_put32(bgep, STATISTICS_TICKS_REG, 4639 STATISTICS_TICKS_DEFAULT); 4640 bge_reg_put32(bgep, STATUS_BLOCK_BASE_ADDR_REG, 4641 NIC_MEM_STATUS_BLOCK); 4642 bge_reg_put32(bgep, STATISTICS_BASE_ADDR_REG, 4643 NIC_MEM_STATISTICS); 4644 } 4645 4646 /* 4647 * Steps 68-71: start the Host Coalescing Engine, the Receive BD 4648 * Completion Engine, the Receive List Placement Engine, and the 4649 * Receive List selector.Pay attention:0x3400 is not exist in BCM5714 4650 * and BCM5715. 4651 */ 4652 4653 if (bgep->chipid.device == DEVICE_ID_5719) { 4654 for (i = 0; i < BGE_NUM_RDMA_CHANNELS; i++) { 4655 if (bge_reg_get32(bgep, (BGE_RDMA_LENGTH + (i << 2))) > 4656 bgep->chipid.default_mtu) 4657 break; 4658 } 4659 if (i < BGE_NUM_RDMA_CHANNELS) { 4660 regval = bge_reg_get32(bgep, RDMA_CORR_CTRL_REG); 4661 regval |= RDMA_CORR_CTRL_TX_LENGTH_WA; 4662 bge_reg_put32(bgep, RDMA_CORR_CTRL_REG, regval); 4663 bgep->rdma_length_bug_on_5719 = B_TRUE; 4664 } 4665 } 4666 4667 if (bgep->chipid.tx_rings <= COALESCE_64_BYTE_RINGS && 4668 bgep->chipid.rx_rings <= COALESCE_64_BYTE_RINGS) 4669 coalmode = COALESCE_64_BYTE_STATUS; 4670 else 4671 coalmode = 0; 4672 if (DEVICE_5717_SERIES_CHIPSETS(bgep) || 4673 DEVICE_5725_SERIES_CHIPSETS(bgep)) 4674 coalmode = COALESCE_CLR_TICKS_RX; 4675 if (!bge_chip_enable_engine(bgep, HOST_COALESCE_MODE_REG, coalmode)) 4676 retval = DDI_FAILURE; 4677 if (!bge_chip_enable_engine(bgep, RCV_BD_COMPLETION_MODE_REG, 4678 STATE_MACHINE_ATTN_ENABLE_BIT)) 4679 retval = DDI_FAILURE; 4680 if (!bge_chip_enable_engine(bgep, RCV_LIST_PLACEMENT_MODE_REG, 0)) 4681 retval = DDI_FAILURE; 4682 4683 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4684 if (!bge_chip_enable_engine(bgep, RCV_LIST_SELECTOR_MODE_REG, 4685 STATE_MACHINE_ATTN_ENABLE_BIT)) 4686 retval = DDI_FAILURE; 4687 4688 /* 4689 * Step 72: Enable MAC DMA engines 4690 * Step 73: Clear & enable MAC statistics 4691 */ 4692 if (bgep->ape_enabled) { 4693 /* XXX put32 instead of set32 ? */ 4694 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, 4695 ETHERNET_MODE_APE_TX_EN | ETHERNET_MODE_APE_RX_EN); 4696 } 4697 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 4698 ETHERNET_MODE_ENABLE_FHDE | 4699 ETHERNET_MODE_ENABLE_RDE | 4700 ETHERNET_MODE_ENABLE_TDE); 4701 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 4702 ETHERNET_MODE_ENABLE_TX_STATS | 4703 ETHERNET_MODE_ENABLE_RX_STATS | 4704 ETHERNET_MODE_CLEAR_TX_STATS | 4705 ETHERNET_MODE_CLEAR_RX_STATS); 4706 4707 drv_usecwait(140); 4708 4709 if (bgep->ape_enabled) { 4710 /* Write our heartbeat update interval to APE. */ 4711 bge_ape_put32(bgep, BGE_APE_HOST_HEARTBEAT_INT_MS, 4712 APE_HOST_HEARTBEAT_INT_DISABLE); 4713 } 4714 4715 /* 4716 * Step 74: configure the MLCR (Miscellaneous Local Control 4717 * Register); not required, as we set up the MLCR in step 10 4718 * (part of the reset code) above. 4719 * 4720 * Step 75: clear Interrupt Mailbox 0 4721 */ 4722 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 0); 4723 4724 /* 4725 * Steps 76-87: Gentlemen, start your engines ... 4726 * 4727 * Enable the DMA Completion Engine, the Write DMA Engine, 4728 * the Read DMA Engine, Receive Data Completion Engine, 4729 * the MBuf Cluster Free Engine, the Send Data Completion Engine, 4730 * the Send BD Completion Engine, the Receive BD Initiator Engine, 4731 * the Receive Data Initiator Engine, the Send Data Initiator Engine, 4732 * the Send BD Initiator Engine, and the Send BD Selector Engine. 4733 * 4734 * Beware exhaust fumes? 4735 */ 4736 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4737 if (!bge_chip_enable_engine(bgep, DMA_COMPLETION_MODE_REG, 0)) 4738 retval = DDI_FAILURE; 4739 dma_wrprio = (bge_dma_wrprio << DMA_PRIORITY_SHIFT) | 4740 ALL_DMA_ATTN_BITS; 4741 /* the 5723 check here covers all newer chip families (OK) */ 4742 if ((MHCR_CHIP_ASIC_REV(bgep) == MHCR_CHIP_ASIC_REV_5755) || 4743 (MHCR_CHIP_ASIC_REV(bgep) == MHCR_CHIP_ASIC_REV_5723) || 4744 (MHCR_CHIP_ASIC_REV(bgep) == MHCR_CHIP_ASIC_REV_5906)) { 4745 dma_wrprio |= DMA_STATUS_TAG_FIX_CQ12384; 4746 } 4747 if (!bge_chip_enable_engine(bgep, WRITE_DMA_MODE_REG, 4748 dma_wrprio)) 4749 retval = DDI_FAILURE; 4750 4751 drv_usecwait(40); 4752 4753 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || 4754 DEVICE_5717_SERIES_CHIPSETS(bgep) || 4755 DEVICE_5725_SERIES_CHIPSETS(bgep)) 4756 bge_dma_rdprio = 0; 4757 if (!bge_chip_enable_engine(bgep, READ_DMA_MODE_REG, 4758 (bge_dma_rdprio << DMA_PRIORITY_SHIFT) | ALL_DMA_ATTN_BITS)) 4759 retval = DDI_FAILURE; 4760 4761 drv_usecwait(40); 4762 4763 if (!bge_chip_enable_engine(bgep, RCV_DATA_COMPLETION_MODE_REG, 4764 STATE_MACHINE_ATTN_ENABLE_BIT)) 4765 retval = DDI_FAILURE; 4766 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4767 if (!bge_chip_enable_engine(bgep, 4768 MBUF_CLUSTER_FREE_MODE_REG, 0)) 4769 retval = DDI_FAILURE; 4770 if (!bge_chip_enable_engine(bgep, SEND_DATA_COMPLETION_MODE_REG, 0)) 4771 retval = DDI_FAILURE; 4772 if (!bge_chip_enable_engine(bgep, SEND_BD_COMPLETION_MODE_REG, 4773 STATE_MACHINE_ATTN_ENABLE_BIT)) 4774 retval = DDI_FAILURE; 4775 if (!bge_chip_enable_engine(bgep, RCV_BD_INITIATOR_MODE_REG, 4776 RCV_BD_DISABLED_RING_ATTN)) 4777 retval = DDI_FAILURE; 4778 if (!bge_chip_enable_engine(bgep, RCV_DATA_BD_INITIATOR_MODE_REG, 4779 RCV_DATA_BD_ILL_RING_ATTN)) 4780 retval = DDI_FAILURE; 4781 if (!bge_chip_enable_engine(bgep, SEND_DATA_INITIATOR_MODE_REG, 0)) 4782 retval = DDI_FAILURE; 4783 if (!bge_chip_enable_engine(bgep, SEND_BD_INITIATOR_MODE_REG, 4784 STATE_MACHINE_ATTN_ENABLE_BIT)) 4785 retval = DDI_FAILURE; 4786 if (!bge_chip_enable_engine(bgep, SEND_BD_SELECTOR_MODE_REG, 4787 STATE_MACHINE_ATTN_ENABLE_BIT)) 4788 retval = DDI_FAILURE; 4789 4790 drv_usecwait(40); 4791 4792 /* 4793 * Step 88: download firmware -- doesn't apply 4794 * Steps 89-90: enable Transmit & Receive MAC Engines 4795 */ 4796 regval = 0; 4797 if (DEVICE_5717_SERIES_CHIPSETS(bgep)) { 4798 regval |= TRANSMIT_MODE_MBUF_LOCKUP_FIX; 4799 } 4800 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, regval)) 4801 retval = DDI_FAILURE; 4802 4803 drv_usecwait(100); 4804 4805 #ifdef BGE_IPMI_ASF 4806 if (!bgep->asf_enabled) { 4807 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 4808 RECEIVE_MODE_KEEP_VLAN_TAG)) 4809 retval = DDI_FAILURE; 4810 } else { 4811 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 0)) 4812 retval = DDI_FAILURE; 4813 } 4814 #else 4815 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 4816 RECEIVE_MODE_KEEP_VLAN_TAG)) 4817 retval = DDI_FAILURE; 4818 #endif 4819 4820 drv_usecwait(100); 4821 4822 /* 4823 * Step 91: disable auto-polling of PHY status 4824 */ 4825 bge_reg_put32(bgep, MI_MODE_REG, MI_MODE_DEFAULT); 4826 4827 /* 4828 * Step 92: configure D0 power state (not required) 4829 * Step 93: initialise LED control register () 4830 */ 4831 ledctl = LED_CONTROL_DEFAULT; 4832 switch (bgep->chipid.device) { 4833 case DEVICE_ID_5700: 4834 case DEVICE_ID_5700x: 4835 case DEVICE_ID_5701: 4836 /* 4837 * Switch to 5700 (MAC) mode on these older chips 4838 */ 4839 ledctl &= ~LED_CONTROL_LED_MODE_MASK; 4840 ledctl |= LED_CONTROL_LED_MODE_5700; 4841 break; 4842 4843 default: 4844 break; 4845 } 4846 bge_reg_put32(bgep, ETHERNET_MAC_LED_CONTROL_REG, ledctl); 4847 4848 /* 4849 * Step 94: activate link 4850 */ 4851 bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK); 4852 4853 /* 4854 * Step 95: set up physical layer (PHY/SerDes) 4855 * restart autoneg (if required) 4856 */ 4857 if (reset_phys) 4858 { 4859 if (bge_phys_update(bgep) == DDI_FAILURE) 4860 retval = DDI_FAILURE; 4861 /* forcing a mac link update here */ 4862 bge_phys_check(bgep); 4863 bgep->link_state = (bgep->param_link_up) ? LINK_STATE_UP : 4864 LINK_STATE_DOWN; 4865 bge_sync_mac_modes(bgep); 4866 mac_link_update(bgep->mh, bgep->link_state); 4867 } 4868 4869 /* 4870 * Extra step (DSG): hand over all the Receive Buffers to the chip 4871 */ 4872 for (ring = 0; ring < BGE_BUFF_RINGS_USED; ++ring) 4873 bge_mbx_put(bgep, bgep->buff[ring].chip_mbx_reg, 4874 bgep->buff[ring].rf_next); 4875 4876 /* 4877 * MSI bits:The least significant MSI 16-bit word. 4878 * ISR will be triggered different. 4879 */ 4880 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 4881 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 0x70); 4882 4883 /* 4884 * Extra step (DSG): select which interrupts are enabled 4885 * 4886 * Program the Ethernet MAC engine to signal attention on 4887 * Link Change events, then enable interrupts on MAC, DMA, 4888 * and FLOW attention signals. 4889 */ 4890 bge_reg_set32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 4891 ETHERNET_EVENT_LINK_INT | 4892 ETHERNET_STATUS_PCS_ERROR_INT); 4893 #ifdef BGE_IPMI_ASF 4894 if (bgep->asf_enabled) { 4895 bge_reg_set32(bgep, MODE_CONTROL_REG, 4896 MODE_INT_ON_FLOW_ATTN | 4897 MODE_INT_ON_DMA_ATTN | 4898 MODE_HOST_STACK_UP| 4899 MODE_INT_ON_MAC_ATTN); 4900 } else { 4901 #endif 4902 bge_reg_set32(bgep, MODE_CONTROL_REG, 4903 MODE_INT_ON_FLOW_ATTN | 4904 MODE_INT_ON_DMA_ATTN | 4905 MODE_INT_ON_MAC_ATTN); 4906 #ifdef BGE_IPMI_ASF 4907 } 4908 #endif 4909 4910 if (DEVICE_5717_SERIES_CHIPSETS(bgep) || 4911 DEVICE_5725_SERIES_CHIPSETS(bgep)) { 4912 bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL_5717, 4913 DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED); 4914 #if 0 4915 mhcr = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MHCR); 4916 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, 4917 (mhcr | MHCR_TLP_MINOR_ERR_TOLERANCE)); 4918 #endif 4919 } 4920 4921 /* 4922 * Step 97: enable PCI interrupts!!! 4923 */ 4924 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 4925 bge_cfg_clr32(bgep, PCI_CONF_BGE_MHCR, 4926 bgep->chipid.mask_pci_int); 4927 4928 /* 4929 * All done! 4930 */ 4931 bgep->bge_chip_state = BGE_CHIP_RUNNING; 4932 return (retval); 4933 } 4934 4935 4936 /* 4937 * ========== Hardware interrupt handler ========== 4938 */ 4939 4940 #undef BGE_DBG 4941 #define BGE_DBG BGE_DBG_INT /* debug flag for this code */ 4942 4943 /* 4944 * Sync the status block, then atomically clear the specified bits in 4945 * the <flags-and-tag> field of the status block. 4946 * the <flags> word of the status block, returning the value of the 4947 * <tag> and the <flags> before the bits were cleared. 4948 */ 4949 static int bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags); 4950 #pragma inline(bge_status_sync) 4951 4952 static int 4953 bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags) 4954 { 4955 bge_status_t *bsp; 4956 int retval; 4957 4958 BGE_TRACE(("bge_status_sync($%p, 0x%llx)", 4959 (void *)bgep, bits)); 4960 4961 ASSERT(bgep->bge_guard == BGE_GUARD); 4962 4963 DMA_SYNC(bgep->status_block, DDI_DMA_SYNC_FORKERNEL); 4964 retval = bge_check_dma_handle(bgep, bgep->status_block.dma_hdl); 4965 if (retval != DDI_FM_OK) 4966 return (retval); 4967 4968 bsp = DMA_VPTR(bgep->status_block); 4969 *flags = bge_atomic_clr64(&bsp->flags_n_tag, bits); 4970 4971 BGE_DEBUG(("bge_status_sync($%p, 0x%llx) returning 0x%llx", 4972 (void *)bgep, bits, *flags)); 4973 4974 return (retval); 4975 } 4976 4977 void bge_wake_factotum(bge_t *bgep); 4978 #pragma inline(bge_wake_factotum) 4979 4980 void 4981 bge_wake_factotum(bge_t *bgep) 4982 { 4983 mutex_enter(bgep->softintrlock); 4984 if (bgep->factotum_flag == 0) { 4985 bgep->factotum_flag = 1; 4986 ddi_trigger_softintr(bgep->factotum_id); 4987 } 4988 mutex_exit(bgep->softintrlock); 4989 } 4990 4991 static void 4992 bge_intr_error_handler(bge_t *bgep) 4993 { 4994 uint32_t flow; 4995 uint32_t rdma; 4996 uint32_t wdma; 4997 uint32_t tmac; 4998 uint32_t rmac; 4999 uint32_t rxrs; 5000 uint32_t emac; 5001 uint32_t msis; 5002 uint32_t txrs = 0; 5003 5004 ASSERT(mutex_owned(bgep->genlock)); 5005 5006 /* 5007 * Read all the registers that show the possible 5008 * reasons for the ERROR bit to be asserted 5009 */ 5010 flow = bge_reg_get32(bgep, FLOW_ATTN_REG); 5011 rdma = bge_reg_get32(bgep, READ_DMA_STATUS_REG); 5012 wdma = bge_reg_get32(bgep, WRITE_DMA_STATUS_REG); 5013 tmac = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 5014 rmac = bge_reg_get32(bgep, RECEIVE_MAC_STATUS_REG); 5015 rxrs = bge_reg_get32(bgep, RX_RISC_STATE_REG); 5016 emac = bge_reg_get32(bgep, ETHERNET_MAC_STATUS_REG); 5017 msis = bge_reg_get32(bgep, MSI_STATUS_REG); 5018 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 5019 txrs = bge_reg_get32(bgep, TX_RISC_STATE_REG); 5020 5021 BGE_DEBUG(("factotum($%p) flow 0x%x rdma 0x%x wdma 0x%x emac 0x%x msis 0x%x", 5022 (void *)bgep, flow, rdma, wdma, emac, msis)); 5023 BGE_DEBUG(("factotum($%p) tmac 0x%x rmac 0x%x rxrs 0x%08x txrs 0x%08x", 5024 (void *)bgep, tmac, rmac, rxrs, txrs)); 5025 5026 /* 5027 * For now, just clear all the errors ... 5028 */ 5029 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 5030 bge_reg_put32(bgep, TX_RISC_STATE_REG, ~0); 5031 bge_reg_put32(bgep, RX_RISC_STATE_REG, ~0); 5032 bge_reg_put32(bgep, RECEIVE_MAC_STATUS_REG, ~0); 5033 bge_reg_put32(bgep, WRITE_DMA_STATUS_REG, ~0); 5034 bge_reg_put32(bgep, READ_DMA_STATUS_REG, ~0); 5035 bge_reg_put32(bgep, FLOW_ATTN_REG, ~0); 5036 } 5037 5038 /* 5039 * bge_intr() -- handle chip interrupts 5040 */ 5041 uint_t bge_intr(caddr_t arg1, caddr_t arg2); 5042 #pragma no_inline(bge_intr) 5043 5044 uint_t 5045 bge_intr(caddr_t arg1, caddr_t arg2) 5046 { 5047 bge_t *bgep = (void *)arg1; /* private device info */ 5048 bge_status_t *bsp; 5049 uint64_t flags; 5050 uint32_t regval; 5051 uint_t result; 5052 int retval, loop_cnt = 0; 5053 5054 BGE_TRACE(("bge_intr($%p) ($%p)", arg1, arg2)); 5055 5056 /* 5057 * GLD v2 checks that s/w setup is complete before passing 5058 * interrupts to this routine, thus eliminating the old 5059 * (and well-known) race condition around ddi_add_intr() 5060 */ 5061 ASSERT(bgep->progress & PROGRESS_HWINT); 5062 5063 result = DDI_INTR_UNCLAIMED; 5064 mutex_enter(bgep->genlock); 5065 5066 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) { 5067 /* 5068 * Check whether chip's says it's asserting #INTA; 5069 * if not, don't process or claim the interrupt. 5070 * 5071 * Note that the PCI signal is active low, so the 5072 * bit is *zero* when the interrupt is asserted. 5073 */ 5074 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 5075 if (!(DEVICE_5717_SERIES_CHIPSETS(bgep) || 5076 DEVICE_5725_SERIES_CHIPSETS(bgep)) && 5077 (regval & MLCR_INTA_STATE)) { 5078 if (bge_check_acc_handle(bgep, bgep->io_handle) 5079 != DDI_FM_OK) 5080 goto chip_stop; 5081 mutex_exit(bgep->genlock); 5082 return (result); 5083 } 5084 5085 /* 5086 * Block further PCI interrupts ... 5087 */ 5088 bge_reg_set32(bgep, PCI_CONF_BGE_MHCR, 5089 bgep->chipid.mask_pci_int); 5090 5091 } else { 5092 /* 5093 * Check MSI status 5094 */ 5095 regval = bge_reg_get32(bgep, MSI_STATUS_REG); 5096 if (regval & MSI_ERROR_ATTENTION) { 5097 BGE_REPORT((bgep, "msi error attention," 5098 " status=0x%x", regval)); 5099 bge_reg_put32(bgep, MSI_STATUS_REG, regval); 5100 } 5101 } 5102 5103 result = DDI_INTR_CLAIMED; 5104 5105 BGE_DEBUG(("bge_intr($%p) ($%p) regval 0x%08x", arg1, arg2, regval)); 5106 5107 /* 5108 * Sync the status block and grab the flags-n-tag from it. 5109 * We count the number of interrupts where there doesn't 5110 * seem to have been a DMA update of the status block; if 5111 * it *has* been updated, the counter will be cleared in 5112 * the while() loop below ... 5113 */ 5114 bgep->missed_dmas += 1; 5115 bsp = DMA_VPTR(bgep->status_block); 5116 for (loop_cnt = 0; loop_cnt < bge_intr_max_loop; loop_cnt++) { 5117 if (bgep->bge_chip_state != BGE_CHIP_RUNNING) { 5118 /* 5119 * bge_chip_stop() may have freed dma area etc 5120 * while we were in this interrupt handler - 5121 * better not call bge_status_sync() 5122 */ 5123 (void) bge_check_acc_handle(bgep, 5124 bgep->io_handle); 5125 mutex_exit(bgep->genlock); 5126 return (DDI_INTR_CLAIMED); 5127 } 5128 5129 retval = bge_status_sync(bgep, STATUS_FLAG_UPDATED | 5130 STATUS_FLAG_LINK_CHANGED | STATUS_FLAG_ERROR, &flags); 5131 if (retval != DDI_FM_OK) { 5132 bgep->bge_dma_error = B_TRUE; 5133 goto chip_stop; 5134 } 5135 5136 if (!(flags & STATUS_FLAG_UPDATED)) 5137 break; 5138 5139 /* 5140 * Tell the chip that we're processing the interrupt 5141 */ 5142 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 5143 INTERRUPT_MBOX_DISABLE(flags)); 5144 if (bge_check_acc_handle(bgep, bgep->io_handle) != 5145 DDI_FM_OK) 5146 goto chip_stop; 5147 5148 if (flags & STATUS_FLAG_LINK_CHANGED) { 5149 BGE_DEBUG(("bge_intr($%p) ($%p) link event", arg1, arg2)); 5150 if (bge_phys_check(bgep)) { 5151 bgep->link_state = bgep->param_link_up ? 5152 LINK_STATE_UP : LINK_STATE_DOWN; 5153 bge_sync_mac_modes(bgep); 5154 mac_link_update(bgep->mh, bgep->link_state); 5155 } 5156 5157 if (bge_check_acc_handle(bgep, bgep->io_handle) != 5158 DDI_FM_OK) 5159 goto chip_stop; 5160 } 5161 5162 if (flags & STATUS_FLAG_ERROR) { 5163 bge_intr_error_handler(bgep); 5164 5165 if (bge_check_acc_handle(bgep, bgep->io_handle) != 5166 DDI_FM_OK) 5167 goto chip_stop; 5168 } 5169 5170 /* 5171 * Drop the mutex while we: 5172 * Receive any newly-arrived packets 5173 * Recycle any newly-finished send buffers 5174 */ 5175 bgep->bge_intr_running = B_TRUE; 5176 mutex_exit(bgep->genlock); 5177 bge_receive(bgep, bsp); 5178 (void) bge_recycle(bgep, bsp); 5179 mutex_enter(bgep->genlock); 5180 bgep->bge_intr_running = B_FALSE; 5181 5182 /* 5183 * Tell the chip we've finished processing, and 5184 * give it the tag that we got from the status 5185 * block earlier, so that it knows just how far 5186 * we've gone. If it's got more for us to do, 5187 * it will now update the status block and try 5188 * to assert an interrupt (but we've got the 5189 * #INTA blocked at present). If we see the 5190 * update, we'll loop around to do some more. 5191 * Eventually we'll get out of here ... 5192 */ 5193 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 5194 INTERRUPT_MBOX_ENABLE(flags)); 5195 if (bgep->chipid.pci_type == BGE_PCI_E) 5196 (void) bge_mbx_get(bgep, INTERRUPT_MBOX_0_REG); 5197 bgep->missed_dmas = 0; 5198 } 5199 5200 if (bgep->missed_dmas) { 5201 /* 5202 * Probably due to the internal status tag not 5203 * being reset. Force a status block update now; 5204 * this should ensure that we get an update and 5205 * a new interrupt. After that, we should be in 5206 * sync again ... 5207 */ 5208 BGE_REPORT((bgep, "interrupt: flags 0x%llx - " 5209 "not updated?", flags)); 5210 bgep->missed_updates++; 5211 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 5212 COALESCE_NOW); 5213 5214 if (bgep->missed_dmas >= bge_dma_miss_limit) { 5215 /* 5216 * If this happens multiple times in a row, 5217 * it means DMA is just not working. Maybe 5218 * the chip's failed, or maybe there's a 5219 * problem on the PCI bus or in the host-PCI 5220 * bridge (Tomatillo). 5221 * 5222 * At all events, we want to stop further 5223 * interrupts and let the recovery code take 5224 * over to see whether anything can be done 5225 * about it ... 5226 */ 5227 bge_fm_ereport(bgep, 5228 DDI_FM_DEVICE_BADINT_LIMIT); 5229 goto chip_stop; 5230 } 5231 } 5232 5233 /* 5234 * Reenable assertion of #INTA, unless there's a DMA fault 5235 */ 5236 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) { 5237 bge_reg_clr32(bgep, PCI_CONF_BGE_MHCR, 5238 bgep->chipid.mask_pci_int); 5239 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != 5240 DDI_FM_OK) 5241 goto chip_stop; 5242 } 5243 5244 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5245 goto chip_stop; 5246 5247 mutex_exit(bgep->genlock); 5248 return (result); 5249 5250 chip_stop: 5251 5252 #ifdef BGE_IPMI_ASF 5253 if (bgep->asf_enabled && bgep->asf_status == ASF_STAT_RUN) { 5254 /* 5255 * We must stop ASF heart beat before 5256 * bge_chip_stop(), otherwise some 5257 * computers (ex. IBM HS20 blade 5258 * server) may crash. 5259 */ 5260 bge_asf_update_status(bgep); 5261 bge_asf_stop_timer(bgep); 5262 bgep->asf_status = ASF_STAT_STOP; 5263 5264 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 5265 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 5266 } 5267 #endif 5268 bge_chip_stop(bgep, B_TRUE); 5269 (void) bge_check_acc_handle(bgep, bgep->io_handle); 5270 mutex_exit(bgep->genlock); 5271 return (result); 5272 } 5273 5274 /* 5275 * ========== Factotum, implemented as a softint handler ========== 5276 */ 5277 5278 #undef BGE_DBG 5279 #define BGE_DBG BGE_DBG_FACT /* debug flag for this code */ 5280 5281 /* 5282 * Factotum routine to check for Tx stall, using the 'watchdog' counter 5283 */ 5284 static boolean_t bge_factotum_stall_check(bge_t *bgep); 5285 #pragma no_inline(bge_factotum_stall_check) 5286 5287 static boolean_t 5288 bge_factotum_stall_check(bge_t *bgep) 5289 { 5290 uint32_t dogval; 5291 bge_status_t *bsp; 5292 uint64_t now = gethrtime(); 5293 5294 if ((now - bgep->timestamp) < BGE_CYCLIC_PERIOD) 5295 return (B_FALSE); 5296 5297 bgep->timestamp = now; 5298 5299 ASSERT(mutex_owned(bgep->genlock)); 5300 5301 /* 5302 * Specific check for Tx stall ... 5303 * 5304 * The 'watchdog' counter is incremented whenever a packet 5305 * is queued, reset to 1 when some (but not all) buffers 5306 * are reclaimed, reset to 0 (disabled) when all buffers 5307 * are reclaimed, and shifted left here. If it exceeds the 5308 * threshold value, the chip is assumed to have stalled and 5309 * is put into the ERROR state. The factotum will then reset 5310 * it on the next pass. 5311 * 5312 * All of which should ensure that we don't get into a state 5313 * where packets are left pending indefinitely! 5314 */ 5315 dogval = bge_atomic_shl32(&bgep->watchdog, 1); 5316 bsp = DMA_VPTR(bgep->status_block); 5317 if (dogval < bge_watchdog_count || bge_recycle(bgep, bsp)) 5318 return (B_FALSE); 5319 5320 #if !defined(BGE_NETCONSOLE) 5321 BGE_REPORT((bgep, "Tx stall detected, watchdog code 0x%x", dogval)); 5322 #endif 5323 bge_fm_ereport(bgep, DDI_FM_DEVICE_STALL); 5324 return (B_TRUE); 5325 } 5326 5327 /* 5328 * The factotum is woken up when there's something to do that we'd rather 5329 * not do from inside a hardware interrupt handler or high-level cyclic. 5330 * Its main task is to reset & restart the chip after an error. 5331 */ 5332 uint_t bge_chip_factotum(caddr_t arg); 5333 #pragma no_inline(bge_chip_factotum) 5334 5335 uint_t 5336 bge_chip_factotum(caddr_t arg) 5337 { 5338 bge_t *bgep; 5339 uint_t result; 5340 boolean_t error; 5341 int dma_state; 5342 5343 bgep = (void *)arg; 5344 5345 BGE_TRACE(("bge_chip_factotum($%p)", (void *)bgep)); 5346 5347 mutex_enter(bgep->softintrlock); 5348 if (bgep->factotum_flag == 0) { 5349 mutex_exit(bgep->softintrlock); 5350 return (DDI_INTR_UNCLAIMED); 5351 } 5352 bgep->factotum_flag = 0; 5353 mutex_exit(bgep->softintrlock); 5354 5355 result = DDI_INTR_CLAIMED; 5356 error = B_FALSE; 5357 5358 mutex_enter(bgep->genlock); 5359 switch (bgep->bge_chip_state) { 5360 default: 5361 break; 5362 5363 case BGE_CHIP_RUNNING: 5364 5365 if (bgep->chipid.device == DEVICE_ID_5700) { 5366 if (bge_phys_check(bgep)) { 5367 bgep->link_state = (bgep->param_link_up) ? 5368 LINK_STATE_UP : LINK_STATE_DOWN; 5369 bge_sync_mac_modes(bgep); 5370 mac_link_update(bgep->mh, bgep->link_state); 5371 } 5372 } 5373 5374 error = bge_factotum_stall_check(bgep); 5375 if (dma_state != DDI_FM_OK) { 5376 bgep->bge_dma_error = B_TRUE; 5377 error = B_TRUE; 5378 } 5379 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5380 error = B_TRUE; 5381 if (error) 5382 bgep->bge_chip_state = BGE_CHIP_ERROR; 5383 break; 5384 5385 case BGE_CHIP_ERROR: 5386 error = B_TRUE; 5387 break; 5388 5389 case BGE_CHIP_FAULT: 5390 /* 5391 * Fault detected, time to reset ... 5392 */ 5393 if (bge_autorecover) { 5394 if (!(bgep->progress & PROGRESS_BUFS)) { 5395 /* 5396 * if we can't allocate the ring buffers, 5397 * try later 5398 */ 5399 if (bge_alloc_bufs(bgep) != DDI_SUCCESS) { 5400 mutex_exit(bgep->genlock); 5401 return (result); 5402 } 5403 bgep->progress |= PROGRESS_BUFS; 5404 } 5405 if (!(bgep->progress & PROGRESS_INTR)) { 5406 bge_init_rings(bgep); 5407 bge_intr_enable(bgep); 5408 bgep->progress |= PROGRESS_INTR; 5409 } 5410 if (!(bgep->progress & PROGRESS_KSTATS)) { 5411 bge_init_kstats(bgep, 5412 ddi_get_instance(bgep->devinfo)); 5413 bgep->progress |= PROGRESS_KSTATS; 5414 } 5415 5416 BGE_REPORT((bgep, "automatic recovery activated")); 5417 5418 if (bge_restart(bgep, B_FALSE) != DDI_SUCCESS) { 5419 bgep->bge_chip_state = BGE_CHIP_ERROR; 5420 error = B_TRUE; 5421 } 5422 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != 5423 DDI_FM_OK) { 5424 bgep->bge_chip_state = BGE_CHIP_ERROR; 5425 error = B_TRUE; 5426 } 5427 if (bge_check_acc_handle(bgep, bgep->io_handle) != 5428 DDI_FM_OK) { 5429 bgep->bge_chip_state = BGE_CHIP_ERROR; 5430 error = B_TRUE; 5431 } 5432 if (error == B_FALSE) { 5433 #ifdef BGE_IPMI_ASF 5434 if (bgep->asf_enabled && 5435 bgep->asf_status != ASF_STAT_RUN) { 5436 bgep->asf_timeout_id = timeout( 5437 bge_asf_heartbeat, (void *)bgep, 5438 drv_usectohz( 5439 BGE_ASF_HEARTBEAT_INTERVAL)); 5440 bgep->asf_status = ASF_STAT_RUN; 5441 } 5442 #endif 5443 if (!bgep->manual_reset) { 5444 ddi_fm_service_impact(bgep->devinfo, 5445 DDI_SERVICE_RESTORED); 5446 } 5447 } 5448 } 5449 break; 5450 } 5451 5452 /* 5453 * If an error is detected, stop the chip now, marking it as 5454 * faulty, so that it will be reset next time through ... 5455 * 5456 * Note that if intr_running is set, then bge_intr() has dropped 5457 * genlock to call bge_receive/bge_recycle. Can't stop the chip at 5458 * this point so have to wait until the next time the factotum runs. 5459 */ 5460 if (error && !bgep->bge_intr_running) { 5461 #ifdef BGE_IPMI_ASF 5462 if (bgep->asf_enabled && (bgep->asf_status == ASF_STAT_RUN)) { 5463 /* 5464 * We must stop ASF heart beat before bge_chip_stop(), 5465 * otherwise some computers (ex. IBM HS20 blade server) 5466 * may crash. 5467 */ 5468 bge_asf_update_status(bgep); 5469 bge_asf_stop_timer(bgep); 5470 bgep->asf_status = ASF_STAT_STOP; 5471 5472 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 5473 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 5474 } 5475 #endif 5476 bge_chip_stop(bgep, B_TRUE); 5477 (void) bge_check_acc_handle(bgep, bgep->io_handle); 5478 } 5479 mutex_exit(bgep->genlock); 5480 5481 return (result); 5482 } 5483 5484 /* 5485 * High-level cyclic handler 5486 * 5487 * This routine schedules a (low-level) softint callback to the 5488 * factotum, and prods the chip to update the status block (which 5489 * will cause a hardware interrupt when complete). 5490 */ 5491 void bge_chip_cyclic(void *arg); 5492 #pragma no_inline(bge_chip_cyclic) 5493 5494 void 5495 bge_chip_cyclic(void *arg) 5496 { 5497 bge_t *bgep; 5498 uint32_t regval; 5499 5500 bgep = arg; 5501 5502 switch (bgep->bge_chip_state) { 5503 default: 5504 return; 5505 5506 case BGE_CHIP_RUNNING: 5507 5508 /* XXX I really don't like this forced interrupt... */ 5509 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, COALESCE_NOW); 5510 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5511 ddi_fm_service_impact(bgep->devinfo, 5512 DDI_SERVICE_UNAFFECTED); 5513 5514 break; 5515 5516 case BGE_CHIP_FAULT: 5517 case BGE_CHIP_ERROR: 5518 5519 break; 5520 } 5521 5522 mutex_enter(bgep->genlock); 5523 5524 if (bgep->eee_lpi_wait && !--bgep->eee_lpi_wait) { 5525 BGE_DEBUG(("eee cyclic, lpi enabled")); 5526 bge_eee_enable(bgep); 5527 } 5528 5529 if (bgep->rdma_length_bug_on_5719) { 5530 if ((bge_reg_get32(bgep, STAT_IFHCOUT_UPKGS_REG) + 5531 bge_reg_get32(bgep, STAT_IFHCOUT_MPKGS_REG) + 5532 bge_reg_get32(bgep, STAT_IFHCOUT_BPKGS_REG)) > 5533 BGE_NUM_RDMA_CHANNELS) { 5534 regval = bge_reg_get32(bgep, RDMA_CORR_CTRL_REG); 5535 regval &= ~RDMA_CORR_CTRL_TX_LENGTH_WA; 5536 bge_reg_put32(bgep, RDMA_CORR_CTRL_REG, regval); 5537 bgep->rdma_length_bug_on_5719 = B_FALSE; 5538 } 5539 } 5540 5541 mutex_exit(bgep->genlock); 5542 5543 bge_wake_factotum(bgep); 5544 5545 } 5546 5547 5548 /* 5549 * ========== Ioctl subfunctions ========== 5550 */ 5551 5552 #undef BGE_DBG 5553 #define BGE_DBG BGE_DBG_PPIO /* debug flag for this code */ 5554 5555 #if BGE_DEBUGGING || BGE_DO_PPIO 5556 5557 static void bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 5558 #pragma no_inline(bge_chip_peek_cfg) 5559 5560 static void 5561 bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 5562 { 5563 uint64_t regval; 5564 uint64_t regno; 5565 5566 BGE_TRACE(("bge_chip_peek_cfg($%p, $%p)", 5567 (void *)bgep, (void *)ppd)); 5568 5569 regno = ppd->pp_acc_offset; 5570 5571 switch (ppd->pp_acc_size) { 5572 case 1: 5573 regval = pci_config_get8(bgep->cfg_handle, regno); 5574 break; 5575 5576 case 2: 5577 regval = pci_config_get16(bgep->cfg_handle, regno); 5578 break; 5579 5580 case 4: 5581 regval = pci_config_get32(bgep->cfg_handle, regno); 5582 break; 5583 5584 case 8: 5585 regval = pci_config_get64(bgep->cfg_handle, regno); 5586 break; 5587 } 5588 5589 ppd->pp_acc_data = regval; 5590 } 5591 5592 static void bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 5593 #pragma no_inline(bge_chip_poke_cfg) 5594 5595 static void 5596 bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 5597 { 5598 uint64_t regval; 5599 uint64_t regno; 5600 5601 BGE_TRACE(("bge_chip_poke_cfg($%p, $%p)", 5602 (void *)bgep, (void *)ppd)); 5603 5604 regno = ppd->pp_acc_offset; 5605 regval = ppd->pp_acc_data; 5606 5607 switch (ppd->pp_acc_size) { 5608 case 1: 5609 pci_config_put8(bgep->cfg_handle, regno, regval); 5610 break; 5611 5612 case 2: 5613 pci_config_put16(bgep->cfg_handle, regno, regval); 5614 break; 5615 5616 case 4: 5617 pci_config_put32(bgep->cfg_handle, regno, regval); 5618 break; 5619 5620 case 8: 5621 pci_config_put64(bgep->cfg_handle, regno, regval); 5622 break; 5623 } 5624 } 5625 5626 static void bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd); 5627 #pragma no_inline(bge_chip_peek_reg) 5628 5629 static void 5630 bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd) 5631 { 5632 uint64_t regval; 5633 void *regaddr; 5634 5635 BGE_TRACE(("bge_chip_peek_reg($%p, $%p)", 5636 (void *)bgep, (void *)ppd)); 5637 5638 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 5639 5640 switch (ppd->pp_acc_size) { 5641 case 1: 5642 regval = ddi_get8(bgep->io_handle, regaddr); 5643 break; 5644 5645 case 2: 5646 regval = ddi_get16(bgep->io_handle, regaddr); 5647 break; 5648 5649 case 4: 5650 regval = ddi_get32(bgep->io_handle, regaddr); 5651 break; 5652 5653 case 8: 5654 regval = ddi_get64(bgep->io_handle, regaddr); 5655 break; 5656 } 5657 5658 ppd->pp_acc_data = regval; 5659 } 5660 5661 static void bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd); 5662 #pragma no_inline(bge_chip_peek_reg) 5663 5664 static void 5665 bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd) 5666 { 5667 uint64_t regval; 5668 void *regaddr; 5669 5670 BGE_TRACE(("bge_chip_poke_reg($%p, $%p)", 5671 (void *)bgep, (void *)ppd)); 5672 5673 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 5674 regval = ppd->pp_acc_data; 5675 5676 switch (ppd->pp_acc_size) { 5677 case 1: 5678 ddi_put8(bgep->io_handle, regaddr, regval); 5679 break; 5680 5681 case 2: 5682 ddi_put16(bgep->io_handle, regaddr, regval); 5683 break; 5684 5685 case 4: 5686 ddi_put32(bgep->io_handle, regaddr, regval); 5687 break; 5688 5689 case 8: 5690 ddi_put64(bgep->io_handle, regaddr, regval); 5691 break; 5692 } 5693 BGE_PCICHK(bgep); 5694 } 5695 5696 static void bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd); 5697 #pragma no_inline(bge_chip_peek_nic) 5698 5699 static void 5700 bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd) 5701 { 5702 uint64_t regoff; 5703 uint64_t regval; 5704 void *regaddr; 5705 5706 BGE_TRACE(("bge_chip_peek_nic($%p, $%p)", 5707 (void *)bgep, (void *)ppd)); 5708 5709 regoff = ppd->pp_acc_offset; 5710 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 5711 regoff &= MWBAR_GRANULE_MASK; 5712 regoff += NIC_MEM_WINDOW_OFFSET; 5713 regaddr = PIO_ADDR(bgep, regoff); 5714 5715 switch (ppd->pp_acc_size) { 5716 case 1: 5717 regval = ddi_get8(bgep->io_handle, regaddr); 5718 break; 5719 5720 case 2: 5721 regval = ddi_get16(bgep->io_handle, regaddr); 5722 break; 5723 5724 case 4: 5725 regval = ddi_get32(bgep->io_handle, regaddr); 5726 break; 5727 5728 case 8: 5729 regval = ddi_get64(bgep->io_handle, regaddr); 5730 break; 5731 } 5732 5733 ppd->pp_acc_data = regval; 5734 } 5735 5736 static void bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd); 5737 #pragma no_inline(bge_chip_poke_nic) 5738 5739 static void 5740 bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd) 5741 { 5742 uint64_t regoff; 5743 uint64_t regval; 5744 void *regaddr; 5745 5746 BGE_TRACE(("bge_chip_poke_nic($%p, $%p)", 5747 (void *)bgep, (void *)ppd)); 5748 5749 regoff = ppd->pp_acc_offset; 5750 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 5751 regoff &= MWBAR_GRANULE_MASK; 5752 regoff += NIC_MEM_WINDOW_OFFSET; 5753 regaddr = PIO_ADDR(bgep, regoff); 5754 regval = ppd->pp_acc_data; 5755 5756 switch (ppd->pp_acc_size) { 5757 case 1: 5758 ddi_put8(bgep->io_handle, regaddr, regval); 5759 break; 5760 5761 case 2: 5762 ddi_put16(bgep->io_handle, regaddr, regval); 5763 break; 5764 5765 case 4: 5766 ddi_put32(bgep->io_handle, regaddr, regval); 5767 break; 5768 5769 case 8: 5770 ddi_put64(bgep->io_handle, regaddr, regval); 5771 break; 5772 } 5773 BGE_PCICHK(bgep); 5774 } 5775 5776 static void bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd); 5777 #pragma no_inline(bge_chip_peek_mii) 5778 5779 static void 5780 bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd) 5781 { 5782 BGE_TRACE(("bge_chip_peek_mii($%p, $%p)", 5783 (void *)bgep, (void *)ppd)); 5784 5785 ppd->pp_acc_data = bge_mii_get16(bgep, ppd->pp_acc_offset/2); 5786 } 5787 5788 static void bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd); 5789 #pragma no_inline(bge_chip_poke_mii) 5790 5791 static void 5792 bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd) 5793 { 5794 BGE_TRACE(("bge_chip_poke_mii($%p, $%p)", 5795 (void *)bgep, (void *)ppd)); 5796 5797 bge_mii_put16(bgep, ppd->pp_acc_offset/2, ppd->pp_acc_data); 5798 } 5799 5800 #if BGE_SEE_IO32 5801 5802 static void bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 5803 #pragma no_inline(bge_chip_peek_seeprom) 5804 5805 static void 5806 bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 5807 { 5808 uint32_t data; 5809 int err; 5810 5811 BGE_TRACE(("bge_chip_peek_seeprom($%p, $%p)", 5812 (void *)bgep, (void *)ppd)); 5813 5814 err = bge_nvmem_rw32(bgep, BGE_SEE_READ, ppd->pp_acc_offset, &data); 5815 ppd->pp_acc_data = err ? ~0ull : data; 5816 } 5817 5818 static void bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 5819 #pragma no_inline(bge_chip_poke_seeprom) 5820 5821 static void 5822 bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 5823 { 5824 uint32_t data; 5825 5826 BGE_TRACE(("bge_chip_poke_seeprom($%p, $%p)", 5827 (void *)bgep, (void *)ppd)); 5828 5829 data = ppd->pp_acc_data; 5830 (void) bge_nvmem_rw32(bgep, BGE_SEE_WRITE, ppd->pp_acc_offset, &data); 5831 } 5832 #endif /* BGE_SEE_IO32 */ 5833 5834 #if BGE_FLASH_IO32 5835 5836 static void bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd); 5837 #pragma no_inline(bge_chip_peek_flash) 5838 5839 static void 5840 bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd) 5841 { 5842 uint32_t data; 5843 int err; 5844 5845 BGE_TRACE(("bge_chip_peek_flash($%p, $%p)", 5846 (void *)bgep, (void *)ppd)); 5847 5848 err = bge_nvmem_rw32(bgep, BGE_FLASH_READ, ppd->pp_acc_offset, &data); 5849 ppd->pp_acc_data = err ? ~0ull : data; 5850 } 5851 5852 static void bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd); 5853 #pragma no_inline(bge_chip_poke_flash) 5854 5855 static void 5856 bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd) 5857 { 5858 uint32_t data; 5859 5860 BGE_TRACE(("bge_chip_poke_flash($%p, $%p)", 5861 (void *)bgep, (void *)ppd)); 5862 5863 data = ppd->pp_acc_data; 5864 (void) bge_nvmem_rw32(bgep, BGE_FLASH_WRITE, 5865 ppd->pp_acc_offset, &data); 5866 } 5867 #endif /* BGE_FLASH_IO32 */ 5868 5869 static void bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd); 5870 #pragma no_inline(bge_chip_peek_mem) 5871 5872 static void 5873 bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd) 5874 { 5875 uint64_t regval; 5876 void *vaddr; 5877 5878 BGE_TRACE(("bge_chip_peek_bge($%p, $%p)", 5879 (void *)bgep, (void *)ppd)); 5880 5881 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 5882 5883 switch (ppd->pp_acc_size) { 5884 case 1: 5885 regval = *(uint8_t *)vaddr; 5886 break; 5887 5888 case 2: 5889 regval = *(uint16_t *)vaddr; 5890 break; 5891 5892 case 4: 5893 regval = *(uint32_t *)vaddr; 5894 break; 5895 5896 case 8: 5897 regval = *(uint64_t *)vaddr; 5898 break; 5899 } 5900 5901 BGE_DEBUG(("bge_chip_peek_mem($%p, $%p) peeked 0x%llx from $%p", 5902 (void *)bgep, (void *)ppd, regval, vaddr)); 5903 5904 ppd->pp_acc_data = regval; 5905 } 5906 5907 static void bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd); 5908 #pragma no_inline(bge_chip_poke_mem) 5909 5910 static void 5911 bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd) 5912 { 5913 uint64_t regval; 5914 void *vaddr; 5915 5916 BGE_TRACE(("bge_chip_poke_mem($%p, $%p)", 5917 (void *)bgep, (void *)ppd)); 5918 5919 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 5920 regval = ppd->pp_acc_data; 5921 5922 BGE_DEBUG(("bge_chip_poke_mem($%p, $%p) poking 0x%llx at $%p", 5923 (void *)bgep, (void *)ppd, regval, vaddr)); 5924 5925 switch (ppd->pp_acc_size) { 5926 case 1: 5927 *(uint8_t *)vaddr = (uint8_t)regval; 5928 break; 5929 5930 case 2: 5931 *(uint16_t *)vaddr = (uint16_t)regval; 5932 break; 5933 5934 case 4: 5935 *(uint32_t *)vaddr = (uint32_t)regval; 5936 break; 5937 5938 case 8: 5939 *(uint64_t *)vaddr = (uint64_t)regval; 5940 break; 5941 } 5942 } 5943 5944 static enum ioc_reply bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5945 struct iocblk *iocp); 5946 #pragma no_inline(bge_pp_ioctl) 5947 5948 static enum ioc_reply 5949 bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5950 { 5951 void (*ppfn)(bge_t *bgep, bge_peekpoke_t *ppd); 5952 bge_peekpoke_t *ppd; 5953 dma_area_t *areap; 5954 uint64_t sizemask; 5955 uint64_t mem_va; 5956 uint64_t maxoff; 5957 boolean_t peek; 5958 5959 switch (cmd) { 5960 default: 5961 /* NOTREACHED */ 5962 bge_error(bgep, "bge_pp_ioctl: invalid cmd 0x%x", cmd); 5963 return (IOC_INVAL); 5964 5965 case BGE_PEEK: 5966 peek = B_TRUE; 5967 break; 5968 5969 case BGE_POKE: 5970 peek = B_FALSE; 5971 break; 5972 } 5973 5974 /* 5975 * Validate format of ioctl 5976 */ 5977 if (iocp->ioc_count != sizeof (bge_peekpoke_t)) 5978 return (IOC_INVAL); 5979 if (mp->b_cont == NULL) 5980 return (IOC_INVAL); 5981 ppd = (void *)mp->b_cont->b_rptr; 5982 5983 /* 5984 * Validate request parameters 5985 */ 5986 switch (ppd->pp_acc_space) { 5987 default: 5988 return (IOC_INVAL); 5989 5990 case BGE_PP_SPACE_CFG: 5991 /* 5992 * Config space 5993 */ 5994 sizemask = 8|4|2|1; 5995 mem_va = 0; 5996 maxoff = PCI_CONF_HDR_SIZE; 5997 ppfn = peek ? bge_chip_peek_cfg : bge_chip_poke_cfg; 5998 break; 5999 6000 case BGE_PP_SPACE_REG: 6001 /* 6002 * Memory-mapped I/O space 6003 */ 6004 sizemask = 8|4|2|1; 6005 mem_va = 0; 6006 maxoff = RIAAR_REGISTER_MAX; 6007 ppfn = peek ? bge_chip_peek_reg : bge_chip_poke_reg; 6008 break; 6009 6010 case BGE_PP_SPACE_NIC: 6011 /* 6012 * NIC on-chip memory 6013 */ 6014 sizemask = 8|4|2|1; 6015 mem_va = 0; 6016 maxoff = MWBAR_ONCHIP_MAX; 6017 ppfn = peek ? bge_chip_peek_nic : bge_chip_poke_nic; 6018 break; 6019 6020 case BGE_PP_SPACE_MII: 6021 /* 6022 * PHY's MII registers 6023 * NB: all PHY registers are two bytes, but the 6024 * addresses increment in ones (word addressing). 6025 * So we scale the address here, then undo the 6026 * transformation inside the peek/poke functions. 6027 */ 6028 ppd->pp_acc_offset *= 2; 6029 sizemask = 2; 6030 mem_va = 0; 6031 maxoff = (MII_MAXREG+1)*2; 6032 ppfn = peek ? bge_chip_peek_mii : bge_chip_poke_mii; 6033 break; 6034 6035 #if BGE_SEE_IO32 6036 case BGE_PP_SPACE_SEEPROM: 6037 /* 6038 * Attached SEEPROM(s), if any. 6039 * NB: we use the high-order bits of the 'address' as 6040 * a device select to accommodate multiple SEEPROMS, 6041 * If each one is the maximum size (64kbytes), this 6042 * makes them appear contiguous. Otherwise, there may 6043 * be holes in the mapping. ENxS doesn't have any 6044 * SEEPROMs anyway ... 6045 */ 6046 sizemask = 4; 6047 mem_va = 0; 6048 maxoff = SEEPROM_DEV_AND_ADDR_MASK; 6049 ppfn = peek ? bge_chip_peek_seeprom : bge_chip_poke_seeprom; 6050 break; 6051 #endif /* BGE_SEE_IO32 */ 6052 6053 #if BGE_FLASH_IO32 6054 case BGE_PP_SPACE_FLASH: 6055 /* 6056 * Attached Flash device (if any); a maximum of one device 6057 * is currently supported. But it can be up to 1MB (unlike 6058 * the 64k limit on SEEPROMs) so why would you need more ;-) 6059 */ 6060 sizemask = 4; 6061 mem_va = 0; 6062 maxoff = NVM_FLASH_ADDR_MASK; 6063 ppfn = peek ? bge_chip_peek_flash : bge_chip_poke_flash; 6064 break; 6065 #endif /* BGE_FLASH_IO32 */ 6066 6067 case BGE_PP_SPACE_BGE: 6068 /* 6069 * BGE data structure! 6070 */ 6071 sizemask = 8|4|2|1; 6072 mem_va = (uintptr_t)bgep; 6073 maxoff = sizeof (*bgep); 6074 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 6075 break; 6076 6077 case BGE_PP_SPACE_STATUS: 6078 case BGE_PP_SPACE_STATISTICS: 6079 case BGE_PP_SPACE_TXDESC: 6080 case BGE_PP_SPACE_TXBUFF: 6081 case BGE_PP_SPACE_RXDESC: 6082 case BGE_PP_SPACE_RXBUFF: 6083 /* 6084 * Various DMA_AREAs 6085 */ 6086 switch (ppd->pp_acc_space) { 6087 case BGE_PP_SPACE_TXDESC: 6088 areap = &bgep->tx_desc; 6089 break; 6090 case BGE_PP_SPACE_TXBUFF: 6091 areap = &bgep->tx_buff[0]; 6092 break; 6093 case BGE_PP_SPACE_RXDESC: 6094 areap = &bgep->rx_desc[0]; 6095 break; 6096 case BGE_PP_SPACE_RXBUFF: 6097 areap = &bgep->rx_buff[0]; 6098 break; 6099 case BGE_PP_SPACE_STATUS: 6100 areap = &bgep->status_block; 6101 break; 6102 case BGE_PP_SPACE_STATISTICS: 6103 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 6104 areap = &bgep->statistics; 6105 break; 6106 } 6107 6108 sizemask = 8|4|2|1; 6109 mem_va = (uintptr_t)areap->mem_va; 6110 maxoff = areap->alength; 6111 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 6112 break; 6113 } 6114 6115 switch (ppd->pp_acc_size) { 6116 default: 6117 return (IOC_INVAL); 6118 6119 case 8: 6120 case 4: 6121 case 2: 6122 case 1: 6123 if ((ppd->pp_acc_size & sizemask) == 0) 6124 return (IOC_INVAL); 6125 break; 6126 } 6127 6128 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 6129 return (IOC_INVAL); 6130 6131 if (ppd->pp_acc_offset >= maxoff) 6132 return (IOC_INVAL); 6133 6134 if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff) 6135 return (IOC_INVAL); 6136 6137 /* 6138 * All OK - go do it! 6139 */ 6140 ppd->pp_acc_offset += mem_va; 6141 (*ppfn)(bgep, ppd); 6142 return (peek ? IOC_REPLY : IOC_ACK); 6143 } 6144 6145 static enum ioc_reply bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 6146 struct iocblk *iocp); 6147 #pragma no_inline(bge_diag_ioctl) 6148 6149 static enum ioc_reply 6150 bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 6151 { 6152 ASSERT(mutex_owned(bgep->genlock)); 6153 6154 switch (cmd) { 6155 default: 6156 /* NOTREACHED */ 6157 bge_error(bgep, "bge_diag_ioctl: invalid cmd 0x%x", cmd); 6158 return (IOC_INVAL); 6159 6160 case BGE_DIAG: 6161 /* 6162 * Currently a no-op 6163 */ 6164 return (IOC_ACK); 6165 6166 case BGE_PEEK: 6167 case BGE_POKE: 6168 return (bge_pp_ioctl(bgep, cmd, mp, iocp)); 6169 6170 case BGE_PHY_RESET: 6171 return (IOC_RESTART_ACK); 6172 6173 case BGE_SOFT_RESET: 6174 case BGE_HARD_RESET: 6175 /* 6176 * Reset and reinitialise the 570x hardware 6177 */ 6178 bgep->bge_chip_state = BGE_CHIP_FAULT; 6179 ddi_trigger_softintr(bgep->factotum_id); 6180 (void) bge_restart(bgep, cmd == BGE_HARD_RESET); 6181 return (IOC_ACK); 6182 } 6183 6184 /* NOTREACHED */ 6185 } 6186 6187 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 6188 6189 static enum ioc_reply bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 6190 struct iocblk *iocp); 6191 #pragma no_inline(bge_mii_ioctl) 6192 6193 static enum ioc_reply 6194 bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 6195 { 6196 struct bge_mii_rw *miirwp; 6197 6198 /* 6199 * Validate format of ioctl 6200 */ 6201 if (iocp->ioc_count != sizeof (struct bge_mii_rw)) 6202 return (IOC_INVAL); 6203 if (mp->b_cont == NULL) 6204 return (IOC_INVAL); 6205 miirwp = (void *)mp->b_cont->b_rptr; 6206 6207 /* 6208 * Validate request parameters ... 6209 */ 6210 if (miirwp->mii_reg > MII_MAXREG) 6211 return (IOC_INVAL); 6212 6213 switch (cmd) { 6214 default: 6215 /* NOTREACHED */ 6216 bge_error(bgep, "bge_mii_ioctl: invalid cmd 0x%x", cmd); 6217 return (IOC_INVAL); 6218 6219 case BGE_MII_READ: 6220 miirwp->mii_data = bge_mii_get16(bgep, miirwp->mii_reg); 6221 return (IOC_REPLY); 6222 6223 case BGE_MII_WRITE: 6224 bge_mii_put16(bgep, miirwp->mii_reg, miirwp->mii_data); 6225 return (IOC_ACK); 6226 } 6227 6228 /* NOTREACHED */ 6229 } 6230 6231 #if BGE_SEE_IO32 6232 6233 static enum ioc_reply bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 6234 struct iocblk *iocp); 6235 #pragma no_inline(bge_see_ioctl) 6236 6237 static enum ioc_reply 6238 bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 6239 { 6240 struct bge_see_rw *seerwp; 6241 6242 /* 6243 * Validate format of ioctl 6244 */ 6245 if (iocp->ioc_count != sizeof (struct bge_see_rw)) 6246 return (IOC_INVAL); 6247 if (mp->b_cont == NULL) 6248 return (IOC_INVAL); 6249 seerwp = (void *)mp->b_cont->b_rptr; 6250 6251 /* 6252 * Validate request parameters ... 6253 */ 6254 if (seerwp->see_addr & ~SEEPROM_DEV_AND_ADDR_MASK) 6255 return (IOC_INVAL); 6256 6257 switch (cmd) { 6258 default: 6259 /* NOTREACHED */ 6260 bge_error(bgep, "bge_see_ioctl: invalid cmd 0x%x", cmd); 6261 return (IOC_INVAL); 6262 6263 case BGE_SEE_READ: 6264 case BGE_SEE_WRITE: 6265 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 6266 seerwp->see_addr, &seerwp->see_data); 6267 return (IOC_REPLY); 6268 } 6269 6270 /* NOTREACHED */ 6271 } 6272 6273 #endif /* BGE_SEE_IO32 */ 6274 6275 #if BGE_FLASH_IO32 6276 6277 static enum ioc_reply bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 6278 struct iocblk *iocp); 6279 #pragma no_inline(bge_flash_ioctl) 6280 6281 static enum ioc_reply 6282 bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 6283 { 6284 struct bge_flash_rw *flashrwp; 6285 6286 /* 6287 * Validate format of ioctl 6288 */ 6289 if (iocp->ioc_count != sizeof (struct bge_flash_rw)) 6290 return (IOC_INVAL); 6291 if (mp->b_cont == NULL) 6292 return (IOC_INVAL); 6293 flashrwp = (void *)mp->b_cont->b_rptr; 6294 6295 /* 6296 * Validate request parameters ... 6297 */ 6298 if (flashrwp->flash_addr & ~NVM_FLASH_ADDR_MASK) 6299 return (IOC_INVAL); 6300 6301 switch (cmd) { 6302 default: 6303 /* NOTREACHED */ 6304 bge_error(bgep, "bge_flash_ioctl: invalid cmd 0x%x", cmd); 6305 return (IOC_INVAL); 6306 6307 case BGE_FLASH_READ: 6308 case BGE_FLASH_WRITE: 6309 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 6310 flashrwp->flash_addr, &flashrwp->flash_data); 6311 return (IOC_REPLY); 6312 } 6313 6314 /* NOTREACHED */ 6315 } 6316 6317 #endif /* BGE_FLASH_IO32 */ 6318 6319 enum ioc_reply bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, 6320 struct iocblk *iocp); 6321 #pragma no_inline(bge_chip_ioctl) 6322 6323 enum ioc_reply 6324 bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 6325 { 6326 int cmd; 6327 6328 BGE_TRACE(("bge_chip_ioctl($%p, $%p, $%p, $%p)", 6329 (void *)bgep, (void *)wq, (void *)mp, (void *)iocp)); 6330 6331 ASSERT(mutex_owned(bgep->genlock)); 6332 6333 cmd = iocp->ioc_cmd; 6334 switch (cmd) { 6335 default: 6336 /* NOTREACHED */ 6337 bge_error(bgep, "bge_chip_ioctl: invalid cmd 0x%x", cmd); 6338 return (IOC_INVAL); 6339 6340 case BGE_DIAG: 6341 case BGE_PEEK: 6342 case BGE_POKE: 6343 case BGE_PHY_RESET: 6344 case BGE_SOFT_RESET: 6345 case BGE_HARD_RESET: 6346 #if BGE_DEBUGGING || BGE_DO_PPIO 6347 return (bge_diag_ioctl(bgep, cmd, mp, iocp)); 6348 #else 6349 return (IOC_INVAL); 6350 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 6351 6352 case BGE_MII_READ: 6353 case BGE_MII_WRITE: 6354 return (bge_mii_ioctl(bgep, cmd, mp, iocp)); 6355 6356 #if BGE_SEE_IO32 6357 case BGE_SEE_READ: 6358 case BGE_SEE_WRITE: 6359 return (bge_see_ioctl(bgep, cmd, mp, iocp)); 6360 #endif /* BGE_SEE_IO32 */ 6361 6362 #if BGE_FLASH_IO32 6363 case BGE_FLASH_READ: 6364 case BGE_FLASH_WRITE: 6365 return (bge_flash_ioctl(bgep, cmd, mp, iocp)); 6366 #endif /* BGE_FLASH_IO32 */ 6367 } 6368 6369 /* NOTREACHED */ 6370 } 6371 6372 /* ARGSUSED */ 6373 void 6374 bge_chip_blank(void *arg, time_t ticks, uint_t count, int flag) 6375 { 6376 recv_ring_t *rrp = arg; 6377 bge_t *bgep = rrp->bgep; 6378 6379 mutex_enter(bgep->genlock); 6380 rrp->poll_flag = flag; 6381 #ifdef NOT_YET 6382 /* 6383 * XXX-Sunay: Since most broadcom cards support only one 6384 * interrupt but multiple rx rings, we can't disable the 6385 * physical interrupt. This need to be done via capability 6386 * negotiation depending on the NIC. 6387 */ 6388 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, ticks); 6389 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, count); 6390 #endif 6391 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 6392 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 6393 mutex_exit(bgep->genlock); 6394 } 6395 6396 #ifdef BGE_IPMI_ASF 6397 6398 uint32_t 6399 bge_nic_read32(bge_t *bgep, bge_regno_t addr) 6400 { 6401 uint32_t data; 6402 6403 #ifndef __sparc 6404 if (!bgep->asf_wordswapped) { 6405 /* a workaround word swap error */ 6406 if (addr & 4) 6407 addr = addr - 4; 6408 else 6409 addr = addr + 4; 6410 } 6411 #else 6412 if (DEVICE_5717_SERIES_CHIPSETS(bgep) || 6413 DEVICE_5725_SERIES_CHIPSETS(bgep)) { 6414 addr = LE_32(addr); 6415 } 6416 #endif 6417 6418 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr); 6419 data = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR); 6420 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0); 6421 6422 data = LE_32(data); 6423 6424 BGE_DEBUG(("bge_nic_read32($%p, 0x%x) => 0x%x", 6425 (void *)bgep, addr, data)); 6426 6427 return (data); 6428 } 6429 6430 void 6431 bge_asf_update_status(bge_t *bgep) 6432 { 6433 uint32_t event; 6434 6435 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_ALIVE); 6436 bge_nic_put32(bgep, BGE_CMD_LENGTH_MAILBOX, 4); 6437 bge_nic_put32(bgep, BGE_CMD_DATA_MAILBOX, 3); 6438 6439 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 6440 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 6441 } 6442 6443 6444 /* 6445 * The driver is supposed to notify ASF that the OS is still running 6446 * every three seconds, otherwise the management server may attempt 6447 * to reboot the machine. If it hasn't actually failed, this is 6448 * not a desirable result. However, this isn't running as a real-time 6449 * thread, and even if it were, it might not be able to generate the 6450 * heartbeat in a timely manner due to system load. As it isn't a 6451 * significant strain on the machine, we will set the interval to half 6452 * of the required value. 6453 */ 6454 void 6455 bge_asf_heartbeat(void *arg) 6456 { 6457 bge_t *bgep = (bge_t *)arg; 6458 6459 mutex_enter(bgep->genlock); 6460 bge_asf_update_status((bge_t *)bgep); 6461 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 6462 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 6463 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) 6464 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 6465 mutex_exit(bgep->genlock); 6466 ((bge_t *)bgep)->asf_timeout_id = timeout(bge_asf_heartbeat, bgep, 6467 drv_usectohz(BGE_ASF_HEARTBEAT_INTERVAL)); 6468 } 6469 6470 6471 void 6472 bge_asf_stop_timer(bge_t *bgep) 6473 { 6474 timeout_id_t tmp_id = 0; 6475 6476 while ((bgep->asf_timeout_id != 0) && 6477 (tmp_id != bgep->asf_timeout_id)) { 6478 tmp_id = bgep->asf_timeout_id; 6479 (void) untimeout(tmp_id); 6480 } 6481 bgep->asf_timeout_id = 0; 6482 } 6483 6484 6485 6486 /* 6487 * This function should be placed at the earliest position of bge_attach(). 6488 */ 6489 void 6490 bge_asf_get_config(bge_t *bgep) 6491 { 6492 uint32_t nicsig; 6493 uint32_t niccfg; 6494 6495 bgep->asf_enabled = B_FALSE; 6496 nicsig = bge_nic_read32(bgep, BGE_NIC_DATA_SIG_ADDR); 6497 if (nicsig == BGE_NIC_DATA_SIG) { 6498 niccfg = bge_nic_read32(bgep, BGE_NIC_DATA_NIC_CFG_ADDR); 6499 if (niccfg & BGE_NIC_CFG_ENABLE_ASF) 6500 /* 6501 * Here, we don't consider BAXTER, because BGE haven't 6502 * supported BAXTER (that is 5752). Also, as I know, 6503 * BAXTER doesn't support ASF feature. 6504 */ 6505 bgep->asf_enabled = B_TRUE; 6506 else 6507 bgep->asf_enabled = B_FALSE; 6508 } else 6509 bgep->asf_enabled = B_FALSE; 6510 } 6511 6512 6513 void 6514 bge_asf_pre_reset_operations(bge_t *bgep, uint32_t mode) 6515 { 6516 uint32_t tries; 6517 uint32_t event; 6518 6519 ASSERT(bgep->asf_enabled); 6520 6521 /* Issues "pause firmware" command and wait for ACK */ 6522 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_PAUSE_FW); 6523 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 6524 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 6525 6526 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 6527 tries = 0; 6528 while ((event & RRER_ASF_EVENT) && (tries < 100)) { 6529 drv_usecwait(1); 6530 tries ++; 6531 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 6532 } 6533 6534 bge_nic_put32(bgep, BGE_FIRMWARE_MAILBOX, 6535 BGE_MAGIC_NUM_FIRMWARE_INIT_DONE); 6536 6537 if (bgep->asf_newhandshake) { 6538 switch (mode) { 6539 case BGE_INIT_RESET: 6540 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 6541 BGE_DRV_STATE_START); 6542 break; 6543 case BGE_SHUTDOWN_RESET: 6544 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 6545 BGE_DRV_STATE_UNLOAD); 6546 break; 6547 case BGE_SUSPEND_RESET: 6548 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 6549 BGE_DRV_STATE_SUSPEND); 6550 break; 6551 default: 6552 break; 6553 } 6554 } 6555 6556 if (mode == BGE_INIT_RESET || 6557 mode == BGE_SUSPEND_RESET) 6558 bge_ape_driver_state_change(bgep, mode); 6559 } 6560 6561 6562 void 6563 bge_asf_post_reset_old_mode(bge_t *bgep, uint32_t mode) 6564 { 6565 switch (mode) { 6566 case BGE_INIT_RESET: 6567 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 6568 BGE_DRV_STATE_START); 6569 break; 6570 case BGE_SHUTDOWN_RESET: 6571 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 6572 BGE_DRV_STATE_UNLOAD); 6573 break; 6574 case BGE_SUSPEND_RESET: 6575 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 6576 BGE_DRV_STATE_SUSPEND); 6577 break; 6578 default: 6579 break; 6580 } 6581 } 6582 6583 6584 void 6585 bge_asf_post_reset_new_mode(bge_t *bgep, uint32_t mode) 6586 { 6587 switch (mode) { 6588 case BGE_INIT_RESET: 6589 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 6590 BGE_DRV_STATE_START_DONE); 6591 break; 6592 case BGE_SHUTDOWN_RESET: 6593 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 6594 BGE_DRV_STATE_UNLOAD_DONE); 6595 break; 6596 default: 6597 break; 6598 } 6599 6600 if (mode == BGE_SHUTDOWN_RESET) 6601 bge_ape_driver_state_change(bgep, mode); 6602 } 6603 6604 #endif /* BGE_IPMI_ASF */ 6605