1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include "bge_impl.h" 30 31 #define PIO_ADDR(bgep, offset) ((void *)((caddr_t)(bgep)->io_regs+(offset))) 32 33 /* 34 * Future features ... ? 35 */ 36 #define BGE_CFG_IO8 1 /* 8/16-bit cfg space BIS/BIC */ 37 #define BGE_IND_IO32 1 /* indirect access code */ 38 #define BGE_SEE_IO32 1 /* SEEPROM access code */ 39 #define BGE_FLASH_IO32 1 /* FLASH access code */ 40 41 /* 42 * BGE MSI tunable: 43 * 44 * By default MSI is enabled on all supported platforms but it is disabled 45 * for some Broadcom chips due to known MSI hardware issues. Currently MSI 46 * is enabled only for 5714C A2 and 5715C A2 broadcom chips. 47 */ 48 #if defined(__sparc) 49 boolean_t bge_enable_msi = B_TRUE; 50 #else 51 boolean_t bge_enable_msi = B_FALSE; 52 #endif 53 54 /* 55 * PCI-X/PCI-E relaxed ordering tunable for OS/Nexus driver 56 */ 57 boolean_t bge_relaxed_ordering = B_TRUE; 58 59 /* 60 * Property names 61 */ 62 static char knownids_propname[] = "bge-known-subsystems"; 63 64 /* 65 * Patchable globals: 66 * 67 * bge_autorecover 68 * Enables/disables automatic recovery after fault detection 69 * 70 * bge_mlcr_default 71 * Value to program into the MLCR; controls the chip's GPIO pins 72 * 73 * bge_dma_{rd,wr}prio 74 * Relative priorities of DMA reads & DMA writes respectively. 75 * These may each be patched to any value 0-3. Equal values 76 * will give "fair" (round-robin) arbitration for PCI access. 77 * Unequal values will give one or the other function priority. 78 * 79 * bge_dma_rwctrl 80 * Value to put in the Read/Write DMA control register. See 81 * the Broadcom PRM for things you can fiddle with in this 82 * register ... 83 * 84 * bge_{tx,rx}_{count,ticks}_{norm,intr} 85 * Send/receive interrupt coalescing parameters. Counts are 86 * #s of descriptors, ticks are in microseconds. *norm* values 87 * apply between status updates/interrupts; the *intr* values 88 * refer to the 'during-interrupt' versions - see the PRM. 89 * 90 * NOTE: these values have been determined by measurement. They 91 * differ significantly from the values recommended in the PRM. 92 */ 93 static uint32_t bge_autorecover = 1; 94 static uint32_t bge_mlcr_default = MLCR_DEFAULT; 95 static uint32_t bge_mlcr_default_5714 = MLCR_DEFAULT_5714; 96 97 static uint32_t bge_dma_rdprio = 1; 98 static uint32_t bge_dma_wrprio = 0; 99 static uint32_t bge_dma_rwctrl = PDRWCR_VAR_DEFAULT; 100 static uint32_t bge_dma_rwctrl_5721 = PDRWCR_VAR_5721; 101 static uint32_t bge_dma_rwctrl_5714 = PDRWCR_VAR_5714; 102 static uint32_t bge_dma_rwctrl_5715 = PDRWCR_VAR_5715; 103 104 uint32_t bge_rx_ticks_norm = 128; 105 uint32_t bge_tx_ticks_norm = 2048; /* 8 for FJ2+ !?!? */ 106 uint32_t bge_rx_count_norm = 8; 107 uint32_t bge_tx_count_norm = 128; 108 109 static uint32_t bge_rx_ticks_intr = 128; 110 static uint32_t bge_tx_ticks_intr = 0; /* 8 for FJ2+ !?!? */ 111 static uint32_t bge_rx_count_intr = 2; 112 static uint32_t bge_tx_count_intr = 0; 113 114 /* 115 * Memory pool configuration parameters. 116 * 117 * These are generally specific to each member of the chip family, since 118 * each one may have a different memory size/configuration. 119 * 120 * Setting the mbuf pool length for a specific type of chip to 0 inhibits 121 * the driver from programming the various registers; instead they are left 122 * at their hardware defaults. This is the preferred option for later chips 123 * (5705+), whereas the older chips *required* these registers to be set, 124 * since the h/w default was 0 ;-( 125 */ 126 static uint32_t bge_mbuf_pool_base = MBUF_POOL_BASE_DEFAULT; 127 static uint32_t bge_mbuf_pool_base_5704 = MBUF_POOL_BASE_5704; 128 static uint32_t bge_mbuf_pool_base_5705 = MBUF_POOL_BASE_5705; 129 static uint32_t bge_mbuf_pool_base_5721 = MBUF_POOL_BASE_5721; 130 static uint32_t bge_mbuf_pool_len = MBUF_POOL_LENGTH_DEFAULT; 131 static uint32_t bge_mbuf_pool_len_5704 = MBUF_POOL_LENGTH_5704; 132 static uint32_t bge_mbuf_pool_len_5705 = 0; /* use h/w default */ 133 static uint32_t bge_mbuf_pool_len_5721 = 0; 134 135 /* 136 * Various high and low water marks, thresholds, etc ... 137 * 138 * Note: these are taken from revision 7 of the PRM, and some are different 139 * from both the values in earlier PRMs *and* those determined experimentally 140 * and used in earlier versions of this driver ... 141 */ 142 static uint32_t bge_mbuf_hi_water = MBUF_HIWAT_DEFAULT; 143 static uint32_t bge_mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_DEFAULT; 144 static uint32_t bge_mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_DEFAULT; 145 146 static uint32_t bge_dmad_lo_water = DMAD_POOL_LOWAT_DEFAULT; 147 static uint32_t bge_dmad_hi_water = DMAD_POOL_HIWAT_DEFAULT; 148 static uint32_t bge_lowat_recv_frames = LOWAT_MAX_RECV_FRAMES_DEFAULT; 149 150 static uint32_t bge_replenish_std = STD_RCV_BD_REPLENISH_DEFAULT; 151 static uint32_t bge_replenish_mini = MINI_RCV_BD_REPLENISH_DEFAULT; 152 static uint32_t bge_replenish_jumbo = JUMBO_RCV_BD_REPLENISH_DEFAULT; 153 154 static uint32_t bge_watchdog_count = 1 << 16; 155 static uint16_t bge_dma_miss_limit = 20; 156 157 static uint32_t bge_stop_start_on_sync = 0; 158 159 boolean_t bge_jumbo_enable = B_TRUE; 160 static uint32_t bge_default_jumbo_size = BGE_JUMBO_BUFF_SIZE; 161 162 /* 163 * bge_intr_max_loop controls the maximum loop number within bge_intr. 164 * When loading NIC with heavy network traffic, it is useful. 165 * Increasing this value could have positive effect to throughput, 166 * but it might also increase ticks of a bge ISR stick on CPU, which might 167 * lead to bad UI interactive experience. So tune this with caution. 168 */ 169 static int bge_intr_max_loop = 1; 170 171 /* 172 * ========== Low-level chip & ring buffer manipulation ========== 173 */ 174 175 #define BGE_DBG BGE_DBG_REGS /* debug flag for this code */ 176 177 178 /* 179 * Config space read-modify-write routines 180 */ 181 182 #if BGE_CFG_IO8 183 184 /* 185 * 8- and 16-bit set/clr operations are not used; all the config registers 186 * that we need to do bit-twiddling on are 32 bits wide. I'll leave the 187 * code here, though, in case we ever find that we do want it after all ... 188 */ 189 190 static void bge_cfg_set8(bge_t *bgep, bge_regno_t regno, uint8_t bits); 191 #pragma inline(bge_cfg_set8) 192 193 static void 194 bge_cfg_set8(bge_t *bgep, bge_regno_t regno, uint8_t bits) 195 { 196 uint8_t regval; 197 198 BGE_TRACE(("bge_cfg_set8($%p, 0x%lx, 0x%x)", 199 (void *)bgep, regno, bits)); 200 201 regval = pci_config_get8(bgep->cfg_handle, regno); 202 203 BGE_DEBUG(("bge_cfg_set8($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 204 (void *)bgep, regno, bits, regval, regval | bits)); 205 206 regval |= bits; 207 pci_config_put8(bgep->cfg_handle, regno, regval); 208 } 209 210 static void bge_cfg_clr8(bge_t *bgep, bge_regno_t regno, uint8_t bits); 211 #pragma inline(bge_cfg_clr8) 212 213 static void 214 bge_cfg_clr8(bge_t *bgep, bge_regno_t regno, uint8_t bits) 215 { 216 uint8_t regval; 217 218 BGE_TRACE(("bge_cfg_clr8($%p, 0x%lx, 0x%x)", 219 (void *)bgep, regno, bits)); 220 221 regval = pci_config_get8(bgep->cfg_handle, regno); 222 223 BGE_DEBUG(("bge_cfg_clr8($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 224 (void *)bgep, regno, bits, regval, regval & ~bits)); 225 226 regval &= ~bits; 227 pci_config_put8(bgep->cfg_handle, regno, regval); 228 } 229 230 static void bge_cfg_set16(bge_t *bgep, bge_regno_t regno, uint16_t bits); 231 #pragma inline(bge_cfg_set16) 232 233 static void 234 bge_cfg_set16(bge_t *bgep, bge_regno_t regno, uint16_t bits) 235 { 236 uint16_t regval; 237 238 BGE_TRACE(("bge_cfg_set16($%p, 0x%lx, 0x%x)", 239 (void *)bgep, regno, bits)); 240 241 regval = pci_config_get16(bgep->cfg_handle, regno); 242 243 BGE_DEBUG(("bge_cfg_set16($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 244 (void *)bgep, regno, bits, regval, regval | bits)); 245 246 regval |= bits; 247 pci_config_put16(bgep->cfg_handle, regno, regval); 248 } 249 250 static void bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits); 251 #pragma inline(bge_cfg_clr16) 252 253 static void 254 bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits) 255 { 256 uint16_t regval; 257 258 BGE_TRACE(("bge_cfg_clr16($%p, 0x%lx, 0x%x)", 259 (void *)bgep, regno, bits)); 260 261 regval = pci_config_get16(bgep->cfg_handle, regno); 262 263 BGE_DEBUG(("bge_cfg_clr16($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 264 (void *)bgep, regno, bits, regval, regval & ~bits)); 265 266 regval &= ~bits; 267 pci_config_put16(bgep->cfg_handle, regno, regval); 268 } 269 270 #endif /* BGE_CFG_IO8 */ 271 272 static void bge_cfg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 273 #pragma inline(bge_cfg_set32) 274 275 static void 276 bge_cfg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 277 { 278 uint32_t regval; 279 280 BGE_TRACE(("bge_cfg_set32($%p, 0x%lx, 0x%x)", 281 (void *)bgep, regno, bits)); 282 283 regval = pci_config_get32(bgep->cfg_handle, regno); 284 285 BGE_DEBUG(("bge_cfg_set32($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 286 (void *)bgep, regno, bits, regval, regval | bits)); 287 288 regval |= bits; 289 pci_config_put32(bgep->cfg_handle, regno, regval); 290 } 291 292 static void bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 293 #pragma inline(bge_cfg_clr32) 294 295 static void 296 bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 297 { 298 uint32_t regval; 299 300 BGE_TRACE(("bge_cfg_clr32($%p, 0x%lx, 0x%x)", 301 (void *)bgep, regno, bits)); 302 303 regval = pci_config_get32(bgep->cfg_handle, regno); 304 305 BGE_DEBUG(("bge_cfg_clr32($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 306 (void *)bgep, regno, bits, regval, regval & ~bits)); 307 308 regval &= ~bits; 309 pci_config_put32(bgep->cfg_handle, regno, regval); 310 } 311 312 #if BGE_IND_IO32 313 314 /* 315 * Indirect access to registers & RISC scratchpads, using config space 316 * accesses only. 317 * 318 * This isn't currently used, but someday we might want to use it for 319 * restoring the Subsystem Device/Vendor registers (which aren't directly 320 * writable in Config Space), or for downloading firmware into the RISCs 321 * 322 * In any case there are endian issues to be resolved before this code is 323 * enabled; the bizarre way that bytes get twisted by this chip AND by 324 * the PCI bridge in SPARC systems mean that we shouldn't enable it until 325 * it's been thoroughly tested for all access sizes on all supported 326 * architectures (SPARC *and* x86!). 327 */ 328 uint32_t bge_ind_get32(bge_t *bgep, bge_regno_t regno); 329 #pragma inline(bge_ind_get32) 330 331 uint32_t 332 bge_ind_get32(bge_t *bgep, bge_regno_t regno) 333 { 334 uint32_t val; 335 336 BGE_TRACE(("bge_ind_get32($%p, 0x%lx)", (void *)bgep, regno)); 337 338 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 339 val = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_RIADR); 340 341 BGE_DEBUG(("bge_ind_get32($%p, 0x%lx) => 0x%x", 342 (void *)bgep, regno, val)); 343 344 val = LE_32(val); 345 346 return (val); 347 } 348 349 void bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val); 350 #pragma inline(bge_ind_put32) 351 352 void 353 bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val) 354 { 355 BGE_TRACE(("bge_ind_put32($%p, 0x%lx, 0x%x)", 356 (void *)bgep, regno, val)); 357 358 val = LE_32(val); 359 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 360 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIADR, val); 361 } 362 363 #endif /* BGE_IND_IO32 */ 364 365 #if BGE_DEBUGGING 366 367 static void bge_pci_check(bge_t *bgep); 368 #pragma no_inline(bge_pci_check) 369 370 static void 371 bge_pci_check(bge_t *bgep) 372 { 373 uint16_t pcistatus; 374 375 pcistatus = pci_config_get16(bgep->cfg_handle, PCI_CONF_STAT); 376 if ((pcistatus & (PCI_STAT_R_MAST_AB | PCI_STAT_R_TARG_AB)) != 0) 377 BGE_DEBUG(("bge_pci_check($%p): PCI status 0x%x", 378 (void *)bgep, pcistatus)); 379 } 380 381 #endif /* BGE_DEBUGGING */ 382 383 /* 384 * Perform first-stage chip (re-)initialisation, using only config-space 385 * accesses: 386 * 387 * + Read the vendor/device/revision/subsystem/cache-line-size registers, 388 * returning the data in the structure pointed to by <idp>. 389 * + Configure the target-mode endianness (swap) options. 390 * + Disable interrupts and enable Memory Space accesses. 391 * + Enable or disable Bus Mastering according to the <enable_dma> flag. 392 * 393 * This sequence is adapted from Broadcom document 570X-PG102-R, 394 * page 102, steps 1-3, 6-8 and 11-13. The omitted parts of the sequence 395 * are 4 and 5 (Reset Core and wait) which are handled elsewhere. 396 * 397 * This function MUST be called before any non-config-space accesses 398 * are made; on this first call <enable_dma> is B_FALSE, and it 399 * effectively performs steps 3-1(!) of the initialisation sequence 400 * (the rest are not required but should be harmless). 401 * 402 * It MUST also be called after a chip reset, as this disables 403 * Memory Space cycles! In this case, <enable_dma> is B_TRUE, and 404 * it is effectively performing steps 6-8. 405 */ 406 void bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma); 407 #pragma no_inline(bge_chip_cfg_init) 408 409 void 410 bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma) 411 { 412 ddi_acc_handle_t handle; 413 uint16_t command; 414 uint32_t mhcr; 415 uint16_t value16; 416 int i; 417 418 BGE_TRACE(("bge_chip_cfg_init($%p, $%p, %d)", 419 (void *)bgep, (void *)cidp, enable_dma)); 420 421 /* 422 * Step 3: save PCI cache line size and subsystem vendor ID 423 * 424 * Read all the config-space registers that characterise the 425 * chip, specifically vendor/device/revision/subsystem vendor 426 * and subsystem device id. We expect (but don't check) that 427 * (vendor == VENDOR_ID_BROADCOM) && (device == DEVICE_ID_5704) 428 * 429 * Also save all bus-transaction related registers (cache-line 430 * size, bus-grant/latency parameters, etc). Some of these are 431 * cleared by reset, so we'll have to restore them later. This 432 * comes from the Broadcom document 570X-PG102-R ... 433 * 434 * Note: Broadcom document 570X-PG102-R seems to be in error 435 * here w.r.t. the offsets of the Subsystem Vendor ID and 436 * Subsystem (Device) ID registers, which are the opposite way 437 * round according to the PCI standard. For good measure, we 438 * save/restore both anyway. 439 */ 440 handle = bgep->cfg_handle; 441 442 mhcr = pci_config_get32(handle, PCI_CONF_BGE_MHCR); 443 cidp->asic_rev = mhcr & MHCR_CHIP_REV_MASK; 444 cidp->businfo = pci_config_get32(handle, PCI_CONF_BGE_PCISTATE); 445 cidp->command = pci_config_get16(handle, PCI_CONF_COMM); 446 447 cidp->vendor = pci_config_get16(handle, PCI_CONF_VENID); 448 cidp->device = pci_config_get16(handle, PCI_CONF_DEVID); 449 cidp->subven = pci_config_get16(handle, PCI_CONF_SUBVENID); 450 cidp->subdev = pci_config_get16(handle, PCI_CONF_SUBSYSID); 451 cidp->revision = pci_config_get8(handle, PCI_CONF_REVID); 452 cidp->clsize = pci_config_get8(handle, PCI_CONF_CACHE_LINESZ); 453 cidp->latency = pci_config_get8(handle, PCI_CONF_LATENCY_TIMER); 454 455 BGE_DEBUG(("bge_chip_cfg_init: %s bus is %s and %s; #INTA is %s", 456 cidp->businfo & PCISTATE_BUS_IS_PCI ? "PCI" : "PCI-X", 457 cidp->businfo & PCISTATE_BUS_IS_FAST ? "fast" : "slow", 458 cidp->businfo & PCISTATE_BUS_IS_32_BIT ? "narrow" : "wide", 459 cidp->businfo & PCISTATE_INTA_STATE ? "high" : "low")); 460 BGE_DEBUG(("bge_chip_cfg_init: vendor 0x%x device 0x%x revision 0x%x", 461 cidp->vendor, cidp->device, cidp->revision)); 462 BGE_DEBUG(("bge_chip_cfg_init: subven 0x%x subdev 0x%x asic_rev 0x%x", 463 cidp->subven, cidp->subdev, cidp->asic_rev)); 464 BGE_DEBUG(("bge_chip_cfg_init: clsize %d latency %d command 0x%x", 465 cidp->clsize, cidp->latency, cidp->command)); 466 467 /* 468 * Step 2 (also step 6): disable and clear interrupts. 469 * Steps 11-13: configure PIO endianness options, and enable 470 * indirect register access. We'll also select any other 471 * options controlled by the MHCR (e.g. tagged status, mask 472 * interrupt mode) at this stage ... 473 * 474 * Note: internally, the chip is 64-bit and BIG-endian, but 475 * since it talks to the host over a (LITTLE-endian) PCI bus, 476 * it normally swaps bytes around at the PCI interface. 477 * However, the PCI host bridge on SPARC systems normally 478 * swaps the byte lanes around too, since SPARCs are also 479 * BIG-endian. So it turns out that on SPARC, the right 480 * option is to tell the chip to swap (and the host bridge 481 * will swap back again), whereas on x86 we ask the chip 482 * NOT to swap, so the natural little-endianness of the 483 * PCI bus is assumed. Then the only thing that doesn't 484 * automatically work right is access to an 8-byte register 485 * by a little-endian host; but we don't want to set the 486 * MHCR_ENABLE_REGISTER_WORD_SWAP bit because then 4-byte 487 * accesses don't go where expected ;-( So we live with 488 * that, and perform word-swaps in software in the few cases 489 * where a chip register is defined as an 8-byte value -- 490 * see the code below for details ... 491 * 492 * Note: the meaning of the 'MASK_INTERRUPT_MODE' bit isn't 493 * very clear in the register description in the PRM, but 494 * Broadcom document 570X-PG104-R page 248 explains a little 495 * more (under "Broadcom Mask Mode"). The bit changes the way 496 * the MASK_PCI_INT_OUTPUT bit works: with MASK_INTERRUPT_MODE 497 * clear, the chip interprets MASK_PCI_INT_OUTPUT in the same 498 * way as the 5700 did, which isn't very convenient. Setting 499 * the MASK_INTERRUPT_MODE bit makes the MASK_PCI_INT_OUTPUT 500 * bit do just what its name says -- MASK the PCI #INTA output 501 * (i.e. deassert the signal at the pin) leaving all internal 502 * state unchanged. This is much more convenient for our 503 * interrupt handler, so we set MASK_INTERRUPT_MODE here. 504 * 505 * Note: the inconvenient semantics of the interrupt mailbox 506 * (nonzero disables and acknowledges/clears the interrupt, 507 * zero enables AND CLEARS it) would make race conditions 508 * likely in the interrupt handler: 509 * 510 * (1) acknowledge & disable interrupts 511 * (2) while (more to do) 512 * process packets 513 * (3) enable interrupts -- also clears pending 514 * 515 * If the chip received more packets and internally generated 516 * an interrupt between the check at (2) and the mbox write 517 * at (3), this interrupt would be lost :-( 518 * 519 * The best way to avoid this is to use TAGGED STATUS mode, 520 * where the chip includes a unique tag in each status block 521 * update, and the host, when re-enabling interrupts, passes 522 * the last tag it saw back to the chip; then the chip can 523 * see whether the host is truly up to date, and regenerate 524 * its interrupt if not. 525 */ 526 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 527 MHCR_ENABLE_TAGGED_STATUS_MODE | 528 MHCR_MASK_INTERRUPT_MODE | 529 MHCR_CLEAR_INTERRUPT_INTA; 530 531 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 532 mhcr |= MHCR_MASK_PCI_INT_OUTPUT; 533 534 #ifdef _BIG_ENDIAN 535 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 536 #endif /* _BIG_ENDIAN */ 537 538 pci_config_put32(handle, PCI_CONF_BGE_MHCR, mhcr); 539 540 #ifdef BGE_IPMI_ASF 541 bgep->asf_wordswapped = B_FALSE; 542 #endif 543 /* 544 * Step 1 (also step 7): Enable PCI Memory Space accesses 545 * Disable Memory Write/Invalidate 546 * Enable or disable Bus Mastering 547 * 548 * Note that all other bits are taken from the original value saved 549 * the first time through here, rather than from the current register 550 * value, 'cos that will have been cleared by a soft RESET since. 551 * In this way we preserve the OBP/nexus-parent's preferred settings 552 * of the parity-error and system-error enable bits across multiple 553 * chip RESETs. 554 */ 555 command = bgep->chipid.command | PCI_COMM_MAE; 556 command &= ~(PCI_COMM_ME|PCI_COMM_MEMWR_INVAL); 557 if (enable_dma) 558 command |= PCI_COMM_ME; 559 /* 560 * on BCM5714 revision A0, false parity error gets generated 561 * due to a logic bug. Provide a workaround by disabling parity 562 * error. 563 */ 564 if (((cidp->device == DEVICE_ID_5714C) || 565 (cidp->device == DEVICE_ID_5714S)) && 566 (cidp->revision == REVISION_ID_5714_A0)) { 567 command &= ~PCI_COMM_PARITY_DETECT; 568 } 569 pci_config_put16(handle, PCI_CONF_COMM, command); 570 571 /* 572 * On some PCI-E device, there were instances when 573 * the device was still link training. 574 */ 575 if (bgep->chipid.pci_type == BGE_PCI_E) { 576 i = 0; 577 value16 = pci_config_get16(handle, PCI_CONF_COMM); 578 while ((value16 != command) && (i < 100)) { 579 drv_usecwait(200); 580 value16 = pci_config_get16(handle, PCI_CONF_COMM); 581 ++i; 582 } 583 } 584 585 /* 586 * Clear any remaining error status bits 587 */ 588 pci_config_put16(handle, PCI_CONF_STAT, ~0); 589 590 /* 591 * Do following if and only if the device is NOT BCM5714C OR 592 * BCM5715C 593 */ 594 if (!((cidp->device == DEVICE_ID_5714C) || 595 (cidp->device == DEVICE_ID_5715C))) { 596 /* 597 * Make sure these indirect-access registers are sane 598 * rather than random after power-up or reset 599 */ 600 pci_config_put32(handle, PCI_CONF_BGE_RIAAR, 0); 601 pci_config_put32(handle, PCI_CONF_BGE_MWBAR, 0); 602 } 603 /* 604 * Step 8: Disable PCI-X/PCI-E Relaxed Ordering 605 */ 606 bge_cfg_clr16(bgep, PCIX_CONF_COMM, PCIX_COMM_RELAXED); 607 608 if (cidp->pci_type == BGE_PCI_E) 609 bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL, 610 DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED); 611 } 612 613 #ifdef __amd64 614 /* 615 * Distinguish CPU types 616 * 617 * These use to distinguish AMD64 or Intel EM64T of CPU running mode. 618 * If CPU runs on Intel EM64T mode,the 64bit operation cannot works fine 619 * for PCI-Express based network interface card. This is the work-around 620 * for those nics. 621 */ 622 static boolean_t bge_get_em64t_type(void); 623 #pragma inline(bge_get_em64t_type) 624 625 static boolean_t 626 bge_get_em64t_type(void) 627 { 628 629 return (x86_vendor == X86_VENDOR_Intel); 630 } 631 #endif 632 633 /* 634 * Operating register get/set access routines 635 */ 636 637 uint32_t bge_reg_get32(bge_t *bgep, bge_regno_t regno); 638 #pragma inline(bge_reg_get32) 639 640 uint32_t 641 bge_reg_get32(bge_t *bgep, bge_regno_t regno) 642 { 643 BGE_TRACE(("bge_reg_get32($%p, 0x%lx)", 644 (void *)bgep, regno)); 645 646 return (ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno))); 647 } 648 649 void bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data); 650 #pragma inline(bge_reg_put32) 651 652 void 653 bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data) 654 { 655 BGE_TRACE(("bge_reg_put32($%p, 0x%lx, 0x%x)", 656 (void *)bgep, regno, data)); 657 658 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), data); 659 BGE_PCICHK(bgep); 660 } 661 662 void bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 663 #pragma inline(bge_reg_set32) 664 665 void 666 bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 667 { 668 uint32_t regval; 669 670 BGE_TRACE(("bge_reg_set32($%p, 0x%lx, 0x%x)", 671 (void *)bgep, regno, bits)); 672 673 regval = bge_reg_get32(bgep, regno); 674 regval |= bits; 675 bge_reg_put32(bgep, regno, regval); 676 } 677 678 void bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 679 #pragma inline(bge_reg_clr32) 680 681 void 682 bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 683 { 684 uint32_t regval; 685 686 BGE_TRACE(("bge_reg_clr32($%p, 0x%lx, 0x%x)", 687 (void *)bgep, regno, bits)); 688 689 regval = bge_reg_get32(bgep, regno); 690 regval &= ~bits; 691 bge_reg_put32(bgep, regno, regval); 692 } 693 694 static uint64_t bge_reg_get64(bge_t *bgep, bge_regno_t regno); 695 #pragma inline(bge_reg_get64) 696 697 static uint64_t 698 bge_reg_get64(bge_t *bgep, bge_regno_t regno) 699 { 700 uint64_t regval; 701 702 #ifdef __amd64 703 if (bge_get_em64t_type()) { 704 regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4)); 705 regval <<= 32; 706 regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 707 } else { 708 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 709 } 710 #else 711 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 712 #endif 713 714 #ifdef _LITTLE_ENDIAN 715 regval = (regval >> 32) | (regval << 32); 716 #endif /* _LITTLE_ENDIAN */ 717 718 BGE_TRACE(("bge_reg_get64($%p, 0x%lx) = 0x%016llx", 719 (void *)bgep, regno, regval)); 720 721 return (regval); 722 } 723 724 static void bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data); 725 #pragma inline(bge_reg_put64) 726 727 static void 728 bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data) 729 { 730 BGE_TRACE(("bge_reg_put64($%p, 0x%lx, 0x%016llx)", 731 (void *)bgep, regno, data)); 732 733 #ifdef _LITTLE_ENDIAN 734 data = ((data >> 32) | (data << 32)); 735 #endif /* _LITTLE_ENDIAN */ 736 737 #ifdef __amd64 738 if (bge_get_em64t_type()) { 739 ddi_put32(bgep->io_handle, 740 PIO_ADDR(bgep, regno), (uint32_t)data); 741 BGE_PCICHK(bgep); 742 ddi_put32(bgep->io_handle, 743 PIO_ADDR(bgep, regno + 4), (uint32_t)(data >> 32)); 744 745 } else { 746 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 747 } 748 #else 749 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 750 #endif 751 752 BGE_PCICHK(bgep); 753 } 754 755 /* 756 * The DDI doesn't provide get/put functions for 128 bit data 757 * so we put RCBs out as two 64-bit chunks instead. 758 */ 759 static void bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 760 #pragma inline(bge_reg_putrcb) 761 762 static void 763 bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 764 { 765 uint64_t *p; 766 767 BGE_TRACE(("bge_reg_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 768 (void *)bgep, addr, rcbp->host_ring_addr, 769 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 770 771 ASSERT((addr % sizeof (*rcbp)) == 0); 772 773 p = (void *)rcbp; 774 bge_reg_put64(bgep, addr, *p++); 775 bge_reg_put64(bgep, addr+8, *p); 776 } 777 778 void bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data); 779 #pragma inline(bge_mbx_put) 780 781 void 782 bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data) 783 { 784 BGE_TRACE(("bge_mbx_put($%p, 0x%lx, 0x%016llx)", 785 (void *)bgep, regno, data)); 786 787 /* 788 * Mailbox registers are nominally 64 bits on the 5701, but 789 * the MSW isn't used. On the 5703, they're only 32 bits 790 * anyway. So here we just write the lower(!) 32 bits - 791 * remembering that the chip is big-endian, even though the 792 * PCI bus is little-endian ... 793 */ 794 #ifdef _BIG_ENDIAN 795 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno+4), (uint32_t)data); 796 #else 797 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), (uint32_t)data); 798 #endif /* _BIG_ENDIAN */ 799 BGE_PCICHK(bgep); 800 } 801 802 #if BGE_DEBUGGING 803 804 void bge_led_mark(bge_t *bgep); 805 #pragma no_inline(bge_led_mark) 806 807 void 808 bge_led_mark(bge_t *bgep) 809 { 810 uint32_t led_ctrl = LED_CONTROL_OVERRIDE_LINK | 811 LED_CONTROL_1000MBPS_LED | 812 LED_CONTROL_100MBPS_LED | 813 LED_CONTROL_10MBPS_LED; 814 815 /* 816 * Blink all three LINK LEDs on simultaneously, then all off, 817 * then restore to automatic hardware control. This is used 818 * in laboratory testing to trigger a logic analyser or scope. 819 */ 820 bge_reg_set32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 821 led_ctrl ^= LED_CONTROL_OVERRIDE_LINK; 822 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 823 led_ctrl = LED_CONTROL_OVERRIDE_LINK; 824 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 825 } 826 827 #endif /* BGE_DEBUGGING */ 828 829 /* 830 * NIC on-chip memory access routines 831 * 832 * Only 32K of NIC memory is visible at a time, controlled by the 833 * Memory Window Base Address Register (in PCI config space). Once 834 * this is set, the 32K region of NIC-local memory that it refers 835 * to can be directly addressed in the upper 32K of the 64K of PCI 836 * memory space used for the device. 837 */ 838 839 static void bge_nic_setwin(bge_t *bgep, bge_regno_t base); 840 #pragma inline(bge_nic_setwin) 841 842 static void 843 bge_nic_setwin(bge_t *bgep, bge_regno_t base) 844 { 845 chip_id_t *cidp; 846 847 BGE_TRACE(("bge_nic_setwin($%p, 0x%lx)", 848 (void *)bgep, base)); 849 850 ASSERT((base & MWBAR_GRANULE_MASK) == 0); 851 852 /* 853 * Don't do repeated zero data writes, 854 * if the device is BCM5714C/15C. 855 */ 856 cidp = &bgep->chipid; 857 if ((cidp->device == DEVICE_ID_5714C) || 858 (cidp->device == DEVICE_ID_5715C)) { 859 if (bgep->lastWriteZeroData && (base == (bge_regno_t)0)) 860 return; 861 /* Adjust lastWriteZeroData */ 862 bgep->lastWriteZeroData = ((base == (bge_regno_t)0) ? 863 B_TRUE : B_FALSE); 864 } 865 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, base); 866 } 867 868 static uint32_t bge_nic_get32(bge_t *bgep, bge_regno_t addr); 869 #pragma inline(bge_nic_get32) 870 871 static uint32_t 872 bge_nic_get32(bge_t *bgep, bge_regno_t addr) 873 { 874 uint32_t data; 875 876 #if defined(BGE_IPMI_ASF) && !defined(__sparc) 877 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 878 /* workaround for word swap error */ 879 if (addr & 4) 880 addr = addr - 4; 881 else 882 addr = addr + 4; 883 } 884 #endif 885 886 #ifdef __sparc 887 data = bge_nic_read32(bgep, addr); 888 #else 889 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 890 addr &= MWBAR_GRANULE_MASK; 891 addr += NIC_MEM_WINDOW_OFFSET; 892 893 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 894 #endif 895 896 BGE_TRACE(("bge_nic_get32($%p, 0x%lx) = 0x%08x", 897 (void *)bgep, addr, data)); 898 899 return (data); 900 } 901 902 void bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data); 903 #pragma inline(bge_nic_put32) 904 905 void 906 bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data) 907 { 908 BGE_TRACE(("bge_nic_put32($%p, 0x%lx, 0x%08x)", 909 (void *)bgep, addr, data)); 910 911 #if defined(BGE_IPMI_ASF) && !defined(__sparc) 912 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 913 /* workaround for word swap error */ 914 if (addr & 4) 915 addr = addr - 4; 916 else 917 addr = addr + 4; 918 } 919 #endif 920 921 #ifdef __sparc 922 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr); 923 data = LE_32(data); 924 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR, data); 925 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0); 926 #else 927 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 928 addr &= MWBAR_GRANULE_MASK; 929 addr += NIC_MEM_WINDOW_OFFSET; 930 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), data); 931 BGE_PCICHK(bgep); 932 #endif 933 } 934 935 static uint64_t bge_nic_get64(bge_t *bgep, bge_regno_t addr); 936 #pragma inline(bge_nic_get64) 937 938 static uint64_t 939 bge_nic_get64(bge_t *bgep, bge_regno_t addr) 940 { 941 uint64_t data; 942 943 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 944 addr &= MWBAR_GRANULE_MASK; 945 addr += NIC_MEM_WINDOW_OFFSET; 946 947 #ifdef __amd64 948 if (bge_get_em64t_type()) { 949 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 950 data <<= 32; 951 data |= ddi_get32(bgep->io_handle, 952 PIO_ADDR(bgep, addr + 4)); 953 } else { 954 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 955 } 956 #else 957 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 958 #endif 959 960 BGE_TRACE(("bge_nic_get64($%p, 0x%lx) = 0x%016llx", 961 (void *)bgep, addr, data)); 962 963 return (data); 964 } 965 966 static void bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data); 967 #pragma inline(bge_nic_put64) 968 969 static void 970 bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data) 971 { 972 BGE_TRACE(("bge_nic_put64($%p, 0x%lx, 0x%016llx)", 973 (void *)bgep, addr, data)); 974 975 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 976 addr &= MWBAR_GRANULE_MASK; 977 addr += NIC_MEM_WINDOW_OFFSET; 978 979 #ifdef __amd64 980 if (bge_get_em64t_type()) { 981 ddi_put32(bgep->io_handle, 982 PIO_ADDR(bgep, addr), (uint32_t)data); 983 BGE_PCICHK(bgep); 984 ddi_put32(bgep->io_handle, 985 PIO_ADDR(bgep, addr + 4), (uint32_t)(data >> 32)); 986 } else { 987 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 988 } 989 #else 990 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 991 #endif 992 993 BGE_PCICHK(bgep); 994 } 995 996 /* 997 * The DDI doesn't provide get/put functions for 128 bit data 998 * so we put RCBs out as two 64-bit chunks instead. 999 */ 1000 static void bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 1001 #pragma inline(bge_nic_putrcb) 1002 1003 static void 1004 bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 1005 { 1006 uint64_t *p; 1007 1008 BGE_TRACE(("bge_nic_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 1009 (void *)bgep, addr, rcbp->host_ring_addr, 1010 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 1011 1012 ASSERT((addr % sizeof (*rcbp)) == 0); 1013 1014 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 1015 addr &= MWBAR_GRANULE_MASK; 1016 addr += NIC_MEM_WINDOW_OFFSET; 1017 1018 p = (void *)rcbp; 1019 #ifdef __amd64 1020 if (bge_get_em64t_type()) { 1021 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), 1022 (uint32_t)(*p)); 1023 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4), 1024 (uint32_t)(*p >> 32)); 1025 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8), 1026 (uint32_t)(*(p + 1))); 1027 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12), 1028 (uint32_t)(*p >> 32)); 1029 1030 } else { 1031 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 1032 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr+8), *p); 1033 } 1034 #else 1035 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 1036 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p); 1037 #endif 1038 1039 BGE_PCICHK(bgep); 1040 } 1041 1042 static void bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes); 1043 #pragma inline(bge_nic_zero) 1044 1045 static void 1046 bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes) 1047 { 1048 BGE_TRACE(("bge_nic_zero($%p, 0x%lx, 0x%x)", 1049 (void *)bgep, addr, nbytes)); 1050 1051 ASSERT((addr & ~MWBAR_GRANULE_MASK) == 1052 ((addr+nbytes) & ~MWBAR_GRANULE_MASK)); 1053 1054 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 1055 addr &= MWBAR_GRANULE_MASK; 1056 addr += NIC_MEM_WINDOW_OFFSET; 1057 1058 (void) ddi_device_zero(bgep->io_handle, PIO_ADDR(bgep, addr), 1059 nbytes, 1, DDI_DATA_SZ08_ACC); 1060 BGE_PCICHK(bgep); 1061 } 1062 1063 /* 1064 * MII (PHY) register get/set access routines 1065 * 1066 * These use the chip's MII auto-access method, controlled by the 1067 * MII Communication register at 0x044c, so the CPU doesn't have 1068 * to fiddle with the individual bits. 1069 */ 1070 1071 #undef BGE_DBG 1072 #define BGE_DBG BGE_DBG_MII /* debug flag for this code */ 1073 1074 static uint16_t bge_mii_access(bge_t *bgep, bge_regno_t regno, 1075 uint16_t data, uint32_t cmd); 1076 #pragma no_inline(bge_mii_access) 1077 1078 static uint16_t 1079 bge_mii_access(bge_t *bgep, bge_regno_t regno, uint16_t data, uint32_t cmd) 1080 { 1081 uint32_t timeout; 1082 uint32_t regval1; 1083 uint32_t regval2; 1084 1085 BGE_TRACE(("bge_mii_access($%p, 0x%lx, 0x%x, 0x%x)", 1086 (void *)bgep, regno, data, cmd)); 1087 1088 ASSERT(mutex_owned(bgep->genlock)); 1089 1090 /* 1091 * Assemble the command ... 1092 */ 1093 cmd |= data << MI_COMMS_DATA_SHIFT; 1094 cmd |= regno << MI_COMMS_REGISTER_SHIFT; 1095 cmd |= bgep->phy_mii_addr << MI_COMMS_ADDRESS_SHIFT; 1096 cmd |= MI_COMMS_START; 1097 1098 /* 1099 * Wait for any command already in progress ... 1100 * 1101 * Note: this *shouldn't* ever find that there is a command 1102 * in progress, because we already hold the <genlock> mutex. 1103 * Nonetheless, we have sometimes seen the MI_COMMS_START 1104 * bit set here -- it seems that the chip can initiate MII 1105 * accesses internally, even with polling OFF. 1106 */ 1107 regval1 = regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1108 for (timeout = 100; ; ) { 1109 if ((regval2 & MI_COMMS_START) == 0) { 1110 bge_reg_put32(bgep, MI_COMMS_REG, cmd); 1111 break; 1112 } 1113 if (--timeout == 0) 1114 break; 1115 drv_usecwait(10); 1116 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1117 } 1118 1119 if (timeout == 0) 1120 return ((uint16_t)~0u); 1121 1122 if (timeout != 100) 1123 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1124 "MI_COMMS_START set for %d us; 0x%x->0x%x", 1125 cmd, 10*(100-timeout), regval1, regval2)); 1126 1127 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1128 for (timeout = 1000; ; ) { 1129 if ((regval1 & MI_COMMS_START) == 0) 1130 break; 1131 if (--timeout == 0) 1132 break; 1133 drv_usecwait(10); 1134 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1135 } 1136 1137 /* 1138 * Drop out early if the READ FAILED bit is set -- this chip 1139 * could be a 5703/4S, with a SerDes instead of a PHY! 1140 */ 1141 if (regval2 & MI_COMMS_READ_FAILED) 1142 return ((uint16_t)~0u); 1143 1144 if (timeout == 0) 1145 return ((uint16_t)~0u); 1146 1147 /* 1148 * The PRM says to wait 5us after seeing the START bit clear 1149 * and then re-read the register to get the final value of the 1150 * data field, in order to avoid a race condition where the 1151 * START bit is clear but the data field isn't yet valid. 1152 * 1153 * Note: we don't actually seem to be encounter this race; 1154 * except when the START bit is seen set again (see below), 1155 * the data field doesn't change during this 5us interval. 1156 */ 1157 drv_usecwait(5); 1158 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1159 1160 /* 1161 * Unfortunately, when following the PRMs instructions above, 1162 * we have occasionally seen the START bit set again(!) in the 1163 * value read after the 5us delay. This seems to be due to the 1164 * chip autonomously starting another MII access internally. 1165 * In such cases, the command/data/etc fields relate to the 1166 * internal command, rather than the one that we thought had 1167 * just finished. So in this case, we fall back to returning 1168 * the data from the original read that showed START clear. 1169 */ 1170 if (regval2 & MI_COMMS_START) { 1171 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1172 "MI_COMMS_START set after transaction; 0x%x->0x%x", 1173 cmd, regval1, regval2)); 1174 regval2 = regval1; 1175 } 1176 1177 if (regval2 & MI_COMMS_START) 1178 return ((uint16_t)~0u); 1179 1180 if (regval2 & MI_COMMS_READ_FAILED) 1181 return ((uint16_t)~0u); 1182 1183 return ((regval2 & MI_COMMS_DATA_MASK) >> MI_COMMS_DATA_SHIFT); 1184 } 1185 1186 uint16_t bge_mii_get16(bge_t *bgep, bge_regno_t regno); 1187 #pragma no_inline(bge_mii_get16) 1188 1189 uint16_t 1190 bge_mii_get16(bge_t *bgep, bge_regno_t regno) 1191 { 1192 BGE_TRACE(("bge_mii_get16($%p, 0x%lx)", 1193 (void *)bgep, regno)); 1194 1195 ASSERT(mutex_owned(bgep->genlock)); 1196 1197 return (bge_mii_access(bgep, regno, 0, MI_COMMS_COMMAND_READ)); 1198 } 1199 1200 void bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data); 1201 #pragma no_inline(bge_mii_put16) 1202 1203 void 1204 bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data) 1205 { 1206 BGE_TRACE(("bge_mii_put16($%p, 0x%lx, 0x%x)", 1207 (void *)bgep, regno, data)); 1208 1209 ASSERT(mutex_owned(bgep->genlock)); 1210 1211 (void) bge_mii_access(bgep, regno, data, MI_COMMS_COMMAND_WRITE); 1212 } 1213 1214 #undef BGE_DBG 1215 #define BGE_DBG BGE_DBG_SEEPROM /* debug flag for this code */ 1216 1217 #if BGE_SEE_IO32 || BGE_FLASH_IO32 1218 1219 /* 1220 * Basic SEEPROM get/set access routine 1221 * 1222 * This uses the chip's SEEPROM auto-access method, controlled by the 1223 * Serial EEPROM Address/Data Registers at 0x6838/683c, so the CPU 1224 * doesn't have to fiddle with the individual bits. 1225 * 1226 * The caller should hold <genlock> and *also* have already acquired 1227 * the right to access the SEEPROM, via bge_nvmem_acquire() above. 1228 * 1229 * Return value: 1230 * 0 on success, 1231 * ENODATA on access timeout (maybe retryable: device may just be busy) 1232 * EPROTO on other h/w or s/w errors. 1233 * 1234 * <*dp> is an input to a SEEPROM_ACCESS_WRITE operation, or an output 1235 * from a (successful) SEEPROM_ACCESS_READ. 1236 */ 1237 static int bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1238 uint32_t *dp); 1239 #pragma no_inline(bge_seeprom_access) 1240 1241 static int 1242 bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1243 { 1244 uint32_t tries; 1245 uint32_t regval; 1246 1247 ASSERT(mutex_owned(bgep->genlock)); 1248 1249 /* 1250 * On the newer chips that support both SEEPROM & Flash, we need 1251 * to specifically enable SEEPROM access (Flash is the default). 1252 * On older chips, we don't; SEEPROM is the only NVtype supported, 1253 * and the NVM control registers don't exist ... 1254 */ 1255 switch (bgep->chipid.nvtype) { 1256 case BGE_NVTYPE_NONE: 1257 case BGE_NVTYPE_UNKNOWN: 1258 _NOTE(NOTREACHED) 1259 case BGE_NVTYPE_SEEPROM: 1260 break; 1261 1262 case BGE_NVTYPE_LEGACY_SEEPROM: 1263 case BGE_NVTYPE_UNBUFFERED_FLASH: 1264 case BGE_NVTYPE_BUFFERED_FLASH: 1265 default: 1266 bge_reg_set32(bgep, NVM_CONFIG1_REG, 1267 NVM_CFG1_LEGACY_SEEPROM_MODE); 1268 break; 1269 } 1270 1271 /* 1272 * Check there's no command in progress. 1273 * 1274 * Note: this *shouldn't* ever find that there is a command 1275 * in progress, because we already hold the <genlock> mutex. 1276 * Also, to ensure we don't have a conflict with the chip's 1277 * internal firmware or a process accessing the same (shared) 1278 * SEEPROM through the other port of a 5704, we've already 1279 * been through the "software arbitration" protocol. 1280 * So this is just a final consistency check: we shouldn't 1281 * see EITHER the START bit (command started but not complete) 1282 * OR the COMPLETE bit (command completed but not cleared). 1283 */ 1284 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1285 if (regval & SEEPROM_ACCESS_START) 1286 return (EPROTO); 1287 if (regval & SEEPROM_ACCESS_COMPLETE) 1288 return (EPROTO); 1289 1290 /* 1291 * Assemble the command ... 1292 */ 1293 cmd |= addr & SEEPROM_ACCESS_ADDRESS_MASK; 1294 addr >>= SEEPROM_ACCESS_ADDRESS_SIZE; 1295 addr <<= SEEPROM_ACCESS_DEVID_SHIFT; 1296 cmd |= addr & SEEPROM_ACCESS_DEVID_MASK; 1297 cmd |= SEEPROM_ACCESS_START; 1298 cmd |= SEEPROM_ACCESS_COMPLETE; 1299 cmd |= regval & SEEPROM_ACCESS_HALFCLOCK_MASK; 1300 1301 bge_reg_put32(bgep, SERIAL_EEPROM_DATA_REG, *dp); 1302 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, cmd); 1303 1304 /* 1305 * By observation, a successful access takes ~20us on a 5703/4, 1306 * but apparently much longer (up to 1000us) on the obsolescent 1307 * BCM5700/BCM5701. We want to be sure we don't get any false 1308 * timeouts here; but OTOH, we don't want a bogus access to lock 1309 * out interrupts for longer than necessary. So we'll allow up 1310 * to 1000us ... 1311 */ 1312 for (tries = 0; tries < 1000; ++tries) { 1313 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1314 if (regval & SEEPROM_ACCESS_COMPLETE) 1315 break; 1316 drv_usecwait(1); 1317 } 1318 1319 if (regval & SEEPROM_ACCESS_COMPLETE) { 1320 /* 1321 * All OK; read the SEEPROM data register, then write back 1322 * the value read from the address register in order to 1323 * clear the <complete> bit and leave the SEEPROM access 1324 * state machine idle, ready for the next access ... 1325 */ 1326 BGE_DEBUG(("bge_seeprom_access: complete after %d us", tries)); 1327 *dp = bge_reg_get32(bgep, SERIAL_EEPROM_DATA_REG); 1328 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, regval); 1329 return (0); 1330 } 1331 1332 /* 1333 * Hmm ... what happened here? 1334 * 1335 * Most likely, the user addressed a non-existent SEEPROM. Or 1336 * maybe the SEEPROM was busy internally (e.g. processing a write) 1337 * and didn't respond to being addressed. Either way, it's left 1338 * the SEEPROM access state machine wedged. So we'll reset it 1339 * before we leave, so it's ready for next time ... 1340 */ 1341 BGE_DEBUG(("bge_seeprom_access: timed out after %d us", tries)); 1342 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 1343 return (ENODATA); 1344 } 1345 1346 /* 1347 * Basic Flash get/set access routine 1348 * 1349 * These use the chip's Flash auto-access method, controlled by the 1350 * Flash Access Registers at 0x7000-701c, so the CPU doesn't have to 1351 * fiddle with the individual bits. 1352 * 1353 * The caller should hold <genlock> and *also* have already acquired 1354 * the right to access the Flash, via bge_nvmem_acquire() above. 1355 * 1356 * Return value: 1357 * 0 on success, 1358 * ENODATA on access timeout (maybe retryable: device may just be busy) 1359 * ENODEV if the NVmem device is missing or otherwise unusable 1360 * 1361 * <*dp> is an input to a NVM_FLASH_CMD_WR operation, or an output 1362 * from a (successful) NVM_FLASH_CMD_RD. 1363 */ 1364 static int bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1365 uint32_t *dp); 1366 #pragma no_inline(bge_flash_access) 1367 1368 static int 1369 bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1370 { 1371 uint32_t tries; 1372 uint32_t regval; 1373 1374 ASSERT(mutex_owned(bgep->genlock)); 1375 1376 /* 1377 * On the newer chips that support both SEEPROM & Flash, we need 1378 * to specifically disable SEEPROM access while accessing Flash. 1379 * The older chips don't support Flash, and the NVM registers don't 1380 * exist, so we shouldn't be here at all! 1381 */ 1382 switch (bgep->chipid.nvtype) { 1383 case BGE_NVTYPE_NONE: 1384 case BGE_NVTYPE_UNKNOWN: 1385 _NOTE(NOTREACHED) 1386 case BGE_NVTYPE_SEEPROM: 1387 return (ENODEV); 1388 1389 case BGE_NVTYPE_LEGACY_SEEPROM: 1390 case BGE_NVTYPE_UNBUFFERED_FLASH: 1391 case BGE_NVTYPE_BUFFERED_FLASH: 1392 default: 1393 bge_reg_clr32(bgep, NVM_CONFIG1_REG, 1394 NVM_CFG1_LEGACY_SEEPROM_MODE); 1395 break; 1396 } 1397 1398 /* 1399 * Assemble the command ... 1400 */ 1401 addr &= NVM_FLASH_ADDR_MASK; 1402 cmd |= NVM_FLASH_CMD_DOIT; 1403 cmd |= NVM_FLASH_CMD_FIRST; 1404 cmd |= NVM_FLASH_CMD_LAST; 1405 cmd |= NVM_FLASH_CMD_DONE; 1406 1407 bge_reg_put32(bgep, NVM_FLASH_WRITE_REG, *dp); 1408 bge_reg_put32(bgep, NVM_FLASH_ADDR_REG, addr); 1409 bge_reg_put32(bgep, NVM_FLASH_CMD_REG, cmd); 1410 1411 /* 1412 * Allow up to 1000ms ... 1413 */ 1414 for (tries = 0; tries < 1000; ++tries) { 1415 regval = bge_reg_get32(bgep, NVM_FLASH_CMD_REG); 1416 if (regval & NVM_FLASH_CMD_DONE) 1417 break; 1418 drv_usecwait(1); 1419 } 1420 1421 if (regval & NVM_FLASH_CMD_DONE) { 1422 /* 1423 * All OK; read the data from the Flash read register 1424 */ 1425 BGE_DEBUG(("bge_flash_access: complete after %d us", tries)); 1426 *dp = bge_reg_get32(bgep, NVM_FLASH_READ_REG); 1427 return (0); 1428 } 1429 1430 /* 1431 * Hmm ... what happened here? 1432 * 1433 * Most likely, the user addressed a non-existent Flash. Or 1434 * maybe the Flash was busy internally (e.g. processing a write) 1435 * and didn't respond to being addressed. Either way, there's 1436 * nothing we can here ... 1437 */ 1438 BGE_DEBUG(("bge_flash_access: timed out after %d us", tries)); 1439 return (ENODATA); 1440 } 1441 1442 /* 1443 * The next two functions regulate access to the NVram (if fitted). 1444 * 1445 * On a 5704 (dual core) chip, there's only one SEEPROM and one Flash 1446 * (SPI) interface, but they can be accessed through either port. These 1447 * are managed by different instance of this driver and have no software 1448 * state in common. 1449 * 1450 * In addition (and even on a single core chip) the chip's internal 1451 * firmware can access the SEEPROM/Flash, most notably after a RESET 1452 * when it may download code to run internally. 1453 * 1454 * So we need to arbitrate between these various software agents. For 1455 * this purpose, the chip provides the Software Arbitration Register, 1456 * which implements hardware(!) arbitration. 1457 * 1458 * This functionality didn't exist on older (5700/5701) chips, so there's 1459 * nothing we can do by way of arbitration on those; also, if there's no 1460 * SEEPROM/Flash fitted (or we couldn't determine what type), there's also 1461 * nothing to do. 1462 * 1463 * The internal firmware appears to use Request 0, which is the highest 1464 * priority. So we'd like to use Request 2, leaving one higher and one 1465 * lower for any future developments ... but apparently this doesn't 1466 * always work. So for now, the code uses Request 1 ;-( 1467 */ 1468 1469 #define NVM_READ_REQ NVM_READ_REQ1 1470 #define NVM_RESET_REQ NVM_RESET_REQ1 1471 #define NVM_SET_REQ NVM_SET_REQ1 1472 1473 static void bge_nvmem_relinquish(bge_t *bgep); 1474 #pragma no_inline(bge_nvmem_relinquish) 1475 1476 static void 1477 bge_nvmem_relinquish(bge_t *bgep) 1478 { 1479 ASSERT(mutex_owned(bgep->genlock)); 1480 1481 switch (bgep->chipid.nvtype) { 1482 case BGE_NVTYPE_NONE: 1483 case BGE_NVTYPE_UNKNOWN: 1484 _NOTE(NOTREACHED) 1485 return; 1486 1487 case BGE_NVTYPE_SEEPROM: 1488 /* 1489 * No arbitration performed, no release needed 1490 */ 1491 return; 1492 1493 case BGE_NVTYPE_LEGACY_SEEPROM: 1494 case BGE_NVTYPE_UNBUFFERED_FLASH: 1495 case BGE_NVTYPE_BUFFERED_FLASH: 1496 default: 1497 break; 1498 } 1499 1500 /* 1501 * Our own request should be present (whether or not granted) ... 1502 */ 1503 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1504 1505 /* 1506 * ... this will make it go away. 1507 */ 1508 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_RESET_REQ); 1509 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1510 } 1511 1512 /* 1513 * Arbitrate for access to the NVmem, if necessary 1514 * 1515 * Return value: 1516 * 0 on success 1517 * EAGAIN if the device is in use (retryable) 1518 * ENODEV if the NVmem device is missing or otherwise unusable 1519 */ 1520 static int bge_nvmem_acquire(bge_t *bgep); 1521 #pragma no_inline(bge_nvmem_acquire) 1522 1523 static int 1524 bge_nvmem_acquire(bge_t *bgep) 1525 { 1526 uint32_t regval; 1527 uint32_t tries; 1528 1529 ASSERT(mutex_owned(bgep->genlock)); 1530 1531 switch (bgep->chipid.nvtype) { 1532 case BGE_NVTYPE_NONE: 1533 case BGE_NVTYPE_UNKNOWN: 1534 /* 1535 * Access denied: no (recognisable) device fitted 1536 */ 1537 return (ENODEV); 1538 1539 case BGE_NVTYPE_SEEPROM: 1540 /* 1541 * Access granted: no arbitration needed (or possible) 1542 */ 1543 return (0); 1544 1545 case BGE_NVTYPE_LEGACY_SEEPROM: 1546 case BGE_NVTYPE_UNBUFFERED_FLASH: 1547 case BGE_NVTYPE_BUFFERED_FLASH: 1548 default: 1549 /* 1550 * Access conditional: conduct arbitration protocol 1551 */ 1552 break; 1553 } 1554 1555 /* 1556 * We're holding the per-port mutex <genlock>, so no-one other 1557 * thread can be attempting to access the NVmem through *this* 1558 * port. But it could be in use by the *other* port (of a 5704), 1559 * or by the chip's internal firmware, so we have to go through 1560 * the full (hardware) arbitration protocol ... 1561 * 1562 * Note that *because* we're holding <genlock>, the interrupt handler 1563 * won't be able to progress. So we're only willing to spin for a 1564 * fairly short time. Specifically: 1565 * 1566 * We *must* wait long enough for the hardware to resolve all 1567 * requests and determine the winner. Fortunately, this is 1568 * "almost instantaneous", even as observed by GHz CPUs. 1569 * 1570 * A successful access by another Solaris thread (via either 1571 * port) typically takes ~20us. So waiting a bit longer than 1572 * that will give a good chance of success, if the other user 1573 * *is* another thread on the other port. 1574 * 1575 * However, the internal firmware can hold on to the NVmem 1576 * for *much* longer: at least 10 milliseconds just after a 1577 * RESET, and maybe even longer if the NVmem actually contains 1578 * code to download and run on the internal CPUs. 1579 * 1580 * So, we'll allow 50us; if that's not enough then it's up to the 1581 * caller to retry later (hence the choice of return code EAGAIN). 1582 */ 1583 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1584 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_SET_REQ); 1585 1586 for (tries = 0; tries < 50; ++tries) { 1587 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1588 if (regval & NVM_WON_REQ1) 1589 break; 1590 drv_usecwait(1); 1591 } 1592 1593 if (regval & NVM_WON_REQ1) { 1594 BGE_DEBUG(("bge_nvmem_acquire: won after %d us", tries)); 1595 return (0); 1596 } 1597 1598 /* 1599 * Somebody else must be accessing the NVmem, so abandon our 1600 * attempt take control of it. The caller can try again later ... 1601 */ 1602 BGE_DEBUG(("bge_nvmem_acquire: lost after %d us", tries)); 1603 bge_nvmem_relinquish(bgep); 1604 return (EAGAIN); 1605 } 1606 1607 /* 1608 * This code assumes that the GPIO1 bit has been wired up to the NVmem 1609 * write protect line in such a way that the NVmem is protected when 1610 * GPIO1 is an input, or is an output but driven high. Thus, to make the 1611 * NVmem writable we have to change GPIO1 to an output AND drive it low. 1612 * 1613 * Note: there's only one set of GPIO pins on a 5704, even though they 1614 * can be accessed through either port. So the chip has to resolve what 1615 * happens if the two ports program a single pin differently ... the rule 1616 * it uses is that if the ports disagree about the *direction* of a pin, 1617 * "output" wins over "input", but if they disagree about its *value* as 1618 * an output, then the pin is TRISTATED instead! In such a case, no-one 1619 * wins, and the external signal does whatever the external circuitry 1620 * defines as the default -- which we've assumed is the PROTECTED state. 1621 * So, we always change GPIO1 back to being an *input* whenever we're not 1622 * specifically using it to unprotect the NVmem. This allows either port 1623 * to update the NVmem, although obviously only one at a time! 1624 * 1625 * The caller should hold <genlock> and *also* have already acquired the 1626 * right to access the NVmem, via bge_nvmem_acquire() above. 1627 */ 1628 static void bge_nvmem_protect(bge_t *bgep, boolean_t protect); 1629 #pragma inline(bge_nvmem_protect) 1630 1631 static void 1632 bge_nvmem_protect(bge_t *bgep, boolean_t protect) 1633 { 1634 uint32_t regval; 1635 1636 ASSERT(mutex_owned(bgep->genlock)); 1637 1638 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 1639 if (protect) { 1640 regval |= MLCR_MISC_PINS_OUTPUT_1; 1641 regval &= ~MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1642 } else { 1643 regval &= ~MLCR_MISC_PINS_OUTPUT_1; 1644 regval |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1645 } 1646 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, regval); 1647 } 1648 1649 /* 1650 * Now put it all together ... 1651 * 1652 * Try to acquire control of the NVmem; if successful, then: 1653 * unprotect it (if we want to write to it) 1654 * perform the requested access 1655 * reprotect it (after a write) 1656 * relinquish control 1657 * 1658 * Return value: 1659 * 0 on success, 1660 * EAGAIN if the device is in use (retryable) 1661 * ENODATA on access timeout (maybe retryable: device may just be busy) 1662 * ENODEV if the NVmem device is missing or otherwise unusable 1663 * EPROTO on other h/w or s/w errors. 1664 */ 1665 static int 1666 bge_nvmem_rw32(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1667 { 1668 int err; 1669 1670 if ((err = bge_nvmem_acquire(bgep)) == 0) { 1671 switch (cmd) { 1672 case BGE_SEE_READ: 1673 err = bge_seeprom_access(bgep, 1674 SEEPROM_ACCESS_READ, addr, dp); 1675 break; 1676 1677 case BGE_SEE_WRITE: 1678 bge_nvmem_protect(bgep, B_FALSE); 1679 err = bge_seeprom_access(bgep, 1680 SEEPROM_ACCESS_WRITE, addr, dp); 1681 bge_nvmem_protect(bgep, B_TRUE); 1682 break; 1683 1684 case BGE_FLASH_READ: 1685 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1686 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1687 bge_reg_set32(bgep, NVM_ACCESS_REG, 1688 NVM_ACCESS_ENABLE); 1689 } 1690 err = bge_flash_access(bgep, 1691 NVM_FLASH_CMD_RD, addr, dp); 1692 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1693 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1694 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1695 NVM_ACCESS_ENABLE); 1696 } 1697 break; 1698 1699 case BGE_FLASH_WRITE: 1700 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1701 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1702 bge_reg_set32(bgep, NVM_ACCESS_REG, 1703 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1704 } 1705 bge_nvmem_protect(bgep, B_FALSE); 1706 err = bge_flash_access(bgep, 1707 NVM_FLASH_CMD_WR, addr, dp); 1708 bge_nvmem_protect(bgep, B_TRUE); 1709 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1710 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1711 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1712 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1713 } 1714 1715 break; 1716 1717 default: 1718 _NOTE(NOTREACHED) 1719 break; 1720 } 1721 bge_nvmem_relinquish(bgep); 1722 } 1723 1724 BGE_DEBUG(("bge_nvmem_rw32: err %d", err)); 1725 return (err); 1726 } 1727 1728 /* 1729 * Attempt to get a MAC address from the SEEPROM or Flash, if any 1730 */ 1731 static uint64_t bge_get_nvmac(bge_t *bgep); 1732 #pragma no_inline(bge_get_nvmac) 1733 1734 static uint64_t 1735 bge_get_nvmac(bge_t *bgep) 1736 { 1737 uint32_t mac_high; 1738 uint32_t mac_low; 1739 uint32_t addr; 1740 uint32_t cmd; 1741 uint64_t mac; 1742 1743 BGE_TRACE(("bge_get_nvmac($%p)", 1744 (void *)bgep)); 1745 1746 switch (bgep->chipid.nvtype) { 1747 case BGE_NVTYPE_NONE: 1748 case BGE_NVTYPE_UNKNOWN: 1749 default: 1750 return (0ULL); 1751 1752 case BGE_NVTYPE_SEEPROM: 1753 case BGE_NVTYPE_LEGACY_SEEPROM: 1754 cmd = BGE_SEE_READ; 1755 break; 1756 1757 case BGE_NVTYPE_UNBUFFERED_FLASH: 1758 case BGE_NVTYPE_BUFFERED_FLASH: 1759 cmd = BGE_FLASH_READ; 1760 break; 1761 } 1762 1763 addr = NVMEM_DATA_MAC_ADDRESS; 1764 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_high)) 1765 return (0ULL); 1766 addr += 4; 1767 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_low)) 1768 return (0ULL); 1769 1770 /* 1771 * The Broadcom chip is natively BIG-endian, so that's how the 1772 * MAC address is represented in NVmem. We may need to swap it 1773 * around on a little-endian host ... 1774 */ 1775 #ifdef _BIG_ENDIAN 1776 mac = mac_high; 1777 mac = mac << 32; 1778 mac |= mac_low; 1779 #else 1780 mac = BGE_BSWAP_32(mac_high); 1781 mac = mac << 32; 1782 mac |= BGE_BSWAP_32(mac_low); 1783 #endif /* _BIG_ENDIAN */ 1784 1785 return (mac); 1786 } 1787 1788 #else /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1789 1790 /* 1791 * Dummy version for when we're not supporting NVmem access 1792 */ 1793 static uint64_t bge_get_nvmac(bge_t *bgep); 1794 #pragma inline(bge_get_nvmac) 1795 1796 static uint64_t 1797 bge_get_nvmac(bge_t *bgep) 1798 { 1799 _NOTE(ARGUNUSED(bgep)) 1800 return (0ULL); 1801 } 1802 1803 #endif /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1804 1805 /* 1806 * Determine the type of NVmem that is (or may be) attached to this chip, 1807 */ 1808 static enum bge_nvmem_type bge_nvmem_id(bge_t *bgep); 1809 #pragma no_inline(bge_nvmem_id) 1810 1811 static enum bge_nvmem_type 1812 bge_nvmem_id(bge_t *bgep) 1813 { 1814 enum bge_nvmem_type nvtype; 1815 uint32_t config1; 1816 1817 BGE_TRACE(("bge_nvmem_id($%p)", 1818 (void *)bgep)); 1819 1820 switch (bgep->chipid.device) { 1821 default: 1822 /* 1823 * We shouldn't get here; it means we don't recognise 1824 * the chip, which means we don't know how to determine 1825 * what sort of NVmem (if any) it has. So we'll say 1826 * NONE, to disable the NVmem access code ... 1827 */ 1828 nvtype = BGE_NVTYPE_NONE; 1829 break; 1830 1831 case DEVICE_ID_5700: 1832 case DEVICE_ID_5700x: 1833 case DEVICE_ID_5701: 1834 /* 1835 * These devices support *only* SEEPROMs 1836 */ 1837 nvtype = BGE_NVTYPE_SEEPROM; 1838 break; 1839 1840 case DEVICE_ID_5702: 1841 case DEVICE_ID_5702fe: 1842 case DEVICE_ID_5703C: 1843 case DEVICE_ID_5703S: 1844 case DEVICE_ID_5704C: 1845 case DEVICE_ID_5704S: 1846 case DEVICE_ID_5704: 1847 case DEVICE_ID_5705M: 1848 case DEVICE_ID_5705C: 1849 case DEVICE_ID_5705_2: 1850 case DEVICE_ID_5706: 1851 case DEVICE_ID_5782: 1852 case DEVICE_ID_5788: 1853 case DEVICE_ID_5789: 1854 case DEVICE_ID_5751: 1855 case DEVICE_ID_5751M: 1856 case DEVICE_ID_5752: 1857 case DEVICE_ID_5752M: 1858 case DEVICE_ID_5754: 1859 case DEVICE_ID_5755: 1860 case DEVICE_ID_5721: 1861 case DEVICE_ID_5714C: 1862 case DEVICE_ID_5714S: 1863 case DEVICE_ID_5715C: 1864 case DEVICE_ID_5715S: 1865 config1 = bge_reg_get32(bgep, NVM_CONFIG1_REG); 1866 if (config1 & NVM_CFG1_FLASH_MODE) 1867 if (config1 & NVM_CFG1_BUFFERED_MODE) 1868 nvtype = BGE_NVTYPE_BUFFERED_FLASH; 1869 else 1870 nvtype = BGE_NVTYPE_UNBUFFERED_FLASH; 1871 else 1872 nvtype = BGE_NVTYPE_LEGACY_SEEPROM; 1873 break; 1874 } 1875 1876 return (nvtype); 1877 } 1878 1879 #undef BGE_DBG 1880 #define BGE_DBG BGE_DBG_CHIP /* debug flag for this code */ 1881 1882 static void 1883 bge_init_recv_rule(bge_t *bgep) 1884 { 1885 bge_recv_rule_t *rulep; 1886 uint32_t i; 1887 1888 /* 1889 * receive rule: direct all TCP traffic to ring RULE_MATCH_TO_RING 1890 * 1. to direct UDP traffic, set: 1891 * rulep->control = RULE_PROTO_CONTROL; 1892 * rulep->mask_value = RULE_UDP_MASK_VALUE; 1893 * 2. to direct ICMP traffic, set: 1894 * rulep->control = RULE_PROTO_CONTROL; 1895 * rulep->mask_value = RULE_ICMP_MASK_VALUE; 1896 * 3. to direct traffic by source ip, set: 1897 * rulep->control = RULE_SIP_CONTROL; 1898 * rulep->mask_value = RULE_SIP_MASK_VALUE; 1899 */ 1900 rulep = bgep->recv_rules; 1901 rulep->control = RULE_PROTO_CONTROL; 1902 rulep->mask_value = RULE_TCP_MASK_VALUE; 1903 1904 /* 1905 * set receive rule registers 1906 */ 1907 rulep = bgep->recv_rules; 1908 for (i = 0; i < RECV_RULES_NUM_MAX; i++, rulep++) { 1909 bge_reg_put32(bgep, RECV_RULE_MASK_REG(i), rulep->mask_value); 1910 bge_reg_put32(bgep, RECV_RULE_CONTROL_REG(i), rulep->control); 1911 } 1912 } 1913 1914 /* 1915 * Using the values captured by bge_chip_cfg_init(), and additional probes 1916 * as required, characterise the chip fully: determine the label by which 1917 * to refer to this chip, the correct settings for various registers, and 1918 * of course whether the device and/or subsystem are supported! 1919 */ 1920 int bge_chip_id_init(bge_t *bgep); 1921 #pragma no_inline(bge_chip_id_init) 1922 1923 int 1924 bge_chip_id_init(bge_t *bgep) 1925 { 1926 char buf[MAXPATHLEN]; /* any risk of stack overflow? */ 1927 boolean_t sys_ok; 1928 boolean_t dev_ok; 1929 chip_id_t *cidp; 1930 uint32_t subid; 1931 char *devname; 1932 char *sysname; 1933 int *ids; 1934 int err; 1935 uint_t i; 1936 1937 ASSERT(bgep->bge_chip_state == BGE_CHIP_INITIAL); 1938 1939 sys_ok = dev_ok = B_FALSE; 1940 cidp = &bgep->chipid; 1941 1942 /* 1943 * Check the PCI device ID to determine the generic chip type and 1944 * select parameters that depend on this. 1945 * 1946 * Note: because the SPARC platforms in general don't fit the 1947 * SEEPROM 'behind' the chip, the PCI revision ID register reads 1948 * as zero - which is why we use <asic_rev> rather than <revision> 1949 * below ... 1950 * 1951 * Note: in general we can't distinguish between the Copper/SerDes 1952 * versions by ID alone, as some Copper devices (e.g. some but not 1953 * all 5703Cs) have the same ID as the SerDes equivalents. So we 1954 * treat them the same here, and the MII code works out the media 1955 * type later on ... 1956 */ 1957 cidp->mbuf_base = bge_mbuf_pool_base; 1958 cidp->mbuf_length = bge_mbuf_pool_len; 1959 cidp->recv_slots = BGE_RECV_SLOTS_USED; 1960 cidp->bge_dma_rwctrl = bge_dma_rwctrl; 1961 cidp->pci_type = BGE_PCI_X; 1962 cidp->statistic_type = BGE_STAT_BLK; 1963 cidp->mbuf_lo_water_rdma = bge_mbuf_lo_water_rdma; 1964 cidp->mbuf_lo_water_rmac = bge_mbuf_lo_water_rmac; 1965 cidp->mbuf_hi_water = bge_mbuf_hi_water; 1966 1967 if (cidp->rx_rings == 0 || cidp->rx_rings > BGE_RECV_RINGS_MAX) 1968 cidp->rx_rings = BGE_RECV_RINGS_DEFAULT; 1969 if (cidp->tx_rings == 0 || cidp->tx_rings > BGE_SEND_RINGS_MAX) 1970 cidp->tx_rings = BGE_SEND_RINGS_DEFAULT; 1971 1972 cidp->msi_enabled = B_FALSE; 1973 1974 switch (cidp->device) { 1975 case DEVICE_ID_5700: 1976 case DEVICE_ID_5700x: 1977 cidp->chip_label = 5700; 1978 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1979 break; 1980 1981 case DEVICE_ID_5701: 1982 cidp->chip_label = 5701; 1983 dev_ok = B_TRUE; 1984 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1985 break; 1986 1987 case DEVICE_ID_5702: 1988 case DEVICE_ID_5702fe: 1989 cidp->chip_label = 5702; 1990 dev_ok = B_TRUE; 1991 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1992 cidp->pci_type = BGE_PCI; 1993 break; 1994 1995 case DEVICE_ID_5703C: 1996 case DEVICE_ID_5703S: 1997 case DEVICE_ID_5703: 1998 /* 1999 * Revision A0 of the 5703/5793 had various errata 2000 * that we can't or don't work around, so it's not 2001 * supported, but all later versions are 2002 */ 2003 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5793 : 5703; 2004 if (bgep->chipid.asic_rev != MHCR_CHIP_REV_5703_A0) 2005 dev_ok = B_TRUE; 2006 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2007 break; 2008 2009 case DEVICE_ID_5704C: 2010 case DEVICE_ID_5704S: 2011 case DEVICE_ID_5704: 2012 /* 2013 * Revision A0 of the 5704/5794 had various errata 2014 * but we have workarounds, so it *is* supported. 2015 */ 2016 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5794 : 5704; 2017 cidp->mbuf_base = bge_mbuf_pool_base_5704; 2018 cidp->mbuf_length = bge_mbuf_pool_len_5704; 2019 dev_ok = B_TRUE; 2020 if (cidp->asic_rev < MHCR_CHIP_REV_5704_B0) 2021 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2022 break; 2023 2024 case DEVICE_ID_5705C: 2025 case DEVICE_ID_5705M: 2026 case DEVICE_ID_5705MA3: 2027 case DEVICE_ID_5705F: 2028 case DEVICE_ID_5705_2: 2029 case DEVICE_ID_5754: 2030 if (cidp->device == DEVICE_ID_5754) { 2031 cidp->chip_label = 5754; 2032 cidp->pci_type = BGE_PCI_E; 2033 } else { 2034 cidp->chip_label = 5705; 2035 cidp->pci_type = BGE_PCI; 2036 } 2037 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2038 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2039 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2040 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2041 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2042 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2043 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2044 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2045 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2046 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2047 cidp->statistic_type = BGE_STAT_REG; 2048 dev_ok = B_TRUE; 2049 break; 2050 2051 case DEVICE_ID_5755: 2052 cidp->chip_label = 5755; 2053 cidp->pci_type = BGE_PCI_E; 2054 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2055 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2056 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2057 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2058 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2059 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2060 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2061 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2062 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2063 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2064 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2065 cidp->statistic_type = BGE_STAT_REG; 2066 dev_ok = B_TRUE; 2067 break; 2068 2069 case DEVICE_ID_5706: 2070 cidp->chip_label = 5706; 2071 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2072 break; 2073 2074 case DEVICE_ID_5782: 2075 /* 2076 * Apart from the label, we treat this as a 5705(?) 2077 */ 2078 cidp->chip_label = 5782; 2079 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2080 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2081 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2082 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2083 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2084 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2085 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2086 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2087 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2088 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2089 cidp->statistic_type = BGE_STAT_REG; 2090 dev_ok = B_TRUE; 2091 break; 2092 2093 case DEVICE_ID_5788: 2094 /* 2095 * Apart from the label, we treat this as a 5705(?) 2096 */ 2097 cidp->chip_label = 5788; 2098 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2099 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2100 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2101 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2102 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2103 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2104 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2105 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2106 cidp->statistic_type = BGE_STAT_REG; 2107 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2108 dev_ok = B_TRUE; 2109 break; 2110 2111 case DEVICE_ID_5714C: 2112 if (cidp->revision >= REVISION_ID_5714_A2) 2113 cidp->msi_enabled = bge_enable_msi; 2114 /* FALLTHRU */ 2115 case DEVICE_ID_5714S: 2116 cidp->chip_label = 5714; 2117 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2118 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2119 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2120 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2121 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2122 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2123 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5714; 2124 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2125 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2126 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2127 cidp->pci_type = BGE_PCI_E; 2128 cidp->statistic_type = BGE_STAT_REG; 2129 dev_ok = B_TRUE; 2130 break; 2131 2132 case DEVICE_ID_5715C: 2133 case DEVICE_ID_5715S: 2134 cidp->chip_label = 5715; 2135 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2136 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2137 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2138 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2139 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2140 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2141 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5715; 2142 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2143 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2144 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2145 cidp->pci_type = BGE_PCI_E; 2146 cidp->statistic_type = BGE_STAT_REG; 2147 if (cidp->revision >= REVISION_ID_5715_A2) 2148 cidp->msi_enabled = bge_enable_msi; 2149 dev_ok = B_TRUE; 2150 break; 2151 2152 case DEVICE_ID_5721: 2153 cidp->chip_label = 5721; 2154 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2155 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2156 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2157 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2158 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2159 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2160 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2161 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2162 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2163 cidp->pci_type = BGE_PCI_E; 2164 cidp->statistic_type = BGE_STAT_REG; 2165 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2166 dev_ok = B_TRUE; 2167 break; 2168 2169 case DEVICE_ID_5751: 2170 case DEVICE_ID_5751M: 2171 cidp->chip_label = 5751; 2172 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2173 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2174 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2175 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2176 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2177 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2178 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2179 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2180 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2181 cidp->pci_type = BGE_PCI_E; 2182 cidp->statistic_type = BGE_STAT_REG; 2183 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2184 dev_ok = B_TRUE; 2185 break; 2186 2187 case DEVICE_ID_5752: 2188 case DEVICE_ID_5752M: 2189 cidp->chip_label = 5752; 2190 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2191 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2192 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2193 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2194 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2195 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2196 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2197 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2198 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2199 cidp->pci_type = BGE_PCI_E; 2200 cidp->statistic_type = BGE_STAT_REG; 2201 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2202 dev_ok = B_TRUE; 2203 break; 2204 2205 case DEVICE_ID_5789: 2206 cidp->chip_label = 5789; 2207 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2208 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2209 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2210 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2211 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2212 cidp->tx_rings = BGE_RECV_RINGS_MAX_5705; 2213 cidp->pci_type = BGE_PCI_E; 2214 cidp->statistic_type = BGE_STAT_REG; 2215 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2216 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2217 cidp->msi_enabled = B_TRUE; 2218 dev_ok = B_TRUE; 2219 break; 2220 2221 } 2222 2223 /* 2224 * Setup the default jumbo parameter. 2225 */ 2226 cidp->ethmax_size = ETHERMAX; 2227 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_DEFAULT; 2228 cidp->std_buf_size = BGE_STD_BUFF_SIZE; 2229 2230 /* 2231 * If jumbo is enabled and this kind of chipset supports jumbo feature, 2232 * setup below jumbo specific parameters. 2233 * 2234 * For BCM5714/5715, there is only one standard receive ring. So the 2235 * std buffer size should be set to BGE_JUMBO_BUFF_SIZE when jumbo 2236 * feature is enabled. 2237 */ 2238 if (bge_jumbo_enable && 2239 !(cidp->flags & CHIP_FLAG_NO_JUMBO) && 2240 (cidp->default_mtu > BGE_DEFAULT_MTU) && 2241 (cidp->default_mtu <= BGE_MAXIMUM_MTU)) { 2242 if (DEVICE_5714_SERIES_CHIPSETS(bgep)) { 2243 cidp->mbuf_lo_water_rdma = 2244 RDMA_MBUF_LOWAT_5714_JUMBO; 2245 cidp->mbuf_lo_water_rmac = 2246 MAC_RX_MBUF_LOWAT_5714_JUMBO; 2247 cidp->mbuf_hi_water = MBUF_HIWAT_5714_JUMBO; 2248 cidp->jumbo_slots = 0; 2249 cidp->std_buf_size = BGE_JUMBO_BUFF_SIZE; 2250 } else { 2251 cidp->mbuf_lo_water_rdma = 2252 RDMA_MBUF_LOWAT_JUMBO; 2253 cidp->mbuf_lo_water_rmac = 2254 MAC_RX_MBUF_LOWAT_JUMBO; 2255 cidp->mbuf_hi_water = MBUF_HIWAT_JUMBO; 2256 cidp->jumbo_slots = BGE_JUMBO_SLOTS_USED; 2257 } 2258 cidp->recv_jumbo_size = BGE_JUMBO_BUFF_SIZE; 2259 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_JUMBO; 2260 cidp->ethmax_size = cidp->default_mtu + 2261 sizeof (struct ether_header); 2262 } 2263 2264 /* 2265 * Identify the NV memory type: SEEPROM or Flash? 2266 */ 2267 cidp->nvtype = bge_nvmem_id(bgep); 2268 2269 /* 2270 * Now, we want to check whether this device is part of a 2271 * supported subsystem (e.g., on the motherboard of a Sun 2272 * branded platform). 2273 * 2274 * Rule 1: If the Subsystem Vendor ID is "Sun", then it's OK ;-) 2275 */ 2276 if (cidp->subven == VENDOR_ID_SUN) 2277 sys_ok = B_TRUE; 2278 2279 /* 2280 * Rule 2: If it's on the list on known subsystems, then it's OK. 2281 * Note: 0x14e41647 should *not* appear in the list, but the code 2282 * doesn't enforce that. 2283 */ 2284 err = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, bgep->devinfo, 2285 DDI_PROP_DONTPASS, knownids_propname, &ids, &i); 2286 if (err == DDI_PROP_SUCCESS) { 2287 /* 2288 * Got the list; scan for a matching subsystem vendor/device 2289 */ 2290 subid = (cidp->subven << 16) | cidp->subdev; 2291 while (i--) 2292 if (ids[i] == subid) 2293 sys_ok = B_TRUE; 2294 ddi_prop_free(ids); 2295 } 2296 2297 /* 2298 * Rule 3: If it's a Taco/ENWS motherboard device, then it's OK 2299 * 2300 * Unfortunately, early SunBlade 1500s and 2500s didn't reprogram 2301 * the Subsystem Vendor ID, so it defaults to Broadcom. Therefore, 2302 * we have to check specially for the exact device paths to the 2303 * motherboard devices on those platforms ;-( 2304 * 2305 * Note: we can't just use the "supported-subsystems" mechanism 2306 * above, because the entry would have to be 0x14e41647 -- which 2307 * would then accept *any* plugin card that *didn't* contain a 2308 * (valid) SEEPROM ;-( 2309 */ 2310 sysname = ddi_node_name(ddi_root_node()); 2311 devname = ddi_pathname(bgep->devinfo, buf); 2312 ASSERT(strlen(devname) > 0); 2313 if (strcmp(sysname, "SUNW,Sun-Blade-1500") == 0) /* Taco */ 2314 if (strcmp(devname, "/pci@1f,700000/network@2") == 0) 2315 sys_ok = B_TRUE; 2316 if (strcmp(sysname, "SUNW,Sun-Blade-2500") == 0) /* ENWS */ 2317 if (strcmp(devname, "/pci@1c,600000/network@3") == 0) 2318 sys_ok = B_TRUE; 2319 2320 /* 2321 * Now check what we've discovered: is this truly a supported 2322 * chip on (the motherboard of) a supported platform? 2323 * 2324 * Possible problems here: 2325 * 1) it's a completely unheard-of chip (e.g. 5761) 2326 * 2) it's a recognised but unsupported chip (e.g. 5701, 5703C-A0) 2327 * 3) it's a chip we would support if it were on the motherboard 2328 * of a Sun platform, but this one isn't ;-( 2329 */ 2330 if (cidp->chip_label == 0) 2331 bge_problem(bgep, 2332 "Device 'pci%04x,%04x' not recognized (%d?)", 2333 cidp->vendor, cidp->device, cidp->device); 2334 else if (!dev_ok) 2335 bge_problem(bgep, 2336 "Device 'pci%04x,%04x' (%d) revision %d not supported", 2337 cidp->vendor, cidp->device, cidp->chip_label, 2338 cidp->revision); 2339 #if BGE_DEBUGGING 2340 else if (!sys_ok) 2341 bge_problem(bgep, 2342 "%d-based subsystem 'pci%04x,%04x' not validated", 2343 cidp->chip_label, cidp->subven, cidp->subdev); 2344 #endif 2345 else 2346 cidp->flags |= CHIP_FLAG_SUPPORTED; 2347 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 2348 return (EIO); 2349 return (0); 2350 } 2351 2352 void 2353 bge_chip_msi_trig(bge_t *bgep) 2354 { 2355 uint32_t regval; 2356 2357 regval = bgep->param_msi_cnt<<4; 2358 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, regval); 2359 BGE_DEBUG(("bge_chip_msi_trig:data = %d", regval)); 2360 } 2361 2362 /* 2363 * Various registers that control the chip's internal engines (state 2364 * machines) have a <reset> and <enable> bits (fortunately, in the 2365 * same place in each such register :-). 2366 * 2367 * To reset the state machine, the <reset> bit must be written with 1; 2368 * it will then read back as 1 while the reset is in progress, but 2369 * self-clear to 0 when the reset completes. 2370 * 2371 * To enable a state machine, one must set the <enable> bit, which 2372 * will continue to read back as 0 until the state machine is running. 2373 * 2374 * To disable a state machine, the <enable> bit must be cleared, but 2375 * it will continue to read back as 1 until the state machine actually 2376 * stops. 2377 * 2378 * This routine implements polling for completion of a reset, enable 2379 * or disable operation, returning B_TRUE on success (bit reached the 2380 * required state) or B_FALSE on timeout (200*100us == 20ms). 2381 */ 2382 static boolean_t bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 2383 uint32_t mask, uint32_t val); 2384 #pragma no_inline(bge_chip_poll_engine) 2385 2386 static boolean_t 2387 bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 2388 uint32_t mask, uint32_t val) 2389 { 2390 uint32_t regval; 2391 uint32_t n; 2392 2393 BGE_TRACE(("bge_chip_poll_engine($%p, 0x%lx, 0x%x, 0x%x)", 2394 (void *)bgep, regno, mask, val)); 2395 2396 for (n = 200; n; --n) { 2397 regval = bge_reg_get32(bgep, regno); 2398 if ((regval & mask) == val) 2399 return (B_TRUE); 2400 drv_usecwait(100); 2401 } 2402 2403 bge_fm_ereport(bgep, DDI_FM_DEVICE_NO_RESPONSE); 2404 return (B_FALSE); 2405 } 2406 2407 /* 2408 * Various registers that control the chip's internal engines (state 2409 * machines) have a <reset> bit (fortunately, in the same place in 2410 * each such register :-). To reset the state machine, this bit must 2411 * be written with 1; it will then read back as 1 while the reset is 2412 * in progress, but self-clear to 0 when the reset completes. 2413 * 2414 * This code sets the bit, then polls for it to read back as zero. 2415 * The return value is B_TRUE on success (reset bit cleared itself), 2416 * or B_FALSE if the state machine didn't recover :( 2417 * 2418 * NOTE: the Core reset is similar to other resets, except that we 2419 * can't poll for completion, since the Core reset disables memory 2420 * access! So we just have to assume that it will all complete in 2421 * 100us. See Broadcom document 570X-PG102-R, p102, steps 4-5. 2422 */ 2423 static boolean_t bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno); 2424 #pragma no_inline(bge_chip_reset_engine) 2425 2426 static boolean_t 2427 bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno) 2428 { 2429 uint32_t regval; 2430 uint32_t val32; 2431 2432 regval = bge_reg_get32(bgep, regno); 2433 2434 BGE_TRACE(("bge_chip_reset_engine($%p, 0x%lx)", 2435 (void *)bgep, regno)); 2436 BGE_DEBUG(("bge_chip_reset_engine: 0x%lx before reset = 0x%08x", 2437 regno, regval)); 2438 2439 regval |= STATE_MACHINE_RESET_BIT; 2440 2441 switch (regno) { 2442 case MISC_CONFIG_REG: 2443 /* 2444 * BCM5714/5721/5751 pcie chip special case. In order to avoid 2445 * resetting PCIE block and bringing PCIE link down, bit 29 2446 * in the register needs to be set first, and then set it again 2447 * while the reset bit is written. 2448 * See:P500 of 57xx-PG102-RDS.pdf. 2449 */ 2450 if (DEVICE_5705_SERIES_CHIPSETS(bgep)|| 2451 DEVICE_5721_SERIES_CHIPSETS(bgep)|| 2452 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 2453 regval |= MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE; 2454 if (bgep->chipid.pci_type == BGE_PCI_E) { 2455 if (bgep->chipid.asic_rev == 2456 MHCR_CHIP_REV_5751_A0 || 2457 bgep->chipid.asic_rev == 2458 MHCR_CHIP_REV_5721_A0 || 2459 bgep->chipid.asic_rev == 2460 MHCR_CHIP_REV_5755_A0) { 2461 val32 = bge_reg_get32(bgep, 2462 PHY_TEST_CTRL_REG); 2463 if (val32 == (PHY_PCIE_SCRAM_MODE | 2464 PHY_PCIE_LTASS_MODE)) 2465 bge_reg_put32(bgep, 2466 PHY_TEST_CTRL_REG, 2467 PHY_PCIE_SCRAM_MODE); 2468 val32 = pci_config_get32 2469 (bgep->cfg_handle, 2470 PCI_CONF_BGE_CLKCTL); 2471 val32 |= CLKCTL_PCIE_A0_FIX; 2472 pci_config_put32(bgep->cfg_handle, 2473 PCI_CONF_BGE_CLKCTL, val32); 2474 } 2475 bge_reg_set32(bgep, regno, 2476 MISC_CONFIG_GRC_RESET_DISABLE); 2477 regval |= MISC_CONFIG_GRC_RESET_DISABLE; 2478 } 2479 } 2480 2481 /* 2482 * Special case - causes Core reset 2483 * 2484 * On SPARC v9 we want to ensure that we don't start 2485 * timing until the I/O access has actually reached 2486 * the chip, otherwise we might make the next access 2487 * too early. And we can't just force the write out 2488 * by following it with a read (even to config space) 2489 * because that would cause the fault we're trying 2490 * to avoid. Hence the need for membar_sync() here. 2491 */ 2492 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), regval); 2493 #ifdef __sparcv9 2494 membar_sync(); 2495 #endif /* __sparcv9 */ 2496 /* 2497 * On some platforms,system need about 300us for 2498 * link setup. 2499 */ 2500 drv_usecwait(300); 2501 2502 if (bgep->chipid.pci_type == BGE_PCI_E) { 2503 /* PCI-E device need more reset time */ 2504 drv_usecwait(120000); 2505 2506 /* Set PCIE max payload size and clear error status. */ 2507 if ((bgep->chipid.chip_label == 5721) || 2508 (bgep->chipid.chip_label == 5751) || 2509 (bgep->chipid.chip_label == 5752) || 2510 (bgep->chipid.chip_label == 5789)) { 2511 pci_config_put16(bgep->cfg_handle, 2512 PCI_CONF_DEV_CTRL, READ_REQ_SIZE_MAX); 2513 pci_config_put16(bgep->cfg_handle, 2514 PCI_CONF_DEV_STUS, DEVICE_ERROR_STUS); 2515 } 2516 } 2517 2518 BGE_PCICHK(bgep); 2519 return (B_TRUE); 2520 2521 default: 2522 bge_reg_put32(bgep, regno, regval); 2523 return (bge_chip_poll_engine(bgep, regno, 2524 STATE_MACHINE_RESET_BIT, 0)); 2525 } 2526 } 2527 2528 /* 2529 * Various registers that control the chip's internal engines (state 2530 * machines) have an <enable> bit (fortunately, in the same place in 2531 * each such register :-). To stop the state machine, this bit must 2532 * be written with 0, then polled to see when the state machine has 2533 * actually stopped. 2534 * 2535 * The return value is B_TRUE on success (enable bit cleared), or 2536 * B_FALSE if the state machine didn't stop :( 2537 */ 2538 static boolean_t bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, 2539 uint32_t morebits); 2540 #pragma no_inline(bge_chip_disable_engine) 2541 2542 static boolean_t 2543 bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 2544 { 2545 uint32_t regval; 2546 2547 BGE_TRACE(("bge_chip_disable_engine($%p, 0x%lx, 0x%x)", 2548 (void *)bgep, regno, morebits)); 2549 2550 switch (regno) { 2551 case FTQ_RESET_REG: 2552 /* 2553 * For Schumacher's bugfix CR6490108 2554 */ 2555 #ifdef BGE_IPMI_ASF 2556 #ifdef BGE_NETCONSOLE 2557 if (bgep->asf_enabled) 2558 return (B_TRUE); 2559 #endif 2560 #endif 2561 /* 2562 * Not quite like the others; it doesn't 2563 * have an <enable> bit, but instead we 2564 * have to set and then clear all the bits 2565 */ 2566 bge_reg_put32(bgep, regno, ~(uint32_t)0); 2567 drv_usecwait(100); 2568 bge_reg_put32(bgep, regno, 0); 2569 return (B_TRUE); 2570 2571 default: 2572 regval = bge_reg_get32(bgep, regno); 2573 regval &= ~STATE_MACHINE_ENABLE_BIT; 2574 regval &= ~morebits; 2575 bge_reg_put32(bgep, regno, regval); 2576 return (bge_chip_poll_engine(bgep, regno, 2577 STATE_MACHINE_ENABLE_BIT, 0)); 2578 } 2579 } 2580 2581 /* 2582 * Various registers that control the chip's internal engines (state 2583 * machines) have an <enable> bit (fortunately, in the same place in 2584 * each such register :-). To start the state machine, this bit must 2585 * be written with 1, then polled to see when the state machine has 2586 * actually started. 2587 * 2588 * The return value is B_TRUE on success (enable bit set), or 2589 * B_FALSE if the state machine didn't start :( 2590 */ 2591 static boolean_t bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, 2592 uint32_t morebits); 2593 #pragma no_inline(bge_chip_enable_engine) 2594 2595 static boolean_t 2596 bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 2597 { 2598 uint32_t regval; 2599 2600 BGE_TRACE(("bge_chip_enable_engine($%p, 0x%lx, 0x%x)", 2601 (void *)bgep, regno, morebits)); 2602 2603 switch (regno) { 2604 case FTQ_RESET_REG: 2605 #ifdef BGE_IPMI_ASF 2606 #ifdef BGE_NETCONSOLE 2607 if (bgep->asf_enabled) 2608 return (B_TRUE); 2609 #endif 2610 #endif 2611 /* 2612 * Not quite like the others; it doesn't 2613 * have an <enable> bit, but instead we 2614 * have to set and then clear all the bits 2615 */ 2616 bge_reg_put32(bgep, regno, ~(uint32_t)0); 2617 drv_usecwait(100); 2618 bge_reg_put32(bgep, regno, 0); 2619 return (B_TRUE); 2620 2621 default: 2622 regval = bge_reg_get32(bgep, regno); 2623 regval |= STATE_MACHINE_ENABLE_BIT; 2624 regval |= morebits; 2625 bge_reg_put32(bgep, regno, regval); 2626 return (bge_chip_poll_engine(bgep, regno, 2627 STATE_MACHINE_ENABLE_BIT, STATE_MACHINE_ENABLE_BIT)); 2628 } 2629 } 2630 2631 /* 2632 * Reprogram the Ethernet, Transmit, and Receive MAC 2633 * modes to match the param_* variables 2634 */ 2635 static void bge_sync_mac_modes(bge_t *bgep); 2636 #pragma no_inline(bge_sync_mac_modes) 2637 2638 static void 2639 bge_sync_mac_modes(bge_t *bgep) 2640 { 2641 uint32_t macmode; 2642 uint32_t regval; 2643 2644 ASSERT(mutex_owned(bgep->genlock)); 2645 2646 /* 2647 * Reprogram the Ethernet MAC mode ... 2648 */ 2649 macmode = regval = bge_reg_get32(bgep, ETHERNET_MAC_MODE_REG); 2650 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 2651 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) 2652 macmode &= ~ETHERNET_MODE_LINK_POLARITY; 2653 else 2654 macmode |= ETHERNET_MODE_LINK_POLARITY; 2655 macmode &= ~ETHERNET_MODE_PORTMODE_MASK; 2656 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 2657 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) 2658 macmode |= ETHERNET_MODE_PORTMODE_TBI; 2659 else if (bgep->param_link_speed == 10 || bgep->param_link_speed == 100) 2660 macmode |= ETHERNET_MODE_PORTMODE_MII; 2661 else 2662 macmode |= ETHERNET_MODE_PORTMODE_GMII; 2663 if (bgep->param_link_duplex == LINK_DUPLEX_HALF) 2664 macmode |= ETHERNET_MODE_HALF_DUPLEX; 2665 else 2666 macmode &= ~ETHERNET_MODE_HALF_DUPLEX; 2667 if (bgep->param_loop_mode == BGE_LOOP_INTERNAL_MAC) 2668 macmode |= ETHERNET_MODE_MAC_LOOPBACK; 2669 else 2670 macmode &= ~ETHERNET_MODE_MAC_LOOPBACK; 2671 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, macmode); 2672 BGE_DEBUG(("bge_sync_mac_modes($%p) Ethernet MAC mode 0x%x => 0x%x", 2673 (void *)bgep, regval, macmode)); 2674 2675 /* 2676 * ... the Transmit MAC mode ... 2677 */ 2678 macmode = regval = bge_reg_get32(bgep, TRANSMIT_MAC_MODE_REG); 2679 if (bgep->param_link_tx_pause) 2680 macmode |= TRANSMIT_MODE_FLOW_CONTROL; 2681 else 2682 macmode &= ~TRANSMIT_MODE_FLOW_CONTROL; 2683 bge_reg_put32(bgep, TRANSMIT_MAC_MODE_REG, macmode); 2684 BGE_DEBUG(("bge_sync_mac_modes($%p) Transmit MAC mode 0x%x => 0x%x", 2685 (void *)bgep, regval, macmode)); 2686 2687 /* 2688 * ... and the Receive MAC mode 2689 */ 2690 macmode = regval = bge_reg_get32(bgep, RECEIVE_MAC_MODE_REG); 2691 if (bgep->param_link_rx_pause) 2692 macmode |= RECEIVE_MODE_FLOW_CONTROL; 2693 else 2694 macmode &= ~RECEIVE_MODE_FLOW_CONTROL; 2695 bge_reg_put32(bgep, RECEIVE_MAC_MODE_REG, macmode); 2696 BGE_DEBUG(("bge_sync_mac_modes($%p) Receive MAC mode 0x%x => 0x%x", 2697 (void *)bgep, regval, macmode)); 2698 } 2699 2700 /* 2701 * bge_chip_sync() -- program the chip with the unicast MAC address, 2702 * the multicast hash table, the required level of promiscuity, and 2703 * the current loopback mode ... 2704 */ 2705 #ifdef BGE_IPMI_ASF 2706 int bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive); 2707 #else 2708 int bge_chip_sync(bge_t *bgep); 2709 #endif 2710 #pragma no_inline(bge_chip_sync) 2711 2712 int 2713 #ifdef BGE_IPMI_ASF 2714 bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive) 2715 #else 2716 bge_chip_sync(bge_t *bgep) 2717 #endif 2718 { 2719 void (*opfn)(bge_t *bgep, bge_regno_t reg, uint32_t bits); 2720 boolean_t promisc; 2721 uint64_t macaddr; 2722 uint32_t fill; 2723 int i, j; 2724 int retval = DDI_SUCCESS; 2725 2726 BGE_TRACE(("bge_chip_sync($%p)", 2727 (void *)bgep)); 2728 2729 ASSERT(mutex_owned(bgep->genlock)); 2730 2731 promisc = B_FALSE; 2732 fill = ~(uint32_t)0; 2733 2734 if (bgep->promisc) 2735 promisc = B_TRUE; 2736 else 2737 fill = (uint32_t)0; 2738 2739 /* 2740 * If the TX/RX MAC engines are already running, we should stop 2741 * them (and reset the RX engine) before changing the parameters. 2742 * If they're not running, this will have no effect ... 2743 * 2744 * NOTE: this is currently disabled by default because stopping 2745 * and restarting the Tx engine may cause an outgoing packet in 2746 * transit to be truncated. Also, stopping and restarting the 2747 * Rx engine seems to not work correctly on the 5705. Testing 2748 * has not (yet!) revealed any problems with NOT stopping and 2749 * restarting these engines (and Broadcom say their drivers don't 2750 * do this), but if it is found to cause problems, this variable 2751 * can be patched to re-enable the old behaviour ... 2752 */ 2753 if (bge_stop_start_on_sync) { 2754 #ifdef BGE_IPMI_ASF 2755 if (!bgep->asf_enabled) { 2756 if (!bge_chip_disable_engine(bgep, 2757 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG)) 2758 retval = DDI_FAILURE; 2759 } else { 2760 if (!bge_chip_disable_engine(bgep, 2761 RECEIVE_MAC_MODE_REG, 0)) 2762 retval = DDI_FAILURE; 2763 } 2764 #else 2765 if (!bge_chip_disable_engine(bgep, RECEIVE_MAC_MODE_REG, 2766 RECEIVE_MODE_KEEP_VLAN_TAG)) 2767 retval = DDI_FAILURE; 2768 #endif 2769 if (!bge_chip_disable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 2770 retval = DDI_FAILURE; 2771 if (!bge_chip_reset_engine(bgep, RECEIVE_MAC_MODE_REG)) 2772 retval = DDI_FAILURE; 2773 } 2774 2775 /* 2776 * Reprogram the hashed multicast address table ... 2777 */ 2778 for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i) 2779 bge_reg_put32(bgep, MAC_HASH_REG(i), 2780 bgep->mcast_hash[i] | fill); 2781 2782 #ifdef BGE_IPMI_ASF 2783 if (!bgep->asf_enabled || !asf_keeplive) { 2784 #endif 2785 /* 2786 * Transform the MAC address(es) from host to chip format, then 2787 * reprogram the transmit random backoff seed and the unicast 2788 * MAC address(es) ... 2789 */ 2790 for (j = 0; j < MAC_ADDRESS_REGS_MAX; j++) { 2791 for (i = 0, fill = 0, macaddr = 0ull; 2792 i < ETHERADDRL; ++i) { 2793 macaddr <<= 8; 2794 macaddr |= bgep->curr_addr[j].addr[i]; 2795 fill += bgep->curr_addr[j].addr[i]; 2796 } 2797 bge_reg_put32(bgep, MAC_TX_RANDOM_BACKOFF_REG, fill); 2798 bge_reg_put64(bgep, MAC_ADDRESS_REG(j), macaddr); 2799 } 2800 2801 BGE_DEBUG(("bge_chip_sync($%p) setting MAC address %012llx", 2802 (void *)bgep, macaddr)); 2803 #ifdef BGE_IPMI_ASF 2804 } 2805 #endif 2806 2807 /* 2808 * Set or clear the PROMISCUOUS mode bit 2809 */ 2810 opfn = promisc ? bge_reg_set32 : bge_reg_clr32; 2811 (*opfn)(bgep, RECEIVE_MAC_MODE_REG, RECEIVE_MODE_PROMISCUOUS); 2812 2813 /* 2814 * Sync the rest of the MAC modes too ... 2815 */ 2816 bge_sync_mac_modes(bgep); 2817 2818 /* 2819 * Restart RX/TX MAC engines if required ... 2820 */ 2821 if (bgep->bge_chip_state == BGE_CHIP_RUNNING) { 2822 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 2823 retval = DDI_FAILURE; 2824 #ifdef BGE_IPMI_ASF 2825 if (!bgep->asf_enabled) { 2826 if (!bge_chip_enable_engine(bgep, 2827 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG)) 2828 retval = DDI_FAILURE; 2829 } else { 2830 if (!bge_chip_enable_engine(bgep, 2831 RECEIVE_MAC_MODE_REG, 0)) 2832 retval = DDI_FAILURE; 2833 } 2834 #else 2835 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 2836 RECEIVE_MODE_KEEP_VLAN_TAG)) 2837 retval = DDI_FAILURE; 2838 #endif 2839 } 2840 return (retval); 2841 } 2842 2843 /* 2844 * This array defines the sequence of state machine control registers 2845 * in which the <enable> bit must be cleared to bring the chip to a 2846 * clean stop. Taken from Broadcom document 570X-PG102-R, p116. 2847 */ 2848 static bge_regno_t shutdown_engine_regs[] = { 2849 RECEIVE_MAC_MODE_REG, 2850 RCV_BD_INITIATOR_MODE_REG, 2851 RCV_LIST_PLACEMENT_MODE_REG, 2852 RCV_LIST_SELECTOR_MODE_REG, /* BCM5704 series only */ 2853 RCV_DATA_BD_INITIATOR_MODE_REG, 2854 RCV_DATA_COMPLETION_MODE_REG, 2855 RCV_BD_COMPLETION_MODE_REG, 2856 2857 SEND_BD_SELECTOR_MODE_REG, 2858 SEND_BD_INITIATOR_MODE_REG, 2859 SEND_DATA_INITIATOR_MODE_REG, 2860 READ_DMA_MODE_REG, 2861 SEND_DATA_COMPLETION_MODE_REG, 2862 DMA_COMPLETION_MODE_REG, /* BCM5704 series only */ 2863 SEND_BD_COMPLETION_MODE_REG, 2864 TRANSMIT_MAC_MODE_REG, 2865 2866 HOST_COALESCE_MODE_REG, 2867 WRITE_DMA_MODE_REG, 2868 MBUF_CLUSTER_FREE_MODE_REG, /* BCM5704 series only */ 2869 FTQ_RESET_REG, /* special - see code */ 2870 BUFFER_MANAGER_MODE_REG, /* BCM5704 series only */ 2871 MEMORY_ARBITER_MODE_REG, /* BCM5704 series only */ 2872 BGE_REGNO_NONE /* terminator */ 2873 }; 2874 2875 /* 2876 * bge_chip_stop() -- stop all chip processing 2877 * 2878 * If the <fault> parameter is B_TRUE, we're stopping the chip because 2879 * we've detected a problem internally; otherwise, this is a normal 2880 * (clean) stop (at user request i.e. the last STREAM has been closed). 2881 */ 2882 void bge_chip_stop(bge_t *bgep, boolean_t fault); 2883 #pragma no_inline(bge_chip_stop) 2884 2885 void 2886 bge_chip_stop(bge_t *bgep, boolean_t fault) 2887 { 2888 bge_regno_t regno; 2889 bge_regno_t *rbp; 2890 boolean_t ok; 2891 2892 BGE_TRACE(("bge_chip_stop($%p)", 2893 (void *)bgep)); 2894 2895 ASSERT(mutex_owned(bgep->genlock)); 2896 2897 rbp = shutdown_engine_regs; 2898 /* 2899 * When driver try to shutdown the BCM5705/5788/5721/5751/ 2900 * 5752/5714 and 5715 chipsets,the buffer manager and the mem 2901 * -ory arbiter should not be disabled. 2902 */ 2903 for (ok = B_TRUE; (regno = *rbp) != BGE_REGNO_NONE; ++rbp) { 2904 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 2905 ok &= bge_chip_disable_engine(bgep, regno, 0); 2906 else if ((regno != RCV_LIST_SELECTOR_MODE_REG) && 2907 (regno != DMA_COMPLETION_MODE_REG) && 2908 (regno != MBUF_CLUSTER_FREE_MODE_REG)&& 2909 (regno != BUFFER_MANAGER_MODE_REG) && 2910 (regno != MEMORY_ARBITER_MODE_REG)) 2911 ok &= bge_chip_disable_engine(bgep, 2912 regno, 0); 2913 } 2914 2915 if (!ok && !fault) 2916 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 2917 2918 /* 2919 * Finally, disable (all) MAC events & clear the MAC status 2920 */ 2921 bge_reg_put32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 0); 2922 bge_reg_put32(bgep, ETHERNET_MAC_STATUS_REG, ~0); 2923 2924 /* 2925 * if we're stopping the chip because of a detected fault then do 2926 * appropriate actions 2927 */ 2928 if (fault) { 2929 if (bgep->bge_chip_state != BGE_CHIP_FAULT) { 2930 bgep->bge_chip_state = BGE_CHIP_FAULT; 2931 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_LOST); 2932 if (bgep->bge_dma_error) { 2933 /* 2934 * need to free buffers in case the fault was 2935 * due to a memory error in a buffer - got to 2936 * do a fair bit of tidying first 2937 */ 2938 if (bgep->progress & PROGRESS_KSTATS) { 2939 bge_fini_kstats(bgep); 2940 bgep->progress &= ~PROGRESS_KSTATS; 2941 } 2942 if (bgep->progress & PROGRESS_INTR) { 2943 bge_intr_disable(bgep); 2944 rw_enter(bgep->errlock, RW_WRITER); 2945 bge_fini_rings(bgep); 2946 rw_exit(bgep->errlock); 2947 bgep->progress &= ~PROGRESS_INTR; 2948 } 2949 if (bgep->progress & PROGRESS_BUFS) { 2950 bge_free_bufs(bgep); 2951 bgep->progress &= ~PROGRESS_BUFS; 2952 } 2953 bgep->bge_dma_error = B_FALSE; 2954 } 2955 } 2956 } else 2957 bgep->bge_chip_state = BGE_CHIP_STOPPED; 2958 } 2959 2960 /* 2961 * Poll for completion of chip's ROM firmware; also, at least on the 2962 * first time through, find and return the hardware MAC address, if any. 2963 */ 2964 static uint64_t bge_poll_firmware(bge_t *bgep); 2965 #pragma no_inline(bge_poll_firmware) 2966 2967 static uint64_t 2968 bge_poll_firmware(bge_t *bgep) 2969 { 2970 uint64_t magic; 2971 uint64_t mac; 2972 uint32_t gen; 2973 uint32_t i; 2974 2975 /* 2976 * Step 19: poll for firmware completion (GENCOMM port set 2977 * to the ones complement of T3_MAGIC_NUMBER). 2978 * 2979 * While we're at it, we also read the MAC address register; 2980 * at some stage the firmware will load this with the 2981 * factory-set value. 2982 * 2983 * When both the magic number and the MAC address are set, 2984 * we're done; but we impose a time limit of one second 2985 * (1000*1000us) in case the firmware fails in some fashion 2986 * or the SEEPROM that provides that MAC address isn't fitted. 2987 * 2988 * After the first time through (chip state != INITIAL), we 2989 * don't need the MAC address to be set (we've already got it 2990 * or not, from the first time), so we don't wait for it, but 2991 * we still have to wait for the T3_MAGIC_NUMBER. 2992 * 2993 * Note: the magic number is only a 32-bit quantity, but the NIC 2994 * memory is 64-bit (and big-endian) internally. Addressing the 2995 * GENCOMM word as "the upper half of a 64-bit quantity" makes 2996 * it work correctly on both big- and little-endian hosts. 2997 */ 2998 for (i = 0; i < 1000; ++i) { 2999 drv_usecwait(1000); 3000 gen = bge_nic_get64(bgep, NIC_MEM_GENCOMM) >> 32; 3001 mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0)); 3002 #ifdef BGE_IPMI_ASF 3003 if (!bgep->asf_enabled) { 3004 #endif 3005 if (gen != ~T3_MAGIC_NUMBER) 3006 continue; 3007 #ifdef BGE_IPMI_ASF 3008 } 3009 #endif 3010 if (mac != 0ULL) 3011 break; 3012 if (bgep->bge_chip_state != BGE_CHIP_INITIAL) 3013 break; 3014 } 3015 3016 magic = bge_nic_get64(bgep, NIC_MEM_GENCOMM); 3017 BGE_DEBUG(("bge_poll_firmware($%p): PXE magic 0x%x after %d loops", 3018 (void *)bgep, gen, i)); 3019 BGE_DEBUG(("bge_poll_firmware: MAC %016llx, GENCOMM %016llx", 3020 mac, magic)); 3021 3022 return (mac); 3023 } 3024 3025 /* 3026 * Maximum times of trying to get the NVRAM access lock 3027 * by calling bge_nvmem_acquire() 3028 */ 3029 #define MAX_TRY_NVMEM_ACQUIRE 10000 3030 3031 #ifdef BGE_IPMI_ASF 3032 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode); 3033 #else 3034 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma); 3035 #endif 3036 #pragma no_inline(bge_chip_reset) 3037 3038 int 3039 #ifdef BGE_IPMI_ASF 3040 bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode) 3041 #else 3042 bge_chip_reset(bge_t *bgep, boolean_t enable_dma) 3043 #endif 3044 { 3045 chip_id_t chipid; 3046 uint64_t mac; 3047 uint64_t magic; 3048 uint32_t modeflags; 3049 uint32_t mhcr; 3050 uint32_t sx0; 3051 uint32_t i, tries; 3052 #ifdef BGE_IPMI_ASF 3053 uint32_t mailbox; 3054 #endif 3055 int retval = DDI_SUCCESS; 3056 3057 BGE_TRACE(("bge_chip_reset($%p, %d)", 3058 (void *)bgep, enable_dma)); 3059 3060 ASSERT(mutex_owned(bgep->genlock)); 3061 3062 BGE_DEBUG(("bge_chip_reset($%p, %d): current state is %d", 3063 (void *)bgep, enable_dma, bgep->bge_chip_state)); 3064 3065 /* 3066 * Do we need to stop the chip cleanly before resetting? 3067 */ 3068 switch (bgep->bge_chip_state) { 3069 default: 3070 _NOTE(NOTREACHED) 3071 return (DDI_FAILURE); 3072 3073 case BGE_CHIP_INITIAL: 3074 case BGE_CHIP_STOPPED: 3075 case BGE_CHIP_RESET: 3076 break; 3077 3078 case BGE_CHIP_RUNNING: 3079 case BGE_CHIP_ERROR: 3080 case BGE_CHIP_FAULT: 3081 bge_chip_stop(bgep, B_FALSE); 3082 break; 3083 } 3084 3085 #ifdef BGE_IPMI_ASF 3086 if (bgep->asf_enabled) { 3087 #ifdef __sparc 3088 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 3089 MHCR_ENABLE_TAGGED_STATUS_MODE | 3090 MHCR_MASK_INTERRUPT_MODE | 3091 MHCR_MASK_PCI_INT_OUTPUT | 3092 MHCR_CLEAR_INTERRUPT_INTA | 3093 MHCR_ENABLE_ENDIAN_WORD_SWAP | 3094 MHCR_ENABLE_ENDIAN_BYTE_SWAP; 3095 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr); 3096 bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG, 3097 bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG) | 3098 MEMORY_ARBITER_ENABLE); 3099 #endif 3100 if (asf_mode == ASF_MODE_INIT) { 3101 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 3102 } else if (asf_mode == ASF_MODE_SHUTDOWN) { 3103 bge_asf_pre_reset_operations(bgep, BGE_SHUTDOWN_RESET); 3104 } 3105 } 3106 #endif 3107 /* 3108 * Adapted from Broadcom document 570X-PG102-R, pp 102-116. 3109 * Updated to reflect Broadcom document 570X-PG104-R, pp 146-159. 3110 * 3111 * Before reset Core clock,it is 3112 * also required to initialize the Memory Arbiter as specified in step9 3113 * and Misc Host Control Register as specified in step-13 3114 * Step 4-5: reset Core clock & wait for completion 3115 * Steps 6-8: are done by bge_chip_cfg_init() 3116 * put the T3_MAGIC_NUMBER into the GENCOMM port before reset 3117 */ 3118 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 3119 retval = DDI_FAILURE; 3120 3121 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 3122 MHCR_ENABLE_TAGGED_STATUS_MODE | 3123 MHCR_MASK_INTERRUPT_MODE | 3124 MHCR_MASK_PCI_INT_OUTPUT | 3125 MHCR_CLEAR_INTERRUPT_INTA; 3126 #ifdef _BIG_ENDIAN 3127 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 3128 #endif /* _BIG_ENDIAN */ 3129 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr); 3130 #ifdef BGE_IPMI_ASF 3131 if (bgep->asf_enabled) 3132 bgep->asf_wordswapped = B_FALSE; 3133 #endif 3134 /* 3135 * NVRAM Corruption Workaround 3136 */ 3137 for (tries = 0; tries < MAX_TRY_NVMEM_ACQUIRE; tries++) 3138 if (bge_nvmem_acquire(bgep) != EAGAIN) 3139 break; 3140 if (tries >= MAX_TRY_NVMEM_ACQUIRE) 3141 BGE_DEBUG(("%s: fail to acquire nvram lock", 3142 bgep->ifname)); 3143 3144 #ifdef BGE_IPMI_ASF 3145 if (!bgep->asf_enabled) { 3146 #endif 3147 magic = (uint64_t)T3_MAGIC_NUMBER << 32; 3148 bge_nic_put64(bgep, NIC_MEM_GENCOMM, magic); 3149 #ifdef BGE_IPMI_ASF 3150 } 3151 #endif 3152 3153 if (!bge_chip_reset_engine(bgep, MISC_CONFIG_REG)) 3154 retval = DDI_FAILURE; 3155 bge_chip_cfg_init(bgep, &chipid, enable_dma); 3156 3157 /* 3158 * Step 8a: This may belong elsewhere, but BCM5721 needs 3159 * a bit set to avoid a fifo overflow/underflow bug. 3160 */ 3161 if ((bgep->chipid.chip_label == 5721) || 3162 (bgep->chipid.chip_label == 5751) || 3163 (bgep->chipid.chip_label == 5752) || 3164 (bgep->chipid.chip_label == 5755) || 3165 (bgep->chipid.chip_label == 5789)) 3166 bge_reg_set32(bgep, TLP_CONTROL_REG, TLP_DATA_FIFO_PROTECT); 3167 3168 3169 /* 3170 * Step 9: enable MAC memory arbiter,bit30 and bit31 of 5714/5715 should 3171 * not be changed. 3172 */ 3173 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 3174 retval = DDI_FAILURE; 3175 3176 /* 3177 * Steps 10-11: configure PIO endianness options and 3178 * enable indirect register access -- already done 3179 * Steps 12-13: enable writing to the PCI state & clock 3180 * control registers -- not required; we aren't going to 3181 * use those features. 3182 * Steps 14-15: Configure DMA endianness options. See 3183 * the comments on the setting of the MHCR above. 3184 */ 3185 #ifdef _BIG_ENDIAN 3186 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME | 3187 MODE_WORD_SWAP_NONFRAME | MODE_BYTE_SWAP_NONFRAME; 3188 #else 3189 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME; 3190 #endif /* _BIG_ENDIAN */ 3191 #ifdef BGE_IPMI_ASF 3192 if (bgep->asf_enabled) 3193 modeflags |= MODE_HOST_STACK_UP; 3194 #endif 3195 bge_reg_put32(bgep, MODE_CONTROL_REG, modeflags); 3196 3197 #ifdef BGE_IPMI_ASF 3198 if (bgep->asf_enabled) { 3199 #ifdef __sparc 3200 bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG, 3201 MEMORY_ARBITER_ENABLE | 3202 bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG)); 3203 #endif 3204 3205 #ifdef BGE_NETCONSOLE 3206 if (!bgep->asf_newhandshake) { 3207 if ((asf_mode == ASF_MODE_INIT) || 3208 (asf_mode == ASF_MODE_POST_INIT)) { 3209 bge_asf_post_reset_old_mode(bgep, 3210 BGE_INIT_RESET); 3211 } else { 3212 bge_asf_post_reset_old_mode(bgep, 3213 BGE_SHUTDOWN_RESET); 3214 } 3215 } 3216 #endif 3217 3218 /* Wait for NVRAM init */ 3219 i = 0; 3220 drv_usecwait(5000); 3221 mailbox = bge_nic_get32(bgep, BGE_FIRMWARE_MAILBOX); 3222 3223 while ((mailbox != (uint32_t) 3224 ~BGE_MAGIC_NUM_FIRMWARE_INIT_DONE) && 3225 (i < 10000)) { 3226 drv_usecwait(100); 3227 mailbox = bge_nic_get32(bgep, 3228 BGE_FIRMWARE_MAILBOX); 3229 i++; 3230 } 3231 3232 #ifndef BGE_NETCONSOLE 3233 if (!bgep->asf_newhandshake) { 3234 if ((asf_mode == ASF_MODE_INIT) || 3235 (asf_mode == ASF_MODE_POST_INIT)) { 3236 3237 bge_asf_post_reset_old_mode(bgep, 3238 BGE_INIT_RESET); 3239 } else { 3240 bge_asf_post_reset_old_mode(bgep, 3241 BGE_SHUTDOWN_RESET); 3242 } 3243 } 3244 #endif 3245 } 3246 #endif 3247 /* 3248 * Steps 16-17: poll for firmware completion 3249 */ 3250 mac = bge_poll_firmware(bgep); 3251 3252 /* 3253 * Step 18: enable external memory -- doesn't apply. 3254 * 3255 * However we take the opportunity to set the MLCR anyway, as 3256 * this register also controls the SEEPROM auto-access method 3257 * which we may want to use later ... 3258 * 3259 * The proper value here depends on the way the chip is wired 3260 * into the circuit board, as this register *also* controls which 3261 * of the "Miscellaneous I/O" pins are driven as outputs and the 3262 * values driven onto those pins! 3263 * 3264 * See also step 74 in the PRM ... 3265 */ 3266 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, 3267 bgep->chipid.bge_mlcr_default); 3268 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 3269 3270 /* 3271 * Step 20: clear the Ethernet MAC mode register 3272 */ 3273 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, 0); 3274 3275 /* 3276 * Step 21: restore cache-line-size, latency timer, and 3277 * subsystem ID registers to their original values (not 3278 * those read into the local structure <chipid>, 'cos 3279 * that was after they were cleared by the RESET). 3280 * 3281 * Note: the Subsystem Vendor/Device ID registers are not 3282 * directly writable in config space, so we use the shadow 3283 * copy in "Page Zero" of register space to restore them 3284 * both in one go ... 3285 */ 3286 pci_config_put8(bgep->cfg_handle, PCI_CONF_CACHE_LINESZ, 3287 bgep->chipid.clsize); 3288 pci_config_put8(bgep->cfg_handle, PCI_CONF_LATENCY_TIMER, 3289 bgep->chipid.latency); 3290 bge_reg_put32(bgep, PCI_CONF_SUBVENID, 3291 (bgep->chipid.subdev << 16) | bgep->chipid.subven); 3292 3293 /* 3294 * The SEND INDEX registers should be reset to zero by the 3295 * global chip reset; if they're not, there'll be trouble 3296 * later on. 3297 */ 3298 sx0 = bge_reg_get32(bgep, NIC_DIAG_SEND_INDEX_REG(0)); 3299 if (sx0 != 0) { 3300 BGE_REPORT((bgep, "SEND INDEX - device didn't RESET")); 3301 bge_fm_ereport(bgep, DDI_FM_DEVICE_INVAL_STATE); 3302 retval = DDI_FAILURE; 3303 } 3304 3305 /* Enable MSI code */ 3306 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 3307 bge_reg_set32(bgep, MSI_MODE_REG, 3308 MSI_PRI_HIGHEST|MSI_MSI_ENABLE|MSI_ERROR_ATTENTION); 3309 3310 /* 3311 * On the first time through, save the factory-set MAC address 3312 * (if any). If bge_poll_firmware() above didn't return one 3313 * (from a chip register) consider looking in the attached NV 3314 * memory device, if any. Once we have it, we save it in both 3315 * register-image (64-bit) and byte-array forms. All-zero and 3316 * all-one addresses are not valid, and we refuse to stash those. 3317 */ 3318 if (bgep->bge_chip_state == BGE_CHIP_INITIAL) { 3319 if (mac == 0ULL) 3320 mac = bge_get_nvmac(bgep); 3321 if (mac != 0ULL && mac != ~0ULL) { 3322 bgep->chipid.hw_mac_addr = mac; 3323 for (i = ETHERADDRL; i-- != 0; ) { 3324 bgep->chipid.vendor_addr.addr[i] = (uchar_t)mac; 3325 mac >>= 8; 3326 } 3327 bgep->chipid.vendor_addr.set = B_TRUE; 3328 } 3329 } 3330 3331 #ifdef BGE_IPMI_ASF 3332 if (bgep->asf_enabled && bgep->asf_newhandshake) { 3333 if (asf_mode != ASF_MODE_NONE) { 3334 if ((asf_mode == ASF_MODE_INIT) || 3335 (asf_mode == ASF_MODE_POST_INIT)) { 3336 3337 bge_asf_post_reset_new_mode(bgep, 3338 BGE_INIT_RESET); 3339 } else { 3340 bge_asf_post_reset_new_mode(bgep, 3341 BGE_SHUTDOWN_RESET); 3342 } 3343 } 3344 } 3345 #endif 3346 3347 /* 3348 * Record the new state 3349 */ 3350 bgep->chip_resets += 1; 3351 bgep->bge_chip_state = BGE_CHIP_RESET; 3352 return (retval); 3353 } 3354 3355 /* 3356 * bge_chip_start() -- start the chip transmitting and/or receiving, 3357 * including enabling interrupts 3358 */ 3359 int bge_chip_start(bge_t *bgep, boolean_t reset_phys); 3360 #pragma no_inline(bge_chip_start) 3361 3362 int 3363 bge_chip_start(bge_t *bgep, boolean_t reset_phys) 3364 { 3365 uint32_t coalmode; 3366 uint32_t ledctl; 3367 uint32_t mtu; 3368 uint32_t maxring; 3369 uint32_t stats_mask; 3370 uint32_t dma_wrprio; 3371 uint64_t ring; 3372 int retval = DDI_SUCCESS; 3373 3374 BGE_TRACE(("bge_chip_start($%p)", 3375 (void *)bgep)); 3376 3377 ASSERT(mutex_owned(bgep->genlock)); 3378 ASSERT(bgep->bge_chip_state == BGE_CHIP_RESET); 3379 3380 /* 3381 * Taken from Broadcom document 570X-PG102-R, pp 102-116. 3382 * The document specifies 95 separate steps to fully 3383 * initialise the chip!!!! 3384 * 3385 * The reset code above has already got us as far as step 3386 * 21, so we continue with ... 3387 * 3388 * Step 22: clear the MAC statistics block 3389 * (0x0300-0x0aff in NIC-local memory) 3390 */ 3391 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 3392 bge_nic_zero(bgep, NIC_MEM_STATISTICS, 3393 NIC_MEM_STATISTICS_SIZE); 3394 3395 /* 3396 * Step 23: clear the status block (in host memory) 3397 */ 3398 DMA_ZERO(bgep->status_block); 3399 3400 /* 3401 * Step 24: set DMA read/write control register 3402 */ 3403 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_PDRWCR, 3404 bgep->chipid.bge_dma_rwctrl); 3405 3406 /* 3407 * Step 25: Configure DMA endianness -- already done (16/17) 3408 * Step 26: Configure Host-Based Send Rings 3409 * Step 27: Indicate Host Stack Up 3410 */ 3411 bge_reg_set32(bgep, MODE_CONTROL_REG, 3412 MODE_HOST_SEND_BDS | 3413 MODE_HOST_STACK_UP); 3414 3415 /* 3416 * Step 28: Configure checksum options: 3417 * Solaris supports the hardware default checksum options. 3418 * 3419 * Workaround for Incorrect pseudo-header checksum calculation. 3420 */ 3421 if (bgep->chipid.flags & CHIP_FLAG_PARTIAL_CSUM) 3422 bge_reg_set32(bgep, MODE_CONTROL_REG, 3423 MODE_SEND_NO_PSEUDO_HDR_CSUM); 3424 3425 /* 3426 * Step 29: configure Timer Prescaler. The value is always the 3427 * same: the Core Clock frequency in MHz (66), minus 1, shifted 3428 * into bits 7-1. Don't set bit 0, 'cos that's the RESET bit 3429 * for the whole chip! 3430 */ 3431 bge_reg_put32(bgep, MISC_CONFIG_REG, MISC_CONFIG_DEFAULT); 3432 3433 /* 3434 * Steps 30-31: Configure MAC local memory pool & DMA pool registers 3435 * 3436 * If the mbuf_length is specified as 0, we just leave these at 3437 * their hardware defaults, rather than explicitly setting them. 3438 * As the Broadcom HRM,driver better not change the parameters 3439 * when the chipsets is 5705/5788/5721/5751/5714 and 5715. 3440 */ 3441 if ((bgep->chipid.mbuf_length != 0) && 3442 (DEVICE_5704_SERIES_CHIPSETS(bgep))) { 3443 bge_reg_put32(bgep, MBUF_POOL_BASE_REG, 3444 bgep->chipid.mbuf_base); 3445 bge_reg_put32(bgep, MBUF_POOL_LENGTH_REG, 3446 bgep->chipid.mbuf_length); 3447 bge_reg_put32(bgep, DMAD_POOL_BASE_REG, 3448 DMAD_POOL_BASE_DEFAULT); 3449 bge_reg_put32(bgep, DMAD_POOL_LENGTH_REG, 3450 DMAD_POOL_LENGTH_DEFAULT); 3451 } 3452 3453 /* 3454 * Step 32: configure MAC memory pool watermarks 3455 */ 3456 bge_reg_put32(bgep, RDMA_MBUF_LOWAT_REG, 3457 bgep->chipid.mbuf_lo_water_rdma); 3458 bge_reg_put32(bgep, MAC_RX_MBUF_LOWAT_REG, 3459 bgep->chipid.mbuf_lo_water_rmac); 3460 bge_reg_put32(bgep, MBUF_HIWAT_REG, 3461 bgep->chipid.mbuf_hi_water); 3462 3463 /* 3464 * Step 33: configure DMA resource watermarks 3465 */ 3466 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3467 bge_reg_put32(bgep, DMAD_POOL_LOWAT_REG, 3468 bge_dmad_lo_water); 3469 bge_reg_put32(bgep, DMAD_POOL_HIWAT_REG, 3470 bge_dmad_hi_water); 3471 } 3472 bge_reg_put32(bgep, LOWAT_MAX_RECV_FRAMES_REG, bge_lowat_recv_frames); 3473 3474 /* 3475 * Steps 34-36: enable buffer manager & internal h/w queues 3476 */ 3477 if (!bge_chip_enable_engine(bgep, BUFFER_MANAGER_MODE_REG, 3478 STATE_MACHINE_ATTN_ENABLE_BIT)) 3479 retval = DDI_FAILURE; 3480 if (!bge_chip_enable_engine(bgep, FTQ_RESET_REG, 0)) 3481 retval = DDI_FAILURE; 3482 3483 /* 3484 * Steps 37-39: initialise Receive Buffer (Producer) RCBs 3485 */ 3486 bge_reg_putrcb(bgep, STD_RCV_BD_RING_RCB_REG, 3487 &bgep->buff[BGE_STD_BUFF_RING].hw_rcb); 3488 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3489 bge_reg_putrcb(bgep, JUMBO_RCV_BD_RING_RCB_REG, 3490 &bgep->buff[BGE_JUMBO_BUFF_RING].hw_rcb); 3491 bge_reg_putrcb(bgep, MINI_RCV_BD_RING_RCB_REG, 3492 &bgep->buff[BGE_MINI_BUFF_RING].hw_rcb); 3493 } 3494 3495 /* 3496 * Step 40: set Receive Buffer Descriptor Ring replenish thresholds 3497 */ 3498 bge_reg_put32(bgep, STD_RCV_BD_REPLENISH_REG, bge_replenish_std); 3499 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3500 bge_reg_put32(bgep, JUMBO_RCV_BD_REPLENISH_REG, 3501 bge_replenish_jumbo); 3502 bge_reg_put32(bgep, MINI_RCV_BD_REPLENISH_REG, 3503 bge_replenish_mini); 3504 } 3505 3506 /* 3507 * Steps 41-43: clear Send Ring Producer Indices and initialise 3508 * Send Producer Rings (0x0100-0x01ff in NIC-local memory) 3509 */ 3510 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3511 maxring = BGE_SEND_RINGS_MAX; 3512 else 3513 maxring = BGE_SEND_RINGS_MAX_5705; 3514 for (ring = 0; ring < maxring; ++ring) { 3515 bge_mbx_put(bgep, SEND_RING_HOST_INDEX_REG(ring), 0); 3516 bge_mbx_put(bgep, SEND_RING_NIC_INDEX_REG(ring), 0); 3517 bge_nic_putrcb(bgep, NIC_MEM_SEND_RING(ring), 3518 &bgep->send[ring].hw_rcb); 3519 } 3520 3521 /* 3522 * Steps 44-45: initialise Receive Return Rings 3523 * (0x0200-0x02ff in NIC-local memory) 3524 */ 3525 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3526 maxring = BGE_RECV_RINGS_MAX; 3527 else 3528 maxring = BGE_RECV_RINGS_MAX_5705; 3529 for (ring = 0; ring < maxring; ++ring) 3530 bge_nic_putrcb(bgep, NIC_MEM_RECV_RING(ring), 3531 &bgep->recv[ring].hw_rcb); 3532 3533 /* 3534 * Step 46: initialise Receive Buffer (Producer) Ring indexes 3535 */ 3536 bge_mbx_put(bgep, RECV_STD_PROD_INDEX_REG, 0); 3537 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3538 bge_mbx_put(bgep, RECV_JUMBO_PROD_INDEX_REG, 0); 3539 bge_mbx_put(bgep, RECV_MINI_PROD_INDEX_REG, 0); 3540 } 3541 /* 3542 * Step 47: configure the MAC unicast address 3543 * Step 48: configure the random backoff seed 3544 * Step 96: set up multicast filters 3545 */ 3546 #ifdef BGE_IPMI_ASF 3547 if (bge_chip_sync(bgep, B_FALSE) == DDI_FAILURE) 3548 #else 3549 if (bge_chip_sync(bgep) == DDI_FAILURE) 3550 #endif 3551 retval = DDI_FAILURE; 3552 3553 /* 3554 * Step 49: configure the MTU 3555 */ 3556 mtu = bgep->chipid.ethmax_size+ETHERFCSL+VLAN_TAGSZ; 3557 bge_reg_put32(bgep, MAC_RX_MTU_SIZE_REG, mtu); 3558 3559 /* 3560 * Step 50: configure the IPG et al 3561 */ 3562 bge_reg_put32(bgep, MAC_TX_LENGTHS_REG, MAC_TX_LENGTHS_DEFAULT); 3563 3564 /* 3565 * Step 51: configure the default Rx Return Ring 3566 */ 3567 bge_reg_put32(bgep, RCV_RULES_CONFIG_REG, RCV_RULES_CONFIG_DEFAULT); 3568 3569 /* 3570 * Steps 52-54: configure Receive List Placement, 3571 * and enable Receive List Placement Statistics 3572 */ 3573 bge_reg_put32(bgep, RCV_LP_CONFIG_REG, 3574 RCV_LP_CONFIG(bgep->chipid.rx_rings)); 3575 switch (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev)) { 3576 case MHCR_CHIP_ASIC_REV_5700: 3577 case MHCR_CHIP_ASIC_REV_5701: 3578 case MHCR_CHIP_ASIC_REV_5703: 3579 case MHCR_CHIP_ASIC_REV_5704: 3580 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, ~0); 3581 break; 3582 case MHCR_CHIP_ASIC_REV_5705: 3583 break; 3584 default: 3585 stats_mask = bge_reg_get32(bgep, RCV_LP_STATS_ENABLE_MASK_REG); 3586 stats_mask &= ~RCV_LP_STATS_DISABLE_MACTQ; 3587 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, stats_mask); 3588 break; 3589 } 3590 bge_reg_set32(bgep, RCV_LP_STATS_CONTROL_REG, RCV_LP_STATS_ENABLE); 3591 3592 if (bgep->chipid.rx_rings > 1) 3593 bge_init_recv_rule(bgep); 3594 3595 /* 3596 * Steps 55-56: enable Send Data Initiator Statistics 3597 */ 3598 bge_reg_put32(bgep, SEND_INIT_STATS_ENABLE_MASK_REG, ~0); 3599 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3600 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 3601 SEND_INIT_STATS_ENABLE | SEND_INIT_STATS_FASTER); 3602 } else { 3603 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 3604 SEND_INIT_STATS_ENABLE); 3605 } 3606 /* 3607 * Steps 57-58: stop (?) the Host Coalescing Engine 3608 */ 3609 if (!bge_chip_disable_engine(bgep, HOST_COALESCE_MODE_REG, ~0)) 3610 retval = DDI_FAILURE; 3611 3612 /* 3613 * Steps 59-62: initialise Host Coalescing parameters 3614 */ 3615 bge_reg_put32(bgep, SEND_COALESCE_MAX_BD_REG, bge_tx_count_norm); 3616 bge_reg_put32(bgep, SEND_COALESCE_TICKS_REG, bge_tx_ticks_norm); 3617 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, bge_rx_count_norm); 3618 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, bge_rx_ticks_norm); 3619 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3620 bge_reg_put32(bgep, SEND_COALESCE_INT_BD_REG, 3621 bge_tx_count_intr); 3622 bge_reg_put32(bgep, SEND_COALESCE_INT_TICKS_REG, 3623 bge_tx_ticks_intr); 3624 bge_reg_put32(bgep, RCV_COALESCE_INT_BD_REG, 3625 bge_rx_count_intr); 3626 bge_reg_put32(bgep, RCV_COALESCE_INT_TICKS_REG, 3627 bge_rx_ticks_intr); 3628 } 3629 3630 /* 3631 * Steps 63-64: initialise status block & statistics 3632 * host memory addresses 3633 * The statistic block does not exist in some chipsets 3634 * Step 65: initialise Statistics Coalescing Tick Counter 3635 */ 3636 bge_reg_put64(bgep, STATUS_BLOCK_HOST_ADDR_REG, 3637 bgep->status_block.cookie.dmac_laddress); 3638 3639 /* 3640 * Steps 66-67: initialise status block & statistics 3641 * NIC-local memory addresses 3642 */ 3643 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3644 bge_reg_put64(bgep, STATISTICS_HOST_ADDR_REG, 3645 bgep->statistics.cookie.dmac_laddress); 3646 bge_reg_put32(bgep, STATISTICS_TICKS_REG, 3647 STATISTICS_TICKS_DEFAULT); 3648 bge_reg_put32(bgep, STATUS_BLOCK_BASE_ADDR_REG, 3649 NIC_MEM_STATUS_BLOCK); 3650 bge_reg_put32(bgep, STATISTICS_BASE_ADDR_REG, 3651 NIC_MEM_STATISTICS); 3652 } 3653 3654 /* 3655 * Steps 68-71: start the Host Coalescing Engine, the Receive BD 3656 * Completion Engine, the Receive List Placement Engine, and the 3657 * Receive List selector.Pay attention:0x3400 is not exist in BCM5714 3658 * and BCM5715. 3659 */ 3660 if (bgep->chipid.tx_rings <= COALESCE_64_BYTE_RINGS && 3661 bgep->chipid.rx_rings <= COALESCE_64_BYTE_RINGS) 3662 coalmode = COALESCE_64_BYTE_STATUS; 3663 else 3664 coalmode = 0; 3665 if (!bge_chip_enable_engine(bgep, HOST_COALESCE_MODE_REG, coalmode)) 3666 retval = DDI_FAILURE; 3667 if (!bge_chip_enable_engine(bgep, RCV_BD_COMPLETION_MODE_REG, 3668 STATE_MACHINE_ATTN_ENABLE_BIT)) 3669 retval = DDI_FAILURE; 3670 if (!bge_chip_enable_engine(bgep, RCV_LIST_PLACEMENT_MODE_REG, 0)) 3671 retval = DDI_FAILURE; 3672 3673 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3674 if (!bge_chip_enable_engine(bgep, RCV_LIST_SELECTOR_MODE_REG, 3675 STATE_MACHINE_ATTN_ENABLE_BIT)) 3676 retval = DDI_FAILURE; 3677 3678 /* 3679 * Step 72: Enable MAC DMA engines 3680 * Step 73: Clear & enable MAC statistics 3681 */ 3682 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 3683 ETHERNET_MODE_ENABLE_FHDE | 3684 ETHERNET_MODE_ENABLE_RDE | 3685 ETHERNET_MODE_ENABLE_TDE); 3686 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 3687 ETHERNET_MODE_ENABLE_TX_STATS | 3688 ETHERNET_MODE_ENABLE_RX_STATS | 3689 ETHERNET_MODE_CLEAR_TX_STATS | 3690 ETHERNET_MODE_CLEAR_RX_STATS); 3691 3692 /* 3693 * Step 74: configure the MLCR (Miscellaneous Local Control 3694 * Register); not required, as we set up the MLCR in step 10 3695 * (part of the reset code) above. 3696 * 3697 * Step 75: clear Interrupt Mailbox 0 3698 */ 3699 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 0); 3700 3701 /* 3702 * Steps 76-87: Gentlemen, start your engines ... 3703 * 3704 * Enable the DMA Completion Engine, the Write DMA Engine, 3705 * the Read DMA Engine, Receive Data Completion Engine, 3706 * the MBuf Cluster Free Engine, the Send Data Completion Engine, 3707 * the Send BD Completion Engine, the Receive BD Initiator Engine, 3708 * the Receive Data Initiator Engine, the Send Data Initiator Engine, 3709 * the Send BD Initiator Engine, and the Send BD Selector Engine. 3710 * 3711 * Beware exhaust fumes? 3712 */ 3713 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3714 if (!bge_chip_enable_engine(bgep, DMA_COMPLETION_MODE_REG, 0)) 3715 retval = DDI_FAILURE; 3716 dma_wrprio = (bge_dma_wrprio << DMA_PRIORITY_SHIFT) | 3717 ALL_DMA_ATTN_BITS; 3718 if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) == 3719 MHCR_CHIP_ASIC_REV_5755) { 3720 dma_wrprio |= DMA_STATUS_TAG_FIX_CQ12384; 3721 } 3722 if (!bge_chip_enable_engine(bgep, WRITE_DMA_MODE_REG, 3723 dma_wrprio)) 3724 retval = DDI_FAILURE; 3725 if (!bge_chip_enable_engine(bgep, READ_DMA_MODE_REG, 3726 (bge_dma_rdprio << DMA_PRIORITY_SHIFT) | ALL_DMA_ATTN_BITS)) 3727 retval = DDI_FAILURE; 3728 if (!bge_chip_enable_engine(bgep, RCV_DATA_COMPLETION_MODE_REG, 3729 STATE_MACHINE_ATTN_ENABLE_BIT)) 3730 retval = DDI_FAILURE; 3731 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3732 if (!bge_chip_enable_engine(bgep, 3733 MBUF_CLUSTER_FREE_MODE_REG, 0)) 3734 retval = DDI_FAILURE; 3735 if (!bge_chip_enable_engine(bgep, SEND_DATA_COMPLETION_MODE_REG, 0)) 3736 retval = DDI_FAILURE; 3737 if (!bge_chip_enable_engine(bgep, SEND_BD_COMPLETION_MODE_REG, 3738 STATE_MACHINE_ATTN_ENABLE_BIT)) 3739 retval = DDI_FAILURE; 3740 if (!bge_chip_enable_engine(bgep, RCV_BD_INITIATOR_MODE_REG, 3741 RCV_BD_DISABLED_RING_ATTN)) 3742 retval = DDI_FAILURE; 3743 if (!bge_chip_enable_engine(bgep, RCV_DATA_BD_INITIATOR_MODE_REG, 3744 RCV_DATA_BD_ILL_RING_ATTN)) 3745 retval = DDI_FAILURE; 3746 if (!bge_chip_enable_engine(bgep, SEND_DATA_INITIATOR_MODE_REG, 0)) 3747 retval = DDI_FAILURE; 3748 if (!bge_chip_enable_engine(bgep, SEND_BD_INITIATOR_MODE_REG, 3749 STATE_MACHINE_ATTN_ENABLE_BIT)) 3750 retval = DDI_FAILURE; 3751 if (!bge_chip_enable_engine(bgep, SEND_BD_SELECTOR_MODE_REG, 3752 STATE_MACHINE_ATTN_ENABLE_BIT)) 3753 retval = DDI_FAILURE; 3754 3755 /* 3756 * Step 88: download firmware -- doesn't apply 3757 * Steps 89-90: enable Transmit & Receive MAC Engines 3758 */ 3759 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 3760 retval = DDI_FAILURE; 3761 #ifdef BGE_IPMI_ASF 3762 if (!bgep->asf_enabled) { 3763 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 3764 RECEIVE_MODE_KEEP_VLAN_TAG)) 3765 retval = DDI_FAILURE; 3766 } else { 3767 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 0)) 3768 retval = DDI_FAILURE; 3769 } 3770 #else 3771 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 3772 RECEIVE_MODE_KEEP_VLAN_TAG)) 3773 retval = DDI_FAILURE; 3774 #endif 3775 3776 /* 3777 * Step 91: disable auto-polling of PHY status 3778 */ 3779 bge_reg_put32(bgep, MI_MODE_REG, MI_MODE_DEFAULT); 3780 3781 /* 3782 * Step 92: configure D0 power state (not required) 3783 * Step 93: initialise LED control register () 3784 */ 3785 ledctl = LED_CONTROL_DEFAULT; 3786 switch (bgep->chipid.device) { 3787 case DEVICE_ID_5700: 3788 case DEVICE_ID_5700x: 3789 case DEVICE_ID_5701: 3790 /* 3791 * Switch to 5700 (MAC) mode on these older chips 3792 */ 3793 ledctl &= ~LED_CONTROL_LED_MODE_MASK; 3794 ledctl |= LED_CONTROL_LED_MODE_5700; 3795 break; 3796 3797 default: 3798 break; 3799 } 3800 bge_reg_put32(bgep, ETHERNET_MAC_LED_CONTROL_REG, ledctl); 3801 3802 /* 3803 * Step 94: activate link 3804 */ 3805 bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK); 3806 3807 /* 3808 * Step 95: set up physical layer (PHY/SerDes) 3809 * restart autoneg (if required) 3810 */ 3811 if (reset_phys) 3812 if (bge_phys_update(bgep) == DDI_FAILURE) 3813 retval = DDI_FAILURE; 3814 3815 /* 3816 * Extra step (DSG): hand over all the Receive Buffers to the chip 3817 */ 3818 for (ring = 0; ring < BGE_BUFF_RINGS_USED; ++ring) 3819 bge_mbx_put(bgep, bgep->buff[ring].chip_mbx_reg, 3820 bgep->buff[ring].rf_next); 3821 3822 /* 3823 * MSI bits:The least significant MSI 16-bit word. 3824 * ISR will be triggered different. 3825 */ 3826 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 3827 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 0x70); 3828 3829 /* 3830 * Extra step (DSG): select which interrupts are enabled 3831 * 3832 * Program the Ethernet MAC engine to signal attention on 3833 * Link Change events, then enable interrupts on MAC, DMA, 3834 * and FLOW attention signals. 3835 */ 3836 bge_reg_set32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 3837 ETHERNET_EVENT_LINK_INT | 3838 ETHERNET_STATUS_PCS_ERROR_INT); 3839 #ifdef BGE_IPMI_ASF 3840 if (bgep->asf_enabled) { 3841 bge_reg_set32(bgep, MODE_CONTROL_REG, 3842 MODE_INT_ON_FLOW_ATTN | 3843 MODE_INT_ON_DMA_ATTN | 3844 MODE_HOST_STACK_UP| 3845 MODE_INT_ON_MAC_ATTN); 3846 } else { 3847 #endif 3848 bge_reg_set32(bgep, MODE_CONTROL_REG, 3849 MODE_INT_ON_FLOW_ATTN | 3850 MODE_INT_ON_DMA_ATTN | 3851 MODE_INT_ON_MAC_ATTN); 3852 #ifdef BGE_IPMI_ASF 3853 } 3854 #endif 3855 3856 /* 3857 * Step 97: enable PCI interrupts!!! 3858 */ 3859 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 3860 bge_cfg_clr32(bgep, PCI_CONF_BGE_MHCR, 3861 MHCR_MASK_PCI_INT_OUTPUT); 3862 3863 /* 3864 * All done! 3865 */ 3866 bgep->bge_chip_state = BGE_CHIP_RUNNING; 3867 return (retval); 3868 } 3869 3870 3871 /* 3872 * ========== Hardware interrupt handler ========== 3873 */ 3874 3875 #undef BGE_DBG 3876 #define BGE_DBG BGE_DBG_INT /* debug flag for this code */ 3877 3878 /* 3879 * Sync the status block, then atomically clear the specified bits in 3880 * the <flags-and-tag> field of the status block. 3881 * the <flags> word of the status block, returning the value of the 3882 * <tag> and the <flags> before the bits were cleared. 3883 */ 3884 static int bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags); 3885 #pragma inline(bge_status_sync) 3886 3887 static int 3888 bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags) 3889 { 3890 bge_status_t *bsp; 3891 int retval; 3892 3893 BGE_TRACE(("bge_status_sync($%p, 0x%llx)", 3894 (void *)bgep, bits)); 3895 3896 ASSERT(bgep->bge_guard == BGE_GUARD); 3897 3898 DMA_SYNC(bgep->status_block, DDI_DMA_SYNC_FORKERNEL); 3899 retval = bge_check_dma_handle(bgep, bgep->status_block.dma_hdl); 3900 if (retval != DDI_FM_OK) 3901 return (retval); 3902 3903 bsp = DMA_VPTR(bgep->status_block); 3904 *flags = bge_atomic_clr64(&bsp->flags_n_tag, bits); 3905 3906 BGE_DEBUG(("bge_status_sync($%p, 0x%llx) returning 0x%llx", 3907 (void *)bgep, bits, *flags)); 3908 3909 return (retval); 3910 } 3911 3912 static void bge_wake_factotum(bge_t *bgep); 3913 #pragma inline(bge_wake_factotum) 3914 3915 static void 3916 bge_wake_factotum(bge_t *bgep) 3917 { 3918 mutex_enter(bgep->softintrlock); 3919 if (bgep->factotum_flag == 0) { 3920 bgep->factotum_flag = 1; 3921 ddi_trigger_softintr(bgep->factotum_id); 3922 } 3923 mutex_exit(bgep->softintrlock); 3924 } 3925 3926 /* 3927 * bge_intr() -- handle chip interrupts 3928 */ 3929 uint_t bge_intr(caddr_t arg1, caddr_t arg2); 3930 #pragma no_inline(bge_intr) 3931 3932 uint_t 3933 bge_intr(caddr_t arg1, caddr_t arg2) 3934 { 3935 bge_t *bgep = (bge_t *)arg1; /* private device info */ 3936 bge_status_t *bsp; 3937 uint64_t flags; 3938 uint32_t regval; 3939 uint_t result; 3940 int retval, loop_cnt = 0; 3941 3942 BGE_TRACE(("bge_intr($%p) ($%p)", arg1, arg2)); 3943 3944 /* 3945 * GLD v2 checks that s/w setup is complete before passing 3946 * interrupts to this routine, thus eliminating the old 3947 * (and well-known) race condition around ddi_add_intr() 3948 */ 3949 ASSERT(bgep->progress & PROGRESS_HWINT); 3950 3951 result = DDI_INTR_UNCLAIMED; 3952 mutex_enter(bgep->genlock); 3953 3954 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) { 3955 /* 3956 * Check whether chip's says it's asserting #INTA; 3957 * if not, don't process or claim the interrupt. 3958 * 3959 * Note that the PCI signal is active low, so the 3960 * bit is *zero* when the interrupt is asserted. 3961 */ 3962 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 3963 if (regval & MLCR_INTA_STATE) { 3964 if (bge_check_acc_handle(bgep, bgep->io_handle) 3965 != DDI_FM_OK) 3966 goto chip_stop; 3967 mutex_exit(bgep->genlock); 3968 return (result); 3969 } 3970 3971 /* 3972 * Block further PCI interrupts ... 3973 */ 3974 bge_reg_set32(bgep, PCI_CONF_BGE_MHCR, 3975 MHCR_MASK_PCI_INT_OUTPUT); 3976 3977 } else { 3978 /* 3979 * Check MSI status 3980 */ 3981 regval = bge_reg_get32(bgep, MSI_STATUS_REG); 3982 if (regval & MSI_ERROR_ATTENTION) { 3983 BGE_REPORT((bgep, "msi error attention," 3984 " status=0x%x", regval)); 3985 bge_reg_put32(bgep, MSI_STATUS_REG, regval); 3986 } 3987 } 3988 3989 result = DDI_INTR_CLAIMED; 3990 3991 BGE_DEBUG(("bge_intr($%p) ($%p) regval 0x%08x", arg1, arg2, regval)); 3992 3993 /* 3994 * Sync the status block and grab the flags-n-tag from it. 3995 * We count the number of interrupts where there doesn't 3996 * seem to have been a DMA update of the status block; if 3997 * it *has* been updated, the counter will be cleared in 3998 * the while() loop below ... 3999 */ 4000 bgep->missed_dmas += 1; 4001 bsp = DMA_VPTR(bgep->status_block); 4002 for (loop_cnt = 0; loop_cnt < bge_intr_max_loop; loop_cnt++) { 4003 if (bgep->bge_chip_state != BGE_CHIP_RUNNING) { 4004 /* 4005 * bge_chip_stop() may have freed dma area etc 4006 * while we were in this interrupt handler - 4007 * better not call bge_status_sync() 4008 */ 4009 (void) bge_check_acc_handle(bgep, 4010 bgep->io_handle); 4011 mutex_exit(bgep->genlock); 4012 return (DDI_INTR_CLAIMED); 4013 } 4014 retval = bge_status_sync(bgep, STATUS_FLAG_UPDATED, 4015 &flags); 4016 if (retval != DDI_FM_OK) { 4017 bgep->bge_dma_error = B_TRUE; 4018 goto chip_stop; 4019 } 4020 4021 if (!(flags & STATUS_FLAG_UPDATED)) 4022 break; 4023 4024 /* 4025 * Tell the chip that we're processing the interrupt 4026 */ 4027 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 4028 INTERRUPT_MBOX_DISABLE(flags)); 4029 if (bge_check_acc_handle(bgep, bgep->io_handle) != 4030 DDI_FM_OK) 4031 goto chip_stop; 4032 4033 /* 4034 * Drop the mutex while we: 4035 * Receive any newly-arrived packets 4036 * Recycle any newly-finished send buffers 4037 */ 4038 bgep->bge_intr_running = B_TRUE; 4039 mutex_exit(bgep->genlock); 4040 bge_receive(bgep, bsp); 4041 bge_recycle(bgep, bsp); 4042 mutex_enter(bgep->genlock); 4043 bgep->bge_intr_running = B_FALSE; 4044 4045 /* 4046 * Tell the chip we've finished processing, and 4047 * give it the tag that we got from the status 4048 * block earlier, so that it knows just how far 4049 * we've gone. If it's got more for us to do, 4050 * it will now update the status block and try 4051 * to assert an interrupt (but we've got the 4052 * #INTA blocked at present). If we see the 4053 * update, we'll loop around to do some more. 4054 * Eventually we'll get out of here ... 4055 */ 4056 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 4057 INTERRUPT_MBOX_ENABLE(flags)); 4058 bgep->missed_dmas = 0; 4059 } 4060 4061 /* 4062 * Check for exceptional conditions that we need to handle 4063 * 4064 * Link status changed 4065 * Status block not updated 4066 */ 4067 if (flags & STATUS_FLAG_LINK_CHANGED) 4068 bge_wake_factotum(bgep); 4069 4070 if (bgep->missed_dmas) { 4071 /* 4072 * Probably due to the internal status tag not 4073 * being reset. Force a status block update now; 4074 * this should ensure that we get an update and 4075 * a new interrupt. After that, we should be in 4076 * sync again ... 4077 */ 4078 BGE_REPORT((bgep, "interrupt: flags 0x%llx - " 4079 "not updated?", flags)); 4080 bgep->missed_updates++; 4081 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 4082 COALESCE_NOW); 4083 4084 if (bgep->missed_dmas >= bge_dma_miss_limit) { 4085 /* 4086 * If this happens multiple times in a row, 4087 * it means DMA is just not working. Maybe 4088 * the chip's failed, or maybe there's a 4089 * problem on the PCI bus or in the host-PCI 4090 * bridge (Tomatillo). 4091 * 4092 * At all events, we want to stop further 4093 * interrupts and let the recovery code take 4094 * over to see whether anything can be done 4095 * about it ... 4096 */ 4097 bge_fm_ereport(bgep, 4098 DDI_FM_DEVICE_BADINT_LIMIT); 4099 goto chip_stop; 4100 } 4101 } 4102 4103 /* 4104 * Reenable assertion of #INTA, unless there's a DMA fault 4105 */ 4106 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) { 4107 bge_reg_clr32(bgep, PCI_CONF_BGE_MHCR, 4108 MHCR_MASK_PCI_INT_OUTPUT); 4109 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != 4110 DDI_FM_OK) 4111 goto chip_stop; 4112 } 4113 4114 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4115 goto chip_stop; 4116 4117 mutex_exit(bgep->genlock); 4118 return (result); 4119 4120 chip_stop: 4121 #ifdef BGE_IPMI_ASF 4122 if (bgep->asf_enabled && bgep->asf_status == ASF_STAT_RUN) { 4123 /* 4124 * We must stop ASF heart beat before 4125 * bge_chip_stop(), otherwise some 4126 * computers (ex. IBM HS20 blade 4127 * server) may crash. 4128 */ 4129 bge_asf_update_status(bgep); 4130 bge_asf_stop_timer(bgep); 4131 bgep->asf_status = ASF_STAT_STOP; 4132 4133 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 4134 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 4135 } 4136 #endif 4137 bge_chip_stop(bgep, B_TRUE); 4138 (void) bge_check_acc_handle(bgep, bgep->io_handle); 4139 mutex_exit(bgep->genlock); 4140 return (result); 4141 } 4142 4143 /* 4144 * ========== Factotum, implemented as a softint handler ========== 4145 */ 4146 4147 #undef BGE_DBG 4148 #define BGE_DBG BGE_DBG_FACT /* debug flag for this code */ 4149 4150 static void bge_factotum_error_handler(bge_t *bgep); 4151 #pragma no_inline(bge_factotum_error_handler) 4152 4153 static void 4154 bge_factotum_error_handler(bge_t *bgep) 4155 { 4156 uint32_t flow; 4157 uint32_t rdma; 4158 uint32_t wdma; 4159 uint32_t tmac; 4160 uint32_t rmac; 4161 uint32_t rxrs; 4162 uint32_t txrs = 0; 4163 4164 ASSERT(mutex_owned(bgep->genlock)); 4165 4166 /* 4167 * Read all the registers that show the possible 4168 * reasons for the ERROR bit to be asserted 4169 */ 4170 flow = bge_reg_get32(bgep, FLOW_ATTN_REG); 4171 rdma = bge_reg_get32(bgep, READ_DMA_STATUS_REG); 4172 wdma = bge_reg_get32(bgep, WRITE_DMA_STATUS_REG); 4173 tmac = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 4174 rmac = bge_reg_get32(bgep, RECEIVE_MAC_STATUS_REG); 4175 rxrs = bge_reg_get32(bgep, RX_RISC_STATE_REG); 4176 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4177 txrs = bge_reg_get32(bgep, TX_RISC_STATE_REG); 4178 4179 BGE_DEBUG(("factotum($%p) flow 0x%x rdma 0x%x wdma 0x%x", 4180 (void *)bgep, flow, rdma, wdma)); 4181 BGE_DEBUG(("factotum($%p) tmac 0x%x rmac 0x%x rxrs 0x%08x txrs 0x%08x", 4182 (void *)bgep, tmac, rmac, rxrs, txrs)); 4183 4184 /* 4185 * For now, just clear all the errors ... 4186 */ 4187 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4188 bge_reg_put32(bgep, TX_RISC_STATE_REG, ~0); 4189 bge_reg_put32(bgep, RX_RISC_STATE_REG, ~0); 4190 bge_reg_put32(bgep, RECEIVE_MAC_STATUS_REG, ~0); 4191 bge_reg_put32(bgep, WRITE_DMA_STATUS_REG, ~0); 4192 bge_reg_put32(bgep, READ_DMA_STATUS_REG, ~0); 4193 bge_reg_put32(bgep, FLOW_ATTN_REG, ~0); 4194 } 4195 4196 /* 4197 * Handler for hardware link state change. 4198 * 4199 * When this routine is called, the hardware link state has changed 4200 * and the new state is reflected in the param_* variables. Here 4201 * we must update the softstate, reprogram the MAC to match, and 4202 * record the change in the log and/or on the console. 4203 */ 4204 static void bge_factotum_link_handler(bge_t *bgep); 4205 #pragma no_inline(bge_factotum_link_handler) 4206 4207 static void 4208 bge_factotum_link_handler(bge_t *bgep) 4209 { 4210 void (*logfn)(bge_t *bgep, const char *fmt, ...); 4211 const char *msg; 4212 hrtime_t deltat; 4213 4214 ASSERT(mutex_owned(bgep->genlock)); 4215 4216 /* 4217 * Update the s/w link_state 4218 */ 4219 if (bgep->param_link_up) 4220 bgep->link_state = LINK_STATE_UP; 4221 else 4222 bgep->link_state = LINK_STATE_DOWN; 4223 4224 /* 4225 * Reprogram the MAC modes to match 4226 */ 4227 bge_sync_mac_modes(bgep); 4228 4229 /* 4230 * Finally, we have to decide whether to write a message 4231 * on the console or only in the log. If the PHY has 4232 * been reprogrammed (at user request) "recently", then 4233 * the message only goes in the log. Otherwise it's an 4234 * "unexpected" event, and it goes on the console as well. 4235 */ 4236 deltat = bgep->phys_event_time - bgep->phys_write_time; 4237 if (deltat > BGE_LINK_SETTLE_TIME) 4238 msg = ""; 4239 else if (bgep->param_link_up) 4240 msg = bgep->link_up_msg; 4241 else 4242 msg = bgep->link_down_msg; 4243 4244 logfn = (msg == NULL || *msg == '\0') ? bge_notice : bge_log; 4245 (*logfn)(bgep, "link %s%s", bgep->link_mode_msg, msg); 4246 } 4247 4248 static boolean_t bge_factotum_link_check(bge_t *bgep, int *dma_state); 4249 #pragma no_inline(bge_factotum_link_check) 4250 4251 static boolean_t 4252 bge_factotum_link_check(bge_t *bgep, int *dma_state) 4253 { 4254 boolean_t check; 4255 uint64_t flags; 4256 uint32_t tmac_status; 4257 4258 ASSERT(mutex_owned(bgep->genlock)); 4259 4260 /* 4261 * Get & clear the writable status bits in the Tx status register 4262 * (some bits are write-1-to-clear, others are just readonly). 4263 */ 4264 tmac_status = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 4265 bge_reg_put32(bgep, TRANSMIT_MAC_STATUS_REG, tmac_status); 4266 4267 /* 4268 * Get & clear the ERROR and LINK_CHANGED bits from the status block 4269 */ 4270 *dma_state = bge_status_sync(bgep, STATUS_FLAG_ERROR | 4271 STATUS_FLAG_LINK_CHANGED, &flags); 4272 if (*dma_state != DDI_FM_OK) 4273 return (B_FALSE); 4274 4275 /* 4276 * Clear any errors flagged in the status block ... 4277 */ 4278 if (flags & STATUS_FLAG_ERROR) 4279 bge_factotum_error_handler(bgep); 4280 4281 /* 4282 * We need to check the link status if: 4283 * the status block says there's been a link change 4284 * or there's any discrepancy between the various 4285 * flags indicating the link state (link_state, 4286 * param_link_up, and the LINK STATE bit in the 4287 * Transmit MAC status register). 4288 */ 4289 check = (flags & STATUS_FLAG_LINK_CHANGED) != 0; 4290 switch (bgep->link_state) { 4291 case LINK_STATE_UP: 4292 check |= (bgep->param_link_up == B_FALSE); 4293 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) == 0); 4294 break; 4295 4296 case LINK_STATE_DOWN: 4297 check |= (bgep->param_link_up != B_FALSE); 4298 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) != 0); 4299 break; 4300 4301 default: 4302 check = B_TRUE; 4303 break; 4304 } 4305 4306 /* 4307 * If <check> is false, we're sure the link hasn't changed. 4308 * If true, however, it's not yet definitive; we have to call 4309 * bge_phys_check() to determine whether the link has settled 4310 * into a new state yet ... and if it has, then call the link 4311 * state change handler.But when the chip is 5700 in Dell 6650 4312 * ,even if check is false, the link may have changed.So we 4313 * have to call bge_phys_check() to determine the link state. 4314 */ 4315 if (check || bgep->chipid.device == DEVICE_ID_5700) { 4316 check = bge_phys_check(bgep); 4317 if (check) 4318 bge_factotum_link_handler(bgep); 4319 } 4320 4321 return (check); 4322 } 4323 4324 /* 4325 * Factotum routine to check for Tx stall, using the 'watchdog' counter 4326 */ 4327 static boolean_t bge_factotum_stall_check(bge_t *bgep); 4328 #pragma no_inline(bge_factotum_stall_check) 4329 4330 static boolean_t 4331 bge_factotum_stall_check(bge_t *bgep) 4332 { 4333 uint32_t dogval; 4334 4335 ASSERT(mutex_owned(bgep->genlock)); 4336 4337 /* 4338 * Specific check for Tx stall ... 4339 * 4340 * The 'watchdog' counter is incremented whenever a packet 4341 * is queued, reset to 1 when some (but not all) buffers 4342 * are reclaimed, reset to 0 (disabled) when all buffers 4343 * are reclaimed, and shifted left here. If it exceeds the 4344 * threshold value, the chip is assumed to have stalled and 4345 * is put into the ERROR state. The factotum will then reset 4346 * it on the next pass. 4347 * 4348 * All of which should ensure that we don't get into a state 4349 * where packets are left pending indefinitely! 4350 */ 4351 dogval = bge_atomic_shl32(&bgep->watchdog, 1); 4352 if (dogval < bge_watchdog_count) 4353 return (B_FALSE); 4354 4355 #if !defined(BGE_NETCONSOLE) 4356 BGE_REPORT((bgep, "Tx stall detected, watchdog code 0x%x", dogval)); 4357 #endif 4358 bge_fm_ereport(bgep, DDI_FM_DEVICE_STALL); 4359 return (B_TRUE); 4360 } 4361 4362 /* 4363 * The factotum is woken up when there's something to do that we'd rather 4364 * not do from inside a hardware interrupt handler or high-level cyclic. 4365 * Its two main tasks are: 4366 * reset & restart the chip after an error 4367 * check the link status whenever necessary 4368 */ 4369 uint_t bge_chip_factotum(caddr_t arg); 4370 #pragma no_inline(bge_chip_factotum) 4371 4372 uint_t 4373 bge_chip_factotum(caddr_t arg) 4374 { 4375 bge_t *bgep; 4376 uint_t result; 4377 boolean_t error; 4378 boolean_t linkchg; 4379 int dma_state; 4380 4381 bgep = (bge_t *)arg; 4382 4383 BGE_TRACE(("bge_chip_factotum($%p)", (void *)bgep)); 4384 4385 mutex_enter(bgep->softintrlock); 4386 if (bgep->factotum_flag == 0) { 4387 mutex_exit(bgep->softintrlock); 4388 return (DDI_INTR_UNCLAIMED); 4389 } 4390 bgep->factotum_flag = 0; 4391 mutex_exit(bgep->softintrlock); 4392 4393 result = DDI_INTR_CLAIMED; 4394 error = B_FALSE; 4395 linkchg = B_FALSE; 4396 4397 mutex_enter(bgep->genlock); 4398 switch (bgep->bge_chip_state) { 4399 default: 4400 break; 4401 4402 case BGE_CHIP_RUNNING: 4403 linkchg = bge_factotum_link_check(bgep, &dma_state); 4404 error = bge_factotum_stall_check(bgep); 4405 if (dma_state != DDI_FM_OK) { 4406 bgep->bge_dma_error = B_TRUE; 4407 error = B_TRUE; 4408 } 4409 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4410 error = B_TRUE; 4411 if (error) 4412 bgep->bge_chip_state = BGE_CHIP_ERROR; 4413 break; 4414 4415 case BGE_CHIP_ERROR: 4416 error = B_TRUE; 4417 break; 4418 4419 case BGE_CHIP_FAULT: 4420 /* 4421 * Fault detected, time to reset ... 4422 */ 4423 if (bge_autorecover) { 4424 if (!(bgep->progress & PROGRESS_BUFS)) { 4425 /* 4426 * if we can't allocate the ring buffers, 4427 * try later 4428 */ 4429 if (bge_alloc_bufs(bgep) != DDI_SUCCESS) { 4430 mutex_exit(bgep->genlock); 4431 return (result); 4432 } 4433 bgep->progress |= PROGRESS_BUFS; 4434 } 4435 if (!(bgep->progress & PROGRESS_INTR)) { 4436 bge_init_rings(bgep); 4437 bge_intr_enable(bgep); 4438 bgep->progress |= PROGRESS_INTR; 4439 } 4440 if (!(bgep->progress & PROGRESS_KSTATS)) { 4441 bge_init_kstats(bgep, 4442 ddi_get_instance(bgep->devinfo)); 4443 bgep->progress |= PROGRESS_KSTATS; 4444 } 4445 4446 BGE_REPORT((bgep, "automatic recovery activated")); 4447 4448 if (bge_restart(bgep, B_FALSE) != DDI_SUCCESS) { 4449 bgep->bge_chip_state = BGE_CHIP_ERROR; 4450 error = B_TRUE; 4451 } 4452 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != 4453 DDI_FM_OK) { 4454 bgep->bge_chip_state = BGE_CHIP_ERROR; 4455 error = B_TRUE; 4456 } 4457 if (bge_check_acc_handle(bgep, bgep->io_handle) != 4458 DDI_FM_OK) { 4459 bgep->bge_chip_state = BGE_CHIP_ERROR; 4460 error = B_TRUE; 4461 } 4462 if (error == B_FALSE) { 4463 #ifdef BGE_IPMI_ASF 4464 if (bgep->asf_enabled && 4465 bgep->asf_status != ASF_STAT_RUN) { 4466 bgep->asf_timeout_id = timeout( 4467 bge_asf_heartbeat, (void *)bgep, 4468 drv_usectohz( 4469 BGE_ASF_HEARTBEAT_INTERVAL)); 4470 bgep->asf_status = ASF_STAT_RUN; 4471 } 4472 #endif 4473 ddi_fm_service_impact(bgep->devinfo, 4474 DDI_SERVICE_RESTORED); 4475 } 4476 } 4477 break; 4478 } 4479 4480 4481 /* 4482 * If an error is detected, stop the chip now, marking it as 4483 * faulty, so that it will be reset next time through ... 4484 * 4485 * Note that if intr_running is set, then bge_intr() has dropped 4486 * genlock to call bge_receive/bge_recycle. Can't stop the chip at 4487 * this point so have to wait until the next time the factotum runs. 4488 */ 4489 if (error && !bgep->bge_intr_running) { 4490 #ifdef BGE_IPMI_ASF 4491 if (bgep->asf_enabled && (bgep->asf_status == ASF_STAT_RUN)) { 4492 /* 4493 * We must stop ASF heart beat before bge_chip_stop(), 4494 * otherwise some computers (ex. IBM HS20 blade server) 4495 * may crash. 4496 */ 4497 bge_asf_update_status(bgep); 4498 bge_asf_stop_timer(bgep); 4499 bgep->asf_status = ASF_STAT_STOP; 4500 4501 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 4502 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 4503 } 4504 #endif 4505 bge_chip_stop(bgep, B_TRUE); 4506 (void) bge_check_acc_handle(bgep, bgep->io_handle); 4507 } 4508 mutex_exit(bgep->genlock); 4509 4510 /* 4511 * If the link state changed, tell the world about it. 4512 * Note: can't do this while still holding the mutex. 4513 */ 4514 if (linkchg) 4515 mac_link_update(bgep->mh, bgep->link_state); 4516 4517 return (result); 4518 } 4519 4520 /* 4521 * High-level cyclic handler 4522 * 4523 * This routine schedules a (low-level) softint callback to the 4524 * factotum, and prods the chip to update the status block (which 4525 * will cause a hardware interrupt when complete). 4526 */ 4527 void bge_chip_cyclic(void *arg); 4528 #pragma no_inline(bge_chip_cyclic) 4529 4530 void 4531 bge_chip_cyclic(void *arg) 4532 { 4533 bge_t *bgep; 4534 4535 bgep = arg; 4536 4537 switch (bgep->bge_chip_state) { 4538 default: 4539 return; 4540 4541 case BGE_CHIP_RUNNING: 4542 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, COALESCE_NOW); 4543 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4544 ddi_fm_service_impact(bgep->devinfo, 4545 DDI_SERVICE_UNAFFECTED); 4546 break; 4547 4548 case BGE_CHIP_FAULT: 4549 case BGE_CHIP_ERROR: 4550 break; 4551 } 4552 4553 bge_wake_factotum(bgep); 4554 } 4555 4556 4557 /* 4558 * ========== Ioctl subfunctions ========== 4559 */ 4560 4561 #undef BGE_DBG 4562 #define BGE_DBG BGE_DBG_PPIO /* debug flag for this code */ 4563 4564 #if BGE_DEBUGGING || BGE_DO_PPIO 4565 4566 static void bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 4567 #pragma no_inline(bge_chip_peek_cfg) 4568 4569 static void 4570 bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 4571 { 4572 uint64_t regval; 4573 uint64_t regno; 4574 4575 BGE_TRACE(("bge_chip_peek_cfg($%p, $%p)", 4576 (void *)bgep, (void *)ppd)); 4577 4578 regno = ppd->pp_acc_offset; 4579 4580 switch (ppd->pp_acc_size) { 4581 case 1: 4582 regval = pci_config_get8(bgep->cfg_handle, regno); 4583 break; 4584 4585 case 2: 4586 regval = pci_config_get16(bgep->cfg_handle, regno); 4587 break; 4588 4589 case 4: 4590 regval = pci_config_get32(bgep->cfg_handle, regno); 4591 break; 4592 4593 case 8: 4594 regval = pci_config_get64(bgep->cfg_handle, regno); 4595 break; 4596 } 4597 4598 ppd->pp_acc_data = regval; 4599 } 4600 4601 static void bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 4602 #pragma no_inline(bge_chip_poke_cfg) 4603 4604 static void 4605 bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 4606 { 4607 uint64_t regval; 4608 uint64_t regno; 4609 4610 BGE_TRACE(("bge_chip_poke_cfg($%p, $%p)", 4611 (void *)bgep, (void *)ppd)); 4612 4613 regno = ppd->pp_acc_offset; 4614 regval = ppd->pp_acc_data; 4615 4616 switch (ppd->pp_acc_size) { 4617 case 1: 4618 pci_config_put8(bgep->cfg_handle, regno, regval); 4619 break; 4620 4621 case 2: 4622 pci_config_put16(bgep->cfg_handle, regno, regval); 4623 break; 4624 4625 case 4: 4626 pci_config_put32(bgep->cfg_handle, regno, regval); 4627 break; 4628 4629 case 8: 4630 pci_config_put64(bgep->cfg_handle, regno, regval); 4631 break; 4632 } 4633 } 4634 4635 static void bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd); 4636 #pragma no_inline(bge_chip_peek_reg) 4637 4638 static void 4639 bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd) 4640 { 4641 uint64_t regval; 4642 void *regaddr; 4643 4644 BGE_TRACE(("bge_chip_peek_reg($%p, $%p)", 4645 (void *)bgep, (void *)ppd)); 4646 4647 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 4648 4649 switch (ppd->pp_acc_size) { 4650 case 1: 4651 regval = ddi_get8(bgep->io_handle, regaddr); 4652 break; 4653 4654 case 2: 4655 regval = ddi_get16(bgep->io_handle, regaddr); 4656 break; 4657 4658 case 4: 4659 regval = ddi_get32(bgep->io_handle, regaddr); 4660 break; 4661 4662 case 8: 4663 regval = ddi_get64(bgep->io_handle, regaddr); 4664 break; 4665 } 4666 4667 ppd->pp_acc_data = regval; 4668 } 4669 4670 static void bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd); 4671 #pragma no_inline(bge_chip_peek_reg) 4672 4673 static void 4674 bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd) 4675 { 4676 uint64_t regval; 4677 void *regaddr; 4678 4679 BGE_TRACE(("bge_chip_poke_reg($%p, $%p)", 4680 (void *)bgep, (void *)ppd)); 4681 4682 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 4683 regval = ppd->pp_acc_data; 4684 4685 switch (ppd->pp_acc_size) { 4686 case 1: 4687 ddi_put8(bgep->io_handle, regaddr, regval); 4688 break; 4689 4690 case 2: 4691 ddi_put16(bgep->io_handle, regaddr, regval); 4692 break; 4693 4694 case 4: 4695 ddi_put32(bgep->io_handle, regaddr, regval); 4696 break; 4697 4698 case 8: 4699 ddi_put64(bgep->io_handle, regaddr, regval); 4700 break; 4701 } 4702 BGE_PCICHK(bgep); 4703 } 4704 4705 static void bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd); 4706 #pragma no_inline(bge_chip_peek_nic) 4707 4708 static void 4709 bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd) 4710 { 4711 uint64_t regoff; 4712 uint64_t regval; 4713 void *regaddr; 4714 4715 BGE_TRACE(("bge_chip_peek_nic($%p, $%p)", 4716 (void *)bgep, (void *)ppd)); 4717 4718 regoff = ppd->pp_acc_offset; 4719 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 4720 regoff &= MWBAR_GRANULE_MASK; 4721 regoff += NIC_MEM_WINDOW_OFFSET; 4722 regaddr = PIO_ADDR(bgep, regoff); 4723 4724 switch (ppd->pp_acc_size) { 4725 case 1: 4726 regval = ddi_get8(bgep->io_handle, regaddr); 4727 break; 4728 4729 case 2: 4730 regval = ddi_get16(bgep->io_handle, regaddr); 4731 break; 4732 4733 case 4: 4734 regval = ddi_get32(bgep->io_handle, regaddr); 4735 break; 4736 4737 case 8: 4738 regval = ddi_get64(bgep->io_handle, regaddr); 4739 break; 4740 } 4741 4742 ppd->pp_acc_data = regval; 4743 } 4744 4745 static void bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd); 4746 #pragma no_inline(bge_chip_poke_nic) 4747 4748 static void 4749 bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd) 4750 { 4751 uint64_t regoff; 4752 uint64_t regval; 4753 void *regaddr; 4754 4755 BGE_TRACE(("bge_chip_poke_nic($%p, $%p)", 4756 (void *)bgep, (void *)ppd)); 4757 4758 regoff = ppd->pp_acc_offset; 4759 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 4760 regoff &= MWBAR_GRANULE_MASK; 4761 regoff += NIC_MEM_WINDOW_OFFSET; 4762 regaddr = PIO_ADDR(bgep, regoff); 4763 regval = ppd->pp_acc_data; 4764 4765 switch (ppd->pp_acc_size) { 4766 case 1: 4767 ddi_put8(bgep->io_handle, regaddr, regval); 4768 break; 4769 4770 case 2: 4771 ddi_put16(bgep->io_handle, regaddr, regval); 4772 break; 4773 4774 case 4: 4775 ddi_put32(bgep->io_handle, regaddr, regval); 4776 break; 4777 4778 case 8: 4779 ddi_put64(bgep->io_handle, regaddr, regval); 4780 break; 4781 } 4782 BGE_PCICHK(bgep); 4783 } 4784 4785 static void bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd); 4786 #pragma no_inline(bge_chip_peek_mii) 4787 4788 static void 4789 bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd) 4790 { 4791 BGE_TRACE(("bge_chip_peek_mii($%p, $%p)", 4792 (void *)bgep, (void *)ppd)); 4793 4794 ppd->pp_acc_data = bge_mii_get16(bgep, ppd->pp_acc_offset/2); 4795 } 4796 4797 static void bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd); 4798 #pragma no_inline(bge_chip_poke_mii) 4799 4800 static void 4801 bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd) 4802 { 4803 BGE_TRACE(("bge_chip_poke_mii($%p, $%p)", 4804 (void *)bgep, (void *)ppd)); 4805 4806 bge_mii_put16(bgep, ppd->pp_acc_offset/2, ppd->pp_acc_data); 4807 } 4808 4809 #if BGE_SEE_IO32 4810 4811 static void bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 4812 #pragma no_inline(bge_chip_peek_seeprom) 4813 4814 static void 4815 bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 4816 { 4817 uint32_t data; 4818 int err; 4819 4820 BGE_TRACE(("bge_chip_peek_seeprom($%p, $%p)", 4821 (void *)bgep, (void *)ppd)); 4822 4823 err = bge_nvmem_rw32(bgep, BGE_SEE_READ, ppd->pp_acc_offset, &data); 4824 ppd->pp_acc_data = err ? ~0ull : data; 4825 } 4826 4827 static void bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 4828 #pragma no_inline(bge_chip_poke_seeprom) 4829 4830 static void 4831 bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 4832 { 4833 uint32_t data; 4834 4835 BGE_TRACE(("bge_chip_poke_seeprom($%p, $%p)", 4836 (void *)bgep, (void *)ppd)); 4837 4838 data = ppd->pp_acc_data; 4839 (void) bge_nvmem_rw32(bgep, BGE_SEE_WRITE, ppd->pp_acc_offset, &data); 4840 } 4841 #endif /* BGE_SEE_IO32 */ 4842 4843 #if BGE_FLASH_IO32 4844 4845 static void bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd); 4846 #pragma no_inline(bge_chip_peek_flash) 4847 4848 static void 4849 bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd) 4850 { 4851 uint32_t data; 4852 int err; 4853 4854 BGE_TRACE(("bge_chip_peek_flash($%p, $%p)", 4855 (void *)bgep, (void *)ppd)); 4856 4857 err = bge_nvmem_rw32(bgep, BGE_FLASH_READ, ppd->pp_acc_offset, &data); 4858 ppd->pp_acc_data = err ? ~0ull : data; 4859 } 4860 4861 static void bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd); 4862 #pragma no_inline(bge_chip_poke_flash) 4863 4864 static void 4865 bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd) 4866 { 4867 uint32_t data; 4868 4869 BGE_TRACE(("bge_chip_poke_flash($%p, $%p)", 4870 (void *)bgep, (void *)ppd)); 4871 4872 data = ppd->pp_acc_data; 4873 (void) bge_nvmem_rw32(bgep, BGE_FLASH_WRITE, 4874 ppd->pp_acc_offset, &data); 4875 } 4876 #endif /* BGE_FLASH_IO32 */ 4877 4878 static void bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd); 4879 #pragma no_inline(bge_chip_peek_mem) 4880 4881 static void 4882 bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd) 4883 { 4884 uint64_t regval; 4885 void *vaddr; 4886 4887 BGE_TRACE(("bge_chip_peek_bge($%p, $%p)", 4888 (void *)bgep, (void *)ppd)); 4889 4890 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4891 4892 switch (ppd->pp_acc_size) { 4893 case 1: 4894 regval = *(uint8_t *)vaddr; 4895 break; 4896 4897 case 2: 4898 regval = *(uint16_t *)vaddr; 4899 break; 4900 4901 case 4: 4902 regval = *(uint32_t *)vaddr; 4903 break; 4904 4905 case 8: 4906 regval = *(uint64_t *)vaddr; 4907 break; 4908 } 4909 4910 BGE_DEBUG(("bge_chip_peek_mem($%p, $%p) peeked 0x%llx from $%p", 4911 (void *)bgep, (void *)ppd, regval, vaddr)); 4912 4913 ppd->pp_acc_data = regval; 4914 } 4915 4916 static void bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd); 4917 #pragma no_inline(bge_chip_poke_mem) 4918 4919 static void 4920 bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd) 4921 { 4922 uint64_t regval; 4923 void *vaddr; 4924 4925 BGE_TRACE(("bge_chip_poke_mem($%p, $%p)", 4926 (void *)bgep, (void *)ppd)); 4927 4928 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4929 regval = ppd->pp_acc_data; 4930 4931 BGE_DEBUG(("bge_chip_poke_mem($%p, $%p) poking 0x%llx at $%p", 4932 (void *)bgep, (void *)ppd, regval, vaddr)); 4933 4934 switch (ppd->pp_acc_size) { 4935 case 1: 4936 *(uint8_t *)vaddr = (uint8_t)regval; 4937 break; 4938 4939 case 2: 4940 *(uint16_t *)vaddr = (uint16_t)regval; 4941 break; 4942 4943 case 4: 4944 *(uint32_t *)vaddr = (uint32_t)regval; 4945 break; 4946 4947 case 8: 4948 *(uint64_t *)vaddr = (uint64_t)regval; 4949 break; 4950 } 4951 } 4952 4953 static enum ioc_reply bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 4954 struct iocblk *iocp); 4955 #pragma no_inline(bge_pp_ioctl) 4956 4957 static enum ioc_reply 4958 bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 4959 { 4960 void (*ppfn)(bge_t *bgep, bge_peekpoke_t *ppd); 4961 bge_peekpoke_t *ppd; 4962 dma_area_t *areap; 4963 uint64_t sizemask; 4964 uint64_t mem_va; 4965 uint64_t maxoff; 4966 boolean_t peek; 4967 4968 switch (cmd) { 4969 default: 4970 /* NOTREACHED */ 4971 bge_error(bgep, "bge_pp_ioctl: invalid cmd 0x%x", cmd); 4972 return (IOC_INVAL); 4973 4974 case BGE_PEEK: 4975 peek = B_TRUE; 4976 break; 4977 4978 case BGE_POKE: 4979 peek = B_FALSE; 4980 break; 4981 } 4982 4983 /* 4984 * Validate format of ioctl 4985 */ 4986 if (iocp->ioc_count != sizeof (bge_peekpoke_t)) 4987 return (IOC_INVAL); 4988 if (mp->b_cont == NULL) 4989 return (IOC_INVAL); 4990 ppd = (bge_peekpoke_t *)mp->b_cont->b_rptr; 4991 4992 /* 4993 * Validate request parameters 4994 */ 4995 switch (ppd->pp_acc_space) { 4996 default: 4997 return (IOC_INVAL); 4998 4999 case BGE_PP_SPACE_CFG: 5000 /* 5001 * Config space 5002 */ 5003 sizemask = 8|4|2|1; 5004 mem_va = 0; 5005 maxoff = PCI_CONF_HDR_SIZE; 5006 ppfn = peek ? bge_chip_peek_cfg : bge_chip_poke_cfg; 5007 break; 5008 5009 case BGE_PP_SPACE_REG: 5010 /* 5011 * Memory-mapped I/O space 5012 */ 5013 sizemask = 8|4|2|1; 5014 mem_va = 0; 5015 maxoff = RIAAR_REGISTER_MAX; 5016 ppfn = peek ? bge_chip_peek_reg : bge_chip_poke_reg; 5017 break; 5018 5019 case BGE_PP_SPACE_NIC: 5020 /* 5021 * NIC on-chip memory 5022 */ 5023 sizemask = 8|4|2|1; 5024 mem_va = 0; 5025 maxoff = MWBAR_ONCHIP_MAX; 5026 ppfn = peek ? bge_chip_peek_nic : bge_chip_poke_nic; 5027 break; 5028 5029 case BGE_PP_SPACE_MII: 5030 /* 5031 * PHY's MII registers 5032 * NB: all PHY registers are two bytes, but the 5033 * addresses increment in ones (word addressing). 5034 * So we scale the address here, then undo the 5035 * transformation inside the peek/poke functions. 5036 */ 5037 ppd->pp_acc_offset *= 2; 5038 sizemask = 2; 5039 mem_va = 0; 5040 maxoff = (MII_MAXREG+1)*2; 5041 ppfn = peek ? bge_chip_peek_mii : bge_chip_poke_mii; 5042 break; 5043 5044 #if BGE_SEE_IO32 5045 case BGE_PP_SPACE_SEEPROM: 5046 /* 5047 * Attached SEEPROM(s), if any. 5048 * NB: we use the high-order bits of the 'address' as 5049 * a device select to accommodate multiple SEEPROMS, 5050 * If each one is the maximum size (64kbytes), this 5051 * makes them appear contiguous. Otherwise, there may 5052 * be holes in the mapping. ENxS doesn't have any 5053 * SEEPROMs anyway ... 5054 */ 5055 sizemask = 4; 5056 mem_va = 0; 5057 maxoff = SEEPROM_DEV_AND_ADDR_MASK; 5058 ppfn = peek ? bge_chip_peek_seeprom : bge_chip_poke_seeprom; 5059 break; 5060 #endif /* BGE_SEE_IO32 */ 5061 5062 #if BGE_FLASH_IO32 5063 case BGE_PP_SPACE_FLASH: 5064 /* 5065 * Attached Flash device (if any); a maximum of one device 5066 * is currently supported. But it can be up to 1MB (unlike 5067 * the 64k limit on SEEPROMs) so why would you need more ;-) 5068 */ 5069 sizemask = 4; 5070 mem_va = 0; 5071 maxoff = NVM_FLASH_ADDR_MASK; 5072 ppfn = peek ? bge_chip_peek_flash : bge_chip_poke_flash; 5073 break; 5074 #endif /* BGE_FLASH_IO32 */ 5075 5076 case BGE_PP_SPACE_BGE: 5077 /* 5078 * BGE data structure! 5079 */ 5080 sizemask = 8|4|2|1; 5081 mem_va = (uintptr_t)bgep; 5082 maxoff = sizeof (*bgep); 5083 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 5084 break; 5085 5086 case BGE_PP_SPACE_STATUS: 5087 case BGE_PP_SPACE_STATISTICS: 5088 case BGE_PP_SPACE_TXDESC: 5089 case BGE_PP_SPACE_TXBUFF: 5090 case BGE_PP_SPACE_RXDESC: 5091 case BGE_PP_SPACE_RXBUFF: 5092 /* 5093 * Various DMA_AREAs 5094 */ 5095 switch (ppd->pp_acc_space) { 5096 case BGE_PP_SPACE_TXDESC: 5097 areap = &bgep->tx_desc; 5098 break; 5099 case BGE_PP_SPACE_TXBUFF: 5100 areap = &bgep->tx_buff[0]; 5101 break; 5102 case BGE_PP_SPACE_RXDESC: 5103 areap = &bgep->rx_desc[0]; 5104 break; 5105 case BGE_PP_SPACE_RXBUFF: 5106 areap = &bgep->rx_buff[0]; 5107 break; 5108 case BGE_PP_SPACE_STATUS: 5109 areap = &bgep->status_block; 5110 break; 5111 case BGE_PP_SPACE_STATISTICS: 5112 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 5113 areap = &bgep->statistics; 5114 break; 5115 } 5116 5117 sizemask = 8|4|2|1; 5118 mem_va = (uintptr_t)areap->mem_va; 5119 maxoff = areap->alength; 5120 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 5121 break; 5122 } 5123 5124 switch (ppd->pp_acc_size) { 5125 default: 5126 return (IOC_INVAL); 5127 5128 case 8: 5129 case 4: 5130 case 2: 5131 case 1: 5132 if ((ppd->pp_acc_size & sizemask) == 0) 5133 return (IOC_INVAL); 5134 break; 5135 } 5136 5137 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 5138 return (IOC_INVAL); 5139 5140 if (ppd->pp_acc_offset >= maxoff) 5141 return (IOC_INVAL); 5142 5143 if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff) 5144 return (IOC_INVAL); 5145 5146 /* 5147 * All OK - go do it! 5148 */ 5149 ppd->pp_acc_offset += mem_va; 5150 (*ppfn)(bgep, ppd); 5151 return (peek ? IOC_REPLY : IOC_ACK); 5152 } 5153 5154 static enum ioc_reply bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5155 struct iocblk *iocp); 5156 #pragma no_inline(bge_diag_ioctl) 5157 5158 static enum ioc_reply 5159 bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5160 { 5161 ASSERT(mutex_owned(bgep->genlock)); 5162 5163 switch (cmd) { 5164 default: 5165 /* NOTREACHED */ 5166 bge_error(bgep, "bge_diag_ioctl: invalid cmd 0x%x", cmd); 5167 return (IOC_INVAL); 5168 5169 case BGE_DIAG: 5170 /* 5171 * Currently a no-op 5172 */ 5173 return (IOC_ACK); 5174 5175 case BGE_PEEK: 5176 case BGE_POKE: 5177 return (bge_pp_ioctl(bgep, cmd, mp, iocp)); 5178 5179 case BGE_PHY_RESET: 5180 return (IOC_RESTART_ACK); 5181 5182 case BGE_SOFT_RESET: 5183 case BGE_HARD_RESET: 5184 /* 5185 * Reset and reinitialise the 570x hardware 5186 */ 5187 bgep->bge_chip_state = BGE_CHIP_FAULT; 5188 ddi_trigger_softintr(bgep->factotum_id); 5189 (void) bge_restart(bgep, cmd == BGE_HARD_RESET); 5190 return (IOC_ACK); 5191 } 5192 5193 /* NOTREACHED */ 5194 } 5195 5196 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 5197 5198 static enum ioc_reply bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5199 struct iocblk *iocp); 5200 #pragma no_inline(bge_mii_ioctl) 5201 5202 static enum ioc_reply 5203 bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5204 { 5205 struct bge_mii_rw *miirwp; 5206 5207 /* 5208 * Validate format of ioctl 5209 */ 5210 if (iocp->ioc_count != sizeof (struct bge_mii_rw)) 5211 return (IOC_INVAL); 5212 if (mp->b_cont == NULL) 5213 return (IOC_INVAL); 5214 miirwp = (struct bge_mii_rw *)mp->b_cont->b_rptr; 5215 5216 /* 5217 * Validate request parameters ... 5218 */ 5219 if (miirwp->mii_reg > MII_MAXREG) 5220 return (IOC_INVAL); 5221 5222 switch (cmd) { 5223 default: 5224 /* NOTREACHED */ 5225 bge_error(bgep, "bge_mii_ioctl: invalid cmd 0x%x", cmd); 5226 return (IOC_INVAL); 5227 5228 case BGE_MII_READ: 5229 miirwp->mii_data = bge_mii_get16(bgep, miirwp->mii_reg); 5230 return (IOC_REPLY); 5231 5232 case BGE_MII_WRITE: 5233 bge_mii_put16(bgep, miirwp->mii_reg, miirwp->mii_data); 5234 return (IOC_ACK); 5235 } 5236 5237 /* NOTREACHED */ 5238 } 5239 5240 #if BGE_SEE_IO32 5241 5242 static enum ioc_reply bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5243 struct iocblk *iocp); 5244 #pragma no_inline(bge_see_ioctl) 5245 5246 static enum ioc_reply 5247 bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5248 { 5249 struct bge_see_rw *seerwp; 5250 5251 /* 5252 * Validate format of ioctl 5253 */ 5254 if (iocp->ioc_count != sizeof (struct bge_see_rw)) 5255 return (IOC_INVAL); 5256 if (mp->b_cont == NULL) 5257 return (IOC_INVAL); 5258 seerwp = (struct bge_see_rw *)mp->b_cont->b_rptr; 5259 5260 /* 5261 * Validate request parameters ... 5262 */ 5263 if (seerwp->see_addr & ~SEEPROM_DEV_AND_ADDR_MASK) 5264 return (IOC_INVAL); 5265 5266 switch (cmd) { 5267 default: 5268 /* NOTREACHED */ 5269 bge_error(bgep, "bge_see_ioctl: invalid cmd 0x%x", cmd); 5270 return (IOC_INVAL); 5271 5272 case BGE_SEE_READ: 5273 case BGE_SEE_WRITE: 5274 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 5275 seerwp->see_addr, &seerwp->see_data); 5276 return (IOC_REPLY); 5277 } 5278 5279 /* NOTREACHED */ 5280 } 5281 5282 #endif /* BGE_SEE_IO32 */ 5283 5284 #if BGE_FLASH_IO32 5285 5286 static enum ioc_reply bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5287 struct iocblk *iocp); 5288 #pragma no_inline(bge_flash_ioctl) 5289 5290 static enum ioc_reply 5291 bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5292 { 5293 struct bge_flash_rw *flashrwp; 5294 5295 /* 5296 * Validate format of ioctl 5297 */ 5298 if (iocp->ioc_count != sizeof (struct bge_flash_rw)) 5299 return (IOC_INVAL); 5300 if (mp->b_cont == NULL) 5301 return (IOC_INVAL); 5302 flashrwp = (struct bge_flash_rw *)mp->b_cont->b_rptr; 5303 5304 /* 5305 * Validate request parameters ... 5306 */ 5307 if (flashrwp->flash_addr & ~NVM_FLASH_ADDR_MASK) 5308 return (IOC_INVAL); 5309 5310 switch (cmd) { 5311 default: 5312 /* NOTREACHED */ 5313 bge_error(bgep, "bge_flash_ioctl: invalid cmd 0x%x", cmd); 5314 return (IOC_INVAL); 5315 5316 case BGE_FLASH_READ: 5317 case BGE_FLASH_WRITE: 5318 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 5319 flashrwp->flash_addr, &flashrwp->flash_data); 5320 return (IOC_REPLY); 5321 } 5322 5323 /* NOTREACHED */ 5324 } 5325 5326 #endif /* BGE_FLASH_IO32 */ 5327 5328 enum ioc_reply bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, 5329 struct iocblk *iocp); 5330 #pragma no_inline(bge_chip_ioctl) 5331 5332 enum ioc_reply 5333 bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 5334 { 5335 int cmd; 5336 5337 BGE_TRACE(("bge_chip_ioctl($%p, $%p, $%p, $%p)", 5338 (void *)bgep, (void *)wq, (void *)mp, (void *)iocp)); 5339 5340 ASSERT(mutex_owned(bgep->genlock)); 5341 5342 cmd = iocp->ioc_cmd; 5343 switch (cmd) { 5344 default: 5345 /* NOTREACHED */ 5346 bge_error(bgep, "bge_chip_ioctl: invalid cmd 0x%x", cmd); 5347 return (IOC_INVAL); 5348 5349 case BGE_DIAG: 5350 case BGE_PEEK: 5351 case BGE_POKE: 5352 case BGE_PHY_RESET: 5353 case BGE_SOFT_RESET: 5354 case BGE_HARD_RESET: 5355 #if BGE_DEBUGGING || BGE_DO_PPIO 5356 return (bge_diag_ioctl(bgep, cmd, mp, iocp)); 5357 #else 5358 return (IOC_INVAL); 5359 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 5360 5361 case BGE_MII_READ: 5362 case BGE_MII_WRITE: 5363 return (bge_mii_ioctl(bgep, cmd, mp, iocp)); 5364 5365 #if BGE_SEE_IO32 5366 case BGE_SEE_READ: 5367 case BGE_SEE_WRITE: 5368 return (bge_see_ioctl(bgep, cmd, mp, iocp)); 5369 #endif /* BGE_SEE_IO32 */ 5370 5371 #if BGE_FLASH_IO32 5372 case BGE_FLASH_READ: 5373 case BGE_FLASH_WRITE: 5374 return (bge_flash_ioctl(bgep, cmd, mp, iocp)); 5375 #endif /* BGE_FLASH_IO32 */ 5376 } 5377 5378 /* NOTREACHED */ 5379 } 5380 5381 void 5382 bge_chip_blank(void *arg, time_t ticks, uint_t count) 5383 { 5384 bge_t *bgep = arg; 5385 5386 mutex_enter(bgep->genlock); 5387 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, ticks); 5388 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, count); 5389 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5390 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 5391 mutex_exit(bgep->genlock); 5392 } 5393 5394 #ifdef BGE_IPMI_ASF 5395 5396 uint32_t 5397 bge_nic_read32(bge_t *bgep, bge_regno_t addr) 5398 { 5399 uint32_t data; 5400 5401 #ifndef __sparc 5402 if (!bgep->asf_wordswapped) { 5403 /* a workaround word swap error */ 5404 if (addr & 4) 5405 addr = addr - 4; 5406 else 5407 addr = addr + 4; 5408 } 5409 #endif 5410 5411 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr); 5412 data = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR); 5413 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0); 5414 5415 data = LE_32(data); 5416 return (data); 5417 } 5418 5419 void 5420 bge_asf_update_status(bge_t *bgep) 5421 { 5422 uint32_t event; 5423 5424 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_ALIVE); 5425 bge_nic_put32(bgep, BGE_CMD_LENGTH_MAILBOX, 4); 5426 bge_nic_put32(bgep, BGE_CMD_DATA_MAILBOX, 3); 5427 5428 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5429 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 5430 } 5431 5432 5433 /* 5434 * The driver is supposed to notify ASF that the OS is still running 5435 * every three seconds, otherwise the management server may attempt 5436 * to reboot the machine. If it hasn't actually failed, this is 5437 * not a desirable result. However, this isn't running as a real-time 5438 * thread, and even if it were, it might not be able to generate the 5439 * heartbeat in a timely manner due to system load. As it isn't a 5440 * significant strain on the machine, we will set the interval to half 5441 * of the required value. 5442 */ 5443 void 5444 bge_asf_heartbeat(void *arg) 5445 { 5446 bge_t *bgep = (bge_t *)arg; 5447 5448 mutex_enter(bgep->genlock); 5449 bge_asf_update_status((bge_t *)bgep); 5450 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5451 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 5452 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) 5453 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 5454 mutex_exit(bgep->genlock); 5455 ((bge_t *)bgep)->asf_timeout_id = timeout(bge_asf_heartbeat, bgep, 5456 drv_usectohz(BGE_ASF_HEARTBEAT_INTERVAL)); 5457 } 5458 5459 5460 void 5461 bge_asf_stop_timer(bge_t *bgep) 5462 { 5463 timeout_id_t tmp_id = 0; 5464 5465 while ((bgep->asf_timeout_id != 0) && 5466 (tmp_id != bgep->asf_timeout_id)) { 5467 tmp_id = bgep->asf_timeout_id; 5468 (void) untimeout(tmp_id); 5469 } 5470 bgep->asf_timeout_id = 0; 5471 } 5472 5473 5474 5475 /* 5476 * This function should be placed at the earliest position of bge_attach(). 5477 */ 5478 void 5479 bge_asf_get_config(bge_t *bgep) 5480 { 5481 uint32_t nicsig; 5482 uint32_t niccfg; 5483 5484 bgep->asf_enabled = B_FALSE; 5485 nicsig = bge_nic_read32(bgep, BGE_NIC_DATA_SIG_ADDR); 5486 if (nicsig == BGE_NIC_DATA_SIG) { 5487 niccfg = bge_nic_read32(bgep, BGE_NIC_DATA_NIC_CFG_ADDR); 5488 if (niccfg & BGE_NIC_CFG_ENABLE_ASF) 5489 /* 5490 * Here, we don't consider BAXTER, because BGE haven't 5491 * supported BAXTER (that is 5752). Also, as I know, 5492 * BAXTER doesn't support ASF feature. 5493 */ 5494 bgep->asf_enabled = B_TRUE; 5495 else 5496 bgep->asf_enabled = B_FALSE; 5497 } else 5498 bgep->asf_enabled = B_FALSE; 5499 } 5500 5501 5502 void 5503 bge_asf_pre_reset_operations(bge_t *bgep, uint32_t mode) 5504 { 5505 uint32_t tries; 5506 uint32_t event; 5507 5508 ASSERT(bgep->asf_enabled); 5509 5510 /* Issues "pause firmware" command and wait for ACK */ 5511 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_PAUSE_FW); 5512 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5513 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 5514 5515 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5516 tries = 0; 5517 while ((event & RRER_ASF_EVENT) && (tries < 100)) { 5518 drv_usecwait(1); 5519 tries ++; 5520 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5521 } 5522 5523 bge_nic_put32(bgep, BGE_FIRMWARE_MAILBOX, 5524 BGE_MAGIC_NUM_FIRMWARE_INIT_DONE); 5525 5526 if (bgep->asf_newhandshake) { 5527 switch (mode) { 5528 case BGE_INIT_RESET: 5529 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5530 BGE_DRV_STATE_START); 5531 break; 5532 case BGE_SHUTDOWN_RESET: 5533 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5534 BGE_DRV_STATE_UNLOAD); 5535 break; 5536 case BGE_SUSPEND_RESET: 5537 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5538 BGE_DRV_STATE_SUSPEND); 5539 break; 5540 default: 5541 break; 5542 } 5543 } 5544 } 5545 5546 5547 void 5548 bge_asf_post_reset_old_mode(bge_t *bgep, uint32_t mode) 5549 { 5550 switch (mode) { 5551 case BGE_INIT_RESET: 5552 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5553 BGE_DRV_STATE_START); 5554 break; 5555 case BGE_SHUTDOWN_RESET: 5556 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5557 BGE_DRV_STATE_UNLOAD); 5558 break; 5559 case BGE_SUSPEND_RESET: 5560 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5561 BGE_DRV_STATE_SUSPEND); 5562 break; 5563 default: 5564 break; 5565 } 5566 } 5567 5568 5569 void 5570 bge_asf_post_reset_new_mode(bge_t *bgep, uint32_t mode) 5571 { 5572 switch (mode) { 5573 case BGE_INIT_RESET: 5574 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5575 BGE_DRV_STATE_START_DONE); 5576 break; 5577 case BGE_SHUTDOWN_RESET: 5578 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5579 BGE_DRV_STATE_UNLOAD_DONE); 5580 break; 5581 default: 5582 break; 5583 } 5584 } 5585 5586 #endif /* BGE_IPMI_ASF */ 5587