1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 2010-2013, by Broadcom, Inc. 24 * All Rights Reserved. 25 */ 26 27 /* 28 * Copyright (c) 2002, 2010, Oracle and/or its affiliates. 29 * All rights reserved. 30 * Copyright 2016 Nexenta Systems, Inc. All rights reserved. 31 */ 32 33 #include "bge_impl.h" 34 35 #define PIO_ADDR(bgep, offset) ((void *)((caddr_t)(bgep)->io_regs+(offset))) 36 #define APE_ADDR(bgep, offset) ((void *)((caddr_t)(bgep)->ape_regs+(offset))) 37 38 /* 39 * Future features ... ? 40 */ 41 #define BGE_CFG_IO8 1 /* 8/16-bit cfg space BIS/BIC */ 42 #define BGE_IND_IO32 1 /* indirect access code */ 43 #define BGE_SEE_IO32 1 /* SEEPROM access code */ 44 #define BGE_FLASH_IO32 1 /* FLASH access code */ 45 46 /* 47 * BGE MSI tunable: 48 * 49 * By default MSI is enabled on all supported platforms but it is disabled 50 * for some Broadcom chips due to known MSI hardware issues. Currently MSI 51 * is enabled only for 5714C A2 and 5715C A2 broadcom chips. 52 */ 53 boolean_t bge_enable_msi = B_TRUE; 54 55 /* 56 * PCI-X/PCI-E relaxed ordering tunable for OS/Nexus driver 57 */ 58 boolean_t bge_relaxed_ordering = B_TRUE; 59 60 /* 61 * Patchable globals: 62 * 63 * bge_autorecover 64 * Enables/disables automatic recovery after fault detection 65 * 66 * bge_mlcr_default 67 * Value to program into the MLCR; controls the chip's GPIO pins 68 * 69 * bge_dma_{rd,wr}prio 70 * Relative priorities of DMA reads & DMA writes respectively. 71 * These may each be patched to any value 0-3. Equal values 72 * will give "fair" (round-robin) arbitration for PCI access. 73 * Unequal values will give one or the other function priority. 74 * 75 * bge_dma_rwctrl 76 * Value to put in the Read/Write DMA control register. See 77 * the Broadcom PRM for things you can fiddle with in this 78 * register ... 79 * 80 * bge_{tx,rx}_{count,ticks}_{norm,intr} 81 * Send/receive interrupt coalescing parameters. Counts are 82 * #s of descriptors, ticks are in microseconds. *norm* values 83 * apply between status updates/interrupts; the *intr* values 84 * refer to the 'during-interrupt' versions - see the PRM. 85 * 86 * NOTE: these values have been determined by measurement. They 87 * differ significantly from the values recommended in the PRM. 88 */ 89 static uint32_t bge_autorecover = 1; 90 static uint32_t bge_mlcr_default_5714 = MLCR_DEFAULT_5714; 91 92 static uint32_t bge_dma_rdprio = 1; 93 static uint32_t bge_dma_wrprio = 0; 94 static uint32_t bge_dma_rwctrl = PDRWCR_VAR_DEFAULT; 95 static uint32_t bge_dma_rwctrl_5721 = PDRWCR_VAR_5721; 96 static uint32_t bge_dma_rwctrl_5714 = PDRWCR_VAR_5714; 97 static uint32_t bge_dma_rwctrl_5715 = PDRWCR_VAR_5715; 98 99 uint32_t bge_rx_ticks_norm = 128; 100 uint32_t bge_tx_ticks_norm = 512; 101 uint32_t bge_rx_count_norm = 8; 102 uint32_t bge_tx_count_norm = 128; 103 104 static uint32_t bge_rx_ticks_intr = 128; 105 static uint32_t bge_tx_ticks_intr = 0; /* 8 for FJ2+ !?!? */ 106 static uint32_t bge_rx_count_intr = 2; 107 static uint32_t bge_tx_count_intr = 0; 108 109 /* 110 * Memory pool configuration parameters. 111 * 112 * These are generally specific to each member of the chip family, since 113 * each one may have a different memory size/configuration. 114 * 115 * Setting the mbuf pool length for a specific type of chip to 0 inhibits 116 * the driver from programming the various registers; instead they are left 117 * at their hardware defaults. This is the preferred option for later chips 118 * (5705+), whereas the older chips *required* these registers to be set, 119 * since the h/w default was 0 ;-( 120 */ 121 static uint32_t bge_mbuf_pool_base = MBUF_POOL_BASE_DEFAULT; 122 static uint32_t bge_mbuf_pool_base_5704 = MBUF_POOL_BASE_5704; 123 static uint32_t bge_mbuf_pool_base_5705 = MBUF_POOL_BASE_5705; 124 static uint32_t bge_mbuf_pool_base_5721 = MBUF_POOL_BASE_5721; 125 static uint32_t bge_mbuf_pool_len = MBUF_POOL_LENGTH_DEFAULT; 126 static uint32_t bge_mbuf_pool_len_5704 = MBUF_POOL_LENGTH_5704; 127 static uint32_t bge_mbuf_pool_len_5705 = 0; /* use h/w default */ 128 static uint32_t bge_mbuf_pool_len_5721 = 0; 129 130 /* 131 * Various high and low water marks, thresholds, etc ... 132 * 133 * Note: these are taken from revision 7 of the PRM, and some are different 134 * from both the values in earlier PRMs *and* those determined experimentally 135 * and used in earlier versions of this driver ... 136 */ 137 static uint32_t bge_mbuf_hi_water = MBUF_HIWAT_DEFAULT; 138 static uint32_t bge_mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_DEFAULT; 139 static uint32_t bge_mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_DEFAULT; 140 141 static uint32_t bge_dmad_lo_water = DMAD_POOL_LOWAT_DEFAULT; 142 static uint32_t bge_dmad_hi_water = DMAD_POOL_HIWAT_DEFAULT; 143 static uint32_t bge_lowat_recv_frames = LOWAT_MAX_RECV_FRAMES_DEFAULT; 144 145 static uint32_t bge_replenish_std = STD_RCV_BD_REPLENISH_DEFAULT; 146 static uint32_t bge_replenish_mini = MINI_RCV_BD_REPLENISH_DEFAULT; 147 static uint32_t bge_replenish_jumbo = JUMBO_RCV_BD_REPLENISH_DEFAULT; 148 149 static uint32_t bge_watchdog_count = 1 << 16; 150 static uint16_t bge_dma_miss_limit = 20; 151 152 static uint32_t bge_stop_start_on_sync = 0; 153 154 /* 155 * bge_intr_max_loop controls the maximum loop number within bge_intr. 156 * When loading NIC with heavy network traffic, it is useful. 157 * Increasing this value could have positive effect to throughput, 158 * but it might also increase ticks of a bge ISR stick on CPU, which might 159 * lead to bad UI interactive experience. So tune this with caution. 160 */ 161 static int bge_intr_max_loop = 1; 162 163 /* 164 * ========== Low-level chip & ring buffer manipulation ========== 165 */ 166 167 #define BGE_DBG BGE_DBG_REGS /* debug flag for this code */ 168 169 170 /* 171 * Config space read-modify-write routines 172 */ 173 174 #if BGE_CFG_IO8 175 176 static void bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits); 177 #pragma inline(bge_cfg_clr16) 178 179 static void 180 bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits) 181 { 182 uint16_t regval; 183 184 BGE_TRACE(("bge_cfg_clr16($%p, 0x%lx, 0x%x)", 185 (void *)bgep, regno, bits)); 186 187 regval = pci_config_get16(bgep->cfg_handle, regno); 188 189 BGE_DEBUG(("bge_cfg_clr16($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 190 (void *)bgep, regno, bits, regval, regval & ~bits)); 191 192 regval &= ~bits; 193 pci_config_put16(bgep->cfg_handle, regno, regval); 194 } 195 196 #endif /* BGE_CFG_IO8 */ 197 198 static void bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 199 #pragma inline(bge_cfg_clr32) 200 201 static void 202 bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 203 { 204 uint32_t regval; 205 206 BGE_TRACE(("bge_cfg_clr32($%p, 0x%lx, 0x%x)", 207 (void *)bgep, regno, bits)); 208 209 regval = pci_config_get32(bgep->cfg_handle, regno); 210 211 BGE_DEBUG(("bge_cfg_clr32($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 212 (void *)bgep, regno, bits, regval, regval & ~bits)); 213 214 regval &= ~bits; 215 pci_config_put32(bgep->cfg_handle, regno, regval); 216 } 217 218 #if BGE_IND_IO32 219 220 /* 221 * Indirect access to registers & RISC scratchpads, using config space 222 * accesses only. 223 * 224 * This isn't currently used, but someday we might want to use it for 225 * restoring the Subsystem Device/Vendor registers (which aren't directly 226 * writable in Config Space), or for downloading firmware into the RISCs 227 * 228 * In any case there are endian issues to be resolved before this code is 229 * enabled; the bizarre way that bytes get twisted by this chip AND by 230 * the PCI bridge in SPARC systems mean that we shouldn't enable it until 231 * it's been thoroughly tested for all access sizes on all supported 232 * architectures (SPARC *and* x86!). 233 */ 234 uint32_t bge_ind_get32(bge_t *bgep, bge_regno_t regno); 235 #pragma inline(bge_ind_get32) 236 237 uint32_t 238 bge_ind_get32(bge_t *bgep, bge_regno_t regno) 239 { 240 uint32_t val; 241 242 BGE_TRACE(("bge_ind_get32($%p, 0x%lx)", (void *)bgep, regno)); 243 244 #ifdef __sparc 245 if (DEVICE_5717_SERIES_CHIPSETS(bgep) || 246 DEVICE_5725_SERIES_CHIPSETS(bgep)) { 247 regno = LE_32(regno); 248 } 249 #endif 250 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 251 val = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_RIADR); 252 253 BGE_DEBUG(("bge_ind_get32($%p, 0x%lx) => 0x%x", 254 (void *)bgep, regno, val)); 255 256 val = LE_32(val); 257 258 return (val); 259 } 260 261 void bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val); 262 #pragma inline(bge_ind_put32) 263 264 void 265 bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val) 266 { 267 BGE_TRACE(("bge_ind_put32($%p, 0x%lx, 0x%x)", 268 (void *)bgep, regno, val)); 269 270 val = LE_32(val); 271 #ifdef __sparc 272 if (DEVICE_5717_SERIES_CHIPSETS(bgep) || 273 DEVICE_5725_SERIES_CHIPSETS(bgep)) { 274 regno = LE_32(regno); 275 } 276 #endif 277 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 278 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIADR, val); 279 } 280 281 #endif /* BGE_IND_IO32 */ 282 283 #if BGE_DEBUGGING 284 285 static void bge_pci_check(bge_t *bgep); 286 #pragma no_inline(bge_pci_check) 287 288 static void 289 bge_pci_check(bge_t *bgep) 290 { 291 uint16_t pcistatus; 292 293 pcistatus = pci_config_get16(bgep->cfg_handle, PCI_CONF_STAT); 294 if ((pcistatus & (PCI_STAT_R_MAST_AB | PCI_STAT_R_TARG_AB)) != 0) 295 BGE_DEBUG(("bge_pci_check($%p): PCI status 0x%x", 296 (void *)bgep, pcistatus)); 297 } 298 299 #endif /* BGE_DEBUGGING */ 300 301 /* 302 * Perform first-stage chip (re-)initialisation, using only config-space 303 * accesses: 304 * 305 * + Read the vendor/device/revision/subsystem/cache-line-size registers, 306 * returning the data in the structure pointed to by <idp>. 307 * + Configure the target-mode endianness (swap) options. 308 * + Disable interrupts and enable Memory Space accesses. 309 * + Enable or disable Bus Mastering according to the <enable_dma> flag. 310 * 311 * This sequence is adapted from Broadcom document 570X-PG102-R, 312 * page 102, steps 1-3, 6-8 and 11-13. The omitted parts of the sequence 313 * are 4 and 5 (Reset Core and wait) which are handled elsewhere. 314 * 315 * This function MUST be called before any non-config-space accesses 316 * are made; on this first call <enable_dma> is B_FALSE, and it 317 * effectively performs steps 3-1(!) of the initialisation sequence 318 * (the rest are not required but should be harmless). 319 * 320 * It MUST also be called after a chip reset, as this disables 321 * Memory Space cycles! In this case, <enable_dma> is B_TRUE, and 322 * it is effectively performing steps 6-8. 323 */ 324 void bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma); 325 #pragma no_inline(bge_chip_cfg_init) 326 327 void 328 bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma) 329 { 330 ddi_acc_handle_t handle; 331 uint16_t command; 332 uint32_t mhcr; 333 uint32_t prodid; 334 uint32_t pci_state; 335 uint16_t value16; 336 int i; 337 338 BGE_TRACE(("bge_chip_cfg_init($%p, $%p, %d)", 339 (void *)bgep, (void *)cidp, enable_dma)); 340 341 /* 342 * Step 3: save PCI cache line size and subsystem vendor ID 343 * 344 * Read all the config-space registers that characterise the 345 * chip, specifically vendor/device/revision/subsystem vendor 346 * and subsystem device id. We expect (but don't check) that 347 * (vendor == VENDOR_ID_BROADCOM) && (device == DEVICE_ID_5704) 348 * 349 * Also save all bus-transaction related registers (cache-line 350 * size, bus-grant/latency parameters, etc). Some of these are 351 * cleared by reset, so we'll have to restore them later. This 352 * comes from the Broadcom document 570X-PG102-R ... 353 * 354 * Note: Broadcom document 570X-PG102-R seems to be in error 355 * here w.r.t. the offsets of the Subsystem Vendor ID and 356 * Subsystem (Device) ID registers, which are the opposite way 357 * round according to the PCI standard. For good measure, we 358 * save/restore both anyway. 359 */ 360 handle = bgep->cfg_handle; 361 362 /* 363 * For some chipsets (e.g., BCM5718), if MHCR_ENABLE_ENDIAN_BYTE_SWAP 364 * has been set in PCI_CONF_COMM already, we need to write the 365 * byte-swapped value to it. So we just write zero first for simplicity. 366 */ 367 cidp->device = pci_config_get16(handle, PCI_CONF_DEVID); 368 if (DEVICE_5717_SERIES_CHIPSETS(bgep) || 369 DEVICE_5725_SERIES_CHIPSETS(bgep)) { 370 pci_config_put32(handle, PCI_CONF_BGE_MHCR, 0); 371 } 372 373 mhcr = pci_config_get32(handle, PCI_CONF_BGE_MHCR); 374 cidp->asic_rev = (mhcr & MHCR_CHIP_REV_MASK); 375 cidp->asic_rev_prod_id = 0; 376 if ((cidp->asic_rev & 0xf0000000) == CHIP_ASIC_REV_USE_PROD_ID_REG) { 377 prodid = CHIP_ASIC_REV_PROD_ID_REG; 378 if (DEVICE_5717_SERIES_CHIPSETS(bgep) || 379 DEVICE_5725_SERIES_CHIPSETS(bgep)) { 380 prodid = CHIP_ASIC_REV_PROD_ID_GEN2_REG; 381 } 382 cidp->asic_rev_prod_id = pci_config_get32(handle, prodid); 383 } 384 385 cidp->businfo = pci_config_get32(handle, PCI_CONF_BGE_PCISTATE); 386 cidp->command = pci_config_get16(handle, PCI_CONF_COMM); 387 388 cidp->vendor = pci_config_get16(handle, PCI_CONF_VENID); 389 cidp->subven = pci_config_get16(handle, PCI_CONF_SUBVENID); 390 cidp->subdev = pci_config_get16(handle, PCI_CONF_SUBSYSID); 391 cidp->revision = pci_config_get8(handle, PCI_CONF_REVID); 392 cidp->clsize = pci_config_get8(handle, PCI_CONF_CACHE_LINESZ); 393 cidp->latency = pci_config_get8(handle, PCI_CONF_LATENCY_TIMER); 394 395 /* 5717 C0 is treated just like 5720 A0 */ 396 if (pci_config_get16(bgep->cfg_handle, PCI_CONF_DEVID) == 397 DEVICE_ID_5717_C0) { 398 cidp->device = DEVICE_ID_5720; 399 } 400 401 BGE_DEBUG(("bge_chip_cfg_init: %s bus is %s and %s; #INTA is %s", 402 cidp->businfo & PCISTATE_BUS_IS_PCI ? "PCI" : "PCI-X", 403 cidp->businfo & PCISTATE_BUS_IS_FAST ? "fast" : "slow", 404 cidp->businfo & PCISTATE_BUS_IS_32_BIT ? "narrow" : "wide", 405 cidp->businfo & PCISTATE_INTA_STATE ? "high" : "low")); 406 BGE_DEBUG(("bge_chip_cfg_init: vendor 0x%x device 0x%x revision 0x%x", 407 cidp->vendor, cidp->device, cidp->revision)); 408 BGE_DEBUG(("bge_chip_cfg_init: subven 0x%x subdev 0x%x asic_rev 0x%x", 409 cidp->subven, cidp->subdev, cidp->asic_rev)); 410 BGE_DEBUG(("bge_chip_cfg_init: clsize %d latency %d command 0x%x", 411 cidp->clsize, cidp->latency, cidp->command)); 412 413 /* 414 * Step 2 (also step 6): disable and clear interrupts. 415 * Steps 11-13: configure PIO endianness options, and enable 416 * indirect register access. We'll also select any other 417 * options controlled by the MHCR (e.g. tagged status, mask 418 * interrupt mode) at this stage ... 419 * 420 * Note: internally, the chip is 64-bit and BIG-endian, but 421 * since it talks to the host over a (LITTLE-endian) PCI bus, 422 * it normally swaps bytes around at the PCI interface. 423 * However, the PCI host bridge on SPARC systems normally 424 * swaps the byte lanes around too, since SPARCs are also 425 * BIG-endian. So it turns out that on SPARC, the right 426 * option is to tell the chip to swap (and the host bridge 427 * will swap back again), whereas on x86 we ask the chip 428 * NOT to swap, so the natural little-endianness of the 429 * PCI bus is assumed. Then the only thing that doesn't 430 * automatically work right is access to an 8-byte register 431 * by a little-endian host; but we don't want to set the 432 * MHCR_ENABLE_REGISTER_WORD_SWAP bit because then 4-byte 433 * accesses don't go where expected ;-( So we live with 434 * that, and perform word-swaps in software in the few cases 435 * where a chip register is defined as an 8-byte value -- 436 * see the code below for details ... 437 * 438 * Note: the meaning of the 'MASK_INTERRUPT_MODE' bit isn't 439 * very clear in the register description in the PRM, but 440 * Broadcom document 570X-PG104-R page 248 explains a little 441 * more (under "Broadcom Mask Mode"). The bit changes the way 442 * the MASK_PCI_INT_OUTPUT bit works: with MASK_INTERRUPT_MODE 443 * clear, the chip interprets MASK_PCI_INT_OUTPUT in the same 444 * way as the 5700 did, which isn't very convenient. Setting 445 * the MASK_INTERRUPT_MODE bit makes the MASK_PCI_INT_OUTPUT 446 * bit do just what its name says -- MASK the PCI #INTA output 447 * (i.e. deassert the signal at the pin) leaving all internal 448 * state unchanged. This is much more convenient for our 449 * interrupt handler, so we set MASK_INTERRUPT_MODE here. 450 * 451 * Note: the inconvenient semantics of the interrupt mailbox 452 * (nonzero disables and acknowledges/clears the interrupt, 453 * zero enables AND CLEARS it) would make race conditions 454 * likely in the interrupt handler: 455 * 456 * (1) acknowledge & disable interrupts 457 * (2) while (more to do) 458 * process packets 459 * (3) enable interrupts -- also clears pending 460 * 461 * If the chip received more packets and internally generated 462 * an interrupt between the check at (2) and the mbox write 463 * at (3), this interrupt would be lost :-( 464 * 465 * The best way to avoid this is to use TAGGED STATUS mode, 466 * where the chip includes a unique tag in each status block 467 * update, and the host, when re-enabling interrupts, passes 468 * the last tag it saw back to the chip; then the chip can 469 * see whether the host is truly up to date, and regenerate 470 * its interrupt if not. 471 */ 472 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 473 MHCR_ENABLE_PCI_STATE_RW | 474 MHCR_ENABLE_TAGGED_STATUS_MODE | 475 MHCR_MASK_INTERRUPT_MODE | 476 MHCR_CLEAR_INTERRUPT_INTA; 477 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 478 mhcr |= MHCR_MASK_PCI_INT_OUTPUT; 479 480 #ifdef _BIG_ENDIAN 481 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 482 #endif /* _BIG_ENDIAN */ 483 pci_config_put32(handle, PCI_CONF_BGE_MHCR, mhcr); 484 485 #ifdef BGE_IPMI_ASF 486 bgep->asf_wordswapped = B_FALSE; 487 #endif 488 489 pci_state = (PCISTATE_EXT_ROM_ENABLE | PCISTATE_EXT_ROM_RETRY); 490 /* allow reads and writes to the APE register and memory space */ 491 if (bgep->ape_enabled) { 492 pci_state |= PCISTATE_ALLOW_APE_CTLSPC_WR | 493 PCISTATE_ALLOW_APE_SHMEM_WR | PCISTATE_ALLOW_APE_PSPACE_WR; 494 } 495 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_PCISTATE, pci_state); 496 497 /* 498 * Step 1 (also step 7): Enable PCI Memory Space accesses 499 * Disable Memory Write/Invalidate 500 * Enable or disable Bus Mastering 501 * 502 * Note that all other bits are taken from the original value saved 503 * the first time through here, rather than from the current register 504 * value, 'cos that will have been cleared by a soft RESET since. 505 * In this way we preserve the OBP/nexus-parent's preferred settings 506 * of the parity-error and system-error enable bits across multiple 507 * chip RESETs. 508 */ 509 command = bgep->chipid.command | PCI_COMM_MAE; 510 command &= ~(PCI_COMM_ME|PCI_COMM_MEMWR_INVAL); 511 if (enable_dma) 512 command |= PCI_COMM_ME; 513 /* 514 * on BCM5714 revision A0, false parity error gets generated 515 * due to a logic bug. Provide a workaround by disabling parity 516 * error. 517 */ 518 if (((cidp->device == DEVICE_ID_5714C) || 519 (cidp->device == DEVICE_ID_5714S)) && 520 (cidp->revision == REVISION_ID_5714_A0)) { 521 command &= ~PCI_COMM_PARITY_DETECT; 522 } 523 pci_config_put16(handle, PCI_CONF_COMM, command); 524 525 /* 526 * On some PCI-E device, there were instances when 527 * the device was still link training. 528 */ 529 if (bgep->chipid.pci_type == BGE_PCI_E) { 530 i = 0; 531 value16 = pci_config_get16(handle, PCI_CONF_COMM); 532 while ((value16 != command) && (i < 100)) { 533 drv_usecwait(200); 534 value16 = pci_config_get16(handle, PCI_CONF_COMM); 535 ++i; 536 } 537 } 538 539 /* 540 * Clear any remaining error status bits 541 */ 542 pci_config_put16(handle, PCI_CONF_STAT, ~0); 543 544 /* 545 * Do following if and only if the device is NOT BCM5714C OR 546 * BCM5715C 547 */ 548 if (!((cidp->device == DEVICE_ID_5714C) || 549 (cidp->device == DEVICE_ID_5715C))) { 550 /* 551 * Make sure these indirect-access registers are sane 552 * rather than random after power-up or reset 553 */ 554 pci_config_put32(handle, PCI_CONF_BGE_RIAAR, 0); 555 pci_config_put32(handle, PCI_CONF_BGE_MWBAR, 0); 556 } 557 /* 558 * Step 8: Disable PCI-X/PCI-E Relaxed Ordering 559 */ 560 bge_cfg_clr16(bgep, PCIX_CONF_COMM, PCIX_COMM_RELAXED); 561 562 if (cidp->pci_type == BGE_PCI_E) { 563 if (DEVICE_5723_SERIES_CHIPSETS(bgep)) { 564 bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL_5723, 565 DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED); 566 } else if (DEVICE_5717_SERIES_CHIPSETS(bgep) || 567 DEVICE_5725_SERIES_CHIPSETS(bgep)) { 568 bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL_5717, 569 DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED); 570 } else { 571 bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL, 572 DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED); 573 } 574 } 575 } 576 577 #ifdef __amd64 578 /* 579 * Distinguish CPU types 580 * 581 * These use to distinguish AMD64 or Intel EM64T of CPU running mode. 582 * If CPU runs on Intel EM64T mode,the 64bit operation cannot works fine 583 * for PCI-Express based network interface card. This is the work-around 584 * for those nics. 585 */ 586 static boolean_t bge_get_em64t_type(void); 587 #pragma inline(bge_get_em64t_type) 588 589 static boolean_t 590 bge_get_em64t_type(void) 591 { 592 593 return (x86_vendor == X86_VENDOR_Intel); 594 } 595 #endif 596 597 /* 598 * Operating register get/set access routines 599 */ 600 601 uint32_t bge_reg_get32(bge_t *bgep, bge_regno_t regno); 602 #pragma inline(bge_reg_get32) 603 604 uint32_t 605 bge_reg_get32(bge_t *bgep, bge_regno_t regno) 606 { 607 BGE_TRACE(("bge_reg_get32($%p, 0x%lx)", 608 (void *)bgep, regno)); 609 610 return (ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno))); 611 } 612 613 void bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data); 614 #pragma inline(bge_reg_put32) 615 616 void 617 bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data) 618 { 619 BGE_TRACE(("bge_reg_put32($%p, 0x%lx, 0x%x)", 620 (void *)bgep, regno, data)); 621 622 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), data); 623 BGE_PCICHK(bgep); 624 } 625 626 void bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 627 #pragma inline(bge_reg_set32) 628 629 void 630 bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 631 { 632 uint32_t regval; 633 634 BGE_TRACE(("bge_reg_set32($%p, 0x%lx, 0x%x)", 635 (void *)bgep, regno, bits)); 636 637 regval = bge_reg_get32(bgep, regno); 638 regval |= bits; 639 bge_reg_put32(bgep, regno, regval); 640 } 641 642 void bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 643 #pragma inline(bge_reg_clr32) 644 645 void 646 bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 647 { 648 uint32_t regval; 649 650 BGE_TRACE(("bge_reg_clr32($%p, 0x%lx, 0x%x)", 651 (void *)bgep, regno, bits)); 652 653 regval = bge_reg_get32(bgep, regno); 654 regval &= ~bits; 655 bge_reg_put32(bgep, regno, regval); 656 } 657 658 static uint64_t bge_reg_get64(bge_t *bgep, bge_regno_t regno); 659 #pragma inline(bge_reg_get64) 660 661 static uint64_t 662 bge_reg_get64(bge_t *bgep, bge_regno_t regno) 663 { 664 uint64_t regval; 665 666 #ifdef __amd64 667 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || 668 bge_get_em64t_type() || 669 DEVICE_5717_SERIES_CHIPSETS(bgep) || 670 DEVICE_5725_SERIES_CHIPSETS(bgep)) { 671 regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4)); 672 regval <<= 32; 673 regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 674 } else { 675 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 676 } 677 #elif defined(__sparc) 678 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || 679 DEVICE_5717_SERIES_CHIPSETS(bgep) || 680 DEVICE_5725_SERIES_CHIPSETS(bgep)) { 681 regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 682 regval <<= 32; 683 regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4)); 684 } else { 685 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 686 } 687 #else 688 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 689 #endif 690 691 #ifdef _LITTLE_ENDIAN 692 regval = (regval >> 32) | (regval << 32); 693 #endif /* _LITTLE_ENDIAN */ 694 695 BGE_TRACE(("bge_reg_get64($%p, 0x%lx) = 0x%016llx", 696 (void *)bgep, regno, regval)); 697 698 return (regval); 699 } 700 701 static void bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data); 702 #pragma inline(bge_reg_put64) 703 704 static void 705 bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data) 706 { 707 BGE_TRACE(("bge_reg_put64($%p, 0x%lx, 0x%016llx)", 708 (void *)bgep, regno, data)); 709 710 #ifdef _LITTLE_ENDIAN 711 data = ((data >> 32) | (data << 32)); 712 #endif /* _LITTLE_ENDIAN */ 713 714 #ifdef __amd64 715 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || 716 bge_get_em64t_type() || 717 DEVICE_5717_SERIES_CHIPSETS(bgep) || 718 DEVICE_5725_SERIES_CHIPSETS(bgep)) { 719 ddi_put32(bgep->io_handle, 720 PIO_ADDR(bgep, regno), (uint32_t)data); 721 BGE_PCICHK(bgep); 722 ddi_put32(bgep->io_handle, 723 PIO_ADDR(bgep, regno + 4), (uint32_t)(data >> 32)); 724 725 } else { 726 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 727 } 728 #elif defined(__sparc) 729 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || 730 DEVICE_5717_SERIES_CHIPSETS(bgep) || 731 DEVICE_5725_SERIES_CHIPSETS(bgep)) { 732 ddi_put32(bgep->io_handle, 733 PIO_ADDR(bgep, regno + 4), (uint32_t)data); 734 BGE_PCICHK(bgep); 735 ddi_put32(bgep->io_handle, 736 PIO_ADDR(bgep, regno), (uint32_t)(data >> 32)); 737 } else { 738 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 739 } 740 #else 741 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 742 #endif 743 744 BGE_PCICHK(bgep); 745 } 746 747 /* 748 * The DDI doesn't provide get/put functions for 128 bit data 749 * so we put RCBs out as two 64-bit chunks instead. 750 */ 751 static void bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 752 #pragma inline(bge_reg_putrcb) 753 754 static void 755 bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 756 { 757 uint64_t *p; 758 759 BGE_TRACE(("bge_reg_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 760 (void *)bgep, addr, rcbp->host_ring_addr, 761 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 762 763 ASSERT((addr % sizeof (*rcbp)) == 0); 764 765 p = (void *)rcbp; 766 bge_reg_put64(bgep, addr, *p++); 767 bge_reg_put64(bgep, addr+8, *p); 768 } 769 770 void bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data); 771 #pragma inline(bge_mbx_put) 772 773 void 774 bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data) 775 { 776 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) 777 regno += INTERRUPT_LP_MBOX_0_REG - INTERRUPT_MBOX_0_REG + 4; 778 779 BGE_TRACE(("bge_mbx_put($%p, 0x%lx, 0x%016llx)", 780 (void *)bgep, regno, data)); 781 782 /* 783 * Mailbox registers are nominally 64 bits on the 5701, but 784 * the MSW isn't used. On the 5703, they're only 32 bits 785 * anyway. So here we just write the lower(!) 32 bits - 786 * remembering that the chip is big-endian, even though the 787 * PCI bus is little-endian ... 788 */ 789 #ifdef _BIG_ENDIAN 790 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno+4), (uint32_t)data); 791 #else 792 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), (uint32_t)data); 793 #endif /* _BIG_ENDIAN */ 794 BGE_PCICHK(bgep); 795 } 796 797 uint32_t bge_mbx_get(bge_t *bgep, bge_regno_t regno); 798 #pragma inline(bge_mbx_get) 799 800 uint32_t 801 bge_mbx_get(bge_t *bgep, bge_regno_t regno) 802 { 803 uint32_t val32; 804 805 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) 806 regno += INTERRUPT_LP_MBOX_0_REG - INTERRUPT_MBOX_0_REG + 4; 807 808 BGE_TRACE(("bge_mbx_get($%p, 0x%lx)", 809 (void *)bgep, regno)); 810 811 #ifdef _BIG_ENDIAN 812 val32 = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno+4)); 813 #else 814 val32 = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 815 #endif /* _BIG_ENDIAN */ 816 BGE_PCICHK(bgep); 817 818 BGE_DEBUG(("bge_mbx_get($%p, 0x%lx) => 0x%08x", 819 (void *)bgep, regno, val32)); 820 821 return (val32); 822 } 823 824 825 #if BGE_DEBUGGING 826 827 void bge_led_mark(bge_t *bgep); 828 #pragma no_inline(bge_led_mark) 829 830 void 831 bge_led_mark(bge_t *bgep) 832 { 833 uint32_t led_ctrl = LED_CONTROL_OVERRIDE_LINK | 834 LED_CONTROL_1000MBPS_LED | 835 LED_CONTROL_100MBPS_LED | 836 LED_CONTROL_10MBPS_LED; 837 838 /* 839 * Blink all three LINK LEDs on simultaneously, then all off, 840 * then restore to automatic hardware control. This is used 841 * in laboratory testing to trigger a logic analyser or scope. 842 */ 843 bge_reg_set32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 844 led_ctrl ^= LED_CONTROL_OVERRIDE_LINK; 845 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 846 led_ctrl = LED_CONTROL_OVERRIDE_LINK; 847 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 848 } 849 850 #endif /* BGE_DEBUGGING */ 851 852 /* 853 * NIC on-chip memory access routines 854 * 855 * Only 32K of NIC memory is visible at a time, controlled by the 856 * Memory Window Base Address Register (in PCI config space). Once 857 * this is set, the 32K region of NIC-local memory that it refers 858 * to can be directly addressed in the upper 32K of the 64K of PCI 859 * memory space used for the device. 860 */ 861 862 static void bge_nic_setwin(bge_t *bgep, bge_regno_t base); 863 #pragma inline(bge_nic_setwin) 864 865 static void 866 bge_nic_setwin(bge_t *bgep, bge_regno_t base) 867 { 868 chip_id_t *cidp; 869 870 BGE_TRACE(("bge_nic_setwin($%p, 0x%lx)", 871 (void *)bgep, base)); 872 873 ASSERT((base & MWBAR_GRANULE_MASK) == 0); 874 875 /* 876 * Don't do repeated zero data writes, 877 * if the device is BCM5714C/15C. 878 */ 879 cidp = &bgep->chipid; 880 if ((cidp->device == DEVICE_ID_5714C) || 881 (cidp->device == DEVICE_ID_5715C)) { 882 if (bgep->lastWriteZeroData && (base == (bge_regno_t)0)) 883 return; 884 /* Adjust lastWriteZeroData */ 885 bgep->lastWriteZeroData = ((base == (bge_regno_t)0) ? 886 B_TRUE : B_FALSE); 887 } 888 #ifdef __sparc 889 if (DEVICE_5717_SERIES_CHIPSETS(bgep) || 890 DEVICE_5725_SERIES_CHIPSETS(bgep)) { 891 base = LE_32(base); 892 } 893 #endif 894 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, base); 895 } 896 897 static uint32_t bge_nic_get32(bge_t *bgep, bge_regno_t addr); 898 #pragma inline(bge_nic_get32) 899 900 static uint32_t 901 bge_nic_get32(bge_t *bgep, bge_regno_t addr) 902 { 903 uint32_t data; 904 905 #if defined(BGE_IPMI_ASF) && !defined(__sparc) 906 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 907 /* workaround for word swap error */ 908 if (addr & 4) 909 addr = addr - 4; 910 else 911 addr = addr + 4; 912 } 913 #endif 914 915 #ifdef __sparc 916 data = bge_nic_read32(bgep, addr); 917 #else 918 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 919 addr &= MWBAR_GRANULE_MASK; 920 addr += NIC_MEM_WINDOW_OFFSET; 921 922 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 923 #endif 924 925 BGE_TRACE(("bge_nic_get32($%p, 0x%lx) = 0x%08x", 926 (void *)bgep, addr, data)); 927 928 return (data); 929 } 930 931 void bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data); 932 #pragma inline(bge_nic_put32) 933 934 void 935 bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data) 936 { 937 BGE_TRACE(("bge_nic_put32($%p, 0x%lx, 0x%08x)", 938 (void *)bgep, addr, data)); 939 940 #if defined(BGE_IPMI_ASF) && !defined(__sparc) 941 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 942 /* workaround for word swap error */ 943 if (addr & 4) 944 addr = addr - 4; 945 else 946 addr = addr + 4; 947 } 948 #endif 949 950 #ifdef __sparc 951 if (DEVICE_5717_SERIES_CHIPSETS(bgep) || 952 DEVICE_5725_SERIES_CHIPSETS(bgep)) { 953 addr = LE_32(addr); 954 } 955 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr); 956 data = LE_32(data); 957 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR, data); 958 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0); 959 #else 960 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 961 addr &= MWBAR_GRANULE_MASK; 962 addr += NIC_MEM_WINDOW_OFFSET; 963 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), data); 964 BGE_PCICHK(bgep); 965 #endif 966 } 967 968 static uint64_t bge_nic_get64(bge_t *bgep, bge_regno_t addr); 969 #pragma inline(bge_nic_get64) 970 971 static uint64_t 972 bge_nic_get64(bge_t *bgep, bge_regno_t addr) 973 { 974 uint64_t data; 975 976 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 977 addr &= MWBAR_GRANULE_MASK; 978 addr += NIC_MEM_WINDOW_OFFSET; 979 980 #ifdef __amd64 981 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || 982 bge_get_em64t_type() || 983 DEVICE_5717_SERIES_CHIPSETS(bgep) || 984 DEVICE_5725_SERIES_CHIPSETS(bgep)) { 985 data = ddi_get32(bgep->io_handle, 986 PIO_ADDR(bgep, addr + 4)); 987 data <<= 32; 988 data |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 989 } else { 990 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 991 } 992 #elif defined(__sparc) 993 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || 994 DEVICE_5717_SERIES_CHIPSETS(bgep) || 995 DEVICE_5725_SERIES_CHIPSETS(bgep)) { 996 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 997 data <<= 32; 998 data |= ddi_get32(bgep->io_handle, 999 PIO_ADDR(bgep, addr + 4)); 1000 } else { 1001 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 1002 } 1003 #else 1004 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 1005 #endif 1006 1007 BGE_TRACE(("bge_nic_get64($%p, 0x%lx) = 0x%016llx", 1008 (void *)bgep, addr, data)); 1009 1010 return (data); 1011 } 1012 1013 static void bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data); 1014 #pragma inline(bge_nic_put64) 1015 1016 static void 1017 bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data) 1018 { 1019 BGE_TRACE(("bge_nic_put64($%p, 0x%lx, 0x%016llx)", 1020 (void *)bgep, addr, data)); 1021 1022 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 1023 addr &= MWBAR_GRANULE_MASK; 1024 addr += NIC_MEM_WINDOW_OFFSET; 1025 1026 #ifdef __amd64 1027 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || 1028 bge_get_em64t_type() || 1029 DEVICE_5717_SERIES_CHIPSETS(bgep) || 1030 DEVICE_5725_SERIES_CHIPSETS(bgep)) { 1031 ddi_put32(bgep->io_handle, 1032 PIO_ADDR(bgep, addr + 4), (uint32_t)data); 1033 BGE_PCICHK(bgep); 1034 ddi_put32(bgep->io_handle, 1035 PIO_ADDR(bgep, addr), (uint32_t)(data >> 32)); 1036 } else { 1037 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 1038 } 1039 #elif defined(__sparc) 1040 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || 1041 DEVICE_5717_SERIES_CHIPSETS(bgep) || 1042 DEVICE_5725_SERIES_CHIPSETS(bgep)) { 1043 ddi_put32(bgep->io_handle, 1044 PIO_ADDR(bgep, addr + 4), (uint32_t)data); 1045 BGE_PCICHK(bgep); 1046 ddi_put32(bgep->io_handle, 1047 PIO_ADDR(bgep, addr), (uint32_t)(data >> 32)); 1048 } else { 1049 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 1050 } 1051 #else 1052 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 1053 #endif 1054 1055 BGE_PCICHK(bgep); 1056 } 1057 1058 /* 1059 * The DDI doesn't provide get/put functions for 128 bit data 1060 * so we put RCBs out as two 64-bit chunks instead. 1061 */ 1062 static void bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 1063 #pragma inline(bge_nic_putrcb) 1064 1065 static void 1066 bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 1067 { 1068 uint64_t *p; 1069 1070 BGE_TRACE(("bge_nic_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 1071 (void *)bgep, addr, rcbp->host_ring_addr, 1072 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 1073 1074 ASSERT((addr % sizeof (*rcbp)) == 0); 1075 1076 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 1077 addr &= MWBAR_GRANULE_MASK; 1078 addr += NIC_MEM_WINDOW_OFFSET; 1079 1080 p = (void *)rcbp; 1081 #ifdef __amd64 1082 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || 1083 bge_get_em64t_type() || 1084 DEVICE_5717_SERIES_CHIPSETS(bgep) || 1085 DEVICE_5725_SERIES_CHIPSETS(bgep)) { 1086 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), 1087 (uint32_t)(*p)); 1088 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4), 1089 (uint32_t)(*p++ >> 32)); 1090 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8), 1091 (uint32_t)(*p)); 1092 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12), 1093 (uint32_t)(*p >> 32)); 1094 1095 } else { 1096 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 1097 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr+8), *p); 1098 } 1099 #elif defined(__sparc) 1100 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || 1101 DEVICE_5717_SERIES_CHIPSETS(bgep) || 1102 DEVICE_5725_SERIES_CHIPSETS(bgep)) { 1103 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4), 1104 (uint32_t)(*p)); 1105 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), 1106 (uint32_t)(*p++ >> 32)); 1107 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12), 1108 (uint32_t)(*p)); 1109 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8), 1110 (uint32_t)(*p >> 32)); 1111 } else { 1112 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 1113 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p); 1114 } 1115 #else 1116 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 1117 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p); 1118 #endif 1119 1120 BGE_PCICHK(bgep); 1121 } 1122 1123 static void bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes); 1124 #pragma inline(bge_nic_zero) 1125 1126 static void 1127 bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes) 1128 { 1129 BGE_TRACE(("bge_nic_zero($%p, 0x%lx, 0x%x)", 1130 (void *)bgep, addr, nbytes)); 1131 1132 ASSERT((addr & ~MWBAR_GRANULE_MASK) == 1133 ((addr+nbytes) & ~MWBAR_GRANULE_MASK)); 1134 1135 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 1136 addr &= MWBAR_GRANULE_MASK; 1137 addr += NIC_MEM_WINDOW_OFFSET; 1138 1139 (void) ddi_device_zero(bgep->io_handle, PIO_ADDR(bgep, addr), 1140 nbytes, 1, DDI_DATA_SZ08_ACC); 1141 BGE_PCICHK(bgep); 1142 } 1143 1144 /* 1145 * MII (PHY) register get/set access routines 1146 * 1147 * These use the chip's MII auto-access method, controlled by the 1148 * MII Communication register at 0x044c, so the CPU doesn't have 1149 * to fiddle with the individual bits. 1150 */ 1151 1152 #undef BGE_DBG 1153 #define BGE_DBG BGE_DBG_MII /* debug flag for this code */ 1154 1155 static uint16_t bge_mii_access(bge_t *bgep, bge_regno_t regno, 1156 uint16_t data, uint32_t cmd); 1157 #pragma no_inline(bge_mii_access) 1158 1159 static uint16_t 1160 bge_mii_access(bge_t *bgep, bge_regno_t regno, uint16_t data, uint32_t cmd) 1161 { 1162 uint32_t timeout; 1163 uint32_t regval1; 1164 uint32_t regval2; 1165 1166 BGE_TRACE(("bge_mii_access($%p, 0x%lx, 0x%x, 0x%x)", 1167 (void *)bgep, regno, data, cmd)); 1168 1169 ASSERT(mutex_owned(bgep->genlock)); 1170 1171 /* 1172 * Assemble the command ... 1173 */ 1174 cmd |= data << MI_COMMS_DATA_SHIFT; 1175 cmd |= regno << MI_COMMS_REGISTER_SHIFT; 1176 cmd |= bgep->phy_mii_addr << MI_COMMS_ADDRESS_SHIFT; 1177 cmd |= MI_COMMS_START; 1178 1179 /* 1180 * Wait for any command already in progress ... 1181 * 1182 * Note: this *shouldn't* ever find that there is a command 1183 * in progress, because we already hold the <genlock> mutex. 1184 * Nonetheless, we have sometimes seen the MI_COMMS_START 1185 * bit set here -- it seems that the chip can initiate MII 1186 * accesses internally, even with polling OFF. 1187 */ 1188 regval1 = regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1189 for (timeout = 100; ; ) { 1190 if ((regval2 & MI_COMMS_START) == 0) { 1191 bge_reg_put32(bgep, MI_COMMS_REG, cmd); 1192 break; 1193 } 1194 if (--timeout == 0) 1195 break; 1196 drv_usecwait(10); 1197 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1198 } 1199 1200 if (timeout == 0) 1201 return ((uint16_t)~0u); 1202 1203 if (timeout != 100) 1204 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1205 "MI_COMMS_START set for %d us; 0x%x->0x%x", 1206 cmd, 10*(100-timeout), regval1, regval2)); 1207 1208 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1209 for (timeout = 1000; ; ) { 1210 if ((regval1 & MI_COMMS_START) == 0) 1211 break; 1212 if (--timeout == 0) 1213 break; 1214 drv_usecwait(10); 1215 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1216 } 1217 1218 /* 1219 * Drop out early if the READ FAILED bit is set -- this chip 1220 * could be a 5703/4S, with a SerDes instead of a PHY! 1221 */ 1222 if (regval2 & MI_COMMS_READ_FAILED) 1223 return ((uint16_t)~0u); 1224 1225 if (timeout == 0) 1226 return ((uint16_t)~0u); 1227 1228 /* 1229 * The PRM says to wait 5us after seeing the START bit clear 1230 * and then re-read the register to get the final value of the 1231 * data field, in order to avoid a race condition where the 1232 * START bit is clear but the data field isn't yet valid. 1233 * 1234 * Note: we don't actually seem to be encounter this race; 1235 * except when the START bit is seen set again (see below), 1236 * the data field doesn't change during this 5us interval. 1237 */ 1238 drv_usecwait(5); 1239 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1240 1241 /* 1242 * Unfortunately, when following the PRMs instructions above, 1243 * we have occasionally seen the START bit set again(!) in the 1244 * value read after the 5us delay. This seems to be due to the 1245 * chip autonomously starting another MII access internally. 1246 * In such cases, the command/data/etc fields relate to the 1247 * internal command, rather than the one that we thought had 1248 * just finished. So in this case, we fall back to returning 1249 * the data from the original read that showed START clear. 1250 */ 1251 if (regval2 & MI_COMMS_START) { 1252 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1253 "MI_COMMS_START set after transaction; 0x%x->0x%x", 1254 cmd, regval1, regval2)); 1255 regval2 = regval1; 1256 } 1257 1258 if (regval2 & MI_COMMS_START) 1259 return ((uint16_t)~0u); 1260 1261 if (regval2 & MI_COMMS_READ_FAILED) 1262 return ((uint16_t)~0u); 1263 1264 return ((regval2 & MI_COMMS_DATA_MASK) >> MI_COMMS_DATA_SHIFT); 1265 } 1266 1267 uint16_t bge_mii_get16(bge_t *bgep, bge_regno_t regno); 1268 #pragma no_inline(bge_mii_get16) 1269 1270 uint16_t 1271 bge_mii_get16(bge_t *bgep, bge_regno_t regno) 1272 { 1273 BGE_TRACE(("bge_mii_get16($%p, 0x%lx)", 1274 (void *)bgep, regno)); 1275 1276 ASSERT(mutex_owned(bgep->genlock)); 1277 1278 if (DEVICE_5906_SERIES_CHIPSETS(bgep) && ((regno == MII_AUX_CONTROL) || 1279 (regno == MII_MSCONTROL))) 1280 return (0); 1281 1282 return (bge_mii_access(bgep, regno, 0, MI_COMMS_COMMAND_READ)); 1283 } 1284 1285 void bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data); 1286 #pragma no_inline(bge_mii_put16) 1287 1288 void 1289 bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data) 1290 { 1291 BGE_TRACE(("bge_mii_put16($%p, 0x%lx, 0x%x)", 1292 (void *)bgep, regno, data)); 1293 1294 ASSERT(mutex_owned(bgep->genlock)); 1295 1296 if (DEVICE_5906_SERIES_CHIPSETS(bgep) && ((regno == MII_AUX_CONTROL) || 1297 (regno == MII_MSCONTROL))) 1298 return; 1299 1300 (void) bge_mii_access(bgep, regno, data, MI_COMMS_COMMAND_WRITE); 1301 } 1302 1303 uint16_t 1304 bge_phydsp_read(bge_t *bgep, bge_regno_t regno) 1305 { 1306 BGE_TRACE(("bge_phydsp_read($%p, 0x%lx)", 1307 (void *)bgep, regno)); 1308 1309 ASSERT(mutex_owned(bgep->genlock)); 1310 1311 bge_mii_put16(bgep, MII_DSP_ADDRESS, regno); 1312 return bge_mii_get16(bgep, MII_DSP_RW_PORT); 1313 } 1314 1315 #pragma no_inline(bge_phydsp_write) 1316 1317 void 1318 bge_phydsp_write(bge_t *bgep, bge_regno_t regno, uint16_t data) 1319 { 1320 BGE_TRACE(("bge_phydsp_write($%p, 0x%lx, 0x%x)", 1321 (void *)bgep, regno, data)); 1322 1323 ASSERT(mutex_owned(bgep->genlock)); 1324 1325 bge_mii_put16(bgep, MII_DSP_ADDRESS, regno); 1326 bge_mii_put16(bgep, MII_DSP_RW_PORT, data); 1327 } 1328 1329 #undef BGE_DBG 1330 #define BGE_DBG BGE_DBG_SEEPROM /* debug flag for this code */ 1331 1332 #if BGE_SEE_IO32 || BGE_FLASH_IO32 1333 1334 /* 1335 * Basic SEEPROM get/set access routine 1336 * 1337 * This uses the chip's SEEPROM auto-access method, controlled by the 1338 * Serial EEPROM Address/Data Registers at 0x6838/683c, so the CPU 1339 * doesn't have to fiddle with the individual bits. 1340 * 1341 * The caller should hold <genlock> and *also* have already acquired 1342 * the right to access the SEEPROM, via bge_nvmem_acquire() above. 1343 * 1344 * Return value: 1345 * 0 on success, 1346 * ENODATA on access timeout (maybe retryable: device may just be busy) 1347 * EPROTO on other h/w or s/w errors. 1348 * 1349 * <*dp> is an input to a SEEPROM_ACCESS_WRITE operation, or an output 1350 * from a (successful) SEEPROM_ACCESS_READ. 1351 */ 1352 static int bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1353 uint32_t *dp); 1354 #pragma no_inline(bge_seeprom_access) 1355 1356 static int 1357 bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1358 { 1359 uint32_t tries; 1360 uint32_t regval; 1361 1362 ASSERT(mutex_owned(bgep->genlock)); 1363 1364 /* 1365 * On the newer chips that support both SEEPROM & Flash, we need 1366 * to specifically enable SEEPROM access (Flash is the default). 1367 * On older chips, we don't; SEEPROM is the only NVtype supported, 1368 * and the NVM control registers don't exist ... 1369 */ 1370 switch (bgep->chipid.nvtype) { 1371 case BGE_NVTYPE_NONE: 1372 case BGE_NVTYPE_UNKNOWN: 1373 _NOTE(NOTREACHED) 1374 case BGE_NVTYPE_SEEPROM: 1375 break; 1376 1377 case BGE_NVTYPE_LEGACY_SEEPROM: 1378 case BGE_NVTYPE_UNBUFFERED_FLASH: 1379 case BGE_NVTYPE_BUFFERED_FLASH: 1380 default: 1381 bge_reg_set32(bgep, NVM_CONFIG1_REG, 1382 NVM_CFG1_LEGACY_SEEPROM_MODE); 1383 break; 1384 } 1385 1386 /* 1387 * Check there's no command in progress. 1388 * 1389 * Note: this *shouldn't* ever find that there is a command 1390 * in progress, because we already hold the <genlock> mutex. 1391 * Also, to ensure we don't have a conflict with the chip's 1392 * internal firmware or a process accessing the same (shared) 1393 * SEEPROM through the other port of a 5704, we've already 1394 * been through the "software arbitration" protocol. 1395 * So this is just a final consistency check: we shouldn't 1396 * see EITHER the START bit (command started but not complete) 1397 * OR the COMPLETE bit (command completed but not cleared). 1398 */ 1399 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1400 if (regval & SEEPROM_ACCESS_START) 1401 return (EPROTO); 1402 if (regval & SEEPROM_ACCESS_COMPLETE) 1403 return (EPROTO); 1404 1405 /* 1406 * Assemble the command ... 1407 */ 1408 cmd |= addr & SEEPROM_ACCESS_ADDRESS_MASK; 1409 addr >>= SEEPROM_ACCESS_ADDRESS_SIZE; 1410 addr <<= SEEPROM_ACCESS_DEVID_SHIFT; 1411 cmd |= addr & SEEPROM_ACCESS_DEVID_MASK; 1412 cmd |= SEEPROM_ACCESS_START; 1413 cmd |= SEEPROM_ACCESS_COMPLETE; 1414 cmd |= regval & SEEPROM_ACCESS_HALFCLOCK_MASK; 1415 1416 bge_reg_put32(bgep, SERIAL_EEPROM_DATA_REG, *dp); 1417 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, cmd); 1418 1419 /* 1420 * By observation, a successful access takes ~20us on a 5703/4, 1421 * but apparently much longer (up to 1000us) on the obsolescent 1422 * BCM5700/BCM5701. We want to be sure we don't get any false 1423 * timeouts here; but OTOH, we don't want a bogus access to lock 1424 * out interrupts for longer than necessary. So we'll allow up 1425 * to 1000us ... 1426 */ 1427 for (tries = 0; tries < 1000; ++tries) { 1428 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1429 if (regval & SEEPROM_ACCESS_COMPLETE) 1430 break; 1431 drv_usecwait(1); 1432 } 1433 1434 if (regval & SEEPROM_ACCESS_COMPLETE) { 1435 /* 1436 * All OK; read the SEEPROM data register, then write back 1437 * the value read from the address register in order to 1438 * clear the <complete> bit and leave the SEEPROM access 1439 * state machine idle, ready for the next access ... 1440 */ 1441 BGE_DEBUG(("bge_seeprom_access: complete after %d us", tries)); 1442 *dp = bge_reg_get32(bgep, SERIAL_EEPROM_DATA_REG); 1443 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, regval); 1444 return (0); 1445 } 1446 1447 /* 1448 * Hmm ... what happened here? 1449 * 1450 * Most likely, the user addressed a non-existent SEEPROM. Or 1451 * maybe the SEEPROM was busy internally (e.g. processing a write) 1452 * and didn't respond to being addressed. Either way, it's left 1453 * the SEEPROM access state machine wedged. So we'll reset it 1454 * before we leave, so it's ready for next time ... 1455 */ 1456 BGE_DEBUG(("bge_seeprom_access: timed out after %d us", tries)); 1457 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 1458 return (ENODATA); 1459 } 1460 1461 /* 1462 * Basic Flash get/set access routine 1463 * 1464 * These use the chip's Flash auto-access method, controlled by the 1465 * Flash Access Registers at 0x7000-701c, so the CPU doesn't have to 1466 * fiddle with the individual bits. 1467 * 1468 * The caller should hold <genlock> and *also* have already acquired 1469 * the right to access the Flash, via bge_nvmem_acquire() above. 1470 * 1471 * Return value: 1472 * 0 on success, 1473 * ENODATA on access timeout (maybe retryable: device may just be busy) 1474 * ENODEV if the NVmem device is missing or otherwise unusable 1475 * 1476 * <*dp> is an input to a NVM_FLASH_CMD_WR operation, or an output 1477 * from a (successful) NVM_FLASH_CMD_RD. 1478 */ 1479 static int bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1480 uint32_t *dp); 1481 #pragma no_inline(bge_flash_access) 1482 1483 static int 1484 bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1485 { 1486 uint32_t tries; 1487 uint32_t regval; 1488 1489 ASSERT(mutex_owned(bgep->genlock)); 1490 1491 /* 1492 * On the newer chips that support both SEEPROM & Flash, we need 1493 * to specifically disable SEEPROM access while accessing Flash. 1494 * The older chips don't support Flash, and the NVM registers don't 1495 * exist, so we shouldn't be here at all! 1496 */ 1497 switch (bgep->chipid.nvtype) { 1498 case BGE_NVTYPE_NONE: 1499 case BGE_NVTYPE_UNKNOWN: 1500 _NOTE(NOTREACHED) 1501 case BGE_NVTYPE_SEEPROM: 1502 return (ENODEV); 1503 1504 case BGE_NVTYPE_LEGACY_SEEPROM: 1505 case BGE_NVTYPE_UNBUFFERED_FLASH: 1506 case BGE_NVTYPE_BUFFERED_FLASH: 1507 default: 1508 bge_reg_clr32(bgep, NVM_CONFIG1_REG, 1509 NVM_CFG1_LEGACY_SEEPROM_MODE); 1510 break; 1511 } 1512 1513 /* 1514 * Assemble the command ... 1515 */ 1516 addr &= NVM_FLASH_ADDR_MASK; 1517 cmd |= NVM_FLASH_CMD_DOIT; 1518 cmd |= NVM_FLASH_CMD_FIRST; 1519 cmd |= NVM_FLASH_CMD_LAST; 1520 cmd |= NVM_FLASH_CMD_DONE; 1521 1522 bge_reg_put32(bgep, NVM_FLASH_WRITE_REG, *dp); 1523 bge_reg_put32(bgep, NVM_FLASH_ADDR_REG, addr); 1524 bge_reg_put32(bgep, NVM_FLASH_CMD_REG, cmd); 1525 1526 /* 1527 * Allow up to 1000ms ... 1528 */ 1529 for (tries = 0; tries < 1000; ++tries) { 1530 regval = bge_reg_get32(bgep, NVM_FLASH_CMD_REG); 1531 if (regval & NVM_FLASH_CMD_DONE) 1532 break; 1533 drv_usecwait(1); 1534 } 1535 1536 if (regval & NVM_FLASH_CMD_DONE) { 1537 /* 1538 * All OK; read the data from the Flash read register 1539 */ 1540 BGE_DEBUG(("bge_flash_access: complete after %d us", tries)); 1541 *dp = bge_reg_get32(bgep, NVM_FLASH_READ_REG); 1542 return (0); 1543 } 1544 1545 /* 1546 * Hmm ... what happened here? 1547 * 1548 * Most likely, the user addressed a non-existent Flash. Or 1549 * maybe the Flash was busy internally (e.g. processing a write) 1550 * and didn't respond to being addressed. Either way, there's 1551 * nothing we can here ... 1552 */ 1553 BGE_DEBUG(("bge_flash_access: timed out after %d us", tries)); 1554 return (ENODATA); 1555 } 1556 1557 /* 1558 * The next two functions regulate access to the NVram (if fitted). 1559 * 1560 * On a 5704 (dual core) chip, there's only one SEEPROM and one Flash 1561 * (SPI) interface, but they can be accessed through either port. These 1562 * are managed by different instance of this driver and have no software 1563 * state in common. 1564 * 1565 * In addition (and even on a single core chip) the chip's internal 1566 * firmware can access the SEEPROM/Flash, most notably after a RESET 1567 * when it may download code to run internally. 1568 * 1569 * So we need to arbitrate between these various software agents. For 1570 * this purpose, the chip provides the Software Arbitration Register, 1571 * which implements hardware(!) arbitration. 1572 * 1573 * This functionality didn't exist on older (5700/5701) chips, so there's 1574 * nothing we can do by way of arbitration on those; also, if there's no 1575 * SEEPROM/Flash fitted (or we couldn't determine what type), there's also 1576 * nothing to do. 1577 * 1578 * The internal firmware appears to use Request 0, which is the highest 1579 * priority. So we'd like to use Request 2, leaving one higher and one 1580 * lower for any future developments ... but apparently this doesn't 1581 * always work. So for now, the code uses Request 1 ;-( 1582 */ 1583 1584 #define NVM_READ_REQ NVM_READ_REQ1 1585 #define NVM_RESET_REQ NVM_RESET_REQ1 1586 #define NVM_SET_REQ NVM_SET_REQ1 1587 1588 static void bge_nvmem_relinquish(bge_t *bgep); 1589 #pragma no_inline(bge_nvmem_relinquish) 1590 1591 static void 1592 bge_nvmem_relinquish(bge_t *bgep) 1593 { 1594 ASSERT(mutex_owned(bgep->genlock)); 1595 1596 switch (bgep->chipid.nvtype) { 1597 case BGE_NVTYPE_NONE: 1598 case BGE_NVTYPE_UNKNOWN: 1599 _NOTE(NOTREACHED) 1600 return; 1601 1602 case BGE_NVTYPE_SEEPROM: 1603 /* 1604 * No arbitration performed, no release needed 1605 */ 1606 return; 1607 1608 case BGE_NVTYPE_LEGACY_SEEPROM: 1609 case BGE_NVTYPE_UNBUFFERED_FLASH: 1610 case BGE_NVTYPE_BUFFERED_FLASH: 1611 default: 1612 break; 1613 } 1614 1615 /* 1616 * Our own request should be present (whether or not granted) ... 1617 */ 1618 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1619 1620 /* 1621 * ... this will make it go away. 1622 */ 1623 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_RESET_REQ); 1624 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1625 } 1626 1627 /* 1628 * Arbitrate for access to the NVmem, if necessary 1629 * 1630 * Return value: 1631 * 0 on success 1632 * EAGAIN if the device is in use (retryable) 1633 * ENODEV if the NVmem device is missing or otherwise unusable 1634 */ 1635 static int bge_nvmem_acquire(bge_t *bgep); 1636 #pragma no_inline(bge_nvmem_acquire) 1637 1638 static int 1639 bge_nvmem_acquire(bge_t *bgep) 1640 { 1641 uint32_t regval; 1642 uint32_t tries; 1643 1644 ASSERT(mutex_owned(bgep->genlock)); 1645 1646 switch (bgep->chipid.nvtype) { 1647 case BGE_NVTYPE_NONE: 1648 case BGE_NVTYPE_UNKNOWN: 1649 /* 1650 * Access denied: no (recognisable) device fitted 1651 */ 1652 return (ENODEV); 1653 1654 case BGE_NVTYPE_SEEPROM: 1655 /* 1656 * Access granted: no arbitration needed (or possible) 1657 */ 1658 return (0); 1659 1660 case BGE_NVTYPE_LEGACY_SEEPROM: 1661 case BGE_NVTYPE_UNBUFFERED_FLASH: 1662 case BGE_NVTYPE_BUFFERED_FLASH: 1663 default: 1664 /* 1665 * Access conditional: conduct arbitration protocol 1666 */ 1667 break; 1668 } 1669 1670 /* 1671 * We're holding the per-port mutex <genlock>, so no-one other 1672 * thread can be attempting to access the NVmem through *this* 1673 * port. But it could be in use by the *other* port (of a 5704), 1674 * or by the chip's internal firmware, so we have to go through 1675 * the full (hardware) arbitration protocol ... 1676 * 1677 * Note that *because* we're holding <genlock>, the interrupt handler 1678 * won't be able to progress. So we're only willing to spin for a 1679 * fairly short time. Specifically: 1680 * 1681 * We *must* wait long enough for the hardware to resolve all 1682 * requests and determine the winner. Fortunately, this is 1683 * "almost instantaneous", even as observed by GHz CPUs. 1684 * 1685 * A successful access by another Solaris thread (via either 1686 * port) typically takes ~20us. So waiting a bit longer than 1687 * that will give a good chance of success, if the other user 1688 * *is* another thread on the other port. 1689 * 1690 * However, the internal firmware can hold on to the NVmem 1691 * for *much* longer: at least 10 milliseconds just after a 1692 * RESET, and maybe even longer if the NVmem actually contains 1693 * code to download and run on the internal CPUs. 1694 * 1695 * So, we'll allow 50us; if that's not enough then it's up to the 1696 * caller to retry later (hence the choice of return code EAGAIN). 1697 */ 1698 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1699 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_SET_REQ); 1700 1701 for (tries = 0; tries < 50; ++tries) { 1702 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1703 if (regval & NVM_WON_REQ1) 1704 break; 1705 drv_usecwait(1); 1706 } 1707 1708 if (regval & NVM_WON_REQ1) { 1709 BGE_DEBUG(("bge_nvmem_acquire: won after %d us", tries)); 1710 return (0); 1711 } 1712 1713 /* 1714 * Somebody else must be accessing the NVmem, so abandon our 1715 * attempt take control of it. The caller can try again later ... 1716 */ 1717 BGE_DEBUG(("bge_nvmem_acquire: lost after %d us", tries)); 1718 bge_nvmem_relinquish(bgep); 1719 return (EAGAIN); 1720 } 1721 1722 /* 1723 * This code assumes that the GPIO1 bit has been wired up to the NVmem 1724 * write protect line in such a way that the NVmem is protected when 1725 * GPIO1 is an input, or is an output but driven high. Thus, to make the 1726 * NVmem writable we have to change GPIO1 to an output AND drive it low. 1727 * 1728 * Note: there's only one set of GPIO pins on a 5704, even though they 1729 * can be accessed through either port. So the chip has to resolve what 1730 * happens if the two ports program a single pin differently ... the rule 1731 * it uses is that if the ports disagree about the *direction* of a pin, 1732 * "output" wins over "input", but if they disagree about its *value* as 1733 * an output, then the pin is TRISTATED instead! In such a case, no-one 1734 * wins, and the external signal does whatever the external circuitry 1735 * defines as the default -- which we've assumed is the PROTECTED state. 1736 * So, we always change GPIO1 back to being an *input* whenever we're not 1737 * specifically using it to unprotect the NVmem. This allows either port 1738 * to update the NVmem, although obviously only one at a time! 1739 * 1740 * The caller should hold <genlock> and *also* have already acquired the 1741 * right to access the NVmem, via bge_nvmem_acquire() above. 1742 */ 1743 static void bge_nvmem_protect(bge_t *bgep, boolean_t protect); 1744 #pragma inline(bge_nvmem_protect) 1745 1746 static void 1747 bge_nvmem_protect(bge_t *bgep, boolean_t protect) 1748 { 1749 uint32_t regval; 1750 1751 ASSERT(mutex_owned(bgep->genlock)); 1752 1753 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 1754 if (protect) { 1755 regval |= MLCR_MISC_PINS_OUTPUT_1; 1756 regval &= ~MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1757 } else { 1758 regval &= ~MLCR_MISC_PINS_OUTPUT_1; 1759 regval |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1760 } 1761 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, regval); 1762 } 1763 1764 /* 1765 * Now put it all together ... 1766 * 1767 * Try to acquire control of the NVmem; if successful, then: 1768 * unprotect it (if we want to write to it) 1769 * perform the requested access 1770 * reprotect it (after a write) 1771 * relinquish control 1772 * 1773 * Return value: 1774 * 0 on success, 1775 * EAGAIN if the device is in use (retryable) 1776 * ENODATA on access timeout (maybe retryable: device may just be busy) 1777 * ENODEV if the NVmem device is missing or otherwise unusable 1778 * EPROTO on other h/w or s/w errors. 1779 */ 1780 static int 1781 bge_nvmem_rw32(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1782 { 1783 int err; 1784 1785 if ((err = bge_nvmem_acquire(bgep)) == 0) { 1786 switch (cmd) { 1787 case BGE_SEE_READ: 1788 err = bge_seeprom_access(bgep, 1789 SEEPROM_ACCESS_READ, addr, dp); 1790 break; 1791 1792 case BGE_SEE_WRITE: 1793 bge_nvmem_protect(bgep, B_FALSE); 1794 err = bge_seeprom_access(bgep, 1795 SEEPROM_ACCESS_WRITE, addr, dp); 1796 bge_nvmem_protect(bgep, B_TRUE); 1797 break; 1798 1799 case BGE_FLASH_READ: 1800 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1801 DEVICE_5723_SERIES_CHIPSETS(bgep) || 1802 DEVICE_5717_SERIES_CHIPSETS(bgep) || 1803 DEVICE_5725_SERIES_CHIPSETS(bgep) || 1804 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1805 bge_reg_set32(bgep, NVM_ACCESS_REG, 1806 NVM_ACCESS_ENABLE); 1807 } 1808 err = bge_flash_access(bgep, 1809 NVM_FLASH_CMD_RD, addr, dp); 1810 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1811 DEVICE_5723_SERIES_CHIPSETS(bgep) || 1812 DEVICE_5717_SERIES_CHIPSETS(bgep) || 1813 DEVICE_5725_SERIES_CHIPSETS(bgep) || 1814 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1815 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1816 NVM_ACCESS_ENABLE); 1817 } 1818 break; 1819 1820 case BGE_FLASH_WRITE: 1821 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1822 DEVICE_5723_SERIES_CHIPSETS(bgep) || 1823 DEVICE_5717_SERIES_CHIPSETS(bgep) || 1824 DEVICE_5725_SERIES_CHIPSETS(bgep) || 1825 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1826 bge_reg_set32(bgep, NVM_ACCESS_REG, 1827 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1828 } 1829 bge_nvmem_protect(bgep, B_FALSE); 1830 err = bge_flash_access(bgep, 1831 NVM_FLASH_CMD_WR, addr, dp); 1832 bge_nvmem_protect(bgep, B_TRUE); 1833 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1834 DEVICE_5723_SERIES_CHIPSETS(bgep) || 1835 DEVICE_5717_SERIES_CHIPSETS(bgep) || 1836 DEVICE_5725_SERIES_CHIPSETS(bgep) || 1837 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1838 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1839 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1840 } 1841 1842 break; 1843 1844 default: 1845 _NOTE(NOTREACHED) 1846 break; 1847 } 1848 bge_nvmem_relinquish(bgep); 1849 } 1850 1851 BGE_DEBUG(("bge_nvmem_rw32: err %d", err)); 1852 return (err); 1853 } 1854 1855 static uint32_t 1856 bge_nvmem_access_cmd(bge_t *bgep, boolean_t read) 1857 { 1858 switch (bgep->chipid.nvtype) { 1859 case BGE_NVTYPE_NONE: 1860 case BGE_NVTYPE_UNKNOWN: 1861 default: 1862 return 0; 1863 1864 case BGE_NVTYPE_SEEPROM: 1865 case BGE_NVTYPE_LEGACY_SEEPROM: 1866 return (read ? BGE_SEE_READ : BGE_SEE_WRITE); 1867 1868 case BGE_NVTYPE_UNBUFFERED_FLASH: 1869 case BGE_NVTYPE_BUFFERED_FLASH: 1870 return (read ? BGE_FLASH_READ : BGE_FLASH_WRITE); 1871 } 1872 } 1873 1874 1875 int 1876 bge_nvmem_read32(bge_t *bgep, bge_regno_t addr, uint32_t *dp) 1877 { 1878 return (bge_nvmem_rw32(bgep, bge_nvmem_access_cmd(bgep, B_TRUE), 1879 addr, dp)); 1880 } 1881 1882 1883 int 1884 bge_nvmem_write32(bge_t *bgep, bge_regno_t addr, uint32_t *dp) 1885 { 1886 return (bge_nvmem_rw32(bgep, bge_nvmem_access_cmd(bgep, B_FALSE), 1887 addr, dp)); 1888 } 1889 1890 1891 /* 1892 * Attempt to get a MAC address from the SEEPROM or Flash, if any 1893 */ 1894 static uint64_t bge_get_nvmac(bge_t *bgep); 1895 #pragma no_inline(bge_get_nvmac) 1896 1897 static uint64_t 1898 bge_get_nvmac(bge_t *bgep) 1899 { 1900 uint32_t mac_high; 1901 uint32_t mac_low; 1902 uint32_t addr; 1903 uint32_t cmd; 1904 uint64_t mac; 1905 1906 BGE_TRACE(("bge_get_nvmac($%p)", 1907 (void *)bgep)); 1908 1909 switch (bgep->chipid.nvtype) { 1910 case BGE_NVTYPE_NONE: 1911 case BGE_NVTYPE_UNKNOWN: 1912 default: 1913 return (0ULL); 1914 1915 case BGE_NVTYPE_SEEPROM: 1916 case BGE_NVTYPE_LEGACY_SEEPROM: 1917 cmd = BGE_SEE_READ; 1918 break; 1919 1920 case BGE_NVTYPE_UNBUFFERED_FLASH: 1921 case BGE_NVTYPE_BUFFERED_FLASH: 1922 cmd = BGE_FLASH_READ; 1923 break; 1924 } 1925 1926 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) 1927 addr = NVMEM_DATA_MAC_ADDRESS_5906; 1928 else 1929 addr = NVMEM_DATA_MAC_ADDRESS; 1930 1931 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_high)) 1932 return (0ULL); 1933 addr += 4; 1934 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_low)) 1935 return (0ULL); 1936 1937 /* 1938 * The Broadcom chip is natively BIG-endian, so that's how the 1939 * MAC address is represented in NVmem. We may need to swap it 1940 * around on a little-endian host ... 1941 */ 1942 #ifdef _BIG_ENDIAN 1943 mac = mac_high; 1944 mac = mac << 32; 1945 mac |= mac_low; 1946 #else 1947 mac = BGE_BSWAP_32(mac_high); 1948 mac = mac << 32; 1949 mac |= BGE_BSWAP_32(mac_low); 1950 #endif /* _BIG_ENDIAN */ 1951 1952 return (mac); 1953 } 1954 1955 #else /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1956 1957 /* 1958 * Dummy version for when we're not supporting NVmem access 1959 */ 1960 static uint64_t bge_get_nvmac(bge_t *bgep); 1961 #pragma inline(bge_get_nvmac) 1962 1963 static uint64_t 1964 bge_get_nvmac(bge_t *bgep) 1965 { 1966 _NOTE(ARGUNUSED(bgep)) 1967 return (0ULL); 1968 } 1969 1970 #endif /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1971 1972 /* 1973 * Determine the type of NVmem that is (or may be) attached to this chip, 1974 */ 1975 static enum bge_nvmem_type bge_nvmem_id(bge_t *bgep); 1976 #pragma no_inline(bge_nvmem_id) 1977 1978 static enum bge_nvmem_type 1979 bge_nvmem_id(bge_t *bgep) 1980 { 1981 enum bge_nvmem_type nvtype; 1982 uint32_t config1; 1983 1984 BGE_TRACE(("bge_nvmem_id($%p)", 1985 (void *)bgep)); 1986 1987 switch (bgep->chipid.device) { 1988 default: 1989 /* 1990 * We shouldn't get here; it means we don't recognise 1991 * the chip, which means we don't know how to determine 1992 * what sort of NVmem (if any) it has. So we'll say 1993 * NONE, to disable the NVmem access code ... 1994 */ 1995 nvtype = BGE_NVTYPE_NONE; 1996 break; 1997 1998 case DEVICE_ID_5700: 1999 case DEVICE_ID_5700x: 2000 case DEVICE_ID_5701: 2001 /* 2002 * These devices support *only* SEEPROMs 2003 */ 2004 nvtype = BGE_NVTYPE_SEEPROM; 2005 break; 2006 2007 case DEVICE_ID_5702: 2008 case DEVICE_ID_5702fe: 2009 case DEVICE_ID_5703C: 2010 case DEVICE_ID_5703S: 2011 case DEVICE_ID_5704C: 2012 case DEVICE_ID_5704S: 2013 case DEVICE_ID_5704: 2014 case DEVICE_ID_5705M: 2015 case DEVICE_ID_5705C: 2016 case DEVICE_ID_5705_2: 2017 case DEVICE_ID_5717: 2018 case DEVICE_ID_5718: 2019 case DEVICE_ID_5719: 2020 case DEVICE_ID_5720: 2021 case DEVICE_ID_5724: 2022 case DEVICE_ID_5725: 2023 case DEVICE_ID_5727: 2024 case DEVICE_ID_57780: 2025 case DEVICE_ID_5780: 2026 case DEVICE_ID_5782: 2027 case DEVICE_ID_5785: 2028 case DEVICE_ID_5787: 2029 case DEVICE_ID_5787M: 2030 case DEVICE_ID_5788: 2031 case DEVICE_ID_5789: 2032 case DEVICE_ID_5751: 2033 case DEVICE_ID_5751M: 2034 case DEVICE_ID_5752: 2035 case DEVICE_ID_5752M: 2036 case DEVICE_ID_5754: 2037 case DEVICE_ID_5755: 2038 case DEVICE_ID_5755M: 2039 case DEVICE_ID_5756M: 2040 case DEVICE_ID_5721: 2041 case DEVICE_ID_5722: 2042 case DEVICE_ID_5723: 2043 case DEVICE_ID_5761: 2044 case DEVICE_ID_5761E: 2045 case DEVICE_ID_5764: 2046 case DEVICE_ID_5714C: 2047 case DEVICE_ID_5714S: 2048 case DEVICE_ID_5715C: 2049 case DEVICE_ID_5715S: 2050 config1 = bge_reg_get32(bgep, NVM_CONFIG1_REG); 2051 if (config1 & NVM_CFG1_FLASH_MODE) 2052 if (config1 & NVM_CFG1_BUFFERED_MODE) 2053 nvtype = BGE_NVTYPE_BUFFERED_FLASH; 2054 else 2055 nvtype = BGE_NVTYPE_UNBUFFERED_FLASH; 2056 else 2057 nvtype = BGE_NVTYPE_LEGACY_SEEPROM; 2058 break; 2059 case DEVICE_ID_5906: 2060 case DEVICE_ID_5906M: 2061 nvtype = BGE_NVTYPE_BUFFERED_FLASH; 2062 break; 2063 } 2064 2065 return (nvtype); 2066 } 2067 2068 #undef BGE_DBG 2069 #define BGE_DBG BGE_DBG_APE /* debug flag for this code */ 2070 2071 uint32_t bge_ape_get32(bge_t *bgep, bge_regno_t regno); 2072 #pragma inline(bge_ape_get32) 2073 2074 uint32_t 2075 bge_ape_get32(bge_t *bgep, bge_regno_t regno) 2076 { 2077 BGE_TRACE(("bge_ape_get32($%p, 0x%lx)", 2078 (void *)bgep, regno)); 2079 2080 return (ddi_get32(bgep->ape_handle, APE_ADDR(bgep, regno))); 2081 } 2082 2083 void bge_ape_put32(bge_t *bgep, bge_regno_t regno, uint32_t data); 2084 #pragma inline(bge_ape_put32) 2085 2086 void 2087 bge_ape_put32(bge_t *bgep, bge_regno_t regno, uint32_t data) 2088 { 2089 BGE_TRACE(("bge_ape_put32($%p, 0x%lx, 0x%x)", 2090 (void *)bgep, regno, data)); 2091 2092 ddi_put32(bgep->ape_handle, APE_ADDR(bgep, regno), data); 2093 BGE_PCICHK(bgep); 2094 } 2095 2096 void 2097 bge_ape_lock_init(bge_t *bgep) 2098 { 2099 int i; 2100 uint32_t regbase; 2101 uint32_t bit; 2102 2103 BGE_TRACE(("bge_ape_lock_init($%p)", (void *)bgep)); 2104 2105 if (bgep->chipid.device == DEVICE_ID_5761) 2106 regbase = BGE_APE_LOCK_GRANT; 2107 else 2108 regbase = BGE_APE_PER_LOCK_GRANT; 2109 2110 /* Make sure the driver hasn't any stale locks. */ 2111 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) { 2112 switch (i) { 2113 case BGE_APE_LOCK_PHY0: 2114 case BGE_APE_LOCK_PHY1: 2115 case BGE_APE_LOCK_PHY2: 2116 case BGE_APE_LOCK_PHY3: 2117 bit = APE_LOCK_GRANT_DRIVER; 2118 break; 2119 default: 2120 if (!bgep->pci_func) 2121 bit = APE_LOCK_GRANT_DRIVER; 2122 else 2123 bit = 1 << bgep->pci_func; 2124 } 2125 bge_ape_put32(bgep, regbase + 4 * i, bit); 2126 } 2127 } 2128 2129 static int 2130 bge_ape_lock(bge_t *bgep, int locknum) 2131 { 2132 int i, off; 2133 int ret = 0; 2134 uint32_t status; 2135 uint32_t req; 2136 uint32_t gnt; 2137 uint32_t bit; 2138 2139 BGE_TRACE(("bge_ape_lock($%p, 0x%x)", (void *)bgep, locknum)); 2140 2141 if (!bgep->ape_enabled) 2142 return (0); 2143 2144 switch (locknum) { 2145 case BGE_APE_LOCK_GPIO: 2146 if (bgep->chipid.device == DEVICE_ID_5761) 2147 return (0); 2148 /* FALLTHROUGH */ 2149 case BGE_APE_LOCK_GRC: 2150 case BGE_APE_LOCK_MEM: 2151 if (!bgep->pci_func) 2152 bit = APE_LOCK_REQ_DRIVER; 2153 else 2154 bit = 1 << bgep->pci_func; 2155 break; 2156 case BGE_APE_LOCK_PHY0: 2157 case BGE_APE_LOCK_PHY1: 2158 case BGE_APE_LOCK_PHY2: 2159 case BGE_APE_LOCK_PHY3: 2160 bit = APE_LOCK_REQ_DRIVER; 2161 break; 2162 default: 2163 return (-1); 2164 } 2165 2166 if (bgep->chipid.device == DEVICE_ID_5761) { 2167 req = BGE_APE_LOCK_REQ; 2168 gnt = BGE_APE_LOCK_GRANT; 2169 } else { 2170 req = BGE_APE_PER_LOCK_REQ; 2171 gnt = BGE_APE_PER_LOCK_GRANT; 2172 } 2173 2174 off = 4 * locknum; 2175 2176 bge_ape_put32(bgep, req + off, bit); 2177 2178 /* Wait for up to 1 millisecond to acquire lock. */ 2179 for (i = 0; i < 100; i++) { 2180 status = bge_ape_get32(bgep, gnt + off); 2181 if (status == bit) 2182 break; 2183 drv_usecwait(10); 2184 } 2185 2186 if (status != bit) { 2187 /* Revoke the lock request. */ 2188 bge_ape_put32(bgep, gnt + off, bit); 2189 ret = -1; 2190 } 2191 2192 return (ret); 2193 } 2194 2195 static void 2196 bge_ape_unlock(bge_t *bgep, int locknum) 2197 { 2198 uint32_t gnt; 2199 uint32_t bit; 2200 2201 BGE_TRACE(("bge_ape_unlock($%p, 0x%x)", (void *)bgep, locknum)); 2202 2203 if (!bgep->ape_enabled) 2204 return; 2205 2206 switch (locknum) { 2207 case BGE_APE_LOCK_GPIO: 2208 if (bgep->chipid.device == DEVICE_ID_5761) 2209 return; 2210 /* FALLTHROUGH */ 2211 case BGE_APE_LOCK_GRC: 2212 case BGE_APE_LOCK_MEM: 2213 if (!bgep->pci_func) 2214 bit = APE_LOCK_GRANT_DRIVER; 2215 else 2216 bit = 1 << bgep->pci_func; 2217 break; 2218 case BGE_APE_LOCK_PHY0: 2219 case BGE_APE_LOCK_PHY1: 2220 case BGE_APE_LOCK_PHY2: 2221 case BGE_APE_LOCK_PHY3: 2222 bit = APE_LOCK_GRANT_DRIVER; 2223 break; 2224 default: 2225 return; 2226 } 2227 2228 if (bgep->chipid.device == DEVICE_ID_5761) 2229 gnt = BGE_APE_LOCK_GRANT; 2230 else 2231 gnt = BGE_APE_PER_LOCK_GRANT; 2232 2233 bge_ape_put32(bgep, gnt + 4 * locknum, bit); 2234 } 2235 2236 /* wait for pending event to finish, if successful returns with MEM locked */ 2237 static int 2238 bge_ape_event_lock(bge_t *bgep, uint32_t timeout_us) 2239 { 2240 uint32_t apedata; 2241 2242 BGE_TRACE(("bge_ape_event_lock($%p, %d)", (void *)bgep, timeout_us)); 2243 2244 ASSERT(timeout_us > 0); 2245 2246 while (timeout_us) { 2247 if (bge_ape_lock(bgep, BGE_APE_LOCK_MEM)) 2248 return (-1); 2249 2250 apedata = bge_ape_get32(bgep, BGE_APE_EVENT_STATUS); 2251 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) 2252 break; 2253 2254 bge_ape_unlock(bgep, BGE_APE_LOCK_MEM); 2255 2256 drv_usecwait(10); 2257 timeout_us -= (timeout_us > 10) ? 10 : timeout_us; 2258 } 2259 2260 return (timeout_us ? 0 : -1); 2261 } 2262 2263 /* wait for pending event to finish, returns non-zero if not finished */ 2264 static int 2265 bge_ape_wait_for_event(bge_t *bgep, uint32_t timeout_us) 2266 { 2267 uint32_t i; 2268 uint32_t apedata; 2269 2270 BGE_TRACE(("bge_ape_wait_for_event($%p, %d)", (void *)bgep, timeout_us)); 2271 2272 ASSERT(timeout_us > 0); 2273 2274 for (i = 0; i < timeout_us / 10; i++) { 2275 apedata = bge_ape_get32(bgep, BGE_APE_EVENT_STATUS); 2276 2277 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) 2278 break; 2279 2280 drv_usecwait(10); 2281 } 2282 2283 return (i == timeout_us / 10); 2284 } 2285 2286 int 2287 bge_ape_scratchpad_read(bge_t *bgep, uint32_t *data, uint32_t base_off, 2288 uint32_t lenToRead) 2289 { 2290 int err; 2291 uint32_t i; 2292 uint32_t bufoff; 2293 uint32_t msgoff; 2294 uint32_t maxlen; 2295 uint32_t apedata; 2296 2297 BGE_TRACE(("bge_ape_scratchpad_read($%p, %p, 0x%0x, %d)", 2298 (void *)bgep, (void*)data, base_off, lenToRead)); 2299 2300 if (!bgep->ape_has_ncsi) 2301 return (0); 2302 2303 apedata = bge_ape_get32(bgep, BGE_APE_SEG_SIG); 2304 if (apedata != APE_SEG_SIG_MAGIC) 2305 return (-1); 2306 2307 apedata = bge_ape_get32(bgep, BGE_APE_FW_STATUS); 2308 if (!(apedata & APE_FW_STATUS_READY)) 2309 return (-1); 2310 2311 bufoff = (bge_ape_get32(bgep, BGE_APE_SEG_MSG_BUF_OFF) + 2312 BGE_APE_SHMEM_BASE); 2313 msgoff = bufoff + 2 * sizeof(uint32_t); 2314 maxlen = bge_ape_get32(bgep, BGE_APE_SEG_MSG_BUF_LEN); 2315 2316 while (lenToRead) { 2317 uint32_t transferLen; 2318 2319 /* Cap xfer sizes to scratchpad limits. */ 2320 transferLen = (lenToRead > maxlen) ? maxlen : lenToRead; 2321 lenToRead -= transferLen; 2322 2323 apedata = bge_ape_get32(bgep, BGE_APE_FW_STATUS); 2324 if (!(apedata & APE_FW_STATUS_READY)) 2325 return (-1); 2326 2327 /* Wait for up to 1 millisecond for APE to service previous event. */ 2328 err = bge_ape_event_lock(bgep, 1000); 2329 if (err) 2330 return (err); 2331 2332 apedata = (APE_EVENT_STATUS_DRIVER_EVNT | 2333 APE_EVENT_STATUS_SCRTCHPD_READ | 2334 APE_EVENT_STATUS_EVENT_PENDING); 2335 bge_ape_put32(bgep, BGE_APE_EVENT_STATUS, apedata); 2336 2337 bge_ape_put32(bgep, bufoff, base_off); 2338 bge_ape_put32(bgep, bufoff + sizeof(uint32_t), transferLen); 2339 2340 bge_ape_unlock(bgep, BGE_APE_LOCK_MEM); 2341 bge_ape_put32(bgep, BGE_APE_EVENT, APE_EVENT_1); 2342 2343 base_off += transferLen; 2344 2345 if (bge_ape_wait_for_event(bgep, 30000)) 2346 return (-1); 2347 2348 for (i = 0; transferLen; i += 4, transferLen -= 4) { 2349 uint32_t val = bge_ape_get32(bgep, msgoff + i); 2350 memcpy(data, &val, sizeof(uint32_t)); 2351 data++; 2352 } 2353 } 2354 2355 return (0); 2356 } 2357 2358 int 2359 bge_ape_scratchpad_write(bge_t *bgep, uint32_t dstoff, uint32_t *data, 2360 uint32_t lenToWrite) 2361 { 2362 int err; 2363 uint32_t i; 2364 uint32_t bufoff; 2365 uint32_t msgoff; 2366 uint32_t maxlen; 2367 uint32_t apedata; 2368 2369 BGE_TRACE(("bge_ape_scratchpad_write($%p, %d, %p, %d)", 2370 (void *)bgep, dstoff, data, lenToWrite)); 2371 2372 if (!bgep->ape_has_ncsi) 2373 return (0); 2374 2375 apedata = bge_ape_get32(bgep, BGE_APE_SEG_SIG); 2376 if (apedata != APE_SEG_SIG_MAGIC) 2377 return (-1); 2378 2379 apedata = bge_ape_get32(bgep, BGE_APE_FW_STATUS); 2380 if (!(apedata & APE_FW_STATUS_READY)) 2381 return (-1); 2382 2383 bufoff = (bge_ape_get32(bgep, BGE_APE_SEG_MSG_BUF_OFF) + 2384 BGE_APE_SHMEM_BASE); 2385 msgoff = bufoff + 2 * sizeof(uint32_t); 2386 maxlen = bge_ape_get32(bgep, BGE_APE_SEG_MSG_BUF_LEN); 2387 2388 while (lenToWrite) { 2389 uint32_t transferLen; 2390 2391 /* Cap xfer sizes to scratchpad limits. */ 2392 transferLen = (lenToWrite > maxlen) ? maxlen : lenToWrite; 2393 lenToWrite -= transferLen; 2394 2395 /* Wait for up to 1 millisecond for 2396 * APE to service previous event. 2397 */ 2398 err = bge_ape_event_lock(bgep, 1000); 2399 if (err) 2400 return (err); 2401 2402 bge_ape_put32(bgep, bufoff, dstoff); 2403 bge_ape_put32(bgep, bufoff + sizeof(uint32_t), transferLen); 2404 apedata = msgoff; 2405 2406 dstoff += transferLen; 2407 2408 for (i = 0; transferLen; i += 4, transferLen -= 4) { 2409 bge_ape_put32(bgep, apedata, *data++); 2410 apedata += sizeof(uint32_t); 2411 } 2412 2413 apedata = (APE_EVENT_STATUS_DRIVER_EVNT | 2414 APE_EVENT_STATUS_SCRTCHPD_WRITE | 2415 APE_EVENT_STATUS_EVENT_PENDING); 2416 bge_ape_put32(bgep, BGE_APE_EVENT_STATUS, apedata); 2417 2418 bge_ape_unlock(bgep, BGE_APE_LOCK_MEM); 2419 bge_ape_put32(bgep, BGE_APE_EVENT, APE_EVENT_1); 2420 } 2421 2422 return (0); 2423 } 2424 2425 static int 2426 bge_ape_send_event(bge_t *bgep, uint32_t event) 2427 { 2428 int err; 2429 uint32_t apedata; 2430 2431 BGE_TRACE(("bge_ape_send_event($%p, %d)", (void *)bgep, event)); 2432 2433 apedata = bge_ape_get32(bgep, BGE_APE_SEG_SIG); 2434 if (apedata != APE_SEG_SIG_MAGIC) 2435 return (-1); 2436 2437 apedata = bge_ape_get32(bgep, BGE_APE_FW_STATUS); 2438 if (!(apedata & APE_FW_STATUS_READY)) 2439 return (-1); 2440 2441 /* Wait for up to 1 millisecond for APE to service previous event. */ 2442 err = bge_ape_event_lock(bgep, 1000); 2443 if (err) 2444 return (err); 2445 2446 bge_ape_put32(bgep, BGE_APE_EVENT_STATUS, 2447 event | APE_EVENT_STATUS_EVENT_PENDING); 2448 2449 bge_ape_unlock(bgep, BGE_APE_LOCK_MEM); 2450 bge_ape_put32(bgep, BGE_APE_EVENT, APE_EVENT_1); 2451 2452 return 0; 2453 } 2454 2455 static void 2456 bge_ape_driver_state_change(bge_t *bgep, int mode) 2457 { 2458 uint32_t event; 2459 uint32_t apedata; 2460 2461 BGE_TRACE(("bge_ape_driver_state_change($%p, %d)", 2462 (void *)bgep, mode)); 2463 2464 if (!bgep->ape_enabled) 2465 return; 2466 2467 switch (mode) { 2468 case BGE_INIT_RESET: 2469 bge_ape_put32(bgep, BGE_APE_HOST_SEG_SIG, 2470 APE_HOST_SEG_SIG_MAGIC); 2471 bge_ape_put32(bgep, BGE_APE_HOST_SEG_LEN, 2472 APE_HOST_SEG_LEN_MAGIC); 2473 apedata = bge_ape_get32(bgep, BGE_APE_HOST_INIT_COUNT); 2474 bge_ape_put32(bgep, BGE_APE_HOST_INIT_COUNT, ++apedata); 2475 bge_ape_put32(bgep, BGE_APE_HOST_DRIVER_ID, 2476 APE_HOST_DRIVER_ID_MAGIC(1, 0)); 2477 bge_ape_put32(bgep, BGE_APE_HOST_BEHAVIOR, 2478 APE_HOST_BEHAV_NO_PHYLOCK); 2479 bge_ape_put32(bgep, BGE_APE_HOST_DRVR_STATE, 2480 BGE_APE_HOST_DRVR_STATE_START); 2481 2482 event = APE_EVENT_STATUS_STATE_START; 2483 break; 2484 case BGE_SHUTDOWN_RESET: 2485 /* With the interface we are currently using, 2486 * APE does not track driver state. Wiping 2487 * out the HOST SEGMENT SIGNATURE forces 2488 * the APE to assume OS absent status. 2489 */ 2490 bge_ape_put32(bgep, BGE_APE_HOST_SEG_SIG, 0x0); 2491 2492 #if 0 2493 if (WOL supported) { 2494 bge_ape_put32(bgep, BGE_APE_HOST_WOL_SPEED, 2495 BGE_APE_HOST_WOL_SPEED_AUTO); 2496 apedata = BGE_APE_HOST_DRVR_STATE_WOL; 2497 } else 2498 #endif 2499 apedata = BGE_APE_HOST_DRVR_STATE_UNLOAD; 2500 2501 bge_ape_put32(bgep, BGE_APE_HOST_DRVR_STATE, apedata); 2502 2503 event = APE_EVENT_STATUS_STATE_UNLOAD; 2504 break; 2505 case BGE_SUSPEND_RESET: 2506 event = APE_EVENT_STATUS_STATE_SUSPEND; 2507 break; 2508 default: 2509 return; 2510 } 2511 2512 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE; 2513 2514 bge_ape_send_event(bgep, event); 2515 } 2516 2517 #undef BGE_DBG 2518 #define BGE_DBG BGE_DBG_CHIP /* debug flag for this code */ 2519 2520 static void 2521 bge_init_recv_rule(bge_t *bgep) 2522 { 2523 bge_recv_rule_t *rulep = bgep->recv_rules; 2524 uint32_t i; 2525 2526 /* 2527 * Initialize receive rule registers. 2528 * Note that rules may persist across each bge_m_start/stop() call. 2529 */ 2530 for (i = 0; i < RECV_RULES_NUM_MAX; i++, rulep++) { 2531 bge_reg_put32(bgep, RECV_RULE_MASK_REG(i), rulep->mask_value); 2532 bge_reg_put32(bgep, RECV_RULE_CONTROL_REG(i), rulep->control); 2533 } 2534 } 2535 2536 /* 2537 * Using the values captured by bge_chip_cfg_init(), and additional probes 2538 * as required, characterise the chip fully: determine the label by which 2539 * to refer to this chip, the correct settings for various registers, and 2540 * of course whether the device and/or subsystem are supported! 2541 */ 2542 int bge_chip_id_init(bge_t *bgep); 2543 #pragma no_inline(bge_chip_id_init) 2544 2545 int 2546 bge_chip_id_init(bge_t *bgep) 2547 { 2548 char buf[MAXPATHLEN]; /* any risk of stack overflow? */ 2549 boolean_t dev_ok; 2550 chip_id_t *cidp; 2551 uint32_t subid; 2552 char *devname; 2553 char *sysname; 2554 int *ids; 2555 int err; 2556 uint_t i; 2557 2558 dev_ok = B_FALSE; 2559 cidp = &bgep->chipid; 2560 2561 /* 2562 * Check the PCI device ID to determine the generic chip type and 2563 * select parameters that depend on this. 2564 * 2565 * Note: because the SPARC platforms in general don't fit the 2566 * SEEPROM 'behind' the chip, the PCI revision ID register reads 2567 * as zero - which is why we use <asic_rev> rather than <revision> 2568 * below ... 2569 * 2570 * Note: in general we can't distinguish between the Copper/SerDes 2571 * versions by ID alone, as some Copper devices (e.g. some but not 2572 * all 5703Cs) have the same ID as the SerDes equivalents. So we 2573 * treat them the same here, and the MII code works out the media 2574 * type later on ... 2575 */ 2576 cidp->mbuf_base = bge_mbuf_pool_base; 2577 cidp->mbuf_length = bge_mbuf_pool_len; 2578 cidp->recv_slots = BGE_RECV_SLOTS_USED; 2579 cidp->bge_dma_rwctrl = bge_dma_rwctrl; 2580 cidp->pci_type = BGE_PCI_X; 2581 cidp->statistic_type = BGE_STAT_BLK; 2582 cidp->mbuf_lo_water_rdma = bge_mbuf_lo_water_rdma; 2583 cidp->mbuf_lo_water_rmac = bge_mbuf_lo_water_rmac; 2584 cidp->mbuf_hi_water = bge_mbuf_hi_water; 2585 cidp->rx_ticks_norm = bge_rx_ticks_norm; 2586 cidp->rx_count_norm = bge_rx_count_norm; 2587 cidp->tx_ticks_norm = bge_tx_ticks_norm; 2588 cidp->tx_count_norm = bge_tx_count_norm; 2589 cidp->mask_pci_int = MHCR_MASK_PCI_INT_OUTPUT; 2590 2591 if (cidp->rx_rings == 0 || cidp->rx_rings > BGE_RECV_RINGS_MAX) 2592 cidp->rx_rings = BGE_RECV_RINGS_DEFAULT; 2593 if (cidp->tx_rings == 0 || cidp->tx_rings > BGE_SEND_RINGS_MAX) 2594 cidp->tx_rings = BGE_SEND_RINGS_DEFAULT; 2595 2596 cidp->msi_enabled = B_FALSE; 2597 2598 switch (cidp->device) { 2599 case DEVICE_ID_5717: 2600 case DEVICE_ID_5718: 2601 case DEVICE_ID_5719: 2602 case DEVICE_ID_5720: 2603 case DEVICE_ID_5724: 2604 case DEVICE_ID_5725: 2605 case DEVICE_ID_5727: 2606 if (cidp->device == DEVICE_ID_5717) { 2607 cidp->chip_label = 5717; 2608 } else if (cidp->device == DEVICE_ID_5718) { 2609 cidp->chip_label = 5718; 2610 } else if (cidp->device == DEVICE_ID_5719) { 2611 cidp->chip_label = 5719; 2612 } else if (cidp->device == DEVICE_ID_5720) { 2613 if (pci_config_get16(bgep->cfg_handle, PCI_CONF_DEVID) == 2614 DEVICE_ID_5717_C0) { 2615 cidp->chip_label = 5717; 2616 } else { 2617 cidp->chip_label = 5720; 2618 } 2619 } else if (cidp->device == DEVICE_ID_5724) { 2620 cidp->chip_label = 5724; 2621 } else if (cidp->device == DEVICE_ID_5725) { 2622 cidp->chip_label = 5725; 2623 } else /* (cidp->device == DEVICE_ID_5727) */ { 2624 cidp->chip_label = 5727; 2625 } 2626 cidp->msi_enabled = bge_enable_msi; 2627 #ifdef __sparc 2628 cidp->mask_pci_int = LE_32(MHCR_MASK_PCI_INT_OUTPUT); 2629 #endif 2630 cidp->bge_dma_rwctrl = LE_32(PDRWCR_VAR_5717); 2631 cidp->pci_type = BGE_PCI_E; 2632 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2633 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5717; 2634 cidp->mbuf_hi_water = MBUF_HIWAT_5717; 2635 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2636 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2637 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2638 cidp->bge_mlcr_default = MLCR_DEFAULT_5717; 2639 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2640 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2641 cidp->statistic_type = BGE_STAT_REG; 2642 dev_ok = B_TRUE; 2643 break; 2644 2645 case DEVICE_ID_5700: 2646 case DEVICE_ID_5700x: 2647 cidp->chip_label = 5700; 2648 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2649 break; 2650 2651 case DEVICE_ID_5701: 2652 cidp->chip_label = 5701; 2653 dev_ok = B_TRUE; 2654 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2655 break; 2656 2657 case DEVICE_ID_5702: 2658 case DEVICE_ID_5702fe: 2659 cidp->chip_label = 5702; 2660 dev_ok = B_TRUE; 2661 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2662 cidp->pci_type = BGE_PCI; 2663 break; 2664 2665 case DEVICE_ID_5703C: 2666 case DEVICE_ID_5703S: 2667 case DEVICE_ID_5703: 2668 /* 2669 * Revision A0 of the 5703/5793 had various errata 2670 * that we can't or don't work around, so it's not 2671 * supported, but all later versions are 2672 */ 2673 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5793 : 5703; 2674 if (bgep->chipid.asic_rev != MHCR_CHIP_REV_5703_A0) 2675 dev_ok = B_TRUE; 2676 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2677 break; 2678 2679 case DEVICE_ID_5704C: 2680 case DEVICE_ID_5704S: 2681 case DEVICE_ID_5704: 2682 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5794 : 5704; 2683 cidp->mbuf_base = bge_mbuf_pool_base_5704; 2684 cidp->mbuf_length = bge_mbuf_pool_len_5704; 2685 dev_ok = B_TRUE; 2686 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2687 break; 2688 2689 case DEVICE_ID_5705C: 2690 case DEVICE_ID_5705M: 2691 case DEVICE_ID_5705MA3: 2692 case DEVICE_ID_5705F: 2693 case DEVICE_ID_5705_2: 2694 case DEVICE_ID_5754: 2695 if (cidp->device == DEVICE_ID_5754) { 2696 cidp->chip_label = 5754; 2697 cidp->pci_type = BGE_PCI_E; 2698 } else { 2699 cidp->chip_label = 5705; 2700 cidp->pci_type = BGE_PCI; 2701 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2702 } 2703 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2704 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2705 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2706 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2707 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2708 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2709 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2710 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2711 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2712 cidp->statistic_type = BGE_STAT_REG; 2713 dev_ok = B_TRUE; 2714 break; 2715 2716 case DEVICE_ID_5906: 2717 case DEVICE_ID_5906M: 2718 cidp->chip_label = 5906; 2719 cidp->pci_type = BGE_PCI_E; 2720 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5906; 2721 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5906; 2722 cidp->mbuf_hi_water = MBUF_HIWAT_5906; 2723 cidp->mbuf_base = bge_mbuf_pool_base; 2724 cidp->mbuf_length = bge_mbuf_pool_len; 2725 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2726 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2727 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2728 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2729 cidp->statistic_type = BGE_STAT_REG; 2730 dev_ok = B_TRUE; 2731 break; 2732 2733 case DEVICE_ID_5753: 2734 cidp->chip_label = 5753; 2735 cidp->pci_type = BGE_PCI_E; 2736 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2737 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2738 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2739 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2740 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2741 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2742 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2743 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2744 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2745 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2746 cidp->statistic_type = BGE_STAT_REG; 2747 dev_ok = B_TRUE; 2748 break; 2749 2750 case DEVICE_ID_5755: 2751 case DEVICE_ID_5755M: 2752 cidp->chip_label = 5755; 2753 cidp->pci_type = BGE_PCI_E; 2754 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2755 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2756 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2757 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2758 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2759 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2760 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2761 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2762 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2763 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2764 if (cidp->device == DEVICE_ID_5755M) 2765 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2766 cidp->statistic_type = BGE_STAT_REG; 2767 dev_ok = B_TRUE; 2768 break; 2769 2770 case DEVICE_ID_5756M: 2771 /* 2772 * This is nearly identical to the 5755M. 2773 * (Actually reports the 5755 chip ID.) 2774 */ 2775 cidp->chip_label = 5756; 2776 cidp->pci_type = BGE_PCI_E; 2777 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2778 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2779 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2780 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2781 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2782 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2783 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2784 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2785 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2786 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2787 cidp->statistic_type = BGE_STAT_REG; 2788 dev_ok = B_TRUE; 2789 break; 2790 2791 case DEVICE_ID_5787: 2792 case DEVICE_ID_5787M: 2793 cidp->chip_label = 5787; 2794 cidp->pci_type = BGE_PCI_E; 2795 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2796 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2797 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2798 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2799 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2800 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2801 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2802 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2803 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2804 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2805 cidp->statistic_type = BGE_STAT_REG; 2806 dev_ok = B_TRUE; 2807 break; 2808 2809 case DEVICE_ID_5723: 2810 case DEVICE_ID_5761: 2811 case DEVICE_ID_5761E: 2812 case DEVICE_ID_57780: 2813 cidp->msi_enabled = bge_enable_msi; 2814 /* 2815 * We don't use MSI for BCM5764 and BCM5785, as the 2816 * status block may fail to update when the network 2817 * traffic is heavy. 2818 */ 2819 /* FALLTHRU */ 2820 case DEVICE_ID_5785: 2821 case DEVICE_ID_5764: 2822 if (cidp->device == DEVICE_ID_5723) 2823 cidp->chip_label = 5723; 2824 else if (cidp->device == DEVICE_ID_5764) 2825 cidp->chip_label = 5764; 2826 else if (cidp->device == DEVICE_ID_5785) 2827 cidp->chip_label = 5785; 2828 else if (cidp->device == DEVICE_ID_57780) 2829 cidp->chip_label = 57780; 2830 else 2831 cidp->chip_label = 5761; 2832 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2833 cidp->pci_type = BGE_PCI_E; 2834 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2835 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2836 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2837 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2838 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2839 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2840 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2841 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2842 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2843 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2844 cidp->statistic_type = BGE_STAT_REG; 2845 dev_ok = B_TRUE; 2846 break; 2847 2848 /* PCI-X device, identical to 5714 */ 2849 case DEVICE_ID_5780: 2850 cidp->chip_label = 5780; 2851 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2852 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2853 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2854 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2855 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2856 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2857 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2858 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2859 cidp->statistic_type = BGE_STAT_REG; 2860 dev_ok = B_TRUE; 2861 break; 2862 2863 case DEVICE_ID_5782: 2864 /* 2865 * Apart from the label, we treat this as a 5705(?) 2866 */ 2867 cidp->chip_label = 5782; 2868 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2869 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2870 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2871 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2872 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2873 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2874 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2875 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2876 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2877 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2878 cidp->statistic_type = BGE_STAT_REG; 2879 dev_ok = B_TRUE; 2880 break; 2881 2882 case DEVICE_ID_5788: 2883 /* 2884 * Apart from the label, we treat this as a 5705(?) 2885 */ 2886 cidp->chip_label = 5788; 2887 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2888 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2889 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2890 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2891 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2892 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2893 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2894 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2895 cidp->statistic_type = BGE_STAT_REG; 2896 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2897 dev_ok = B_TRUE; 2898 break; 2899 2900 case DEVICE_ID_5714C: 2901 if (cidp->revision >= REVISION_ID_5714_A2) 2902 cidp->msi_enabled = bge_enable_msi; 2903 /* FALLTHRU */ 2904 case DEVICE_ID_5714S: 2905 cidp->chip_label = 5714; 2906 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2907 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2908 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2909 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2910 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2911 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2912 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5714; 2913 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2914 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2915 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2916 cidp->pci_type = BGE_PCI_E; 2917 cidp->statistic_type = BGE_STAT_REG; 2918 dev_ok = B_TRUE; 2919 break; 2920 2921 case DEVICE_ID_5715C: 2922 case DEVICE_ID_5715S: 2923 cidp->chip_label = 5715; 2924 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2925 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2926 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2927 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2928 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2929 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2930 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5715; 2931 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2932 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2933 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2934 cidp->pci_type = BGE_PCI_E; 2935 cidp->statistic_type = BGE_STAT_REG; 2936 if (cidp->revision >= REVISION_ID_5715_A2) 2937 cidp->msi_enabled = bge_enable_msi; 2938 dev_ok = B_TRUE; 2939 break; 2940 2941 case DEVICE_ID_5721: 2942 cidp->chip_label = 5721; 2943 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2944 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2945 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2946 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2947 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2948 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2949 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2950 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2951 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2952 cidp->pci_type = BGE_PCI_E; 2953 cidp->statistic_type = BGE_STAT_REG; 2954 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2955 dev_ok = B_TRUE; 2956 break; 2957 2958 case DEVICE_ID_5722: 2959 cidp->chip_label = 5722; 2960 cidp->pci_type = BGE_PCI_E; 2961 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2962 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2963 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2964 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2965 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2966 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2967 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2968 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2969 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2970 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2971 cidp->statistic_type = BGE_STAT_REG; 2972 dev_ok = B_TRUE; 2973 break; 2974 2975 case DEVICE_ID_5751: 2976 case DEVICE_ID_5751M: 2977 cidp->chip_label = 5751; 2978 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2979 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2980 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2981 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2982 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2983 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2984 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2985 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2986 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2987 cidp->pci_type = BGE_PCI_E; 2988 cidp->statistic_type = BGE_STAT_REG; 2989 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2990 dev_ok = B_TRUE; 2991 break; 2992 2993 case DEVICE_ID_5752: 2994 case DEVICE_ID_5752M: 2995 cidp->chip_label = 5752; 2996 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2997 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2998 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2999 cidp->mbuf_base = bge_mbuf_pool_base_5721; 3000 cidp->mbuf_length = bge_mbuf_pool_len_5721; 3001 cidp->recv_slots = BGE_RECV_SLOTS_5721; 3002 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 3003 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 3004 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 3005 cidp->pci_type = BGE_PCI_E; 3006 cidp->statistic_type = BGE_STAT_REG; 3007 cidp->flags |= CHIP_FLAG_NO_JUMBO; 3008 dev_ok = B_TRUE; 3009 break; 3010 3011 case DEVICE_ID_5789: 3012 cidp->chip_label = 5789; 3013 cidp->mbuf_base = bge_mbuf_pool_base_5721; 3014 cidp->mbuf_length = bge_mbuf_pool_len_5721; 3015 cidp->recv_slots = BGE_RECV_SLOTS_5721; 3016 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 3017 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 3018 cidp->tx_rings = BGE_RECV_RINGS_MAX_5705; 3019 cidp->pci_type = BGE_PCI_E; 3020 cidp->statistic_type = BGE_STAT_REG; 3021 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 3022 cidp->flags |= CHIP_FLAG_NO_JUMBO; 3023 cidp->msi_enabled = B_TRUE; 3024 dev_ok = B_TRUE; 3025 break; 3026 3027 } 3028 3029 /* 3030 * Setup the default jumbo parameter. 3031 */ 3032 cidp->ethmax_size = ETHERMAX; 3033 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_DEFAULT; 3034 cidp->std_buf_size = BGE_STD_BUFF_SIZE; 3035 3036 /* 3037 * If jumbo is enabled and this kind of chipset supports jumbo feature, 3038 * setup below jumbo specific parameters. 3039 * 3040 * For BCM5714/5715, there is only one standard receive ring. So the 3041 * std buffer size should be set to BGE_JUMBO_BUFF_SIZE when jumbo 3042 * feature is enabled. 3043 * 3044 * For the BCM5718 family we hijack the standard receive ring for 3045 * the jumboframe traffic, keeps it simple. 3046 */ 3047 if (!(cidp->flags & CHIP_FLAG_NO_JUMBO) && 3048 (cidp->default_mtu > BGE_DEFAULT_MTU)) { 3049 if (DEVICE_5714_SERIES_CHIPSETS(bgep) || 3050 DEVICE_5717_SERIES_CHIPSETS(bgep) || 3051 DEVICE_5725_SERIES_CHIPSETS(bgep)) { 3052 cidp->mbuf_lo_water_rdma = 3053 RDMA_MBUF_LOWAT_5714_JUMBO; 3054 cidp->mbuf_lo_water_rmac = 3055 MAC_RX_MBUF_LOWAT_5714_JUMBO; 3056 cidp->mbuf_hi_water = MBUF_HIWAT_5714_JUMBO; 3057 cidp->jumbo_slots = 0; 3058 cidp->std_buf_size = BGE_JUMBO_BUFF_SIZE; 3059 } else { 3060 cidp->mbuf_lo_water_rdma = 3061 RDMA_MBUF_LOWAT_JUMBO; 3062 cidp->mbuf_lo_water_rmac = 3063 MAC_RX_MBUF_LOWAT_JUMBO; 3064 cidp->mbuf_hi_water = MBUF_HIWAT_JUMBO; 3065 cidp->jumbo_slots = BGE_JUMBO_SLOTS_USED; 3066 } 3067 cidp->recv_jumbo_size = BGE_JUMBO_BUFF_SIZE; 3068 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_JUMBO; 3069 cidp->ethmax_size = cidp->default_mtu + 3070 sizeof (struct ether_header); 3071 } 3072 3073 /* 3074 * Identify the NV memory type: SEEPROM or Flash? 3075 */ 3076 cidp->nvtype = bge_nvmem_id(bgep); 3077 3078 /* 3079 * Now check what we've discovered: is this truly a supported 3080 * chip on (the motherboard of) a supported platform? 3081 * 3082 * Possible problems here: 3083 * 1) it's a completely unheard-of chip 3084 * 2) it's a recognised but unsupported chip (e.g. 5701, 5703C-A0) 3085 * 3) it's a chip we would support if it were on the motherboard 3086 * of a Sun platform, but this one isn't ;-( 3087 */ 3088 if (cidp->chip_label == 0) 3089 bge_problem(bgep, 3090 "Device 'pci%04x,%04x' not recognized (%d?)", 3091 cidp->vendor, cidp->device, cidp->device); 3092 else if (!dev_ok) 3093 bge_problem(bgep, 3094 "Device 'pci%04x,%04x' (%d) revision %d not supported", 3095 cidp->vendor, cidp->device, cidp->chip_label, 3096 cidp->revision); 3097 else 3098 cidp->flags |= CHIP_FLAG_SUPPORTED; 3099 3100 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 3101 return (EIO); 3102 3103 return (0); 3104 } 3105 3106 void 3107 bge_chip_msi_trig(bge_t *bgep) 3108 { 3109 uint32_t regval; 3110 3111 regval = bgep->param_msi_cnt<<4; 3112 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, regval); 3113 BGE_DEBUG(("bge_chip_msi_trig:data = %d", regval)); 3114 } 3115 3116 /* 3117 * Various registers that control the chip's internal engines (state 3118 * machines) have a <reset> and <enable> bits (fortunately, in the 3119 * same place in each such register :-). 3120 * 3121 * To reset the state machine, the <reset> bit must be written with 1; 3122 * it will then read back as 1 while the reset is in progress, but 3123 * self-clear to 0 when the reset completes. 3124 * 3125 * To enable a state machine, one must set the <enable> bit, which 3126 * will continue to read back as 0 until the state machine is running. 3127 * 3128 * To disable a state machine, the <enable> bit must be cleared, but 3129 * it will continue to read back as 1 until the state machine actually 3130 * stops. 3131 * 3132 * This routine implements polling for completion of a reset, enable 3133 * or disable operation, returning B_TRUE on success (bit reached the 3134 * required state) or B_FALSE on timeout (200*100us == 20ms). 3135 */ 3136 static boolean_t bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 3137 uint32_t mask, uint32_t val); 3138 #pragma no_inline(bge_chip_poll_engine) 3139 3140 static boolean_t 3141 bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 3142 uint32_t mask, uint32_t val) 3143 { 3144 uint32_t regval; 3145 uint32_t n; 3146 3147 BGE_TRACE(("bge_chip_poll_engine($%p, 0x%lx, 0x%x, 0x%x)", 3148 (void *)bgep, regno, mask, val)); 3149 3150 for (n = 200; n; --n) { 3151 regval = bge_reg_get32(bgep, regno); 3152 if ((regval & mask) == val) 3153 return (B_TRUE); 3154 drv_usecwait(100); 3155 } 3156 3157 bge_problem(bgep, "bge_chip_poll_engine failed: regno = 0x%lx", regno); 3158 bge_fm_ereport(bgep, DDI_FM_DEVICE_NO_RESPONSE); 3159 return (B_FALSE); 3160 } 3161 3162 /* 3163 * Various registers that control the chip's internal engines (state 3164 * machines) have a <reset> bit (fortunately, in the same place in 3165 * each such register :-). To reset the state machine, this bit must 3166 * be written with 1; it will then read back as 1 while the reset is 3167 * in progress, but self-clear to 0 when the reset completes. 3168 * 3169 * This code sets the bit, then polls for it to read back as zero. 3170 * The return value is B_TRUE on success (reset bit cleared itself), 3171 * or B_FALSE if the state machine didn't recover :( 3172 * 3173 * NOTE: the Core reset is similar to other resets, except that we 3174 * can't poll for completion, since the Core reset disables memory 3175 * access! So we just have to assume that it will all complete in 3176 * 100us. See Broadcom document 570X-PG102-R, p102, steps 4-5. 3177 */ 3178 static boolean_t bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno); 3179 #pragma no_inline(bge_chip_reset_engine) 3180 3181 static boolean_t 3182 bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno) 3183 { 3184 uint32_t regval; 3185 uint16_t val16; 3186 uint32_t val32; 3187 uint32_t mhcr; 3188 3189 regval = bge_reg_get32(bgep, regno); 3190 3191 BGE_TRACE(("bge_chip_reset_engine($%p, 0x%lx)", 3192 (void *)bgep, regno)); 3193 BGE_DEBUG(("bge_chip_reset_engine: 0x%lx before reset = 0x%08x", 3194 regno, regval)); 3195 3196 regval |= STATE_MACHINE_RESET_BIT; 3197 3198 switch (regno) { 3199 case MISC_CONFIG_REG: 3200 /* 3201 * BCM5714/5721/5751 pcie chip special case. In order to avoid 3202 * resetting PCIE block and bringing PCIE link down, bit 29 3203 * in the register needs to be set first, and then set it again 3204 * while the reset bit is written. 3205 * See:P500 of 57xx-PG102-RDS.pdf. 3206 */ 3207 if (DEVICE_5705_SERIES_CHIPSETS(bgep) || 3208 DEVICE_5717_SERIES_CHIPSETS(bgep) || 3209 DEVICE_5725_SERIES_CHIPSETS(bgep) || 3210 DEVICE_5721_SERIES_CHIPSETS(bgep) || 3211 DEVICE_5723_SERIES_CHIPSETS(bgep) || 3212 DEVICE_5714_SERIES_CHIPSETS(bgep) || 3213 DEVICE_5906_SERIES_CHIPSETS(bgep)) { 3214 regval |= MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE; 3215 if (bgep->chipid.pci_type == BGE_PCI_E) { 3216 if (bgep->chipid.asic_rev == 3217 MHCR_CHIP_REV_5751_A0 || 3218 bgep->chipid.asic_rev == 3219 MHCR_CHIP_REV_5721_A0 || 3220 bgep->chipid.asic_rev == 3221 MHCR_CHIP_REV_5755_A0) { 3222 val32 = bge_reg_get32(bgep, 3223 PHY_TEST_CTRL_REG); 3224 if (val32 == (PHY_PCIE_SCRAM_MODE | 3225 PHY_PCIE_LTASS_MODE)) 3226 bge_reg_put32(bgep, 3227 PHY_TEST_CTRL_REG, 3228 PHY_PCIE_SCRAM_MODE); 3229 val32 = pci_config_get32 3230 (bgep->cfg_handle, 3231 PCI_CONF_BGE_CLKCTL); 3232 val32 |= CLKCTL_PCIE_A0_FIX; 3233 pci_config_put32(bgep->cfg_handle, 3234 PCI_CONF_BGE_CLKCTL, val32); 3235 } 3236 bge_reg_set32(bgep, regno, 3237 MISC_CONFIG_GRC_RESET_DISABLE); 3238 regval |= MISC_CONFIG_GRC_RESET_DISABLE; 3239 } 3240 } 3241 3242 /* 3243 * Special case - causes Core reset 3244 * 3245 * On SPARC v9 we want to ensure that we don't start 3246 * timing until the I/O access has actually reached 3247 * the chip, otherwise we might make the next access 3248 * too early. And we can't just force the write out 3249 * by following it with a read (even to config space) 3250 * because that would cause the fault we're trying 3251 * to avoid. Hence the need for membar_sync() here. 3252 */ 3253 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), regval); 3254 #ifdef __sparcv9 3255 membar_sync(); 3256 #endif /* __sparcv9 */ 3257 /* 3258 * On some platforms,system need about 300us for 3259 * link setup. 3260 */ 3261 drv_usecwait(300); 3262 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) { 3263 bge_reg_set32(bgep, VCPU_STATUS_REG, VCPU_DRV_RESET); 3264 bge_reg_clr32( 3265 bgep, VCPU_EXT_CTL, VCPU_EXT_CTL_HALF); 3266 } 3267 3268 if (bgep->chipid.pci_type == BGE_PCI_E) { 3269 /* PCI-E device need more reset time */ 3270 drv_usecwait(120000); 3271 3272 /* 3273 * (re)Disable interrupts as the bit can be reset after a 3274 * core clock reset. 3275 */ 3276 mhcr = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MHCR); 3277 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, 3278 mhcr | MHCR_MASK_PCI_INT_OUTPUT); 3279 3280 /* Set PCIE max payload size and clear error status. */ 3281 if ((bgep->chipid.chip_label == 5721) || 3282 (bgep->chipid.chip_label == 5751) || 3283 (bgep->chipid.chip_label == 5752) || 3284 (bgep->chipid.chip_label == 5789) || 3285 (bgep->chipid.chip_label == 5906)) { 3286 pci_config_put16(bgep->cfg_handle, 3287 PCI_CONF_DEV_CTRL, READ_REQ_SIZE_MAX); 3288 pci_config_put16(bgep->cfg_handle, 3289 PCI_CONF_DEV_STUS, DEVICE_ERROR_STUS); 3290 } 3291 3292 if ((bgep->chipid.chip_label == 5723) || 3293 (bgep->chipid.chip_label == 5761)) { 3294 pci_config_put16(bgep->cfg_handle, 3295 PCI_CONF_DEV_CTRL_5723, READ_REQ_SIZE_MAX); 3296 pci_config_put16(bgep->cfg_handle, 3297 PCI_CONF_DEV_STUS_5723, DEVICE_ERROR_STUS); 3298 } 3299 3300 if (DEVICE_5717_SERIES_CHIPSETS(bgep) || 3301 DEVICE_5725_SERIES_CHIPSETS(bgep)) { 3302 val16 = pci_config_get16(bgep->cfg_handle, 3303 PCI_CONF_DEV_CTRL_5717); 3304 val16 &= ~READ_REQ_SIZE_MASK; 3305 val16 |= READ_REQ_SIZE_2K; 3306 pci_config_put16(bgep->cfg_handle, 3307 PCI_CONF_DEV_CTRL_5717, val16); 3308 } 3309 } 3310 3311 BGE_PCICHK(bgep); 3312 return (B_TRUE); 3313 3314 default: 3315 bge_reg_put32(bgep, regno, regval); 3316 return (bge_chip_poll_engine(bgep, regno, 3317 STATE_MACHINE_RESET_BIT, 0)); 3318 } 3319 } 3320 3321 /* 3322 * Various registers that control the chip's internal engines (state 3323 * machines) have an <enable> bit (fortunately, in the same place in 3324 * each such register :-). To stop the state machine, this bit must 3325 * be written with 0, then polled to see when the state machine has 3326 * actually stopped. 3327 * 3328 * The return value is B_TRUE on success (enable bit cleared), or 3329 * B_FALSE if the state machine didn't stop :( 3330 */ 3331 static boolean_t bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, 3332 uint32_t morebits); 3333 #pragma no_inline(bge_chip_disable_engine) 3334 3335 static boolean_t 3336 bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 3337 { 3338 uint32_t regval; 3339 3340 BGE_TRACE(("bge_chip_disable_engine($%p, 0x%lx, 0x%x)", 3341 (void *)bgep, regno, morebits)); 3342 3343 switch (regno) { 3344 case FTQ_RESET_REG: 3345 /* 3346 * For Schumacher's bugfix CR6490108 3347 */ 3348 #ifdef BGE_IPMI_ASF 3349 #ifdef BGE_NETCONSOLE 3350 if (bgep->asf_enabled) 3351 return (B_TRUE); 3352 #endif 3353 #endif 3354 /* 3355 * Not quite like the others; it doesn't 3356 * have an <enable> bit, but instead we 3357 * have to set and then clear all the bits 3358 */ 3359 bge_reg_put32(bgep, regno, ~(uint32_t)0); 3360 drv_usecwait(100); 3361 bge_reg_put32(bgep, regno, 0); 3362 return (B_TRUE); 3363 3364 default: 3365 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3366 break; 3367 } 3368 3369 if ((regno == RCV_LIST_SELECTOR_MODE_REG) || 3370 (regno == DMA_COMPLETION_MODE_REG) || 3371 (regno == MBUF_CLUSTER_FREE_MODE_REG) || 3372 (regno == BUFFER_MANAGER_MODE_REG) || 3373 (regno == MEMORY_ARBITER_MODE_REG)) { 3374 return B_TRUE; 3375 } 3376 3377 break; 3378 } 3379 3380 regval = bge_reg_get32(bgep, regno); 3381 regval &= ~STATE_MACHINE_ENABLE_BIT; 3382 regval &= ~morebits; 3383 bge_reg_put32(bgep, regno, regval); 3384 3385 return bge_chip_poll_engine(bgep, regno, STATE_MACHINE_ENABLE_BIT, 0); 3386 } 3387 3388 /* 3389 * Various registers that control the chip's internal engines (state 3390 * machines) have an <enable> bit (fortunately, in the same place in 3391 * each such register :-). To start the state machine, this bit must 3392 * be written with 1, then polled to see when the state machine has 3393 * actually started. 3394 * 3395 * The return value is B_TRUE on success (enable bit set), or 3396 * B_FALSE if the state machine didn't start :( 3397 */ 3398 static boolean_t bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, 3399 uint32_t morebits); 3400 #pragma no_inline(bge_chip_enable_engine) 3401 3402 static boolean_t 3403 bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 3404 { 3405 uint32_t regval; 3406 3407 BGE_TRACE(("bge_chip_enable_engine($%p, 0x%lx, 0x%x)", 3408 (void *)bgep, regno, morebits)); 3409 3410 switch (regno) { 3411 case FTQ_RESET_REG: 3412 #ifdef BGE_IPMI_ASF 3413 #ifdef BGE_NETCONSOLE 3414 if (bgep->asf_enabled) 3415 return (B_TRUE); 3416 #endif 3417 #endif 3418 /* 3419 * Not quite like the others; it doesn't 3420 * have an <enable> bit, but instead we 3421 * have to set and then clear all the bits 3422 */ 3423 bge_reg_put32(bgep, regno, ~(uint32_t)0); 3424 drv_usecwait(100); 3425 bge_reg_put32(bgep, regno, 0); 3426 return (B_TRUE); 3427 3428 default: 3429 regval = bge_reg_get32(bgep, regno); 3430 regval |= STATE_MACHINE_ENABLE_BIT; 3431 regval |= morebits; 3432 bge_reg_put32(bgep, regno, regval); 3433 return (bge_chip_poll_engine(bgep, regno, 3434 STATE_MACHINE_ENABLE_BIT, STATE_MACHINE_ENABLE_BIT)); 3435 } 3436 } 3437 3438 /* 3439 * Reprogram the Ethernet, Transmit, and Receive MAC 3440 * modes to match the param_* variables 3441 */ 3442 void bge_sync_mac_modes(bge_t *bgep); 3443 #pragma no_inline(bge_sync_mac_modes) 3444 3445 void 3446 bge_sync_mac_modes(bge_t *bgep) 3447 { 3448 uint32_t macmode; 3449 uint32_t regval; 3450 3451 ASSERT(mutex_owned(bgep->genlock)); 3452 3453 /* 3454 * Reprogram the Ethernet MAC mode ... 3455 */ 3456 macmode = regval = bge_reg_get32(bgep, ETHERNET_MAC_MODE_REG); 3457 macmode &= ~ETHERNET_MODE_LINK_POLARITY; 3458 macmode &= ~ETHERNET_MODE_PORTMODE_MASK; 3459 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 3460 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) { 3461 if (DEVICE_5717_SERIES_CHIPSETS(bgep) || 3462 DEVICE_5725_SERIES_CHIPSETS(bgep) || 3463 DEVICE_5714_SERIES_CHIPSETS(bgep)) 3464 macmode |= ETHERNET_MODE_PORTMODE_GMII; 3465 else 3466 macmode |= ETHERNET_MODE_PORTMODE_TBI; 3467 } else if (bgep->param_link_speed == 10 || 3468 bgep->param_link_speed == 100) 3469 macmode |= ETHERNET_MODE_PORTMODE_MII; 3470 else 3471 macmode |= ETHERNET_MODE_PORTMODE_GMII; 3472 if (bgep->param_link_duplex == LINK_DUPLEX_HALF) 3473 macmode |= ETHERNET_MODE_HALF_DUPLEX; 3474 else 3475 macmode &= ~ETHERNET_MODE_HALF_DUPLEX; 3476 if (bgep->param_loop_mode == BGE_LOOP_INTERNAL_MAC) 3477 macmode |= ETHERNET_MODE_MAC_LOOPBACK; 3478 else 3479 macmode &= ~ETHERNET_MODE_MAC_LOOPBACK; 3480 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, macmode); 3481 BGE_DEBUG(("bge_sync_mac_modes($%p) Ethernet MAC mode 0x%x => 0x%x", 3482 (void *)bgep, regval, macmode)); 3483 3484 /* 3485 * ... the Transmit MAC mode ... 3486 */ 3487 macmode = regval = bge_reg_get32(bgep, TRANSMIT_MAC_MODE_REG); 3488 if (bgep->param_link_tx_pause) 3489 macmode |= TRANSMIT_MODE_FLOW_CONTROL; 3490 else 3491 macmode &= ~TRANSMIT_MODE_FLOW_CONTROL; 3492 bge_reg_put32(bgep, TRANSMIT_MAC_MODE_REG, macmode); 3493 BGE_DEBUG(("bge_sync_mac_modes($%p) Transmit MAC mode 0x%x => 0x%x", 3494 (void *)bgep, regval, macmode)); 3495 3496 /* 3497 * ... and the Receive MAC mode 3498 */ 3499 macmode = regval = bge_reg_get32(bgep, RECEIVE_MAC_MODE_REG); 3500 if (bgep->param_link_rx_pause) 3501 macmode |= RECEIVE_MODE_FLOW_CONTROL; 3502 else 3503 macmode &= ~RECEIVE_MODE_FLOW_CONTROL; 3504 bge_reg_put32(bgep, RECEIVE_MAC_MODE_REG, macmode); 3505 BGE_DEBUG(("bge_sync_mac_modes($%p) Receive MAC mode 0x%x => 0x%x", 3506 (void *)bgep, regval, macmode)); 3507 3508 /* 3509 * For BCM5785, we need to configure the link status in the MI Status 3510 * register with a write command when auto-polling is disabled. 3511 */ 3512 if (bgep->chipid.device == DEVICE_ID_5785) 3513 if (bgep->param_link_speed == 10) 3514 bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK 3515 | MI_STATUS_10MBPS); 3516 else 3517 bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK); 3518 } 3519 3520 /* 3521 * bge_chip_sync() -- program the chip with the unicast MAC address, 3522 * the multicast hash table, the required level of promiscuity, and 3523 * the current loopback mode ... 3524 */ 3525 #ifdef BGE_IPMI_ASF 3526 int bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive); 3527 #else 3528 int bge_chip_sync(bge_t *bgep); 3529 #endif 3530 #pragma no_inline(bge_chip_sync) 3531 3532 int 3533 #ifdef BGE_IPMI_ASF 3534 bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive) 3535 #else 3536 bge_chip_sync(bge_t *bgep) 3537 #endif 3538 { 3539 void (*opfn)(bge_t *bgep, bge_regno_t reg, uint32_t bits); 3540 boolean_t promisc; 3541 uint64_t macaddr; 3542 uint32_t fill = 0; 3543 int i, j; 3544 int retval = DDI_SUCCESS; 3545 3546 BGE_TRACE(("bge_chip_sync($%p)", 3547 (void *)bgep)); 3548 3549 ASSERT(mutex_owned(bgep->genlock)); 3550 3551 promisc = B_FALSE; 3552 fill = ~(uint32_t)0; 3553 3554 if (bgep->promisc) 3555 promisc = B_TRUE; 3556 else 3557 fill = (uint32_t)0; 3558 3559 /* 3560 * If the TX/RX MAC engines are already running, we should stop 3561 * them (and reset the RX engine) before changing the parameters. 3562 * If they're not running, this will have no effect ... 3563 * 3564 * NOTE: this is currently disabled by default because stopping 3565 * and restarting the Tx engine may cause an outgoing packet in 3566 * transit to be truncated. Also, stopping and restarting the 3567 * Rx engine seems to not work correctly on the 5705. Testing 3568 * has not (yet!) revealed any problems with NOT stopping and 3569 * restarting these engines (and Broadcom say their drivers don't 3570 * do this), but if it is found to cause problems, this variable 3571 * can be patched to re-enable the old behaviour ... 3572 */ 3573 if (bge_stop_start_on_sync) { 3574 #ifdef BGE_IPMI_ASF 3575 if (!bgep->asf_enabled) { 3576 if (!bge_chip_disable_engine(bgep, 3577 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG)) 3578 retval = DDI_FAILURE; 3579 } else { 3580 if (!bge_chip_disable_engine(bgep, 3581 RECEIVE_MAC_MODE_REG, 0)) 3582 retval = DDI_FAILURE; 3583 } 3584 #else 3585 if (!bge_chip_disable_engine(bgep, RECEIVE_MAC_MODE_REG, 3586 RECEIVE_MODE_KEEP_VLAN_TAG)) 3587 retval = DDI_FAILURE; 3588 #endif 3589 if (!bge_chip_disable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 3590 retval = DDI_FAILURE; 3591 if (!bge_chip_reset_engine(bgep, RECEIVE_MAC_MODE_REG)) 3592 retval = DDI_FAILURE; 3593 } 3594 3595 /* 3596 * Reprogram the hashed multicast address table ... 3597 */ 3598 for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i) 3599 bge_reg_put32(bgep, MAC_HASH_REG(i), 0); 3600 3601 for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i) 3602 bge_reg_put32(bgep, MAC_HASH_REG(i), 3603 bgep->mcast_hash[i] | fill); 3604 3605 #ifdef BGE_IPMI_ASF 3606 if (!bgep->asf_enabled || !asf_keeplive) { 3607 #endif 3608 /* 3609 * Transform the MAC address(es) from host to chip format, then 3610 * reprogram the transmit random backoff seed and the unicast 3611 * MAC address(es) ... 3612 */ 3613 for (j = 0; j < MAC_ADDRESS_REGS_MAX; j++) { 3614 for (i = 0, macaddr = 0ull; 3615 i < ETHERADDRL; ++i) { 3616 macaddr <<= 8; 3617 macaddr |= bgep->curr_addr[j].addr[i]; 3618 } 3619 fill += (macaddr >> 16) + (macaddr & 0xffffffff); 3620 bge_reg_put64(bgep, MAC_ADDRESS_REG(j), macaddr); 3621 3622 BGE_DEBUG(("bge_chip_sync($%p) " 3623 "setting MAC address %012llx", 3624 (void *)bgep, macaddr)); 3625 } 3626 #ifdef BGE_IPMI_ASF 3627 } 3628 #endif 3629 /* 3630 * Set random seed of backoff interval 3631 * - Writing zero means no backoff interval 3632 */ 3633 fill = ((fill >> 20) + (fill >> 10) + fill) & 0x3ff; 3634 if (fill == 0) 3635 fill = 1; 3636 bge_reg_put32(bgep, MAC_TX_RANDOM_BACKOFF_REG, fill); 3637 3638 /* 3639 * Set or clear the PROMISCUOUS mode bit 3640 */ 3641 opfn = promisc ? bge_reg_set32 : bge_reg_clr32; 3642 (*opfn)(bgep, RECEIVE_MAC_MODE_REG, RECEIVE_MODE_PROMISCUOUS); 3643 3644 /* 3645 * Sync the rest of the MAC modes too ... 3646 */ 3647 bge_sync_mac_modes(bgep); 3648 3649 /* 3650 * Restart RX/TX MAC engines if required ... 3651 */ 3652 if (bgep->bge_chip_state == BGE_CHIP_RUNNING) { 3653 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 3654 retval = DDI_FAILURE; 3655 #ifdef BGE_IPMI_ASF 3656 if (!bgep->asf_enabled) { 3657 if (!bge_chip_enable_engine(bgep, 3658 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG)) 3659 retval = DDI_FAILURE; 3660 } else { 3661 if (!bge_chip_enable_engine(bgep, 3662 RECEIVE_MAC_MODE_REG, 0)) 3663 retval = DDI_FAILURE; 3664 } 3665 #else 3666 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 3667 RECEIVE_MODE_KEEP_VLAN_TAG)) 3668 retval = DDI_FAILURE; 3669 #endif 3670 } 3671 return (retval); 3672 } 3673 3674 #ifndef __sparc 3675 static bge_regno_t quiesce_regs[] = { 3676 READ_DMA_MODE_REG, 3677 DMA_COMPLETION_MODE_REG, 3678 WRITE_DMA_MODE_REG, 3679 BGE_REGNO_NONE 3680 }; 3681 3682 void bge_chip_stop_nonblocking(bge_t *bgep); 3683 #pragma no_inline(bge_chip_stop_nonblocking) 3684 3685 /* 3686 * This function is called by bge_quiesce(). We 3687 * turn off all the DMA engines here. 3688 */ 3689 void 3690 bge_chip_stop_nonblocking(bge_t *bgep) 3691 { 3692 bge_regno_t *rbp; 3693 3694 /* 3695 * Flag that no more activity may be initiated 3696 */ 3697 bgep->progress &= ~PROGRESS_READY; 3698 3699 rbp = quiesce_regs; 3700 while (*rbp != BGE_REGNO_NONE) { 3701 (void) bge_chip_disable_engine(bgep, *rbp, 0); 3702 ++rbp; 3703 } 3704 3705 bgep->bge_chip_state = BGE_CHIP_STOPPED; 3706 } 3707 3708 #endif 3709 3710 /* 3711 * bge_chip_stop() -- stop all chip processing 3712 * 3713 * If the <fault> parameter is B_TRUE, we're stopping the chip because 3714 * we've detected a problem internally; otherwise, this is a normal 3715 * (clean) stop (at user request i.e. the last STREAM has been closed). 3716 */ 3717 void bge_chip_stop(bge_t *bgep, boolean_t fault); 3718 #pragma no_inline(bge_chip_stop) 3719 3720 void 3721 bge_chip_stop(bge_t *bgep, boolean_t fault) 3722 { 3723 bge_regno_t regno; 3724 bge_regno_t *rbp; 3725 boolean_t ok = B_TRUE; 3726 3727 BGE_TRACE(("bge_chip_stop($%p)", 3728 (void *)bgep)); 3729 3730 ASSERT(mutex_owned(bgep->genlock)); 3731 3732 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, 3733 (pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MHCR) | 3734 MHCR_MASK_PCI_INT_OUTPUT)); 3735 3736 ok &= bge_chip_disable_engine(bgep, RECEIVE_MAC_MODE_REG, 0); 3737 ok &= bge_chip_disable_engine(bgep, RCV_BD_INITIATOR_MODE_REG, 0); 3738 ok &= bge_chip_disable_engine(bgep, RCV_LIST_PLACEMENT_MODE_REG, 0); 3739 ok &= bge_chip_disable_engine(bgep, RCV_LIST_SELECTOR_MODE_REG, 0); 3740 ok &= bge_chip_disable_engine(bgep, RCV_DATA_BD_INITIATOR_MODE_REG, 0); 3741 ok &= bge_chip_disable_engine(bgep, RCV_DATA_COMPLETION_MODE_REG, 0); 3742 ok &= bge_chip_disable_engine(bgep, RCV_BD_COMPLETION_MODE_REG, 0); 3743 3744 ok &= bge_chip_disable_engine(bgep, SEND_BD_SELECTOR_MODE_REG, 0); 3745 ok &= bge_chip_disable_engine(bgep, SEND_BD_INITIATOR_MODE_REG, 0); 3746 ok &= bge_chip_disable_engine(bgep, SEND_DATA_INITIATOR_MODE_REG, 0); 3747 ok &= bge_chip_disable_engine(bgep, READ_DMA_MODE_REG, 0); 3748 ok &= bge_chip_disable_engine(bgep, SEND_DATA_COMPLETION_MODE_REG, 0); 3749 ok &= bge_chip_disable_engine(bgep, DMA_COMPLETION_MODE_REG, 0); 3750 ok &= bge_chip_disable_engine(bgep, SEND_BD_COMPLETION_MODE_REG, 0); 3751 ok &= bge_chip_disable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0); 3752 3753 bge_reg_clr32(bgep, ETHERNET_MAC_MODE_REG, ETHERNET_MODE_ENABLE_TDE); 3754 drv_usecwait(40); 3755 3756 ok &= bge_chip_disable_engine(bgep, HOST_COALESCE_MODE_REG, 0); 3757 ok &= bge_chip_disable_engine(bgep, WRITE_DMA_MODE_REG, 0); 3758 ok &= bge_chip_disable_engine(bgep, MBUF_CLUSTER_FREE_MODE_REG, 0); 3759 ok &= bge_chip_disable_engine(bgep, FTQ_RESET_REG, 0); 3760 ok &= bge_chip_disable_engine(bgep, BUFFER_MANAGER_MODE_REG, 0); 3761 ok &= bge_chip_disable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0); 3762 ok &= bge_chip_disable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0); 3763 3764 if (!ok && !fault) 3765 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 3766 3767 /* 3768 * Finally, disable (all) MAC events & clear the MAC status 3769 */ 3770 bge_reg_put32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 0); 3771 bge_reg_put32(bgep, ETHERNET_MAC_STATUS_REG, ~0); 3772 3773 /* 3774 * if we're stopping the chip because of a detected fault then do 3775 * appropriate actions 3776 */ 3777 if (fault) { 3778 if (bgep->bge_chip_state != BGE_CHIP_FAULT) { 3779 bgep->bge_chip_state = BGE_CHIP_FAULT; 3780 if (!bgep->manual_reset) 3781 ddi_fm_service_impact(bgep->devinfo, 3782 DDI_SERVICE_LOST); 3783 if (bgep->bge_dma_error) { 3784 /* 3785 * need to free buffers in case the fault was 3786 * due to a memory error in a buffer - got to 3787 * do a fair bit of tidying first 3788 */ 3789 if (bgep->progress & PROGRESS_KSTATS) { 3790 bge_fini_kstats(bgep); 3791 bgep->progress &= ~PROGRESS_KSTATS; 3792 } 3793 if (bgep->progress & PROGRESS_INTR) { 3794 bge_intr_disable(bgep); 3795 rw_enter(bgep->errlock, RW_WRITER); 3796 bge_fini_rings(bgep); 3797 rw_exit(bgep->errlock); 3798 bgep->progress &= ~PROGRESS_INTR; 3799 } 3800 if (bgep->progress & PROGRESS_BUFS) { 3801 bge_free_bufs(bgep); 3802 bgep->progress &= ~PROGRESS_BUFS; 3803 } 3804 bgep->bge_dma_error = B_FALSE; 3805 } 3806 } 3807 } else 3808 bgep->bge_chip_state = BGE_CHIP_STOPPED; 3809 } 3810 3811 /* 3812 * Poll for completion of chip's ROM firmware; also, at least on the 3813 * first time through, find and return the hardware MAC address, if any. 3814 */ 3815 static uint64_t bge_poll_firmware(bge_t *bgep); 3816 #pragma no_inline(bge_poll_firmware) 3817 3818 static uint64_t 3819 bge_poll_firmware(bge_t *bgep) 3820 { 3821 uint64_t magic; 3822 uint64_t mac; 3823 uint32_t gen, val; 3824 uint32_t i; 3825 3826 /* 3827 * Step 19: poll for firmware completion (GENCOMM port set 3828 * to the ones complement of T3_MAGIC_NUMBER). 3829 * 3830 * While we're at it, we also read the MAC address register; 3831 * at some stage the firmware will load this with the 3832 * factory-set value. 3833 * 3834 * When both the magic number and the MAC address are set, 3835 * we're done; but we impose a time limit of one second 3836 * (1000*1000us) in case the firmware fails in some fashion 3837 * or the SEEPROM that provides that MAC address isn't fitted. 3838 * 3839 * After the first time through (chip state != INITIAL), we 3840 * don't need the MAC address to be set (we've already got it 3841 * or not, from the first time), so we don't wait for it, but 3842 * we still have to wait for the T3_MAGIC_NUMBER. 3843 * 3844 * Note: the magic number is only a 32-bit quantity, but the NIC 3845 * memory is 64-bit (and big-endian) internally. Addressing the 3846 * GENCOMM word as "the upper half of a 64-bit quantity" makes 3847 * it work correctly on both big- and little-endian hosts. 3848 */ 3849 if (MHCR_CHIP_ASIC_REV(bgep) == MHCR_CHIP_ASIC_REV_5906) { 3850 for (i = 0; i < 1000; ++i) { 3851 drv_usecwait(1000); 3852 val = bge_reg_get32(bgep, VCPU_STATUS_REG); 3853 if (val & VCPU_INIT_DONE) 3854 break; 3855 } 3856 BGE_DEBUG(("bge_poll_firmware($%p): return after %d loops", 3857 (void *)bgep, i)); 3858 mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0)); 3859 } else { 3860 for (i = 0; i < 1000; ++i) { 3861 drv_usecwait(1000); 3862 gen = bge_nic_get64(bgep, NIC_MEM_GENCOMM) >> 32; 3863 if (i == 0 && DEVICE_5704_SERIES_CHIPSETS(bgep)) 3864 drv_usecwait(100000); 3865 mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0)); 3866 #ifdef BGE_IPMI_ASF 3867 if (!bgep->asf_enabled) { 3868 #endif 3869 if (gen != ~T3_MAGIC_NUMBER) 3870 continue; 3871 #ifdef BGE_IPMI_ASF 3872 } 3873 #endif 3874 if (mac != 0ULL) 3875 break; 3876 if (bgep->bge_chip_state != BGE_CHIP_INITIAL) 3877 break; 3878 } 3879 } 3880 3881 magic = bge_nic_get64(bgep, NIC_MEM_GENCOMM); 3882 BGE_DEBUG(("bge_poll_firmware($%p): PXE magic 0x%x after %d loops", 3883 (void *)bgep, gen, i)); 3884 BGE_DEBUG(("bge_poll_firmware: MAC %016llx, GENCOMM %016llx", 3885 mac, magic)); 3886 3887 return (mac); 3888 } 3889 3890 /* 3891 * Maximum times of trying to get the NVRAM access lock 3892 * by calling bge_nvmem_acquire() 3893 */ 3894 #define MAX_TRY_NVMEM_ACQUIRE 10000 3895 3896 #ifdef BGE_IPMI_ASF 3897 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode); 3898 #else 3899 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma); 3900 #endif 3901 #pragma no_inline(bge_chip_reset) 3902 3903 int 3904 #ifdef BGE_IPMI_ASF 3905 bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode) 3906 #else 3907 bge_chip_reset(bge_t *bgep, boolean_t enable_dma) 3908 #endif 3909 { 3910 chip_id_t chipid; 3911 uint64_t mac; 3912 uint64_t magic; 3913 uint32_t tmp; 3914 uint32_t mhcr_base; 3915 uint32_t mhcr; 3916 uint32_t sx0; 3917 uint32_t i, tries; 3918 #ifdef BGE_IPMI_ASF 3919 uint32_t mailbox; 3920 #endif 3921 int retval = DDI_SUCCESS; 3922 3923 BGE_TRACE(("bge_chip_reset($%p, %d)", 3924 (void *)bgep, enable_dma)); 3925 3926 ASSERT(mutex_owned(bgep->genlock)); 3927 3928 BGE_DEBUG(("bge_chip_reset($%p, %d): current state is %d", 3929 (void *)bgep, enable_dma, bgep->bge_chip_state)); 3930 3931 /* 3932 * Do we need to stop the chip cleanly before resetting? 3933 */ 3934 switch (bgep->bge_chip_state) { 3935 default: 3936 _NOTE(NOTREACHED) 3937 return (DDI_FAILURE); 3938 3939 case BGE_CHIP_INITIAL: 3940 case BGE_CHIP_STOPPED: 3941 case BGE_CHIP_RESET: 3942 break; 3943 3944 case BGE_CHIP_RUNNING: 3945 case BGE_CHIP_ERROR: 3946 case BGE_CHIP_FAULT: 3947 bge_chip_stop(bgep, B_FALSE); 3948 break; 3949 } 3950 3951 mhcr_base = MHCR_ENABLE_INDIRECT_ACCESS | 3952 MHCR_ENABLE_PCI_STATE_RW | 3953 MHCR_ENABLE_TAGGED_STATUS_MODE | 3954 MHCR_MASK_INTERRUPT_MODE | 3955 MHCR_MASK_PCI_INT_OUTPUT | 3956 MHCR_CLEAR_INTERRUPT_INTA; 3957 3958 #ifdef BGE_IPMI_ASF 3959 if (bgep->asf_enabled) { 3960 mhcr = mhcr_base; 3961 #ifdef _BIG_ENDIAN 3962 mhcr |= (MHCR_ENABLE_ENDIAN_WORD_SWAP | 3963 MHCR_ENABLE_ENDIAN_BYTE_SWAP); 3964 #endif 3965 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr); 3966 3967 bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG, 3968 bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG) | 3969 MEMORY_ARBITER_ENABLE); 3970 3971 if (asf_mode == ASF_MODE_INIT) { 3972 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 3973 } else if (asf_mode == ASF_MODE_SHUTDOWN) { 3974 bge_asf_pre_reset_operations(bgep, BGE_SHUTDOWN_RESET); 3975 } 3976 } 3977 #endif 3978 3979 /* 3980 * Adapted from Broadcom document 570X-PG102-R, pp 102-116. 3981 * Updated to reflect Broadcom document 570X-PG104-R, pp 146-159. 3982 * 3983 * Before reset Core clock,it is 3984 * also required to initialize the Memory Arbiter as specified in step9 3985 * and Misc Host Control Register as specified in step-13 3986 * Step 4-5: reset Core clock & wait for completion 3987 * Steps 6-8: are done by bge_chip_cfg_init() 3988 * put the T3_MAGIC_NUMBER into the GENCOMM port before reset 3989 */ 3990 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 3991 retval = DDI_FAILURE; 3992 3993 mhcr = mhcr_base; 3994 #ifdef _BIG_ENDIAN 3995 mhcr |= (MHCR_ENABLE_ENDIAN_WORD_SWAP | 3996 MHCR_ENABLE_ENDIAN_BYTE_SWAP); 3997 #endif 3998 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr); 3999 4000 #ifdef BGE_IPMI_ASF 4001 if (bgep->asf_enabled) 4002 bgep->asf_wordswapped = B_FALSE; 4003 #endif 4004 /* 4005 * NVRAM Corruption Workaround 4006 */ 4007 for (tries = 0; tries < MAX_TRY_NVMEM_ACQUIRE; tries++) 4008 if (bge_nvmem_acquire(bgep) != EAGAIN) 4009 break; 4010 if (tries >= MAX_TRY_NVMEM_ACQUIRE) 4011 BGE_DEBUG(("%s: fail to acquire nvram lock", 4012 bgep->ifname)); 4013 4014 bge_ape_lock(bgep, BGE_APE_LOCK_GRC); 4015 4016 #ifdef BGE_IPMI_ASF 4017 if (!bgep->asf_enabled) { 4018 #endif 4019 magic = (uint64_t)T3_MAGIC_NUMBER << 32; 4020 bge_nic_put64(bgep, NIC_MEM_GENCOMM, magic); 4021 #ifdef BGE_IPMI_ASF 4022 } 4023 #endif 4024 4025 if (DEVICE_5717_SERIES_CHIPSETS(bgep) || 4026 DEVICE_5725_SERIES_CHIPSETS(bgep)) { 4027 bge_reg_set32(bgep, FAST_BOOT_PC, 0); 4028 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 4029 retval = DDI_FAILURE; 4030 } 4031 4032 mhcr = mhcr_base; 4033 #ifdef _BIG_ENDIAN 4034 mhcr |= (MHCR_ENABLE_ENDIAN_WORD_SWAP | 4035 MHCR_ENABLE_ENDIAN_BYTE_SWAP); 4036 #endif 4037 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr); 4038 4039 if (!bge_chip_reset_engine(bgep, MISC_CONFIG_REG)) 4040 retval = DDI_FAILURE; 4041 4042 bge_chip_cfg_init(bgep, &chipid, enable_dma); 4043 4044 /* 4045 * Step 8a: This may belong elsewhere, but BCM5721 needs 4046 * a bit set to avoid a fifo overflow/underflow bug. 4047 */ 4048 if ((bgep->chipid.chip_label == 5721) || 4049 (bgep->chipid.chip_label == 5751) || 4050 (bgep->chipid.chip_label == 5752) || 4051 (bgep->chipid.chip_label == 5755) || 4052 (bgep->chipid.chip_label == 5756) || 4053 (bgep->chipid.chip_label == 5789) || 4054 (bgep->chipid.chip_label == 5906)) 4055 bge_reg_set32(bgep, TLP_CONTROL_REG, TLP_DATA_FIFO_PROTECT); 4056 4057 /* 4058 * Step 9: enable MAC memory arbiter,bit30 and bit31 of 5714/5715 should 4059 * not be changed. 4060 */ 4061 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 4062 retval = DDI_FAILURE; 4063 4064 /* 4065 * Steps 10-11: configure PIO endianness options and 4066 * enable indirect register access -- already done 4067 * Steps 12-13: enable writing to the PCI state & clock 4068 * control registers -- not required; we aren't going to 4069 * use those features. 4070 * Steps 14-15: Configure DMA endianness options. See 4071 * the comments on the setting of the MHCR above. 4072 */ 4073 tmp = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME; 4074 #ifdef _BIG_ENDIAN 4075 tmp |= (MODE_WORD_SWAP_NONFRAME | MODE_BYTE_SWAP_NONFRAME); 4076 #endif 4077 #ifdef BGE_IPMI_ASF 4078 if (bgep->asf_enabled) 4079 tmp |= MODE_HOST_STACK_UP; 4080 #endif 4081 bge_reg_put32(bgep, MODE_CONTROL_REG, tmp); 4082 4083 #ifdef BGE_IPMI_ASF 4084 if (bgep->asf_enabled) { 4085 #ifdef __sparc 4086 bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG, 4087 MEMORY_ARBITER_ENABLE | 4088 bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG)); 4089 #endif 4090 4091 #ifdef BGE_NETCONSOLE 4092 if (!bgep->asf_newhandshake) { 4093 if ((asf_mode == ASF_MODE_INIT) || 4094 (asf_mode == ASF_MODE_POST_INIT)) { 4095 bge_asf_post_reset_old_mode(bgep, 4096 BGE_INIT_RESET); 4097 } else { 4098 bge_asf_post_reset_old_mode(bgep, 4099 BGE_SHUTDOWN_RESET); 4100 } 4101 } 4102 #endif 4103 4104 /* Wait for NVRAM init */ 4105 i = 0; 4106 drv_usecwait(5000); 4107 mailbox = bge_nic_get32(bgep, BGE_FIRMWARE_MAILBOX); 4108 4109 while ((mailbox != (uint32_t) 4110 ~BGE_MAGIC_NUM_FIRMWARE_INIT_DONE) && 4111 (i < 10000)) { 4112 drv_usecwait(100); 4113 mailbox = bge_nic_get32(bgep, 4114 BGE_FIRMWARE_MAILBOX); 4115 i++; 4116 } 4117 4118 #ifndef BGE_NETCONSOLE 4119 if (!bgep->asf_newhandshake) { 4120 if ((asf_mode == ASF_MODE_INIT) || 4121 (asf_mode == ASF_MODE_POST_INIT)) { 4122 4123 bge_asf_post_reset_old_mode(bgep, 4124 BGE_INIT_RESET); 4125 } else { 4126 bge_asf_post_reset_old_mode(bgep, 4127 BGE_SHUTDOWN_RESET); 4128 } 4129 } 4130 #endif 4131 } 4132 #endif 4133 4134 bge_ape_unlock(bgep, BGE_APE_LOCK_GRC); 4135 4136 /* 4137 * Steps 16-17: poll for firmware completion 4138 */ 4139 mac = bge_poll_firmware(bgep); 4140 4141 if (bgep->chipid.device == DEVICE_ID_5720) { 4142 tmp = bge_reg_get32(bgep, CPMU_CLCK_ORIDE_REG); 4143 bge_reg_put32(bgep, CPMU_CLCK_ORIDE_REG, 4144 (tmp & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN)); 4145 } 4146 4147 /* 4148 * Step 18: enable external memory -- doesn't apply. 4149 * 4150 * However we take the opportunity to set the MLCR anyway, as 4151 * this register also controls the SEEPROM auto-access method 4152 * which we may want to use later ... 4153 * 4154 * The proper value here depends on the way the chip is wired 4155 * into the circuit board, as this register *also* controls which 4156 * of the "Miscellaneous I/O" pins are driven as outputs and the 4157 * values driven onto those pins! 4158 * 4159 * See also step 74 in the PRM ... 4160 */ 4161 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, 4162 bgep->chipid.bge_mlcr_default); 4163 4164 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 4165 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 4166 tmp = bge_reg_get32(bgep, SERDES_RX_CONTROL); 4167 tmp |= SERDES_RX_CONTROL_SIG_DETECT; 4168 bge_reg_put32(bgep, SERDES_RX_CONTROL, tmp); 4169 } 4170 4171 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 4172 4173 /* 4174 * Step 20: clear the Ethernet MAC mode register 4175 */ 4176 if (bgep->ape_enabled) 4177 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, 4178 ETHERNET_MODE_APE_TX_EN | ETHERNET_MODE_APE_RX_EN); 4179 else 4180 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, 0); 4181 4182 /* 4183 * Step 21: restore cache-line-size, latency timer, and 4184 * subsystem ID registers to their original values (not 4185 * those read into the local structure <chipid>, 'cos 4186 * that was after they were cleared by the RESET). 4187 * 4188 * Note: the Subsystem Vendor/Device ID registers are not 4189 * directly writable in config space, so we use the shadow 4190 * copy in "Page Zero" of register space to restore them 4191 * both in one go ... 4192 */ 4193 pci_config_put8(bgep->cfg_handle, PCI_CONF_CACHE_LINESZ, 4194 bgep->chipid.clsize); 4195 pci_config_put8(bgep->cfg_handle, PCI_CONF_LATENCY_TIMER, 4196 bgep->chipid.latency); 4197 bge_reg_put32(bgep, PCI_CONF_SUBVENID, 4198 (bgep->chipid.subdev << 16) | bgep->chipid.subven); 4199 4200 /* 4201 * The SEND INDEX registers should be reset to zero by the 4202 * global chip reset; if they're not, there'll be trouble 4203 * later on. 4204 */ 4205 sx0 = bge_reg_get32(bgep, NIC_DIAG_SEND_INDEX_REG(0)); 4206 if (sx0 != 0) { 4207 BGE_REPORT((bgep, "SEND INDEX - device didn't RESET")); 4208 bge_fm_ereport(bgep, DDI_FM_DEVICE_INVAL_STATE); 4209 retval = DDI_FAILURE; 4210 } 4211 4212 /* Enable MSI code */ 4213 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 4214 bge_reg_set32(bgep, MSI_MODE_REG, 4215 MSI_PRI_HIGHEST|MSI_MSI_ENABLE|MSI_ERROR_ATTENTION); 4216 4217 /* 4218 * On the first time through, save the factory-set MAC address 4219 * (if any). If bge_poll_firmware() above didn't return one 4220 * (from a chip register) consider looking in the attached NV 4221 * memory device, if any. Once we have it, we save it in both 4222 * register-image (64-bit) and byte-array forms. All-zero and 4223 * all-one addresses are not valid, and we refuse to stash those. 4224 */ 4225 if (bgep->bge_chip_state == BGE_CHIP_INITIAL) { 4226 if (mac == 0ULL) 4227 mac = bge_get_nvmac(bgep); 4228 if (mac != 0ULL && mac != ~0ULL) { 4229 bgep->chipid.hw_mac_addr = mac; 4230 for (i = ETHERADDRL; i-- != 0; ) { 4231 bgep->chipid.vendor_addr.addr[i] = (uchar_t)mac; 4232 mac >>= 8; 4233 } 4234 bgep->chipid.vendor_addr.set = B_TRUE; 4235 } 4236 } 4237 4238 #ifdef BGE_IPMI_ASF 4239 if (bgep->asf_enabled && bgep->asf_newhandshake) { 4240 if (asf_mode != ASF_MODE_NONE) { 4241 if ((asf_mode == ASF_MODE_INIT) || 4242 (asf_mode == ASF_MODE_POST_INIT)) { 4243 4244 bge_asf_post_reset_new_mode(bgep, 4245 BGE_INIT_RESET); 4246 } else { 4247 bge_asf_post_reset_new_mode(bgep, 4248 BGE_SHUTDOWN_RESET); 4249 } 4250 } 4251 } 4252 #endif 4253 4254 /* 4255 * Record the new state 4256 */ 4257 bgep->chip_resets += 1; 4258 bgep->bge_chip_state = BGE_CHIP_RESET; 4259 return (retval); 4260 } 4261 4262 /* 4263 * bge_chip_start() -- start the chip transmitting and/or receiving, 4264 * including enabling interrupts 4265 */ 4266 int bge_chip_start(bge_t *bgep, boolean_t reset_phys); 4267 #pragma no_inline(bge_chip_start) 4268 4269 void 4270 bge_chip_coalesce_update(bge_t *bgep) 4271 { 4272 bge_reg_put32(bgep, SEND_COALESCE_MAX_BD_REG, 4273 bgep->chipid.tx_count_norm); 4274 bge_reg_put32(bgep, SEND_COALESCE_TICKS_REG, 4275 bgep->chipid.tx_ticks_norm); 4276 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, 4277 bgep->chipid.rx_count_norm); 4278 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, 4279 bgep->chipid.rx_ticks_norm); 4280 } 4281 4282 int 4283 bge_chip_start(bge_t *bgep, boolean_t reset_phys) 4284 { 4285 uint32_t coalmode; 4286 uint32_t ledctl; 4287 uint32_t mtu; 4288 uint32_t maxring; 4289 uint32_t stats_mask; 4290 uint32_t dma_wrprio; 4291 uint64_t ring; 4292 uint32_t reg; 4293 uint32_t regval; 4294 uint32_t mhcr; 4295 int retval = DDI_SUCCESS; 4296 int i; 4297 4298 BGE_TRACE(("bge_chip_start($%p)", 4299 (void *)bgep)); 4300 4301 ASSERT(mutex_owned(bgep->genlock)); 4302 ASSERT(bgep->bge_chip_state == BGE_CHIP_RESET); 4303 4304 /* Initialize EEE, enable MAC control of LPI */ 4305 bge_eee_init(bgep); 4306 4307 if (bgep->ape_enabled) { 4308 /* 4309 * Allow reads and writes to the 4310 * APE register and memory space. 4311 */ 4312 regval = pci_config_get32(bgep->cfg_handle, 4313 PCI_CONF_BGE_PCISTATE); 4314 regval |= PCISTATE_ALLOW_APE_CTLSPC_WR | 4315 PCISTATE_ALLOW_APE_SHMEM_WR | PCISTATE_ALLOW_APE_PSPACE_WR; 4316 pci_config_put32(bgep->cfg_handle, 4317 PCI_CONF_BGE_PCISTATE, regval); 4318 } 4319 4320 /* 4321 * Taken from Broadcom document 570X-PG102-R, pp 102-116. 4322 * The document specifies 95 separate steps to fully 4323 * initialise the chip!!!! 4324 * 4325 * The reset code above has already got us as far as step 4326 * 21, so we continue with ... 4327 * 4328 * Step 22: clear the MAC statistics block 4329 * (0x0300-0x0aff in NIC-local memory) 4330 */ 4331 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 4332 bge_nic_zero(bgep, NIC_MEM_STATISTICS, 4333 NIC_MEM_STATISTICS_SIZE); 4334 4335 /* 4336 * Step 23: clear the status block (in host memory) 4337 */ 4338 DMA_ZERO(bgep->status_block); 4339 4340 /* 4341 * Step 24: set DMA read/write control register 4342 */ 4343 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_PDRWCR, 4344 bgep->chipid.bge_dma_rwctrl); 4345 4346 /* 4347 * Step 25: Configure DMA endianness -- already done (16/17) 4348 * Step 26: Configure Host-Based Send Rings 4349 * Step 27: Indicate Host Stack Up 4350 */ 4351 bge_reg_set32(bgep, MODE_CONTROL_REG, 4352 MODE_HOST_SEND_BDS | 4353 MODE_HOST_STACK_UP); 4354 4355 if (DEVICE_5717_SERIES_CHIPSETS(bgep) || 4356 DEVICE_5725_SERIES_CHIPSETS(bgep)) { 4357 reg = (CHIP_ASIC_REV(bgep) == CHIP_ASIC_REV_5762) 4358 ? RDMA_RSRV_CTRL_REG2 : RDMA_RSRV_CTRL_REG; 4359 regval = bge_reg_get32(bgep, reg); 4360 if ((bgep->chipid.device == DEVICE_ID_5719) || 4361 (bgep->chipid.device == DEVICE_ID_5720) || 4362 (CHIP_ASIC_REV(bgep) == CHIP_ASIC_REV_5762)) { 4363 regval &= ~(RDMA_RSRV_CTRL_TXMRGN_MASK | 4364 RDMA_RSRV_CTRL_FIFO_LWM_MASK | 4365 RDMA_RSRV_CTRL_FIFO_HWM_MASK); 4366 regval |= (RDMA_RSRV_CTRL_TXMRGN_320B | 4367 RDMA_RSRV_CTRL_FIFO_LWM_1_5K | 4368 RDMA_RSRV_CTRL_FIFO_HWM_1_5K); 4369 } 4370 /* Enable the DMA FIFO Overrun fix. */ 4371 bge_reg_put32(bgep, reg, 4372 (regval | RDMA_RSRV_CTRL_FIFO_OFLW_FIX)); 4373 4374 if ((CHIP_ASIC_REV(bgep) == CHIP_ASIC_REV_5719) || 4375 (CHIP_ASIC_REV(bgep) == CHIP_ASIC_REV_5720) || 4376 (CHIP_ASIC_REV(bgep) == CHIP_ASIC_REV_5762)) { 4377 reg = (CHIP_ASIC_REV(bgep) == CHIP_ASIC_REV_5762) 4378 ? RDMA_CORR_CTRL_REG2 : RDMA_CORR_CTRL_REG; 4379 regval = bge_reg_get32(bgep, reg); 4380 bge_reg_put32(bgep, reg, (regval | 4381 RDMA_CORR_CTRL_BLEN_BD_4K | 4382 RDMA_CORR_CTRL_BLEN_LSO_4K)); 4383 } 4384 } 4385 4386 /* 4387 * Step 28: Configure checksum options: 4388 * Solaris supports the hardware default checksum options. 4389 * 4390 * Workaround for Incorrect pseudo-header checksum calculation. 4391 */ 4392 if (bgep->chipid.flags & CHIP_FLAG_PARTIAL_CSUM) 4393 bge_reg_set32(bgep, MODE_CONTROL_REG, 4394 MODE_SEND_NO_PSEUDO_HDR_CSUM); 4395 4396 /* 4397 * Step 29: configure Timer Prescaler. The value is always the 4398 * same: the Core Clock frequency in MHz (66), minus 1, shifted 4399 * into bits 7-1. Don't set bit 0, 'cos that's the RESET bit 4400 * for the whole chip! 4401 */ 4402 regval = bge_reg_get32(bgep, MISC_CONFIG_REG); 4403 regval = (regval & 0xffffff00) | MISC_CONFIG_DEFAULT; 4404 bge_reg_put32(bgep, MISC_CONFIG_REG, regval); 4405 4406 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) { 4407 drv_usecwait(40); 4408 /* put PHY into ready state */ 4409 bge_reg_clr32(bgep, MISC_CONFIG_REG, MISC_CONFIG_EPHY_IDDQ); 4410 (void) bge_reg_get32(bgep, MISC_CONFIG_REG); /* flush */ 4411 drv_usecwait(40); 4412 } 4413 4414 /* 4415 * Steps 30-31: Configure MAC local memory pool & DMA pool registers 4416 * 4417 * If the mbuf_length is specified as 0, we just leave these at 4418 * their hardware defaults, rather than explicitly setting them. 4419 * As the Broadcom HRM,driver better not change the parameters 4420 * when the chipsets is 5705/5788/5721/5751/5714 and 5715. 4421 */ 4422 if ((bgep->chipid.mbuf_length != 0) && 4423 (DEVICE_5704_SERIES_CHIPSETS(bgep))) { 4424 bge_reg_put32(bgep, MBUF_POOL_BASE_REG, 4425 bgep->chipid.mbuf_base); 4426 bge_reg_put32(bgep, MBUF_POOL_LENGTH_REG, 4427 bgep->chipid.mbuf_length); 4428 bge_reg_put32(bgep, DMAD_POOL_BASE_REG, 4429 DMAD_POOL_BASE_DEFAULT); 4430 bge_reg_put32(bgep, DMAD_POOL_LENGTH_REG, 4431 DMAD_POOL_LENGTH_DEFAULT); 4432 } 4433 4434 /* 4435 * Step 32: configure MAC memory pool watermarks 4436 */ 4437 bge_reg_put32(bgep, RDMA_MBUF_LOWAT_REG, 4438 bgep->chipid.mbuf_lo_water_rdma); 4439 bge_reg_put32(bgep, MAC_RX_MBUF_LOWAT_REG, 4440 bgep->chipid.mbuf_lo_water_rmac); 4441 bge_reg_put32(bgep, MBUF_HIWAT_REG, 4442 bgep->chipid.mbuf_hi_water); 4443 4444 /* 4445 * Step 33: configure DMA resource watermarks 4446 */ 4447 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 4448 bge_reg_put32(bgep, DMAD_POOL_LOWAT_REG, 4449 bge_dmad_lo_water); 4450 bge_reg_put32(bgep, DMAD_POOL_HIWAT_REG, 4451 bge_dmad_hi_water); 4452 } 4453 bge_reg_put32(bgep, LOWAT_MAX_RECV_FRAMES_REG, bge_lowat_recv_frames); 4454 4455 /* 4456 * Steps 34-36: enable buffer manager & internal h/w queues 4457 */ 4458 regval = STATE_MACHINE_ATTN_ENABLE_BIT; 4459 if (bgep->chipid.device == DEVICE_ID_5719) 4460 regval |= BUFFER_MANAGER_MODE_NO_TX_UNDERRUN; 4461 if (DEVICE_5717_SERIES_CHIPSETS(bgep) || 4462 DEVICE_5725_SERIES_CHIPSETS(bgep)) 4463 regval |= BUFFER_MANAGER_MODE_MBLOW_ATTN_ENABLE; 4464 if (!bge_chip_enable_engine(bgep, BUFFER_MANAGER_MODE_REG, regval)) 4465 retval = DDI_FAILURE; 4466 4467 if (!bge_chip_enable_engine(bgep, FTQ_RESET_REG, 0)) 4468 retval = DDI_FAILURE; 4469 4470 /* 4471 * Steps 37-39: initialise Receive Buffer (Producer) RCBs 4472 */ 4473 if (DEVICE_5717_SERIES_CHIPSETS(bgep) || 4474 DEVICE_5725_SERIES_CHIPSETS(bgep)) { 4475 buff_ring_t *brp = &bgep->buff[BGE_STD_BUFF_RING]; 4476 bge_reg_put64(bgep, STD_RCV_BD_RING_RCB_REG, 4477 brp->desc.cookie.dmac_laddress); 4478 bge_reg_put32(bgep, STD_RCV_BD_RING_RCB_REG + 8, 4479 (brp->desc.nslots) << 16 | brp->buf[0].size << 2); 4480 bge_reg_put32(bgep, STD_RCV_BD_RING_RCB_REG + 0xc, 4481 NIC_MEM_SHADOW_BUFF_STD_5717); 4482 } else 4483 bge_reg_putrcb(bgep, STD_RCV_BD_RING_RCB_REG, 4484 &bgep->buff[BGE_STD_BUFF_RING].hw_rcb); 4485 4486 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 4487 bge_reg_putrcb(bgep, JUMBO_RCV_BD_RING_RCB_REG, 4488 &bgep->buff[BGE_JUMBO_BUFF_RING].hw_rcb); 4489 bge_reg_putrcb(bgep, MINI_RCV_BD_RING_RCB_REG, 4490 &bgep->buff[BGE_MINI_BUFF_RING].hw_rcb); 4491 } 4492 4493 /* 4494 * Step 40: set Receive Buffer Descriptor Ring replenish thresholds 4495 */ 4496 bge_reg_put32(bgep, STD_RCV_BD_REPLENISH_REG, bge_replenish_std); 4497 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 4498 bge_reg_put32(bgep, JUMBO_RCV_BD_REPLENISH_REG, 4499 bge_replenish_jumbo); 4500 bge_reg_put32(bgep, MINI_RCV_BD_REPLENISH_REG, 4501 bge_replenish_mini); 4502 } 4503 4504 /* 4505 * Steps 41-43: clear Send Ring Producer Indices and initialise 4506 * Send Producer Rings (0x0100-0x01ff in NIC-local memory) 4507 */ 4508 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4509 maxring = BGE_SEND_RINGS_MAX; 4510 else 4511 maxring = BGE_SEND_RINGS_MAX_5705; 4512 for (ring = 0; ring < maxring; ++ring) { 4513 bge_mbx_put(bgep, SEND_RING_HOST_INDEX_REG(ring), 0); 4514 bge_mbx_put(bgep, SEND_RING_NIC_INDEX_REG(ring), 0); 4515 bge_nic_putrcb(bgep, NIC_MEM_SEND_RING(ring), 4516 &bgep->send[ring].hw_rcb); 4517 } 4518 4519 /* 4520 * Steps 44-45: initialise Receive Return Rings 4521 * (0x0200-0x02ff in NIC-local memory) 4522 */ 4523 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4524 maxring = BGE_RECV_RINGS_MAX; 4525 else 4526 maxring = BGE_RECV_RINGS_MAX_5705; 4527 for (ring = 0; ring < maxring; ++ring) 4528 bge_nic_putrcb(bgep, NIC_MEM_RECV_RING(ring), 4529 &bgep->recv[ring].hw_rcb); 4530 4531 /* 4532 * Step 46: initialise Receive Buffer (Producer) Ring indexes 4533 */ 4534 bge_mbx_put(bgep, RECV_STD_PROD_INDEX_REG, 0); 4535 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 4536 bge_mbx_put(bgep, RECV_JUMBO_PROD_INDEX_REG, 0); 4537 bge_mbx_put(bgep, RECV_MINI_PROD_INDEX_REG, 0); 4538 } 4539 /* 4540 * Step 47: configure the MAC unicast address 4541 * Step 48: configure the random backoff seed 4542 * Step 96: set up multicast filters 4543 */ 4544 #ifdef BGE_IPMI_ASF 4545 if (bge_chip_sync(bgep, B_FALSE) == DDI_FAILURE) 4546 #else 4547 if (bge_chip_sync(bgep) == DDI_FAILURE) 4548 #endif 4549 retval = DDI_FAILURE; 4550 4551 /* 4552 * Step 49: configure the MTU 4553 */ 4554 mtu = bgep->chipid.ethmax_size+ETHERFCSL+VLAN_TAGSZ; 4555 bge_reg_put32(bgep, MAC_RX_MTU_SIZE_REG, mtu); 4556 4557 /* 4558 * Step 50: configure the IPG et al 4559 */ 4560 bge_reg_put32(bgep, MAC_TX_LENGTHS_REG, MAC_TX_LENGTHS_DEFAULT); 4561 4562 /* 4563 * Step 51: configure the default Rx Return Ring 4564 */ 4565 bge_reg_put32(bgep, RCV_RULES_CONFIG_REG, RCV_RULES_CONFIG_DEFAULT); 4566 4567 /* 4568 * Steps 52-54: configure Receive List Placement, 4569 * and enable Receive List Placement Statistics 4570 */ 4571 bge_reg_put32(bgep, RCV_LP_CONFIG_REG, 4572 RCV_LP_CONFIG(bgep->chipid.rx_rings)); 4573 switch (MHCR_CHIP_ASIC_REV(bgep)) { 4574 case MHCR_CHIP_ASIC_REV_5700: 4575 case MHCR_CHIP_ASIC_REV_5701: 4576 case MHCR_CHIP_ASIC_REV_5703: 4577 case MHCR_CHIP_ASIC_REV_5704: 4578 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, ~0); 4579 break; 4580 case MHCR_CHIP_ASIC_REV_5705: 4581 break; 4582 default: 4583 stats_mask = bge_reg_get32(bgep, RCV_LP_STATS_ENABLE_MASK_REG); 4584 stats_mask &= ~RCV_LP_STATS_DISABLE_MACTQ; 4585 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, stats_mask); 4586 break; 4587 } 4588 bge_reg_set32(bgep, RCV_LP_STATS_CONTROL_REG, RCV_LP_STATS_ENABLE); 4589 4590 if (bgep->chipid.rx_rings > 1) 4591 bge_init_recv_rule(bgep); 4592 4593 /* 4594 * Steps 55-56: enable Send Data Initiator Statistics 4595 */ 4596 bge_reg_put32(bgep, SEND_INIT_STATS_ENABLE_MASK_REG, ~0); 4597 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 4598 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 4599 SEND_INIT_STATS_ENABLE | SEND_INIT_STATS_FASTER); 4600 } else { 4601 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 4602 SEND_INIT_STATS_ENABLE); 4603 } 4604 /* 4605 * Steps 57-58: stop (?) the Host Coalescing Engine 4606 */ 4607 if (!bge_chip_disable_engine(bgep, HOST_COALESCE_MODE_REG, ~0)) 4608 retval = DDI_FAILURE; 4609 4610 /* 4611 * Steps 59-62: initialise Host Coalescing parameters 4612 */ 4613 bge_chip_coalesce_update(bgep); 4614 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 4615 bge_reg_put32(bgep, SEND_COALESCE_INT_BD_REG, 4616 bge_tx_count_intr); 4617 bge_reg_put32(bgep, SEND_COALESCE_INT_TICKS_REG, 4618 bge_tx_ticks_intr); 4619 bge_reg_put32(bgep, RCV_COALESCE_INT_BD_REG, 4620 bge_rx_count_intr); 4621 bge_reg_put32(bgep, RCV_COALESCE_INT_TICKS_REG, 4622 bge_rx_ticks_intr); 4623 } 4624 4625 /* 4626 * Steps 63-64: initialise status block & statistics 4627 * host memory addresses 4628 * The statistic block does not exist in some chipsets 4629 * Step 65: initialise Statistics Coalescing Tick Counter 4630 */ 4631 bge_reg_put64(bgep, STATUS_BLOCK_HOST_ADDR_REG, 4632 bgep->status_block.cookie.dmac_laddress); 4633 4634 /* 4635 * Steps 66-67: initialise status block & statistics 4636 * NIC-local memory addresses 4637 */ 4638 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 4639 bge_reg_put64(bgep, STATISTICS_HOST_ADDR_REG, 4640 bgep->statistics.cookie.dmac_laddress); 4641 bge_reg_put32(bgep, STATISTICS_TICKS_REG, 4642 STATISTICS_TICKS_DEFAULT); 4643 bge_reg_put32(bgep, STATUS_BLOCK_BASE_ADDR_REG, 4644 NIC_MEM_STATUS_BLOCK); 4645 bge_reg_put32(bgep, STATISTICS_BASE_ADDR_REG, 4646 NIC_MEM_STATISTICS); 4647 } 4648 4649 /* 4650 * Steps 68-71: start the Host Coalescing Engine, the Receive BD 4651 * Completion Engine, the Receive List Placement Engine, and the 4652 * Receive List selector.Pay attention:0x3400 is not exist in BCM5714 4653 * and BCM5715. 4654 */ 4655 4656 if (bgep->chipid.device == DEVICE_ID_5719) { 4657 for (i = 0; i < BGE_NUM_RDMA_CHANNELS; i++) { 4658 if (bge_reg_get32(bgep, (BGE_RDMA_LENGTH + (i << 2))) > 4659 bgep->chipid.default_mtu) 4660 break; 4661 } 4662 if (i < BGE_NUM_RDMA_CHANNELS) { 4663 regval = bge_reg_get32(bgep, RDMA_CORR_CTRL_REG); 4664 regval |= RDMA_CORR_CTRL_TX_LENGTH_WA; 4665 bge_reg_put32(bgep, RDMA_CORR_CTRL_REG, regval); 4666 bgep->rdma_length_bug_on_5719 = B_TRUE; 4667 } 4668 } 4669 4670 if (bgep->chipid.tx_rings <= COALESCE_64_BYTE_RINGS && 4671 bgep->chipid.rx_rings <= COALESCE_64_BYTE_RINGS) 4672 coalmode = COALESCE_64_BYTE_STATUS; 4673 else 4674 coalmode = 0; 4675 if (DEVICE_5717_SERIES_CHIPSETS(bgep) || 4676 DEVICE_5725_SERIES_CHIPSETS(bgep)) 4677 coalmode = COALESCE_CLR_TICKS_RX; 4678 if (!bge_chip_enable_engine(bgep, HOST_COALESCE_MODE_REG, coalmode)) 4679 retval = DDI_FAILURE; 4680 if (!bge_chip_enable_engine(bgep, RCV_BD_COMPLETION_MODE_REG, 4681 STATE_MACHINE_ATTN_ENABLE_BIT)) 4682 retval = DDI_FAILURE; 4683 if (!bge_chip_enable_engine(bgep, RCV_LIST_PLACEMENT_MODE_REG, 0)) 4684 retval = DDI_FAILURE; 4685 4686 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4687 if (!bge_chip_enable_engine(bgep, RCV_LIST_SELECTOR_MODE_REG, 4688 STATE_MACHINE_ATTN_ENABLE_BIT)) 4689 retval = DDI_FAILURE; 4690 4691 /* 4692 * Step 72: Enable MAC DMA engines 4693 * Step 73: Clear & enable MAC statistics 4694 */ 4695 if (bgep->ape_enabled) { 4696 /* XXX put32 instead of set32 ? */ 4697 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, 4698 ETHERNET_MODE_APE_TX_EN | ETHERNET_MODE_APE_RX_EN); 4699 } 4700 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 4701 ETHERNET_MODE_ENABLE_FHDE | 4702 ETHERNET_MODE_ENABLE_RDE | 4703 ETHERNET_MODE_ENABLE_TDE); 4704 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 4705 ETHERNET_MODE_ENABLE_TX_STATS | 4706 ETHERNET_MODE_ENABLE_RX_STATS | 4707 ETHERNET_MODE_CLEAR_TX_STATS | 4708 ETHERNET_MODE_CLEAR_RX_STATS); 4709 4710 drv_usecwait(140); 4711 4712 if (bgep->ape_enabled) { 4713 /* Write our heartbeat update interval to APE. */ 4714 bge_ape_put32(bgep, BGE_APE_HOST_HEARTBEAT_INT_MS, 4715 APE_HOST_HEARTBEAT_INT_DISABLE); 4716 } 4717 4718 /* 4719 * Step 74: configure the MLCR (Miscellaneous Local Control 4720 * Register); not required, as we set up the MLCR in step 10 4721 * (part of the reset code) above. 4722 * 4723 * Step 75: clear Interrupt Mailbox 0 4724 */ 4725 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 0); 4726 4727 /* 4728 * Steps 76-87: Gentlemen, start your engines ... 4729 * 4730 * Enable the DMA Completion Engine, the Write DMA Engine, 4731 * the Read DMA Engine, Receive Data Completion Engine, 4732 * the MBuf Cluster Free Engine, the Send Data Completion Engine, 4733 * the Send BD Completion Engine, the Receive BD Initiator Engine, 4734 * the Receive Data Initiator Engine, the Send Data Initiator Engine, 4735 * the Send BD Initiator Engine, and the Send BD Selector Engine. 4736 * 4737 * Beware exhaust fumes? 4738 */ 4739 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4740 if (!bge_chip_enable_engine(bgep, DMA_COMPLETION_MODE_REG, 0)) 4741 retval = DDI_FAILURE; 4742 dma_wrprio = (bge_dma_wrprio << DMA_PRIORITY_SHIFT) | 4743 ALL_DMA_ATTN_BITS; 4744 /* the 5723 check here covers all newer chip families (OK) */ 4745 if ((MHCR_CHIP_ASIC_REV(bgep) == MHCR_CHIP_ASIC_REV_5755) || 4746 (MHCR_CHIP_ASIC_REV(bgep) == MHCR_CHIP_ASIC_REV_5723) || 4747 (MHCR_CHIP_ASIC_REV(bgep) == MHCR_CHIP_ASIC_REV_5906)) { 4748 dma_wrprio |= DMA_STATUS_TAG_FIX_CQ12384; 4749 } 4750 if (!bge_chip_enable_engine(bgep, WRITE_DMA_MODE_REG, 4751 dma_wrprio)) 4752 retval = DDI_FAILURE; 4753 4754 drv_usecwait(40); 4755 4756 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || 4757 DEVICE_5717_SERIES_CHIPSETS(bgep) || 4758 DEVICE_5725_SERIES_CHIPSETS(bgep)) 4759 bge_dma_rdprio = 0; 4760 if (!bge_chip_enable_engine(bgep, READ_DMA_MODE_REG, 4761 (bge_dma_rdprio << DMA_PRIORITY_SHIFT) | ALL_DMA_ATTN_BITS)) 4762 retval = DDI_FAILURE; 4763 4764 drv_usecwait(40); 4765 4766 if (!bge_chip_enable_engine(bgep, RCV_DATA_COMPLETION_MODE_REG, 4767 STATE_MACHINE_ATTN_ENABLE_BIT)) 4768 retval = DDI_FAILURE; 4769 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4770 if (!bge_chip_enable_engine(bgep, 4771 MBUF_CLUSTER_FREE_MODE_REG, 0)) 4772 retval = DDI_FAILURE; 4773 if (!bge_chip_enable_engine(bgep, SEND_DATA_COMPLETION_MODE_REG, 0)) 4774 retval = DDI_FAILURE; 4775 if (!bge_chip_enable_engine(bgep, SEND_BD_COMPLETION_MODE_REG, 4776 STATE_MACHINE_ATTN_ENABLE_BIT)) 4777 retval = DDI_FAILURE; 4778 if (!bge_chip_enable_engine(bgep, RCV_BD_INITIATOR_MODE_REG, 4779 RCV_BD_DISABLED_RING_ATTN)) 4780 retval = DDI_FAILURE; 4781 if (!bge_chip_enable_engine(bgep, RCV_DATA_BD_INITIATOR_MODE_REG, 4782 RCV_DATA_BD_ILL_RING_ATTN)) 4783 retval = DDI_FAILURE; 4784 if (!bge_chip_enable_engine(bgep, SEND_DATA_INITIATOR_MODE_REG, 0)) 4785 retval = DDI_FAILURE; 4786 if (!bge_chip_enable_engine(bgep, SEND_BD_INITIATOR_MODE_REG, 4787 STATE_MACHINE_ATTN_ENABLE_BIT)) 4788 retval = DDI_FAILURE; 4789 if (!bge_chip_enable_engine(bgep, SEND_BD_SELECTOR_MODE_REG, 4790 STATE_MACHINE_ATTN_ENABLE_BIT)) 4791 retval = DDI_FAILURE; 4792 4793 drv_usecwait(40); 4794 4795 /* 4796 * Step 88: download firmware -- doesn't apply 4797 * Steps 89-90: enable Transmit & Receive MAC Engines 4798 */ 4799 regval = 0; 4800 if (DEVICE_5717_SERIES_CHIPSETS(bgep)) { 4801 regval |= TRANSMIT_MODE_MBUF_LOCKUP_FIX; 4802 } 4803 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, regval)) 4804 retval = DDI_FAILURE; 4805 4806 drv_usecwait(100); 4807 4808 #ifdef BGE_IPMI_ASF 4809 if (!bgep->asf_enabled) { 4810 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 4811 RECEIVE_MODE_KEEP_VLAN_TAG)) 4812 retval = DDI_FAILURE; 4813 } else { 4814 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 0)) 4815 retval = DDI_FAILURE; 4816 } 4817 #else 4818 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 4819 RECEIVE_MODE_KEEP_VLAN_TAG)) 4820 retval = DDI_FAILURE; 4821 #endif 4822 4823 drv_usecwait(100); 4824 4825 /* 4826 * Step 91: disable auto-polling of PHY status 4827 */ 4828 bge_reg_put32(bgep, MI_MODE_REG, MI_MODE_DEFAULT); 4829 4830 /* 4831 * Step 92: configure D0 power state (not required) 4832 * Step 93: initialise LED control register () 4833 */ 4834 ledctl = LED_CONTROL_DEFAULT; 4835 switch (bgep->chipid.device) { 4836 case DEVICE_ID_5700: 4837 case DEVICE_ID_5700x: 4838 case DEVICE_ID_5701: 4839 /* 4840 * Switch to 5700 (MAC) mode on these older chips 4841 */ 4842 ledctl &= ~LED_CONTROL_LED_MODE_MASK; 4843 ledctl |= LED_CONTROL_LED_MODE_5700; 4844 break; 4845 4846 default: 4847 break; 4848 } 4849 bge_reg_put32(bgep, ETHERNET_MAC_LED_CONTROL_REG, ledctl); 4850 4851 /* 4852 * Step 94: activate link 4853 */ 4854 bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK); 4855 4856 /* 4857 * Step 95: set up physical layer (PHY/SerDes) 4858 * restart autoneg (if required) 4859 */ 4860 if (reset_phys) 4861 { 4862 if (bge_phys_update(bgep) == DDI_FAILURE) 4863 retval = DDI_FAILURE; 4864 /* forcing a mac link update here */ 4865 bge_phys_check(bgep); 4866 bgep->link_state = (bgep->param_link_up) ? LINK_STATE_UP : 4867 LINK_STATE_DOWN; 4868 bge_sync_mac_modes(bgep); 4869 mac_link_update(bgep->mh, bgep->link_state); 4870 } 4871 4872 /* 4873 * Extra step (DSG): hand over all the Receive Buffers to the chip 4874 */ 4875 for (ring = 0; ring < BGE_BUFF_RINGS_USED; ++ring) 4876 bge_mbx_put(bgep, bgep->buff[ring].chip_mbx_reg, 4877 bgep->buff[ring].rf_next); 4878 4879 /* 4880 * MSI bits:The least significant MSI 16-bit word. 4881 * ISR will be triggered different. 4882 */ 4883 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 4884 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 0x70); 4885 4886 /* 4887 * Extra step (DSG): select which interrupts are enabled 4888 * 4889 * Program the Ethernet MAC engine to signal attention on 4890 * Link Change events, then enable interrupts on MAC, DMA, 4891 * and FLOW attention signals. 4892 */ 4893 bge_reg_set32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 4894 ETHERNET_EVENT_LINK_INT | 4895 ETHERNET_STATUS_PCS_ERROR_INT); 4896 #ifdef BGE_IPMI_ASF 4897 if (bgep->asf_enabled) { 4898 bge_reg_set32(bgep, MODE_CONTROL_REG, 4899 MODE_INT_ON_FLOW_ATTN | 4900 MODE_INT_ON_DMA_ATTN | 4901 MODE_HOST_STACK_UP| 4902 MODE_INT_ON_MAC_ATTN); 4903 } else { 4904 #endif 4905 bge_reg_set32(bgep, MODE_CONTROL_REG, 4906 MODE_INT_ON_FLOW_ATTN | 4907 MODE_INT_ON_DMA_ATTN | 4908 MODE_INT_ON_MAC_ATTN); 4909 #ifdef BGE_IPMI_ASF 4910 } 4911 #endif 4912 4913 if (DEVICE_5717_SERIES_CHIPSETS(bgep) || 4914 DEVICE_5725_SERIES_CHIPSETS(bgep)) { 4915 bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL_5717, 4916 DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED); 4917 #if 0 4918 mhcr = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MHCR); 4919 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, 4920 (mhcr | MHCR_TLP_MINOR_ERR_TOLERANCE)); 4921 #endif 4922 } 4923 4924 /* 4925 * Step 97: enable PCI interrupts!!! 4926 */ 4927 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 4928 bge_cfg_clr32(bgep, PCI_CONF_BGE_MHCR, 4929 bgep->chipid.mask_pci_int); 4930 4931 /* 4932 * All done! 4933 */ 4934 bgep->bge_chip_state = BGE_CHIP_RUNNING; 4935 return (retval); 4936 } 4937 4938 4939 /* 4940 * ========== Hardware interrupt handler ========== 4941 */ 4942 4943 #undef BGE_DBG 4944 #define BGE_DBG BGE_DBG_INT /* debug flag for this code */ 4945 4946 /* 4947 * Sync the status block, then atomically clear the specified bits in 4948 * the <flags-and-tag> field of the status block. 4949 * the <flags> word of the status block, returning the value of the 4950 * <tag> and the <flags> before the bits were cleared. 4951 */ 4952 static int bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags); 4953 #pragma inline(bge_status_sync) 4954 4955 static int 4956 bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags) 4957 { 4958 bge_status_t *bsp; 4959 int retval; 4960 4961 BGE_TRACE(("bge_status_sync($%p, 0x%llx)", 4962 (void *)bgep, bits)); 4963 4964 ASSERT(bgep->bge_guard == BGE_GUARD); 4965 4966 DMA_SYNC(bgep->status_block, DDI_DMA_SYNC_FORKERNEL); 4967 retval = bge_check_dma_handle(bgep, bgep->status_block.dma_hdl); 4968 if (retval != DDI_FM_OK) 4969 return (retval); 4970 4971 bsp = DMA_VPTR(bgep->status_block); 4972 *flags = bge_atomic_clr64(&bsp->flags_n_tag, bits); 4973 4974 BGE_DEBUG(("bge_status_sync($%p, 0x%llx) returning 0x%llx", 4975 (void *)bgep, bits, *flags)); 4976 4977 return (retval); 4978 } 4979 4980 void bge_wake_factotum(bge_t *bgep); 4981 #pragma inline(bge_wake_factotum) 4982 4983 void 4984 bge_wake_factotum(bge_t *bgep) 4985 { 4986 mutex_enter(bgep->softintrlock); 4987 if (bgep->factotum_flag == 0) { 4988 bgep->factotum_flag = 1; 4989 ddi_trigger_softintr(bgep->factotum_id); 4990 } 4991 mutex_exit(bgep->softintrlock); 4992 } 4993 4994 static void 4995 bge_intr_error_handler(bge_t *bgep) 4996 { 4997 uint32_t flow; 4998 uint32_t rdma; 4999 uint32_t wdma; 5000 uint32_t tmac; 5001 uint32_t rmac; 5002 uint32_t rxrs; 5003 uint32_t emac; 5004 uint32_t msis; 5005 uint32_t txrs = 0; 5006 5007 ASSERT(mutex_owned(bgep->genlock)); 5008 5009 /* 5010 * Read all the registers that show the possible 5011 * reasons for the ERROR bit to be asserted 5012 */ 5013 flow = bge_reg_get32(bgep, FLOW_ATTN_REG); 5014 rdma = bge_reg_get32(bgep, READ_DMA_STATUS_REG); 5015 wdma = bge_reg_get32(bgep, WRITE_DMA_STATUS_REG); 5016 tmac = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 5017 rmac = bge_reg_get32(bgep, RECEIVE_MAC_STATUS_REG); 5018 rxrs = bge_reg_get32(bgep, RX_RISC_STATE_REG); 5019 emac = bge_reg_get32(bgep, ETHERNET_MAC_STATUS_REG); 5020 msis = bge_reg_get32(bgep, MSI_STATUS_REG); 5021 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 5022 txrs = bge_reg_get32(bgep, TX_RISC_STATE_REG); 5023 5024 BGE_DEBUG(("factotum($%p) flow 0x%x rdma 0x%x wdma 0x%x emac 0x%x msis 0x%x", 5025 (void *)bgep, flow, rdma, wdma, emac, msis)); 5026 BGE_DEBUG(("factotum($%p) tmac 0x%x rmac 0x%x rxrs 0x%08x txrs 0x%08x", 5027 (void *)bgep, tmac, rmac, rxrs, txrs)); 5028 5029 /* 5030 * For now, just clear all the errors ... 5031 */ 5032 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 5033 bge_reg_put32(bgep, TX_RISC_STATE_REG, ~0); 5034 bge_reg_put32(bgep, RX_RISC_STATE_REG, ~0); 5035 bge_reg_put32(bgep, RECEIVE_MAC_STATUS_REG, ~0); 5036 bge_reg_put32(bgep, WRITE_DMA_STATUS_REG, ~0); 5037 bge_reg_put32(bgep, READ_DMA_STATUS_REG, ~0); 5038 bge_reg_put32(bgep, FLOW_ATTN_REG, ~0); 5039 } 5040 5041 /* 5042 * bge_intr() -- handle chip interrupts 5043 */ 5044 uint_t bge_intr(caddr_t arg1, caddr_t arg2); 5045 #pragma no_inline(bge_intr) 5046 5047 uint_t 5048 bge_intr(caddr_t arg1, caddr_t arg2) 5049 { 5050 bge_t *bgep = (void *)arg1; /* private device info */ 5051 bge_status_t *bsp; 5052 uint64_t flags; 5053 uint32_t regval; 5054 uint_t result; 5055 int retval, loop_cnt = 0; 5056 5057 BGE_TRACE(("bge_intr($%p) ($%p)", arg1, arg2)); 5058 5059 /* 5060 * GLD v2 checks that s/w setup is complete before passing 5061 * interrupts to this routine, thus eliminating the old 5062 * (and well-known) race condition around ddi_add_intr() 5063 */ 5064 ASSERT(bgep->progress & PROGRESS_HWINT); 5065 5066 result = DDI_INTR_UNCLAIMED; 5067 mutex_enter(bgep->genlock); 5068 5069 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) { 5070 /* 5071 * Check whether chip's says it's asserting #INTA; 5072 * if not, don't process or claim the interrupt. 5073 * 5074 * Note that the PCI signal is active low, so the 5075 * bit is *zero* when the interrupt is asserted. 5076 */ 5077 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 5078 if (!(DEVICE_5717_SERIES_CHIPSETS(bgep) || 5079 DEVICE_5725_SERIES_CHIPSETS(bgep)) && 5080 (regval & MLCR_INTA_STATE)) { 5081 if (bge_check_acc_handle(bgep, bgep->io_handle) 5082 != DDI_FM_OK) 5083 goto chip_stop; 5084 mutex_exit(bgep->genlock); 5085 return (result); 5086 } 5087 5088 /* 5089 * Block further PCI interrupts ... 5090 */ 5091 bge_reg_set32(bgep, PCI_CONF_BGE_MHCR, 5092 bgep->chipid.mask_pci_int); 5093 5094 } else { 5095 /* 5096 * Check MSI status 5097 */ 5098 regval = bge_reg_get32(bgep, MSI_STATUS_REG); 5099 if (regval & MSI_ERROR_ATTENTION) { 5100 BGE_REPORT((bgep, "msi error attention," 5101 " status=0x%x", regval)); 5102 bge_reg_put32(bgep, MSI_STATUS_REG, regval); 5103 } 5104 } 5105 5106 result = DDI_INTR_CLAIMED; 5107 5108 BGE_DEBUG(("bge_intr($%p) ($%p) regval 0x%08x", arg1, arg2, regval)); 5109 5110 /* 5111 * Sync the status block and grab the flags-n-tag from it. 5112 * We count the number of interrupts where there doesn't 5113 * seem to have been a DMA update of the status block; if 5114 * it *has* been updated, the counter will be cleared in 5115 * the while() loop below ... 5116 */ 5117 bgep->missed_dmas += 1; 5118 bsp = DMA_VPTR(bgep->status_block); 5119 for (loop_cnt = 0; loop_cnt < bge_intr_max_loop; loop_cnt++) { 5120 if (bgep->bge_chip_state != BGE_CHIP_RUNNING) { 5121 /* 5122 * bge_chip_stop() may have freed dma area etc 5123 * while we were in this interrupt handler - 5124 * better not call bge_status_sync() 5125 */ 5126 (void) bge_check_acc_handle(bgep, 5127 bgep->io_handle); 5128 mutex_exit(bgep->genlock); 5129 return (DDI_INTR_CLAIMED); 5130 } 5131 5132 retval = bge_status_sync(bgep, STATUS_FLAG_UPDATED | 5133 STATUS_FLAG_LINK_CHANGED | STATUS_FLAG_ERROR, &flags); 5134 if (retval != DDI_FM_OK) { 5135 bgep->bge_dma_error = B_TRUE; 5136 goto chip_stop; 5137 } 5138 5139 if (!(flags & STATUS_FLAG_UPDATED)) 5140 break; 5141 5142 /* 5143 * Tell the chip that we're processing the interrupt 5144 */ 5145 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 5146 INTERRUPT_MBOX_DISABLE(flags)); 5147 if (bge_check_acc_handle(bgep, bgep->io_handle) != 5148 DDI_FM_OK) 5149 goto chip_stop; 5150 5151 if (flags & STATUS_FLAG_LINK_CHANGED) { 5152 BGE_DEBUG(("bge_intr($%p) ($%p) link event", arg1, arg2)); 5153 if (bge_phys_check(bgep)) { 5154 bgep->link_state = bgep->param_link_up ? 5155 LINK_STATE_UP : LINK_STATE_DOWN; 5156 bge_sync_mac_modes(bgep); 5157 mac_link_update(bgep->mh, bgep->link_state); 5158 } 5159 5160 if (bge_check_acc_handle(bgep, bgep->io_handle) != 5161 DDI_FM_OK) 5162 goto chip_stop; 5163 } 5164 5165 if (flags & STATUS_FLAG_ERROR) { 5166 bge_intr_error_handler(bgep); 5167 5168 if (bge_check_acc_handle(bgep, bgep->io_handle) != 5169 DDI_FM_OK) 5170 goto chip_stop; 5171 } 5172 5173 /* 5174 * Drop the mutex while we: 5175 * Receive any newly-arrived packets 5176 * Recycle any newly-finished send buffers 5177 */ 5178 bgep->bge_intr_running = B_TRUE; 5179 mutex_exit(bgep->genlock); 5180 bge_receive(bgep, bsp); 5181 (void) bge_recycle(bgep, bsp); 5182 mutex_enter(bgep->genlock); 5183 bgep->bge_intr_running = B_FALSE; 5184 5185 /* 5186 * Tell the chip we've finished processing, and 5187 * give it the tag that we got from the status 5188 * block earlier, so that it knows just how far 5189 * we've gone. If it's got more for us to do, 5190 * it will now update the status block and try 5191 * to assert an interrupt (but we've got the 5192 * #INTA blocked at present). If we see the 5193 * update, we'll loop around to do some more. 5194 * Eventually we'll get out of here ... 5195 */ 5196 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 5197 INTERRUPT_MBOX_ENABLE(flags)); 5198 if (bgep->chipid.pci_type == BGE_PCI_E) 5199 (void) bge_mbx_get(bgep, INTERRUPT_MBOX_0_REG); 5200 bgep->missed_dmas = 0; 5201 } 5202 5203 if (bgep->missed_dmas) { 5204 /* 5205 * Probably due to the internal status tag not 5206 * being reset. Force a status block update now; 5207 * this should ensure that we get an update and 5208 * a new interrupt. After that, we should be in 5209 * sync again ... 5210 */ 5211 BGE_REPORT((bgep, "interrupt: flags 0x%llx - " 5212 "not updated?", flags)); 5213 bgep->missed_updates++; 5214 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 5215 COALESCE_NOW); 5216 5217 if (bgep->missed_dmas >= bge_dma_miss_limit) { 5218 /* 5219 * If this happens multiple times in a row, 5220 * it means DMA is just not working. Maybe 5221 * the chip's failed, or maybe there's a 5222 * problem on the PCI bus or in the host-PCI 5223 * bridge (Tomatillo). 5224 * 5225 * At all events, we want to stop further 5226 * interrupts and let the recovery code take 5227 * over to see whether anything can be done 5228 * about it ... 5229 */ 5230 bge_fm_ereport(bgep, 5231 DDI_FM_DEVICE_BADINT_LIMIT); 5232 goto chip_stop; 5233 } 5234 } 5235 5236 /* 5237 * Reenable assertion of #INTA, unless there's a DMA fault 5238 */ 5239 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) { 5240 bge_reg_clr32(bgep, PCI_CONF_BGE_MHCR, 5241 bgep->chipid.mask_pci_int); 5242 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != 5243 DDI_FM_OK) 5244 goto chip_stop; 5245 } 5246 5247 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5248 goto chip_stop; 5249 5250 mutex_exit(bgep->genlock); 5251 return (result); 5252 5253 chip_stop: 5254 5255 #ifdef BGE_IPMI_ASF 5256 if (bgep->asf_enabled && bgep->asf_status == ASF_STAT_RUN) { 5257 /* 5258 * We must stop ASF heart beat before 5259 * bge_chip_stop(), otherwise some 5260 * computers (ex. IBM HS20 blade 5261 * server) may crash. 5262 */ 5263 bge_asf_update_status(bgep); 5264 bge_asf_stop_timer(bgep); 5265 bgep->asf_status = ASF_STAT_STOP; 5266 5267 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 5268 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 5269 } 5270 #endif 5271 bge_chip_stop(bgep, B_TRUE); 5272 (void) bge_check_acc_handle(bgep, bgep->io_handle); 5273 mutex_exit(bgep->genlock); 5274 return (result); 5275 } 5276 5277 /* 5278 * ========== Factotum, implemented as a softint handler ========== 5279 */ 5280 5281 #undef BGE_DBG 5282 #define BGE_DBG BGE_DBG_FACT /* debug flag for this code */ 5283 5284 /* 5285 * Factotum routine to check for Tx stall, using the 'watchdog' counter 5286 */ 5287 static boolean_t bge_factotum_stall_check(bge_t *bgep); 5288 #pragma no_inline(bge_factotum_stall_check) 5289 5290 static boolean_t 5291 bge_factotum_stall_check(bge_t *bgep) 5292 { 5293 uint32_t dogval; 5294 bge_status_t *bsp; 5295 uint64_t now = gethrtime(); 5296 5297 if ((now - bgep->timestamp) < BGE_CYCLIC_PERIOD) 5298 return (B_FALSE); 5299 5300 bgep->timestamp = now; 5301 5302 ASSERT(mutex_owned(bgep->genlock)); 5303 5304 /* 5305 * Specific check for Tx stall ... 5306 * 5307 * The 'watchdog' counter is incremented whenever a packet 5308 * is queued, reset to 1 when some (but not all) buffers 5309 * are reclaimed, reset to 0 (disabled) when all buffers 5310 * are reclaimed, and shifted left here. If it exceeds the 5311 * threshold value, the chip is assumed to have stalled and 5312 * is put into the ERROR state. The factotum will then reset 5313 * it on the next pass. 5314 * 5315 * All of which should ensure that we don't get into a state 5316 * where packets are left pending indefinitely! 5317 */ 5318 dogval = bge_atomic_shl32(&bgep->watchdog, 1); 5319 bsp = DMA_VPTR(bgep->status_block); 5320 if (dogval < bge_watchdog_count || bge_recycle(bgep, bsp)) 5321 return (B_FALSE); 5322 5323 #if !defined(BGE_NETCONSOLE) 5324 BGE_REPORT((bgep, "Tx stall detected, watchdog code 0x%x", dogval)); 5325 #endif 5326 bge_fm_ereport(bgep, DDI_FM_DEVICE_STALL); 5327 return (B_TRUE); 5328 } 5329 5330 /* 5331 * The factotum is woken up when there's something to do that we'd rather 5332 * not do from inside a hardware interrupt handler or high-level cyclic. 5333 * Its main task is to reset & restart the chip after an error. 5334 */ 5335 uint_t bge_chip_factotum(caddr_t arg); 5336 #pragma no_inline(bge_chip_factotum) 5337 5338 uint_t 5339 bge_chip_factotum(caddr_t arg) 5340 { 5341 bge_t *bgep; 5342 uint_t result; 5343 boolean_t error; 5344 int dma_state; 5345 5346 bgep = (void *)arg; 5347 5348 BGE_TRACE(("bge_chip_factotum($%p)", (void *)bgep)); 5349 5350 mutex_enter(bgep->softintrlock); 5351 if (bgep->factotum_flag == 0) { 5352 mutex_exit(bgep->softintrlock); 5353 return (DDI_INTR_UNCLAIMED); 5354 } 5355 bgep->factotum_flag = 0; 5356 mutex_exit(bgep->softintrlock); 5357 5358 result = DDI_INTR_CLAIMED; 5359 error = B_FALSE; 5360 5361 mutex_enter(bgep->genlock); 5362 switch (bgep->bge_chip_state) { 5363 default: 5364 break; 5365 5366 case BGE_CHIP_RUNNING: 5367 5368 if (bgep->chipid.device == DEVICE_ID_5700) { 5369 if (bge_phys_check(bgep)) { 5370 bgep->link_state = (bgep->param_link_up) ? 5371 LINK_STATE_UP : LINK_STATE_DOWN; 5372 bge_sync_mac_modes(bgep); 5373 mac_link_update(bgep->mh, bgep->link_state); 5374 } 5375 } 5376 5377 error = bge_factotum_stall_check(bgep); 5378 if (dma_state != DDI_FM_OK) { 5379 bgep->bge_dma_error = B_TRUE; 5380 error = B_TRUE; 5381 } 5382 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5383 error = B_TRUE; 5384 if (error) 5385 bgep->bge_chip_state = BGE_CHIP_ERROR; 5386 break; 5387 5388 case BGE_CHIP_ERROR: 5389 error = B_TRUE; 5390 break; 5391 5392 case BGE_CHIP_FAULT: 5393 /* 5394 * Fault detected, time to reset ... 5395 */ 5396 if (bge_autorecover) { 5397 if (!(bgep->progress & PROGRESS_BUFS)) { 5398 /* 5399 * if we can't allocate the ring buffers, 5400 * try later 5401 */ 5402 if (bge_alloc_bufs(bgep) != DDI_SUCCESS) { 5403 mutex_exit(bgep->genlock); 5404 return (result); 5405 } 5406 bgep->progress |= PROGRESS_BUFS; 5407 } 5408 if (!(bgep->progress & PROGRESS_INTR)) { 5409 bge_init_rings(bgep); 5410 bge_intr_enable(bgep); 5411 bgep->progress |= PROGRESS_INTR; 5412 } 5413 if (!(bgep->progress & PROGRESS_KSTATS)) { 5414 bge_init_kstats(bgep, 5415 ddi_get_instance(bgep->devinfo)); 5416 bgep->progress |= PROGRESS_KSTATS; 5417 } 5418 5419 BGE_REPORT((bgep, "automatic recovery activated")); 5420 5421 if (bge_restart(bgep, B_FALSE) != DDI_SUCCESS) { 5422 bgep->bge_chip_state = BGE_CHIP_ERROR; 5423 error = B_TRUE; 5424 } 5425 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != 5426 DDI_FM_OK) { 5427 bgep->bge_chip_state = BGE_CHIP_ERROR; 5428 error = B_TRUE; 5429 } 5430 if (bge_check_acc_handle(bgep, bgep->io_handle) != 5431 DDI_FM_OK) { 5432 bgep->bge_chip_state = BGE_CHIP_ERROR; 5433 error = B_TRUE; 5434 } 5435 if (error == B_FALSE) { 5436 #ifdef BGE_IPMI_ASF 5437 if (bgep->asf_enabled && 5438 bgep->asf_status != ASF_STAT_RUN) { 5439 bgep->asf_timeout_id = timeout( 5440 bge_asf_heartbeat, (void *)bgep, 5441 drv_usectohz( 5442 BGE_ASF_HEARTBEAT_INTERVAL)); 5443 bgep->asf_status = ASF_STAT_RUN; 5444 } 5445 #endif 5446 if (!bgep->manual_reset) { 5447 ddi_fm_service_impact(bgep->devinfo, 5448 DDI_SERVICE_RESTORED); 5449 } 5450 } 5451 } 5452 break; 5453 } 5454 5455 /* 5456 * If an error is detected, stop the chip now, marking it as 5457 * faulty, so that it will be reset next time through ... 5458 * 5459 * Note that if intr_running is set, then bge_intr() has dropped 5460 * genlock to call bge_receive/bge_recycle. Can't stop the chip at 5461 * this point so have to wait until the next time the factotum runs. 5462 */ 5463 if (error && !bgep->bge_intr_running) { 5464 #ifdef BGE_IPMI_ASF 5465 if (bgep->asf_enabled && (bgep->asf_status == ASF_STAT_RUN)) { 5466 /* 5467 * We must stop ASF heart beat before bge_chip_stop(), 5468 * otherwise some computers (ex. IBM HS20 blade server) 5469 * may crash. 5470 */ 5471 bge_asf_update_status(bgep); 5472 bge_asf_stop_timer(bgep); 5473 bgep->asf_status = ASF_STAT_STOP; 5474 5475 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 5476 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 5477 } 5478 #endif 5479 bge_chip_stop(bgep, B_TRUE); 5480 (void) bge_check_acc_handle(bgep, bgep->io_handle); 5481 } 5482 mutex_exit(bgep->genlock); 5483 5484 return (result); 5485 } 5486 5487 /* 5488 * High-level cyclic handler 5489 * 5490 * This routine schedules a (low-level) softint callback to the 5491 * factotum, and prods the chip to update the status block (which 5492 * will cause a hardware interrupt when complete). 5493 */ 5494 void bge_chip_cyclic(void *arg); 5495 #pragma no_inline(bge_chip_cyclic) 5496 5497 void 5498 bge_chip_cyclic(void *arg) 5499 { 5500 bge_t *bgep; 5501 uint32_t regval; 5502 5503 bgep = arg; 5504 5505 switch (bgep->bge_chip_state) { 5506 default: 5507 return; 5508 5509 case BGE_CHIP_RUNNING: 5510 5511 /* XXX I really don't like this forced interrupt... */ 5512 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, COALESCE_NOW); 5513 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5514 ddi_fm_service_impact(bgep->devinfo, 5515 DDI_SERVICE_UNAFFECTED); 5516 5517 break; 5518 5519 case BGE_CHIP_FAULT: 5520 case BGE_CHIP_ERROR: 5521 5522 break; 5523 } 5524 5525 mutex_enter(bgep->genlock); 5526 5527 if (bgep->eee_lpi_wait && !--bgep->eee_lpi_wait) { 5528 BGE_DEBUG(("eee cyclic, lpi enabled")); 5529 bge_eee_enable(bgep); 5530 } 5531 5532 if (bgep->rdma_length_bug_on_5719) { 5533 if ((bge_reg_get32(bgep, STAT_IFHCOUT_UPKGS_REG) + 5534 bge_reg_get32(bgep, STAT_IFHCOUT_MPKGS_REG) + 5535 bge_reg_get32(bgep, STAT_IFHCOUT_BPKGS_REG)) > 5536 BGE_NUM_RDMA_CHANNELS) { 5537 regval = bge_reg_get32(bgep, RDMA_CORR_CTRL_REG); 5538 regval &= ~RDMA_CORR_CTRL_TX_LENGTH_WA; 5539 bge_reg_put32(bgep, RDMA_CORR_CTRL_REG, regval); 5540 bgep->rdma_length_bug_on_5719 = B_FALSE; 5541 } 5542 } 5543 5544 mutex_exit(bgep->genlock); 5545 5546 bge_wake_factotum(bgep); 5547 5548 } 5549 5550 5551 /* 5552 * ========== Ioctl subfunctions ========== 5553 */ 5554 5555 #undef BGE_DBG 5556 #define BGE_DBG BGE_DBG_PPIO /* debug flag for this code */ 5557 5558 #if BGE_DEBUGGING || BGE_DO_PPIO 5559 5560 static void bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 5561 #pragma no_inline(bge_chip_peek_cfg) 5562 5563 static void 5564 bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 5565 { 5566 uint64_t regval; 5567 uint64_t regno; 5568 5569 BGE_TRACE(("bge_chip_peek_cfg($%p, $%p)", 5570 (void *)bgep, (void *)ppd)); 5571 5572 regno = ppd->pp_acc_offset; 5573 5574 switch (ppd->pp_acc_size) { 5575 case 1: 5576 regval = pci_config_get8(bgep->cfg_handle, regno); 5577 break; 5578 5579 case 2: 5580 regval = pci_config_get16(bgep->cfg_handle, regno); 5581 break; 5582 5583 case 4: 5584 regval = pci_config_get32(bgep->cfg_handle, regno); 5585 break; 5586 5587 case 8: 5588 regval = pci_config_get64(bgep->cfg_handle, regno); 5589 break; 5590 } 5591 5592 ppd->pp_acc_data = regval; 5593 } 5594 5595 static void bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 5596 #pragma no_inline(bge_chip_poke_cfg) 5597 5598 static void 5599 bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 5600 { 5601 uint64_t regval; 5602 uint64_t regno; 5603 5604 BGE_TRACE(("bge_chip_poke_cfg($%p, $%p)", 5605 (void *)bgep, (void *)ppd)); 5606 5607 regno = ppd->pp_acc_offset; 5608 regval = ppd->pp_acc_data; 5609 5610 switch (ppd->pp_acc_size) { 5611 case 1: 5612 pci_config_put8(bgep->cfg_handle, regno, regval); 5613 break; 5614 5615 case 2: 5616 pci_config_put16(bgep->cfg_handle, regno, regval); 5617 break; 5618 5619 case 4: 5620 pci_config_put32(bgep->cfg_handle, regno, regval); 5621 break; 5622 5623 case 8: 5624 pci_config_put64(bgep->cfg_handle, regno, regval); 5625 break; 5626 } 5627 } 5628 5629 static void bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd); 5630 #pragma no_inline(bge_chip_peek_reg) 5631 5632 static void 5633 bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd) 5634 { 5635 uint64_t regval; 5636 void *regaddr; 5637 5638 BGE_TRACE(("bge_chip_peek_reg($%p, $%p)", 5639 (void *)bgep, (void *)ppd)); 5640 5641 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 5642 5643 switch (ppd->pp_acc_size) { 5644 case 1: 5645 regval = ddi_get8(bgep->io_handle, regaddr); 5646 break; 5647 5648 case 2: 5649 regval = ddi_get16(bgep->io_handle, regaddr); 5650 break; 5651 5652 case 4: 5653 regval = ddi_get32(bgep->io_handle, regaddr); 5654 break; 5655 5656 case 8: 5657 regval = ddi_get64(bgep->io_handle, regaddr); 5658 break; 5659 } 5660 5661 ppd->pp_acc_data = regval; 5662 } 5663 5664 static void bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd); 5665 #pragma no_inline(bge_chip_peek_reg) 5666 5667 static void 5668 bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd) 5669 { 5670 uint64_t regval; 5671 void *regaddr; 5672 5673 BGE_TRACE(("bge_chip_poke_reg($%p, $%p)", 5674 (void *)bgep, (void *)ppd)); 5675 5676 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 5677 regval = ppd->pp_acc_data; 5678 5679 switch (ppd->pp_acc_size) { 5680 case 1: 5681 ddi_put8(bgep->io_handle, regaddr, regval); 5682 break; 5683 5684 case 2: 5685 ddi_put16(bgep->io_handle, regaddr, regval); 5686 break; 5687 5688 case 4: 5689 ddi_put32(bgep->io_handle, regaddr, regval); 5690 break; 5691 5692 case 8: 5693 ddi_put64(bgep->io_handle, regaddr, regval); 5694 break; 5695 } 5696 BGE_PCICHK(bgep); 5697 } 5698 5699 static void bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd); 5700 #pragma no_inline(bge_chip_peek_nic) 5701 5702 static void 5703 bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd) 5704 { 5705 uint64_t regoff; 5706 uint64_t regval; 5707 void *regaddr; 5708 5709 BGE_TRACE(("bge_chip_peek_nic($%p, $%p)", 5710 (void *)bgep, (void *)ppd)); 5711 5712 regoff = ppd->pp_acc_offset; 5713 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 5714 regoff &= MWBAR_GRANULE_MASK; 5715 regoff += NIC_MEM_WINDOW_OFFSET; 5716 regaddr = PIO_ADDR(bgep, regoff); 5717 5718 switch (ppd->pp_acc_size) { 5719 case 1: 5720 regval = ddi_get8(bgep->io_handle, regaddr); 5721 break; 5722 5723 case 2: 5724 regval = ddi_get16(bgep->io_handle, regaddr); 5725 break; 5726 5727 case 4: 5728 regval = ddi_get32(bgep->io_handle, regaddr); 5729 break; 5730 5731 case 8: 5732 regval = ddi_get64(bgep->io_handle, regaddr); 5733 break; 5734 } 5735 5736 ppd->pp_acc_data = regval; 5737 } 5738 5739 static void bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd); 5740 #pragma no_inline(bge_chip_poke_nic) 5741 5742 static void 5743 bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd) 5744 { 5745 uint64_t regoff; 5746 uint64_t regval; 5747 void *regaddr; 5748 5749 BGE_TRACE(("bge_chip_poke_nic($%p, $%p)", 5750 (void *)bgep, (void *)ppd)); 5751 5752 regoff = ppd->pp_acc_offset; 5753 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 5754 regoff &= MWBAR_GRANULE_MASK; 5755 regoff += NIC_MEM_WINDOW_OFFSET; 5756 regaddr = PIO_ADDR(bgep, regoff); 5757 regval = ppd->pp_acc_data; 5758 5759 switch (ppd->pp_acc_size) { 5760 case 1: 5761 ddi_put8(bgep->io_handle, regaddr, regval); 5762 break; 5763 5764 case 2: 5765 ddi_put16(bgep->io_handle, regaddr, regval); 5766 break; 5767 5768 case 4: 5769 ddi_put32(bgep->io_handle, regaddr, regval); 5770 break; 5771 5772 case 8: 5773 ddi_put64(bgep->io_handle, regaddr, regval); 5774 break; 5775 } 5776 BGE_PCICHK(bgep); 5777 } 5778 5779 static void bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd); 5780 #pragma no_inline(bge_chip_peek_mii) 5781 5782 static void 5783 bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd) 5784 { 5785 BGE_TRACE(("bge_chip_peek_mii($%p, $%p)", 5786 (void *)bgep, (void *)ppd)); 5787 5788 ppd->pp_acc_data = bge_mii_get16(bgep, ppd->pp_acc_offset/2); 5789 } 5790 5791 static void bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd); 5792 #pragma no_inline(bge_chip_poke_mii) 5793 5794 static void 5795 bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd) 5796 { 5797 BGE_TRACE(("bge_chip_poke_mii($%p, $%p)", 5798 (void *)bgep, (void *)ppd)); 5799 5800 bge_mii_put16(bgep, ppd->pp_acc_offset/2, ppd->pp_acc_data); 5801 } 5802 5803 #if BGE_SEE_IO32 5804 5805 static void bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 5806 #pragma no_inline(bge_chip_peek_seeprom) 5807 5808 static void 5809 bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 5810 { 5811 uint32_t data; 5812 int err; 5813 5814 BGE_TRACE(("bge_chip_peek_seeprom($%p, $%p)", 5815 (void *)bgep, (void *)ppd)); 5816 5817 err = bge_nvmem_rw32(bgep, BGE_SEE_READ, ppd->pp_acc_offset, &data); 5818 ppd->pp_acc_data = err ? ~0ull : data; 5819 } 5820 5821 static void bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 5822 #pragma no_inline(bge_chip_poke_seeprom) 5823 5824 static void 5825 bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 5826 { 5827 uint32_t data; 5828 5829 BGE_TRACE(("bge_chip_poke_seeprom($%p, $%p)", 5830 (void *)bgep, (void *)ppd)); 5831 5832 data = ppd->pp_acc_data; 5833 (void) bge_nvmem_rw32(bgep, BGE_SEE_WRITE, ppd->pp_acc_offset, &data); 5834 } 5835 #endif /* BGE_SEE_IO32 */ 5836 5837 #if BGE_FLASH_IO32 5838 5839 static void bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd); 5840 #pragma no_inline(bge_chip_peek_flash) 5841 5842 static void 5843 bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd) 5844 { 5845 uint32_t data; 5846 int err; 5847 5848 BGE_TRACE(("bge_chip_peek_flash($%p, $%p)", 5849 (void *)bgep, (void *)ppd)); 5850 5851 err = bge_nvmem_rw32(bgep, BGE_FLASH_READ, ppd->pp_acc_offset, &data); 5852 ppd->pp_acc_data = err ? ~0ull : data; 5853 } 5854 5855 static void bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd); 5856 #pragma no_inline(bge_chip_poke_flash) 5857 5858 static void 5859 bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd) 5860 { 5861 uint32_t data; 5862 5863 BGE_TRACE(("bge_chip_poke_flash($%p, $%p)", 5864 (void *)bgep, (void *)ppd)); 5865 5866 data = ppd->pp_acc_data; 5867 (void) bge_nvmem_rw32(bgep, BGE_FLASH_WRITE, 5868 ppd->pp_acc_offset, &data); 5869 } 5870 #endif /* BGE_FLASH_IO32 */ 5871 5872 static void bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd); 5873 #pragma no_inline(bge_chip_peek_mem) 5874 5875 static void 5876 bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd) 5877 { 5878 uint64_t regval; 5879 void *vaddr; 5880 5881 BGE_TRACE(("bge_chip_peek_bge($%p, $%p)", 5882 (void *)bgep, (void *)ppd)); 5883 5884 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 5885 5886 switch (ppd->pp_acc_size) { 5887 case 1: 5888 regval = *(uint8_t *)vaddr; 5889 break; 5890 5891 case 2: 5892 regval = *(uint16_t *)vaddr; 5893 break; 5894 5895 case 4: 5896 regval = *(uint32_t *)vaddr; 5897 break; 5898 5899 case 8: 5900 regval = *(uint64_t *)vaddr; 5901 break; 5902 } 5903 5904 BGE_DEBUG(("bge_chip_peek_mem($%p, $%p) peeked 0x%llx from $%p", 5905 (void *)bgep, (void *)ppd, regval, vaddr)); 5906 5907 ppd->pp_acc_data = regval; 5908 } 5909 5910 static void bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd); 5911 #pragma no_inline(bge_chip_poke_mem) 5912 5913 static void 5914 bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd) 5915 { 5916 uint64_t regval; 5917 void *vaddr; 5918 5919 BGE_TRACE(("bge_chip_poke_mem($%p, $%p)", 5920 (void *)bgep, (void *)ppd)); 5921 5922 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 5923 regval = ppd->pp_acc_data; 5924 5925 BGE_DEBUG(("bge_chip_poke_mem($%p, $%p) poking 0x%llx at $%p", 5926 (void *)bgep, (void *)ppd, regval, vaddr)); 5927 5928 switch (ppd->pp_acc_size) { 5929 case 1: 5930 *(uint8_t *)vaddr = (uint8_t)regval; 5931 break; 5932 5933 case 2: 5934 *(uint16_t *)vaddr = (uint16_t)regval; 5935 break; 5936 5937 case 4: 5938 *(uint32_t *)vaddr = (uint32_t)regval; 5939 break; 5940 5941 case 8: 5942 *(uint64_t *)vaddr = (uint64_t)regval; 5943 break; 5944 } 5945 } 5946 5947 static enum ioc_reply bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5948 struct iocblk *iocp); 5949 #pragma no_inline(bge_pp_ioctl) 5950 5951 static enum ioc_reply 5952 bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5953 { 5954 void (*ppfn)(bge_t *bgep, bge_peekpoke_t *ppd); 5955 bge_peekpoke_t *ppd; 5956 dma_area_t *areap; 5957 uint64_t sizemask; 5958 uint64_t mem_va; 5959 uint64_t maxoff; 5960 boolean_t peek; 5961 5962 switch (cmd) { 5963 default: 5964 /* NOTREACHED */ 5965 bge_error(bgep, "bge_pp_ioctl: invalid cmd 0x%x", cmd); 5966 return (IOC_INVAL); 5967 5968 case BGE_PEEK: 5969 peek = B_TRUE; 5970 break; 5971 5972 case BGE_POKE: 5973 peek = B_FALSE; 5974 break; 5975 } 5976 5977 /* 5978 * Validate format of ioctl 5979 */ 5980 if (iocp->ioc_count != sizeof (bge_peekpoke_t)) 5981 return (IOC_INVAL); 5982 if (mp->b_cont == NULL) 5983 return (IOC_INVAL); 5984 ppd = (void *)mp->b_cont->b_rptr; 5985 5986 /* 5987 * Validate request parameters 5988 */ 5989 switch (ppd->pp_acc_space) { 5990 default: 5991 return (IOC_INVAL); 5992 5993 case BGE_PP_SPACE_CFG: 5994 /* 5995 * Config space 5996 */ 5997 sizemask = 8|4|2|1; 5998 mem_va = 0; 5999 maxoff = PCI_CONF_HDR_SIZE; 6000 ppfn = peek ? bge_chip_peek_cfg : bge_chip_poke_cfg; 6001 break; 6002 6003 case BGE_PP_SPACE_REG: 6004 /* 6005 * Memory-mapped I/O space 6006 */ 6007 sizemask = 8|4|2|1; 6008 mem_va = 0; 6009 maxoff = RIAAR_REGISTER_MAX; 6010 ppfn = peek ? bge_chip_peek_reg : bge_chip_poke_reg; 6011 break; 6012 6013 case BGE_PP_SPACE_NIC: 6014 /* 6015 * NIC on-chip memory 6016 */ 6017 sizemask = 8|4|2|1; 6018 mem_va = 0; 6019 maxoff = MWBAR_ONCHIP_MAX; 6020 ppfn = peek ? bge_chip_peek_nic : bge_chip_poke_nic; 6021 break; 6022 6023 case BGE_PP_SPACE_MII: 6024 /* 6025 * PHY's MII registers 6026 * NB: all PHY registers are two bytes, but the 6027 * addresses increment in ones (word addressing). 6028 * So we scale the address here, then undo the 6029 * transformation inside the peek/poke functions. 6030 */ 6031 ppd->pp_acc_offset *= 2; 6032 sizemask = 2; 6033 mem_va = 0; 6034 maxoff = (MII_MAXREG+1)*2; 6035 ppfn = peek ? bge_chip_peek_mii : bge_chip_poke_mii; 6036 break; 6037 6038 #if BGE_SEE_IO32 6039 case BGE_PP_SPACE_SEEPROM: 6040 /* 6041 * Attached SEEPROM(s), if any. 6042 * NB: we use the high-order bits of the 'address' as 6043 * a device select to accommodate multiple SEEPROMS, 6044 * If each one is the maximum size (64kbytes), this 6045 * makes them appear contiguous. Otherwise, there may 6046 * be holes in the mapping. ENxS doesn't have any 6047 * SEEPROMs anyway ... 6048 */ 6049 sizemask = 4; 6050 mem_va = 0; 6051 maxoff = SEEPROM_DEV_AND_ADDR_MASK; 6052 ppfn = peek ? bge_chip_peek_seeprom : bge_chip_poke_seeprom; 6053 break; 6054 #endif /* BGE_SEE_IO32 */ 6055 6056 #if BGE_FLASH_IO32 6057 case BGE_PP_SPACE_FLASH: 6058 /* 6059 * Attached Flash device (if any); a maximum of one device 6060 * is currently supported. But it can be up to 1MB (unlike 6061 * the 64k limit on SEEPROMs) so why would you need more ;-) 6062 */ 6063 sizemask = 4; 6064 mem_va = 0; 6065 maxoff = NVM_FLASH_ADDR_MASK; 6066 ppfn = peek ? bge_chip_peek_flash : bge_chip_poke_flash; 6067 break; 6068 #endif /* BGE_FLASH_IO32 */ 6069 6070 case BGE_PP_SPACE_BGE: 6071 /* 6072 * BGE data structure! 6073 */ 6074 sizemask = 8|4|2|1; 6075 mem_va = (uintptr_t)bgep; 6076 maxoff = sizeof (*bgep); 6077 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 6078 break; 6079 6080 case BGE_PP_SPACE_STATUS: 6081 case BGE_PP_SPACE_STATISTICS: 6082 case BGE_PP_SPACE_TXDESC: 6083 case BGE_PP_SPACE_TXBUFF: 6084 case BGE_PP_SPACE_RXDESC: 6085 case BGE_PP_SPACE_RXBUFF: 6086 /* 6087 * Various DMA_AREAs 6088 */ 6089 switch (ppd->pp_acc_space) { 6090 case BGE_PP_SPACE_TXDESC: 6091 areap = &bgep->tx_desc; 6092 break; 6093 case BGE_PP_SPACE_TXBUFF: 6094 areap = &bgep->tx_buff[0]; 6095 break; 6096 case BGE_PP_SPACE_RXDESC: 6097 areap = &bgep->rx_desc[0]; 6098 break; 6099 case BGE_PP_SPACE_RXBUFF: 6100 areap = &bgep->rx_buff[0]; 6101 break; 6102 case BGE_PP_SPACE_STATUS: 6103 areap = &bgep->status_block; 6104 break; 6105 case BGE_PP_SPACE_STATISTICS: 6106 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 6107 areap = &bgep->statistics; 6108 break; 6109 } 6110 6111 sizemask = 8|4|2|1; 6112 mem_va = (uintptr_t)areap->mem_va; 6113 maxoff = areap->alength; 6114 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 6115 break; 6116 } 6117 6118 switch (ppd->pp_acc_size) { 6119 default: 6120 return (IOC_INVAL); 6121 6122 case 8: 6123 case 4: 6124 case 2: 6125 case 1: 6126 if ((ppd->pp_acc_size & sizemask) == 0) 6127 return (IOC_INVAL); 6128 break; 6129 } 6130 6131 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 6132 return (IOC_INVAL); 6133 6134 if (ppd->pp_acc_offset >= maxoff) 6135 return (IOC_INVAL); 6136 6137 if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff) 6138 return (IOC_INVAL); 6139 6140 /* 6141 * All OK - go do it! 6142 */ 6143 ppd->pp_acc_offset += mem_va; 6144 (*ppfn)(bgep, ppd); 6145 return (peek ? IOC_REPLY : IOC_ACK); 6146 } 6147 6148 static enum ioc_reply bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 6149 struct iocblk *iocp); 6150 #pragma no_inline(bge_diag_ioctl) 6151 6152 static enum ioc_reply 6153 bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 6154 { 6155 ASSERT(mutex_owned(bgep->genlock)); 6156 6157 switch (cmd) { 6158 default: 6159 /* NOTREACHED */ 6160 bge_error(bgep, "bge_diag_ioctl: invalid cmd 0x%x", cmd); 6161 return (IOC_INVAL); 6162 6163 case BGE_DIAG: 6164 /* 6165 * Currently a no-op 6166 */ 6167 return (IOC_ACK); 6168 6169 case BGE_PEEK: 6170 case BGE_POKE: 6171 return (bge_pp_ioctl(bgep, cmd, mp, iocp)); 6172 6173 case BGE_PHY_RESET: 6174 return (IOC_RESTART_ACK); 6175 6176 case BGE_SOFT_RESET: 6177 case BGE_HARD_RESET: 6178 /* 6179 * Reset and reinitialise the 570x hardware 6180 */ 6181 bgep->bge_chip_state = BGE_CHIP_FAULT; 6182 ddi_trigger_softintr(bgep->factotum_id); 6183 (void) bge_restart(bgep, cmd == BGE_HARD_RESET); 6184 return (IOC_ACK); 6185 } 6186 6187 /* NOTREACHED */ 6188 } 6189 6190 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 6191 6192 static enum ioc_reply bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 6193 struct iocblk *iocp); 6194 #pragma no_inline(bge_mii_ioctl) 6195 6196 static enum ioc_reply 6197 bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 6198 { 6199 struct bge_mii_rw *miirwp; 6200 6201 /* 6202 * Validate format of ioctl 6203 */ 6204 if (iocp->ioc_count != sizeof (struct bge_mii_rw)) 6205 return (IOC_INVAL); 6206 if (mp->b_cont == NULL) 6207 return (IOC_INVAL); 6208 miirwp = (void *)mp->b_cont->b_rptr; 6209 6210 /* 6211 * Validate request parameters ... 6212 */ 6213 if (miirwp->mii_reg > MII_MAXREG) 6214 return (IOC_INVAL); 6215 6216 switch (cmd) { 6217 default: 6218 /* NOTREACHED */ 6219 bge_error(bgep, "bge_mii_ioctl: invalid cmd 0x%x", cmd); 6220 return (IOC_INVAL); 6221 6222 case BGE_MII_READ: 6223 miirwp->mii_data = bge_mii_get16(bgep, miirwp->mii_reg); 6224 return (IOC_REPLY); 6225 6226 case BGE_MII_WRITE: 6227 bge_mii_put16(bgep, miirwp->mii_reg, miirwp->mii_data); 6228 return (IOC_ACK); 6229 } 6230 6231 /* NOTREACHED */ 6232 } 6233 6234 #if BGE_SEE_IO32 6235 6236 static enum ioc_reply bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 6237 struct iocblk *iocp); 6238 #pragma no_inline(bge_see_ioctl) 6239 6240 static enum ioc_reply 6241 bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 6242 { 6243 struct bge_see_rw *seerwp; 6244 6245 /* 6246 * Validate format of ioctl 6247 */ 6248 if (iocp->ioc_count != sizeof (struct bge_see_rw)) 6249 return (IOC_INVAL); 6250 if (mp->b_cont == NULL) 6251 return (IOC_INVAL); 6252 seerwp = (void *)mp->b_cont->b_rptr; 6253 6254 /* 6255 * Validate request parameters ... 6256 */ 6257 if (seerwp->see_addr & ~SEEPROM_DEV_AND_ADDR_MASK) 6258 return (IOC_INVAL); 6259 6260 switch (cmd) { 6261 default: 6262 /* NOTREACHED */ 6263 bge_error(bgep, "bge_see_ioctl: invalid cmd 0x%x", cmd); 6264 return (IOC_INVAL); 6265 6266 case BGE_SEE_READ: 6267 case BGE_SEE_WRITE: 6268 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 6269 seerwp->see_addr, &seerwp->see_data); 6270 return (IOC_REPLY); 6271 } 6272 6273 /* NOTREACHED */ 6274 } 6275 6276 #endif /* BGE_SEE_IO32 */ 6277 6278 #if BGE_FLASH_IO32 6279 6280 static enum ioc_reply bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 6281 struct iocblk *iocp); 6282 #pragma no_inline(bge_flash_ioctl) 6283 6284 static enum ioc_reply 6285 bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 6286 { 6287 struct bge_flash_rw *flashrwp; 6288 6289 /* 6290 * Validate format of ioctl 6291 */ 6292 if (iocp->ioc_count != sizeof (struct bge_flash_rw)) 6293 return (IOC_INVAL); 6294 if (mp->b_cont == NULL) 6295 return (IOC_INVAL); 6296 flashrwp = (void *)mp->b_cont->b_rptr; 6297 6298 /* 6299 * Validate request parameters ... 6300 */ 6301 if (flashrwp->flash_addr & ~NVM_FLASH_ADDR_MASK) 6302 return (IOC_INVAL); 6303 6304 switch (cmd) { 6305 default: 6306 /* NOTREACHED */ 6307 bge_error(bgep, "bge_flash_ioctl: invalid cmd 0x%x", cmd); 6308 return (IOC_INVAL); 6309 6310 case BGE_FLASH_READ: 6311 case BGE_FLASH_WRITE: 6312 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 6313 flashrwp->flash_addr, &flashrwp->flash_data); 6314 return (IOC_REPLY); 6315 } 6316 6317 /* NOTREACHED */ 6318 } 6319 6320 #endif /* BGE_FLASH_IO32 */ 6321 6322 enum ioc_reply bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, 6323 struct iocblk *iocp); 6324 #pragma no_inline(bge_chip_ioctl) 6325 6326 enum ioc_reply 6327 bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 6328 { 6329 int cmd; 6330 6331 BGE_TRACE(("bge_chip_ioctl($%p, $%p, $%p, $%p)", 6332 (void *)bgep, (void *)wq, (void *)mp, (void *)iocp)); 6333 6334 ASSERT(mutex_owned(bgep->genlock)); 6335 6336 cmd = iocp->ioc_cmd; 6337 switch (cmd) { 6338 default: 6339 /* NOTREACHED */ 6340 bge_error(bgep, "bge_chip_ioctl: invalid cmd 0x%x", cmd); 6341 return (IOC_INVAL); 6342 6343 case BGE_DIAG: 6344 case BGE_PEEK: 6345 case BGE_POKE: 6346 case BGE_PHY_RESET: 6347 case BGE_SOFT_RESET: 6348 case BGE_HARD_RESET: 6349 #if BGE_DEBUGGING || BGE_DO_PPIO 6350 return (bge_diag_ioctl(bgep, cmd, mp, iocp)); 6351 #else 6352 return (IOC_INVAL); 6353 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 6354 6355 case BGE_MII_READ: 6356 case BGE_MII_WRITE: 6357 return (bge_mii_ioctl(bgep, cmd, mp, iocp)); 6358 6359 #if BGE_SEE_IO32 6360 case BGE_SEE_READ: 6361 case BGE_SEE_WRITE: 6362 return (bge_see_ioctl(bgep, cmd, mp, iocp)); 6363 #endif /* BGE_SEE_IO32 */ 6364 6365 #if BGE_FLASH_IO32 6366 case BGE_FLASH_READ: 6367 case BGE_FLASH_WRITE: 6368 return (bge_flash_ioctl(bgep, cmd, mp, iocp)); 6369 #endif /* BGE_FLASH_IO32 */ 6370 } 6371 6372 /* NOTREACHED */ 6373 } 6374 6375 /* ARGSUSED */ 6376 void 6377 bge_chip_blank(void *arg, time_t ticks, uint_t count, int flag) 6378 { 6379 recv_ring_t *rrp = arg; 6380 bge_t *bgep = rrp->bgep; 6381 6382 mutex_enter(bgep->genlock); 6383 rrp->poll_flag = flag; 6384 #ifdef NOT_YET 6385 /* 6386 * XXX-Sunay: Since most broadcom cards support only one 6387 * interrupt but multiple rx rings, we can't disable the 6388 * physical interrupt. This need to be done via capability 6389 * negotiation depending on the NIC. 6390 */ 6391 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, ticks); 6392 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, count); 6393 #endif 6394 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 6395 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 6396 mutex_exit(bgep->genlock); 6397 } 6398 6399 #ifdef BGE_IPMI_ASF 6400 6401 uint32_t 6402 bge_nic_read32(bge_t *bgep, bge_regno_t addr) 6403 { 6404 uint32_t data; 6405 6406 #ifndef __sparc 6407 if (!bgep->asf_wordswapped) { 6408 /* a workaround word swap error */ 6409 if (addr & 4) 6410 addr = addr - 4; 6411 else 6412 addr = addr + 4; 6413 } 6414 #else 6415 if (DEVICE_5717_SERIES_CHIPSETS(bgep) || 6416 DEVICE_5725_SERIES_CHIPSETS(bgep)) { 6417 addr = LE_32(addr); 6418 } 6419 #endif 6420 6421 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr); 6422 data = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR); 6423 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0); 6424 6425 data = LE_32(data); 6426 6427 BGE_DEBUG(("bge_nic_read32($%p, 0x%x) => 0x%x", 6428 (void *)bgep, addr, data)); 6429 6430 return (data); 6431 } 6432 6433 void 6434 bge_asf_update_status(bge_t *bgep) 6435 { 6436 uint32_t event; 6437 6438 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_ALIVE); 6439 bge_nic_put32(bgep, BGE_CMD_LENGTH_MAILBOX, 4); 6440 bge_nic_put32(bgep, BGE_CMD_DATA_MAILBOX, 3); 6441 6442 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 6443 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 6444 } 6445 6446 6447 /* 6448 * The driver is supposed to notify ASF that the OS is still running 6449 * every three seconds, otherwise the management server may attempt 6450 * to reboot the machine. If it hasn't actually failed, this is 6451 * not a desirable result. However, this isn't running as a real-time 6452 * thread, and even if it were, it might not be able to generate the 6453 * heartbeat in a timely manner due to system load. As it isn't a 6454 * significant strain on the machine, we will set the interval to half 6455 * of the required value. 6456 */ 6457 void 6458 bge_asf_heartbeat(void *arg) 6459 { 6460 bge_t *bgep = (bge_t *)arg; 6461 6462 mutex_enter(bgep->genlock); 6463 bge_asf_update_status((bge_t *)bgep); 6464 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 6465 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 6466 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) 6467 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 6468 mutex_exit(bgep->genlock); 6469 ((bge_t *)bgep)->asf_timeout_id = timeout(bge_asf_heartbeat, bgep, 6470 drv_usectohz(BGE_ASF_HEARTBEAT_INTERVAL)); 6471 } 6472 6473 6474 void 6475 bge_asf_stop_timer(bge_t *bgep) 6476 { 6477 timeout_id_t tmp_id = 0; 6478 6479 while ((bgep->asf_timeout_id != 0) && 6480 (tmp_id != bgep->asf_timeout_id)) { 6481 tmp_id = bgep->asf_timeout_id; 6482 (void) untimeout(tmp_id); 6483 } 6484 bgep->asf_timeout_id = 0; 6485 } 6486 6487 6488 6489 /* 6490 * This function should be placed at the earliest position of bge_attach(). 6491 */ 6492 void 6493 bge_asf_get_config(bge_t *bgep) 6494 { 6495 uint32_t nicsig; 6496 uint32_t niccfg; 6497 6498 bgep->asf_enabled = B_FALSE; 6499 6500 /* No ASF if APE present. */ 6501 if (bgep->ape_enabled) 6502 return; 6503 6504 nicsig = bge_nic_read32(bgep, BGE_NIC_DATA_SIG_ADDR); 6505 if (nicsig == BGE_NIC_DATA_SIG) { 6506 niccfg = bge_nic_read32(bgep, BGE_NIC_DATA_NIC_CFG_ADDR); 6507 if (niccfg & BGE_NIC_CFG_ENABLE_ASF) 6508 /* 6509 * Here, we don't consider BAXTER, because BGE haven't 6510 * supported BAXTER (that is 5752). Also, as I know, 6511 * BAXTER doesn't support ASF feature. 6512 */ 6513 bgep->asf_enabled = B_TRUE; 6514 else 6515 bgep->asf_enabled = B_FALSE; 6516 } else 6517 bgep->asf_enabled = B_FALSE; 6518 } 6519 6520 6521 void 6522 bge_asf_pre_reset_operations(bge_t *bgep, uint32_t mode) 6523 { 6524 uint32_t tries; 6525 uint32_t event; 6526 6527 ASSERT(bgep->asf_enabled); 6528 6529 /* Issues "pause firmware" command and wait for ACK */ 6530 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_PAUSE_FW); 6531 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 6532 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 6533 6534 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 6535 tries = 0; 6536 while ((event & RRER_ASF_EVENT) && (tries < 100)) { 6537 drv_usecwait(1); 6538 tries ++; 6539 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 6540 } 6541 6542 bge_nic_put32(bgep, BGE_FIRMWARE_MAILBOX, 6543 BGE_MAGIC_NUM_FIRMWARE_INIT_DONE); 6544 6545 if (bgep->asf_newhandshake) { 6546 switch (mode) { 6547 case BGE_INIT_RESET: 6548 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 6549 BGE_DRV_STATE_START); 6550 break; 6551 case BGE_SHUTDOWN_RESET: 6552 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 6553 BGE_DRV_STATE_UNLOAD); 6554 break; 6555 case BGE_SUSPEND_RESET: 6556 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 6557 BGE_DRV_STATE_SUSPEND); 6558 break; 6559 default: 6560 break; 6561 } 6562 } 6563 6564 if (mode == BGE_INIT_RESET || 6565 mode == BGE_SUSPEND_RESET) 6566 bge_ape_driver_state_change(bgep, mode); 6567 } 6568 6569 6570 void 6571 bge_asf_post_reset_old_mode(bge_t *bgep, uint32_t mode) 6572 { 6573 switch (mode) { 6574 case BGE_INIT_RESET: 6575 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 6576 BGE_DRV_STATE_START); 6577 break; 6578 case BGE_SHUTDOWN_RESET: 6579 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 6580 BGE_DRV_STATE_UNLOAD); 6581 break; 6582 case BGE_SUSPEND_RESET: 6583 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 6584 BGE_DRV_STATE_SUSPEND); 6585 break; 6586 default: 6587 break; 6588 } 6589 } 6590 6591 6592 void 6593 bge_asf_post_reset_new_mode(bge_t *bgep, uint32_t mode) 6594 { 6595 switch (mode) { 6596 case BGE_INIT_RESET: 6597 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 6598 BGE_DRV_STATE_START_DONE); 6599 break; 6600 case BGE_SHUTDOWN_RESET: 6601 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 6602 BGE_DRV_STATE_UNLOAD_DONE); 6603 break; 6604 default: 6605 break; 6606 } 6607 6608 if (mode == BGE_SHUTDOWN_RESET) 6609 bge_ape_driver_state_change(bgep, mode); 6610 } 6611 6612 #endif /* BGE_IPMI_ASF */ 6613