1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #include "bge_impl.h" 28 29 #define PIO_ADDR(bgep, offset) ((void *)((caddr_t)(bgep)->io_regs+(offset))) 30 31 /* 32 * Future features ... ? 33 */ 34 #define BGE_CFG_IO8 1 /* 8/16-bit cfg space BIS/BIC */ 35 #define BGE_IND_IO32 1 /* indirect access code */ 36 #define BGE_SEE_IO32 1 /* SEEPROM access code */ 37 #define BGE_FLASH_IO32 1 /* FLASH access code */ 38 39 /* 40 * BGE MSI tunable: 41 * 42 * By default MSI is enabled on all supported platforms but it is disabled 43 * for some Broadcom chips due to known MSI hardware issues. Currently MSI 44 * is enabled only for 5714C A2 and 5715C A2 broadcom chips. 45 */ 46 boolean_t bge_enable_msi = B_TRUE; 47 48 /* 49 * PCI-X/PCI-E relaxed ordering tunable for OS/Nexus driver 50 */ 51 boolean_t bge_relaxed_ordering = B_TRUE; 52 53 /* 54 * Property names 55 */ 56 static char knownids_propname[] = "bge-known-subsystems"; 57 58 /* 59 * Patchable globals: 60 * 61 * bge_autorecover 62 * Enables/disables automatic recovery after fault detection 63 * 64 * bge_mlcr_default 65 * Value to program into the MLCR; controls the chip's GPIO pins 66 * 67 * bge_dma_{rd,wr}prio 68 * Relative priorities of DMA reads & DMA writes respectively. 69 * These may each be patched to any value 0-3. Equal values 70 * will give "fair" (round-robin) arbitration for PCI access. 71 * Unequal values will give one or the other function priority. 72 * 73 * bge_dma_rwctrl 74 * Value to put in the Read/Write DMA control register. See 75 * the Broadcom PRM for things you can fiddle with in this 76 * register ... 77 * 78 * bge_{tx,rx}_{count,ticks}_{norm,intr} 79 * Send/receive interrupt coalescing parameters. Counts are 80 * #s of descriptors, ticks are in microseconds. *norm* values 81 * apply between status updates/interrupts; the *intr* values 82 * refer to the 'during-interrupt' versions - see the PRM. 83 * 84 * NOTE: these values have been determined by measurement. They 85 * differ significantly from the values recommended in the PRM. 86 */ 87 static uint32_t bge_autorecover = 1; 88 static uint32_t bge_mlcr_default_5714 = MLCR_DEFAULT_5714; 89 90 static uint32_t bge_dma_rdprio = 1; 91 static uint32_t bge_dma_wrprio = 0; 92 static uint32_t bge_dma_rwctrl = PDRWCR_VAR_DEFAULT; 93 static uint32_t bge_dma_rwctrl_5721 = PDRWCR_VAR_5721; 94 static uint32_t bge_dma_rwctrl_5714 = PDRWCR_VAR_5714; 95 static uint32_t bge_dma_rwctrl_5715 = PDRWCR_VAR_5715; 96 97 uint32_t bge_rx_ticks_norm = 128; 98 uint32_t bge_tx_ticks_norm = 2048; /* 8 for FJ2+ !?!? */ 99 uint32_t bge_rx_count_norm = 8; 100 uint32_t bge_tx_count_norm = 128; 101 102 static uint32_t bge_rx_ticks_intr = 128; 103 static uint32_t bge_tx_ticks_intr = 0; /* 8 for FJ2+ !?!? */ 104 static uint32_t bge_rx_count_intr = 2; 105 static uint32_t bge_tx_count_intr = 0; 106 107 /* 108 * Memory pool configuration parameters. 109 * 110 * These are generally specific to each member of the chip family, since 111 * each one may have a different memory size/configuration. 112 * 113 * Setting the mbuf pool length for a specific type of chip to 0 inhibits 114 * the driver from programming the various registers; instead they are left 115 * at their hardware defaults. This is the preferred option for later chips 116 * (5705+), whereas the older chips *required* these registers to be set, 117 * since the h/w default was 0 ;-( 118 */ 119 static uint32_t bge_mbuf_pool_base = MBUF_POOL_BASE_DEFAULT; 120 static uint32_t bge_mbuf_pool_base_5704 = MBUF_POOL_BASE_5704; 121 static uint32_t bge_mbuf_pool_base_5705 = MBUF_POOL_BASE_5705; 122 static uint32_t bge_mbuf_pool_base_5721 = MBUF_POOL_BASE_5721; 123 static uint32_t bge_mbuf_pool_len = MBUF_POOL_LENGTH_DEFAULT; 124 static uint32_t bge_mbuf_pool_len_5704 = MBUF_POOL_LENGTH_5704; 125 static uint32_t bge_mbuf_pool_len_5705 = 0; /* use h/w default */ 126 static uint32_t bge_mbuf_pool_len_5721 = 0; 127 128 /* 129 * Various high and low water marks, thresholds, etc ... 130 * 131 * Note: these are taken from revision 7 of the PRM, and some are different 132 * from both the values in earlier PRMs *and* those determined experimentally 133 * and used in earlier versions of this driver ... 134 */ 135 static uint32_t bge_mbuf_hi_water = MBUF_HIWAT_DEFAULT; 136 static uint32_t bge_mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_DEFAULT; 137 static uint32_t bge_mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_DEFAULT; 138 139 static uint32_t bge_dmad_lo_water = DMAD_POOL_LOWAT_DEFAULT; 140 static uint32_t bge_dmad_hi_water = DMAD_POOL_HIWAT_DEFAULT; 141 static uint32_t bge_lowat_recv_frames = LOWAT_MAX_RECV_FRAMES_DEFAULT; 142 143 static uint32_t bge_replenish_std = STD_RCV_BD_REPLENISH_DEFAULT; 144 static uint32_t bge_replenish_mini = MINI_RCV_BD_REPLENISH_DEFAULT; 145 static uint32_t bge_replenish_jumbo = JUMBO_RCV_BD_REPLENISH_DEFAULT; 146 147 static uint32_t bge_watchdog_count = 1 << 16; 148 static uint16_t bge_dma_miss_limit = 20; 149 150 static uint32_t bge_stop_start_on_sync = 0; 151 152 boolean_t bge_jumbo_enable = B_TRUE; 153 154 /* 155 * bge_intr_max_loop controls the maximum loop number within bge_intr. 156 * When loading NIC with heavy network traffic, it is useful. 157 * Increasing this value could have positive effect to throughput, 158 * but it might also increase ticks of a bge ISR stick on CPU, which might 159 * lead to bad UI interactive experience. So tune this with caution. 160 */ 161 static int bge_intr_max_loop = 1; 162 163 /* 164 * ========== Low-level chip & ring buffer manipulation ========== 165 */ 166 167 #define BGE_DBG BGE_DBG_REGS /* debug flag for this code */ 168 169 170 /* 171 * Config space read-modify-write routines 172 */ 173 174 #if BGE_CFG_IO8 175 176 static void bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits); 177 #pragma inline(bge_cfg_clr16) 178 179 static void 180 bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits) 181 { 182 uint16_t regval; 183 184 BGE_TRACE(("bge_cfg_clr16($%p, 0x%lx, 0x%x)", 185 (void *)bgep, regno, bits)); 186 187 regval = pci_config_get16(bgep->cfg_handle, regno); 188 189 BGE_DEBUG(("bge_cfg_clr16($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 190 (void *)bgep, regno, bits, regval, regval & ~bits)); 191 192 regval &= ~bits; 193 pci_config_put16(bgep->cfg_handle, regno, regval); 194 } 195 196 #endif /* BGE_CFG_IO8 */ 197 198 static void bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 199 #pragma inline(bge_cfg_clr32) 200 201 static void 202 bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 203 { 204 uint32_t regval; 205 206 BGE_TRACE(("bge_cfg_clr32($%p, 0x%lx, 0x%x)", 207 (void *)bgep, regno, bits)); 208 209 regval = pci_config_get32(bgep->cfg_handle, regno); 210 211 BGE_DEBUG(("bge_cfg_clr32($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 212 (void *)bgep, regno, bits, regval, regval & ~bits)); 213 214 regval &= ~bits; 215 pci_config_put32(bgep->cfg_handle, regno, regval); 216 } 217 218 #if BGE_IND_IO32 219 220 /* 221 * Indirect access to registers & RISC scratchpads, using config space 222 * accesses only. 223 * 224 * This isn't currently used, but someday we might want to use it for 225 * restoring the Subsystem Device/Vendor registers (which aren't directly 226 * writable in Config Space), or for downloading firmware into the RISCs 227 * 228 * In any case there are endian issues to be resolved before this code is 229 * enabled; the bizarre way that bytes get twisted by this chip AND by 230 * the PCI bridge in SPARC systems mean that we shouldn't enable it until 231 * it's been thoroughly tested for all access sizes on all supported 232 * architectures (SPARC *and* x86!). 233 */ 234 uint32_t bge_ind_get32(bge_t *bgep, bge_regno_t regno); 235 #pragma inline(bge_ind_get32) 236 237 uint32_t 238 bge_ind_get32(bge_t *bgep, bge_regno_t regno) 239 { 240 uint32_t val; 241 242 BGE_TRACE(("bge_ind_get32($%p, 0x%lx)", (void *)bgep, regno)); 243 244 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 245 val = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_RIADR); 246 247 BGE_DEBUG(("bge_ind_get32($%p, 0x%lx) => 0x%x", 248 (void *)bgep, regno, val)); 249 250 val = LE_32(val); 251 252 return (val); 253 } 254 255 void bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val); 256 #pragma inline(bge_ind_put32) 257 258 void 259 bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val) 260 { 261 BGE_TRACE(("bge_ind_put32($%p, 0x%lx, 0x%x)", 262 (void *)bgep, regno, val)); 263 264 val = LE_32(val); 265 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 266 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIADR, val); 267 } 268 269 #endif /* BGE_IND_IO32 */ 270 271 #if BGE_DEBUGGING 272 273 static void bge_pci_check(bge_t *bgep); 274 #pragma no_inline(bge_pci_check) 275 276 static void 277 bge_pci_check(bge_t *bgep) 278 { 279 uint16_t pcistatus; 280 281 pcistatus = pci_config_get16(bgep->cfg_handle, PCI_CONF_STAT); 282 if ((pcistatus & (PCI_STAT_R_MAST_AB | PCI_STAT_R_TARG_AB)) != 0) 283 BGE_DEBUG(("bge_pci_check($%p): PCI status 0x%x", 284 (void *)bgep, pcistatus)); 285 } 286 287 #endif /* BGE_DEBUGGING */ 288 289 /* 290 * Perform first-stage chip (re-)initialisation, using only config-space 291 * accesses: 292 * 293 * + Read the vendor/device/revision/subsystem/cache-line-size registers, 294 * returning the data in the structure pointed to by <idp>. 295 * + Configure the target-mode endianness (swap) options. 296 * + Disable interrupts and enable Memory Space accesses. 297 * + Enable or disable Bus Mastering according to the <enable_dma> flag. 298 * 299 * This sequence is adapted from Broadcom document 570X-PG102-R, 300 * page 102, steps 1-3, 6-8 and 11-13. The omitted parts of the sequence 301 * are 4 and 5 (Reset Core and wait) which are handled elsewhere. 302 * 303 * This function MUST be called before any non-config-space accesses 304 * are made; on this first call <enable_dma> is B_FALSE, and it 305 * effectively performs steps 3-1(!) of the initialisation sequence 306 * (the rest are not required but should be harmless). 307 * 308 * It MUST also be called after a chip reset, as this disables 309 * Memory Space cycles! In this case, <enable_dma> is B_TRUE, and 310 * it is effectively performing steps 6-8. 311 */ 312 void bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma); 313 #pragma no_inline(bge_chip_cfg_init) 314 315 void 316 bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma) 317 { 318 ddi_acc_handle_t handle; 319 uint16_t command; 320 uint32_t mhcr; 321 uint16_t value16; 322 int i; 323 324 BGE_TRACE(("bge_chip_cfg_init($%p, $%p, %d)", 325 (void *)bgep, (void *)cidp, enable_dma)); 326 327 /* 328 * Step 3: save PCI cache line size and subsystem vendor ID 329 * 330 * Read all the config-space registers that characterise the 331 * chip, specifically vendor/device/revision/subsystem vendor 332 * and subsystem device id. We expect (but don't check) that 333 * (vendor == VENDOR_ID_BROADCOM) && (device == DEVICE_ID_5704) 334 * 335 * Also save all bus-transaction related registers (cache-line 336 * size, bus-grant/latency parameters, etc). Some of these are 337 * cleared by reset, so we'll have to restore them later. This 338 * comes from the Broadcom document 570X-PG102-R ... 339 * 340 * Note: Broadcom document 570X-PG102-R seems to be in error 341 * here w.r.t. the offsets of the Subsystem Vendor ID and 342 * Subsystem (Device) ID registers, which are the opposite way 343 * round according to the PCI standard. For good measure, we 344 * save/restore both anyway. 345 */ 346 handle = bgep->cfg_handle; 347 348 mhcr = pci_config_get32(handle, PCI_CONF_BGE_MHCR); 349 cidp->asic_rev = mhcr & MHCR_CHIP_REV_MASK; 350 cidp->businfo = pci_config_get32(handle, PCI_CONF_BGE_PCISTATE); 351 cidp->command = pci_config_get16(handle, PCI_CONF_COMM); 352 353 cidp->vendor = pci_config_get16(handle, PCI_CONF_VENID); 354 cidp->device = pci_config_get16(handle, PCI_CONF_DEVID); 355 cidp->subven = pci_config_get16(handle, PCI_CONF_SUBVENID); 356 cidp->subdev = pci_config_get16(handle, PCI_CONF_SUBSYSID); 357 cidp->revision = pci_config_get8(handle, PCI_CONF_REVID); 358 cidp->clsize = pci_config_get8(handle, PCI_CONF_CACHE_LINESZ); 359 cidp->latency = pci_config_get8(handle, PCI_CONF_LATENCY_TIMER); 360 361 BGE_DEBUG(("bge_chip_cfg_init: %s bus is %s and %s; #INTA is %s", 362 cidp->businfo & PCISTATE_BUS_IS_PCI ? "PCI" : "PCI-X", 363 cidp->businfo & PCISTATE_BUS_IS_FAST ? "fast" : "slow", 364 cidp->businfo & PCISTATE_BUS_IS_32_BIT ? "narrow" : "wide", 365 cidp->businfo & PCISTATE_INTA_STATE ? "high" : "low")); 366 BGE_DEBUG(("bge_chip_cfg_init: vendor 0x%x device 0x%x revision 0x%x", 367 cidp->vendor, cidp->device, cidp->revision)); 368 BGE_DEBUG(("bge_chip_cfg_init: subven 0x%x subdev 0x%x asic_rev 0x%x", 369 cidp->subven, cidp->subdev, cidp->asic_rev)); 370 BGE_DEBUG(("bge_chip_cfg_init: clsize %d latency %d command 0x%x", 371 cidp->clsize, cidp->latency, cidp->command)); 372 373 /* 374 * Step 2 (also step 6): disable and clear interrupts. 375 * Steps 11-13: configure PIO endianness options, and enable 376 * indirect register access. We'll also select any other 377 * options controlled by the MHCR (e.g. tagged status, mask 378 * interrupt mode) at this stage ... 379 * 380 * Note: internally, the chip is 64-bit and BIG-endian, but 381 * since it talks to the host over a (LITTLE-endian) PCI bus, 382 * it normally swaps bytes around at the PCI interface. 383 * However, the PCI host bridge on SPARC systems normally 384 * swaps the byte lanes around too, since SPARCs are also 385 * BIG-endian. So it turns out that on SPARC, the right 386 * option is to tell the chip to swap (and the host bridge 387 * will swap back again), whereas on x86 we ask the chip 388 * NOT to swap, so the natural little-endianness of the 389 * PCI bus is assumed. Then the only thing that doesn't 390 * automatically work right is access to an 8-byte register 391 * by a little-endian host; but we don't want to set the 392 * MHCR_ENABLE_REGISTER_WORD_SWAP bit because then 4-byte 393 * accesses don't go where expected ;-( So we live with 394 * that, and perform word-swaps in software in the few cases 395 * where a chip register is defined as an 8-byte value -- 396 * see the code below for details ... 397 * 398 * Note: the meaning of the 'MASK_INTERRUPT_MODE' bit isn't 399 * very clear in the register description in the PRM, but 400 * Broadcom document 570X-PG104-R page 248 explains a little 401 * more (under "Broadcom Mask Mode"). The bit changes the way 402 * the MASK_PCI_INT_OUTPUT bit works: with MASK_INTERRUPT_MODE 403 * clear, the chip interprets MASK_PCI_INT_OUTPUT in the same 404 * way as the 5700 did, which isn't very convenient. Setting 405 * the MASK_INTERRUPT_MODE bit makes the MASK_PCI_INT_OUTPUT 406 * bit do just what its name says -- MASK the PCI #INTA output 407 * (i.e. deassert the signal at the pin) leaving all internal 408 * state unchanged. This is much more convenient for our 409 * interrupt handler, so we set MASK_INTERRUPT_MODE here. 410 * 411 * Note: the inconvenient semantics of the interrupt mailbox 412 * (nonzero disables and acknowledges/clears the interrupt, 413 * zero enables AND CLEARS it) would make race conditions 414 * likely in the interrupt handler: 415 * 416 * (1) acknowledge & disable interrupts 417 * (2) while (more to do) 418 * process packets 419 * (3) enable interrupts -- also clears pending 420 * 421 * If the chip received more packets and internally generated 422 * an interrupt between the check at (2) and the mbox write 423 * at (3), this interrupt would be lost :-( 424 * 425 * The best way to avoid this is to use TAGGED STATUS mode, 426 * where the chip includes a unique tag in each status block 427 * update, and the host, when re-enabling interrupts, passes 428 * the last tag it saw back to the chip; then the chip can 429 * see whether the host is truly up to date, and regenerate 430 * its interrupt if not. 431 */ 432 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 433 MHCR_ENABLE_TAGGED_STATUS_MODE | 434 MHCR_MASK_INTERRUPT_MODE | 435 MHCR_CLEAR_INTERRUPT_INTA; 436 437 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 438 mhcr |= MHCR_MASK_PCI_INT_OUTPUT; 439 440 #ifdef _BIG_ENDIAN 441 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 442 #endif /* _BIG_ENDIAN */ 443 444 pci_config_put32(handle, PCI_CONF_BGE_MHCR, mhcr); 445 446 #ifdef BGE_IPMI_ASF 447 bgep->asf_wordswapped = B_FALSE; 448 #endif 449 /* 450 * Step 1 (also step 7): Enable PCI Memory Space accesses 451 * Disable Memory Write/Invalidate 452 * Enable or disable Bus Mastering 453 * 454 * Note that all other bits are taken from the original value saved 455 * the first time through here, rather than from the current register 456 * value, 'cos that will have been cleared by a soft RESET since. 457 * In this way we preserve the OBP/nexus-parent's preferred settings 458 * of the parity-error and system-error enable bits across multiple 459 * chip RESETs. 460 */ 461 command = bgep->chipid.command | PCI_COMM_MAE; 462 command &= ~(PCI_COMM_ME|PCI_COMM_MEMWR_INVAL); 463 if (enable_dma) 464 command |= PCI_COMM_ME; 465 /* 466 * on BCM5714 revision A0, false parity error gets generated 467 * due to a logic bug. Provide a workaround by disabling parity 468 * error. 469 */ 470 if (((cidp->device == DEVICE_ID_5714C) || 471 (cidp->device == DEVICE_ID_5714S)) && 472 (cidp->revision == REVISION_ID_5714_A0)) { 473 command &= ~PCI_COMM_PARITY_DETECT; 474 } 475 pci_config_put16(handle, PCI_CONF_COMM, command); 476 477 /* 478 * On some PCI-E device, there were instances when 479 * the device was still link training. 480 */ 481 if (bgep->chipid.pci_type == BGE_PCI_E) { 482 i = 0; 483 value16 = pci_config_get16(handle, PCI_CONF_COMM); 484 while ((value16 != command) && (i < 100)) { 485 drv_usecwait(200); 486 value16 = pci_config_get16(handle, PCI_CONF_COMM); 487 ++i; 488 } 489 } 490 491 /* 492 * Clear any remaining error status bits 493 */ 494 pci_config_put16(handle, PCI_CONF_STAT, ~0); 495 496 /* 497 * Do following if and only if the device is NOT BCM5714C OR 498 * BCM5715C 499 */ 500 if (!((cidp->device == DEVICE_ID_5714C) || 501 (cidp->device == DEVICE_ID_5715C))) { 502 /* 503 * Make sure these indirect-access registers are sane 504 * rather than random after power-up or reset 505 */ 506 pci_config_put32(handle, PCI_CONF_BGE_RIAAR, 0); 507 pci_config_put32(handle, PCI_CONF_BGE_MWBAR, 0); 508 } 509 /* 510 * Step 8: Disable PCI-X/PCI-E Relaxed Ordering 511 */ 512 bge_cfg_clr16(bgep, PCIX_CONF_COMM, PCIX_COMM_RELAXED); 513 514 if (cidp->pci_type == BGE_PCI_E) { 515 if (DEVICE_5723_SERIES_CHIPSETS(bgep)) { 516 bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL_5723, 517 DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED); 518 } else 519 bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL, 520 DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED); 521 } 522 } 523 524 #ifdef __amd64 525 /* 526 * Distinguish CPU types 527 * 528 * These use to distinguish AMD64 or Intel EM64T of CPU running mode. 529 * If CPU runs on Intel EM64T mode,the 64bit operation cannot works fine 530 * for PCI-Express based network interface card. This is the work-around 531 * for those nics. 532 */ 533 static boolean_t bge_get_em64t_type(void); 534 #pragma inline(bge_get_em64t_type) 535 536 static boolean_t 537 bge_get_em64t_type(void) 538 { 539 540 return (x86_vendor == X86_VENDOR_Intel); 541 } 542 #endif 543 544 /* 545 * Operating register get/set access routines 546 */ 547 548 uint32_t bge_reg_get32(bge_t *bgep, bge_regno_t regno); 549 #pragma inline(bge_reg_get32) 550 551 uint32_t 552 bge_reg_get32(bge_t *bgep, bge_regno_t regno) 553 { 554 BGE_TRACE(("bge_reg_get32($%p, 0x%lx)", 555 (void *)bgep, regno)); 556 557 return (ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno))); 558 } 559 560 void bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data); 561 #pragma inline(bge_reg_put32) 562 563 void 564 bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data) 565 { 566 BGE_TRACE(("bge_reg_put32($%p, 0x%lx, 0x%x)", 567 (void *)bgep, regno, data)); 568 569 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), data); 570 BGE_PCICHK(bgep); 571 } 572 573 void bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 574 #pragma inline(bge_reg_set32) 575 576 void 577 bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 578 { 579 uint32_t regval; 580 581 BGE_TRACE(("bge_reg_set32($%p, 0x%lx, 0x%x)", 582 (void *)bgep, regno, bits)); 583 584 regval = bge_reg_get32(bgep, regno); 585 regval |= bits; 586 bge_reg_put32(bgep, regno, regval); 587 } 588 589 void bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 590 #pragma inline(bge_reg_clr32) 591 592 void 593 bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 594 { 595 uint32_t regval; 596 597 BGE_TRACE(("bge_reg_clr32($%p, 0x%lx, 0x%x)", 598 (void *)bgep, regno, bits)); 599 600 regval = bge_reg_get32(bgep, regno); 601 regval &= ~bits; 602 bge_reg_put32(bgep, regno, regval); 603 } 604 605 static uint64_t bge_reg_get64(bge_t *bgep, bge_regno_t regno); 606 #pragma inline(bge_reg_get64) 607 608 static uint64_t 609 bge_reg_get64(bge_t *bgep, bge_regno_t regno) 610 { 611 uint64_t regval; 612 613 #ifdef __amd64 614 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type()) { 615 regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4)); 616 regval <<= 32; 617 regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 618 } else { 619 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 620 } 621 #elif defined(__sparc) 622 if (DEVICE_5723_SERIES_CHIPSETS(bgep)) { 623 regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 624 regval <<= 32; 625 regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4)); 626 } else { 627 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 628 } 629 #else 630 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 631 #endif 632 633 #ifdef _LITTLE_ENDIAN 634 regval = (regval >> 32) | (regval << 32); 635 #endif /* _LITTLE_ENDIAN */ 636 637 BGE_TRACE(("bge_reg_get64($%p, 0x%lx) = 0x%016llx", 638 (void *)bgep, regno, regval)); 639 640 return (regval); 641 } 642 643 static void bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data); 644 #pragma inline(bge_reg_put64) 645 646 static void 647 bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data) 648 { 649 BGE_TRACE(("bge_reg_put64($%p, 0x%lx, 0x%016llx)", 650 (void *)bgep, regno, data)); 651 652 #ifdef _LITTLE_ENDIAN 653 data = ((data >> 32) | (data << 32)); 654 #endif /* _LITTLE_ENDIAN */ 655 656 #ifdef __amd64 657 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type()) { 658 ddi_put32(bgep->io_handle, 659 PIO_ADDR(bgep, regno), (uint32_t)data); 660 BGE_PCICHK(bgep); 661 ddi_put32(bgep->io_handle, 662 PIO_ADDR(bgep, regno + 4), (uint32_t)(data >> 32)); 663 664 } else { 665 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 666 } 667 #elif defined(__sparc) 668 if (DEVICE_5723_SERIES_CHIPSETS(bgep)) { 669 ddi_put32(bgep->io_handle, 670 PIO_ADDR(bgep, regno + 4), (uint32_t)data); 671 BGE_PCICHK(bgep); 672 ddi_put32(bgep->io_handle, 673 PIO_ADDR(bgep, regno), (uint32_t)(data >> 32)); 674 } else { 675 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 676 } 677 #else 678 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 679 #endif 680 681 BGE_PCICHK(bgep); 682 } 683 684 /* 685 * The DDI doesn't provide get/put functions for 128 bit data 686 * so we put RCBs out as two 64-bit chunks instead. 687 */ 688 static void bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 689 #pragma inline(bge_reg_putrcb) 690 691 static void 692 bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 693 { 694 uint64_t *p; 695 696 BGE_TRACE(("bge_reg_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 697 (void *)bgep, addr, rcbp->host_ring_addr, 698 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 699 700 ASSERT((addr % sizeof (*rcbp)) == 0); 701 702 p = (void *)rcbp; 703 bge_reg_put64(bgep, addr, *p++); 704 bge_reg_put64(bgep, addr+8, *p); 705 } 706 707 void bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data); 708 #pragma inline(bge_mbx_put) 709 710 void 711 bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data) 712 { 713 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) 714 regno += INTERRUPT_LP_MBOX_0_REG - INTERRUPT_MBOX_0_REG + 4; 715 716 BGE_TRACE(("bge_mbx_put($%p, 0x%lx, 0x%016llx)", 717 (void *)bgep, regno, data)); 718 719 /* 720 * Mailbox registers are nominally 64 bits on the 5701, but 721 * the MSW isn't used. On the 5703, they're only 32 bits 722 * anyway. So here we just write the lower(!) 32 bits - 723 * remembering that the chip is big-endian, even though the 724 * PCI bus is little-endian ... 725 */ 726 #ifdef _BIG_ENDIAN 727 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno+4), (uint32_t)data); 728 #else 729 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), (uint32_t)data); 730 #endif /* _BIG_ENDIAN */ 731 BGE_PCICHK(bgep); 732 } 733 734 uint32_t bge_mbx_get(bge_t *bgep, bge_regno_t regno); 735 #pragma inline(bge_mbx_get) 736 737 uint32_t 738 bge_mbx_get(bge_t *bgep, bge_regno_t regno) 739 { 740 uint32_t val32; 741 742 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) 743 regno += INTERRUPT_LP_MBOX_0_REG - INTERRUPT_MBOX_0_REG + 4; 744 745 BGE_TRACE(("bge_mbx_get($%p, 0x%lx)", 746 (void *)bgep, regno)); 747 748 #ifdef _BIG_ENDIAN 749 val32 = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno+4)); 750 #else 751 val32 = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 752 #endif /* _BIG_ENDIAN */ 753 BGE_PCICHK(bgep); 754 755 return (val32); 756 } 757 758 759 #if BGE_DEBUGGING 760 761 void bge_led_mark(bge_t *bgep); 762 #pragma no_inline(bge_led_mark) 763 764 void 765 bge_led_mark(bge_t *bgep) 766 { 767 uint32_t led_ctrl = LED_CONTROL_OVERRIDE_LINK | 768 LED_CONTROL_1000MBPS_LED | 769 LED_CONTROL_100MBPS_LED | 770 LED_CONTROL_10MBPS_LED; 771 772 /* 773 * Blink all three LINK LEDs on simultaneously, then all off, 774 * then restore to automatic hardware control. This is used 775 * in laboratory testing to trigger a logic analyser or scope. 776 */ 777 bge_reg_set32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 778 led_ctrl ^= LED_CONTROL_OVERRIDE_LINK; 779 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 780 led_ctrl = LED_CONTROL_OVERRIDE_LINK; 781 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 782 } 783 784 #endif /* BGE_DEBUGGING */ 785 786 /* 787 * NIC on-chip memory access routines 788 * 789 * Only 32K of NIC memory is visible at a time, controlled by the 790 * Memory Window Base Address Register (in PCI config space). Once 791 * this is set, the 32K region of NIC-local memory that it refers 792 * to can be directly addressed in the upper 32K of the 64K of PCI 793 * memory space used for the device. 794 */ 795 796 static void bge_nic_setwin(bge_t *bgep, bge_regno_t base); 797 #pragma inline(bge_nic_setwin) 798 799 static void 800 bge_nic_setwin(bge_t *bgep, bge_regno_t base) 801 { 802 chip_id_t *cidp; 803 804 BGE_TRACE(("bge_nic_setwin($%p, 0x%lx)", 805 (void *)bgep, base)); 806 807 ASSERT((base & MWBAR_GRANULE_MASK) == 0); 808 809 /* 810 * Don't do repeated zero data writes, 811 * if the device is BCM5714C/15C. 812 */ 813 cidp = &bgep->chipid; 814 if ((cidp->device == DEVICE_ID_5714C) || 815 (cidp->device == DEVICE_ID_5715C)) { 816 if (bgep->lastWriteZeroData && (base == (bge_regno_t)0)) 817 return; 818 /* Adjust lastWriteZeroData */ 819 bgep->lastWriteZeroData = ((base == (bge_regno_t)0) ? 820 B_TRUE : B_FALSE); 821 } 822 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, base); 823 } 824 825 static uint32_t bge_nic_get32(bge_t *bgep, bge_regno_t addr); 826 #pragma inline(bge_nic_get32) 827 828 static uint32_t 829 bge_nic_get32(bge_t *bgep, bge_regno_t addr) 830 { 831 uint32_t data; 832 833 #if defined(BGE_IPMI_ASF) && !defined(__sparc) 834 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 835 /* workaround for word swap error */ 836 if (addr & 4) 837 addr = addr - 4; 838 else 839 addr = addr + 4; 840 } 841 #endif 842 843 #ifdef __sparc 844 data = bge_nic_read32(bgep, addr); 845 #else 846 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 847 addr &= MWBAR_GRANULE_MASK; 848 addr += NIC_MEM_WINDOW_OFFSET; 849 850 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 851 #endif 852 853 BGE_TRACE(("bge_nic_get32($%p, 0x%lx) = 0x%08x", 854 (void *)bgep, addr, data)); 855 856 return (data); 857 } 858 859 void bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data); 860 #pragma inline(bge_nic_put32) 861 862 void 863 bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data) 864 { 865 BGE_TRACE(("bge_nic_put32($%p, 0x%lx, 0x%08x)", 866 (void *)bgep, addr, data)); 867 868 #if defined(BGE_IPMI_ASF) && !defined(__sparc) 869 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 870 /* workaround for word swap error */ 871 if (addr & 4) 872 addr = addr - 4; 873 else 874 addr = addr + 4; 875 } 876 #endif 877 878 #ifdef __sparc 879 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr); 880 data = LE_32(data); 881 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR, data); 882 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0); 883 #else 884 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 885 addr &= MWBAR_GRANULE_MASK; 886 addr += NIC_MEM_WINDOW_OFFSET; 887 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), data); 888 BGE_PCICHK(bgep); 889 #endif 890 } 891 892 static uint64_t bge_nic_get64(bge_t *bgep, bge_regno_t addr); 893 #pragma inline(bge_nic_get64) 894 895 static uint64_t 896 bge_nic_get64(bge_t *bgep, bge_regno_t addr) 897 { 898 uint64_t data; 899 900 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 901 addr &= MWBAR_GRANULE_MASK; 902 addr += NIC_MEM_WINDOW_OFFSET; 903 904 #ifdef __amd64 905 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type()) { 906 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 907 data <<= 32; 908 data |= ddi_get32(bgep->io_handle, 909 PIO_ADDR(bgep, addr + 4)); 910 } else { 911 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 912 } 913 #elif defined(__sparc) 914 if (DEVICE_5723_SERIES_CHIPSETS(bgep)) { 915 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 916 data <<= 32; 917 data |= ddi_get32(bgep->io_handle, 918 PIO_ADDR(bgep, addr + 4)); 919 } else { 920 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 921 } 922 #else 923 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 924 #endif 925 926 BGE_TRACE(("bge_nic_get64($%p, 0x%lx) = 0x%016llx", 927 (void *)bgep, addr, data)); 928 929 return (data); 930 } 931 932 static void bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data); 933 #pragma inline(bge_nic_put64) 934 935 static void 936 bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data) 937 { 938 BGE_TRACE(("bge_nic_put64($%p, 0x%lx, 0x%016llx)", 939 (void *)bgep, addr, data)); 940 941 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 942 addr &= MWBAR_GRANULE_MASK; 943 addr += NIC_MEM_WINDOW_OFFSET; 944 945 #ifdef __amd64 946 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type()) { 947 ddi_put32(bgep->io_handle, 948 PIO_ADDR(bgep, addr), (uint32_t)data); 949 BGE_PCICHK(bgep); 950 ddi_put32(bgep->io_handle, 951 PIO_ADDR(bgep, addr + 4), (uint32_t)(data >> 32)); 952 } else { 953 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 954 } 955 #elif defined(__sparc) 956 if (DEVICE_5723_SERIES_CHIPSETS(bgep)) { 957 ddi_put32(bgep->io_handle, 958 PIO_ADDR(bgep, addr + 4), (uint32_t)data); 959 BGE_PCICHK(bgep); 960 ddi_put32(bgep->io_handle, 961 PIO_ADDR(bgep, addr), (uint32_t)(data >> 32)); 962 } else { 963 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 964 } 965 #else 966 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 967 #endif 968 969 BGE_PCICHK(bgep); 970 } 971 972 /* 973 * The DDI doesn't provide get/put functions for 128 bit data 974 * so we put RCBs out as two 64-bit chunks instead. 975 */ 976 static void bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 977 #pragma inline(bge_nic_putrcb) 978 979 static void 980 bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 981 { 982 uint64_t *p; 983 984 BGE_TRACE(("bge_nic_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 985 (void *)bgep, addr, rcbp->host_ring_addr, 986 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 987 988 ASSERT((addr % sizeof (*rcbp)) == 0); 989 990 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 991 addr &= MWBAR_GRANULE_MASK; 992 addr += NIC_MEM_WINDOW_OFFSET; 993 994 p = (void *)rcbp; 995 #ifdef __amd64 996 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type()) { 997 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), 998 (uint32_t)(*p)); 999 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4), 1000 (uint32_t)(*p >> 32)); 1001 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8), 1002 (uint32_t)(*(p + 1))); 1003 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12), 1004 (uint32_t)(*p >> 32)); 1005 1006 } else { 1007 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 1008 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr+8), *p); 1009 } 1010 #elif defined(__sparc) 1011 if (DEVICE_5723_SERIES_CHIPSETS(bgep)) { 1012 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4), 1013 (uint32_t)(*p)); 1014 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), 1015 (uint32_t)(*p >> 32)); 1016 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12), 1017 (uint32_t)(*(p + 1))); 1018 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8), 1019 (uint32_t)(*p >> 32)); 1020 } else { 1021 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 1022 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p); 1023 } 1024 #else 1025 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 1026 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p); 1027 #endif 1028 1029 BGE_PCICHK(bgep); 1030 } 1031 1032 static void bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes); 1033 #pragma inline(bge_nic_zero) 1034 1035 static void 1036 bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes) 1037 { 1038 BGE_TRACE(("bge_nic_zero($%p, 0x%lx, 0x%x)", 1039 (void *)bgep, addr, nbytes)); 1040 1041 ASSERT((addr & ~MWBAR_GRANULE_MASK) == 1042 ((addr+nbytes) & ~MWBAR_GRANULE_MASK)); 1043 1044 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 1045 addr &= MWBAR_GRANULE_MASK; 1046 addr += NIC_MEM_WINDOW_OFFSET; 1047 1048 (void) ddi_device_zero(bgep->io_handle, PIO_ADDR(bgep, addr), 1049 nbytes, 1, DDI_DATA_SZ08_ACC); 1050 BGE_PCICHK(bgep); 1051 } 1052 1053 /* 1054 * MII (PHY) register get/set access routines 1055 * 1056 * These use the chip's MII auto-access method, controlled by the 1057 * MII Communication register at 0x044c, so the CPU doesn't have 1058 * to fiddle with the individual bits. 1059 */ 1060 1061 #undef BGE_DBG 1062 #define BGE_DBG BGE_DBG_MII /* debug flag for this code */ 1063 1064 static uint16_t bge_mii_access(bge_t *bgep, bge_regno_t regno, 1065 uint16_t data, uint32_t cmd); 1066 #pragma no_inline(bge_mii_access) 1067 1068 static uint16_t 1069 bge_mii_access(bge_t *bgep, bge_regno_t regno, uint16_t data, uint32_t cmd) 1070 { 1071 uint32_t timeout; 1072 uint32_t regval1; 1073 uint32_t regval2; 1074 1075 BGE_TRACE(("bge_mii_access($%p, 0x%lx, 0x%x, 0x%x)", 1076 (void *)bgep, regno, data, cmd)); 1077 1078 ASSERT(mutex_owned(bgep->genlock)); 1079 1080 /* 1081 * Assemble the command ... 1082 */ 1083 cmd |= data << MI_COMMS_DATA_SHIFT; 1084 cmd |= regno << MI_COMMS_REGISTER_SHIFT; 1085 cmd |= bgep->phy_mii_addr << MI_COMMS_ADDRESS_SHIFT; 1086 cmd |= MI_COMMS_START; 1087 1088 /* 1089 * Wait for any command already in progress ... 1090 * 1091 * Note: this *shouldn't* ever find that there is a command 1092 * in progress, because we already hold the <genlock> mutex. 1093 * Nonetheless, we have sometimes seen the MI_COMMS_START 1094 * bit set here -- it seems that the chip can initiate MII 1095 * accesses internally, even with polling OFF. 1096 */ 1097 regval1 = regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1098 for (timeout = 100; ; ) { 1099 if ((regval2 & MI_COMMS_START) == 0) { 1100 bge_reg_put32(bgep, MI_COMMS_REG, cmd); 1101 break; 1102 } 1103 if (--timeout == 0) 1104 break; 1105 drv_usecwait(10); 1106 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1107 } 1108 1109 if (timeout == 0) 1110 return ((uint16_t)~0u); 1111 1112 if (timeout != 100) 1113 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1114 "MI_COMMS_START set for %d us; 0x%x->0x%x", 1115 cmd, 10*(100-timeout), regval1, regval2)); 1116 1117 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1118 for (timeout = 1000; ; ) { 1119 if ((regval1 & MI_COMMS_START) == 0) 1120 break; 1121 if (--timeout == 0) 1122 break; 1123 drv_usecwait(10); 1124 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1125 } 1126 1127 /* 1128 * Drop out early if the READ FAILED bit is set -- this chip 1129 * could be a 5703/4S, with a SerDes instead of a PHY! 1130 */ 1131 if (regval2 & MI_COMMS_READ_FAILED) 1132 return ((uint16_t)~0u); 1133 1134 if (timeout == 0) 1135 return ((uint16_t)~0u); 1136 1137 /* 1138 * The PRM says to wait 5us after seeing the START bit clear 1139 * and then re-read the register to get the final value of the 1140 * data field, in order to avoid a race condition where the 1141 * START bit is clear but the data field isn't yet valid. 1142 * 1143 * Note: we don't actually seem to be encounter this race; 1144 * except when the START bit is seen set again (see below), 1145 * the data field doesn't change during this 5us interval. 1146 */ 1147 drv_usecwait(5); 1148 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1149 1150 /* 1151 * Unfortunately, when following the PRMs instructions above, 1152 * we have occasionally seen the START bit set again(!) in the 1153 * value read after the 5us delay. This seems to be due to the 1154 * chip autonomously starting another MII access internally. 1155 * In such cases, the command/data/etc fields relate to the 1156 * internal command, rather than the one that we thought had 1157 * just finished. So in this case, we fall back to returning 1158 * the data from the original read that showed START clear. 1159 */ 1160 if (regval2 & MI_COMMS_START) { 1161 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1162 "MI_COMMS_START set after transaction; 0x%x->0x%x", 1163 cmd, regval1, regval2)); 1164 regval2 = regval1; 1165 } 1166 1167 if (regval2 & MI_COMMS_START) 1168 return ((uint16_t)~0u); 1169 1170 if (regval2 & MI_COMMS_READ_FAILED) 1171 return ((uint16_t)~0u); 1172 1173 return ((regval2 & MI_COMMS_DATA_MASK) >> MI_COMMS_DATA_SHIFT); 1174 } 1175 1176 uint16_t bge_mii_get16(bge_t *bgep, bge_regno_t regno); 1177 #pragma no_inline(bge_mii_get16) 1178 1179 uint16_t 1180 bge_mii_get16(bge_t *bgep, bge_regno_t regno) 1181 { 1182 BGE_TRACE(("bge_mii_get16($%p, 0x%lx)", 1183 (void *)bgep, regno)); 1184 1185 ASSERT(mutex_owned(bgep->genlock)); 1186 1187 if (DEVICE_5906_SERIES_CHIPSETS(bgep) && ((regno == MII_AUX_CONTROL) || 1188 (regno == MII_1000BASE_T_CONTROL))) 1189 return (0); 1190 1191 return (bge_mii_access(bgep, regno, 0, MI_COMMS_COMMAND_READ)); 1192 } 1193 1194 void bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data); 1195 #pragma no_inline(bge_mii_put16) 1196 1197 void 1198 bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data) 1199 { 1200 BGE_TRACE(("bge_mii_put16($%p, 0x%lx, 0x%x)", 1201 (void *)bgep, regno, data)); 1202 1203 ASSERT(mutex_owned(bgep->genlock)); 1204 1205 if (DEVICE_5906_SERIES_CHIPSETS(bgep) && ((regno == MII_AUX_CONTROL) || 1206 (regno == MII_1000BASE_T_CONTROL))) 1207 return; 1208 1209 (void) bge_mii_access(bgep, regno, data, MI_COMMS_COMMAND_WRITE); 1210 } 1211 1212 #undef BGE_DBG 1213 #define BGE_DBG BGE_DBG_SEEPROM /* debug flag for this code */ 1214 1215 #if BGE_SEE_IO32 || BGE_FLASH_IO32 1216 1217 /* 1218 * Basic SEEPROM get/set access routine 1219 * 1220 * This uses the chip's SEEPROM auto-access method, controlled by the 1221 * Serial EEPROM Address/Data Registers at 0x6838/683c, so the CPU 1222 * doesn't have to fiddle with the individual bits. 1223 * 1224 * The caller should hold <genlock> and *also* have already acquired 1225 * the right to access the SEEPROM, via bge_nvmem_acquire() above. 1226 * 1227 * Return value: 1228 * 0 on success, 1229 * ENODATA on access timeout (maybe retryable: device may just be busy) 1230 * EPROTO on other h/w or s/w errors. 1231 * 1232 * <*dp> is an input to a SEEPROM_ACCESS_WRITE operation, or an output 1233 * from a (successful) SEEPROM_ACCESS_READ. 1234 */ 1235 static int bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1236 uint32_t *dp); 1237 #pragma no_inline(bge_seeprom_access) 1238 1239 static int 1240 bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1241 { 1242 uint32_t tries; 1243 uint32_t regval; 1244 1245 ASSERT(mutex_owned(bgep->genlock)); 1246 1247 /* 1248 * On the newer chips that support both SEEPROM & Flash, we need 1249 * to specifically enable SEEPROM access (Flash is the default). 1250 * On older chips, we don't; SEEPROM is the only NVtype supported, 1251 * and the NVM control registers don't exist ... 1252 */ 1253 switch (bgep->chipid.nvtype) { 1254 case BGE_NVTYPE_NONE: 1255 case BGE_NVTYPE_UNKNOWN: 1256 _NOTE(NOTREACHED) 1257 case BGE_NVTYPE_SEEPROM: 1258 break; 1259 1260 case BGE_NVTYPE_LEGACY_SEEPROM: 1261 case BGE_NVTYPE_UNBUFFERED_FLASH: 1262 case BGE_NVTYPE_BUFFERED_FLASH: 1263 default: 1264 bge_reg_set32(bgep, NVM_CONFIG1_REG, 1265 NVM_CFG1_LEGACY_SEEPROM_MODE); 1266 break; 1267 } 1268 1269 /* 1270 * Check there's no command in progress. 1271 * 1272 * Note: this *shouldn't* ever find that there is a command 1273 * in progress, because we already hold the <genlock> mutex. 1274 * Also, to ensure we don't have a conflict with the chip's 1275 * internal firmware or a process accessing the same (shared) 1276 * SEEPROM through the other port of a 5704, we've already 1277 * been through the "software arbitration" protocol. 1278 * So this is just a final consistency check: we shouldn't 1279 * see EITHER the START bit (command started but not complete) 1280 * OR the COMPLETE bit (command completed but not cleared). 1281 */ 1282 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1283 if (regval & SEEPROM_ACCESS_START) 1284 return (EPROTO); 1285 if (regval & SEEPROM_ACCESS_COMPLETE) 1286 return (EPROTO); 1287 1288 /* 1289 * Assemble the command ... 1290 */ 1291 cmd |= addr & SEEPROM_ACCESS_ADDRESS_MASK; 1292 addr >>= SEEPROM_ACCESS_ADDRESS_SIZE; 1293 addr <<= SEEPROM_ACCESS_DEVID_SHIFT; 1294 cmd |= addr & SEEPROM_ACCESS_DEVID_MASK; 1295 cmd |= SEEPROM_ACCESS_START; 1296 cmd |= SEEPROM_ACCESS_COMPLETE; 1297 cmd |= regval & SEEPROM_ACCESS_HALFCLOCK_MASK; 1298 1299 bge_reg_put32(bgep, SERIAL_EEPROM_DATA_REG, *dp); 1300 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, cmd); 1301 1302 /* 1303 * By observation, a successful access takes ~20us on a 5703/4, 1304 * but apparently much longer (up to 1000us) on the obsolescent 1305 * BCM5700/BCM5701. We want to be sure we don't get any false 1306 * timeouts here; but OTOH, we don't want a bogus access to lock 1307 * out interrupts for longer than necessary. So we'll allow up 1308 * to 1000us ... 1309 */ 1310 for (tries = 0; tries < 1000; ++tries) { 1311 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1312 if (regval & SEEPROM_ACCESS_COMPLETE) 1313 break; 1314 drv_usecwait(1); 1315 } 1316 1317 if (regval & SEEPROM_ACCESS_COMPLETE) { 1318 /* 1319 * All OK; read the SEEPROM data register, then write back 1320 * the value read from the address register in order to 1321 * clear the <complete> bit and leave the SEEPROM access 1322 * state machine idle, ready for the next access ... 1323 */ 1324 BGE_DEBUG(("bge_seeprom_access: complete after %d us", tries)); 1325 *dp = bge_reg_get32(bgep, SERIAL_EEPROM_DATA_REG); 1326 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, regval); 1327 return (0); 1328 } 1329 1330 /* 1331 * Hmm ... what happened here? 1332 * 1333 * Most likely, the user addressed a non-existent SEEPROM. Or 1334 * maybe the SEEPROM was busy internally (e.g. processing a write) 1335 * and didn't respond to being addressed. Either way, it's left 1336 * the SEEPROM access state machine wedged. So we'll reset it 1337 * before we leave, so it's ready for next time ... 1338 */ 1339 BGE_DEBUG(("bge_seeprom_access: timed out after %d us", tries)); 1340 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 1341 return (ENODATA); 1342 } 1343 1344 /* 1345 * Basic Flash get/set access routine 1346 * 1347 * These use the chip's Flash auto-access method, controlled by the 1348 * Flash Access Registers at 0x7000-701c, so the CPU doesn't have to 1349 * fiddle with the individual bits. 1350 * 1351 * The caller should hold <genlock> and *also* have already acquired 1352 * the right to access the Flash, via bge_nvmem_acquire() above. 1353 * 1354 * Return value: 1355 * 0 on success, 1356 * ENODATA on access timeout (maybe retryable: device may just be busy) 1357 * ENODEV if the NVmem device is missing or otherwise unusable 1358 * 1359 * <*dp> is an input to a NVM_FLASH_CMD_WR operation, or an output 1360 * from a (successful) NVM_FLASH_CMD_RD. 1361 */ 1362 static int bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1363 uint32_t *dp); 1364 #pragma no_inline(bge_flash_access) 1365 1366 static int 1367 bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1368 { 1369 uint32_t tries; 1370 uint32_t regval; 1371 1372 ASSERT(mutex_owned(bgep->genlock)); 1373 1374 /* 1375 * On the newer chips that support both SEEPROM & Flash, we need 1376 * to specifically disable SEEPROM access while accessing Flash. 1377 * The older chips don't support Flash, and the NVM registers don't 1378 * exist, so we shouldn't be here at all! 1379 */ 1380 switch (bgep->chipid.nvtype) { 1381 case BGE_NVTYPE_NONE: 1382 case BGE_NVTYPE_UNKNOWN: 1383 _NOTE(NOTREACHED) 1384 case BGE_NVTYPE_SEEPROM: 1385 return (ENODEV); 1386 1387 case BGE_NVTYPE_LEGACY_SEEPROM: 1388 case BGE_NVTYPE_UNBUFFERED_FLASH: 1389 case BGE_NVTYPE_BUFFERED_FLASH: 1390 default: 1391 bge_reg_clr32(bgep, NVM_CONFIG1_REG, 1392 NVM_CFG1_LEGACY_SEEPROM_MODE); 1393 break; 1394 } 1395 1396 /* 1397 * Assemble the command ... 1398 */ 1399 addr &= NVM_FLASH_ADDR_MASK; 1400 cmd |= NVM_FLASH_CMD_DOIT; 1401 cmd |= NVM_FLASH_CMD_FIRST; 1402 cmd |= NVM_FLASH_CMD_LAST; 1403 cmd |= NVM_FLASH_CMD_DONE; 1404 1405 bge_reg_put32(bgep, NVM_FLASH_WRITE_REG, *dp); 1406 bge_reg_put32(bgep, NVM_FLASH_ADDR_REG, addr); 1407 bge_reg_put32(bgep, NVM_FLASH_CMD_REG, cmd); 1408 1409 /* 1410 * Allow up to 1000ms ... 1411 */ 1412 for (tries = 0; tries < 1000; ++tries) { 1413 regval = bge_reg_get32(bgep, NVM_FLASH_CMD_REG); 1414 if (regval & NVM_FLASH_CMD_DONE) 1415 break; 1416 drv_usecwait(1); 1417 } 1418 1419 if (regval & NVM_FLASH_CMD_DONE) { 1420 /* 1421 * All OK; read the data from the Flash read register 1422 */ 1423 BGE_DEBUG(("bge_flash_access: complete after %d us", tries)); 1424 *dp = bge_reg_get32(bgep, NVM_FLASH_READ_REG); 1425 return (0); 1426 } 1427 1428 /* 1429 * Hmm ... what happened here? 1430 * 1431 * Most likely, the user addressed a non-existent Flash. Or 1432 * maybe the Flash was busy internally (e.g. processing a write) 1433 * and didn't respond to being addressed. Either way, there's 1434 * nothing we can here ... 1435 */ 1436 BGE_DEBUG(("bge_flash_access: timed out after %d us", tries)); 1437 return (ENODATA); 1438 } 1439 1440 /* 1441 * The next two functions regulate access to the NVram (if fitted). 1442 * 1443 * On a 5704 (dual core) chip, there's only one SEEPROM and one Flash 1444 * (SPI) interface, but they can be accessed through either port. These 1445 * are managed by different instance of this driver and have no software 1446 * state in common. 1447 * 1448 * In addition (and even on a single core chip) the chip's internal 1449 * firmware can access the SEEPROM/Flash, most notably after a RESET 1450 * when it may download code to run internally. 1451 * 1452 * So we need to arbitrate between these various software agents. For 1453 * this purpose, the chip provides the Software Arbitration Register, 1454 * which implements hardware(!) arbitration. 1455 * 1456 * This functionality didn't exist on older (5700/5701) chips, so there's 1457 * nothing we can do by way of arbitration on those; also, if there's no 1458 * SEEPROM/Flash fitted (or we couldn't determine what type), there's also 1459 * nothing to do. 1460 * 1461 * The internal firmware appears to use Request 0, which is the highest 1462 * priority. So we'd like to use Request 2, leaving one higher and one 1463 * lower for any future developments ... but apparently this doesn't 1464 * always work. So for now, the code uses Request 1 ;-( 1465 */ 1466 1467 #define NVM_READ_REQ NVM_READ_REQ1 1468 #define NVM_RESET_REQ NVM_RESET_REQ1 1469 #define NVM_SET_REQ NVM_SET_REQ1 1470 1471 static void bge_nvmem_relinquish(bge_t *bgep); 1472 #pragma no_inline(bge_nvmem_relinquish) 1473 1474 static void 1475 bge_nvmem_relinquish(bge_t *bgep) 1476 { 1477 ASSERT(mutex_owned(bgep->genlock)); 1478 1479 switch (bgep->chipid.nvtype) { 1480 case BGE_NVTYPE_NONE: 1481 case BGE_NVTYPE_UNKNOWN: 1482 _NOTE(NOTREACHED) 1483 return; 1484 1485 case BGE_NVTYPE_SEEPROM: 1486 /* 1487 * No arbitration performed, no release needed 1488 */ 1489 return; 1490 1491 case BGE_NVTYPE_LEGACY_SEEPROM: 1492 case BGE_NVTYPE_UNBUFFERED_FLASH: 1493 case BGE_NVTYPE_BUFFERED_FLASH: 1494 default: 1495 break; 1496 } 1497 1498 /* 1499 * Our own request should be present (whether or not granted) ... 1500 */ 1501 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1502 1503 /* 1504 * ... this will make it go away. 1505 */ 1506 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_RESET_REQ); 1507 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1508 } 1509 1510 /* 1511 * Arbitrate for access to the NVmem, if necessary 1512 * 1513 * Return value: 1514 * 0 on success 1515 * EAGAIN if the device is in use (retryable) 1516 * ENODEV if the NVmem device is missing or otherwise unusable 1517 */ 1518 static int bge_nvmem_acquire(bge_t *bgep); 1519 #pragma no_inline(bge_nvmem_acquire) 1520 1521 static int 1522 bge_nvmem_acquire(bge_t *bgep) 1523 { 1524 uint32_t regval; 1525 uint32_t tries; 1526 1527 ASSERT(mutex_owned(bgep->genlock)); 1528 1529 switch (bgep->chipid.nvtype) { 1530 case BGE_NVTYPE_NONE: 1531 case BGE_NVTYPE_UNKNOWN: 1532 /* 1533 * Access denied: no (recognisable) device fitted 1534 */ 1535 return (ENODEV); 1536 1537 case BGE_NVTYPE_SEEPROM: 1538 /* 1539 * Access granted: no arbitration needed (or possible) 1540 */ 1541 return (0); 1542 1543 case BGE_NVTYPE_LEGACY_SEEPROM: 1544 case BGE_NVTYPE_UNBUFFERED_FLASH: 1545 case BGE_NVTYPE_BUFFERED_FLASH: 1546 default: 1547 /* 1548 * Access conditional: conduct arbitration protocol 1549 */ 1550 break; 1551 } 1552 1553 /* 1554 * We're holding the per-port mutex <genlock>, so no-one other 1555 * thread can be attempting to access the NVmem through *this* 1556 * port. But it could be in use by the *other* port (of a 5704), 1557 * or by the chip's internal firmware, so we have to go through 1558 * the full (hardware) arbitration protocol ... 1559 * 1560 * Note that *because* we're holding <genlock>, the interrupt handler 1561 * won't be able to progress. So we're only willing to spin for a 1562 * fairly short time. Specifically: 1563 * 1564 * We *must* wait long enough for the hardware to resolve all 1565 * requests and determine the winner. Fortunately, this is 1566 * "almost instantaneous", even as observed by GHz CPUs. 1567 * 1568 * A successful access by another Solaris thread (via either 1569 * port) typically takes ~20us. So waiting a bit longer than 1570 * that will give a good chance of success, if the other user 1571 * *is* another thread on the other port. 1572 * 1573 * However, the internal firmware can hold on to the NVmem 1574 * for *much* longer: at least 10 milliseconds just after a 1575 * RESET, and maybe even longer if the NVmem actually contains 1576 * code to download and run on the internal CPUs. 1577 * 1578 * So, we'll allow 50us; if that's not enough then it's up to the 1579 * caller to retry later (hence the choice of return code EAGAIN). 1580 */ 1581 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1582 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_SET_REQ); 1583 1584 for (tries = 0; tries < 50; ++tries) { 1585 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1586 if (regval & NVM_WON_REQ1) 1587 break; 1588 drv_usecwait(1); 1589 } 1590 1591 if (regval & NVM_WON_REQ1) { 1592 BGE_DEBUG(("bge_nvmem_acquire: won after %d us", tries)); 1593 return (0); 1594 } 1595 1596 /* 1597 * Somebody else must be accessing the NVmem, so abandon our 1598 * attempt take control of it. The caller can try again later ... 1599 */ 1600 BGE_DEBUG(("bge_nvmem_acquire: lost after %d us", tries)); 1601 bge_nvmem_relinquish(bgep); 1602 return (EAGAIN); 1603 } 1604 1605 /* 1606 * This code assumes that the GPIO1 bit has been wired up to the NVmem 1607 * write protect line in such a way that the NVmem is protected when 1608 * GPIO1 is an input, or is an output but driven high. Thus, to make the 1609 * NVmem writable we have to change GPIO1 to an output AND drive it low. 1610 * 1611 * Note: there's only one set of GPIO pins on a 5704, even though they 1612 * can be accessed through either port. So the chip has to resolve what 1613 * happens if the two ports program a single pin differently ... the rule 1614 * it uses is that if the ports disagree about the *direction* of a pin, 1615 * "output" wins over "input", but if they disagree about its *value* as 1616 * an output, then the pin is TRISTATED instead! In such a case, no-one 1617 * wins, and the external signal does whatever the external circuitry 1618 * defines as the default -- which we've assumed is the PROTECTED state. 1619 * So, we always change GPIO1 back to being an *input* whenever we're not 1620 * specifically using it to unprotect the NVmem. This allows either port 1621 * to update the NVmem, although obviously only one at a time! 1622 * 1623 * The caller should hold <genlock> and *also* have already acquired the 1624 * right to access the NVmem, via bge_nvmem_acquire() above. 1625 */ 1626 static void bge_nvmem_protect(bge_t *bgep, boolean_t protect); 1627 #pragma inline(bge_nvmem_protect) 1628 1629 static void 1630 bge_nvmem_protect(bge_t *bgep, boolean_t protect) 1631 { 1632 uint32_t regval; 1633 1634 ASSERT(mutex_owned(bgep->genlock)); 1635 1636 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 1637 if (protect) { 1638 regval |= MLCR_MISC_PINS_OUTPUT_1; 1639 regval &= ~MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1640 } else { 1641 regval &= ~MLCR_MISC_PINS_OUTPUT_1; 1642 regval |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1643 } 1644 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, regval); 1645 } 1646 1647 /* 1648 * Now put it all together ... 1649 * 1650 * Try to acquire control of the NVmem; if successful, then: 1651 * unprotect it (if we want to write to it) 1652 * perform the requested access 1653 * reprotect it (after a write) 1654 * relinquish control 1655 * 1656 * Return value: 1657 * 0 on success, 1658 * EAGAIN if the device is in use (retryable) 1659 * ENODATA on access timeout (maybe retryable: device may just be busy) 1660 * ENODEV if the NVmem device is missing or otherwise unusable 1661 * EPROTO on other h/w or s/w errors. 1662 */ 1663 static int 1664 bge_nvmem_rw32(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1665 { 1666 int err; 1667 1668 if ((err = bge_nvmem_acquire(bgep)) == 0) { 1669 switch (cmd) { 1670 case BGE_SEE_READ: 1671 err = bge_seeprom_access(bgep, 1672 SEEPROM_ACCESS_READ, addr, dp); 1673 break; 1674 1675 case BGE_SEE_WRITE: 1676 bge_nvmem_protect(bgep, B_FALSE); 1677 err = bge_seeprom_access(bgep, 1678 SEEPROM_ACCESS_WRITE, addr, dp); 1679 bge_nvmem_protect(bgep, B_TRUE); 1680 break; 1681 1682 case BGE_FLASH_READ: 1683 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1684 DEVICE_5723_SERIES_CHIPSETS(bgep) || 1685 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1686 bge_reg_set32(bgep, NVM_ACCESS_REG, 1687 NVM_ACCESS_ENABLE); 1688 } 1689 err = bge_flash_access(bgep, 1690 NVM_FLASH_CMD_RD, addr, dp); 1691 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1692 DEVICE_5723_SERIES_CHIPSETS(bgep) || 1693 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1694 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1695 NVM_ACCESS_ENABLE); 1696 } 1697 break; 1698 1699 case BGE_FLASH_WRITE: 1700 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1701 DEVICE_5723_SERIES_CHIPSETS(bgep) || 1702 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1703 bge_reg_set32(bgep, NVM_ACCESS_REG, 1704 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1705 } 1706 bge_nvmem_protect(bgep, B_FALSE); 1707 err = bge_flash_access(bgep, 1708 NVM_FLASH_CMD_WR, addr, dp); 1709 bge_nvmem_protect(bgep, B_TRUE); 1710 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1711 DEVICE_5723_SERIES_CHIPSETS(bgep) || 1712 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1713 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1714 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1715 } 1716 1717 break; 1718 1719 default: 1720 _NOTE(NOTREACHED) 1721 break; 1722 } 1723 bge_nvmem_relinquish(bgep); 1724 } 1725 1726 BGE_DEBUG(("bge_nvmem_rw32: err %d", err)); 1727 return (err); 1728 } 1729 1730 /* 1731 * Attempt to get a MAC address from the SEEPROM or Flash, if any 1732 */ 1733 static uint64_t bge_get_nvmac(bge_t *bgep); 1734 #pragma no_inline(bge_get_nvmac) 1735 1736 static uint64_t 1737 bge_get_nvmac(bge_t *bgep) 1738 { 1739 uint32_t mac_high; 1740 uint32_t mac_low; 1741 uint32_t addr; 1742 uint32_t cmd; 1743 uint64_t mac; 1744 1745 BGE_TRACE(("bge_get_nvmac($%p)", 1746 (void *)bgep)); 1747 1748 switch (bgep->chipid.nvtype) { 1749 case BGE_NVTYPE_NONE: 1750 case BGE_NVTYPE_UNKNOWN: 1751 default: 1752 return (0ULL); 1753 1754 case BGE_NVTYPE_SEEPROM: 1755 case BGE_NVTYPE_LEGACY_SEEPROM: 1756 cmd = BGE_SEE_READ; 1757 break; 1758 1759 case BGE_NVTYPE_UNBUFFERED_FLASH: 1760 case BGE_NVTYPE_BUFFERED_FLASH: 1761 cmd = BGE_FLASH_READ; 1762 break; 1763 } 1764 1765 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) 1766 addr = NVMEM_DATA_MAC_ADDRESS_5906; 1767 else 1768 addr = NVMEM_DATA_MAC_ADDRESS; 1769 1770 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_high)) 1771 return (0ULL); 1772 addr += 4; 1773 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_low)) 1774 return (0ULL); 1775 1776 /* 1777 * The Broadcom chip is natively BIG-endian, so that's how the 1778 * MAC address is represented in NVmem. We may need to swap it 1779 * around on a little-endian host ... 1780 */ 1781 #ifdef _BIG_ENDIAN 1782 mac = mac_high; 1783 mac = mac << 32; 1784 mac |= mac_low; 1785 #else 1786 mac = BGE_BSWAP_32(mac_high); 1787 mac = mac << 32; 1788 mac |= BGE_BSWAP_32(mac_low); 1789 #endif /* _BIG_ENDIAN */ 1790 1791 return (mac); 1792 } 1793 1794 #else /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1795 1796 /* 1797 * Dummy version for when we're not supporting NVmem access 1798 */ 1799 static uint64_t bge_get_nvmac(bge_t *bgep); 1800 #pragma inline(bge_get_nvmac) 1801 1802 static uint64_t 1803 bge_get_nvmac(bge_t *bgep) 1804 { 1805 _NOTE(ARGUNUSED(bgep)) 1806 return (0ULL); 1807 } 1808 1809 #endif /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1810 1811 /* 1812 * Determine the type of NVmem that is (or may be) attached to this chip, 1813 */ 1814 static enum bge_nvmem_type bge_nvmem_id(bge_t *bgep); 1815 #pragma no_inline(bge_nvmem_id) 1816 1817 static enum bge_nvmem_type 1818 bge_nvmem_id(bge_t *bgep) 1819 { 1820 enum bge_nvmem_type nvtype; 1821 uint32_t config1; 1822 1823 BGE_TRACE(("bge_nvmem_id($%p)", 1824 (void *)bgep)); 1825 1826 switch (bgep->chipid.device) { 1827 default: 1828 /* 1829 * We shouldn't get here; it means we don't recognise 1830 * the chip, which means we don't know how to determine 1831 * what sort of NVmem (if any) it has. So we'll say 1832 * NONE, to disable the NVmem access code ... 1833 */ 1834 nvtype = BGE_NVTYPE_NONE; 1835 break; 1836 1837 case DEVICE_ID_5700: 1838 case DEVICE_ID_5700x: 1839 case DEVICE_ID_5701: 1840 /* 1841 * These devices support *only* SEEPROMs 1842 */ 1843 nvtype = BGE_NVTYPE_SEEPROM; 1844 break; 1845 1846 case DEVICE_ID_5702: 1847 case DEVICE_ID_5702fe: 1848 case DEVICE_ID_5703C: 1849 case DEVICE_ID_5703S: 1850 case DEVICE_ID_5704C: 1851 case DEVICE_ID_5704S: 1852 case DEVICE_ID_5704: 1853 case DEVICE_ID_5705M: 1854 case DEVICE_ID_5705C: 1855 case DEVICE_ID_5705_2: 1856 case DEVICE_ID_5780: 1857 case DEVICE_ID_5782: 1858 case DEVICE_ID_5787: 1859 case DEVICE_ID_5787M: 1860 case DEVICE_ID_5788: 1861 case DEVICE_ID_5789: 1862 case DEVICE_ID_5751: 1863 case DEVICE_ID_5751M: 1864 case DEVICE_ID_5752: 1865 case DEVICE_ID_5752M: 1866 case DEVICE_ID_5754: 1867 case DEVICE_ID_5755: 1868 case DEVICE_ID_5755M: 1869 case DEVICE_ID_5756M: 1870 case DEVICE_ID_5721: 1871 case DEVICE_ID_5722: 1872 case DEVICE_ID_5723: 1873 case DEVICE_ID_5714C: 1874 case DEVICE_ID_5714S: 1875 case DEVICE_ID_5715C: 1876 case DEVICE_ID_5715S: 1877 config1 = bge_reg_get32(bgep, NVM_CONFIG1_REG); 1878 if (config1 & NVM_CFG1_FLASH_MODE) 1879 if (config1 & NVM_CFG1_BUFFERED_MODE) 1880 nvtype = BGE_NVTYPE_BUFFERED_FLASH; 1881 else 1882 nvtype = BGE_NVTYPE_UNBUFFERED_FLASH; 1883 else 1884 nvtype = BGE_NVTYPE_LEGACY_SEEPROM; 1885 break; 1886 case DEVICE_ID_5906: 1887 case DEVICE_ID_5906M: 1888 nvtype = BGE_NVTYPE_BUFFERED_FLASH; 1889 break; 1890 } 1891 1892 return (nvtype); 1893 } 1894 1895 #undef BGE_DBG 1896 #define BGE_DBG BGE_DBG_CHIP /* debug flag for this code */ 1897 1898 static void 1899 bge_init_recv_rule(bge_t *bgep) 1900 { 1901 bge_recv_rule_t *rulep = bgep->recv_rules; 1902 uint32_t i; 1903 1904 /* 1905 * Initialize receive rule registers. 1906 * Note that rules may persist across each bge_m_start/stop() call. 1907 */ 1908 for (i = 0; i < RECV_RULES_NUM_MAX; i++, rulep++) { 1909 bge_reg_put32(bgep, RECV_RULE_MASK_REG(i), rulep->mask_value); 1910 bge_reg_put32(bgep, RECV_RULE_CONTROL_REG(i), rulep->control); 1911 } 1912 } 1913 1914 /* 1915 * Using the values captured by bge_chip_cfg_init(), and additional probes 1916 * as required, characterise the chip fully: determine the label by which 1917 * to refer to this chip, the correct settings for various registers, and 1918 * of course whether the device and/or subsystem are supported! 1919 */ 1920 int bge_chip_id_init(bge_t *bgep); 1921 #pragma no_inline(bge_chip_id_init) 1922 1923 int 1924 bge_chip_id_init(bge_t *bgep) 1925 { 1926 char buf[MAXPATHLEN]; /* any risk of stack overflow? */ 1927 boolean_t sys_ok; 1928 boolean_t dev_ok; 1929 chip_id_t *cidp; 1930 uint32_t subid; 1931 char *devname; 1932 char *sysname; 1933 int *ids; 1934 int err; 1935 uint_t i; 1936 1937 sys_ok = dev_ok = B_FALSE; 1938 cidp = &bgep->chipid; 1939 1940 /* 1941 * Check the PCI device ID to determine the generic chip type and 1942 * select parameters that depend on this. 1943 * 1944 * Note: because the SPARC platforms in general don't fit the 1945 * SEEPROM 'behind' the chip, the PCI revision ID register reads 1946 * as zero - which is why we use <asic_rev> rather than <revision> 1947 * below ... 1948 * 1949 * Note: in general we can't distinguish between the Copper/SerDes 1950 * versions by ID alone, as some Copper devices (e.g. some but not 1951 * all 5703Cs) have the same ID as the SerDes equivalents. So we 1952 * treat them the same here, and the MII code works out the media 1953 * type later on ... 1954 */ 1955 cidp->mbuf_base = bge_mbuf_pool_base; 1956 cidp->mbuf_length = bge_mbuf_pool_len; 1957 cidp->recv_slots = BGE_RECV_SLOTS_USED; 1958 cidp->bge_dma_rwctrl = bge_dma_rwctrl; 1959 cidp->pci_type = BGE_PCI_X; 1960 cidp->statistic_type = BGE_STAT_BLK; 1961 cidp->mbuf_lo_water_rdma = bge_mbuf_lo_water_rdma; 1962 cidp->mbuf_lo_water_rmac = bge_mbuf_lo_water_rmac; 1963 cidp->mbuf_hi_water = bge_mbuf_hi_water; 1964 cidp->rx_ticks_norm = bge_rx_ticks_norm; 1965 cidp->rx_count_norm = bge_rx_count_norm; 1966 1967 if (cidp->rx_rings == 0 || cidp->rx_rings > BGE_RECV_RINGS_MAX) 1968 cidp->rx_rings = BGE_RECV_RINGS_DEFAULT; 1969 if (cidp->tx_rings == 0 || cidp->tx_rings > BGE_SEND_RINGS_MAX) 1970 cidp->tx_rings = BGE_SEND_RINGS_DEFAULT; 1971 1972 cidp->msi_enabled = B_FALSE; 1973 1974 switch (cidp->device) { 1975 case DEVICE_ID_5700: 1976 case DEVICE_ID_5700x: 1977 cidp->chip_label = 5700; 1978 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1979 break; 1980 1981 case DEVICE_ID_5701: 1982 cidp->chip_label = 5701; 1983 dev_ok = B_TRUE; 1984 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1985 break; 1986 1987 case DEVICE_ID_5702: 1988 case DEVICE_ID_5702fe: 1989 cidp->chip_label = 5702; 1990 dev_ok = B_TRUE; 1991 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1992 cidp->pci_type = BGE_PCI; 1993 break; 1994 1995 case DEVICE_ID_5703C: 1996 case DEVICE_ID_5703S: 1997 case DEVICE_ID_5703: 1998 /* 1999 * Revision A0 of the 5703/5793 had various errata 2000 * that we can't or don't work around, so it's not 2001 * supported, but all later versions are 2002 */ 2003 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5793 : 5703; 2004 if (bgep->chipid.asic_rev != MHCR_CHIP_REV_5703_A0) 2005 dev_ok = B_TRUE; 2006 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2007 break; 2008 2009 case DEVICE_ID_5704C: 2010 case DEVICE_ID_5704S: 2011 case DEVICE_ID_5704: 2012 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5794 : 5704; 2013 cidp->mbuf_base = bge_mbuf_pool_base_5704; 2014 cidp->mbuf_length = bge_mbuf_pool_len_5704; 2015 dev_ok = B_TRUE; 2016 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2017 break; 2018 2019 case DEVICE_ID_5705C: 2020 case DEVICE_ID_5705M: 2021 case DEVICE_ID_5705MA3: 2022 case DEVICE_ID_5705F: 2023 case DEVICE_ID_5705_2: 2024 case DEVICE_ID_5754: 2025 if (cidp->device == DEVICE_ID_5754) { 2026 cidp->chip_label = 5754; 2027 cidp->pci_type = BGE_PCI_E; 2028 } else { 2029 cidp->chip_label = 5705; 2030 cidp->pci_type = BGE_PCI; 2031 } 2032 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2033 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2034 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2035 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2036 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2037 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2038 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2039 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2040 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2041 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2042 cidp->statistic_type = BGE_STAT_REG; 2043 dev_ok = B_TRUE; 2044 break; 2045 2046 case DEVICE_ID_5906: 2047 case DEVICE_ID_5906M: 2048 cidp->chip_label = 5906; 2049 cidp->pci_type = BGE_PCI_E; 2050 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5906; 2051 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5906; 2052 cidp->mbuf_hi_water = MBUF_HIWAT_5906; 2053 cidp->mbuf_base = bge_mbuf_pool_base; 2054 cidp->mbuf_length = bge_mbuf_pool_len; 2055 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2056 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2057 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2058 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2059 cidp->statistic_type = BGE_STAT_REG; 2060 dev_ok = B_TRUE; 2061 break; 2062 2063 case DEVICE_ID_5753: 2064 cidp->chip_label = 5753; 2065 cidp->pci_type = BGE_PCI_E; 2066 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2067 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2068 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2069 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2070 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2071 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2072 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2073 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2074 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2075 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2076 cidp->statistic_type = BGE_STAT_REG; 2077 dev_ok = B_TRUE; 2078 break; 2079 2080 case DEVICE_ID_5755: 2081 case DEVICE_ID_5755M: 2082 cidp->chip_label = 5755; 2083 cidp->pci_type = BGE_PCI_E; 2084 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2085 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2086 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2087 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2088 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2089 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2090 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2091 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2092 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2093 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2094 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2095 cidp->statistic_type = BGE_STAT_REG; 2096 dev_ok = B_TRUE; 2097 break; 2098 2099 case DEVICE_ID_5756M: 2100 /* 2101 * This is nearly identical to the 5755M. 2102 * (Actually reports the 5755 chip ID.) 2103 */ 2104 cidp->chip_label = 5756; 2105 cidp->pci_type = BGE_PCI_E; 2106 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2107 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2108 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2109 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2110 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2111 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2112 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2113 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2114 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2115 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2116 cidp->statistic_type = BGE_STAT_REG; 2117 dev_ok = B_TRUE; 2118 break; 2119 2120 case DEVICE_ID_5787: 2121 case DEVICE_ID_5787M: 2122 cidp->chip_label = 5787; 2123 cidp->pci_type = BGE_PCI_E; 2124 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2125 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2126 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2127 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2128 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2129 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2130 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2131 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2132 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2133 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2134 cidp->statistic_type = BGE_STAT_REG; 2135 dev_ok = B_TRUE; 2136 break; 2137 2138 case DEVICE_ID_5723: 2139 cidp->chip_label = 5723; 2140 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2141 cidp->msi_enabled = bge_enable_msi; 2142 cidp->pci_type = BGE_PCI_E; 2143 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2144 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2145 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2146 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2147 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2148 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2149 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2150 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2151 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2152 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2153 cidp->statistic_type = BGE_STAT_REG; 2154 dev_ok = B_TRUE; 2155 break; 2156 2157 case DEVICE_ID_5780: 2158 cidp->chip_label = 5780; 2159 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2160 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2161 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2162 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2163 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2164 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2165 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2166 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2167 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2168 cidp->statistic_type = BGE_STAT_REG; 2169 cidp->pci_type = BGE_PCI; 2170 dev_ok = B_TRUE; 2171 break; 2172 2173 case DEVICE_ID_5782: 2174 /* 2175 * Apart from the label, we treat this as a 5705(?) 2176 */ 2177 cidp->chip_label = 5782; 2178 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2179 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2180 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2181 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2182 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2183 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2184 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2185 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2186 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2187 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2188 cidp->statistic_type = BGE_STAT_REG; 2189 dev_ok = B_TRUE; 2190 break; 2191 2192 case DEVICE_ID_5788: 2193 /* 2194 * Apart from the label, we treat this as a 5705(?) 2195 */ 2196 cidp->chip_label = 5788; 2197 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2198 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2199 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2200 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2201 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2202 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2203 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2204 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2205 cidp->statistic_type = BGE_STAT_REG; 2206 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2207 dev_ok = B_TRUE; 2208 break; 2209 2210 case DEVICE_ID_5714C: 2211 if (cidp->revision >= REVISION_ID_5714_A2) 2212 cidp->msi_enabled = bge_enable_msi; 2213 /* FALLTHRU */ 2214 case DEVICE_ID_5714S: 2215 cidp->chip_label = 5714; 2216 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2217 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2218 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2219 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2220 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2221 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2222 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5714; 2223 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2224 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2225 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2226 cidp->pci_type = BGE_PCI_E; 2227 cidp->statistic_type = BGE_STAT_REG; 2228 dev_ok = B_TRUE; 2229 break; 2230 2231 case DEVICE_ID_5715C: 2232 case DEVICE_ID_5715S: 2233 cidp->chip_label = 5715; 2234 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2235 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2236 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2237 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2238 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2239 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2240 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5715; 2241 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2242 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2243 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2244 cidp->pci_type = BGE_PCI_E; 2245 cidp->statistic_type = BGE_STAT_REG; 2246 if (cidp->revision >= REVISION_ID_5715_A2) 2247 cidp->msi_enabled = bge_enable_msi; 2248 dev_ok = B_TRUE; 2249 break; 2250 2251 case DEVICE_ID_5721: 2252 cidp->chip_label = 5721; 2253 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2254 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2255 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2256 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2257 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2258 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2259 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2260 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2261 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2262 cidp->pci_type = BGE_PCI_E; 2263 cidp->statistic_type = BGE_STAT_REG; 2264 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2265 dev_ok = B_TRUE; 2266 break; 2267 2268 case DEVICE_ID_5722: 2269 cidp->chip_label = 5722; 2270 cidp->pci_type = BGE_PCI_E; 2271 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2272 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2273 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2274 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2275 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2276 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2277 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2278 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2279 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2280 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2281 cidp->statistic_type = BGE_STAT_REG; 2282 dev_ok = B_TRUE; 2283 break; 2284 2285 case DEVICE_ID_5751: 2286 case DEVICE_ID_5751M: 2287 cidp->chip_label = 5751; 2288 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2289 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2290 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2291 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2292 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2293 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2294 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2295 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2296 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2297 cidp->pci_type = BGE_PCI_E; 2298 cidp->statistic_type = BGE_STAT_REG; 2299 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2300 dev_ok = B_TRUE; 2301 break; 2302 2303 case DEVICE_ID_5752: 2304 case DEVICE_ID_5752M: 2305 cidp->chip_label = 5752; 2306 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2307 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2308 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2309 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2310 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2311 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2312 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2313 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2314 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2315 cidp->pci_type = BGE_PCI_E; 2316 cidp->statistic_type = BGE_STAT_REG; 2317 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2318 dev_ok = B_TRUE; 2319 break; 2320 2321 case DEVICE_ID_5789: 2322 cidp->chip_label = 5789; 2323 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2324 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2325 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2326 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2327 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2328 cidp->tx_rings = BGE_RECV_RINGS_MAX_5705; 2329 cidp->pci_type = BGE_PCI_E; 2330 cidp->statistic_type = BGE_STAT_REG; 2331 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2332 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2333 cidp->msi_enabled = B_TRUE; 2334 dev_ok = B_TRUE; 2335 break; 2336 2337 } 2338 2339 /* 2340 * Setup the default jumbo parameter. 2341 */ 2342 cidp->ethmax_size = ETHERMAX; 2343 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_DEFAULT; 2344 cidp->std_buf_size = BGE_STD_BUFF_SIZE; 2345 2346 /* 2347 * If jumbo is enabled and this kind of chipset supports jumbo feature, 2348 * setup below jumbo specific parameters. 2349 * 2350 * For BCM5714/5715, there is only one standard receive ring. So the 2351 * std buffer size should be set to BGE_JUMBO_BUFF_SIZE when jumbo 2352 * feature is enabled. 2353 */ 2354 if (bge_jumbo_enable && 2355 !(cidp->flags & CHIP_FLAG_NO_JUMBO) && 2356 (cidp->default_mtu > BGE_DEFAULT_MTU) && 2357 (cidp->default_mtu <= BGE_MAXIMUM_MTU)) { 2358 if (DEVICE_5714_SERIES_CHIPSETS(bgep)) { 2359 cidp->mbuf_lo_water_rdma = 2360 RDMA_MBUF_LOWAT_5714_JUMBO; 2361 cidp->mbuf_lo_water_rmac = 2362 MAC_RX_MBUF_LOWAT_5714_JUMBO; 2363 cidp->mbuf_hi_water = MBUF_HIWAT_5714_JUMBO; 2364 cidp->jumbo_slots = 0; 2365 cidp->std_buf_size = BGE_JUMBO_BUFF_SIZE; 2366 } else { 2367 cidp->mbuf_lo_water_rdma = 2368 RDMA_MBUF_LOWAT_JUMBO; 2369 cidp->mbuf_lo_water_rmac = 2370 MAC_RX_MBUF_LOWAT_JUMBO; 2371 cidp->mbuf_hi_water = MBUF_HIWAT_JUMBO; 2372 cidp->jumbo_slots = BGE_JUMBO_SLOTS_USED; 2373 } 2374 cidp->recv_jumbo_size = BGE_JUMBO_BUFF_SIZE; 2375 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_JUMBO; 2376 cidp->ethmax_size = cidp->default_mtu + 2377 sizeof (struct ether_header); 2378 } 2379 2380 /* 2381 * Identify the NV memory type: SEEPROM or Flash? 2382 */ 2383 cidp->nvtype = bge_nvmem_id(bgep); 2384 2385 /* 2386 * Now, we want to check whether this device is part of a 2387 * supported subsystem (e.g., on the motherboard of a Sun 2388 * branded platform). 2389 * 2390 * Rule 1: If the Subsystem Vendor ID is "Sun", then it's OK ;-) 2391 */ 2392 if (cidp->subven == VENDOR_ID_SUN) 2393 sys_ok = B_TRUE; 2394 2395 /* 2396 * Rule 2: If it's on the list on known subsystems, then it's OK. 2397 * Note: 0x14e41647 should *not* appear in the list, but the code 2398 * doesn't enforce that. 2399 */ 2400 err = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, bgep->devinfo, 2401 DDI_PROP_DONTPASS, knownids_propname, &ids, &i); 2402 if (err == DDI_PROP_SUCCESS) { 2403 /* 2404 * Got the list; scan for a matching subsystem vendor/device 2405 */ 2406 subid = (cidp->subven << 16) | cidp->subdev; 2407 while (i--) 2408 if (ids[i] == subid) 2409 sys_ok = B_TRUE; 2410 ddi_prop_free(ids); 2411 } 2412 2413 /* 2414 * Rule 3: If it's a Taco/ENWS motherboard device, then it's OK 2415 * 2416 * Unfortunately, early SunBlade 1500s and 2500s didn't reprogram 2417 * the Subsystem Vendor ID, so it defaults to Broadcom. Therefore, 2418 * we have to check specially for the exact device paths to the 2419 * motherboard devices on those platforms ;-( 2420 * 2421 * Note: we can't just use the "supported-subsystems" mechanism 2422 * above, because the entry would have to be 0x14e41647 -- which 2423 * would then accept *any* plugin card that *didn't* contain a 2424 * (valid) SEEPROM ;-( 2425 */ 2426 sysname = ddi_node_name(ddi_root_node()); 2427 devname = ddi_pathname(bgep->devinfo, buf); 2428 ASSERT(strlen(devname) > 0); 2429 if (strcmp(sysname, "SUNW,Sun-Blade-1500") == 0) /* Taco */ 2430 if (strcmp(devname, "/pci@1f,700000/network@2") == 0) 2431 sys_ok = B_TRUE; 2432 if (strcmp(sysname, "SUNW,Sun-Blade-2500") == 0) /* ENWS */ 2433 if (strcmp(devname, "/pci@1c,600000/network@3") == 0) 2434 sys_ok = B_TRUE; 2435 2436 /* 2437 * Now check what we've discovered: is this truly a supported 2438 * chip on (the motherboard of) a supported platform? 2439 * 2440 * Possible problems here: 2441 * 1) it's a completely unheard-of chip (e.g. 5761) 2442 * 2) it's a recognised but unsupported chip (e.g. 5701, 5703C-A0) 2443 * 3) it's a chip we would support if it were on the motherboard 2444 * of a Sun platform, but this one isn't ;-( 2445 */ 2446 if (cidp->chip_label == 0) 2447 bge_problem(bgep, 2448 "Device 'pci%04x,%04x' not recognized (%d?)", 2449 cidp->vendor, cidp->device, cidp->device); 2450 else if (!dev_ok) 2451 bge_problem(bgep, 2452 "Device 'pci%04x,%04x' (%d) revision %d not supported", 2453 cidp->vendor, cidp->device, cidp->chip_label, 2454 cidp->revision); 2455 #if BGE_DEBUGGING 2456 else if (!sys_ok) 2457 bge_problem(bgep, 2458 "%d-based subsystem 'pci%04x,%04x' not validated", 2459 cidp->chip_label, cidp->subven, cidp->subdev); 2460 #endif 2461 else 2462 cidp->flags |= CHIP_FLAG_SUPPORTED; 2463 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 2464 return (EIO); 2465 return (0); 2466 } 2467 2468 void 2469 bge_chip_msi_trig(bge_t *bgep) 2470 { 2471 uint32_t regval; 2472 2473 regval = bgep->param_msi_cnt<<4; 2474 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, regval); 2475 BGE_DEBUG(("bge_chip_msi_trig:data = %d", regval)); 2476 } 2477 2478 /* 2479 * Various registers that control the chip's internal engines (state 2480 * machines) have a <reset> and <enable> bits (fortunately, in the 2481 * same place in each such register :-). 2482 * 2483 * To reset the state machine, the <reset> bit must be written with 1; 2484 * it will then read back as 1 while the reset is in progress, but 2485 * self-clear to 0 when the reset completes. 2486 * 2487 * To enable a state machine, one must set the <enable> bit, which 2488 * will continue to read back as 0 until the state machine is running. 2489 * 2490 * To disable a state machine, the <enable> bit must be cleared, but 2491 * it will continue to read back as 1 until the state machine actually 2492 * stops. 2493 * 2494 * This routine implements polling for completion of a reset, enable 2495 * or disable operation, returning B_TRUE on success (bit reached the 2496 * required state) or B_FALSE on timeout (200*100us == 20ms). 2497 */ 2498 static boolean_t bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 2499 uint32_t mask, uint32_t val); 2500 #pragma no_inline(bge_chip_poll_engine) 2501 2502 static boolean_t 2503 bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 2504 uint32_t mask, uint32_t val) 2505 { 2506 uint32_t regval; 2507 uint32_t n; 2508 2509 BGE_TRACE(("bge_chip_poll_engine($%p, 0x%lx, 0x%x, 0x%x)", 2510 (void *)bgep, regno, mask, val)); 2511 2512 for (n = 200; n; --n) { 2513 regval = bge_reg_get32(bgep, regno); 2514 if ((regval & mask) == val) 2515 return (B_TRUE); 2516 drv_usecwait(100); 2517 } 2518 2519 bge_fm_ereport(bgep, DDI_FM_DEVICE_NO_RESPONSE); 2520 return (B_FALSE); 2521 } 2522 2523 /* 2524 * Various registers that control the chip's internal engines (state 2525 * machines) have a <reset> bit (fortunately, in the same place in 2526 * each such register :-). To reset the state machine, this bit must 2527 * be written with 1; it will then read back as 1 while the reset is 2528 * in progress, but self-clear to 0 when the reset completes. 2529 * 2530 * This code sets the bit, then polls for it to read back as zero. 2531 * The return value is B_TRUE on success (reset bit cleared itself), 2532 * or B_FALSE if the state machine didn't recover :( 2533 * 2534 * NOTE: the Core reset is similar to other resets, except that we 2535 * can't poll for completion, since the Core reset disables memory 2536 * access! So we just have to assume that it will all complete in 2537 * 100us. See Broadcom document 570X-PG102-R, p102, steps 4-5. 2538 */ 2539 static boolean_t bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno); 2540 #pragma no_inline(bge_chip_reset_engine) 2541 2542 static boolean_t 2543 bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno) 2544 { 2545 uint32_t regval; 2546 uint32_t val32; 2547 2548 regval = bge_reg_get32(bgep, regno); 2549 2550 BGE_TRACE(("bge_chip_reset_engine($%p, 0x%lx)", 2551 (void *)bgep, regno)); 2552 BGE_DEBUG(("bge_chip_reset_engine: 0x%lx before reset = 0x%08x", 2553 regno, regval)); 2554 2555 regval |= STATE_MACHINE_RESET_BIT; 2556 2557 switch (regno) { 2558 case MISC_CONFIG_REG: 2559 /* 2560 * BCM5714/5721/5751 pcie chip special case. In order to avoid 2561 * resetting PCIE block and bringing PCIE link down, bit 29 2562 * in the register needs to be set first, and then set it again 2563 * while the reset bit is written. 2564 * See:P500 of 57xx-PG102-RDS.pdf. 2565 */ 2566 if (DEVICE_5705_SERIES_CHIPSETS(bgep)|| 2567 DEVICE_5721_SERIES_CHIPSETS(bgep)|| 2568 DEVICE_5723_SERIES_CHIPSETS(bgep)|| 2569 DEVICE_5714_SERIES_CHIPSETS(bgep)|| 2570 DEVICE_5906_SERIES_CHIPSETS(bgep)) { 2571 regval |= MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE; 2572 if (bgep->chipid.pci_type == BGE_PCI_E) { 2573 if (bgep->chipid.asic_rev == 2574 MHCR_CHIP_REV_5751_A0 || 2575 bgep->chipid.asic_rev == 2576 MHCR_CHIP_REV_5721_A0 || 2577 bgep->chipid.asic_rev == 2578 MHCR_CHIP_REV_5755_A0) { 2579 val32 = bge_reg_get32(bgep, 2580 PHY_TEST_CTRL_REG); 2581 if (val32 == (PHY_PCIE_SCRAM_MODE | 2582 PHY_PCIE_LTASS_MODE)) 2583 bge_reg_put32(bgep, 2584 PHY_TEST_CTRL_REG, 2585 PHY_PCIE_SCRAM_MODE); 2586 val32 = pci_config_get32 2587 (bgep->cfg_handle, 2588 PCI_CONF_BGE_CLKCTL); 2589 val32 |= CLKCTL_PCIE_A0_FIX; 2590 pci_config_put32(bgep->cfg_handle, 2591 PCI_CONF_BGE_CLKCTL, val32); 2592 } 2593 bge_reg_set32(bgep, regno, 2594 MISC_CONFIG_GRC_RESET_DISABLE); 2595 regval |= MISC_CONFIG_GRC_RESET_DISABLE; 2596 } 2597 } 2598 2599 /* 2600 * Special case - causes Core reset 2601 * 2602 * On SPARC v9 we want to ensure that we don't start 2603 * timing until the I/O access has actually reached 2604 * the chip, otherwise we might make the next access 2605 * too early. And we can't just force the write out 2606 * by following it with a read (even to config space) 2607 * because that would cause the fault we're trying 2608 * to avoid. Hence the need for membar_sync() here. 2609 */ 2610 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), regval); 2611 #ifdef __sparcv9 2612 membar_sync(); 2613 #endif /* __sparcv9 */ 2614 /* 2615 * On some platforms,system need about 300us for 2616 * link setup. 2617 */ 2618 drv_usecwait(300); 2619 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) { 2620 bge_reg_set32(bgep, VCPU_STATUS_REG, VCPU_DRV_RESET); 2621 bge_reg_clr32( 2622 bgep, VCPU_EXT_CTL, VCPU_EXT_CTL_HALF); 2623 } 2624 2625 if (bgep->chipid.pci_type == BGE_PCI_E) { 2626 /* PCI-E device need more reset time */ 2627 drv_usecwait(120000); 2628 2629 /* Set PCIE max payload size and clear error status. */ 2630 if ((bgep->chipid.chip_label == 5721) || 2631 (bgep->chipid.chip_label == 5751) || 2632 (bgep->chipid.chip_label == 5752) || 2633 (bgep->chipid.chip_label == 5789) || 2634 (bgep->chipid.chip_label == 5906)) { 2635 pci_config_put16(bgep->cfg_handle, 2636 PCI_CONF_DEV_CTRL, READ_REQ_SIZE_MAX); 2637 pci_config_put16(bgep->cfg_handle, 2638 PCI_CONF_DEV_STUS, DEVICE_ERROR_STUS); 2639 } 2640 2641 if (bgep->chipid.chip_label == 5723) { 2642 pci_config_put16(bgep->cfg_handle, 2643 PCI_CONF_DEV_CTRL_5723, READ_REQ_SIZE_MAX); 2644 pci_config_put16(bgep->cfg_handle, 2645 PCI_CONF_DEV_STUS_5723, DEVICE_ERROR_STUS); 2646 } 2647 } 2648 2649 BGE_PCICHK(bgep); 2650 return (B_TRUE); 2651 2652 default: 2653 bge_reg_put32(bgep, regno, regval); 2654 return (bge_chip_poll_engine(bgep, regno, 2655 STATE_MACHINE_RESET_BIT, 0)); 2656 } 2657 } 2658 2659 /* 2660 * Various registers that control the chip's internal engines (state 2661 * machines) have an <enable> bit (fortunately, in the same place in 2662 * each such register :-). To stop the state machine, this bit must 2663 * be written with 0, then polled to see when the state machine has 2664 * actually stopped. 2665 * 2666 * The return value is B_TRUE on success (enable bit cleared), or 2667 * B_FALSE if the state machine didn't stop :( 2668 */ 2669 static boolean_t bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, 2670 uint32_t morebits); 2671 #pragma no_inline(bge_chip_disable_engine) 2672 2673 static boolean_t 2674 bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 2675 { 2676 uint32_t regval; 2677 2678 BGE_TRACE(("bge_chip_disable_engine($%p, 0x%lx, 0x%x)", 2679 (void *)bgep, regno, morebits)); 2680 2681 switch (regno) { 2682 case FTQ_RESET_REG: 2683 /* 2684 * For Schumacher's bugfix CR6490108 2685 */ 2686 #ifdef BGE_IPMI_ASF 2687 #ifdef BGE_NETCONSOLE 2688 if (bgep->asf_enabled) 2689 return (B_TRUE); 2690 #endif 2691 #endif 2692 /* 2693 * Not quite like the others; it doesn't 2694 * have an <enable> bit, but instead we 2695 * have to set and then clear all the bits 2696 */ 2697 bge_reg_put32(bgep, regno, ~(uint32_t)0); 2698 drv_usecwait(100); 2699 bge_reg_put32(bgep, regno, 0); 2700 return (B_TRUE); 2701 2702 default: 2703 regval = bge_reg_get32(bgep, regno); 2704 regval &= ~STATE_MACHINE_ENABLE_BIT; 2705 regval &= ~morebits; 2706 bge_reg_put32(bgep, regno, regval); 2707 return (bge_chip_poll_engine(bgep, regno, 2708 STATE_MACHINE_ENABLE_BIT, 0)); 2709 } 2710 } 2711 2712 /* 2713 * Various registers that control the chip's internal engines (state 2714 * machines) have an <enable> bit (fortunately, in the same place in 2715 * each such register :-). To start the state machine, this bit must 2716 * be written with 1, then polled to see when the state machine has 2717 * actually started. 2718 * 2719 * The return value is B_TRUE on success (enable bit set), or 2720 * B_FALSE if the state machine didn't start :( 2721 */ 2722 static boolean_t bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, 2723 uint32_t morebits); 2724 #pragma no_inline(bge_chip_enable_engine) 2725 2726 static boolean_t 2727 bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 2728 { 2729 uint32_t regval; 2730 2731 BGE_TRACE(("bge_chip_enable_engine($%p, 0x%lx, 0x%x)", 2732 (void *)bgep, regno, morebits)); 2733 2734 switch (regno) { 2735 case FTQ_RESET_REG: 2736 #ifdef BGE_IPMI_ASF 2737 #ifdef BGE_NETCONSOLE 2738 if (bgep->asf_enabled) 2739 return (B_TRUE); 2740 #endif 2741 #endif 2742 /* 2743 * Not quite like the others; it doesn't 2744 * have an <enable> bit, but instead we 2745 * have to set and then clear all the bits 2746 */ 2747 bge_reg_put32(bgep, regno, ~(uint32_t)0); 2748 drv_usecwait(100); 2749 bge_reg_put32(bgep, regno, 0); 2750 return (B_TRUE); 2751 2752 default: 2753 regval = bge_reg_get32(bgep, regno); 2754 regval |= STATE_MACHINE_ENABLE_BIT; 2755 regval |= morebits; 2756 bge_reg_put32(bgep, regno, regval); 2757 return (bge_chip_poll_engine(bgep, regno, 2758 STATE_MACHINE_ENABLE_BIT, STATE_MACHINE_ENABLE_BIT)); 2759 } 2760 } 2761 2762 /* 2763 * Reprogram the Ethernet, Transmit, and Receive MAC 2764 * modes to match the param_* variables 2765 */ 2766 void bge_sync_mac_modes(bge_t *bgep); 2767 #pragma no_inline(bge_sync_mac_modes) 2768 2769 void 2770 bge_sync_mac_modes(bge_t *bgep) 2771 { 2772 uint32_t macmode; 2773 uint32_t regval; 2774 2775 ASSERT(mutex_owned(bgep->genlock)); 2776 2777 /* 2778 * Reprogram the Ethernet MAC mode ... 2779 */ 2780 macmode = regval = bge_reg_get32(bgep, ETHERNET_MAC_MODE_REG); 2781 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 2782 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) 2783 if (DEVICE_5714_SERIES_CHIPSETS(bgep)) 2784 macmode |= ETHERNET_MODE_LINK_POLARITY; 2785 else 2786 macmode &= ~ETHERNET_MODE_LINK_POLARITY; 2787 else 2788 macmode |= ETHERNET_MODE_LINK_POLARITY; 2789 macmode &= ~ETHERNET_MODE_PORTMODE_MASK; 2790 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 2791 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) { 2792 if (DEVICE_5714_SERIES_CHIPSETS(bgep)) 2793 macmode |= ETHERNET_MODE_PORTMODE_GMII; 2794 else 2795 macmode |= ETHERNET_MODE_PORTMODE_TBI; 2796 } else if (bgep->param_link_speed == 10 || 2797 bgep->param_link_speed == 100) 2798 macmode |= ETHERNET_MODE_PORTMODE_MII; 2799 else 2800 macmode |= ETHERNET_MODE_PORTMODE_GMII; 2801 if (bgep->param_link_duplex == LINK_DUPLEX_HALF) 2802 macmode |= ETHERNET_MODE_HALF_DUPLEX; 2803 else 2804 macmode &= ~ETHERNET_MODE_HALF_DUPLEX; 2805 if (bgep->param_loop_mode == BGE_LOOP_INTERNAL_MAC) 2806 macmode |= ETHERNET_MODE_MAC_LOOPBACK; 2807 else 2808 macmode &= ~ETHERNET_MODE_MAC_LOOPBACK; 2809 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, macmode); 2810 BGE_DEBUG(("bge_sync_mac_modes($%p) Ethernet MAC mode 0x%x => 0x%x", 2811 (void *)bgep, regval, macmode)); 2812 2813 /* 2814 * ... the Transmit MAC mode ... 2815 */ 2816 macmode = regval = bge_reg_get32(bgep, TRANSMIT_MAC_MODE_REG); 2817 if (bgep->param_link_tx_pause) 2818 macmode |= TRANSMIT_MODE_FLOW_CONTROL; 2819 else 2820 macmode &= ~TRANSMIT_MODE_FLOW_CONTROL; 2821 bge_reg_put32(bgep, TRANSMIT_MAC_MODE_REG, macmode); 2822 BGE_DEBUG(("bge_sync_mac_modes($%p) Transmit MAC mode 0x%x => 0x%x", 2823 (void *)bgep, regval, macmode)); 2824 2825 /* 2826 * ... and the Receive MAC mode 2827 */ 2828 macmode = regval = bge_reg_get32(bgep, RECEIVE_MAC_MODE_REG); 2829 if (bgep->param_link_rx_pause) 2830 macmode |= RECEIVE_MODE_FLOW_CONTROL; 2831 else 2832 macmode &= ~RECEIVE_MODE_FLOW_CONTROL; 2833 bge_reg_put32(bgep, RECEIVE_MAC_MODE_REG, macmode); 2834 BGE_DEBUG(("bge_sync_mac_modes($%p) Receive MAC mode 0x%x => 0x%x", 2835 (void *)bgep, regval, macmode)); 2836 } 2837 2838 /* 2839 * bge_chip_sync() -- program the chip with the unicast MAC address, 2840 * the multicast hash table, the required level of promiscuity, and 2841 * the current loopback mode ... 2842 */ 2843 #ifdef BGE_IPMI_ASF 2844 int bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive); 2845 #else 2846 int bge_chip_sync(bge_t *bgep); 2847 #endif 2848 #pragma no_inline(bge_chip_sync) 2849 2850 int 2851 #ifdef BGE_IPMI_ASF 2852 bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive) 2853 #else 2854 bge_chip_sync(bge_t *bgep) 2855 #endif 2856 { 2857 void (*opfn)(bge_t *bgep, bge_regno_t reg, uint32_t bits); 2858 boolean_t promisc; 2859 uint64_t macaddr; 2860 uint32_t fill = 0; 2861 int i, j; 2862 int retval = DDI_SUCCESS; 2863 2864 BGE_TRACE(("bge_chip_sync($%p)", 2865 (void *)bgep)); 2866 2867 ASSERT(mutex_owned(bgep->genlock)); 2868 2869 promisc = B_FALSE; 2870 fill = ~(uint32_t)0; 2871 2872 if (bgep->promisc) 2873 promisc = B_TRUE; 2874 else 2875 fill = (uint32_t)0; 2876 2877 /* 2878 * If the TX/RX MAC engines are already running, we should stop 2879 * them (and reset the RX engine) before changing the parameters. 2880 * If they're not running, this will have no effect ... 2881 * 2882 * NOTE: this is currently disabled by default because stopping 2883 * and restarting the Tx engine may cause an outgoing packet in 2884 * transit to be truncated. Also, stopping and restarting the 2885 * Rx engine seems to not work correctly on the 5705. Testing 2886 * has not (yet!) revealed any problems with NOT stopping and 2887 * restarting these engines (and Broadcom say their drivers don't 2888 * do this), but if it is found to cause problems, this variable 2889 * can be patched to re-enable the old behaviour ... 2890 */ 2891 if (bge_stop_start_on_sync) { 2892 #ifdef BGE_IPMI_ASF 2893 if (!bgep->asf_enabled) { 2894 if (!bge_chip_disable_engine(bgep, 2895 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG)) 2896 retval = DDI_FAILURE; 2897 } else { 2898 if (!bge_chip_disable_engine(bgep, 2899 RECEIVE_MAC_MODE_REG, 0)) 2900 retval = DDI_FAILURE; 2901 } 2902 #else 2903 if (!bge_chip_disable_engine(bgep, RECEIVE_MAC_MODE_REG, 2904 RECEIVE_MODE_KEEP_VLAN_TAG)) 2905 retval = DDI_FAILURE; 2906 #endif 2907 if (!bge_chip_disable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 2908 retval = DDI_FAILURE; 2909 if (!bge_chip_reset_engine(bgep, RECEIVE_MAC_MODE_REG)) 2910 retval = DDI_FAILURE; 2911 } 2912 2913 /* 2914 * Reprogram the hashed multicast address table ... 2915 */ 2916 for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i) 2917 bge_reg_put32(bgep, MAC_HASH_REG(i), 0); 2918 2919 for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i) 2920 bge_reg_put32(bgep, MAC_HASH_REG(i), 2921 bgep->mcast_hash[i] | fill); 2922 2923 #ifdef BGE_IPMI_ASF 2924 if (!bgep->asf_enabled || !asf_keeplive) { 2925 #endif 2926 /* 2927 * Transform the MAC address(es) from host to chip format, then 2928 * reprogram the transmit random backoff seed and the unicast 2929 * MAC address(es) ... 2930 */ 2931 for (j = 0; j < MAC_ADDRESS_REGS_MAX; j++) { 2932 for (i = 0, macaddr = 0ull; 2933 i < ETHERADDRL; ++i) { 2934 macaddr <<= 8; 2935 macaddr |= bgep->curr_addr[j].addr[i]; 2936 } 2937 fill += (macaddr >> 16) + (macaddr & 0xffffffff); 2938 bge_reg_put64(bgep, MAC_ADDRESS_REG(j), macaddr); 2939 2940 BGE_DEBUG(("bge_chip_sync($%p) " 2941 "setting MAC address %012llx", 2942 (void *)bgep, macaddr)); 2943 } 2944 #ifdef BGE_IPMI_ASF 2945 } 2946 #endif 2947 /* 2948 * Set random seed of backoff interval 2949 * - Writing zero means no backoff interval 2950 */ 2951 fill = ((fill >> 20) + (fill >> 10) + fill) & 0x3ff; 2952 if (fill == 0) 2953 fill = 1; 2954 bge_reg_put32(bgep, MAC_TX_RANDOM_BACKOFF_REG, fill); 2955 2956 /* 2957 * Set or clear the PROMISCUOUS mode bit 2958 */ 2959 opfn = promisc ? bge_reg_set32 : bge_reg_clr32; 2960 (*opfn)(bgep, RECEIVE_MAC_MODE_REG, RECEIVE_MODE_PROMISCUOUS); 2961 2962 /* 2963 * Sync the rest of the MAC modes too ... 2964 */ 2965 bge_sync_mac_modes(bgep); 2966 2967 /* 2968 * Restart RX/TX MAC engines if required ... 2969 */ 2970 if (bgep->bge_chip_state == BGE_CHIP_RUNNING) { 2971 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 2972 retval = DDI_FAILURE; 2973 #ifdef BGE_IPMI_ASF 2974 if (!bgep->asf_enabled) { 2975 if (!bge_chip_enable_engine(bgep, 2976 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG)) 2977 retval = DDI_FAILURE; 2978 } else { 2979 if (!bge_chip_enable_engine(bgep, 2980 RECEIVE_MAC_MODE_REG, 0)) 2981 retval = DDI_FAILURE; 2982 } 2983 #else 2984 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 2985 RECEIVE_MODE_KEEP_VLAN_TAG)) 2986 retval = DDI_FAILURE; 2987 #endif 2988 } 2989 return (retval); 2990 } 2991 2992 /* 2993 * This array defines the sequence of state machine control registers 2994 * in which the <enable> bit must be cleared to bring the chip to a 2995 * clean stop. Taken from Broadcom document 570X-PG102-R, p116. 2996 */ 2997 static bge_regno_t shutdown_engine_regs[] = { 2998 RECEIVE_MAC_MODE_REG, 2999 RCV_BD_INITIATOR_MODE_REG, 3000 RCV_LIST_PLACEMENT_MODE_REG, 3001 RCV_LIST_SELECTOR_MODE_REG, /* BCM5704 series only */ 3002 RCV_DATA_BD_INITIATOR_MODE_REG, 3003 RCV_DATA_COMPLETION_MODE_REG, 3004 RCV_BD_COMPLETION_MODE_REG, 3005 3006 SEND_BD_SELECTOR_MODE_REG, 3007 SEND_BD_INITIATOR_MODE_REG, 3008 SEND_DATA_INITIATOR_MODE_REG, 3009 READ_DMA_MODE_REG, 3010 SEND_DATA_COMPLETION_MODE_REG, 3011 DMA_COMPLETION_MODE_REG, /* BCM5704 series only */ 3012 SEND_BD_COMPLETION_MODE_REG, 3013 TRANSMIT_MAC_MODE_REG, 3014 3015 HOST_COALESCE_MODE_REG, 3016 WRITE_DMA_MODE_REG, 3017 MBUF_CLUSTER_FREE_MODE_REG, /* BCM5704 series only */ 3018 FTQ_RESET_REG, /* special - see code */ 3019 BUFFER_MANAGER_MODE_REG, /* BCM5704 series only */ 3020 MEMORY_ARBITER_MODE_REG, /* BCM5704 series only */ 3021 BGE_REGNO_NONE /* terminator */ 3022 }; 3023 3024 #ifndef __sparc 3025 static bge_regno_t quiesce_regs[] = { 3026 READ_DMA_MODE_REG, 3027 DMA_COMPLETION_MODE_REG, 3028 WRITE_DMA_MODE_REG, 3029 BGE_REGNO_NONE 3030 }; 3031 3032 void bge_chip_stop_nonblocking(bge_t *bgep); 3033 #pragma no_inline(bge_chip_stop_nonblocking) 3034 3035 /* 3036 * This function is called by bge_quiesce(). We 3037 * turn off all the DMA engines here. 3038 */ 3039 void 3040 bge_chip_stop_nonblocking(bge_t *bgep) 3041 { 3042 bge_regno_t *rbp; 3043 3044 /* 3045 * Flag that no more activity may be initiated 3046 */ 3047 bgep->progress &= ~PROGRESS_READY; 3048 3049 rbp = quiesce_regs; 3050 while (*rbp != BGE_REGNO_NONE) { 3051 (void) bge_chip_disable_engine(bgep, *rbp, 0); 3052 ++rbp; 3053 } 3054 3055 bgep->bge_chip_state = BGE_CHIP_STOPPED; 3056 } 3057 3058 #endif 3059 3060 /* 3061 * bge_chip_stop() -- stop all chip processing 3062 * 3063 * If the <fault> parameter is B_TRUE, we're stopping the chip because 3064 * we've detected a problem internally; otherwise, this is a normal 3065 * (clean) stop (at user request i.e. the last STREAM has been closed). 3066 */ 3067 void bge_chip_stop(bge_t *bgep, boolean_t fault); 3068 #pragma no_inline(bge_chip_stop) 3069 3070 void 3071 bge_chip_stop(bge_t *bgep, boolean_t fault) 3072 { 3073 bge_regno_t regno; 3074 bge_regno_t *rbp; 3075 boolean_t ok; 3076 3077 BGE_TRACE(("bge_chip_stop($%p)", 3078 (void *)bgep)); 3079 3080 ASSERT(mutex_owned(bgep->genlock)); 3081 3082 rbp = shutdown_engine_regs; 3083 /* 3084 * When driver try to shutdown the BCM5705/5788/5721/5751/ 3085 * 5752/5714 and 5715 chipsets,the buffer manager and the mem 3086 * -ory arbiter should not be disabled. 3087 */ 3088 for (ok = B_TRUE; (regno = *rbp) != BGE_REGNO_NONE; ++rbp) { 3089 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3090 ok &= bge_chip_disable_engine(bgep, regno, 0); 3091 else if ((regno != RCV_LIST_SELECTOR_MODE_REG) && 3092 (regno != DMA_COMPLETION_MODE_REG) && 3093 (regno != MBUF_CLUSTER_FREE_MODE_REG)&& 3094 (regno != BUFFER_MANAGER_MODE_REG) && 3095 (regno != MEMORY_ARBITER_MODE_REG)) 3096 ok &= bge_chip_disable_engine(bgep, 3097 regno, 0); 3098 } 3099 3100 if (!ok && !fault) 3101 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 3102 3103 /* 3104 * Finally, disable (all) MAC events & clear the MAC status 3105 */ 3106 bge_reg_put32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 0); 3107 bge_reg_put32(bgep, ETHERNET_MAC_STATUS_REG, ~0); 3108 3109 /* 3110 * if we're stopping the chip because of a detected fault then do 3111 * appropriate actions 3112 */ 3113 if (fault) { 3114 if (bgep->bge_chip_state != BGE_CHIP_FAULT) { 3115 bgep->bge_chip_state = BGE_CHIP_FAULT; 3116 if (!bgep->manual_reset) 3117 ddi_fm_service_impact(bgep->devinfo, 3118 DDI_SERVICE_LOST); 3119 if (bgep->bge_dma_error) { 3120 /* 3121 * need to free buffers in case the fault was 3122 * due to a memory error in a buffer - got to 3123 * do a fair bit of tidying first 3124 */ 3125 if (bgep->progress & PROGRESS_KSTATS) { 3126 bge_fini_kstats(bgep); 3127 bgep->progress &= ~PROGRESS_KSTATS; 3128 } 3129 if (bgep->progress & PROGRESS_INTR) { 3130 bge_intr_disable(bgep); 3131 rw_enter(bgep->errlock, RW_WRITER); 3132 bge_fini_rings(bgep); 3133 rw_exit(bgep->errlock); 3134 bgep->progress &= ~PROGRESS_INTR; 3135 } 3136 if (bgep->progress & PROGRESS_BUFS) { 3137 bge_free_bufs(bgep); 3138 bgep->progress &= ~PROGRESS_BUFS; 3139 } 3140 bgep->bge_dma_error = B_FALSE; 3141 } 3142 } 3143 } else 3144 bgep->bge_chip_state = BGE_CHIP_STOPPED; 3145 } 3146 3147 /* 3148 * Poll for completion of chip's ROM firmware; also, at least on the 3149 * first time through, find and return the hardware MAC address, if any. 3150 */ 3151 static uint64_t bge_poll_firmware(bge_t *bgep); 3152 #pragma no_inline(bge_poll_firmware) 3153 3154 static uint64_t 3155 bge_poll_firmware(bge_t *bgep) 3156 { 3157 uint64_t magic; 3158 uint64_t mac; 3159 uint32_t gen, val; 3160 uint32_t i; 3161 3162 /* 3163 * Step 19: poll for firmware completion (GENCOMM port set 3164 * to the ones complement of T3_MAGIC_NUMBER). 3165 * 3166 * While we're at it, we also read the MAC address register; 3167 * at some stage the firmware will load this with the 3168 * factory-set value. 3169 * 3170 * When both the magic number and the MAC address are set, 3171 * we're done; but we impose a time limit of one second 3172 * (1000*1000us) in case the firmware fails in some fashion 3173 * or the SEEPROM that provides that MAC address isn't fitted. 3174 * 3175 * After the first time through (chip state != INITIAL), we 3176 * don't need the MAC address to be set (we've already got it 3177 * or not, from the first time), so we don't wait for it, but 3178 * we still have to wait for the T3_MAGIC_NUMBER. 3179 * 3180 * Note: the magic number is only a 32-bit quantity, but the NIC 3181 * memory is 64-bit (and big-endian) internally. Addressing the 3182 * GENCOMM word as "the upper half of a 64-bit quantity" makes 3183 * it work correctly on both big- and little-endian hosts. 3184 */ 3185 if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) == 3186 MHCR_CHIP_ASIC_REV_5906) { 3187 for (i = 0; i < 1000; ++i) { 3188 drv_usecwait(1000); 3189 val = bge_reg_get32(bgep, VCPU_STATUS_REG); 3190 if (val & VCPU_INIT_DONE) 3191 break; 3192 } 3193 BGE_DEBUG(("bge_poll_firmware($%p): return after %d loops", 3194 (void *)bgep, i)); 3195 mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0)); 3196 } else { 3197 for (i = 0; i < 1000; ++i) { 3198 drv_usecwait(1000); 3199 gen = bge_nic_get64(bgep, NIC_MEM_GENCOMM) >> 32; 3200 if (i == 0 && DEVICE_5704_SERIES_CHIPSETS(bgep)) 3201 drv_usecwait(100000); 3202 mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0)); 3203 #ifdef BGE_IPMI_ASF 3204 if (!bgep->asf_enabled) { 3205 #endif 3206 if (gen != ~T3_MAGIC_NUMBER) 3207 continue; 3208 #ifdef BGE_IPMI_ASF 3209 } 3210 #endif 3211 if (mac != 0ULL) 3212 break; 3213 if (bgep->bge_chip_state != BGE_CHIP_INITIAL) 3214 break; 3215 } 3216 } 3217 3218 magic = bge_nic_get64(bgep, NIC_MEM_GENCOMM); 3219 BGE_DEBUG(("bge_poll_firmware($%p): PXE magic 0x%x after %d loops", 3220 (void *)bgep, gen, i)); 3221 BGE_DEBUG(("bge_poll_firmware: MAC %016llx, GENCOMM %016llx", 3222 mac, magic)); 3223 3224 return (mac); 3225 } 3226 3227 /* 3228 * Maximum times of trying to get the NVRAM access lock 3229 * by calling bge_nvmem_acquire() 3230 */ 3231 #define MAX_TRY_NVMEM_ACQUIRE 10000 3232 3233 #ifdef BGE_IPMI_ASF 3234 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode); 3235 #else 3236 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma); 3237 #endif 3238 #pragma no_inline(bge_chip_reset) 3239 3240 int 3241 #ifdef BGE_IPMI_ASF 3242 bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode) 3243 #else 3244 bge_chip_reset(bge_t *bgep, boolean_t enable_dma) 3245 #endif 3246 { 3247 chip_id_t chipid; 3248 uint64_t mac; 3249 uint64_t magic; 3250 uint32_t modeflags; 3251 uint32_t mhcr; 3252 uint32_t sx0; 3253 uint32_t i, tries; 3254 #ifdef BGE_IPMI_ASF 3255 uint32_t mailbox; 3256 #endif 3257 int retval = DDI_SUCCESS; 3258 3259 BGE_TRACE(("bge_chip_reset($%p, %d)", 3260 (void *)bgep, enable_dma)); 3261 3262 ASSERT(mutex_owned(bgep->genlock)); 3263 3264 BGE_DEBUG(("bge_chip_reset($%p, %d): current state is %d", 3265 (void *)bgep, enable_dma, bgep->bge_chip_state)); 3266 3267 /* 3268 * Do we need to stop the chip cleanly before resetting? 3269 */ 3270 switch (bgep->bge_chip_state) { 3271 default: 3272 _NOTE(NOTREACHED) 3273 return (DDI_FAILURE); 3274 3275 case BGE_CHIP_INITIAL: 3276 case BGE_CHIP_STOPPED: 3277 case BGE_CHIP_RESET: 3278 break; 3279 3280 case BGE_CHIP_RUNNING: 3281 case BGE_CHIP_ERROR: 3282 case BGE_CHIP_FAULT: 3283 bge_chip_stop(bgep, B_FALSE); 3284 break; 3285 } 3286 3287 #ifdef BGE_IPMI_ASF 3288 if (bgep->asf_enabled) { 3289 #ifdef __sparc 3290 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 3291 MHCR_ENABLE_TAGGED_STATUS_MODE | 3292 MHCR_MASK_INTERRUPT_MODE | 3293 MHCR_MASK_PCI_INT_OUTPUT | 3294 MHCR_CLEAR_INTERRUPT_INTA | 3295 MHCR_ENABLE_ENDIAN_WORD_SWAP | 3296 MHCR_ENABLE_ENDIAN_BYTE_SWAP; 3297 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr); 3298 bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG, 3299 bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG) | 3300 MEMORY_ARBITER_ENABLE); 3301 #endif 3302 if (asf_mode == ASF_MODE_INIT) { 3303 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 3304 } else if (asf_mode == ASF_MODE_SHUTDOWN) { 3305 bge_asf_pre_reset_operations(bgep, BGE_SHUTDOWN_RESET); 3306 } 3307 } 3308 #endif 3309 /* 3310 * Adapted from Broadcom document 570X-PG102-R, pp 102-116. 3311 * Updated to reflect Broadcom document 570X-PG104-R, pp 146-159. 3312 * 3313 * Before reset Core clock,it is 3314 * also required to initialize the Memory Arbiter as specified in step9 3315 * and Misc Host Control Register as specified in step-13 3316 * Step 4-5: reset Core clock & wait for completion 3317 * Steps 6-8: are done by bge_chip_cfg_init() 3318 * put the T3_MAGIC_NUMBER into the GENCOMM port before reset 3319 */ 3320 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 3321 retval = DDI_FAILURE; 3322 3323 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 3324 MHCR_ENABLE_TAGGED_STATUS_MODE | 3325 MHCR_MASK_INTERRUPT_MODE | 3326 MHCR_MASK_PCI_INT_OUTPUT | 3327 MHCR_CLEAR_INTERRUPT_INTA; 3328 #ifdef _BIG_ENDIAN 3329 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 3330 #endif /* _BIG_ENDIAN */ 3331 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr); 3332 #ifdef BGE_IPMI_ASF 3333 if (bgep->asf_enabled) 3334 bgep->asf_wordswapped = B_FALSE; 3335 #endif 3336 /* 3337 * NVRAM Corruption Workaround 3338 */ 3339 for (tries = 0; tries < MAX_TRY_NVMEM_ACQUIRE; tries++) 3340 if (bge_nvmem_acquire(bgep) != EAGAIN) 3341 break; 3342 if (tries >= MAX_TRY_NVMEM_ACQUIRE) 3343 BGE_DEBUG(("%s: fail to acquire nvram lock", 3344 bgep->ifname)); 3345 3346 #ifdef BGE_IPMI_ASF 3347 if (!bgep->asf_enabled) { 3348 #endif 3349 magic = (uint64_t)T3_MAGIC_NUMBER << 32; 3350 bge_nic_put64(bgep, NIC_MEM_GENCOMM, magic); 3351 #ifdef BGE_IPMI_ASF 3352 } 3353 #endif 3354 3355 if (!bge_chip_reset_engine(bgep, MISC_CONFIG_REG)) 3356 retval = DDI_FAILURE; 3357 bge_chip_cfg_init(bgep, &chipid, enable_dma); 3358 3359 /* 3360 * Step 8a: This may belong elsewhere, but BCM5721 needs 3361 * a bit set to avoid a fifo overflow/underflow bug. 3362 */ 3363 if ((bgep->chipid.chip_label == 5721) || 3364 (bgep->chipid.chip_label == 5751) || 3365 (bgep->chipid.chip_label == 5752) || 3366 (bgep->chipid.chip_label == 5755) || 3367 (bgep->chipid.chip_label == 5756) || 3368 (bgep->chipid.chip_label == 5789) || 3369 (bgep->chipid.chip_label == 5906)) 3370 bge_reg_set32(bgep, TLP_CONTROL_REG, TLP_DATA_FIFO_PROTECT); 3371 3372 3373 /* 3374 * Step 9: enable MAC memory arbiter,bit30 and bit31 of 5714/5715 should 3375 * not be changed. 3376 */ 3377 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 3378 retval = DDI_FAILURE; 3379 3380 /* 3381 * Steps 10-11: configure PIO endianness options and 3382 * enable indirect register access -- already done 3383 * Steps 12-13: enable writing to the PCI state & clock 3384 * control registers -- not required; we aren't going to 3385 * use those features. 3386 * Steps 14-15: Configure DMA endianness options. See 3387 * the comments on the setting of the MHCR above. 3388 */ 3389 #ifdef _BIG_ENDIAN 3390 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME | 3391 MODE_WORD_SWAP_NONFRAME | MODE_BYTE_SWAP_NONFRAME; 3392 #else 3393 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME; 3394 #endif /* _BIG_ENDIAN */ 3395 #ifdef BGE_IPMI_ASF 3396 if (bgep->asf_enabled) 3397 modeflags |= MODE_HOST_STACK_UP; 3398 #endif 3399 bge_reg_put32(bgep, MODE_CONTROL_REG, modeflags); 3400 3401 #ifdef BGE_IPMI_ASF 3402 if (bgep->asf_enabled) { 3403 #ifdef __sparc 3404 bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG, 3405 MEMORY_ARBITER_ENABLE | 3406 bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG)); 3407 #endif 3408 3409 #ifdef BGE_NETCONSOLE 3410 if (!bgep->asf_newhandshake) { 3411 if ((asf_mode == ASF_MODE_INIT) || 3412 (asf_mode == ASF_MODE_POST_INIT)) { 3413 bge_asf_post_reset_old_mode(bgep, 3414 BGE_INIT_RESET); 3415 } else { 3416 bge_asf_post_reset_old_mode(bgep, 3417 BGE_SHUTDOWN_RESET); 3418 } 3419 } 3420 #endif 3421 3422 /* Wait for NVRAM init */ 3423 i = 0; 3424 drv_usecwait(5000); 3425 mailbox = bge_nic_get32(bgep, BGE_FIRMWARE_MAILBOX); 3426 3427 while ((mailbox != (uint32_t) 3428 ~BGE_MAGIC_NUM_FIRMWARE_INIT_DONE) && 3429 (i < 10000)) { 3430 drv_usecwait(100); 3431 mailbox = bge_nic_get32(bgep, 3432 BGE_FIRMWARE_MAILBOX); 3433 i++; 3434 } 3435 3436 #ifndef BGE_NETCONSOLE 3437 if (!bgep->asf_newhandshake) { 3438 if ((asf_mode == ASF_MODE_INIT) || 3439 (asf_mode == ASF_MODE_POST_INIT)) { 3440 3441 bge_asf_post_reset_old_mode(bgep, 3442 BGE_INIT_RESET); 3443 } else { 3444 bge_asf_post_reset_old_mode(bgep, 3445 BGE_SHUTDOWN_RESET); 3446 } 3447 } 3448 #endif 3449 } 3450 #endif 3451 /* 3452 * Steps 16-17: poll for firmware completion 3453 */ 3454 mac = bge_poll_firmware(bgep); 3455 3456 /* 3457 * Step 18: enable external memory -- doesn't apply. 3458 * 3459 * However we take the opportunity to set the MLCR anyway, as 3460 * this register also controls the SEEPROM auto-access method 3461 * which we may want to use later ... 3462 * 3463 * The proper value here depends on the way the chip is wired 3464 * into the circuit board, as this register *also* controls which 3465 * of the "Miscellaneous I/O" pins are driven as outputs and the 3466 * values driven onto those pins! 3467 * 3468 * See also step 74 in the PRM ... 3469 */ 3470 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, 3471 bgep->chipid.bge_mlcr_default); 3472 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 3473 3474 /* 3475 * Step 20: clear the Ethernet MAC mode register 3476 */ 3477 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, 0); 3478 3479 /* 3480 * Step 21: restore cache-line-size, latency timer, and 3481 * subsystem ID registers to their original values (not 3482 * those read into the local structure <chipid>, 'cos 3483 * that was after they were cleared by the RESET). 3484 * 3485 * Note: the Subsystem Vendor/Device ID registers are not 3486 * directly writable in config space, so we use the shadow 3487 * copy in "Page Zero" of register space to restore them 3488 * both in one go ... 3489 */ 3490 pci_config_put8(bgep->cfg_handle, PCI_CONF_CACHE_LINESZ, 3491 bgep->chipid.clsize); 3492 pci_config_put8(bgep->cfg_handle, PCI_CONF_LATENCY_TIMER, 3493 bgep->chipid.latency); 3494 bge_reg_put32(bgep, PCI_CONF_SUBVENID, 3495 (bgep->chipid.subdev << 16) | bgep->chipid.subven); 3496 3497 /* 3498 * The SEND INDEX registers should be reset to zero by the 3499 * global chip reset; if they're not, there'll be trouble 3500 * later on. 3501 */ 3502 sx0 = bge_reg_get32(bgep, NIC_DIAG_SEND_INDEX_REG(0)); 3503 if (sx0 != 0) { 3504 BGE_REPORT((bgep, "SEND INDEX - device didn't RESET")); 3505 bge_fm_ereport(bgep, DDI_FM_DEVICE_INVAL_STATE); 3506 retval = DDI_FAILURE; 3507 } 3508 3509 /* Enable MSI code */ 3510 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 3511 bge_reg_set32(bgep, MSI_MODE_REG, 3512 MSI_PRI_HIGHEST|MSI_MSI_ENABLE|MSI_ERROR_ATTENTION); 3513 3514 /* 3515 * On the first time through, save the factory-set MAC address 3516 * (if any). If bge_poll_firmware() above didn't return one 3517 * (from a chip register) consider looking in the attached NV 3518 * memory device, if any. Once we have it, we save it in both 3519 * register-image (64-bit) and byte-array forms. All-zero and 3520 * all-one addresses are not valid, and we refuse to stash those. 3521 */ 3522 if (bgep->bge_chip_state == BGE_CHIP_INITIAL) { 3523 if (mac == 0ULL) 3524 mac = bge_get_nvmac(bgep); 3525 if (mac != 0ULL && mac != ~0ULL) { 3526 bgep->chipid.hw_mac_addr = mac; 3527 for (i = ETHERADDRL; i-- != 0; ) { 3528 bgep->chipid.vendor_addr.addr[i] = (uchar_t)mac; 3529 mac >>= 8; 3530 } 3531 bgep->chipid.vendor_addr.set = B_TRUE; 3532 } 3533 } 3534 3535 #ifdef BGE_IPMI_ASF 3536 if (bgep->asf_enabled && bgep->asf_newhandshake) { 3537 if (asf_mode != ASF_MODE_NONE) { 3538 if ((asf_mode == ASF_MODE_INIT) || 3539 (asf_mode == ASF_MODE_POST_INIT)) { 3540 3541 bge_asf_post_reset_new_mode(bgep, 3542 BGE_INIT_RESET); 3543 } else { 3544 bge_asf_post_reset_new_mode(bgep, 3545 BGE_SHUTDOWN_RESET); 3546 } 3547 } 3548 } 3549 #endif 3550 3551 /* 3552 * Record the new state 3553 */ 3554 bgep->chip_resets += 1; 3555 bgep->bge_chip_state = BGE_CHIP_RESET; 3556 return (retval); 3557 } 3558 3559 /* 3560 * bge_chip_start() -- start the chip transmitting and/or receiving, 3561 * including enabling interrupts 3562 */ 3563 int bge_chip_start(bge_t *bgep, boolean_t reset_phys); 3564 #pragma no_inline(bge_chip_start) 3565 3566 int 3567 bge_chip_start(bge_t *bgep, boolean_t reset_phys) 3568 { 3569 uint32_t coalmode; 3570 uint32_t ledctl; 3571 uint32_t mtu; 3572 uint32_t maxring; 3573 uint32_t stats_mask; 3574 uint32_t dma_wrprio; 3575 uint64_t ring; 3576 int retval = DDI_SUCCESS; 3577 3578 BGE_TRACE(("bge_chip_start($%p)", 3579 (void *)bgep)); 3580 3581 ASSERT(mutex_owned(bgep->genlock)); 3582 ASSERT(bgep->bge_chip_state == BGE_CHIP_RESET); 3583 3584 /* 3585 * Taken from Broadcom document 570X-PG102-R, pp 102-116. 3586 * The document specifies 95 separate steps to fully 3587 * initialise the chip!!!! 3588 * 3589 * The reset code above has already got us as far as step 3590 * 21, so we continue with ... 3591 * 3592 * Step 22: clear the MAC statistics block 3593 * (0x0300-0x0aff in NIC-local memory) 3594 */ 3595 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 3596 bge_nic_zero(bgep, NIC_MEM_STATISTICS, 3597 NIC_MEM_STATISTICS_SIZE); 3598 3599 /* 3600 * Step 23: clear the status block (in host memory) 3601 */ 3602 DMA_ZERO(bgep->status_block); 3603 3604 /* 3605 * Step 24: set DMA read/write control register 3606 */ 3607 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_PDRWCR, 3608 bgep->chipid.bge_dma_rwctrl); 3609 3610 /* 3611 * Step 25: Configure DMA endianness -- already done (16/17) 3612 * Step 26: Configure Host-Based Send Rings 3613 * Step 27: Indicate Host Stack Up 3614 */ 3615 bge_reg_set32(bgep, MODE_CONTROL_REG, 3616 MODE_HOST_SEND_BDS | 3617 MODE_HOST_STACK_UP); 3618 3619 /* 3620 * Step 28: Configure checksum options: 3621 * Solaris supports the hardware default checksum options. 3622 * 3623 * Workaround for Incorrect pseudo-header checksum calculation. 3624 */ 3625 if (bgep->chipid.flags & CHIP_FLAG_PARTIAL_CSUM) 3626 bge_reg_set32(bgep, MODE_CONTROL_REG, 3627 MODE_SEND_NO_PSEUDO_HDR_CSUM); 3628 3629 /* 3630 * Step 29: configure Timer Prescaler. The value is always the 3631 * same: the Core Clock frequency in MHz (66), minus 1, shifted 3632 * into bits 7-1. Don't set bit 0, 'cos that's the RESET bit 3633 * for the whole chip! 3634 */ 3635 bge_reg_put32(bgep, MISC_CONFIG_REG, MISC_CONFIG_DEFAULT); 3636 3637 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) { 3638 drv_usecwait(40); 3639 /* put PHY into ready state */ 3640 bge_reg_clr32(bgep, MISC_CONFIG_REG, MISC_CONFIG_EPHY_IDDQ); 3641 (void) bge_reg_get32(bgep, MISC_CONFIG_REG); /* flush */ 3642 drv_usecwait(40); 3643 } 3644 3645 /* 3646 * Steps 30-31: Configure MAC local memory pool & DMA pool registers 3647 * 3648 * If the mbuf_length is specified as 0, we just leave these at 3649 * their hardware defaults, rather than explicitly setting them. 3650 * As the Broadcom HRM,driver better not change the parameters 3651 * when the chipsets is 5705/5788/5721/5751/5714 and 5715. 3652 */ 3653 if ((bgep->chipid.mbuf_length != 0) && 3654 (DEVICE_5704_SERIES_CHIPSETS(bgep))) { 3655 bge_reg_put32(bgep, MBUF_POOL_BASE_REG, 3656 bgep->chipid.mbuf_base); 3657 bge_reg_put32(bgep, MBUF_POOL_LENGTH_REG, 3658 bgep->chipid.mbuf_length); 3659 bge_reg_put32(bgep, DMAD_POOL_BASE_REG, 3660 DMAD_POOL_BASE_DEFAULT); 3661 bge_reg_put32(bgep, DMAD_POOL_LENGTH_REG, 3662 DMAD_POOL_LENGTH_DEFAULT); 3663 } 3664 3665 /* 3666 * Step 32: configure MAC memory pool watermarks 3667 */ 3668 bge_reg_put32(bgep, RDMA_MBUF_LOWAT_REG, 3669 bgep->chipid.mbuf_lo_water_rdma); 3670 bge_reg_put32(bgep, MAC_RX_MBUF_LOWAT_REG, 3671 bgep->chipid.mbuf_lo_water_rmac); 3672 bge_reg_put32(bgep, MBUF_HIWAT_REG, 3673 bgep->chipid.mbuf_hi_water); 3674 3675 /* 3676 * Step 33: configure DMA resource watermarks 3677 */ 3678 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3679 bge_reg_put32(bgep, DMAD_POOL_LOWAT_REG, 3680 bge_dmad_lo_water); 3681 bge_reg_put32(bgep, DMAD_POOL_HIWAT_REG, 3682 bge_dmad_hi_water); 3683 } 3684 bge_reg_put32(bgep, LOWAT_MAX_RECV_FRAMES_REG, bge_lowat_recv_frames); 3685 3686 /* 3687 * Steps 34-36: enable buffer manager & internal h/w queues 3688 */ 3689 if (!bge_chip_enable_engine(bgep, BUFFER_MANAGER_MODE_REG, 3690 STATE_MACHINE_ATTN_ENABLE_BIT)) 3691 retval = DDI_FAILURE; 3692 if (!bge_chip_enable_engine(bgep, FTQ_RESET_REG, 0)) 3693 retval = DDI_FAILURE; 3694 3695 /* 3696 * Steps 37-39: initialise Receive Buffer (Producer) RCBs 3697 */ 3698 bge_reg_putrcb(bgep, STD_RCV_BD_RING_RCB_REG, 3699 &bgep->buff[BGE_STD_BUFF_RING].hw_rcb); 3700 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3701 bge_reg_putrcb(bgep, JUMBO_RCV_BD_RING_RCB_REG, 3702 &bgep->buff[BGE_JUMBO_BUFF_RING].hw_rcb); 3703 bge_reg_putrcb(bgep, MINI_RCV_BD_RING_RCB_REG, 3704 &bgep->buff[BGE_MINI_BUFF_RING].hw_rcb); 3705 } 3706 3707 /* 3708 * Step 40: set Receive Buffer Descriptor Ring replenish thresholds 3709 */ 3710 bge_reg_put32(bgep, STD_RCV_BD_REPLENISH_REG, bge_replenish_std); 3711 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3712 bge_reg_put32(bgep, JUMBO_RCV_BD_REPLENISH_REG, 3713 bge_replenish_jumbo); 3714 bge_reg_put32(bgep, MINI_RCV_BD_REPLENISH_REG, 3715 bge_replenish_mini); 3716 } 3717 3718 /* 3719 * Steps 41-43: clear Send Ring Producer Indices and initialise 3720 * Send Producer Rings (0x0100-0x01ff in NIC-local memory) 3721 */ 3722 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3723 maxring = BGE_SEND_RINGS_MAX; 3724 else 3725 maxring = BGE_SEND_RINGS_MAX_5705; 3726 for (ring = 0; ring < maxring; ++ring) { 3727 bge_mbx_put(bgep, SEND_RING_HOST_INDEX_REG(ring), 0); 3728 bge_mbx_put(bgep, SEND_RING_NIC_INDEX_REG(ring), 0); 3729 bge_nic_putrcb(bgep, NIC_MEM_SEND_RING(ring), 3730 &bgep->send[ring].hw_rcb); 3731 } 3732 3733 /* 3734 * Steps 44-45: initialise Receive Return Rings 3735 * (0x0200-0x02ff in NIC-local memory) 3736 */ 3737 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3738 maxring = BGE_RECV_RINGS_MAX; 3739 else 3740 maxring = BGE_RECV_RINGS_MAX_5705; 3741 for (ring = 0; ring < maxring; ++ring) 3742 bge_nic_putrcb(bgep, NIC_MEM_RECV_RING(ring), 3743 &bgep->recv[ring].hw_rcb); 3744 3745 /* 3746 * Step 46: initialise Receive Buffer (Producer) Ring indexes 3747 */ 3748 bge_mbx_put(bgep, RECV_STD_PROD_INDEX_REG, 0); 3749 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3750 bge_mbx_put(bgep, RECV_JUMBO_PROD_INDEX_REG, 0); 3751 bge_mbx_put(bgep, RECV_MINI_PROD_INDEX_REG, 0); 3752 } 3753 /* 3754 * Step 47: configure the MAC unicast address 3755 * Step 48: configure the random backoff seed 3756 * Step 96: set up multicast filters 3757 */ 3758 #ifdef BGE_IPMI_ASF 3759 if (bge_chip_sync(bgep, B_FALSE) == DDI_FAILURE) 3760 #else 3761 if (bge_chip_sync(bgep) == DDI_FAILURE) 3762 #endif 3763 retval = DDI_FAILURE; 3764 3765 /* 3766 * Step 49: configure the MTU 3767 */ 3768 mtu = bgep->chipid.ethmax_size+ETHERFCSL+VLAN_TAGSZ; 3769 bge_reg_put32(bgep, MAC_RX_MTU_SIZE_REG, mtu); 3770 3771 /* 3772 * Step 50: configure the IPG et al 3773 */ 3774 bge_reg_put32(bgep, MAC_TX_LENGTHS_REG, MAC_TX_LENGTHS_DEFAULT); 3775 3776 /* 3777 * Step 51: configure the default Rx Return Ring 3778 */ 3779 bge_reg_put32(bgep, RCV_RULES_CONFIG_REG, RCV_RULES_CONFIG_DEFAULT); 3780 3781 /* 3782 * Steps 52-54: configure Receive List Placement, 3783 * and enable Receive List Placement Statistics 3784 */ 3785 bge_reg_put32(bgep, RCV_LP_CONFIG_REG, 3786 RCV_LP_CONFIG(bgep->chipid.rx_rings)); 3787 switch (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev)) { 3788 case MHCR_CHIP_ASIC_REV_5700: 3789 case MHCR_CHIP_ASIC_REV_5701: 3790 case MHCR_CHIP_ASIC_REV_5703: 3791 case MHCR_CHIP_ASIC_REV_5704: 3792 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, ~0); 3793 break; 3794 case MHCR_CHIP_ASIC_REV_5705: 3795 break; 3796 default: 3797 stats_mask = bge_reg_get32(bgep, RCV_LP_STATS_ENABLE_MASK_REG); 3798 stats_mask &= ~RCV_LP_STATS_DISABLE_MACTQ; 3799 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, stats_mask); 3800 break; 3801 } 3802 bge_reg_set32(bgep, RCV_LP_STATS_CONTROL_REG, RCV_LP_STATS_ENABLE); 3803 3804 if (bgep->chipid.rx_rings > 1) 3805 bge_init_recv_rule(bgep); 3806 3807 /* 3808 * Steps 55-56: enable Send Data Initiator Statistics 3809 */ 3810 bge_reg_put32(bgep, SEND_INIT_STATS_ENABLE_MASK_REG, ~0); 3811 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3812 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 3813 SEND_INIT_STATS_ENABLE | SEND_INIT_STATS_FASTER); 3814 } else { 3815 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 3816 SEND_INIT_STATS_ENABLE); 3817 } 3818 /* 3819 * Steps 57-58: stop (?) the Host Coalescing Engine 3820 */ 3821 if (!bge_chip_disable_engine(bgep, HOST_COALESCE_MODE_REG, ~0)) 3822 retval = DDI_FAILURE; 3823 3824 /* 3825 * Steps 59-62: initialise Host Coalescing parameters 3826 */ 3827 bge_reg_put32(bgep, SEND_COALESCE_MAX_BD_REG, bge_tx_count_norm); 3828 bge_reg_put32(bgep, SEND_COALESCE_TICKS_REG, bge_tx_ticks_norm); 3829 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, bge_rx_count_norm); 3830 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, bge_rx_ticks_norm); 3831 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3832 bge_reg_put32(bgep, SEND_COALESCE_INT_BD_REG, 3833 bge_tx_count_intr); 3834 bge_reg_put32(bgep, SEND_COALESCE_INT_TICKS_REG, 3835 bge_tx_ticks_intr); 3836 bge_reg_put32(bgep, RCV_COALESCE_INT_BD_REG, 3837 bge_rx_count_intr); 3838 bge_reg_put32(bgep, RCV_COALESCE_INT_TICKS_REG, 3839 bge_rx_ticks_intr); 3840 } 3841 3842 /* 3843 * Steps 63-64: initialise status block & statistics 3844 * host memory addresses 3845 * The statistic block does not exist in some chipsets 3846 * Step 65: initialise Statistics Coalescing Tick Counter 3847 */ 3848 bge_reg_put64(bgep, STATUS_BLOCK_HOST_ADDR_REG, 3849 bgep->status_block.cookie.dmac_laddress); 3850 3851 /* 3852 * Steps 66-67: initialise status block & statistics 3853 * NIC-local memory addresses 3854 */ 3855 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3856 bge_reg_put64(bgep, STATISTICS_HOST_ADDR_REG, 3857 bgep->statistics.cookie.dmac_laddress); 3858 bge_reg_put32(bgep, STATISTICS_TICKS_REG, 3859 STATISTICS_TICKS_DEFAULT); 3860 bge_reg_put32(bgep, STATUS_BLOCK_BASE_ADDR_REG, 3861 NIC_MEM_STATUS_BLOCK); 3862 bge_reg_put32(bgep, STATISTICS_BASE_ADDR_REG, 3863 NIC_MEM_STATISTICS); 3864 } 3865 3866 /* 3867 * Steps 68-71: start the Host Coalescing Engine, the Receive BD 3868 * Completion Engine, the Receive List Placement Engine, and the 3869 * Receive List selector.Pay attention:0x3400 is not exist in BCM5714 3870 * and BCM5715. 3871 */ 3872 if (bgep->chipid.tx_rings <= COALESCE_64_BYTE_RINGS && 3873 bgep->chipid.rx_rings <= COALESCE_64_BYTE_RINGS) 3874 coalmode = COALESCE_64_BYTE_STATUS; 3875 else 3876 coalmode = 0; 3877 if (!bge_chip_enable_engine(bgep, HOST_COALESCE_MODE_REG, coalmode)) 3878 retval = DDI_FAILURE; 3879 if (!bge_chip_enable_engine(bgep, RCV_BD_COMPLETION_MODE_REG, 3880 STATE_MACHINE_ATTN_ENABLE_BIT)) 3881 retval = DDI_FAILURE; 3882 if (!bge_chip_enable_engine(bgep, RCV_LIST_PLACEMENT_MODE_REG, 0)) 3883 retval = DDI_FAILURE; 3884 3885 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3886 if (!bge_chip_enable_engine(bgep, RCV_LIST_SELECTOR_MODE_REG, 3887 STATE_MACHINE_ATTN_ENABLE_BIT)) 3888 retval = DDI_FAILURE; 3889 3890 /* 3891 * Step 72: Enable MAC DMA engines 3892 * Step 73: Clear & enable MAC statistics 3893 */ 3894 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 3895 ETHERNET_MODE_ENABLE_FHDE | 3896 ETHERNET_MODE_ENABLE_RDE | 3897 ETHERNET_MODE_ENABLE_TDE); 3898 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 3899 ETHERNET_MODE_ENABLE_TX_STATS | 3900 ETHERNET_MODE_ENABLE_RX_STATS | 3901 ETHERNET_MODE_CLEAR_TX_STATS | 3902 ETHERNET_MODE_CLEAR_RX_STATS); 3903 3904 /* 3905 * Step 74: configure the MLCR (Miscellaneous Local Control 3906 * Register); not required, as we set up the MLCR in step 10 3907 * (part of the reset code) above. 3908 * 3909 * Step 75: clear Interrupt Mailbox 0 3910 */ 3911 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 0); 3912 3913 /* 3914 * Steps 76-87: Gentlemen, start your engines ... 3915 * 3916 * Enable the DMA Completion Engine, the Write DMA Engine, 3917 * the Read DMA Engine, Receive Data Completion Engine, 3918 * the MBuf Cluster Free Engine, the Send Data Completion Engine, 3919 * the Send BD Completion Engine, the Receive BD Initiator Engine, 3920 * the Receive Data Initiator Engine, the Send Data Initiator Engine, 3921 * the Send BD Initiator Engine, and the Send BD Selector Engine. 3922 * 3923 * Beware exhaust fumes? 3924 */ 3925 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3926 if (!bge_chip_enable_engine(bgep, DMA_COMPLETION_MODE_REG, 0)) 3927 retval = DDI_FAILURE; 3928 dma_wrprio = (bge_dma_wrprio << DMA_PRIORITY_SHIFT) | 3929 ALL_DMA_ATTN_BITS; 3930 if ((MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) == 3931 MHCR_CHIP_ASIC_REV_5755) || 3932 (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) == 3933 MHCR_CHIP_ASIC_REV_5906)) { 3934 dma_wrprio |= DMA_STATUS_TAG_FIX_CQ12384; 3935 } 3936 if (!bge_chip_enable_engine(bgep, WRITE_DMA_MODE_REG, 3937 dma_wrprio)) 3938 retval = DDI_FAILURE; 3939 if (!bge_chip_enable_engine(bgep, READ_DMA_MODE_REG, 3940 (bge_dma_rdprio << DMA_PRIORITY_SHIFT) | ALL_DMA_ATTN_BITS)) 3941 retval = DDI_FAILURE; 3942 if (!bge_chip_enable_engine(bgep, RCV_DATA_COMPLETION_MODE_REG, 3943 STATE_MACHINE_ATTN_ENABLE_BIT)) 3944 retval = DDI_FAILURE; 3945 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3946 if (!bge_chip_enable_engine(bgep, 3947 MBUF_CLUSTER_FREE_MODE_REG, 0)) 3948 retval = DDI_FAILURE; 3949 if (!bge_chip_enable_engine(bgep, SEND_DATA_COMPLETION_MODE_REG, 0)) 3950 retval = DDI_FAILURE; 3951 if (!bge_chip_enable_engine(bgep, SEND_BD_COMPLETION_MODE_REG, 3952 STATE_MACHINE_ATTN_ENABLE_BIT)) 3953 retval = DDI_FAILURE; 3954 if (!bge_chip_enable_engine(bgep, RCV_BD_INITIATOR_MODE_REG, 3955 RCV_BD_DISABLED_RING_ATTN)) 3956 retval = DDI_FAILURE; 3957 if (!bge_chip_enable_engine(bgep, RCV_DATA_BD_INITIATOR_MODE_REG, 3958 RCV_DATA_BD_ILL_RING_ATTN)) 3959 retval = DDI_FAILURE; 3960 if (!bge_chip_enable_engine(bgep, SEND_DATA_INITIATOR_MODE_REG, 0)) 3961 retval = DDI_FAILURE; 3962 if (!bge_chip_enable_engine(bgep, SEND_BD_INITIATOR_MODE_REG, 3963 STATE_MACHINE_ATTN_ENABLE_BIT)) 3964 retval = DDI_FAILURE; 3965 if (!bge_chip_enable_engine(bgep, SEND_BD_SELECTOR_MODE_REG, 3966 STATE_MACHINE_ATTN_ENABLE_BIT)) 3967 retval = DDI_FAILURE; 3968 3969 /* 3970 * Step 88: download firmware -- doesn't apply 3971 * Steps 89-90: enable Transmit & Receive MAC Engines 3972 */ 3973 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 3974 retval = DDI_FAILURE; 3975 #ifdef BGE_IPMI_ASF 3976 if (!bgep->asf_enabled) { 3977 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 3978 RECEIVE_MODE_KEEP_VLAN_TAG)) 3979 retval = DDI_FAILURE; 3980 } else { 3981 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 0)) 3982 retval = DDI_FAILURE; 3983 } 3984 #else 3985 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 3986 RECEIVE_MODE_KEEP_VLAN_TAG)) 3987 retval = DDI_FAILURE; 3988 #endif 3989 3990 /* 3991 * Step 91: disable auto-polling of PHY status 3992 */ 3993 bge_reg_put32(bgep, MI_MODE_REG, MI_MODE_DEFAULT); 3994 3995 /* 3996 * Step 92: configure D0 power state (not required) 3997 * Step 93: initialise LED control register () 3998 */ 3999 ledctl = LED_CONTROL_DEFAULT; 4000 switch (bgep->chipid.device) { 4001 case DEVICE_ID_5700: 4002 case DEVICE_ID_5700x: 4003 case DEVICE_ID_5701: 4004 /* 4005 * Switch to 5700 (MAC) mode on these older chips 4006 */ 4007 ledctl &= ~LED_CONTROL_LED_MODE_MASK; 4008 ledctl |= LED_CONTROL_LED_MODE_5700; 4009 break; 4010 4011 default: 4012 break; 4013 } 4014 bge_reg_put32(bgep, ETHERNET_MAC_LED_CONTROL_REG, ledctl); 4015 4016 /* 4017 * Step 94: activate link 4018 */ 4019 bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK); 4020 4021 /* 4022 * Step 95: set up physical layer (PHY/SerDes) 4023 * restart autoneg (if required) 4024 */ 4025 if (reset_phys) 4026 if (bge_phys_update(bgep) == DDI_FAILURE) 4027 retval = DDI_FAILURE; 4028 4029 /* 4030 * Extra step (DSG): hand over all the Receive Buffers to the chip 4031 */ 4032 for (ring = 0; ring < BGE_BUFF_RINGS_USED; ++ring) 4033 bge_mbx_put(bgep, bgep->buff[ring].chip_mbx_reg, 4034 bgep->buff[ring].rf_next); 4035 4036 /* 4037 * MSI bits:The least significant MSI 16-bit word. 4038 * ISR will be triggered different. 4039 */ 4040 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 4041 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 0x70); 4042 4043 /* 4044 * Extra step (DSG): select which interrupts are enabled 4045 * 4046 * Program the Ethernet MAC engine to signal attention on 4047 * Link Change events, then enable interrupts on MAC, DMA, 4048 * and FLOW attention signals. 4049 */ 4050 bge_reg_set32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 4051 ETHERNET_EVENT_LINK_INT | 4052 ETHERNET_STATUS_PCS_ERROR_INT); 4053 #ifdef BGE_IPMI_ASF 4054 if (bgep->asf_enabled) { 4055 bge_reg_set32(bgep, MODE_CONTROL_REG, 4056 MODE_INT_ON_FLOW_ATTN | 4057 MODE_INT_ON_DMA_ATTN | 4058 MODE_HOST_STACK_UP| 4059 MODE_INT_ON_MAC_ATTN); 4060 } else { 4061 #endif 4062 bge_reg_set32(bgep, MODE_CONTROL_REG, 4063 MODE_INT_ON_FLOW_ATTN | 4064 MODE_INT_ON_DMA_ATTN | 4065 MODE_INT_ON_MAC_ATTN); 4066 #ifdef BGE_IPMI_ASF 4067 } 4068 #endif 4069 4070 /* 4071 * Step 97: enable PCI interrupts!!! 4072 */ 4073 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 4074 bge_cfg_clr32(bgep, PCI_CONF_BGE_MHCR, 4075 MHCR_MASK_PCI_INT_OUTPUT); 4076 4077 /* 4078 * All done! 4079 */ 4080 bgep->bge_chip_state = BGE_CHIP_RUNNING; 4081 return (retval); 4082 } 4083 4084 4085 /* 4086 * ========== Hardware interrupt handler ========== 4087 */ 4088 4089 #undef BGE_DBG 4090 #define BGE_DBG BGE_DBG_INT /* debug flag for this code */ 4091 4092 /* 4093 * Sync the status block, then atomically clear the specified bits in 4094 * the <flags-and-tag> field of the status block. 4095 * the <flags> word of the status block, returning the value of the 4096 * <tag> and the <flags> before the bits were cleared. 4097 */ 4098 static int bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags); 4099 #pragma inline(bge_status_sync) 4100 4101 static int 4102 bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags) 4103 { 4104 bge_status_t *bsp; 4105 int retval; 4106 4107 BGE_TRACE(("bge_status_sync($%p, 0x%llx)", 4108 (void *)bgep, bits)); 4109 4110 ASSERT(bgep->bge_guard == BGE_GUARD); 4111 4112 DMA_SYNC(bgep->status_block, DDI_DMA_SYNC_FORKERNEL); 4113 retval = bge_check_dma_handle(bgep, bgep->status_block.dma_hdl); 4114 if (retval != DDI_FM_OK) 4115 return (retval); 4116 4117 bsp = DMA_VPTR(bgep->status_block); 4118 *flags = bge_atomic_clr64(&bsp->flags_n_tag, bits); 4119 4120 BGE_DEBUG(("bge_status_sync($%p, 0x%llx) returning 0x%llx", 4121 (void *)bgep, bits, *flags)); 4122 4123 return (retval); 4124 } 4125 4126 void bge_wake_factotum(bge_t *bgep); 4127 #pragma inline(bge_wake_factotum) 4128 4129 void 4130 bge_wake_factotum(bge_t *bgep) 4131 { 4132 mutex_enter(bgep->softintrlock); 4133 if (bgep->factotum_flag == 0) { 4134 bgep->factotum_flag = 1; 4135 ddi_trigger_softintr(bgep->factotum_id); 4136 } 4137 mutex_exit(bgep->softintrlock); 4138 } 4139 4140 /* 4141 * bge_intr() -- handle chip interrupts 4142 */ 4143 uint_t bge_intr(caddr_t arg1, caddr_t arg2); 4144 #pragma no_inline(bge_intr) 4145 4146 uint_t 4147 bge_intr(caddr_t arg1, caddr_t arg2) 4148 { 4149 bge_t *bgep = (void *)arg1; /* private device info */ 4150 bge_status_t *bsp; 4151 uint64_t flags; 4152 uint32_t regval; 4153 uint_t result; 4154 int retval, loop_cnt = 0; 4155 4156 BGE_TRACE(("bge_intr($%p) ($%p)", arg1, arg2)); 4157 4158 /* 4159 * GLD v2 checks that s/w setup is complete before passing 4160 * interrupts to this routine, thus eliminating the old 4161 * (and well-known) race condition around ddi_add_intr() 4162 */ 4163 ASSERT(bgep->progress & PROGRESS_HWINT); 4164 4165 result = DDI_INTR_UNCLAIMED; 4166 mutex_enter(bgep->genlock); 4167 4168 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) { 4169 /* 4170 * Check whether chip's says it's asserting #INTA; 4171 * if not, don't process or claim the interrupt. 4172 * 4173 * Note that the PCI signal is active low, so the 4174 * bit is *zero* when the interrupt is asserted. 4175 */ 4176 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 4177 if (regval & MLCR_INTA_STATE) { 4178 if (bge_check_acc_handle(bgep, bgep->io_handle) 4179 != DDI_FM_OK) 4180 goto chip_stop; 4181 mutex_exit(bgep->genlock); 4182 return (result); 4183 } 4184 4185 /* 4186 * Block further PCI interrupts ... 4187 */ 4188 bge_reg_set32(bgep, PCI_CONF_BGE_MHCR, 4189 MHCR_MASK_PCI_INT_OUTPUT); 4190 4191 } else { 4192 /* 4193 * Check MSI status 4194 */ 4195 regval = bge_reg_get32(bgep, MSI_STATUS_REG); 4196 if (regval & MSI_ERROR_ATTENTION) { 4197 BGE_REPORT((bgep, "msi error attention," 4198 " status=0x%x", regval)); 4199 bge_reg_put32(bgep, MSI_STATUS_REG, regval); 4200 } 4201 } 4202 4203 result = DDI_INTR_CLAIMED; 4204 4205 BGE_DEBUG(("bge_intr($%p) ($%p) regval 0x%08x", arg1, arg2, regval)); 4206 4207 /* 4208 * Sync the status block and grab the flags-n-tag from it. 4209 * We count the number of interrupts where there doesn't 4210 * seem to have been a DMA update of the status block; if 4211 * it *has* been updated, the counter will be cleared in 4212 * the while() loop below ... 4213 */ 4214 bgep->missed_dmas += 1; 4215 bsp = DMA_VPTR(bgep->status_block); 4216 for (loop_cnt = 0; loop_cnt < bge_intr_max_loop; loop_cnt++) { 4217 if (bgep->bge_chip_state != BGE_CHIP_RUNNING) { 4218 /* 4219 * bge_chip_stop() may have freed dma area etc 4220 * while we were in this interrupt handler - 4221 * better not call bge_status_sync() 4222 */ 4223 (void) bge_check_acc_handle(bgep, 4224 bgep->io_handle); 4225 mutex_exit(bgep->genlock); 4226 return (DDI_INTR_CLAIMED); 4227 } 4228 retval = bge_status_sync(bgep, STATUS_FLAG_UPDATED, 4229 &flags); 4230 if (retval != DDI_FM_OK) { 4231 bgep->bge_dma_error = B_TRUE; 4232 goto chip_stop; 4233 } 4234 4235 if (!(flags & STATUS_FLAG_UPDATED)) 4236 break; 4237 4238 /* 4239 * Tell the chip that we're processing the interrupt 4240 */ 4241 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 4242 INTERRUPT_MBOX_DISABLE(flags)); 4243 if (bge_check_acc_handle(bgep, bgep->io_handle) != 4244 DDI_FM_OK) 4245 goto chip_stop; 4246 4247 /* 4248 * Drop the mutex while we: 4249 * Receive any newly-arrived packets 4250 * Recycle any newly-finished send buffers 4251 */ 4252 bgep->bge_intr_running = B_TRUE; 4253 mutex_exit(bgep->genlock); 4254 bge_receive(bgep, bsp); 4255 bge_recycle(bgep, bsp); 4256 mutex_enter(bgep->genlock); 4257 bgep->bge_intr_running = B_FALSE; 4258 4259 /* 4260 * Tell the chip we've finished processing, and 4261 * give it the tag that we got from the status 4262 * block earlier, so that it knows just how far 4263 * we've gone. If it's got more for us to do, 4264 * it will now update the status block and try 4265 * to assert an interrupt (but we've got the 4266 * #INTA blocked at present). If we see the 4267 * update, we'll loop around to do some more. 4268 * Eventually we'll get out of here ... 4269 */ 4270 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 4271 INTERRUPT_MBOX_ENABLE(flags)); 4272 if (bgep->chipid.pci_type == BGE_PCI_E) 4273 (void) bge_mbx_get(bgep, INTERRUPT_MBOX_0_REG); 4274 bgep->missed_dmas = 0; 4275 } 4276 4277 /* 4278 * Check for exceptional conditions that we need to handle 4279 * 4280 * Link status changed 4281 * Status block not updated 4282 */ 4283 if (flags & STATUS_FLAG_LINK_CHANGED) 4284 bge_wake_factotum(bgep); 4285 4286 if (bgep->missed_dmas) { 4287 /* 4288 * Probably due to the internal status tag not 4289 * being reset. Force a status block update now; 4290 * this should ensure that we get an update and 4291 * a new interrupt. After that, we should be in 4292 * sync again ... 4293 */ 4294 BGE_REPORT((bgep, "interrupt: flags 0x%llx - " 4295 "not updated?", flags)); 4296 bgep->missed_updates++; 4297 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 4298 COALESCE_NOW); 4299 4300 if (bgep->missed_dmas >= bge_dma_miss_limit) { 4301 /* 4302 * If this happens multiple times in a row, 4303 * it means DMA is just not working. Maybe 4304 * the chip's failed, or maybe there's a 4305 * problem on the PCI bus or in the host-PCI 4306 * bridge (Tomatillo). 4307 * 4308 * At all events, we want to stop further 4309 * interrupts and let the recovery code take 4310 * over to see whether anything can be done 4311 * about it ... 4312 */ 4313 bge_fm_ereport(bgep, 4314 DDI_FM_DEVICE_BADINT_LIMIT); 4315 goto chip_stop; 4316 } 4317 } 4318 4319 /* 4320 * Reenable assertion of #INTA, unless there's a DMA fault 4321 */ 4322 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) { 4323 bge_reg_clr32(bgep, PCI_CONF_BGE_MHCR, 4324 MHCR_MASK_PCI_INT_OUTPUT); 4325 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != 4326 DDI_FM_OK) 4327 goto chip_stop; 4328 } 4329 4330 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4331 goto chip_stop; 4332 4333 mutex_exit(bgep->genlock); 4334 return (result); 4335 4336 chip_stop: 4337 #ifdef BGE_IPMI_ASF 4338 if (bgep->asf_enabled && bgep->asf_status == ASF_STAT_RUN) { 4339 /* 4340 * We must stop ASF heart beat before 4341 * bge_chip_stop(), otherwise some 4342 * computers (ex. IBM HS20 blade 4343 * server) may crash. 4344 */ 4345 bge_asf_update_status(bgep); 4346 bge_asf_stop_timer(bgep); 4347 bgep->asf_status = ASF_STAT_STOP; 4348 4349 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 4350 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 4351 } 4352 #endif 4353 bge_chip_stop(bgep, B_TRUE); 4354 (void) bge_check_acc_handle(bgep, bgep->io_handle); 4355 mutex_exit(bgep->genlock); 4356 return (result); 4357 } 4358 4359 /* 4360 * ========== Factotum, implemented as a softint handler ========== 4361 */ 4362 4363 #undef BGE_DBG 4364 #define BGE_DBG BGE_DBG_FACT /* debug flag for this code */ 4365 4366 static void bge_factotum_error_handler(bge_t *bgep); 4367 #pragma no_inline(bge_factotum_error_handler) 4368 4369 static void 4370 bge_factotum_error_handler(bge_t *bgep) 4371 { 4372 uint32_t flow; 4373 uint32_t rdma; 4374 uint32_t wdma; 4375 uint32_t tmac; 4376 uint32_t rmac; 4377 uint32_t rxrs; 4378 uint32_t txrs = 0; 4379 4380 ASSERT(mutex_owned(bgep->genlock)); 4381 4382 /* 4383 * Read all the registers that show the possible 4384 * reasons for the ERROR bit to be asserted 4385 */ 4386 flow = bge_reg_get32(bgep, FLOW_ATTN_REG); 4387 rdma = bge_reg_get32(bgep, READ_DMA_STATUS_REG); 4388 wdma = bge_reg_get32(bgep, WRITE_DMA_STATUS_REG); 4389 tmac = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 4390 rmac = bge_reg_get32(bgep, RECEIVE_MAC_STATUS_REG); 4391 rxrs = bge_reg_get32(bgep, RX_RISC_STATE_REG); 4392 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4393 txrs = bge_reg_get32(bgep, TX_RISC_STATE_REG); 4394 4395 BGE_DEBUG(("factotum($%p) flow 0x%x rdma 0x%x wdma 0x%x", 4396 (void *)bgep, flow, rdma, wdma)); 4397 BGE_DEBUG(("factotum($%p) tmac 0x%x rmac 0x%x rxrs 0x%08x txrs 0x%08x", 4398 (void *)bgep, tmac, rmac, rxrs, txrs)); 4399 4400 /* 4401 * For now, just clear all the errors ... 4402 */ 4403 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4404 bge_reg_put32(bgep, TX_RISC_STATE_REG, ~0); 4405 bge_reg_put32(bgep, RX_RISC_STATE_REG, ~0); 4406 bge_reg_put32(bgep, RECEIVE_MAC_STATUS_REG, ~0); 4407 bge_reg_put32(bgep, WRITE_DMA_STATUS_REG, ~0); 4408 bge_reg_put32(bgep, READ_DMA_STATUS_REG, ~0); 4409 bge_reg_put32(bgep, FLOW_ATTN_REG, ~0); 4410 } 4411 4412 /* 4413 * Handler for hardware link state change. 4414 * 4415 * When this routine is called, the hardware link state has changed 4416 * and the new state is reflected in the param_* variables. Here 4417 * we must update the softstate and reprogram the MAC to match. 4418 */ 4419 static void bge_factotum_link_handler(bge_t *bgep); 4420 #pragma no_inline(bge_factotum_link_handler) 4421 4422 static void 4423 bge_factotum_link_handler(bge_t *bgep) 4424 { 4425 ASSERT(mutex_owned(bgep->genlock)); 4426 4427 /* 4428 * Update the s/w link_state 4429 */ 4430 if (bgep->param_link_up) 4431 bgep->link_state = LINK_STATE_UP; 4432 else 4433 bgep->link_state = LINK_STATE_DOWN; 4434 4435 /* 4436 * Reprogram the MAC modes to match 4437 */ 4438 bge_sync_mac_modes(bgep); 4439 } 4440 4441 static boolean_t bge_factotum_link_check(bge_t *bgep, int *dma_state); 4442 #pragma no_inline(bge_factotum_link_check) 4443 4444 static boolean_t 4445 bge_factotum_link_check(bge_t *bgep, int *dma_state) 4446 { 4447 boolean_t check; 4448 uint64_t flags; 4449 uint32_t tmac_status; 4450 4451 ASSERT(mutex_owned(bgep->genlock)); 4452 4453 /* 4454 * Get & clear the writable status bits in the Tx status register 4455 * (some bits are write-1-to-clear, others are just readonly). 4456 */ 4457 tmac_status = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 4458 bge_reg_put32(bgep, TRANSMIT_MAC_STATUS_REG, tmac_status); 4459 4460 /* 4461 * Get & clear the ERROR and LINK_CHANGED bits from the status block 4462 */ 4463 *dma_state = bge_status_sync(bgep, STATUS_FLAG_ERROR | 4464 STATUS_FLAG_LINK_CHANGED, &flags); 4465 if (*dma_state != DDI_FM_OK) 4466 return (B_FALSE); 4467 4468 /* 4469 * Clear any errors flagged in the status block ... 4470 */ 4471 if (flags & STATUS_FLAG_ERROR) 4472 bge_factotum_error_handler(bgep); 4473 4474 /* 4475 * We need to check the link status if: 4476 * the status block says there's been a link change 4477 * or there's any discrepancy between the various 4478 * flags indicating the link state (link_state, 4479 * param_link_up, and the LINK STATE bit in the 4480 * Transmit MAC status register). 4481 */ 4482 check = (flags & STATUS_FLAG_LINK_CHANGED) != 0; 4483 switch (bgep->link_state) { 4484 case LINK_STATE_UP: 4485 check |= (bgep->param_link_up == B_FALSE); 4486 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) == 0); 4487 break; 4488 4489 case LINK_STATE_DOWN: 4490 check |= (bgep->param_link_up != B_FALSE); 4491 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) != 0); 4492 break; 4493 4494 default: 4495 check = B_TRUE; 4496 break; 4497 } 4498 4499 /* 4500 * If <check> is false, we're sure the link hasn't changed. 4501 * If true, however, it's not yet definitive; we have to call 4502 * bge_phys_check() to determine whether the link has settled 4503 * into a new state yet ... and if it has, then call the link 4504 * state change handler.But when the chip is 5700 in Dell 6650 4505 * ,even if check is false, the link may have changed.So we 4506 * have to call bge_phys_check() to determine the link state. 4507 */ 4508 if (check || bgep->chipid.device == DEVICE_ID_5700) { 4509 check = bge_phys_check(bgep); 4510 if (check) 4511 bge_factotum_link_handler(bgep); 4512 } 4513 4514 return (check); 4515 } 4516 4517 /* 4518 * Factotum routine to check for Tx stall, using the 'watchdog' counter 4519 */ 4520 static boolean_t bge_factotum_stall_check(bge_t *bgep); 4521 #pragma no_inline(bge_factotum_stall_check) 4522 4523 static boolean_t 4524 bge_factotum_stall_check(bge_t *bgep) 4525 { 4526 uint32_t dogval; 4527 4528 ASSERT(mutex_owned(bgep->genlock)); 4529 4530 /* 4531 * Specific check for Tx stall ... 4532 * 4533 * The 'watchdog' counter is incremented whenever a packet 4534 * is queued, reset to 1 when some (but not all) buffers 4535 * are reclaimed, reset to 0 (disabled) when all buffers 4536 * are reclaimed, and shifted left here. If it exceeds the 4537 * threshold value, the chip is assumed to have stalled and 4538 * is put into the ERROR state. The factotum will then reset 4539 * it on the next pass. 4540 * 4541 * All of which should ensure that we don't get into a state 4542 * where packets are left pending indefinitely! 4543 */ 4544 dogval = bge_atomic_shl32(&bgep->watchdog, 1); 4545 if (dogval < bge_watchdog_count) 4546 return (B_FALSE); 4547 4548 #if !defined(BGE_NETCONSOLE) 4549 BGE_REPORT((bgep, "Tx stall detected, watchdog code 0x%x", dogval)); 4550 #endif 4551 bge_fm_ereport(bgep, DDI_FM_DEVICE_STALL); 4552 return (B_TRUE); 4553 } 4554 4555 /* 4556 * The factotum is woken up when there's something to do that we'd rather 4557 * not do from inside a hardware interrupt handler or high-level cyclic. 4558 * Its two main tasks are: 4559 * reset & restart the chip after an error 4560 * check the link status whenever necessary 4561 */ 4562 uint_t bge_chip_factotum(caddr_t arg); 4563 #pragma no_inline(bge_chip_factotum) 4564 4565 uint_t 4566 bge_chip_factotum(caddr_t arg) 4567 { 4568 bge_t *bgep; 4569 uint_t result; 4570 boolean_t error; 4571 boolean_t linkchg; 4572 int dma_state; 4573 4574 bgep = (void *)arg; 4575 4576 BGE_TRACE(("bge_chip_factotum($%p)", (void *)bgep)); 4577 4578 mutex_enter(bgep->softintrlock); 4579 if (bgep->factotum_flag == 0) { 4580 mutex_exit(bgep->softintrlock); 4581 return (DDI_INTR_UNCLAIMED); 4582 } 4583 bgep->factotum_flag = 0; 4584 mutex_exit(bgep->softintrlock); 4585 4586 result = DDI_INTR_CLAIMED; 4587 error = B_FALSE; 4588 linkchg = B_FALSE; 4589 4590 mutex_enter(bgep->genlock); 4591 switch (bgep->bge_chip_state) { 4592 default: 4593 break; 4594 4595 case BGE_CHIP_RUNNING: 4596 linkchg = bge_factotum_link_check(bgep, &dma_state); 4597 error = bge_factotum_stall_check(bgep); 4598 if (dma_state != DDI_FM_OK) { 4599 bgep->bge_dma_error = B_TRUE; 4600 error = B_TRUE; 4601 } 4602 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4603 error = B_TRUE; 4604 if (error) 4605 bgep->bge_chip_state = BGE_CHIP_ERROR; 4606 break; 4607 4608 case BGE_CHIP_ERROR: 4609 error = B_TRUE; 4610 break; 4611 4612 case BGE_CHIP_FAULT: 4613 /* 4614 * Fault detected, time to reset ... 4615 */ 4616 if (bge_autorecover) { 4617 if (!(bgep->progress & PROGRESS_BUFS)) { 4618 /* 4619 * if we can't allocate the ring buffers, 4620 * try later 4621 */ 4622 if (bge_alloc_bufs(bgep) != DDI_SUCCESS) { 4623 mutex_exit(bgep->genlock); 4624 return (result); 4625 } 4626 bgep->progress |= PROGRESS_BUFS; 4627 } 4628 if (!(bgep->progress & PROGRESS_INTR)) { 4629 bge_init_rings(bgep); 4630 bge_intr_enable(bgep); 4631 bgep->progress |= PROGRESS_INTR; 4632 } 4633 if (!(bgep->progress & PROGRESS_KSTATS)) { 4634 bge_init_kstats(bgep, 4635 ddi_get_instance(bgep->devinfo)); 4636 bgep->progress |= PROGRESS_KSTATS; 4637 } 4638 4639 BGE_REPORT((bgep, "automatic recovery activated")); 4640 4641 if (bge_restart(bgep, B_FALSE) != DDI_SUCCESS) { 4642 bgep->bge_chip_state = BGE_CHIP_ERROR; 4643 error = B_TRUE; 4644 } 4645 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != 4646 DDI_FM_OK) { 4647 bgep->bge_chip_state = BGE_CHIP_ERROR; 4648 error = B_TRUE; 4649 } 4650 if (bge_check_acc_handle(bgep, bgep->io_handle) != 4651 DDI_FM_OK) { 4652 bgep->bge_chip_state = BGE_CHIP_ERROR; 4653 error = B_TRUE; 4654 } 4655 if (error == B_FALSE) { 4656 #ifdef BGE_IPMI_ASF 4657 if (bgep->asf_enabled && 4658 bgep->asf_status != ASF_STAT_RUN) { 4659 bgep->asf_timeout_id = timeout( 4660 bge_asf_heartbeat, (void *)bgep, 4661 drv_usectohz( 4662 BGE_ASF_HEARTBEAT_INTERVAL)); 4663 bgep->asf_status = ASF_STAT_RUN; 4664 } 4665 #endif 4666 if (!bgep->manual_reset) { 4667 ddi_fm_service_impact(bgep->devinfo, 4668 DDI_SERVICE_RESTORED); 4669 } 4670 } 4671 } 4672 break; 4673 } 4674 4675 4676 /* 4677 * If an error is detected, stop the chip now, marking it as 4678 * faulty, so that it will be reset next time through ... 4679 * 4680 * Note that if intr_running is set, then bge_intr() has dropped 4681 * genlock to call bge_receive/bge_recycle. Can't stop the chip at 4682 * this point so have to wait until the next time the factotum runs. 4683 */ 4684 if (error && !bgep->bge_intr_running) { 4685 #ifdef BGE_IPMI_ASF 4686 if (bgep->asf_enabled && (bgep->asf_status == ASF_STAT_RUN)) { 4687 /* 4688 * We must stop ASF heart beat before bge_chip_stop(), 4689 * otherwise some computers (ex. IBM HS20 blade server) 4690 * may crash. 4691 */ 4692 bge_asf_update_status(bgep); 4693 bge_asf_stop_timer(bgep); 4694 bgep->asf_status = ASF_STAT_STOP; 4695 4696 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 4697 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 4698 } 4699 #endif 4700 bge_chip_stop(bgep, B_TRUE); 4701 (void) bge_check_acc_handle(bgep, bgep->io_handle); 4702 } 4703 mutex_exit(bgep->genlock); 4704 4705 /* 4706 * If the link state changed, tell the world about it. 4707 * Note: can't do this while still holding the mutex. 4708 */ 4709 if (bgep->link_update_timer == BGE_LINK_UPDATE_TIMEOUT && 4710 bgep->link_state != LINK_STATE_UNKNOWN) 4711 linkchg = B_TRUE; 4712 else if (bgep->link_update_timer < BGE_LINK_UPDATE_TIMEOUT && 4713 bgep->link_state == LINK_STATE_DOWN) 4714 linkchg = B_FALSE; 4715 4716 if (linkchg) { 4717 mac_link_update(bgep->mh, bgep->link_state); 4718 bgep->link_update_timer = BGE_LINK_UPDATE_DONE; 4719 } 4720 if (bgep->manual_reset) { 4721 bgep->manual_reset = B_FALSE; 4722 } 4723 4724 return (result); 4725 } 4726 4727 /* 4728 * High-level cyclic handler 4729 * 4730 * This routine schedules a (low-level) softint callback to the 4731 * factotum, and prods the chip to update the status block (which 4732 * will cause a hardware interrupt when complete). 4733 */ 4734 void bge_chip_cyclic(void *arg); 4735 #pragma no_inline(bge_chip_cyclic) 4736 4737 void 4738 bge_chip_cyclic(void *arg) 4739 { 4740 bge_t *bgep; 4741 4742 bgep = arg; 4743 4744 switch (bgep->bge_chip_state) { 4745 default: 4746 return; 4747 4748 case BGE_CHIP_RUNNING: 4749 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, COALESCE_NOW); 4750 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4751 ddi_fm_service_impact(bgep->devinfo, 4752 DDI_SERVICE_UNAFFECTED); 4753 4754 if (bgep->link_update_timer < BGE_LINK_UPDATE_TIMEOUT) 4755 bgep->link_update_timer++; 4756 4757 break; 4758 4759 case BGE_CHIP_FAULT: 4760 case BGE_CHIP_ERROR: 4761 break; 4762 } 4763 4764 bge_wake_factotum(bgep); 4765 } 4766 4767 4768 /* 4769 * ========== Ioctl subfunctions ========== 4770 */ 4771 4772 #undef BGE_DBG 4773 #define BGE_DBG BGE_DBG_PPIO /* debug flag for this code */ 4774 4775 #if BGE_DEBUGGING || BGE_DO_PPIO 4776 4777 static void bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 4778 #pragma no_inline(bge_chip_peek_cfg) 4779 4780 static void 4781 bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 4782 { 4783 uint64_t regval; 4784 uint64_t regno; 4785 4786 BGE_TRACE(("bge_chip_peek_cfg($%p, $%p)", 4787 (void *)bgep, (void *)ppd)); 4788 4789 regno = ppd->pp_acc_offset; 4790 4791 switch (ppd->pp_acc_size) { 4792 case 1: 4793 regval = pci_config_get8(bgep->cfg_handle, regno); 4794 break; 4795 4796 case 2: 4797 regval = pci_config_get16(bgep->cfg_handle, regno); 4798 break; 4799 4800 case 4: 4801 regval = pci_config_get32(bgep->cfg_handle, regno); 4802 break; 4803 4804 case 8: 4805 regval = pci_config_get64(bgep->cfg_handle, regno); 4806 break; 4807 } 4808 4809 ppd->pp_acc_data = regval; 4810 } 4811 4812 static void bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 4813 #pragma no_inline(bge_chip_poke_cfg) 4814 4815 static void 4816 bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 4817 { 4818 uint64_t regval; 4819 uint64_t regno; 4820 4821 BGE_TRACE(("bge_chip_poke_cfg($%p, $%p)", 4822 (void *)bgep, (void *)ppd)); 4823 4824 regno = ppd->pp_acc_offset; 4825 regval = ppd->pp_acc_data; 4826 4827 switch (ppd->pp_acc_size) { 4828 case 1: 4829 pci_config_put8(bgep->cfg_handle, regno, regval); 4830 break; 4831 4832 case 2: 4833 pci_config_put16(bgep->cfg_handle, regno, regval); 4834 break; 4835 4836 case 4: 4837 pci_config_put32(bgep->cfg_handle, regno, regval); 4838 break; 4839 4840 case 8: 4841 pci_config_put64(bgep->cfg_handle, regno, regval); 4842 break; 4843 } 4844 } 4845 4846 static void bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd); 4847 #pragma no_inline(bge_chip_peek_reg) 4848 4849 static void 4850 bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd) 4851 { 4852 uint64_t regval; 4853 void *regaddr; 4854 4855 BGE_TRACE(("bge_chip_peek_reg($%p, $%p)", 4856 (void *)bgep, (void *)ppd)); 4857 4858 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 4859 4860 switch (ppd->pp_acc_size) { 4861 case 1: 4862 regval = ddi_get8(bgep->io_handle, regaddr); 4863 break; 4864 4865 case 2: 4866 regval = ddi_get16(bgep->io_handle, regaddr); 4867 break; 4868 4869 case 4: 4870 regval = ddi_get32(bgep->io_handle, regaddr); 4871 break; 4872 4873 case 8: 4874 regval = ddi_get64(bgep->io_handle, regaddr); 4875 break; 4876 } 4877 4878 ppd->pp_acc_data = regval; 4879 } 4880 4881 static void bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd); 4882 #pragma no_inline(bge_chip_peek_reg) 4883 4884 static void 4885 bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd) 4886 { 4887 uint64_t regval; 4888 void *regaddr; 4889 4890 BGE_TRACE(("bge_chip_poke_reg($%p, $%p)", 4891 (void *)bgep, (void *)ppd)); 4892 4893 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 4894 regval = ppd->pp_acc_data; 4895 4896 switch (ppd->pp_acc_size) { 4897 case 1: 4898 ddi_put8(bgep->io_handle, regaddr, regval); 4899 break; 4900 4901 case 2: 4902 ddi_put16(bgep->io_handle, regaddr, regval); 4903 break; 4904 4905 case 4: 4906 ddi_put32(bgep->io_handle, regaddr, regval); 4907 break; 4908 4909 case 8: 4910 ddi_put64(bgep->io_handle, regaddr, regval); 4911 break; 4912 } 4913 BGE_PCICHK(bgep); 4914 } 4915 4916 static void bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd); 4917 #pragma no_inline(bge_chip_peek_nic) 4918 4919 static void 4920 bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd) 4921 { 4922 uint64_t regoff; 4923 uint64_t regval; 4924 void *regaddr; 4925 4926 BGE_TRACE(("bge_chip_peek_nic($%p, $%p)", 4927 (void *)bgep, (void *)ppd)); 4928 4929 regoff = ppd->pp_acc_offset; 4930 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 4931 regoff &= MWBAR_GRANULE_MASK; 4932 regoff += NIC_MEM_WINDOW_OFFSET; 4933 regaddr = PIO_ADDR(bgep, regoff); 4934 4935 switch (ppd->pp_acc_size) { 4936 case 1: 4937 regval = ddi_get8(bgep->io_handle, regaddr); 4938 break; 4939 4940 case 2: 4941 regval = ddi_get16(bgep->io_handle, regaddr); 4942 break; 4943 4944 case 4: 4945 regval = ddi_get32(bgep->io_handle, regaddr); 4946 break; 4947 4948 case 8: 4949 regval = ddi_get64(bgep->io_handle, regaddr); 4950 break; 4951 } 4952 4953 ppd->pp_acc_data = regval; 4954 } 4955 4956 static void bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd); 4957 #pragma no_inline(bge_chip_poke_nic) 4958 4959 static void 4960 bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd) 4961 { 4962 uint64_t regoff; 4963 uint64_t regval; 4964 void *regaddr; 4965 4966 BGE_TRACE(("bge_chip_poke_nic($%p, $%p)", 4967 (void *)bgep, (void *)ppd)); 4968 4969 regoff = ppd->pp_acc_offset; 4970 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 4971 regoff &= MWBAR_GRANULE_MASK; 4972 regoff += NIC_MEM_WINDOW_OFFSET; 4973 regaddr = PIO_ADDR(bgep, regoff); 4974 regval = ppd->pp_acc_data; 4975 4976 switch (ppd->pp_acc_size) { 4977 case 1: 4978 ddi_put8(bgep->io_handle, regaddr, regval); 4979 break; 4980 4981 case 2: 4982 ddi_put16(bgep->io_handle, regaddr, regval); 4983 break; 4984 4985 case 4: 4986 ddi_put32(bgep->io_handle, regaddr, regval); 4987 break; 4988 4989 case 8: 4990 ddi_put64(bgep->io_handle, regaddr, regval); 4991 break; 4992 } 4993 BGE_PCICHK(bgep); 4994 } 4995 4996 static void bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd); 4997 #pragma no_inline(bge_chip_peek_mii) 4998 4999 static void 5000 bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd) 5001 { 5002 BGE_TRACE(("bge_chip_peek_mii($%p, $%p)", 5003 (void *)bgep, (void *)ppd)); 5004 5005 ppd->pp_acc_data = bge_mii_get16(bgep, ppd->pp_acc_offset/2); 5006 } 5007 5008 static void bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd); 5009 #pragma no_inline(bge_chip_poke_mii) 5010 5011 static void 5012 bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd) 5013 { 5014 BGE_TRACE(("bge_chip_poke_mii($%p, $%p)", 5015 (void *)bgep, (void *)ppd)); 5016 5017 bge_mii_put16(bgep, ppd->pp_acc_offset/2, ppd->pp_acc_data); 5018 } 5019 5020 #if BGE_SEE_IO32 5021 5022 static void bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 5023 #pragma no_inline(bge_chip_peek_seeprom) 5024 5025 static void 5026 bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 5027 { 5028 uint32_t data; 5029 int err; 5030 5031 BGE_TRACE(("bge_chip_peek_seeprom($%p, $%p)", 5032 (void *)bgep, (void *)ppd)); 5033 5034 err = bge_nvmem_rw32(bgep, BGE_SEE_READ, ppd->pp_acc_offset, &data); 5035 ppd->pp_acc_data = err ? ~0ull : data; 5036 } 5037 5038 static void bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 5039 #pragma no_inline(bge_chip_poke_seeprom) 5040 5041 static void 5042 bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 5043 { 5044 uint32_t data; 5045 5046 BGE_TRACE(("bge_chip_poke_seeprom($%p, $%p)", 5047 (void *)bgep, (void *)ppd)); 5048 5049 data = ppd->pp_acc_data; 5050 (void) bge_nvmem_rw32(bgep, BGE_SEE_WRITE, ppd->pp_acc_offset, &data); 5051 } 5052 #endif /* BGE_SEE_IO32 */ 5053 5054 #if BGE_FLASH_IO32 5055 5056 static void bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd); 5057 #pragma no_inline(bge_chip_peek_flash) 5058 5059 static void 5060 bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd) 5061 { 5062 uint32_t data; 5063 int err; 5064 5065 BGE_TRACE(("bge_chip_peek_flash($%p, $%p)", 5066 (void *)bgep, (void *)ppd)); 5067 5068 err = bge_nvmem_rw32(bgep, BGE_FLASH_READ, ppd->pp_acc_offset, &data); 5069 ppd->pp_acc_data = err ? ~0ull : data; 5070 } 5071 5072 static void bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd); 5073 #pragma no_inline(bge_chip_poke_flash) 5074 5075 static void 5076 bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd) 5077 { 5078 uint32_t data; 5079 5080 BGE_TRACE(("bge_chip_poke_flash($%p, $%p)", 5081 (void *)bgep, (void *)ppd)); 5082 5083 data = ppd->pp_acc_data; 5084 (void) bge_nvmem_rw32(bgep, BGE_FLASH_WRITE, 5085 ppd->pp_acc_offset, &data); 5086 } 5087 #endif /* BGE_FLASH_IO32 */ 5088 5089 static void bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd); 5090 #pragma no_inline(bge_chip_peek_mem) 5091 5092 static void 5093 bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd) 5094 { 5095 uint64_t regval; 5096 void *vaddr; 5097 5098 BGE_TRACE(("bge_chip_peek_bge($%p, $%p)", 5099 (void *)bgep, (void *)ppd)); 5100 5101 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 5102 5103 switch (ppd->pp_acc_size) { 5104 case 1: 5105 regval = *(uint8_t *)vaddr; 5106 break; 5107 5108 case 2: 5109 regval = *(uint16_t *)vaddr; 5110 break; 5111 5112 case 4: 5113 regval = *(uint32_t *)vaddr; 5114 break; 5115 5116 case 8: 5117 regval = *(uint64_t *)vaddr; 5118 break; 5119 } 5120 5121 BGE_DEBUG(("bge_chip_peek_mem($%p, $%p) peeked 0x%llx from $%p", 5122 (void *)bgep, (void *)ppd, regval, vaddr)); 5123 5124 ppd->pp_acc_data = regval; 5125 } 5126 5127 static void bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd); 5128 #pragma no_inline(bge_chip_poke_mem) 5129 5130 static void 5131 bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd) 5132 { 5133 uint64_t regval; 5134 void *vaddr; 5135 5136 BGE_TRACE(("bge_chip_poke_mem($%p, $%p)", 5137 (void *)bgep, (void *)ppd)); 5138 5139 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 5140 regval = ppd->pp_acc_data; 5141 5142 BGE_DEBUG(("bge_chip_poke_mem($%p, $%p) poking 0x%llx at $%p", 5143 (void *)bgep, (void *)ppd, regval, vaddr)); 5144 5145 switch (ppd->pp_acc_size) { 5146 case 1: 5147 *(uint8_t *)vaddr = (uint8_t)regval; 5148 break; 5149 5150 case 2: 5151 *(uint16_t *)vaddr = (uint16_t)regval; 5152 break; 5153 5154 case 4: 5155 *(uint32_t *)vaddr = (uint32_t)regval; 5156 break; 5157 5158 case 8: 5159 *(uint64_t *)vaddr = (uint64_t)regval; 5160 break; 5161 } 5162 } 5163 5164 static enum ioc_reply bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5165 struct iocblk *iocp); 5166 #pragma no_inline(bge_pp_ioctl) 5167 5168 static enum ioc_reply 5169 bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5170 { 5171 void (*ppfn)(bge_t *bgep, bge_peekpoke_t *ppd); 5172 bge_peekpoke_t *ppd; 5173 dma_area_t *areap; 5174 uint64_t sizemask; 5175 uint64_t mem_va; 5176 uint64_t maxoff; 5177 boolean_t peek; 5178 5179 switch (cmd) { 5180 default: 5181 /* NOTREACHED */ 5182 bge_error(bgep, "bge_pp_ioctl: invalid cmd 0x%x", cmd); 5183 return (IOC_INVAL); 5184 5185 case BGE_PEEK: 5186 peek = B_TRUE; 5187 break; 5188 5189 case BGE_POKE: 5190 peek = B_FALSE; 5191 break; 5192 } 5193 5194 /* 5195 * Validate format of ioctl 5196 */ 5197 if (iocp->ioc_count != sizeof (bge_peekpoke_t)) 5198 return (IOC_INVAL); 5199 if (mp->b_cont == NULL) 5200 return (IOC_INVAL); 5201 ppd = (void *)mp->b_cont->b_rptr; 5202 5203 /* 5204 * Validate request parameters 5205 */ 5206 switch (ppd->pp_acc_space) { 5207 default: 5208 return (IOC_INVAL); 5209 5210 case BGE_PP_SPACE_CFG: 5211 /* 5212 * Config space 5213 */ 5214 sizemask = 8|4|2|1; 5215 mem_va = 0; 5216 maxoff = PCI_CONF_HDR_SIZE; 5217 ppfn = peek ? bge_chip_peek_cfg : bge_chip_poke_cfg; 5218 break; 5219 5220 case BGE_PP_SPACE_REG: 5221 /* 5222 * Memory-mapped I/O space 5223 */ 5224 sizemask = 8|4|2|1; 5225 mem_va = 0; 5226 maxoff = RIAAR_REGISTER_MAX; 5227 ppfn = peek ? bge_chip_peek_reg : bge_chip_poke_reg; 5228 break; 5229 5230 case BGE_PP_SPACE_NIC: 5231 /* 5232 * NIC on-chip memory 5233 */ 5234 sizemask = 8|4|2|1; 5235 mem_va = 0; 5236 maxoff = MWBAR_ONCHIP_MAX; 5237 ppfn = peek ? bge_chip_peek_nic : bge_chip_poke_nic; 5238 break; 5239 5240 case BGE_PP_SPACE_MII: 5241 /* 5242 * PHY's MII registers 5243 * NB: all PHY registers are two bytes, but the 5244 * addresses increment in ones (word addressing). 5245 * So we scale the address here, then undo the 5246 * transformation inside the peek/poke functions. 5247 */ 5248 ppd->pp_acc_offset *= 2; 5249 sizemask = 2; 5250 mem_va = 0; 5251 maxoff = (MII_MAXREG+1)*2; 5252 ppfn = peek ? bge_chip_peek_mii : bge_chip_poke_mii; 5253 break; 5254 5255 #if BGE_SEE_IO32 5256 case BGE_PP_SPACE_SEEPROM: 5257 /* 5258 * Attached SEEPROM(s), if any. 5259 * NB: we use the high-order bits of the 'address' as 5260 * a device select to accommodate multiple SEEPROMS, 5261 * If each one is the maximum size (64kbytes), this 5262 * makes them appear contiguous. Otherwise, there may 5263 * be holes in the mapping. ENxS doesn't have any 5264 * SEEPROMs anyway ... 5265 */ 5266 sizemask = 4; 5267 mem_va = 0; 5268 maxoff = SEEPROM_DEV_AND_ADDR_MASK; 5269 ppfn = peek ? bge_chip_peek_seeprom : bge_chip_poke_seeprom; 5270 break; 5271 #endif /* BGE_SEE_IO32 */ 5272 5273 #if BGE_FLASH_IO32 5274 case BGE_PP_SPACE_FLASH: 5275 /* 5276 * Attached Flash device (if any); a maximum of one device 5277 * is currently supported. But it can be up to 1MB (unlike 5278 * the 64k limit on SEEPROMs) so why would you need more ;-) 5279 */ 5280 sizemask = 4; 5281 mem_va = 0; 5282 maxoff = NVM_FLASH_ADDR_MASK; 5283 ppfn = peek ? bge_chip_peek_flash : bge_chip_poke_flash; 5284 break; 5285 #endif /* BGE_FLASH_IO32 */ 5286 5287 case BGE_PP_SPACE_BGE: 5288 /* 5289 * BGE data structure! 5290 */ 5291 sizemask = 8|4|2|1; 5292 mem_va = (uintptr_t)bgep; 5293 maxoff = sizeof (*bgep); 5294 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 5295 break; 5296 5297 case BGE_PP_SPACE_STATUS: 5298 case BGE_PP_SPACE_STATISTICS: 5299 case BGE_PP_SPACE_TXDESC: 5300 case BGE_PP_SPACE_TXBUFF: 5301 case BGE_PP_SPACE_RXDESC: 5302 case BGE_PP_SPACE_RXBUFF: 5303 /* 5304 * Various DMA_AREAs 5305 */ 5306 switch (ppd->pp_acc_space) { 5307 case BGE_PP_SPACE_TXDESC: 5308 areap = &bgep->tx_desc; 5309 break; 5310 case BGE_PP_SPACE_TXBUFF: 5311 areap = &bgep->tx_buff[0]; 5312 break; 5313 case BGE_PP_SPACE_RXDESC: 5314 areap = &bgep->rx_desc[0]; 5315 break; 5316 case BGE_PP_SPACE_RXBUFF: 5317 areap = &bgep->rx_buff[0]; 5318 break; 5319 case BGE_PP_SPACE_STATUS: 5320 areap = &bgep->status_block; 5321 break; 5322 case BGE_PP_SPACE_STATISTICS: 5323 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 5324 areap = &bgep->statistics; 5325 break; 5326 } 5327 5328 sizemask = 8|4|2|1; 5329 mem_va = (uintptr_t)areap->mem_va; 5330 maxoff = areap->alength; 5331 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 5332 break; 5333 } 5334 5335 switch (ppd->pp_acc_size) { 5336 default: 5337 return (IOC_INVAL); 5338 5339 case 8: 5340 case 4: 5341 case 2: 5342 case 1: 5343 if ((ppd->pp_acc_size & sizemask) == 0) 5344 return (IOC_INVAL); 5345 break; 5346 } 5347 5348 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 5349 return (IOC_INVAL); 5350 5351 if (ppd->pp_acc_offset >= maxoff) 5352 return (IOC_INVAL); 5353 5354 if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff) 5355 return (IOC_INVAL); 5356 5357 /* 5358 * All OK - go do it! 5359 */ 5360 ppd->pp_acc_offset += mem_va; 5361 (*ppfn)(bgep, ppd); 5362 return (peek ? IOC_REPLY : IOC_ACK); 5363 } 5364 5365 static enum ioc_reply bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5366 struct iocblk *iocp); 5367 #pragma no_inline(bge_diag_ioctl) 5368 5369 static enum ioc_reply 5370 bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5371 { 5372 ASSERT(mutex_owned(bgep->genlock)); 5373 5374 switch (cmd) { 5375 default: 5376 /* NOTREACHED */ 5377 bge_error(bgep, "bge_diag_ioctl: invalid cmd 0x%x", cmd); 5378 return (IOC_INVAL); 5379 5380 case BGE_DIAG: 5381 /* 5382 * Currently a no-op 5383 */ 5384 return (IOC_ACK); 5385 5386 case BGE_PEEK: 5387 case BGE_POKE: 5388 return (bge_pp_ioctl(bgep, cmd, mp, iocp)); 5389 5390 case BGE_PHY_RESET: 5391 return (IOC_RESTART_ACK); 5392 5393 case BGE_SOFT_RESET: 5394 case BGE_HARD_RESET: 5395 /* 5396 * Reset and reinitialise the 570x hardware 5397 */ 5398 bgep->bge_chip_state = BGE_CHIP_FAULT; 5399 ddi_trigger_softintr(bgep->factotum_id); 5400 (void) bge_restart(bgep, cmd == BGE_HARD_RESET); 5401 return (IOC_ACK); 5402 } 5403 5404 /* NOTREACHED */ 5405 } 5406 5407 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 5408 5409 static enum ioc_reply bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5410 struct iocblk *iocp); 5411 #pragma no_inline(bge_mii_ioctl) 5412 5413 static enum ioc_reply 5414 bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5415 { 5416 struct bge_mii_rw *miirwp; 5417 5418 /* 5419 * Validate format of ioctl 5420 */ 5421 if (iocp->ioc_count != sizeof (struct bge_mii_rw)) 5422 return (IOC_INVAL); 5423 if (mp->b_cont == NULL) 5424 return (IOC_INVAL); 5425 miirwp = (void *)mp->b_cont->b_rptr; 5426 5427 /* 5428 * Validate request parameters ... 5429 */ 5430 if (miirwp->mii_reg > MII_MAXREG) 5431 return (IOC_INVAL); 5432 5433 switch (cmd) { 5434 default: 5435 /* NOTREACHED */ 5436 bge_error(bgep, "bge_mii_ioctl: invalid cmd 0x%x", cmd); 5437 return (IOC_INVAL); 5438 5439 case BGE_MII_READ: 5440 miirwp->mii_data = bge_mii_get16(bgep, miirwp->mii_reg); 5441 return (IOC_REPLY); 5442 5443 case BGE_MII_WRITE: 5444 bge_mii_put16(bgep, miirwp->mii_reg, miirwp->mii_data); 5445 return (IOC_ACK); 5446 } 5447 5448 /* NOTREACHED */ 5449 } 5450 5451 #if BGE_SEE_IO32 5452 5453 static enum ioc_reply bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5454 struct iocblk *iocp); 5455 #pragma no_inline(bge_see_ioctl) 5456 5457 static enum ioc_reply 5458 bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5459 { 5460 struct bge_see_rw *seerwp; 5461 5462 /* 5463 * Validate format of ioctl 5464 */ 5465 if (iocp->ioc_count != sizeof (struct bge_see_rw)) 5466 return (IOC_INVAL); 5467 if (mp->b_cont == NULL) 5468 return (IOC_INVAL); 5469 seerwp = (void *)mp->b_cont->b_rptr; 5470 5471 /* 5472 * Validate request parameters ... 5473 */ 5474 if (seerwp->see_addr & ~SEEPROM_DEV_AND_ADDR_MASK) 5475 return (IOC_INVAL); 5476 5477 switch (cmd) { 5478 default: 5479 /* NOTREACHED */ 5480 bge_error(bgep, "bge_see_ioctl: invalid cmd 0x%x", cmd); 5481 return (IOC_INVAL); 5482 5483 case BGE_SEE_READ: 5484 case BGE_SEE_WRITE: 5485 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 5486 seerwp->see_addr, &seerwp->see_data); 5487 return (IOC_REPLY); 5488 } 5489 5490 /* NOTREACHED */ 5491 } 5492 5493 #endif /* BGE_SEE_IO32 */ 5494 5495 #if BGE_FLASH_IO32 5496 5497 static enum ioc_reply bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5498 struct iocblk *iocp); 5499 #pragma no_inline(bge_flash_ioctl) 5500 5501 static enum ioc_reply 5502 bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5503 { 5504 struct bge_flash_rw *flashrwp; 5505 5506 /* 5507 * Validate format of ioctl 5508 */ 5509 if (iocp->ioc_count != sizeof (struct bge_flash_rw)) 5510 return (IOC_INVAL); 5511 if (mp->b_cont == NULL) 5512 return (IOC_INVAL); 5513 flashrwp = (void *)mp->b_cont->b_rptr; 5514 5515 /* 5516 * Validate request parameters ... 5517 */ 5518 if (flashrwp->flash_addr & ~NVM_FLASH_ADDR_MASK) 5519 return (IOC_INVAL); 5520 5521 switch (cmd) { 5522 default: 5523 /* NOTREACHED */ 5524 bge_error(bgep, "bge_flash_ioctl: invalid cmd 0x%x", cmd); 5525 return (IOC_INVAL); 5526 5527 case BGE_FLASH_READ: 5528 case BGE_FLASH_WRITE: 5529 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 5530 flashrwp->flash_addr, &flashrwp->flash_data); 5531 return (IOC_REPLY); 5532 } 5533 5534 /* NOTREACHED */ 5535 } 5536 5537 #endif /* BGE_FLASH_IO32 */ 5538 5539 enum ioc_reply bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, 5540 struct iocblk *iocp); 5541 #pragma no_inline(bge_chip_ioctl) 5542 5543 enum ioc_reply 5544 bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 5545 { 5546 int cmd; 5547 5548 BGE_TRACE(("bge_chip_ioctl($%p, $%p, $%p, $%p)", 5549 (void *)bgep, (void *)wq, (void *)mp, (void *)iocp)); 5550 5551 ASSERT(mutex_owned(bgep->genlock)); 5552 5553 cmd = iocp->ioc_cmd; 5554 switch (cmd) { 5555 default: 5556 /* NOTREACHED */ 5557 bge_error(bgep, "bge_chip_ioctl: invalid cmd 0x%x", cmd); 5558 return (IOC_INVAL); 5559 5560 case BGE_DIAG: 5561 case BGE_PEEK: 5562 case BGE_POKE: 5563 case BGE_PHY_RESET: 5564 case BGE_SOFT_RESET: 5565 case BGE_HARD_RESET: 5566 #if BGE_DEBUGGING || BGE_DO_PPIO 5567 return (bge_diag_ioctl(bgep, cmd, mp, iocp)); 5568 #else 5569 return (IOC_INVAL); 5570 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 5571 5572 case BGE_MII_READ: 5573 case BGE_MII_WRITE: 5574 return (bge_mii_ioctl(bgep, cmd, mp, iocp)); 5575 5576 #if BGE_SEE_IO32 5577 case BGE_SEE_READ: 5578 case BGE_SEE_WRITE: 5579 return (bge_see_ioctl(bgep, cmd, mp, iocp)); 5580 #endif /* BGE_SEE_IO32 */ 5581 5582 #if BGE_FLASH_IO32 5583 case BGE_FLASH_READ: 5584 case BGE_FLASH_WRITE: 5585 return (bge_flash_ioctl(bgep, cmd, mp, iocp)); 5586 #endif /* BGE_FLASH_IO32 */ 5587 } 5588 5589 /* NOTREACHED */ 5590 } 5591 5592 /* ARGSUSED */ 5593 void 5594 bge_chip_blank(void *arg, time_t ticks, uint_t count, int flag) 5595 { 5596 recv_ring_t *rrp = arg; 5597 bge_t *bgep = rrp->bgep; 5598 5599 mutex_enter(bgep->genlock); 5600 rrp->poll_flag = flag; 5601 #ifdef NOT_YET 5602 /* 5603 * XXX-Sunay: Since most broadcom cards support only one 5604 * interrupt but multiple rx rings, we can't disable the 5605 * physical interrupt. This need to be done via capability 5606 * negotiation depending on the NIC. 5607 */ 5608 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, ticks); 5609 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, count); 5610 #endif 5611 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5612 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 5613 mutex_exit(bgep->genlock); 5614 } 5615 5616 #ifdef BGE_IPMI_ASF 5617 5618 uint32_t 5619 bge_nic_read32(bge_t *bgep, bge_regno_t addr) 5620 { 5621 uint32_t data; 5622 5623 #ifndef __sparc 5624 if (!bgep->asf_wordswapped) { 5625 /* a workaround word swap error */ 5626 if (addr & 4) 5627 addr = addr - 4; 5628 else 5629 addr = addr + 4; 5630 } 5631 #endif 5632 5633 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr); 5634 data = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR); 5635 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0); 5636 5637 data = LE_32(data); 5638 return (data); 5639 } 5640 5641 void 5642 bge_asf_update_status(bge_t *bgep) 5643 { 5644 uint32_t event; 5645 5646 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_ALIVE); 5647 bge_nic_put32(bgep, BGE_CMD_LENGTH_MAILBOX, 4); 5648 bge_nic_put32(bgep, BGE_CMD_DATA_MAILBOX, 3); 5649 5650 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5651 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 5652 } 5653 5654 5655 /* 5656 * The driver is supposed to notify ASF that the OS is still running 5657 * every three seconds, otherwise the management server may attempt 5658 * to reboot the machine. If it hasn't actually failed, this is 5659 * not a desirable result. However, this isn't running as a real-time 5660 * thread, and even if it were, it might not be able to generate the 5661 * heartbeat in a timely manner due to system load. As it isn't a 5662 * significant strain on the machine, we will set the interval to half 5663 * of the required value. 5664 */ 5665 void 5666 bge_asf_heartbeat(void *arg) 5667 { 5668 bge_t *bgep = (bge_t *)arg; 5669 5670 mutex_enter(bgep->genlock); 5671 bge_asf_update_status((bge_t *)bgep); 5672 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5673 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 5674 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) 5675 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 5676 mutex_exit(bgep->genlock); 5677 ((bge_t *)bgep)->asf_timeout_id = timeout(bge_asf_heartbeat, bgep, 5678 drv_usectohz(BGE_ASF_HEARTBEAT_INTERVAL)); 5679 } 5680 5681 5682 void 5683 bge_asf_stop_timer(bge_t *bgep) 5684 { 5685 timeout_id_t tmp_id = 0; 5686 5687 while ((bgep->asf_timeout_id != 0) && 5688 (tmp_id != bgep->asf_timeout_id)) { 5689 tmp_id = bgep->asf_timeout_id; 5690 (void) untimeout(tmp_id); 5691 } 5692 bgep->asf_timeout_id = 0; 5693 } 5694 5695 5696 5697 /* 5698 * This function should be placed at the earliest position of bge_attach(). 5699 */ 5700 void 5701 bge_asf_get_config(bge_t *bgep) 5702 { 5703 uint32_t nicsig; 5704 uint32_t niccfg; 5705 5706 bgep->asf_enabled = B_FALSE; 5707 nicsig = bge_nic_read32(bgep, BGE_NIC_DATA_SIG_ADDR); 5708 if (nicsig == BGE_NIC_DATA_SIG) { 5709 niccfg = bge_nic_read32(bgep, BGE_NIC_DATA_NIC_CFG_ADDR); 5710 if (niccfg & BGE_NIC_CFG_ENABLE_ASF) 5711 /* 5712 * Here, we don't consider BAXTER, because BGE haven't 5713 * supported BAXTER (that is 5752). Also, as I know, 5714 * BAXTER doesn't support ASF feature. 5715 */ 5716 bgep->asf_enabled = B_TRUE; 5717 else 5718 bgep->asf_enabled = B_FALSE; 5719 } else 5720 bgep->asf_enabled = B_FALSE; 5721 } 5722 5723 5724 void 5725 bge_asf_pre_reset_operations(bge_t *bgep, uint32_t mode) 5726 { 5727 uint32_t tries; 5728 uint32_t event; 5729 5730 ASSERT(bgep->asf_enabled); 5731 5732 /* Issues "pause firmware" command and wait for ACK */ 5733 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_PAUSE_FW); 5734 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5735 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 5736 5737 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5738 tries = 0; 5739 while ((event & RRER_ASF_EVENT) && (tries < 100)) { 5740 drv_usecwait(1); 5741 tries ++; 5742 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5743 } 5744 5745 bge_nic_put32(bgep, BGE_FIRMWARE_MAILBOX, 5746 BGE_MAGIC_NUM_FIRMWARE_INIT_DONE); 5747 5748 if (bgep->asf_newhandshake) { 5749 switch (mode) { 5750 case BGE_INIT_RESET: 5751 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5752 BGE_DRV_STATE_START); 5753 break; 5754 case BGE_SHUTDOWN_RESET: 5755 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5756 BGE_DRV_STATE_UNLOAD); 5757 break; 5758 case BGE_SUSPEND_RESET: 5759 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5760 BGE_DRV_STATE_SUSPEND); 5761 break; 5762 default: 5763 break; 5764 } 5765 } 5766 } 5767 5768 5769 void 5770 bge_asf_post_reset_old_mode(bge_t *bgep, uint32_t mode) 5771 { 5772 switch (mode) { 5773 case BGE_INIT_RESET: 5774 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5775 BGE_DRV_STATE_START); 5776 break; 5777 case BGE_SHUTDOWN_RESET: 5778 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5779 BGE_DRV_STATE_UNLOAD); 5780 break; 5781 case BGE_SUSPEND_RESET: 5782 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5783 BGE_DRV_STATE_SUSPEND); 5784 break; 5785 default: 5786 break; 5787 } 5788 } 5789 5790 5791 void 5792 bge_asf_post_reset_new_mode(bge_t *bgep, uint32_t mode) 5793 { 5794 switch (mode) { 5795 case BGE_INIT_RESET: 5796 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5797 BGE_DRV_STATE_START_DONE); 5798 break; 5799 case BGE_SHUTDOWN_RESET: 5800 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5801 BGE_DRV_STATE_UNLOAD_DONE); 5802 break; 5803 default: 5804 break; 5805 } 5806 } 5807 5808 #endif /* BGE_IPMI_ASF */ 5809