1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include "sys/bge_impl2.h" 30 31 #define PIO_ADDR(bgep, offset) ((void *)((caddr_t)(bgep)->io_regs+(offset))) 32 33 /* 34 * Future features ... ? 35 */ 36 #define BGE_CFG_IO8 1 /* 8/16-bit cfg space BIS/BIC */ 37 #define BGE_IND_IO32 0 /* indirect access code */ 38 #define BGE_SEE_IO32 1 /* SEEPROM access code */ 39 #define BGE_FLASH_IO32 1 /* FLASH access code */ 40 41 /* 42 * BGE MSI tunable: 43 * 44 * By default MSI is enabled on all supported platforms but it is disabled 45 * for some Broadcom chips due to known MSI hardware issues. Currently MSI 46 * is enabled only for 5714C A2 and 5715C A2 broadcom chips. 47 */ 48 #if defined(__sparc) 49 boolean_t bge_enable_msi = B_TRUE; 50 #else 51 boolean_t bge_enable_msi = B_FALSE; 52 #endif 53 54 /* 55 * Property names 56 */ 57 static char knownids_propname[] = "bge-known-subsystems"; 58 59 /* 60 * Patchable globals: 61 * 62 * bge_autorecover 63 * Enables/disables automatic recovery after fault detection 64 * 65 * bge_mlcr_default 66 * Value to program into the MLCR; controls the chip's GPIO pins 67 * 68 * bge_dma_{rd,wr}prio 69 * Relative priorities of DMA reads & DMA writes respectively. 70 * These may each be patched to any value 0-3. Equal values 71 * will give "fair" (round-robin) arbitration for PCI access. 72 * Unequal values will give one or the other function priority. 73 * 74 * bge_dma_rwctrl 75 * Value to put in the Read/Write DMA control register. See 76 * the Broadcom PRM for things you can fiddle with in this 77 * register ... 78 * 79 * bge_{tx,rx}_{count,ticks}_{norm,intr} 80 * Send/receive interrupt coalescing parameters. Counts are 81 * #s of descriptors, ticks are in microseconds. *norm* values 82 * apply between status updates/interrupts; the *intr* values 83 * refer to the 'during-interrupt' versions - see the PRM. 84 * 85 * NOTE: these values have been determined by measurement. They 86 * differ significantly from the values recommended in the PRM. 87 */ 88 static uint32_t bge_autorecover = 1; 89 static uint32_t bge_mlcr_default = MLCR_DEFAULT; 90 static uint32_t bge_mlcr_default_5714 = MLCR_DEFAULT_5714; 91 92 static uint32_t bge_dma_rdprio = 1; 93 static uint32_t bge_dma_wrprio = 0; 94 static uint32_t bge_dma_rwctrl = PDRWCR_VAR_DEFAULT; 95 static uint32_t bge_dma_rwctrl_5721 = PDRWCR_VAR_5721; 96 static uint32_t bge_dma_rwctrl_5714 = PDRWCR_VAR_5714; 97 static uint32_t bge_dma_rwctrl_5715 = PDRWCR_VAR_5715; 98 99 uint32_t bge_rx_ticks_norm = 128; 100 uint32_t bge_tx_ticks_norm = 2048; /* 8 for FJ2+ !?!? */ 101 uint32_t bge_rx_count_norm = 8; 102 uint32_t bge_tx_count_norm = 128; 103 104 static uint32_t bge_rx_ticks_intr = 128; 105 static uint32_t bge_tx_ticks_intr = 0; /* 8 for FJ2+ !?!? */ 106 static uint32_t bge_rx_count_intr = 2; 107 static uint32_t bge_tx_count_intr = 0; 108 109 /* 110 * Memory pool configuration parameters. 111 * 112 * These are generally specific to each member of the chip family, since 113 * each one may have a different memory size/configuration. 114 * 115 * Setting the mbuf pool length for a specific type of chip to 0 inhibits 116 * the driver from programming the various registers; instead they are left 117 * at their hardware defaults. This is the preferred option for later chips 118 * (5705+), whereas the older chips *required* these registers to be set, 119 * since the h/w default was 0 ;-( 120 */ 121 static uint32_t bge_mbuf_pool_base = MBUF_POOL_BASE_DEFAULT; 122 static uint32_t bge_mbuf_pool_base_5704 = MBUF_POOL_BASE_5704; 123 static uint32_t bge_mbuf_pool_base_5705 = MBUF_POOL_BASE_5705; 124 static uint32_t bge_mbuf_pool_base_5721 = MBUF_POOL_BASE_5721; 125 static uint32_t bge_mbuf_pool_len = MBUF_POOL_LENGTH_DEFAULT; 126 static uint32_t bge_mbuf_pool_len_5704 = MBUF_POOL_LENGTH_5704; 127 static uint32_t bge_mbuf_pool_len_5705 = 0; /* use h/w default */ 128 static uint32_t bge_mbuf_pool_len_5721 = 0; 129 130 /* 131 * Various high and low water marks, thresholds, etc ... 132 * 133 * Note: these are taken from revision 7 of the PRM, and some are different 134 * from both the values in earlier PRMs *and* those determined experimentally 135 * and used in earlier versions of this driver ... 136 */ 137 static uint32_t bge_mbuf_hi_water = MBUF_HIWAT_DEFAULT; 138 static uint32_t bge_mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_DEFAULT; 139 static uint32_t bge_mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_DEFAULT; 140 141 static uint32_t bge_dmad_lo_water = DMAD_POOL_LOWAT_DEFAULT; 142 static uint32_t bge_dmad_hi_water = DMAD_POOL_HIWAT_DEFAULT; 143 static uint32_t bge_lowat_recv_frames = LOWAT_MAX_RECV_FRAMES_DEFAULT; 144 145 static uint32_t bge_replenish_std = STD_RCV_BD_REPLENISH_DEFAULT; 146 static uint32_t bge_replenish_mini = MINI_RCV_BD_REPLENISH_DEFAULT; 147 static uint32_t bge_replenish_jumbo = JUMBO_RCV_BD_REPLENISH_DEFAULT; 148 149 static uint32_t bge_watchdog_count = 1 << 16; 150 static uint16_t bge_dma_miss_limit = 20; 151 152 static uint32_t bge_stop_start_on_sync = 0; 153 154 boolean_t bge_jumbo_enable = B_TRUE; 155 static uint32_t bge_default_jumbo_size = BGE_JUMBO_BUFF_SIZE; 156 157 /* 158 * ========== Low-level chip & ring buffer manipulation ========== 159 */ 160 161 #define BGE_DBG BGE_DBG_REGS /* debug flag for this code */ 162 163 164 /* 165 * Config space read-modify-write routines 166 */ 167 168 #if BGE_CFG_IO8 169 170 /* 171 * 8- and 16-bit set/clr operations are not used; all the config registers 172 * that we need to do bit-twiddling on are 32 bits wide. I'll leave the 173 * code here, though, in case we ever find that we do want it after all ... 174 */ 175 176 static void bge_cfg_set8(bge_t *bgep, bge_regno_t regno, uint8_t bits); 177 #pragma inline(bge_cfg_set8) 178 179 static void 180 bge_cfg_set8(bge_t *bgep, bge_regno_t regno, uint8_t bits) 181 { 182 uint8_t regval; 183 184 BGE_TRACE(("bge_cfg_set8($%p, 0x%lx, 0x%x)", 185 (void *)bgep, regno, bits)); 186 187 regval = pci_config_get8(bgep->cfg_handle, regno); 188 189 BGE_DEBUG(("bge_cfg_set8($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 190 (void *)bgep, regno, bits, regval, regval | bits)); 191 192 regval |= bits; 193 pci_config_put8(bgep->cfg_handle, regno, regval); 194 } 195 196 static void bge_cfg_clr8(bge_t *bgep, bge_regno_t regno, uint8_t bits); 197 #pragma inline(bge_cfg_clr8) 198 199 static void 200 bge_cfg_clr8(bge_t *bgep, bge_regno_t regno, uint8_t bits) 201 { 202 uint8_t regval; 203 204 BGE_TRACE(("bge_cfg_clr8($%p, 0x%lx, 0x%x)", 205 (void *)bgep, regno, bits)); 206 207 regval = pci_config_get8(bgep->cfg_handle, regno); 208 209 BGE_DEBUG(("bge_cfg_clr8($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 210 (void *)bgep, regno, bits, regval, regval & ~bits)); 211 212 regval &= ~bits; 213 pci_config_put8(bgep->cfg_handle, regno, regval); 214 } 215 216 static void bge_cfg_set16(bge_t *bgep, bge_regno_t regno, uint16_t bits); 217 #pragma inline(bge_cfg_set16) 218 219 static void 220 bge_cfg_set16(bge_t *bgep, bge_regno_t regno, uint16_t bits) 221 { 222 uint16_t regval; 223 224 BGE_TRACE(("bge_cfg_set16($%p, 0x%lx, 0x%x)", 225 (void *)bgep, regno, bits)); 226 227 regval = pci_config_get16(bgep->cfg_handle, regno); 228 229 BGE_DEBUG(("bge_cfg_set16($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 230 (void *)bgep, regno, bits, regval, regval | bits)); 231 232 regval |= bits; 233 pci_config_put16(bgep->cfg_handle, regno, regval); 234 } 235 236 static void bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits); 237 #pragma inline(bge_cfg_clr16) 238 239 static void 240 bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits) 241 { 242 uint16_t regval; 243 244 BGE_TRACE(("bge_cfg_clr16($%p, 0x%lx, 0x%x)", 245 (void *)bgep, regno, bits)); 246 247 regval = pci_config_get16(bgep->cfg_handle, regno); 248 249 BGE_DEBUG(("bge_cfg_clr16($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 250 (void *)bgep, regno, bits, regval, regval & ~bits)); 251 252 regval &= ~bits; 253 pci_config_put16(bgep->cfg_handle, regno, regval); 254 } 255 256 #endif /* BGE_CFG_IO8 */ 257 258 static void bge_cfg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 259 #pragma inline(bge_cfg_set32) 260 261 static void 262 bge_cfg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 263 { 264 uint32_t regval; 265 266 BGE_TRACE(("bge_cfg_set32($%p, 0x%lx, 0x%x)", 267 (void *)bgep, regno, bits)); 268 269 regval = pci_config_get32(bgep->cfg_handle, regno); 270 271 BGE_DEBUG(("bge_cfg_set32($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 272 (void *)bgep, regno, bits, regval, regval | bits)); 273 274 regval |= bits; 275 pci_config_put32(bgep->cfg_handle, regno, regval); 276 } 277 278 static void bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 279 #pragma inline(bge_cfg_clr32) 280 281 static void 282 bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 283 { 284 uint32_t regval; 285 286 BGE_TRACE(("bge_cfg_clr32($%p, 0x%lx, 0x%x)", 287 (void *)bgep, regno, bits)); 288 289 regval = pci_config_get32(bgep->cfg_handle, regno); 290 291 BGE_DEBUG(("bge_cfg_clr32($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 292 (void *)bgep, regno, bits, regval, regval & ~bits)); 293 294 regval &= ~bits; 295 pci_config_put32(bgep->cfg_handle, regno, regval); 296 } 297 298 #if BGE_IND_IO32 299 300 /* 301 * Indirect access to registers & RISC scratchpads, using config space 302 * accesses only. 303 * 304 * This isn't currently used, but someday we might want to use it for 305 * restoring the Subsystem Device/Vendor registers (which aren't directly 306 * writable in Config Space), or for downloading firmware into the RISCs 307 * 308 * In any case there are endian issues to be resolved before this code is 309 * enabled; the bizarre way that bytes get twisted by this chip AND by 310 * the PCI bridge in SPARC systems mean that we shouldn't enable it until 311 * it's been thoroughly tested for all access sizes on all supported 312 * architectures (SPARC *and* x86!). 313 */ 314 static uint32_t bge_ind_get32(bge_t *bgep, bge_regno_t regno); 315 #pragma inline(bge_ind_get32) 316 317 static uint32_t 318 bge_ind_get32(bge_t *bgep, bge_regno_t regno) 319 { 320 uint32_t val; 321 322 BGE_TRACE(("bge_ind_get32($%p, 0x%lx)", (void *)bgep, regno)); 323 324 ASSERT(mutex_owned(bgep->genlock)); 325 326 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 327 val = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_RIADR); 328 329 BGE_DEBUG(("bge_ind_get32($%p, 0x%lx) => 0x%x", 330 (void *)bgep, regno, val)); 331 332 return (val); 333 } 334 335 static void bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val); 336 #pragma inline(bge_ind_put32) 337 338 static void 339 bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val) 340 { 341 BGE_TRACE(("bge_ind_put32($%p, 0x%lx, 0x%x)", 342 (void *)bgep, regno, val)); 343 344 ASSERT(mutex_owned(bgep->genlock)); 345 346 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 347 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIADR, val); 348 } 349 350 #endif /* BGE_IND_IO32 */ 351 352 #if BGE_DEBUGGING 353 354 static void bge_pci_check(bge_t *bgep); 355 #pragma no_inline(bge_pci_check) 356 357 static void 358 bge_pci_check(bge_t *bgep) 359 { 360 uint16_t pcistatus; 361 362 pcistatus = pci_config_get16(bgep->cfg_handle, PCI_CONF_STAT); 363 if ((pcistatus & (PCI_STAT_R_MAST_AB | PCI_STAT_R_TARG_AB)) != 0) 364 BGE_DEBUG(("bge_pci_check($%p): PCI status 0x%x", 365 (void *)bgep, pcistatus)); 366 } 367 368 #endif /* BGE_DEBUGGING */ 369 370 /* 371 * Perform first-stage chip (re-)initialisation, using only config-space 372 * accesses: 373 * 374 * + Read the vendor/device/revision/subsystem/cache-line-size registers, 375 * returning the data in the structure pointed to by <idp>. 376 * + Configure the target-mode endianness (swap) options. 377 * + Disable interrupts and enable Memory Space accesses. 378 * + Enable or disable Bus Mastering according to the <enable_dma> flag. 379 * 380 * This sequence is adapted from Broadcom document 570X-PG102-R, 381 * page 102, steps 1-3, 6-8 and 11-13. The omitted parts of the sequence 382 * are 4 and 5 (Reset Core and wait) which are handled elsewhere. 383 * 384 * This function MUST be called before any non-config-space accesses 385 * are made; on this first call <enable_dma> is B_FALSE, and it 386 * effectively performs steps 3-1(!) of the initialisation sequence 387 * (the rest are not required but should be harmless). 388 * 389 * It MUST also be called after a chip reset, as this disables 390 * Memory Space cycles! In this case, <enable_dma> is B_TRUE, and 391 * it is effectively performing steps 6-8. 392 */ 393 void bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma); 394 #pragma no_inline(bge_chip_cfg_init) 395 396 void 397 bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma) 398 { 399 ddi_acc_handle_t handle; 400 uint16_t command; 401 uint32_t mhcr; 402 uint16_t value16; 403 int i; 404 405 BGE_TRACE(("bge_chip_cfg_init($%p, $%p, %d)", 406 (void *)bgep, (void *)cidp, enable_dma)); 407 408 /* 409 * Step 3: save PCI cache line size and subsystem vendor ID 410 * 411 * Read all the config-space registers that characterise the 412 * chip, specifically vendor/device/revision/subsystem vendor 413 * and subsystem device id. We expect (but don't check) that 414 * (vendor == VENDOR_ID_BROADCOM) && (device == DEVICE_ID_5704) 415 * 416 * Also save all bus-transaction related registers (cache-line 417 * size, bus-grant/latency parameters, etc). Some of these are 418 * cleared by reset, so we'll have to restore them later. This 419 * comes from the Broadcom document 570X-PG102-R ... 420 * 421 * Note: Broadcom document 570X-PG102-R seems to be in error 422 * here w.r.t. the offsets of the Subsystem Vendor ID and 423 * Subsystem (Device) ID registers, which are the opposite way 424 * round according to the PCI standard. For good measure, we 425 * save/restore both anyway. 426 */ 427 handle = bgep->cfg_handle; 428 429 mhcr = pci_config_get32(handle, PCI_CONF_BGE_MHCR); 430 cidp->asic_rev = mhcr & MHCR_CHIP_REV_MASK; 431 cidp->businfo = pci_config_get32(handle, PCI_CONF_BGE_PCISTATE); 432 cidp->command = pci_config_get16(handle, PCI_CONF_COMM); 433 434 cidp->vendor = pci_config_get16(handle, PCI_CONF_VENID); 435 cidp->device = pci_config_get16(handle, PCI_CONF_DEVID); 436 cidp->subven = pci_config_get16(handle, PCI_CONF_SUBVENID); 437 cidp->subdev = pci_config_get16(handle, PCI_CONF_SUBSYSID); 438 cidp->revision = pci_config_get8(handle, PCI_CONF_REVID); 439 cidp->clsize = pci_config_get8(handle, PCI_CONF_CACHE_LINESZ); 440 cidp->latency = pci_config_get8(handle, PCI_CONF_LATENCY_TIMER); 441 442 BGE_DEBUG(("bge_chip_cfg_init: %s bus is %s and %s; #INTA is %s", 443 cidp->businfo & PCISTATE_BUS_IS_PCI ? "PCI" : "PCI-X", 444 cidp->businfo & PCISTATE_BUS_IS_FAST ? "fast" : "slow", 445 cidp->businfo & PCISTATE_BUS_IS_32_BIT ? "narrow" : "wide", 446 cidp->businfo & PCISTATE_INTA_STATE ? "high" : "low")); 447 BGE_DEBUG(("bge_chip_cfg_init: vendor 0x%x device 0x%x revision 0x%x", 448 cidp->vendor, cidp->device, cidp->revision)); 449 BGE_DEBUG(("bge_chip_cfg_init: subven 0x%x subdev 0x%x asic_rev 0x%x", 450 cidp->subven, cidp->subdev, cidp->asic_rev)); 451 BGE_DEBUG(("bge_chip_cfg_init: clsize %d latency %d command 0x%x", 452 cidp->clsize, cidp->latency, cidp->command)); 453 454 /* 455 * Step 2 (also step 6): disable and clear interrupts. 456 * Steps 11-13: configure PIO endianness options, and enable 457 * indirect register access. We'll also select any other 458 * options controlled by the MHCR (e.g. tagged status, mask 459 * interrupt mode) at this stage ... 460 * 461 * Note: internally, the chip is 64-bit and BIG-endian, but 462 * since it talks to the host over a (LITTLE-endian) PCI bus, 463 * it normally swaps bytes around at the PCI interface. 464 * However, the PCI host bridge on SPARC systems normally 465 * swaps the byte lanes around too, since SPARCs are also 466 * BIG-endian. So it turns out that on SPARC, the right 467 * option is to tell the chip to swap (and the host bridge 468 * will swap back again), whereas on x86 we ask the chip 469 * NOT to swap, so the natural little-endianness of the 470 * PCI bus is assumed. Then the only thing that doesn't 471 * automatically work right is access to an 8-byte register 472 * by a little-endian host; but we don't want to set the 473 * MHCR_ENABLE_REGISTER_WORD_SWAP bit because then 4-byte 474 * accesses don't go where expected ;-( So we live with 475 * that, and perform word-swaps in software in the few cases 476 * where a chip register is defined as an 8-byte value -- 477 * see the code below for details ... 478 * 479 * Note: the meaning of the 'MASK_INTERRUPT_MODE' bit isn't 480 * very clear in the register description in the PRM, but 481 * Broadcom document 570X-PG104-R page 248 explains a little 482 * more (under "Broadcom Mask Mode"). The bit changes the way 483 * the MASK_PCI_INT_OUTPUT bit works: with MASK_INTERRUPT_MODE 484 * clear, the chip interprets MASK_PCI_INT_OUTPUT in the same 485 * way as the 5700 did, which isn't very convenient. Setting 486 * the MASK_INTERRUPT_MODE bit makes the MASK_PCI_INT_OUTPUT 487 * bit do just what its name says -- MASK the PCI #INTA output 488 * (i.e. deassert the signal at the pin) leaving all internal 489 * state unchanged. This is much more convenient for our 490 * interrupt handler, so we set MASK_INTERRUPT_MODE here. 491 * 492 * Note: the inconvenient semantics of the interrupt mailbox 493 * (nonzero disables and acknowledges/clears the interrupt, 494 * zero enables AND CLEARS it) would make race conditions 495 * likely in the interrupt handler: 496 * 497 * (1) acknowledge & disable interrupts 498 * (2) while (more to do) 499 * process packets 500 * (3) enable interrupts -- also clears pending 501 * 502 * If the chip received more packets and internally generated 503 * an interrupt between the check at (2) and the mbox write 504 * at (3), this interrupt would be lost :-( 505 * 506 * The best way to avoid this is to use TAGGED STATUS mode, 507 * where the chip includes a unique tag in each status block 508 * update, and the host, when re-enabling interrupts, passes 509 * the last tag it saw back to the chip; then the chip can 510 * see whether the host is truly up to date, and regenerate 511 * its interrupt if not. 512 */ 513 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 514 MHCR_ENABLE_TAGGED_STATUS_MODE | 515 MHCR_MASK_INTERRUPT_MODE | 516 MHCR_CLEAR_INTERRUPT_INTA; 517 518 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 519 mhcr |= MHCR_MASK_PCI_INT_OUTPUT; 520 521 #ifdef _BIG_ENDIAN 522 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 523 #endif /* _BIG_ENDIAN */ 524 525 pci_config_put32(handle, PCI_CONF_BGE_MHCR, mhcr); 526 527 #ifdef BGE_IPMI_ASF 528 bgep->asf_wordswapped = B_FALSE; 529 #endif 530 /* 531 * Step 1 (also step 7): Enable PCI Memory Space accesses 532 * Disable Memory Write/Invalidate 533 * Enable or disable Bus Mastering 534 * 535 * Note that all other bits are taken from the original value saved 536 * the first time through here, rather than from the current register 537 * value, 'cos that will have been cleared by a soft RESET since. 538 * In this way we preserve the OBP/nexus-parent's preferred settings 539 * of the parity-error and system-error enable bits across multiple 540 * chip RESETs. 541 */ 542 command = bgep->chipid.command | PCI_COMM_MAE; 543 command &= ~(PCI_COMM_ME|PCI_COMM_MEMWR_INVAL); 544 if (enable_dma) 545 command |= PCI_COMM_ME; 546 /* 547 * on BCM5714 revision A0, false parity error gets generated 548 * due to a logic bug. Provide a workaround by disabling parity 549 * error. 550 */ 551 if (((cidp->device == DEVICE_ID_5714C) || 552 (cidp->device == DEVICE_ID_5714S)) && 553 (cidp->revision == REVISION_ID_5714_A0)) { 554 command &= ~PCI_COMM_PARITY_DETECT; 555 } 556 pci_config_put16(handle, PCI_CONF_COMM, command); 557 558 /* 559 * On some PCI-E device, there were instances when 560 * the device was still link training. 561 */ 562 if (bgep->chipid.pci_type == BGE_PCI_E) { 563 i = 0; 564 value16 = pci_config_get16(handle, PCI_CONF_COMM); 565 while ((value16 != command) && (i < 100)) { 566 drv_usecwait(200); 567 value16 = pci_config_get16(handle, PCI_CONF_COMM); 568 ++i; 569 } 570 } 571 572 /* 573 * Clear any remaining error status bits 574 */ 575 pci_config_put16(handle, PCI_CONF_STAT, ~0); 576 577 /* 578 * Do following if and only if the device is NOT BCM5714C OR 579 * BCM5715C 580 */ 581 if (!((cidp->device == DEVICE_ID_5714C) || 582 (cidp->device == DEVICE_ID_5715C))) { 583 /* 584 * Make sure these indirect-access registers are sane 585 * rather than random after power-up or reset 586 */ 587 pci_config_put32(handle, PCI_CONF_BGE_RIAAR, 0); 588 pci_config_put32(handle, PCI_CONF_BGE_MWBAR, 0); 589 } 590 /* 591 * Step 8: Disable PCI-X/PCI-E Relaxed Ordering 592 */ 593 bge_cfg_clr16(bgep, PCIX_CONF_COMM, PCIX_COMM_RELAXED); 594 595 if (cidp->pci_type == BGE_PCI_E) 596 bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL, 597 DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED); 598 } 599 600 #ifdef __amd64 601 /* 602 * Distinguish CPU types 603 * 604 * These use to distinguish AMD64 or Intel EM64T of CPU running mode. 605 * If CPU runs on Intel EM64T mode,the 64bit operation cannot works fine 606 * for PCI-Express based network interface card. This is the work-around 607 * for those nics. 608 */ 609 static boolean_t bge_get_em64t_type(void); 610 #pragma inline(bge_get_em64t_type) 611 612 static boolean_t 613 bge_get_em64t_type(void) 614 { 615 616 return (x86_vendor == X86_VENDOR_Intel); 617 } 618 #endif 619 620 /* 621 * Operating register get/set access routines 622 */ 623 624 uint32_t bge_reg_get32(bge_t *bgep, bge_regno_t regno); 625 #pragma inline(bge_reg_get32) 626 627 uint32_t 628 bge_reg_get32(bge_t *bgep, bge_regno_t regno) 629 { 630 BGE_TRACE(("bge_reg_get32($%p, 0x%lx)", 631 (void *)bgep, regno)); 632 633 return (ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno))); 634 } 635 636 void bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data); 637 #pragma inline(bge_reg_put32) 638 639 void 640 bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data) 641 { 642 BGE_TRACE(("bge_reg_put32($%p, 0x%lx, 0x%x)", 643 (void *)bgep, regno, data)); 644 645 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), data); 646 BGE_PCICHK(bgep); 647 } 648 649 void bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 650 #pragma inline(bge_reg_set32) 651 652 void 653 bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 654 { 655 uint32_t regval; 656 657 BGE_TRACE(("bge_reg_set32($%p, 0x%lx, 0x%x)", 658 (void *)bgep, regno, bits)); 659 660 regval = bge_reg_get32(bgep, regno); 661 regval |= bits; 662 bge_reg_put32(bgep, regno, regval); 663 } 664 665 void bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 666 #pragma inline(bge_reg_clr32) 667 668 void 669 bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 670 { 671 uint32_t regval; 672 673 BGE_TRACE(("bge_reg_clr32($%p, 0x%lx, 0x%x)", 674 (void *)bgep, regno, bits)); 675 676 regval = bge_reg_get32(bgep, regno); 677 regval &= ~bits; 678 bge_reg_put32(bgep, regno, regval); 679 } 680 681 static uint64_t bge_reg_get64(bge_t *bgep, bge_regno_t regno); 682 #pragma inline(bge_reg_get64) 683 684 static uint64_t 685 bge_reg_get64(bge_t *bgep, bge_regno_t regno) 686 { 687 uint64_t regval; 688 689 #ifdef __amd64 690 if (bge_get_em64t_type()) { 691 regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4)); 692 regval <<= 32; 693 regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 694 } else { 695 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 696 } 697 #else 698 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 699 #endif 700 701 #ifdef _LITTLE_ENDIAN 702 regval = (regval >> 32) | (regval << 32); 703 #endif /* _LITTLE_ENDIAN */ 704 705 BGE_TRACE(("bge_reg_get64($%p, 0x%lx) = 0x%016llx", 706 (void *)bgep, regno, regval)); 707 708 return (regval); 709 } 710 711 static void bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data); 712 #pragma inline(bge_reg_put64) 713 714 static void 715 bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data) 716 { 717 BGE_TRACE(("bge_reg_put64($%p, 0x%lx, 0x%016llx)", 718 (void *)bgep, regno, data)); 719 720 #ifdef _LITTLE_ENDIAN 721 data = ((data >> 32) | (data << 32)); 722 #endif /* _LITTLE_ENDIAN */ 723 724 #ifdef __amd64 725 if (bge_get_em64t_type()) { 726 ddi_put32(bgep->io_handle, 727 PIO_ADDR(bgep, regno), (uint32_t)data); 728 BGE_PCICHK(bgep); 729 ddi_put32(bgep->io_handle, 730 PIO_ADDR(bgep, regno + 4), (uint32_t)(data >> 32)); 731 732 } else { 733 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 734 } 735 #else 736 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 737 #endif 738 739 BGE_PCICHK(bgep); 740 } 741 742 /* 743 * The DDI doesn't provide get/put functions for 128 bit data 744 * so we put RCBs out as two 64-bit chunks instead. 745 */ 746 static void bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 747 #pragma inline(bge_reg_putrcb) 748 749 static void 750 bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 751 { 752 uint64_t *p; 753 754 BGE_TRACE(("bge_reg_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 755 (void *)bgep, addr, rcbp->host_ring_addr, 756 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 757 758 ASSERT((addr % sizeof (*rcbp)) == 0); 759 760 p = (void *)rcbp; 761 bge_reg_put64(bgep, addr, *p++); 762 bge_reg_put64(bgep, addr+8, *p); 763 } 764 765 void bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data); 766 #pragma inline(bge_mbx_put) 767 768 void 769 bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data) 770 { 771 BGE_TRACE(("bge_mbx_put($%p, 0x%lx, 0x%016llx)", 772 (void *)bgep, regno, data)); 773 774 /* 775 * Mailbox registers are nominally 64 bits on the 5701, but 776 * the MSW isn't used. On the 5703, they're only 32 bits 777 * anyway. So here we just write the lower(!) 32 bits - 778 * remembering that the chip is big-endian, even though the 779 * PCI bus is little-endian ... 780 */ 781 #ifdef _BIG_ENDIAN 782 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno+4), (uint32_t)data); 783 #else 784 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), (uint32_t)data); 785 #endif /* _BIG_ENDIAN */ 786 BGE_PCICHK(bgep); 787 } 788 789 #if BGE_DEBUGGING 790 791 void bge_led_mark(bge_t *bgep); 792 #pragma no_inline(bge_led_mark) 793 794 void 795 bge_led_mark(bge_t *bgep) 796 { 797 uint32_t led_ctrl = LED_CONTROL_OVERRIDE_LINK | 798 LED_CONTROL_1000MBPS_LED | 799 LED_CONTROL_100MBPS_LED | 800 LED_CONTROL_10MBPS_LED; 801 802 /* 803 * Blink all three LINK LEDs on simultaneously, then all off, 804 * then restore to automatic hardware control. This is used 805 * in laboratory testing to trigger a logic analyser or scope. 806 */ 807 bge_reg_set32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 808 led_ctrl ^= LED_CONTROL_OVERRIDE_LINK; 809 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 810 led_ctrl = LED_CONTROL_OVERRIDE_LINK; 811 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 812 } 813 814 #endif /* BGE_DEBUGGING */ 815 816 /* 817 * NIC on-chip memory access routines 818 * 819 * Only 32K of NIC memory is visible at a time, controlled by the 820 * Memory Window Base Address Register (in PCI config space). Once 821 * this is set, the 32K region of NIC-local memory that it refers 822 * to can be directly addressed in the upper 32K of the 64K of PCI 823 * memory space used for the device. 824 */ 825 826 static void bge_nic_setwin(bge_t *bgep, bge_regno_t base); 827 #pragma inline(bge_nic_setwin) 828 829 static void 830 bge_nic_setwin(bge_t *bgep, bge_regno_t base) 831 { 832 chip_id_t *cidp; 833 834 BGE_TRACE(("bge_nic_setwin($%p, 0x%lx)", 835 (void *)bgep, base)); 836 837 ASSERT((base & MWBAR_GRANULE_MASK) == 0); 838 839 /* 840 * Don't do repeated zero data writes, 841 * if the device is BCM5714C/15C. 842 */ 843 cidp = &bgep->chipid; 844 if ((cidp->device == DEVICE_ID_5714C) || 845 (cidp->device == DEVICE_ID_5715C)) { 846 if (bgep->lastWriteZeroData && (base == (bge_regno_t)0)) 847 return; 848 /* Adjust lastWriteZeroData */ 849 bgep->lastWriteZeroData = ((base == (bge_regno_t)0) ? 850 B_TRUE : B_FALSE); 851 } 852 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, base); 853 } 854 855 856 static uint32_t bge_nic_get32(bge_t *bgep, bge_regno_t addr); 857 #pragma inline(bge_nic_get32) 858 859 static uint32_t 860 bge_nic_get32(bge_t *bgep, bge_regno_t addr) 861 { 862 uint32_t data; 863 864 #ifdef BGE_IPMI_ASF 865 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 866 /* workaround for word swap error */ 867 if (addr & 4) 868 addr = addr - 4; 869 else 870 addr = addr + 4; 871 } 872 #endif 873 874 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 875 addr &= MWBAR_GRANULE_MASK; 876 addr += NIC_MEM_WINDOW_OFFSET; 877 878 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 879 880 BGE_TRACE(("bge_nic_get32($%p, 0x%lx) = 0x%08x", 881 (void *)bgep, addr, data)); 882 883 return (data); 884 } 885 886 void bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data); 887 #pragma inline(bge_nic_put32) 888 889 void 890 bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data) 891 { 892 BGE_TRACE(("bge_nic_put32($%p, 0x%lx, 0x%08x)", 893 (void *)bgep, addr, data)); 894 895 #ifdef BGE_IPMI_ASF 896 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 897 /* workaround for word swap error */ 898 if (addr & 4) 899 addr = addr - 4; 900 else 901 addr = addr + 4; 902 } 903 #endif 904 905 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 906 addr &= MWBAR_GRANULE_MASK; 907 addr += NIC_MEM_WINDOW_OFFSET; 908 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), data); 909 BGE_PCICHK(bgep); 910 } 911 912 913 static uint64_t bge_nic_get64(bge_t *bgep, bge_regno_t addr); 914 #pragma inline(bge_nic_get64) 915 916 static uint64_t 917 bge_nic_get64(bge_t *bgep, bge_regno_t addr) 918 { 919 uint64_t data; 920 921 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 922 addr &= MWBAR_GRANULE_MASK; 923 addr += NIC_MEM_WINDOW_OFFSET; 924 925 #ifdef __amd64 926 if (bge_get_em64t_type()) { 927 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 928 data <<= 32; 929 data |= ddi_get32(bgep->io_handle, 930 PIO_ADDR(bgep, addr + 4)); 931 } else { 932 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 933 } 934 #else 935 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 936 #endif 937 938 BGE_TRACE(("bge_nic_get64($%p, 0x%lx) = 0x%016llx", 939 (void *)bgep, addr, data)); 940 941 return (data); 942 } 943 944 static void bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data); 945 #pragma inline(bge_nic_put64) 946 947 static void 948 bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data) 949 { 950 BGE_TRACE(("bge_nic_put64($%p, 0x%lx, 0x%016llx)", 951 (void *)bgep, addr, data)); 952 953 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 954 addr &= MWBAR_GRANULE_MASK; 955 addr += NIC_MEM_WINDOW_OFFSET; 956 957 #ifdef __amd64 958 if (bge_get_em64t_type()) { 959 ddi_put32(bgep->io_handle, 960 PIO_ADDR(bgep, addr), (uint32_t)data); 961 BGE_PCICHK(bgep); 962 ddi_put32(bgep->io_handle, 963 PIO_ADDR(bgep, addr + 4), (uint32_t)(data >> 32)); 964 } else { 965 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 966 } 967 #else 968 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 969 #endif 970 971 BGE_PCICHK(bgep); 972 } 973 974 /* 975 * The DDI doesn't provide get/put functions for 128 bit data 976 * so we put RCBs out as two 64-bit chunks instead. 977 */ 978 static void bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 979 #pragma inline(bge_nic_putrcb) 980 981 static void 982 bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 983 { 984 uint64_t *p; 985 986 BGE_TRACE(("bge_nic_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 987 (void *)bgep, addr, rcbp->host_ring_addr, 988 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 989 990 ASSERT((addr % sizeof (*rcbp)) == 0); 991 992 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 993 addr &= MWBAR_GRANULE_MASK; 994 addr += NIC_MEM_WINDOW_OFFSET; 995 996 p = (void *)rcbp; 997 #ifdef __amd64 998 if (bge_get_em64t_type()) { 999 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), 1000 (uint32_t)(*p)); 1001 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4), 1002 (uint32_t)(*p >> 32)); 1003 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8), 1004 (uint32_t)(*(p + 1))); 1005 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12), 1006 (uint32_t)(*p >> 32)); 1007 1008 } else { 1009 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 1010 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr+8), *p); 1011 } 1012 #else 1013 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 1014 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p); 1015 #endif 1016 1017 BGE_PCICHK(bgep); 1018 } 1019 1020 static void bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes); 1021 #pragma inline(bge_nic_zero) 1022 1023 static void 1024 bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes) 1025 { 1026 BGE_TRACE(("bge_nic_zero($%p, 0x%lx, 0x%x)", 1027 (void *)bgep, addr, nbytes)); 1028 1029 ASSERT((addr & ~MWBAR_GRANULE_MASK) == 1030 ((addr+nbytes) & ~MWBAR_GRANULE_MASK)); 1031 1032 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 1033 addr &= MWBAR_GRANULE_MASK; 1034 addr += NIC_MEM_WINDOW_OFFSET; 1035 1036 (void) ddi_device_zero(bgep->io_handle, PIO_ADDR(bgep, addr), 1037 nbytes, 1, DDI_DATA_SZ08_ACC); 1038 BGE_PCICHK(bgep); 1039 } 1040 1041 /* 1042 * MII (PHY) register get/set access routines 1043 * 1044 * These use the chip's MII auto-access method, controlled by the 1045 * MII Communication register at 0x044c, so the CPU doesn't have 1046 * to fiddle with the individual bits. 1047 */ 1048 1049 #undef BGE_DBG 1050 #define BGE_DBG BGE_DBG_MII /* debug flag for this code */ 1051 1052 static uint16_t bge_mii_access(bge_t *bgep, bge_regno_t regno, 1053 uint16_t data, uint32_t cmd); 1054 #pragma no_inline(bge_mii_access) 1055 1056 static uint16_t 1057 bge_mii_access(bge_t *bgep, bge_regno_t regno, uint16_t data, uint32_t cmd) 1058 { 1059 uint32_t timeout; 1060 uint32_t regval1; 1061 uint32_t regval2; 1062 1063 BGE_TRACE(("bge_mii_access($%p, 0x%lx, 0x%x, 0x%x)", 1064 (void *)bgep, regno, data, cmd)); 1065 1066 ASSERT(mutex_owned(bgep->genlock)); 1067 1068 /* 1069 * Assemble the command ... 1070 */ 1071 cmd |= data << MI_COMMS_DATA_SHIFT; 1072 cmd |= regno << MI_COMMS_REGISTER_SHIFT; 1073 cmd |= bgep->phy_mii_addr << MI_COMMS_ADDRESS_SHIFT; 1074 cmd |= MI_COMMS_START; 1075 1076 /* 1077 * Wait for any command already in progress ... 1078 * 1079 * Note: this *shouldn't* ever find that there is a command 1080 * in progress, because we already hold the <genlock> mutex. 1081 * Nonetheless, we have sometimes seen the MI_COMMS_START 1082 * bit set here -- it seems that the chip can initiate MII 1083 * accesses internally, even with polling OFF. 1084 */ 1085 regval1 = regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1086 for (timeout = 100; ; ) { 1087 if ((regval2 & MI_COMMS_START) == 0) { 1088 bge_reg_put32(bgep, MI_COMMS_REG, cmd); 1089 break; 1090 } 1091 if (--timeout == 0) 1092 break; 1093 drv_usecwait(10); 1094 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1095 } 1096 1097 if (timeout == 0) 1098 return ((uint16_t)~0u); 1099 1100 if (timeout != 100) 1101 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1102 "MI_COMMS_START set for %d us; 0x%x->0x%x", 1103 cmd, 10*(100-timeout), regval1, regval2)); 1104 1105 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1106 for (timeout = 1000; ; ) { 1107 if ((regval1 & MI_COMMS_START) == 0) 1108 break; 1109 if (--timeout == 0) 1110 break; 1111 drv_usecwait(10); 1112 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1113 } 1114 1115 /* 1116 * Drop out early if the READ FAILED bit is set -- this chip 1117 * could be a 5703/4S, with a SerDes instead of a PHY! 1118 */ 1119 if (regval2 & MI_COMMS_READ_FAILED) 1120 return ((uint16_t)~0u); 1121 1122 if (timeout == 0) 1123 return ((uint16_t)~0u); 1124 1125 /* 1126 * The PRM says to wait 5us after seeing the START bit clear 1127 * and then re-read the register to get the final value of the 1128 * data field, in order to avoid a race condition where the 1129 * START bit is clear but the data field isn't yet valid. 1130 * 1131 * Note: we don't actually seem to be encounter this race; 1132 * except when the START bit is seen set again (see below), 1133 * the data field doesn't change during this 5us interval. 1134 */ 1135 drv_usecwait(5); 1136 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1137 1138 /* 1139 * Unfortunately, when following the PRMs instructions above, 1140 * we have occasionally seen the START bit set again(!) in the 1141 * value read after the 5us delay. This seems to be due to the 1142 * chip autonomously starting another MII access internally. 1143 * In such cases, the command/data/etc fields relate to the 1144 * internal command, rather than the one that we thought had 1145 * just finished. So in this case, we fall back to returning 1146 * the data from the original read that showed START clear. 1147 */ 1148 if (regval2 & MI_COMMS_START) { 1149 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1150 "MI_COMMS_START set after transaction; 0x%x->0x%x", 1151 cmd, regval1, regval2)); 1152 regval2 = regval1; 1153 } 1154 1155 if (regval2 & MI_COMMS_START) 1156 return ((uint16_t)~0u); 1157 1158 if (regval2 & MI_COMMS_READ_FAILED) 1159 return ((uint16_t)~0u); 1160 1161 return ((regval2 & MI_COMMS_DATA_MASK) >> MI_COMMS_DATA_SHIFT); 1162 } 1163 1164 uint16_t bge_mii_get16(bge_t *bgep, bge_regno_t regno); 1165 #pragma no_inline(bge_mii_get16) 1166 1167 uint16_t 1168 bge_mii_get16(bge_t *bgep, bge_regno_t regno) 1169 { 1170 BGE_TRACE(("bge_mii_get16($%p, 0x%lx)", 1171 (void *)bgep, regno)); 1172 1173 ASSERT(mutex_owned(bgep->genlock)); 1174 1175 return (bge_mii_access(bgep, regno, 0, MI_COMMS_COMMAND_READ)); 1176 } 1177 1178 void bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data); 1179 #pragma no_inline(bge_mii_put16) 1180 1181 void 1182 bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data) 1183 { 1184 BGE_TRACE(("bge_mii_put16($%p, 0x%lx, 0x%x)", 1185 (void *)bgep, regno, data)); 1186 1187 ASSERT(mutex_owned(bgep->genlock)); 1188 1189 (void) bge_mii_access(bgep, regno, data, MI_COMMS_COMMAND_WRITE); 1190 } 1191 1192 #undef BGE_DBG 1193 #define BGE_DBG BGE_DBG_SEEPROM /* debug flag for this code */ 1194 1195 #if BGE_SEE_IO32 || BGE_FLASH_IO32 1196 1197 /* 1198 * Basic SEEPROM get/set access routine 1199 * 1200 * This uses the chip's SEEPROM auto-access method, controlled by the 1201 * Serial EEPROM Address/Data Registers at 0x6838/683c, so the CPU 1202 * doesn't have to fiddle with the individual bits. 1203 * 1204 * The caller should hold <genlock> and *also* have already acquired 1205 * the right to access the SEEPROM, via bge_nvmem_acquire() above. 1206 * 1207 * Return value: 1208 * 0 on success, 1209 * ENODATA on access timeout (maybe retryable: device may just be busy) 1210 * EPROTO on other h/w or s/w errors. 1211 * 1212 * <*dp> is an input to a SEEPROM_ACCESS_WRITE operation, or an output 1213 * from a (successful) SEEPROM_ACCESS_READ. 1214 */ 1215 static int bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1216 uint32_t *dp); 1217 #pragma no_inline(bge_seeprom_access) 1218 1219 static int 1220 bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1221 { 1222 uint32_t tries; 1223 uint32_t regval; 1224 1225 ASSERT(mutex_owned(bgep->genlock)); 1226 1227 /* 1228 * On the newer chips that support both SEEPROM & Flash, we need 1229 * to specifically enable SEEPROM access (Flash is the default). 1230 * On older chips, we don't; SEEPROM is the only NVtype supported, 1231 * and the NVM control registers don't exist ... 1232 */ 1233 switch (bgep->chipid.nvtype) { 1234 case BGE_NVTYPE_NONE: 1235 case BGE_NVTYPE_UNKNOWN: 1236 _NOTE(NOTREACHED) 1237 case BGE_NVTYPE_SEEPROM: 1238 break; 1239 1240 case BGE_NVTYPE_LEGACY_SEEPROM: 1241 case BGE_NVTYPE_UNBUFFERED_FLASH: 1242 case BGE_NVTYPE_BUFFERED_FLASH: 1243 default: 1244 bge_reg_set32(bgep, NVM_CONFIG1_REG, 1245 NVM_CFG1_LEGACY_SEEPROM_MODE); 1246 break; 1247 } 1248 1249 /* 1250 * Check there's no command in progress. 1251 * 1252 * Note: this *shouldn't* ever find that there is a command 1253 * in progress, because we already hold the <genlock> mutex. 1254 * Also, to ensure we don't have a conflict with the chip's 1255 * internal firmware or a process accessing the same (shared) 1256 * SEEPROM through the other port of a 5704, we've already 1257 * been through the "software arbitration" protocol. 1258 * So this is just a final consistency check: we shouldn't 1259 * see EITHER the START bit (command started but not complete) 1260 * OR the COMPLETE bit (command completed but not cleared). 1261 */ 1262 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1263 if (regval & SEEPROM_ACCESS_START) 1264 return (EPROTO); 1265 if (regval & SEEPROM_ACCESS_COMPLETE) 1266 return (EPROTO); 1267 1268 /* 1269 * Assemble the command ... 1270 */ 1271 cmd |= addr & SEEPROM_ACCESS_ADDRESS_MASK; 1272 addr >>= SEEPROM_ACCESS_ADDRESS_SIZE; 1273 addr <<= SEEPROM_ACCESS_DEVID_SHIFT; 1274 cmd |= addr & SEEPROM_ACCESS_DEVID_MASK; 1275 cmd |= SEEPROM_ACCESS_START; 1276 cmd |= SEEPROM_ACCESS_COMPLETE; 1277 cmd |= regval & SEEPROM_ACCESS_HALFCLOCK_MASK; 1278 1279 bge_reg_put32(bgep, SERIAL_EEPROM_DATA_REG, *dp); 1280 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, cmd); 1281 1282 /* 1283 * By observation, a successful access takes ~20us on a 5703/4, 1284 * but apparently much longer (up to 1000us) on the obsolescent 1285 * BCM5700/BCM5701. We want to be sure we don't get any false 1286 * timeouts here; but OTOH, we don't want a bogus access to lock 1287 * out interrupts for longer than necessary. So we'll allow up 1288 * to 1000us ... 1289 */ 1290 for (tries = 0; tries < 1000; ++tries) { 1291 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1292 if (regval & SEEPROM_ACCESS_COMPLETE) 1293 break; 1294 drv_usecwait(1); 1295 } 1296 1297 if (regval & SEEPROM_ACCESS_COMPLETE) { 1298 /* 1299 * All OK; read the SEEPROM data register, then write back 1300 * the value read from the address register in order to 1301 * clear the <complete> bit and leave the SEEPROM access 1302 * state machine idle, ready for the next access ... 1303 */ 1304 BGE_DEBUG(("bge_seeprom_access: complete after %d us", tries)); 1305 *dp = bge_reg_get32(bgep, SERIAL_EEPROM_DATA_REG); 1306 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, regval); 1307 return (0); 1308 } 1309 1310 /* 1311 * Hmm ... what happened here? 1312 * 1313 * Most likely, the user addressed a non-existent SEEPROM. Or 1314 * maybe the SEEPROM was busy internally (e.g. processing a write) 1315 * and didn't respond to being addressed. Either way, it's left 1316 * the SEEPROM access state machine wedged. So we'll reset it 1317 * before we leave, so it's ready for next time ... 1318 */ 1319 BGE_DEBUG(("bge_seeprom_access: timed out after %d us", tries)); 1320 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 1321 return (ENODATA); 1322 } 1323 1324 /* 1325 * Basic Flash get/set access routine 1326 * 1327 * These use the chip's Flash auto-access method, controlled by the 1328 * Flash Access Registers at 0x7000-701c, so the CPU doesn't have to 1329 * fiddle with the individual bits. 1330 * 1331 * The caller should hold <genlock> and *also* have already acquired 1332 * the right to access the Flash, via bge_nvmem_acquire() above. 1333 * 1334 * Return value: 1335 * 0 on success, 1336 * ENODATA on access timeout (maybe retryable: device may just be busy) 1337 * ENODEV if the NVmem device is missing or otherwise unusable 1338 * 1339 * <*dp> is an input to a NVM_FLASH_CMD_WR operation, or an output 1340 * from a (successful) NVM_FLASH_CMD_RD. 1341 */ 1342 static int bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1343 uint32_t *dp); 1344 #pragma no_inline(bge_flash_access) 1345 1346 static int 1347 bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1348 { 1349 uint32_t tries; 1350 uint32_t regval; 1351 1352 ASSERT(mutex_owned(bgep->genlock)); 1353 1354 /* 1355 * On the newer chips that support both SEEPROM & Flash, we need 1356 * to specifically disable SEEPROM access while accessing Flash. 1357 * The older chips don't support Flash, and the NVM registers don't 1358 * exist, so we shouldn't be here at all! 1359 */ 1360 switch (bgep->chipid.nvtype) { 1361 case BGE_NVTYPE_NONE: 1362 case BGE_NVTYPE_UNKNOWN: 1363 _NOTE(NOTREACHED) 1364 case BGE_NVTYPE_SEEPROM: 1365 return (ENODEV); 1366 1367 case BGE_NVTYPE_LEGACY_SEEPROM: 1368 case BGE_NVTYPE_UNBUFFERED_FLASH: 1369 case BGE_NVTYPE_BUFFERED_FLASH: 1370 default: 1371 bge_reg_clr32(bgep, NVM_CONFIG1_REG, 1372 NVM_CFG1_LEGACY_SEEPROM_MODE); 1373 break; 1374 } 1375 1376 /* 1377 * Assemble the command ... 1378 */ 1379 addr &= NVM_FLASH_ADDR_MASK; 1380 cmd |= NVM_FLASH_CMD_DOIT; 1381 cmd |= NVM_FLASH_CMD_FIRST; 1382 cmd |= NVM_FLASH_CMD_LAST; 1383 cmd |= NVM_FLASH_CMD_DONE; 1384 1385 bge_reg_put32(bgep, NVM_FLASH_WRITE_REG, *dp); 1386 bge_reg_put32(bgep, NVM_FLASH_ADDR_REG, addr); 1387 bge_reg_put32(bgep, NVM_FLASH_CMD_REG, cmd); 1388 1389 /* 1390 * Allow up to 1000ms ... 1391 */ 1392 for (tries = 0; tries < 1000; ++tries) { 1393 regval = bge_reg_get32(bgep, NVM_FLASH_CMD_REG); 1394 if (regval & NVM_FLASH_CMD_DONE) 1395 break; 1396 drv_usecwait(1); 1397 } 1398 1399 if (regval & NVM_FLASH_CMD_DONE) { 1400 /* 1401 * All OK; read the data from the Flash read register 1402 */ 1403 BGE_DEBUG(("bge_flash_access: complete after %d us", tries)); 1404 *dp = bge_reg_get32(bgep, NVM_FLASH_READ_REG); 1405 return (0); 1406 } 1407 1408 /* 1409 * Hmm ... what happened here? 1410 * 1411 * Most likely, the user addressed a non-existent Flash. Or 1412 * maybe the Flash was busy internally (e.g. processing a write) 1413 * and didn't respond to being addressed. Either way, there's 1414 * nothing we can here ... 1415 */ 1416 BGE_DEBUG(("bge_flash_access: timed out after %d us", tries)); 1417 return (ENODATA); 1418 } 1419 1420 /* 1421 * The next two functions regulate access to the NVram (if fitted). 1422 * 1423 * On a 5704 (dual core) chip, there's only one SEEPROM and one Flash 1424 * (SPI) interface, but they can be accessed through either port. These 1425 * are managed by different instance of this driver and have no software 1426 * state in common. 1427 * 1428 * In addition (and even on a single core chip) the chip's internal 1429 * firmware can access the SEEPROM/Flash, most notably after a RESET 1430 * when it may download code to run internally. 1431 * 1432 * So we need to arbitrate between these various software agents. For 1433 * this purpose, the chip provides the Software Arbitration Register, 1434 * which implements hardware(!) arbitration. 1435 * 1436 * This functionality didn't exist on older (5700/5701) chips, so there's 1437 * nothing we can do by way of arbitration on those; also, if there's no 1438 * SEEPROM/Flash fitted (or we couldn't determine what type), there's also 1439 * nothing to do. 1440 * 1441 * The internal firmware appears to use Request 0, which is the highest 1442 * priority. So we'd like to use Request 2, leaving one higher and one 1443 * lower for any future developments ... but apparently this doesn't 1444 * always work. So for now, the code uses Request 1 ;-( 1445 */ 1446 1447 #define NVM_READ_REQ NVM_READ_REQ1 1448 #define NVM_RESET_REQ NVM_RESET_REQ1 1449 #define NVM_SET_REQ NVM_SET_REQ1 1450 1451 static void bge_nvmem_relinquish(bge_t *bgep); 1452 #pragma no_inline(bge_nvmem_relinquish) 1453 1454 static void 1455 bge_nvmem_relinquish(bge_t *bgep) 1456 { 1457 ASSERT(mutex_owned(bgep->genlock)); 1458 1459 switch (bgep->chipid.nvtype) { 1460 case BGE_NVTYPE_NONE: 1461 case BGE_NVTYPE_UNKNOWN: 1462 _NOTE(NOTREACHED) 1463 return; 1464 1465 case BGE_NVTYPE_SEEPROM: 1466 /* 1467 * No arbitration performed, no release needed 1468 */ 1469 return; 1470 1471 case BGE_NVTYPE_LEGACY_SEEPROM: 1472 case BGE_NVTYPE_UNBUFFERED_FLASH: 1473 case BGE_NVTYPE_BUFFERED_FLASH: 1474 default: 1475 break; 1476 } 1477 1478 /* 1479 * Our own request should be present (whether or not granted) ... 1480 */ 1481 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1482 1483 /* 1484 * ... this will make it go away. 1485 */ 1486 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_RESET_REQ); 1487 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1488 } 1489 1490 /* 1491 * Arbitrate for access to the NVmem, if necessary 1492 * 1493 * Return value: 1494 * 0 on success 1495 * EAGAIN if the device is in use (retryable) 1496 * ENODEV if the NVmem device is missing or otherwise unusable 1497 */ 1498 static int bge_nvmem_acquire(bge_t *bgep); 1499 #pragma no_inline(bge_nvmem_acquire) 1500 1501 static int 1502 bge_nvmem_acquire(bge_t *bgep) 1503 { 1504 uint32_t regval; 1505 uint32_t tries; 1506 1507 ASSERT(mutex_owned(bgep->genlock)); 1508 1509 switch (bgep->chipid.nvtype) { 1510 case BGE_NVTYPE_NONE: 1511 case BGE_NVTYPE_UNKNOWN: 1512 /* 1513 * Access denied: no (recognisable) device fitted 1514 */ 1515 return (ENODEV); 1516 1517 case BGE_NVTYPE_SEEPROM: 1518 /* 1519 * Access granted: no arbitration needed (or possible) 1520 */ 1521 return (0); 1522 1523 case BGE_NVTYPE_LEGACY_SEEPROM: 1524 case BGE_NVTYPE_UNBUFFERED_FLASH: 1525 case BGE_NVTYPE_BUFFERED_FLASH: 1526 default: 1527 /* 1528 * Access conditional: conduct arbitration protocol 1529 */ 1530 break; 1531 } 1532 1533 /* 1534 * We're holding the per-port mutex <genlock>, so no-one other 1535 * thread can be attempting to access the NVmem through *this* 1536 * port. But it could be in use by the *other* port (of a 5704), 1537 * or by the chip's internal firmware, so we have to go through 1538 * the full (hardware) arbitration protocol ... 1539 * 1540 * Note that *because* we're holding <genlock>, the interrupt handler 1541 * won't be able to progress. So we're only willing to spin for a 1542 * fairly short time. Specifically: 1543 * 1544 * We *must* wait long enough for the hardware to resolve all 1545 * requests and determine the winner. Fortunately, this is 1546 * "almost instantaneous", even as observed by GHz CPUs. 1547 * 1548 * A successful access by another Solaris thread (via either 1549 * port) typically takes ~20us. So waiting a bit longer than 1550 * that will give a good chance of success, if the other user 1551 * *is* another thread on the other port. 1552 * 1553 * However, the internal firmware can hold on to the NVmem 1554 * for *much* longer: at least 10 milliseconds just after a 1555 * RESET, and maybe even longer if the NVmem actually contains 1556 * code to download and run on the internal CPUs. 1557 * 1558 * So, we'll allow 50us; if that's not enough then it's up to the 1559 * caller to retry later (hence the choice of return code EAGAIN). 1560 */ 1561 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1562 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_SET_REQ); 1563 1564 for (tries = 0; tries < 50; ++tries) { 1565 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1566 if (regval & NVM_WON_REQ1) 1567 break; 1568 drv_usecwait(1); 1569 } 1570 1571 if (regval & NVM_WON_REQ1) { 1572 BGE_DEBUG(("bge_nvmem_acquire: won after %d us", tries)); 1573 return (0); 1574 } 1575 1576 /* 1577 * Somebody else must be accessing the NVmem, so abandon our 1578 * attempt take control of it. The caller can try again later ... 1579 */ 1580 BGE_DEBUG(("bge_nvmem_acquire: lost after %d us", tries)); 1581 bge_nvmem_relinquish(bgep); 1582 return (EAGAIN); 1583 } 1584 1585 /* 1586 * This code assumes that the GPIO1 bit has been wired up to the NVmem 1587 * write protect line in such a way that the NVmem is protected when 1588 * GPIO1 is an input, or is an output but driven high. Thus, to make the 1589 * NVmem writable we have to change GPIO1 to an output AND drive it low. 1590 * 1591 * Note: there's only one set of GPIO pins on a 5704, even though they 1592 * can be accessed through either port. So the chip has to resolve what 1593 * happens if the two ports program a single pin differently ... the rule 1594 * it uses is that if the ports disagree about the *direction* of a pin, 1595 * "output" wins over "input", but if they disagree about its *value* as 1596 * an output, then the pin is TRISTATED instead! In such a case, no-one 1597 * wins, and the external signal does whatever the external circuitry 1598 * defines as the default -- which we've assumed is the PROTECTED state. 1599 * So, we always change GPIO1 back to being an *input* whenever we're not 1600 * specifically using it to unprotect the NVmem. This allows either port 1601 * to update the NVmem, although obviously only one at a time! 1602 * 1603 * The caller should hold <genlock> and *also* have already acquired the 1604 * right to access the NVmem, via bge_nvmem_acquire() above. 1605 */ 1606 static void bge_nvmem_protect(bge_t *bgep, boolean_t protect); 1607 #pragma inline(bge_nvmem_protect) 1608 1609 static void 1610 bge_nvmem_protect(bge_t *bgep, boolean_t protect) 1611 { 1612 uint32_t regval; 1613 1614 ASSERT(mutex_owned(bgep->genlock)); 1615 1616 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 1617 if (protect) { 1618 regval |= MLCR_MISC_PINS_OUTPUT_1; 1619 regval &= ~MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1620 } else { 1621 regval &= ~MLCR_MISC_PINS_OUTPUT_1; 1622 regval |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1623 } 1624 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, regval); 1625 } 1626 1627 /* 1628 * Now put it all together ... 1629 * 1630 * Try to acquire control of the NVmem; if successful, then: 1631 * unprotect it (if we want to write to it) 1632 * perform the requested access 1633 * reprotect it (after a write) 1634 * relinquish control 1635 * 1636 * Return value: 1637 * 0 on success, 1638 * EAGAIN if the device is in use (retryable) 1639 * ENODATA on access timeout (maybe retryable: device may just be busy) 1640 * ENODEV if the NVmem device is missing or otherwise unusable 1641 * EPROTO on other h/w or s/w errors. 1642 */ 1643 static int 1644 bge_nvmem_rw32(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1645 { 1646 int err; 1647 1648 if ((err = bge_nvmem_acquire(bgep)) == 0) { 1649 switch (cmd) { 1650 case BGE_SEE_READ: 1651 err = bge_seeprom_access(bgep, 1652 SEEPROM_ACCESS_READ, addr, dp); 1653 break; 1654 1655 case BGE_SEE_WRITE: 1656 bge_nvmem_protect(bgep, B_FALSE); 1657 err = bge_seeprom_access(bgep, 1658 SEEPROM_ACCESS_WRITE, addr, dp); 1659 bge_nvmem_protect(bgep, B_TRUE); 1660 break; 1661 1662 case BGE_FLASH_READ: 1663 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1664 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1665 bge_reg_set32(bgep, NVM_ACCESS_REG, 1666 NVM_ACCESS_ENABLE); 1667 } 1668 err = bge_flash_access(bgep, 1669 NVM_FLASH_CMD_RD, addr, dp); 1670 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1671 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1672 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1673 NVM_ACCESS_ENABLE); 1674 } 1675 break; 1676 1677 case BGE_FLASH_WRITE: 1678 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1679 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1680 bge_reg_set32(bgep, NVM_ACCESS_REG, 1681 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1682 } 1683 bge_nvmem_protect(bgep, B_FALSE); 1684 err = bge_flash_access(bgep, 1685 NVM_FLASH_CMD_WR, addr, dp); 1686 bge_nvmem_protect(bgep, B_TRUE); 1687 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1688 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1689 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1690 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1691 } 1692 1693 break; 1694 1695 default: 1696 _NOTE(NOTREACHED) 1697 break; 1698 } 1699 bge_nvmem_relinquish(bgep); 1700 } 1701 1702 BGE_DEBUG(("bge_nvmem_rw32: err %d", err)); 1703 return (err); 1704 } 1705 1706 /* 1707 * Attempt to get a MAC address from the SEEPROM or Flash, if any 1708 */ 1709 static uint64_t bge_get_nvmac(bge_t *bgep); 1710 #pragma no_inline(bge_get_nvmac) 1711 1712 static uint64_t 1713 bge_get_nvmac(bge_t *bgep) 1714 { 1715 uint32_t mac_high; 1716 uint32_t mac_low; 1717 uint32_t addr; 1718 uint32_t cmd; 1719 uint64_t mac; 1720 1721 BGE_TRACE(("bge_get_nvmac($%p)", 1722 (void *)bgep)); 1723 1724 switch (bgep->chipid.nvtype) { 1725 case BGE_NVTYPE_NONE: 1726 case BGE_NVTYPE_UNKNOWN: 1727 default: 1728 return (0ULL); 1729 1730 case BGE_NVTYPE_SEEPROM: 1731 case BGE_NVTYPE_LEGACY_SEEPROM: 1732 cmd = BGE_SEE_READ; 1733 break; 1734 1735 case BGE_NVTYPE_UNBUFFERED_FLASH: 1736 case BGE_NVTYPE_BUFFERED_FLASH: 1737 cmd = BGE_FLASH_READ; 1738 break; 1739 } 1740 1741 addr = NVMEM_DATA_MAC_ADDRESS; 1742 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_high)) 1743 return (0ULL); 1744 addr += 4; 1745 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_low)) 1746 return (0ULL); 1747 1748 /* 1749 * The Broadcom chip is natively BIG-endian, so that's how the 1750 * MAC address is represented in NVmem. We may need to swap it 1751 * around on a little-endian host ... 1752 */ 1753 #ifdef _BIG_ENDIAN 1754 mac = mac_high; 1755 mac = mac << 32; 1756 mac |= mac_low; 1757 #else 1758 mac = BGE_BSWAP_32(mac_high); 1759 mac = mac << 32; 1760 mac |= BGE_BSWAP_32(mac_low); 1761 #endif /* _BIG_ENDIAN */ 1762 1763 return (mac); 1764 } 1765 1766 #else /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1767 1768 /* 1769 * Dummy version for when we're not supporting NVmem access 1770 */ 1771 static uint64_t bge_get_nvmac(bge_t *bgep); 1772 #pragma inline(bge_get_nvmac) 1773 1774 static uint64_t 1775 bge_get_nvmac(bge_t *bgep) 1776 { 1777 _NOTE(ARGUNUSED(bgep)) 1778 return (0ULL); 1779 } 1780 1781 #endif /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1782 1783 /* 1784 * Determine the type of NVmem that is (or may be) attached to this chip, 1785 */ 1786 static enum bge_nvmem_type bge_nvmem_id(bge_t *bgep); 1787 #pragma no_inline(bge_nvmem_id) 1788 1789 static enum bge_nvmem_type 1790 bge_nvmem_id(bge_t *bgep) 1791 { 1792 enum bge_nvmem_type nvtype; 1793 uint32_t config1; 1794 1795 BGE_TRACE(("bge_nvmem_id($%p)", 1796 (void *)bgep)); 1797 1798 switch (bgep->chipid.device) { 1799 default: 1800 /* 1801 * We shouldn't get here; it means we don't recognise 1802 * the chip, which means we don't know how to determine 1803 * what sort of NVmem (if any) it has. So we'll say 1804 * NONE, to disable the NVmem access code ... 1805 */ 1806 nvtype = BGE_NVTYPE_NONE; 1807 break; 1808 1809 case DEVICE_ID_5700: 1810 case DEVICE_ID_5700x: 1811 case DEVICE_ID_5701: 1812 /* 1813 * These devices support *only* SEEPROMs 1814 */ 1815 nvtype = BGE_NVTYPE_SEEPROM; 1816 break; 1817 1818 case DEVICE_ID_5702: 1819 case DEVICE_ID_5702fe: 1820 case DEVICE_ID_5703C: 1821 case DEVICE_ID_5703S: 1822 case DEVICE_ID_5704C: 1823 case DEVICE_ID_5704S: 1824 case DEVICE_ID_5704: 1825 case DEVICE_ID_5705M: 1826 case DEVICE_ID_5705C: 1827 case DEVICE_ID_5706: 1828 case DEVICE_ID_5782: 1829 case DEVICE_ID_5788: 1830 case DEVICE_ID_5789: 1831 case DEVICE_ID_5751: 1832 case DEVICE_ID_5751M: 1833 case DEVICE_ID_5721: 1834 case DEVICE_ID_5714C: 1835 case DEVICE_ID_5714S: 1836 case DEVICE_ID_5715C: 1837 config1 = bge_reg_get32(bgep, NVM_CONFIG1_REG); 1838 if (config1 & NVM_CFG1_FLASH_MODE) 1839 if (config1 & NVM_CFG1_BUFFERED_MODE) 1840 nvtype = BGE_NVTYPE_BUFFERED_FLASH; 1841 else 1842 nvtype = BGE_NVTYPE_UNBUFFERED_FLASH; 1843 else 1844 nvtype = BGE_NVTYPE_LEGACY_SEEPROM; 1845 break; 1846 } 1847 1848 return (nvtype); 1849 } 1850 1851 #undef BGE_DBG 1852 #define BGE_DBG BGE_DBG_CHIP /* debug flag for this code */ 1853 1854 static void 1855 bge_init_recv_rule(bge_t *bgep) 1856 { 1857 bge_recv_rule_t *rulep; 1858 uint32_t i; 1859 1860 /* 1861 * receive rule: direct all TCP traffic to ring RULE_MATCH_TO_RING 1862 * 1. to direct UDP traffic, set: 1863 * rulep->control = RULE_PROTO_CONTROL; 1864 * rulep->mask_value = RULE_UDP_MASK_VALUE; 1865 * 2. to direct ICMP traffic, set: 1866 * rulep->control = RULE_PROTO_CONTROL; 1867 * rulep->mask_value = RULE_ICMP_MASK_VALUE; 1868 * 3. to direct traffic by source ip, set: 1869 * rulep->control = RULE_SIP_CONTROL; 1870 * rulep->mask_value = RULE_SIP_MASK_VALUE; 1871 */ 1872 rulep = bgep->recv_rules; 1873 rulep->control = RULE_PROTO_CONTROL; 1874 rulep->mask_value = RULE_TCP_MASK_VALUE; 1875 1876 /* 1877 * set receive rule registers 1878 */ 1879 rulep = bgep->recv_rules; 1880 for (i = 0; i < RECV_RULES_NUM_MAX; i++, rulep++) { 1881 bge_reg_put32(bgep, RECV_RULE_MASK_REG(i), rulep->mask_value); 1882 bge_reg_put32(bgep, RECV_RULE_CONTROL_REG(i), rulep->control); 1883 } 1884 } 1885 1886 /* 1887 * Using the values captured by bge_chip_cfg_init(), and additional probes 1888 * as required, characterise the chip fully: determine the label by which 1889 * to refer to this chip, the correct settings for various registers, and 1890 * of course whether the device and/or subsystem are supported! 1891 */ 1892 int bge_chip_id_init(bge_t *bgep); 1893 #pragma no_inline(bge_chip_id_init) 1894 1895 int 1896 bge_chip_id_init(bge_t *bgep) 1897 { 1898 char buf[MAXPATHLEN]; /* any risk of stack overflow? */ 1899 boolean_t sys_ok; 1900 boolean_t dev_ok; 1901 chip_id_t *cidp; 1902 uint32_t subid; 1903 char *devname; 1904 char *sysname; 1905 int *ids; 1906 int err; 1907 uint_t i; 1908 1909 ASSERT(bgep->bge_chip_state == BGE_CHIP_INITIAL); 1910 1911 sys_ok = dev_ok = B_FALSE; 1912 cidp = &bgep->chipid; 1913 1914 /* 1915 * Check the PCI device ID to determine the generic chip type and 1916 * select parameters that depend on this. 1917 * 1918 * Note: because the SPARC platforms in general don't fit the 1919 * SEEPROM 'behind' the chip, the PCI revision ID register reads 1920 * as zero - which is why we use <asic_rev> rather than <revision> 1921 * below ... 1922 * 1923 * Note: in general we can't distinguish between the Copper/SerDes 1924 * versions by ID alone, as some Copper devices (e.g. some but not 1925 * all 5703Cs) have the same ID as the SerDes equivalents. So we 1926 * treat them the same here, and the MII code works out the media 1927 * type later on ... 1928 */ 1929 cidp->mbuf_base = bge_mbuf_pool_base; 1930 cidp->mbuf_length = bge_mbuf_pool_len; 1931 cidp->recv_slots = BGE_RECV_SLOTS_USED; 1932 cidp->bge_dma_rwctrl = bge_dma_rwctrl; 1933 cidp->pci_type = BGE_PCI_X; 1934 cidp->statistic_type = BGE_STAT_BLK; 1935 cidp->mbuf_lo_water_rdma = bge_mbuf_lo_water_rdma; 1936 cidp->mbuf_lo_water_rmac = bge_mbuf_lo_water_rmac; 1937 cidp->mbuf_hi_water = bge_mbuf_hi_water; 1938 1939 if (cidp->rx_rings == 0 || cidp->rx_rings > BGE_RECV_RINGS_MAX) 1940 cidp->rx_rings = BGE_RECV_RINGS_DEFAULT; 1941 if (cidp->tx_rings == 0 || cidp->tx_rings > BGE_SEND_RINGS_MAX) 1942 cidp->tx_rings = BGE_SEND_RINGS_DEFAULT; 1943 1944 cidp->msi_enabled = B_FALSE; 1945 1946 switch (cidp->device) { 1947 case DEVICE_ID_5700: 1948 case DEVICE_ID_5700x: 1949 cidp->chip_label = 5700; 1950 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1951 break; 1952 1953 case DEVICE_ID_5701: 1954 cidp->chip_label = 5701; 1955 dev_ok = B_TRUE; 1956 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1957 break; 1958 1959 case DEVICE_ID_5702: 1960 case DEVICE_ID_5702fe: 1961 cidp->chip_label = 5702; 1962 dev_ok = B_TRUE; 1963 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1964 cidp->pci_type = BGE_PCI; 1965 break; 1966 1967 case DEVICE_ID_5703C: 1968 case DEVICE_ID_5703S: 1969 case DEVICE_ID_5703: 1970 /* 1971 * Revision A0 of the 5703/5793 had various errata 1972 * that we can't or don't work around, so it's not 1973 * supported, but all later versions are 1974 */ 1975 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5793 : 5703; 1976 if (bgep->chipid.asic_rev != MHCR_CHIP_REV_5703_A0) 1977 dev_ok = B_TRUE; 1978 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1979 break; 1980 1981 case DEVICE_ID_5704C: 1982 case DEVICE_ID_5704S: 1983 case DEVICE_ID_5704: 1984 /* 1985 * Revision A0 of the 5704/5794 had various errata 1986 * but we have workarounds, so it *is* supported. 1987 */ 1988 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5794 : 5704; 1989 cidp->mbuf_base = bge_mbuf_pool_base_5704; 1990 cidp->mbuf_length = bge_mbuf_pool_len_5704; 1991 dev_ok = B_TRUE; 1992 if (cidp->asic_rev < MHCR_CHIP_REV_5704_B0) 1993 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1994 break; 1995 1996 case DEVICE_ID_5705C: 1997 case DEVICE_ID_5705M: 1998 case DEVICE_ID_5705MA3: 1999 case DEVICE_ID_5705F: 2000 cidp->chip_label = 5705; 2001 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2002 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2003 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2004 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2005 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2006 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2007 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2008 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2009 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2010 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2011 cidp->pci_type = BGE_PCI; 2012 cidp->statistic_type = BGE_STAT_REG; 2013 dev_ok = B_TRUE; 2014 break; 2015 2016 case DEVICE_ID_5706: 2017 cidp->chip_label = 5706; 2018 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2019 break; 2020 2021 case DEVICE_ID_5782: 2022 /* 2023 * Apart from the label, we treat this as a 5705(?) 2024 */ 2025 cidp->chip_label = 5782; 2026 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2027 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2028 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2029 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2030 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2031 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2032 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2033 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2034 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2035 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2036 cidp->statistic_type = BGE_STAT_REG; 2037 dev_ok = B_TRUE; 2038 break; 2039 2040 case DEVICE_ID_5788: 2041 /* 2042 * Apart from the label, we treat this as a 5705(?) 2043 */ 2044 cidp->chip_label = 5788; 2045 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2046 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2047 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2048 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2049 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2050 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2051 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2052 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2053 cidp->statistic_type = BGE_STAT_REG; 2054 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2055 dev_ok = B_TRUE; 2056 break; 2057 2058 case DEVICE_ID_5714C: 2059 if (cidp->revision >= REVISION_ID_5714_A2) 2060 cidp->msi_enabled = bge_enable_msi; 2061 /* FALLTHRU */ 2062 case DEVICE_ID_5714S: 2063 cidp->chip_label = 5714; 2064 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2065 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2066 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2067 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2068 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2069 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2070 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5714; 2071 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2072 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2073 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2074 cidp->pci_type = BGE_PCI_E; 2075 cidp->statistic_type = BGE_STAT_REG; 2076 dev_ok = B_TRUE; 2077 break; 2078 2079 case DEVICE_ID_5715C: 2080 cidp->chip_label = 5715; 2081 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2082 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2083 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2084 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2085 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2086 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2087 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5715; 2088 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2089 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2090 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2091 cidp->pci_type = BGE_PCI_E; 2092 cidp->statistic_type = BGE_STAT_REG; 2093 if (cidp->revision >= REVISION_ID_5715_A2) 2094 cidp->msi_enabled = bge_enable_msi; 2095 dev_ok = B_TRUE; 2096 break; 2097 2098 case DEVICE_ID_5721: 2099 cidp->chip_label = 5721; 2100 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2101 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2102 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2103 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2104 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2105 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2106 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2107 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2108 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2109 cidp->pci_type = BGE_PCI_E; 2110 cidp->statistic_type = BGE_STAT_REG; 2111 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2112 dev_ok = B_TRUE; 2113 break; 2114 2115 case DEVICE_ID_5751: 2116 case DEVICE_ID_5751M: 2117 cidp->chip_label = 5751; 2118 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2119 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2120 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2121 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2122 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2123 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2124 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2125 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2126 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2127 cidp->pci_type = BGE_PCI_E; 2128 cidp->statistic_type = BGE_STAT_REG; 2129 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2130 dev_ok = B_TRUE; 2131 break; 2132 2133 case DEVICE_ID_5789: 2134 cidp->chip_label = 5789; 2135 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2136 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2137 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2138 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2139 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2140 cidp->tx_rings = BGE_RECV_RINGS_MAX_5705; 2141 cidp->pci_type = BGE_PCI_E; 2142 cidp->statistic_type = BGE_STAT_REG; 2143 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2144 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2145 cidp->msi_enabled = B_TRUE; 2146 dev_ok = B_TRUE; 2147 break; 2148 2149 } 2150 2151 /* 2152 * Setup the default jumbo parameter. 2153 */ 2154 cidp->ethmax_size = ETHERMAX; 2155 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_DEFAULT; 2156 cidp->std_buf_size = BGE_STD_BUFF_SIZE; 2157 2158 /* 2159 * If jumbo is enabled and this kind of chipset supports jumbo feature, 2160 * setup below jumbo specific parameters. 2161 * 2162 * For BCM5714/5715, there is only one standard receive ring. So the 2163 * std buffer size should be set to BGE_JUMBO_BUFF_SIZE when jumbo 2164 * feature is enabled. 2165 */ 2166 if (bge_jumbo_enable && 2167 !(cidp->flags & CHIP_FLAG_NO_JUMBO) && 2168 (cidp->default_mtu > BGE_DEFAULT_MTU) && 2169 (cidp->default_mtu <= BGE_MAXIMUM_MTU)) { 2170 if (DEVICE_5714_SERIES_CHIPSETS(bgep)) { 2171 cidp->mbuf_lo_water_rdma = 2172 RDMA_MBUF_LOWAT_5714_JUMBO; 2173 cidp->mbuf_lo_water_rmac = 2174 MAC_RX_MBUF_LOWAT_5714_JUMBO; 2175 cidp->mbuf_hi_water = MBUF_HIWAT_5714_JUMBO; 2176 cidp->jumbo_slots = 0; 2177 cidp->std_buf_size = BGE_JUMBO_BUFF_SIZE; 2178 } else { 2179 cidp->mbuf_lo_water_rdma = 2180 RDMA_MBUF_LOWAT_JUMBO; 2181 cidp->mbuf_lo_water_rmac = 2182 MAC_RX_MBUF_LOWAT_JUMBO; 2183 cidp->mbuf_hi_water = MBUF_HIWAT_JUMBO; 2184 cidp->jumbo_slots = BGE_JUMBO_SLOTS_USED; 2185 } 2186 cidp->recv_jumbo_size = BGE_JUMBO_BUFF_SIZE; 2187 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_JUMBO; 2188 cidp->ethmax_size = cidp->default_mtu + 2189 sizeof (struct ether_header); 2190 } 2191 2192 /* 2193 * Identify the NV memory type: SEEPROM or Flash? 2194 */ 2195 cidp->nvtype = bge_nvmem_id(bgep); 2196 2197 /* 2198 * Now, we want to check whether this device is part of a 2199 * supported subsystem (e.g., on the motherboard of a Sun 2200 * branded platform). 2201 * 2202 * Rule 1: If the Subsystem Vendor ID is "Sun", then it's OK ;-) 2203 */ 2204 if (cidp->subven == VENDOR_ID_SUN) 2205 sys_ok = B_TRUE; 2206 2207 /* 2208 * Rule 2: If it's on the list on known subsystems, then it's OK. 2209 * Note: 0x14e41647 should *not* appear in the list, but the code 2210 * doesn't enforce that. 2211 */ 2212 err = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, bgep->devinfo, 2213 DDI_PROP_DONTPASS, knownids_propname, &ids, &i); 2214 if (err == DDI_PROP_SUCCESS) { 2215 /* 2216 * Got the list; scan for a matching subsystem vendor/device 2217 */ 2218 subid = (cidp->subven << 16) | cidp->subdev; 2219 while (i--) 2220 if (ids[i] == subid) 2221 sys_ok = B_TRUE; 2222 ddi_prop_free(ids); 2223 } 2224 2225 /* 2226 * Rule 3: If it's a Taco/ENWS motherboard device, then it's OK 2227 * 2228 * Unfortunately, early SunBlade 1500s and 2500s didn't reprogram 2229 * the Subsystem Vendor ID, so it defaults to Broadcom. Therefore, 2230 * we have to check specially for the exact device paths to the 2231 * motherboard devices on those platforms ;-( 2232 * 2233 * Note: we can't just use the "supported-subsystems" mechanism 2234 * above, because the entry would have to be 0x14e41647 -- which 2235 * would then accept *any* plugin card that *didn't* contain a 2236 * (valid) SEEPROM ;-( 2237 */ 2238 sysname = ddi_node_name(ddi_root_node()); 2239 devname = ddi_pathname(bgep->devinfo, buf); 2240 ASSERT(strlen(devname) > 0); 2241 if (strcmp(sysname, "SUNW,Sun-Blade-1500") == 0) /* Taco */ 2242 if (strcmp(devname, "/pci@1f,700000/network@2") == 0) 2243 sys_ok = B_TRUE; 2244 if (strcmp(sysname, "SUNW,Sun-Blade-2500") == 0) /* ENWS */ 2245 if (strcmp(devname, "/pci@1c,600000/network@3") == 0) 2246 sys_ok = B_TRUE; 2247 2248 /* 2249 * Now check what we've discovered: is this truly a supported 2250 * chip on (the motherboard of) a supported platform? 2251 * 2252 * Possible problems here: 2253 * 1) it's a completely unheard-of chip (e.g. 5761) 2254 * 2) it's a recognised but unsupported chip (e.g. 5701, 5703C-A0) 2255 * 3) it's a chip we would support if it were on the motherboard 2256 * of a Sun platform, but this one isn't ;-( 2257 */ 2258 if (cidp->chip_label == 0) 2259 bge_problem(bgep, 2260 "Device 'pci%04x,%04x' not recognized (%d?)", 2261 cidp->vendor, cidp->device, cidp->device); 2262 else if (!dev_ok) 2263 bge_problem(bgep, 2264 "Device 'pci%04x,%04x' (%d) revision %d not supported", 2265 cidp->vendor, cidp->device, cidp->chip_label, 2266 cidp->revision); 2267 #if BGE_DEBUGGING 2268 else if (!sys_ok) 2269 bge_problem(bgep, 2270 "%d-based subsystem 'pci%04x,%04x' not validated", 2271 cidp->chip_label, cidp->subven, cidp->subdev); 2272 #endif 2273 else 2274 cidp->flags |= CHIP_FLAG_SUPPORTED; 2275 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 2276 return (EIO); 2277 return (0); 2278 } 2279 2280 void 2281 bge_chip_msi_trig(bge_t *bgep) 2282 { 2283 uint32_t regval; 2284 2285 regval = bgep->param_msi_cnt<<4; 2286 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, regval); 2287 BGE_DEBUG(("bge_chip_msi_trig:data = %d", regval)); 2288 } 2289 2290 /* 2291 * Various registers that control the chip's internal engines (state 2292 * machines) have a <reset> and <enable> bits (fortunately, in the 2293 * same place in each such register :-). 2294 * 2295 * To reset the state machine, the <reset> bit must be written with 1; 2296 * it will then read back as 1 while the reset is in progress, but 2297 * self-clear to 0 when the reset completes. 2298 * 2299 * To enable a state machine, one must set the <enable> bit, which 2300 * will continue to read back as 0 until the state machine is running. 2301 * 2302 * To disable a state machine, the <enable> bit must be cleared, but 2303 * it will continue to read back as 1 until the state machine actually 2304 * stops. 2305 * 2306 * This routine implements polling for completion of a reset, enable 2307 * or disable operation, returning B_TRUE on success (bit reached the 2308 * required state) or B_FALSE on timeout (200*100us == 20ms). 2309 */ 2310 static boolean_t bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 2311 uint32_t mask, uint32_t val); 2312 #pragma no_inline(bge_chip_poll_engine) 2313 2314 static boolean_t 2315 bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 2316 uint32_t mask, uint32_t val) 2317 { 2318 uint32_t regval; 2319 uint32_t n; 2320 2321 BGE_TRACE(("bge_chip_poll_engine($%p, 0x%lx, 0x%x, 0x%x)", 2322 (void *)bgep, regno, mask, val)); 2323 2324 for (n = 200; n; --n) { 2325 regval = bge_reg_get32(bgep, regno); 2326 if ((regval & mask) == val) 2327 return (B_TRUE); 2328 drv_usecwait(100); 2329 } 2330 2331 bge_fm_ereport(bgep, DDI_FM_DEVICE_NO_RESPONSE); 2332 return (B_FALSE); 2333 } 2334 2335 /* 2336 * Various registers that control the chip's internal engines (state 2337 * machines) have a <reset> bit (fortunately, in the same place in 2338 * each such register :-). To reset the state machine, this bit must 2339 * be written with 1; it will then read back as 1 while the reset is 2340 * in progress, but self-clear to 0 when the reset completes. 2341 * 2342 * This code sets the bit, then polls for it to read back as zero. 2343 * The return value is B_TRUE on success (reset bit cleared itself), 2344 * or B_FALSE if the state machine didn't recover :( 2345 * 2346 * NOTE: the Core reset is similar to other resets, except that we 2347 * can't poll for completion, since the Core reset disables memory 2348 * access! So we just have to assume that it will all complete in 2349 * 100us. See Broadcom document 570X-PG102-R, p102, steps 4-5. 2350 */ 2351 static boolean_t bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno); 2352 #pragma no_inline(bge_chip_reset_engine) 2353 2354 static boolean_t 2355 bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno) 2356 { 2357 uint32_t regval; 2358 uint32_t val32; 2359 2360 regval = bge_reg_get32(bgep, regno); 2361 2362 BGE_TRACE(("bge_chip_reset_engine($%p, 0x%lx)", 2363 (void *)bgep, regno)); 2364 BGE_DEBUG(("bge_chip_reset_engine: 0x%lx before reset = 0x%08x", 2365 regno, regval)); 2366 2367 regval |= STATE_MACHINE_RESET_BIT; 2368 2369 switch (regno) { 2370 case MISC_CONFIG_REG: 2371 /* 2372 * BCM5714/5721/5751 pcie chip special case. In order to avoid 2373 * resetting PCIE block and bringing PCIE link down, bit 29 2374 * in the register needs to be set first, and then set it again 2375 * while the reset bit is written. 2376 * See:P500 of 57xx-PG102-RDS.pdf. 2377 */ 2378 if (DEVICE_5705_SERIES_CHIPSETS(bgep)|| 2379 DEVICE_5721_SERIES_CHIPSETS(bgep)|| 2380 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 2381 regval |= MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE; 2382 if (bgep->chipid.pci_type == BGE_PCI_E) { 2383 if (bgep->chipid.asic_rev == 2384 MHCR_CHIP_REV_5751_A0 || 2385 bgep->chipid.asic_rev == 2386 MHCR_CHIP_REV_5721_A0) { 2387 val32 = bge_reg_get32(bgep, 2388 PHY_TEST_CTRL_REG); 2389 if (val32 == (PHY_PCIE_SCRAM_MODE | 2390 PHY_PCIE_LTASS_MODE)) 2391 bge_reg_put32(bgep, 2392 PHY_TEST_CTRL_REG, 2393 PHY_PCIE_SCRAM_MODE); 2394 val32 = pci_config_get32 2395 (bgep->cfg_handle, 2396 PCI_CONF_BGE_CLKCTL); 2397 val32 |= CLKCTL_PCIE_A0_FIX; 2398 pci_config_put32(bgep->cfg_handle, 2399 PCI_CONF_BGE_CLKCTL, val32); 2400 } 2401 bge_reg_set32(bgep, regno, 2402 MISC_CONFIG_GRC_RESET_DISABLE); 2403 regval |= MISC_CONFIG_GRC_RESET_DISABLE; 2404 } 2405 } 2406 2407 /* 2408 * Special case - causes Core reset 2409 * 2410 * On SPARC v9 we want to ensure that we don't start 2411 * timing until the I/O access has actually reached 2412 * the chip, otherwise we might make the next access 2413 * too early. And we can't just force the write out 2414 * by following it with a read (even to config space) 2415 * because that would cause the fault we're trying 2416 * to avoid. Hence the need for membar_sync() here. 2417 */ 2418 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), regval); 2419 #ifdef __sparcv9 2420 membar_sync(); 2421 #endif /* __sparcv9 */ 2422 /* 2423 * On some platforms,system need about 300us for 2424 * link setup. 2425 */ 2426 drv_usecwait(300); 2427 2428 if (bgep->chipid.pci_type == BGE_PCI_E) { 2429 /* PCI-E device need more reset time */ 2430 drv_usecwait(120000); 2431 2432 /* Set PCIE max payload size and clear error status. */ 2433 if ((bgep->chipid.chip_label == 5721) || 2434 (bgep->chipid.chip_label == 5751) || 2435 (bgep->chipid.chip_label == 5789)) { 2436 pci_config_put16(bgep->cfg_handle, 2437 PCI_CONF_DEV_CTRL, READ_REQ_SIZE_MAX); 2438 pci_config_put16(bgep->cfg_handle, 2439 PCI_CONF_DEV_STUS, DEVICE_ERROR_STUS); 2440 } 2441 } 2442 2443 BGE_PCICHK(bgep); 2444 return (B_TRUE); 2445 2446 default: 2447 bge_reg_put32(bgep, regno, regval); 2448 return (bge_chip_poll_engine(bgep, regno, 2449 STATE_MACHINE_RESET_BIT, 0)); 2450 } 2451 } 2452 2453 /* 2454 * Various registers that control the chip's internal engines (state 2455 * machines) have an <enable> bit (fortunately, in the same place in 2456 * each such register :-). To stop the state machine, this bit must 2457 * be written with 0, then polled to see when the state machine has 2458 * actually stopped. 2459 * 2460 * The return value is B_TRUE on success (enable bit cleared), or 2461 * B_FALSE if the state machine didn't stop :( 2462 */ 2463 static boolean_t bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, 2464 uint32_t morebits); 2465 #pragma no_inline(bge_chip_disable_engine) 2466 2467 static boolean_t 2468 bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 2469 { 2470 uint32_t regval; 2471 2472 BGE_TRACE(("bge_chip_disable_engine($%p, 0x%lx, 0x%x)", 2473 (void *)bgep, regno, morebits)); 2474 2475 switch (regno) { 2476 case FTQ_RESET_REG: 2477 /* 2478 * Not quite like the others; it doesn't 2479 * have an <enable> bit, but instead we 2480 * have to set and then clear all the bits 2481 */ 2482 bge_reg_put32(bgep, regno, ~(uint32_t)0); 2483 drv_usecwait(100); 2484 bge_reg_put32(bgep, regno, 0); 2485 return (B_TRUE); 2486 2487 default: 2488 regval = bge_reg_get32(bgep, regno); 2489 regval &= ~STATE_MACHINE_ENABLE_BIT; 2490 regval &= ~morebits; 2491 bge_reg_put32(bgep, regno, regval); 2492 return (bge_chip_poll_engine(bgep, regno, 2493 STATE_MACHINE_ENABLE_BIT, 0)); 2494 } 2495 } 2496 2497 /* 2498 * Various registers that control the chip's internal engines (state 2499 * machines) have an <enable> bit (fortunately, in the same place in 2500 * each such register :-). To start the state machine, this bit must 2501 * be written with 1, then polled to see when the state machine has 2502 * actually started. 2503 * 2504 * The return value is B_TRUE on success (enable bit set), or 2505 * B_FALSE if the state machine didn't start :( 2506 */ 2507 static boolean_t bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, 2508 uint32_t morebits); 2509 #pragma no_inline(bge_chip_enable_engine) 2510 2511 static boolean_t 2512 bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 2513 { 2514 uint32_t regval; 2515 2516 BGE_TRACE(("bge_chip_enable_engine($%p, 0x%lx, 0x%x)", 2517 (void *)bgep, regno, morebits)); 2518 2519 switch (regno) { 2520 case FTQ_RESET_REG: 2521 /* 2522 * Not quite like the others; it doesn't 2523 * have an <enable> bit, but instead we 2524 * have to set and then clear all the bits 2525 */ 2526 bge_reg_put32(bgep, regno, ~(uint32_t)0); 2527 drv_usecwait(100); 2528 bge_reg_put32(bgep, regno, 0); 2529 return (B_TRUE); 2530 2531 default: 2532 regval = bge_reg_get32(bgep, regno); 2533 regval |= STATE_MACHINE_ENABLE_BIT; 2534 regval |= morebits; 2535 bge_reg_put32(bgep, regno, regval); 2536 return (bge_chip_poll_engine(bgep, regno, 2537 STATE_MACHINE_ENABLE_BIT, STATE_MACHINE_ENABLE_BIT)); 2538 } 2539 } 2540 2541 /* 2542 * Reprogram the Ethernet, Transmit, and Receive MAC 2543 * modes to match the param_* variables 2544 */ 2545 static void bge_sync_mac_modes(bge_t *bgep); 2546 #pragma no_inline(bge_sync_mac_modes) 2547 2548 static void 2549 bge_sync_mac_modes(bge_t *bgep) 2550 { 2551 uint32_t macmode; 2552 uint32_t regval; 2553 2554 ASSERT(mutex_owned(bgep->genlock)); 2555 2556 /* 2557 * Reprogram the Ethernet MAC mode ... 2558 */ 2559 macmode = regval = bge_reg_get32(bgep, ETHERNET_MAC_MODE_REG); 2560 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 2561 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) 2562 macmode &= ~ETHERNET_MODE_LINK_POLARITY; 2563 else 2564 macmode |= ETHERNET_MODE_LINK_POLARITY; 2565 macmode &= ~ETHERNET_MODE_PORTMODE_MASK; 2566 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 2567 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) 2568 macmode |= ETHERNET_MODE_PORTMODE_TBI; 2569 else if (bgep->param_link_speed == 10 || bgep->param_link_speed == 100) 2570 macmode |= ETHERNET_MODE_PORTMODE_MII; 2571 else 2572 macmode |= ETHERNET_MODE_PORTMODE_GMII; 2573 if (bgep->param_link_duplex == LINK_DUPLEX_HALF) 2574 macmode |= ETHERNET_MODE_HALF_DUPLEX; 2575 else 2576 macmode &= ~ETHERNET_MODE_HALF_DUPLEX; 2577 if (bgep->param_loop_mode == BGE_LOOP_INTERNAL_MAC) 2578 macmode |= ETHERNET_MODE_MAC_LOOPBACK; 2579 else 2580 macmode &= ~ETHERNET_MODE_MAC_LOOPBACK; 2581 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, macmode); 2582 BGE_DEBUG(("bge_sync_mac_modes($%p) Ethernet MAC mode 0x%x => 0x%x", 2583 (void *)bgep, regval, macmode)); 2584 2585 /* 2586 * ... the Transmit MAC mode ... 2587 */ 2588 macmode = regval = bge_reg_get32(bgep, TRANSMIT_MAC_MODE_REG); 2589 if (bgep->param_link_tx_pause) 2590 macmode |= TRANSMIT_MODE_FLOW_CONTROL; 2591 else 2592 macmode &= ~TRANSMIT_MODE_FLOW_CONTROL; 2593 bge_reg_put32(bgep, TRANSMIT_MAC_MODE_REG, macmode); 2594 BGE_DEBUG(("bge_sync_mac_modes($%p) Transmit MAC mode 0x%x => 0x%x", 2595 (void *)bgep, regval, macmode)); 2596 2597 /* 2598 * ... and the Receive MAC mode 2599 */ 2600 macmode = regval = bge_reg_get32(bgep, RECEIVE_MAC_MODE_REG); 2601 if (bgep->param_link_rx_pause) 2602 macmode |= RECEIVE_MODE_FLOW_CONTROL; 2603 else 2604 macmode &= ~RECEIVE_MODE_FLOW_CONTROL; 2605 bge_reg_put32(bgep, RECEIVE_MAC_MODE_REG, macmode); 2606 BGE_DEBUG(("bge_sync_mac_modes($%p) Receive MAC mode 0x%x => 0x%x", 2607 (void *)bgep, regval, macmode)); 2608 } 2609 2610 /* 2611 * bge_chip_sync() -- program the chip with the unicast MAC address, 2612 * the multicast hash table, the required level of promiscuity, and 2613 * the current loopback mode ... 2614 */ 2615 #ifdef BGE_IPMI_ASF 2616 int bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive); 2617 #else 2618 int bge_chip_sync(bge_t *bgep); 2619 #endif 2620 #pragma no_inline(bge_chip_sync) 2621 2622 int 2623 #ifdef BGE_IPMI_ASF 2624 bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive) 2625 #else 2626 bge_chip_sync(bge_t *bgep) 2627 #endif 2628 { 2629 void (*opfn)(bge_t *bgep, bge_regno_t reg, uint32_t bits); 2630 boolean_t promisc; 2631 uint64_t macaddr; 2632 uint32_t fill; 2633 int i, j; 2634 int retval = DDI_SUCCESS; 2635 2636 BGE_TRACE(("bge_chip_sync($%p)", 2637 (void *)bgep)); 2638 2639 ASSERT(mutex_owned(bgep->genlock)); 2640 2641 promisc = B_FALSE; 2642 fill = ~(uint32_t)0; 2643 2644 if (bgep->promisc) 2645 promisc = B_TRUE; 2646 else 2647 fill = (uint32_t)0; 2648 2649 /* 2650 * If the TX/RX MAC engines are already running, we should stop 2651 * them (and reset the RX engine) before changing the parameters. 2652 * If they're not running, this will have no effect ... 2653 * 2654 * NOTE: this is currently disabled by default because stopping 2655 * and restarting the Tx engine may cause an outgoing packet in 2656 * transit to be truncated. Also, stopping and restarting the 2657 * Rx engine seems to not work correctly on the 5705. Testing 2658 * has not (yet!) revealed any problems with NOT stopping and 2659 * restarting these engines (and Broadcom say their drivers don't 2660 * do this), but if it is found to cause problems, this variable 2661 * can be patched to re-enable the old behaviour ... 2662 */ 2663 if (bge_stop_start_on_sync) { 2664 #ifdef BGE_IPMI_ASF 2665 if (!bgep->asf_enabled) { 2666 if (!bge_chip_disable_engine(bgep, 2667 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG)) 2668 retval = DDI_FAILURE; 2669 } else { 2670 if (!bge_chip_disable_engine(bgep, 2671 RECEIVE_MAC_MODE_REG, 0)) 2672 retval = DDI_FAILURE; 2673 } 2674 #else 2675 if (!bge_chip_disable_engine(bgep, RECEIVE_MAC_MODE_REG, 2676 RECEIVE_MODE_KEEP_VLAN_TAG)) 2677 retval = DDI_FAILURE; 2678 #endif 2679 if (!bge_chip_disable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 2680 retval = DDI_FAILURE; 2681 if (!bge_chip_reset_engine(bgep, RECEIVE_MAC_MODE_REG)) 2682 retval = DDI_FAILURE; 2683 } 2684 2685 /* 2686 * Reprogram the hashed multicast address table ... 2687 */ 2688 for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i) 2689 bge_reg_put32(bgep, MAC_HASH_REG(i), 2690 bgep->mcast_hash[i] | fill); 2691 2692 #ifdef BGE_IPMI_ASF 2693 if (!bgep->asf_enabled || !asf_keeplive) { 2694 #endif 2695 /* 2696 * Transform the MAC address(es) from host to chip format, then 2697 * reprogram the transmit random backoff seed and the unicast 2698 * MAC address(es) ... 2699 */ 2700 for (j = 0; j < MAC_ADDRESS_REGS_MAX; j++) { 2701 for (i = 0, fill = 0, macaddr = 0ull; 2702 i < ETHERADDRL; ++i) { 2703 macaddr <<= 8; 2704 macaddr |= bgep->curr_addr[j].addr[i]; 2705 fill += bgep->curr_addr[j].addr[i]; 2706 } 2707 bge_reg_put32(bgep, MAC_TX_RANDOM_BACKOFF_REG, fill); 2708 bge_reg_put64(bgep, MAC_ADDRESS_REG(j), macaddr); 2709 } 2710 2711 BGE_DEBUG(("bge_chip_sync($%p) setting MAC address %012llx", 2712 (void *)bgep, macaddr)); 2713 #ifdef BGE_IPMI_ASF 2714 } 2715 #endif 2716 2717 /* 2718 * Set or clear the PROMISCUOUS mode bit 2719 */ 2720 opfn = promisc ? bge_reg_set32 : bge_reg_clr32; 2721 (*opfn)(bgep, RECEIVE_MAC_MODE_REG, RECEIVE_MODE_PROMISCUOUS); 2722 2723 /* 2724 * Sync the rest of the MAC modes too ... 2725 */ 2726 bge_sync_mac_modes(bgep); 2727 2728 /* 2729 * Restart RX/TX MAC engines if required ... 2730 */ 2731 if (bgep->bge_chip_state == BGE_CHIP_RUNNING) { 2732 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 2733 retval = DDI_FAILURE; 2734 #ifdef BGE_IPMI_ASF 2735 if (!bgep->asf_enabled) { 2736 if (!bge_chip_enable_engine(bgep, 2737 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG)) 2738 retval = DDI_FAILURE; 2739 } else { 2740 if (!bge_chip_enable_engine(bgep, 2741 RECEIVE_MAC_MODE_REG, 0)) 2742 retval = DDI_FAILURE; 2743 } 2744 #else 2745 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 2746 RECEIVE_MODE_KEEP_VLAN_TAG)) 2747 retval = DDI_FAILURE; 2748 #endif 2749 } 2750 return (retval); 2751 } 2752 2753 /* 2754 * This array defines the sequence of state machine control registers 2755 * in which the <enable> bit must be cleared to bring the chip to a 2756 * clean stop. Taken from Broadcom document 570X-PG102-R, p116. 2757 */ 2758 static bge_regno_t shutdown_engine_regs[] = { 2759 RECEIVE_MAC_MODE_REG, 2760 RCV_BD_INITIATOR_MODE_REG, 2761 RCV_LIST_PLACEMENT_MODE_REG, 2762 RCV_LIST_SELECTOR_MODE_REG, /* BCM5704 series only */ 2763 RCV_DATA_BD_INITIATOR_MODE_REG, 2764 RCV_DATA_COMPLETION_MODE_REG, 2765 RCV_BD_COMPLETION_MODE_REG, 2766 2767 SEND_BD_SELECTOR_MODE_REG, 2768 SEND_BD_INITIATOR_MODE_REG, 2769 SEND_DATA_INITIATOR_MODE_REG, 2770 READ_DMA_MODE_REG, 2771 SEND_DATA_COMPLETION_MODE_REG, 2772 DMA_COMPLETION_MODE_REG, /* BCM5704 series only */ 2773 SEND_BD_COMPLETION_MODE_REG, 2774 TRANSMIT_MAC_MODE_REG, 2775 2776 HOST_COALESCE_MODE_REG, 2777 WRITE_DMA_MODE_REG, 2778 MBUF_CLUSTER_FREE_MODE_REG, /* BCM5704 series only */ 2779 FTQ_RESET_REG, /* special - see code */ 2780 BUFFER_MANAGER_MODE_REG, /* BCM5704 series only */ 2781 MEMORY_ARBITER_MODE_REG, /* BCM5704 series only */ 2782 BGE_REGNO_NONE /* terminator */ 2783 }; 2784 2785 /* 2786 * bge_chip_stop() -- stop all chip processing 2787 * 2788 * If the <fault> parameter is B_TRUE, we're stopping the chip because 2789 * we've detected a problem internally; otherwise, this is a normal 2790 * (clean) stop (at user request i.e. the last STREAM has been closed). 2791 */ 2792 void bge_chip_stop(bge_t *bgep, boolean_t fault); 2793 #pragma no_inline(bge_chip_stop) 2794 2795 void 2796 bge_chip_stop(bge_t *bgep, boolean_t fault) 2797 { 2798 bge_regno_t regno; 2799 bge_regno_t *rbp; 2800 boolean_t ok; 2801 2802 BGE_TRACE(("bge_chip_stop($%p)", 2803 (void *)bgep)); 2804 2805 ASSERT(mutex_owned(bgep->genlock)); 2806 2807 rbp = shutdown_engine_regs; 2808 /* 2809 * When driver try to shutdown the BCM5705/5788/5721/5751/ 2810 * 5752/5714 and 5715 chipsets,the buffer manager and the mem 2811 * -ory arbiter should not be disabled. 2812 */ 2813 for (ok = B_TRUE; (regno = *rbp) != BGE_REGNO_NONE; ++rbp) { 2814 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 2815 ok &= bge_chip_disable_engine(bgep, regno, 0); 2816 else if ((regno != RCV_LIST_SELECTOR_MODE_REG) && 2817 (regno != DMA_COMPLETION_MODE_REG) && 2818 (regno != MBUF_CLUSTER_FREE_MODE_REG)&& 2819 (regno != BUFFER_MANAGER_MODE_REG) && 2820 (regno != MEMORY_ARBITER_MODE_REG)) 2821 ok &= bge_chip_disable_engine(bgep, 2822 regno, 0); 2823 } 2824 2825 if (!ok && !fault) 2826 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 2827 2828 /* 2829 * Finally, disable (all) MAC events & clear the MAC status 2830 */ 2831 bge_reg_put32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 0); 2832 bge_reg_put32(bgep, ETHERNET_MAC_STATUS_REG, ~0); 2833 2834 /* 2835 * if we're stopping the chip because of a detected fault then do 2836 * appropriate actions 2837 */ 2838 if (fault) { 2839 if (bgep->bge_chip_state != BGE_CHIP_FAULT) { 2840 bgep->bge_chip_state = BGE_CHIP_FAULT; 2841 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_LOST); 2842 if (bgep->bge_dma_error) { 2843 /* 2844 * need to free buffers in case the fault was 2845 * due to a memory error in a buffer - got to 2846 * do a fair bit of tidying first 2847 */ 2848 if (bgep->progress & PROGRESS_KSTATS) { 2849 bge_fini_kstats(bgep); 2850 bgep->progress &= ~PROGRESS_KSTATS; 2851 } 2852 if (bgep->progress & PROGRESS_INTR) { 2853 bge_intr_disable(bgep); 2854 rw_enter(bgep->errlock, RW_WRITER); 2855 bge_fini_rings(bgep); 2856 rw_exit(bgep->errlock); 2857 bgep->progress &= ~PROGRESS_INTR; 2858 } 2859 if (bgep->progress & PROGRESS_BUFS) { 2860 bge_free_bufs(bgep); 2861 bgep->progress &= ~PROGRESS_BUFS; 2862 } 2863 bgep->bge_dma_error = B_FALSE; 2864 } 2865 } 2866 } else 2867 bgep->bge_chip_state = BGE_CHIP_STOPPED; 2868 } 2869 2870 /* 2871 * Poll for completion of chip's ROM firmware; also, at least on the 2872 * first time through, find and return the hardware MAC address, if any. 2873 */ 2874 static uint64_t bge_poll_firmware(bge_t *bgep); 2875 #pragma no_inline(bge_poll_firmware) 2876 2877 static uint64_t 2878 bge_poll_firmware(bge_t *bgep) 2879 { 2880 uint64_t magic; 2881 uint64_t mac; 2882 uint32_t gen; 2883 uint32_t i; 2884 2885 /* 2886 * Step 19: poll for firmware completion (GENCOMM port set 2887 * to the ones complement of T3_MAGIC_NUMBER). 2888 * 2889 * While we're at it, we also read the MAC address register; 2890 * at some stage the firmware will load this with the 2891 * factory-set value. 2892 * 2893 * When both the magic number and the MAC address are set, 2894 * we're done; but we impose a time limit of one second 2895 * (1000*1000us) in case the firmware fails in some fashion 2896 * or the SEEPROM that provides that MAC address isn't fitted. 2897 * 2898 * After the first time through (chip state != INITIAL), we 2899 * don't need the MAC address to be set (we've already got it 2900 * or not, from the first time), so we don't wait for it, but 2901 * we still have to wait for the T3_MAGIC_NUMBER. 2902 * 2903 * Note: the magic number is only a 32-bit quantity, but the NIC 2904 * memory is 64-bit (and big-endian) internally. Addressing the 2905 * GENCOMM word as "the upper half of a 64-bit quantity" makes 2906 * it work correctly on both big- and little-endian hosts. 2907 */ 2908 for (i = 0; i < 1000; ++i) { 2909 drv_usecwait(1000); 2910 gen = bge_nic_get64(bgep, NIC_MEM_GENCOMM) >> 32; 2911 mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0)); 2912 #ifdef BGE_IPMI_ASF 2913 if (!bgep->asf_enabled) { 2914 #endif 2915 if (gen != ~T3_MAGIC_NUMBER) 2916 continue; 2917 #ifdef BGE_IPMI_ASF 2918 } 2919 #endif 2920 if (mac != 0ULL) 2921 break; 2922 if (bgep->bge_chip_state != BGE_CHIP_INITIAL) 2923 break; 2924 } 2925 2926 magic = bge_nic_get64(bgep, NIC_MEM_GENCOMM); 2927 BGE_DEBUG(("bge_poll_firmware($%p): PXE magic 0x%x after %d loops", 2928 (void *)bgep, gen, i)); 2929 BGE_DEBUG(("bge_poll_firmware: MAC %016llx, GENCOMM %016llx", 2930 mac, magic)); 2931 2932 return (mac); 2933 } 2934 2935 #ifdef BGE_IPMI_ASF 2936 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode); 2937 #else 2938 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma); 2939 #endif 2940 #pragma no_inline(bge_chip_reset) 2941 2942 int 2943 #ifdef BGE_IPMI_ASF 2944 bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode) 2945 #else 2946 bge_chip_reset(bge_t *bgep, boolean_t enable_dma) 2947 #endif 2948 { 2949 chip_id_t chipid; 2950 uint64_t mac; 2951 uint64_t magic; 2952 uint32_t modeflags; 2953 uint32_t mhcr; 2954 uint32_t sx0; 2955 uint32_t i; 2956 #ifdef BGE_IPMI_ASF 2957 uint32_t mailbox; 2958 #endif 2959 int retval = DDI_SUCCESS; 2960 2961 BGE_TRACE(("bge_chip_reset($%p, %d)", 2962 (void *)bgep, enable_dma)); 2963 2964 ASSERT(mutex_owned(bgep->genlock)); 2965 2966 BGE_DEBUG(("bge_chip_reset($%p, %d): current state is %d", 2967 (void *)bgep, enable_dma, bgep->bge_chip_state)); 2968 2969 /* 2970 * Do we need to stop the chip cleanly before resetting? 2971 */ 2972 switch (bgep->bge_chip_state) { 2973 default: 2974 _NOTE(NOTREACHED) 2975 return (DDI_FAILURE); 2976 2977 case BGE_CHIP_INITIAL: 2978 case BGE_CHIP_STOPPED: 2979 case BGE_CHIP_RESET: 2980 break; 2981 2982 case BGE_CHIP_RUNNING: 2983 case BGE_CHIP_ERROR: 2984 case BGE_CHIP_FAULT: 2985 bge_chip_stop(bgep, B_FALSE); 2986 break; 2987 } 2988 2989 #ifdef BGE_IPMI_ASF 2990 if (bgep->asf_enabled) { 2991 if (asf_mode == ASF_MODE_INIT) { 2992 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 2993 } else if (asf_mode == ASF_MODE_SHUTDOWN) { 2994 bge_asf_pre_reset_operations(bgep, BGE_SHUTDOWN_RESET); 2995 } 2996 } 2997 #endif 2998 /* 2999 * Adapted from Broadcom document 570X-PG102-R, pp 102-116. 3000 * Updated to reflect Broadcom document 570X-PG104-R, pp 146-159. 3001 * 3002 * Before reset Core clock,it is 3003 * also required to initialize the Memory Arbiter as specified in step9 3004 * and Misc Host Control Register as specified in step-13 3005 * Step 4-5: reset Core clock & wait for completion 3006 * Steps 6-8: are done by bge_chip_cfg_init() 3007 * put the T3_MAGIC_NUMBER into the GENCOMM port before reset 3008 */ 3009 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 3010 retval = DDI_FAILURE; 3011 3012 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 3013 MHCR_ENABLE_TAGGED_STATUS_MODE | 3014 MHCR_MASK_INTERRUPT_MODE | 3015 MHCR_MASK_PCI_INT_OUTPUT | 3016 MHCR_CLEAR_INTERRUPT_INTA; 3017 #ifdef _BIG_ENDIAN 3018 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 3019 #endif /* _BIG_ENDIAN */ 3020 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr); 3021 #ifdef BGE_IPMI_ASF 3022 if (bgep->asf_enabled) 3023 bgep->asf_wordswapped = B_FALSE; 3024 #endif 3025 #ifdef BGE_IPMI_ASF 3026 if (!bgep->asf_enabled) { 3027 #endif 3028 magic = (uint64_t)T3_MAGIC_NUMBER << 32; 3029 bge_nic_put64(bgep, NIC_MEM_GENCOMM, magic); 3030 #ifdef BGE_IPMI_ASF 3031 } 3032 #endif 3033 3034 if (!bge_chip_reset_engine(bgep, MISC_CONFIG_REG)) 3035 retval = DDI_FAILURE; 3036 bge_chip_cfg_init(bgep, &chipid, enable_dma); 3037 3038 /* 3039 * Step 8a: This may belong elsewhere, but BCM5721 needs 3040 * a bit set to avoid a fifo overflow/underflow bug. 3041 */ 3042 if ((bgep->chipid.chip_label == 5721) || 3043 (bgep->chipid.chip_label == 5751) || 3044 (bgep->chipid.chip_label == 5789)) 3045 bge_reg_set32(bgep, TLP_CONTROL_REG, TLP_DATA_FIFO_PROTECT); 3046 3047 3048 /* 3049 * Step 9: enable MAC memory arbiter,bit30 and bit31 of 5714/5715 should 3050 * not be changed. 3051 */ 3052 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 3053 retval = DDI_FAILURE; 3054 3055 /* 3056 * Steps 10-11: configure PIO endianness options and 3057 * enable indirect register access -- already done 3058 * Steps 12-13: enable writing to the PCI state & clock 3059 * control registers -- not required; we aren't going to 3060 * use those features. 3061 * Steps 14-15: Configure DMA endianness options. See 3062 * the comments on the setting of the MHCR above. 3063 */ 3064 #ifdef _BIG_ENDIAN 3065 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME | 3066 MODE_WORD_SWAP_NONFRAME | MODE_BYTE_SWAP_NONFRAME; 3067 #else 3068 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME; 3069 #endif /* _BIG_ENDIAN */ 3070 #ifdef BGE_IPMI_ASF 3071 if (bgep->asf_enabled) 3072 modeflags |= MODE_HOST_STACK_UP; 3073 #endif 3074 bge_reg_put32(bgep, MODE_CONTROL_REG, modeflags); 3075 3076 #ifdef BGE_IPMI_ASF 3077 if (bgep->asf_enabled) { 3078 if (asf_mode != ASF_MODE_NONE) { 3079 /* Wait for NVRAM init */ 3080 i = 0; 3081 drv_usecwait(5000); 3082 mailbox = bge_nic_get32(bgep, BGE_FIRMWARE_MAILBOX); 3083 while ((mailbox != (uint32_t) 3084 ~BGE_MAGIC_NUM_FIRMWARE_INIT_DONE) && 3085 (i < 10000)) { 3086 drv_usecwait(100); 3087 mailbox = bge_nic_get32(bgep, 3088 BGE_FIRMWARE_MAILBOX); 3089 i++; 3090 } 3091 if (!bgep->asf_newhandshake) { 3092 if ((asf_mode == ASF_MODE_INIT) || 3093 (asf_mode == ASF_MODE_POST_INIT)) { 3094 3095 bge_asf_post_reset_old_mode(bgep, 3096 BGE_INIT_RESET); 3097 } else { 3098 bge_asf_post_reset_old_mode(bgep, 3099 BGE_SHUTDOWN_RESET); 3100 } 3101 } 3102 } 3103 } 3104 #endif 3105 /* 3106 * Steps 16-17: poll for firmware completion 3107 */ 3108 mac = bge_poll_firmware(bgep); 3109 3110 /* 3111 * Step 18: enable external memory -- doesn't apply. 3112 * 3113 * However we take the opportunity to set the MLCR anyway, as 3114 * this register also controls the SEEPROM auto-access method 3115 * which we may want to use later ... 3116 * 3117 * The proper value here depends on the way the chip is wired 3118 * into the circuit board, as this register *also* controls which 3119 * of the "Miscellaneous I/O" pins are driven as outputs and the 3120 * values driven onto those pins! 3121 * 3122 * See also step 74 in the PRM ... 3123 */ 3124 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, 3125 bgep->chipid.bge_mlcr_default); 3126 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 3127 3128 /* 3129 * Step 20: clear the Ethernet MAC mode register 3130 */ 3131 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, 0); 3132 3133 /* 3134 * Step 21: restore cache-line-size, latency timer, and 3135 * subsystem ID registers to their original values (not 3136 * those read into the local structure <chipid>, 'cos 3137 * that was after they were cleared by the RESET). 3138 * 3139 * Note: the Subsystem Vendor/Device ID registers are not 3140 * directly writable in config space, so we use the shadow 3141 * copy in "Page Zero" of register space to restore them 3142 * both in one go ... 3143 */ 3144 pci_config_put8(bgep->cfg_handle, PCI_CONF_CACHE_LINESZ, 3145 bgep->chipid.clsize); 3146 pci_config_put8(bgep->cfg_handle, PCI_CONF_LATENCY_TIMER, 3147 bgep->chipid.latency); 3148 bge_reg_put32(bgep, PCI_CONF_SUBVENID, 3149 (bgep->chipid.subdev << 16) | bgep->chipid.subven); 3150 3151 /* 3152 * The SEND INDEX registers should be reset to zero by the 3153 * global chip reset; if they're not, there'll be trouble 3154 * later on. 3155 */ 3156 sx0 = bge_reg_get32(bgep, NIC_DIAG_SEND_INDEX_REG(0)); 3157 if (sx0 != 0) { 3158 BGE_REPORT((bgep, "SEND INDEX - device didn't RESET")); 3159 bge_fm_ereport(bgep, DDI_FM_DEVICE_INVAL_STATE); 3160 return (DDI_FAILURE); 3161 } 3162 3163 /* Enable MSI code */ 3164 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 3165 bge_reg_set32(bgep, MSI_MODE_REG, 3166 MSI_PRI_HIGHEST|MSI_MSI_ENABLE); 3167 3168 /* 3169 * On the first time through, save the factory-set MAC address 3170 * (if any). If bge_poll_firmware() above didn't return one 3171 * (from a chip register) consider looking in the attached NV 3172 * memory device, if any. Once we have it, we save it in both 3173 * register-image (64-bit) and byte-array forms. All-zero and 3174 * all-one addresses are not valid, and we refuse to stash those. 3175 */ 3176 if (bgep->bge_chip_state == BGE_CHIP_INITIAL) { 3177 if (mac == 0ULL) 3178 mac = bge_get_nvmac(bgep); 3179 if (mac != 0ULL && mac != ~0ULL) { 3180 bgep->chipid.hw_mac_addr = mac; 3181 for (i = ETHERADDRL; i-- != 0; ) { 3182 bgep->chipid.vendor_addr.addr[i] = (uchar_t)mac; 3183 mac >>= 8; 3184 } 3185 bgep->chipid.vendor_addr.set = B_TRUE; 3186 } 3187 } 3188 3189 #ifdef BGE_IPMI_ASF 3190 if (bgep->asf_enabled && bgep->asf_newhandshake) { 3191 if (asf_mode != ASF_MODE_NONE) { 3192 if ((asf_mode == ASF_MODE_INIT) || 3193 (asf_mode == ASF_MODE_POST_INIT)) { 3194 3195 bge_asf_post_reset_new_mode(bgep, 3196 BGE_INIT_RESET); 3197 } else { 3198 bge_asf_post_reset_new_mode(bgep, 3199 BGE_SHUTDOWN_RESET); 3200 } 3201 } 3202 } 3203 #endif 3204 3205 /* 3206 * Record the new state 3207 */ 3208 bgep->chip_resets += 1; 3209 bgep->bge_chip_state = BGE_CHIP_RESET; 3210 return (retval); 3211 } 3212 3213 /* 3214 * bge_chip_start() -- start the chip transmitting and/or receiving, 3215 * including enabling interrupts 3216 */ 3217 int bge_chip_start(bge_t *bgep, boolean_t reset_phys); 3218 #pragma no_inline(bge_chip_start) 3219 3220 int 3221 bge_chip_start(bge_t *bgep, boolean_t reset_phys) 3222 { 3223 uint32_t coalmode; 3224 uint32_t ledctl; 3225 uint32_t mtu; 3226 uint32_t maxring; 3227 uint64_t ring; 3228 int retval = DDI_SUCCESS; 3229 3230 BGE_TRACE(("bge_chip_start($%p)", 3231 (void *)bgep)); 3232 3233 ASSERT(mutex_owned(bgep->genlock)); 3234 ASSERT(bgep->bge_chip_state == BGE_CHIP_RESET); 3235 3236 /* 3237 * Taken from Broadcom document 570X-PG102-R, pp 102-116. 3238 * The document specifies 95 separate steps to fully 3239 * initialise the chip!!!! 3240 * 3241 * The reset code above has already got us as far as step 3242 * 21, so we continue with ... 3243 * 3244 * Step 22: clear the MAC statistics block 3245 * (0x0300-0x0aff in NIC-local memory) 3246 */ 3247 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 3248 bge_nic_zero(bgep, NIC_MEM_STATISTICS, 3249 NIC_MEM_STATISTICS_SIZE); 3250 3251 /* 3252 * Step 23: clear the status block (in host memory) 3253 */ 3254 DMA_ZERO(bgep->status_block); 3255 3256 /* 3257 * Step 24: set DMA read/write control register 3258 */ 3259 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_PDRWCR, 3260 bgep->chipid.bge_dma_rwctrl); 3261 3262 /* 3263 * Step 25: Configure DMA endianness -- already done (16/17) 3264 * Step 26: Configure Host-Based Send Rings 3265 * Step 27: Indicate Host Stack Up 3266 */ 3267 bge_reg_set32(bgep, MODE_CONTROL_REG, 3268 MODE_HOST_SEND_BDS | 3269 MODE_HOST_STACK_UP); 3270 3271 /* 3272 * Step 28: Configure checksum options: 3273 * Solaris supports the hardware default checksum options. 3274 * 3275 * Workaround for Incorrect pseudo-header checksum calculation. 3276 */ 3277 if (bgep->chipid.flags & CHIP_FLAG_PARTIAL_CSUM) 3278 bge_reg_set32(bgep, MODE_CONTROL_REG, 3279 MODE_SEND_NO_PSEUDO_HDR_CSUM); 3280 3281 /* 3282 * Step 29: configure Timer Prescaler. The value is always the 3283 * same: the Core Clock frequency in MHz (66), minus 1, shifted 3284 * into bits 7-1. Don't set bit 0, 'cos that's the RESET bit 3285 * for the whole chip! 3286 */ 3287 bge_reg_put32(bgep, MISC_CONFIG_REG, MISC_CONFIG_DEFAULT); 3288 3289 /* 3290 * Steps 30-31: Configure MAC local memory pool & DMA pool registers 3291 * 3292 * If the mbuf_length is specified as 0, we just leave these at 3293 * their hardware defaults, rather than explicitly setting them. 3294 * As the Broadcom HRM,driver better not change the parameters 3295 * when the chipsets is 5705/5788/5721/5751/5714 and 5715. 3296 */ 3297 if ((bgep->chipid.mbuf_length != 0) && 3298 (DEVICE_5704_SERIES_CHIPSETS(bgep))) { 3299 bge_reg_put32(bgep, MBUF_POOL_BASE_REG, 3300 bgep->chipid.mbuf_base); 3301 bge_reg_put32(bgep, MBUF_POOL_LENGTH_REG, 3302 bgep->chipid.mbuf_length); 3303 bge_reg_put32(bgep, DMAD_POOL_BASE_REG, 3304 DMAD_POOL_BASE_DEFAULT); 3305 bge_reg_put32(bgep, DMAD_POOL_LENGTH_REG, 3306 DMAD_POOL_LENGTH_DEFAULT); 3307 } 3308 3309 /* 3310 * Step 32: configure MAC memory pool watermarks 3311 */ 3312 bge_reg_put32(bgep, RDMA_MBUF_LOWAT_REG, 3313 bgep->chipid.mbuf_lo_water_rdma); 3314 bge_reg_put32(bgep, MAC_RX_MBUF_LOWAT_REG, 3315 bgep->chipid.mbuf_lo_water_rmac); 3316 bge_reg_put32(bgep, MBUF_HIWAT_REG, 3317 bgep->chipid.mbuf_hi_water); 3318 3319 /* 3320 * Step 33: configure DMA resource watermarks 3321 */ 3322 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3323 bge_reg_put32(bgep, DMAD_POOL_LOWAT_REG, 3324 bge_dmad_lo_water); 3325 bge_reg_put32(bgep, DMAD_POOL_HIWAT_REG, 3326 bge_dmad_hi_water); 3327 } 3328 bge_reg_put32(bgep, LOWAT_MAX_RECV_FRAMES_REG, bge_lowat_recv_frames); 3329 3330 /* 3331 * Steps 34-36: enable buffer manager & internal h/w queues 3332 */ 3333 if (!bge_chip_enable_engine(bgep, BUFFER_MANAGER_MODE_REG, 3334 STATE_MACHINE_ATTN_ENABLE_BIT)) 3335 retval = DDI_FAILURE; 3336 if (!bge_chip_enable_engine(bgep, FTQ_RESET_REG, 0)) 3337 retval = DDI_FAILURE; 3338 3339 /* 3340 * Steps 37-39: initialise Receive Buffer (Producer) RCBs 3341 */ 3342 bge_reg_putrcb(bgep, STD_RCV_BD_RING_RCB_REG, 3343 &bgep->buff[BGE_STD_BUFF_RING].hw_rcb); 3344 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3345 bge_reg_putrcb(bgep, JUMBO_RCV_BD_RING_RCB_REG, 3346 &bgep->buff[BGE_JUMBO_BUFF_RING].hw_rcb); 3347 bge_reg_putrcb(bgep, MINI_RCV_BD_RING_RCB_REG, 3348 &bgep->buff[BGE_MINI_BUFF_RING].hw_rcb); 3349 } 3350 3351 /* 3352 * Step 40: set Receive Buffer Descriptor Ring replenish thresholds 3353 */ 3354 bge_reg_put32(bgep, STD_RCV_BD_REPLENISH_REG, bge_replenish_std); 3355 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3356 bge_reg_put32(bgep, JUMBO_RCV_BD_REPLENISH_REG, 3357 bge_replenish_jumbo); 3358 bge_reg_put32(bgep, MINI_RCV_BD_REPLENISH_REG, 3359 bge_replenish_mini); 3360 } 3361 3362 /* 3363 * Steps 41-43: clear Send Ring Producer Indices and initialise 3364 * Send Producer Rings (0x0100-0x01ff in NIC-local memory) 3365 */ 3366 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3367 maxring = BGE_SEND_RINGS_MAX; 3368 else 3369 maxring = BGE_SEND_RINGS_MAX_5705; 3370 for (ring = 0; ring < maxring; ++ring) { 3371 bge_mbx_put(bgep, SEND_RING_HOST_INDEX_REG(ring), 0); 3372 bge_mbx_put(bgep, SEND_RING_NIC_INDEX_REG(ring), 0); 3373 bge_nic_putrcb(bgep, NIC_MEM_SEND_RING(ring), 3374 &bgep->send[ring].hw_rcb); 3375 } 3376 3377 /* 3378 * Steps 44-45: initialise Receive Return Rings 3379 * (0x0200-0x02ff in NIC-local memory) 3380 */ 3381 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3382 maxring = BGE_RECV_RINGS_MAX; 3383 else 3384 maxring = BGE_RECV_RINGS_MAX_5705; 3385 for (ring = 0; ring < maxring; ++ring) 3386 bge_nic_putrcb(bgep, NIC_MEM_RECV_RING(ring), 3387 &bgep->recv[ring].hw_rcb); 3388 3389 /* 3390 * Step 46: initialise Receive Buffer (Producer) Ring indexes 3391 */ 3392 bge_mbx_put(bgep, RECV_STD_PROD_INDEX_REG, 0); 3393 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3394 bge_mbx_put(bgep, RECV_JUMBO_PROD_INDEX_REG, 0); 3395 bge_mbx_put(bgep, RECV_MINI_PROD_INDEX_REG, 0); 3396 } 3397 /* 3398 * Step 47: configure the MAC unicast address 3399 * Step 48: configure the random backoff seed 3400 * Step 96: set up multicast filters 3401 */ 3402 #ifdef BGE_IPMI_ASF 3403 if (bge_chip_sync(bgep, B_FALSE) == DDI_FAILURE) 3404 #else 3405 if (bge_chip_sync(bgep) == DDI_FAILURE) 3406 #endif 3407 retval = DDI_FAILURE; 3408 3409 /* 3410 * Step 49: configure the MTU 3411 */ 3412 mtu = bgep->chipid.ethmax_size+ETHERFCSL+VLAN_TAGSZ; 3413 bge_reg_put32(bgep, MAC_RX_MTU_SIZE_REG, mtu); 3414 3415 /* 3416 * Step 50: configure the IPG et al 3417 */ 3418 bge_reg_put32(bgep, MAC_TX_LENGTHS_REG, MAC_TX_LENGTHS_DEFAULT); 3419 3420 /* 3421 * Step 51: configure the default Rx Return Ring 3422 */ 3423 bge_reg_put32(bgep, RCV_RULES_CONFIG_REG, RCV_RULES_CONFIG_DEFAULT); 3424 3425 /* 3426 * Steps 52-54: configure Receive List Placement, 3427 * and enable Receive List Placement Statistics 3428 */ 3429 bge_reg_put32(bgep, RCV_LP_CONFIG_REG, 3430 RCV_LP_CONFIG(bgep->chipid.rx_rings)); 3431 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, ~0); 3432 bge_reg_set32(bgep, RCV_LP_STATS_CONTROL_REG, RCV_LP_STATS_ENABLE); 3433 3434 if (bgep->chipid.rx_rings > 1) 3435 bge_init_recv_rule(bgep); 3436 3437 /* 3438 * Steps 55-56: enable Send Data Initiator Statistics 3439 */ 3440 bge_reg_put32(bgep, SEND_INIT_STATS_ENABLE_MASK_REG, ~0); 3441 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3442 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 3443 SEND_INIT_STATS_ENABLE | SEND_INIT_STATS_FASTER); 3444 } else { 3445 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 3446 SEND_INIT_STATS_ENABLE); 3447 } 3448 /* 3449 * Steps 57-58: stop (?) the Host Coalescing Engine 3450 */ 3451 if (!bge_chip_disable_engine(bgep, HOST_COALESCE_MODE_REG, ~0)) 3452 retval = DDI_FAILURE; 3453 3454 /* 3455 * Steps 59-62: initialise Host Coalescing parameters 3456 */ 3457 bge_reg_put32(bgep, SEND_COALESCE_MAX_BD_REG, bge_tx_count_norm); 3458 bge_reg_put32(bgep, SEND_COALESCE_TICKS_REG, bge_tx_ticks_norm); 3459 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, bge_rx_count_norm); 3460 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, bge_rx_ticks_norm); 3461 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3462 bge_reg_put32(bgep, SEND_COALESCE_INT_BD_REG, 3463 bge_tx_count_intr); 3464 bge_reg_put32(bgep, SEND_COALESCE_INT_TICKS_REG, 3465 bge_tx_ticks_intr); 3466 bge_reg_put32(bgep, RCV_COALESCE_INT_BD_REG, 3467 bge_rx_count_intr); 3468 bge_reg_put32(bgep, RCV_COALESCE_INT_TICKS_REG, 3469 bge_rx_ticks_intr); 3470 } 3471 3472 /* 3473 * Steps 63-64: initialise status block & statistics 3474 * host memory addresses 3475 * The statistic block does not exist in some chipsets 3476 * Step 65: initialise Statistics Coalescing Tick Counter 3477 */ 3478 bge_reg_put64(bgep, STATUS_BLOCK_HOST_ADDR_REG, 3479 bgep->status_block.cookie.dmac_laddress); 3480 3481 /* 3482 * Steps 66-67: initialise status block & statistics 3483 * NIC-local memory addresses 3484 */ 3485 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3486 bge_reg_put64(bgep, STATISTICS_HOST_ADDR_REG, 3487 bgep->statistics.cookie.dmac_laddress); 3488 bge_reg_put32(bgep, STATISTICS_TICKS_REG, 3489 STATISTICS_TICKS_DEFAULT); 3490 bge_reg_put32(bgep, STATUS_BLOCK_BASE_ADDR_REG, 3491 NIC_MEM_STATUS_BLOCK); 3492 bge_reg_put32(bgep, STATISTICS_BASE_ADDR_REG, 3493 NIC_MEM_STATISTICS); 3494 } 3495 3496 /* 3497 * Steps 68-71: start the Host Coalescing Engine, the Receive BD 3498 * Completion Engine, the Receive List Placement Engine, and the 3499 * Receive List selector.Pay attention:0x3400 is not exist in BCM5714 3500 * and BCM5715. 3501 */ 3502 if (bgep->chipid.tx_rings <= COALESCE_64_BYTE_RINGS && 3503 bgep->chipid.rx_rings <= COALESCE_64_BYTE_RINGS) 3504 coalmode = COALESCE_64_BYTE_STATUS; 3505 else 3506 coalmode = 0; 3507 if (!bge_chip_enable_engine(bgep, HOST_COALESCE_MODE_REG, coalmode)) 3508 retval = DDI_FAILURE; 3509 if (!bge_chip_enable_engine(bgep, RCV_BD_COMPLETION_MODE_REG, 3510 STATE_MACHINE_ATTN_ENABLE_BIT)) 3511 retval = DDI_FAILURE; 3512 if (!bge_chip_enable_engine(bgep, RCV_LIST_PLACEMENT_MODE_REG, 0)) 3513 retval = DDI_FAILURE; 3514 3515 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3516 if (!bge_chip_enable_engine(bgep, RCV_LIST_SELECTOR_MODE_REG, 3517 STATE_MACHINE_ATTN_ENABLE_BIT)) 3518 retval = DDI_FAILURE; 3519 3520 /* 3521 * Step 72: Enable MAC DMA engines 3522 * Step 73: Clear & enable MAC statistics 3523 */ 3524 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 3525 ETHERNET_MODE_ENABLE_FHDE | 3526 ETHERNET_MODE_ENABLE_RDE | 3527 ETHERNET_MODE_ENABLE_TDE); 3528 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 3529 ETHERNET_MODE_ENABLE_TX_STATS | 3530 ETHERNET_MODE_ENABLE_RX_STATS | 3531 ETHERNET_MODE_CLEAR_TX_STATS | 3532 ETHERNET_MODE_CLEAR_RX_STATS); 3533 3534 /* 3535 * Step 74: configure the MLCR (Miscellaneous Local Control 3536 * Register); not required, as we set up the MLCR in step 10 3537 * (part of the reset code) above. 3538 * 3539 * Step 75: clear Interrupt Mailbox 0 3540 */ 3541 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 0); 3542 3543 /* 3544 * Steps 76-87: Gentlemen, start your engines ... 3545 * 3546 * Enable the DMA Completion Engine, the Write DMA Engine, 3547 * the Read DMA Engine, Receive Data Completion Engine, 3548 * the MBuf Cluster Free Engine, the Send Data Completion Engine, 3549 * the Send BD Completion Engine, the Receive BD Initiator Engine, 3550 * the Receive Data Initiator Engine, the Send Data Initiator Engine, 3551 * the Send BD Initiator Engine, and the Send BD Selector Engine. 3552 * 3553 * Beware exhaust fumes? 3554 */ 3555 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3556 if (!bge_chip_enable_engine(bgep, DMA_COMPLETION_MODE_REG, 0)) 3557 retval = DDI_FAILURE; 3558 if (!bge_chip_enable_engine(bgep, WRITE_DMA_MODE_REG, 3559 (bge_dma_wrprio << DMA_PRIORITY_SHIFT) | ALL_DMA_ATTN_BITS)) 3560 retval = DDI_FAILURE; 3561 if (!bge_chip_enable_engine(bgep, READ_DMA_MODE_REG, 3562 (bge_dma_rdprio << DMA_PRIORITY_SHIFT) | ALL_DMA_ATTN_BITS)) 3563 retval = DDI_FAILURE; 3564 if (!bge_chip_enable_engine(bgep, RCV_DATA_COMPLETION_MODE_REG, 3565 STATE_MACHINE_ATTN_ENABLE_BIT)) 3566 retval = DDI_FAILURE; 3567 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3568 if (!bge_chip_enable_engine(bgep, 3569 MBUF_CLUSTER_FREE_MODE_REG, 0)) 3570 retval = DDI_FAILURE; 3571 if (!bge_chip_enable_engine(bgep, SEND_DATA_COMPLETION_MODE_REG, 0)) 3572 retval = DDI_FAILURE; 3573 if (!bge_chip_enable_engine(bgep, SEND_BD_COMPLETION_MODE_REG, 3574 STATE_MACHINE_ATTN_ENABLE_BIT)) 3575 retval = DDI_FAILURE; 3576 if (!bge_chip_enable_engine(bgep, RCV_BD_INITIATOR_MODE_REG, 3577 RCV_BD_DISABLED_RING_ATTN)) 3578 retval = DDI_FAILURE; 3579 if (!bge_chip_enable_engine(bgep, RCV_DATA_BD_INITIATOR_MODE_REG, 3580 RCV_DATA_BD_ILL_RING_ATTN)) 3581 retval = DDI_FAILURE; 3582 if (!bge_chip_enable_engine(bgep, SEND_DATA_INITIATOR_MODE_REG, 0)) 3583 retval = DDI_FAILURE; 3584 if (!bge_chip_enable_engine(bgep, SEND_BD_INITIATOR_MODE_REG, 3585 STATE_MACHINE_ATTN_ENABLE_BIT)) 3586 retval = DDI_FAILURE; 3587 if (!bge_chip_enable_engine(bgep, SEND_BD_SELECTOR_MODE_REG, 3588 STATE_MACHINE_ATTN_ENABLE_BIT)) 3589 retval = DDI_FAILURE; 3590 3591 /* 3592 * Step 88: download firmware -- doesn't apply 3593 * Steps 89-90: enable Transmit & Receive MAC Engines 3594 */ 3595 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 3596 retval = DDI_FAILURE; 3597 #ifdef BGE_IPMI_ASF 3598 if (!bgep->asf_enabled) { 3599 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 3600 RECEIVE_MODE_KEEP_VLAN_TAG)) 3601 retval = DDI_FAILURE; 3602 } else { 3603 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 0)) 3604 retval = DDI_FAILURE; 3605 } 3606 #else 3607 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 3608 RECEIVE_MODE_KEEP_VLAN_TAG)) 3609 retval = DDI_FAILURE; 3610 #endif 3611 3612 /* 3613 * Step 91: disable auto-polling of PHY status 3614 */ 3615 bge_reg_put32(bgep, MI_MODE_REG, MI_MODE_DEFAULT); 3616 3617 /* 3618 * Step 92: configure D0 power state (not required) 3619 * Step 93: initialise LED control register () 3620 */ 3621 ledctl = LED_CONTROL_DEFAULT; 3622 switch (bgep->chipid.device) { 3623 case DEVICE_ID_5700: 3624 case DEVICE_ID_5700x: 3625 case DEVICE_ID_5701: 3626 /* 3627 * Switch to 5700 (MAC) mode on these older chips 3628 */ 3629 ledctl &= ~LED_CONTROL_LED_MODE_MASK; 3630 ledctl |= LED_CONTROL_LED_MODE_5700; 3631 break; 3632 3633 default: 3634 break; 3635 } 3636 bge_reg_put32(bgep, ETHERNET_MAC_LED_CONTROL_REG, ledctl); 3637 3638 /* 3639 * Step 94: activate link 3640 */ 3641 bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK); 3642 3643 /* 3644 * Step 95: set up physical layer (PHY/SerDes) 3645 * restart autoneg (if required) 3646 */ 3647 if (reset_phys) 3648 if (bge_phys_update(bgep) == DDI_FAILURE) 3649 retval = DDI_FAILURE; 3650 3651 /* 3652 * Extra step (DSG): hand over all the Receive Buffers to the chip 3653 */ 3654 for (ring = 0; ring < BGE_BUFF_RINGS_USED; ++ring) 3655 bge_mbx_put(bgep, bgep->buff[ring].chip_mbx_reg, 3656 bgep->buff[ring].rf_next); 3657 3658 /* 3659 * MSI bits:The least significant MSI 16-bit word. 3660 * ISR will be triggered different. 3661 */ 3662 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 3663 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 0x70); 3664 3665 /* 3666 * Extra step (DSG): select which interrupts are enabled 3667 * 3668 * Program the Ethernet MAC engine to signal attention on 3669 * Link Change events, then enable interrupts on MAC, DMA, 3670 * and FLOW attention signals. 3671 */ 3672 bge_reg_set32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 3673 ETHERNET_EVENT_LINK_INT | 3674 ETHERNET_STATUS_PCS_ERROR_INT); 3675 #ifdef BGE_IPMI_ASF 3676 if (bgep->asf_enabled) { 3677 bge_reg_set32(bgep, MODE_CONTROL_REG, 3678 MODE_INT_ON_FLOW_ATTN | 3679 MODE_INT_ON_DMA_ATTN | 3680 MODE_HOST_STACK_UP| 3681 MODE_INT_ON_MAC_ATTN); 3682 } else { 3683 #endif 3684 bge_reg_set32(bgep, MODE_CONTROL_REG, 3685 MODE_INT_ON_FLOW_ATTN | 3686 MODE_INT_ON_DMA_ATTN | 3687 MODE_INT_ON_MAC_ATTN); 3688 #ifdef BGE_IPMI_ASF 3689 } 3690 #endif 3691 3692 /* 3693 * Step 97: enable PCI interrupts!!! 3694 */ 3695 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 3696 bge_cfg_clr32(bgep, PCI_CONF_BGE_MHCR, 3697 MHCR_MASK_PCI_INT_OUTPUT); 3698 3699 /* 3700 * All done! 3701 */ 3702 bgep->bge_chip_state = BGE_CHIP_RUNNING; 3703 return (retval); 3704 } 3705 3706 3707 /* 3708 * ========== Hardware interrupt handler ========== 3709 */ 3710 3711 #undef BGE_DBG 3712 #define BGE_DBG BGE_DBG_INT /* debug flag for this code */ 3713 3714 /* 3715 * Sync the status block, then atomically clear the specified bits in 3716 * the <flags-and-tag> field of the status block. 3717 * the <flags> word of the status block, returning the value of the 3718 * <tag> and the <flags> before the bits were cleared. 3719 */ 3720 static int bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags); 3721 #pragma inline(bge_status_sync) 3722 3723 static int 3724 bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags) 3725 { 3726 bge_status_t *bsp; 3727 int retval; 3728 3729 BGE_TRACE(("bge_status_sync($%p, 0x%llx)", 3730 (void *)bgep, bits)); 3731 3732 ASSERT(bgep->bge_guard == BGE_GUARD); 3733 3734 DMA_SYNC(bgep->status_block, DDI_DMA_SYNC_FORKERNEL); 3735 retval = bge_check_dma_handle(bgep, bgep->status_block.dma_hdl); 3736 if (retval != DDI_FM_OK) 3737 return (retval); 3738 3739 bsp = DMA_VPTR(bgep->status_block); 3740 *flags = bge_atomic_clr64(&bsp->flags_n_tag, bits); 3741 3742 BGE_DEBUG(("bge_status_sync($%p, 0x%llx) returning 0x%llx", 3743 (void *)bgep, bits, *flags)); 3744 3745 return (retval); 3746 } 3747 3748 static void bge_wake_factotum(bge_t *bgep); 3749 #pragma inline(bge_wake_factotum) 3750 3751 static void 3752 bge_wake_factotum(bge_t *bgep) 3753 { 3754 mutex_enter(bgep->softintrlock); 3755 if (bgep->factotum_flag == 0) { 3756 bgep->factotum_flag = 1; 3757 ddi_trigger_softintr(bgep->factotum_id); 3758 } 3759 mutex_exit(bgep->softintrlock); 3760 } 3761 3762 /* 3763 * bge_intr() -- handle chip interrupts 3764 */ 3765 uint_t bge_intr(caddr_t arg1, caddr_t arg2); 3766 #pragma no_inline(bge_intr) 3767 3768 uint_t 3769 bge_intr(caddr_t arg1, caddr_t arg2) 3770 { 3771 bge_t *bgep = (bge_t *)arg1; /* private device info */ 3772 bge_status_t *bsp; 3773 uint64_t flags; 3774 uint32_t mlcr = 0; 3775 uint_t result; 3776 int retval; 3777 3778 BGE_TRACE(("bge_intr($%p) ($%p)", arg1, arg2)); 3779 3780 /* 3781 * GLD v2 checks that s/w setup is complete before passing 3782 * interrupts to this routine, thus eliminating the old 3783 * (and well-known) race condition around ddi_add_intr() 3784 */ 3785 ASSERT(bgep->progress & PROGRESS_HWINT); 3786 3787 /* 3788 * Check whether chip's says it's asserting #INTA; 3789 * if not, don't process or claim the interrupt. 3790 * 3791 * Note that the PCI signal is active low, so the 3792 * bit is *zero* when the interrupt is asserted. 3793 */ 3794 result = DDI_INTR_UNCLAIMED; 3795 mutex_enter(bgep->genlock); 3796 3797 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 3798 mlcr = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 3799 3800 BGE_DEBUG(("bge_intr($%p) ($%p) mlcr 0x%08x", arg1, arg2, mlcr)); 3801 3802 if ((mlcr & MLCR_INTA_STATE) == 0) { 3803 /* 3804 * Block further PCI interrupts ... 3805 */ 3806 result = DDI_INTR_CLAIMED; 3807 3808 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) { 3809 bge_reg_set32(bgep, PCI_CONF_BGE_MHCR, 3810 MHCR_MASK_PCI_INT_OUTPUT); 3811 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != 3812 DDI_FM_OK) 3813 goto chip_stop; 3814 } 3815 3816 /* 3817 * Sync the status block and grab the flags-n-tag from it. 3818 * We count the number of interrupts where there doesn't 3819 * seem to have been a DMA update of the status block; if 3820 * it *has* been updated, the counter will be cleared in 3821 * the while() loop below ... 3822 */ 3823 bgep->missed_dmas += 1; 3824 bsp = DMA_VPTR(bgep->status_block); 3825 for (;;) { 3826 if (bgep->bge_chip_state != BGE_CHIP_RUNNING) { 3827 /* 3828 * bge_chip_stop() may have freed dma area etc 3829 * while we were in this interrupt handler - 3830 * better not call bge_status_sync() 3831 */ 3832 (void) bge_check_acc_handle(bgep, 3833 bgep->io_handle); 3834 mutex_exit(bgep->genlock); 3835 return (DDI_INTR_CLAIMED); 3836 } 3837 retval = bge_status_sync(bgep, STATUS_FLAG_UPDATED, 3838 &flags); 3839 if (retval != DDI_FM_OK) { 3840 bgep->bge_dma_error = B_TRUE; 3841 goto chip_stop; 3842 } 3843 3844 if (!(flags & STATUS_FLAG_UPDATED)) 3845 break; 3846 3847 /* 3848 * Tell the chip that we're processing the interrupt 3849 */ 3850 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 3851 INTERRUPT_MBOX_DISABLE(flags)); 3852 if (bge_check_acc_handle(bgep, bgep->io_handle) != 3853 DDI_FM_OK) 3854 goto chip_stop; 3855 3856 /* 3857 * Drop the mutex while we: 3858 * Receive any newly-arrived packets 3859 * Recycle any newly-finished send buffers 3860 */ 3861 bgep->bge_intr_running = B_TRUE; 3862 mutex_exit(bgep->genlock); 3863 bge_receive(bgep, bsp); 3864 bge_recycle(bgep, bsp); 3865 mutex_enter(bgep->genlock); 3866 bgep->bge_intr_running = B_FALSE; 3867 3868 /* 3869 * Tell the chip we've finished processing, and 3870 * give it the tag that we got from the status 3871 * block earlier, so that it knows just how far 3872 * we've gone. If it's got more for us to do, 3873 * it will now update the status block and try 3874 * to assert an interrupt (but we've got the 3875 * #INTA blocked at present). If we see the 3876 * update, we'll loop around to do some more. 3877 * Eventually we'll get out of here ... 3878 */ 3879 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 3880 INTERRUPT_MBOX_ENABLE(flags)); 3881 bgep->missed_dmas = 0; 3882 } 3883 3884 /* 3885 * Check for exceptional conditions that we need to handle 3886 * 3887 * Link status changed 3888 * Status block not updated 3889 */ 3890 if (flags & STATUS_FLAG_LINK_CHANGED) 3891 bge_wake_factotum(bgep); 3892 3893 if (bgep->missed_dmas) { 3894 /* 3895 * Probably due to the internal status tag not 3896 * being reset. Force a status block update now; 3897 * this should ensure that we get an update and 3898 * a new interrupt. After that, we should be in 3899 * sync again ... 3900 */ 3901 BGE_REPORT((bgep, "interrupt: flags 0x%llx - " 3902 "not updated?", flags)); 3903 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 3904 COALESCE_NOW); 3905 3906 if (bgep->missed_dmas >= bge_dma_miss_limit) { 3907 /* 3908 * If this happens multiple times in a row, 3909 * it means DMA is just not working. Maybe 3910 * the chip's failed, or maybe there's a 3911 * problem on the PCI bus or in the host-PCI 3912 * bridge (Tomatillo). 3913 * 3914 * At all events, we want to stop further 3915 * interrupts and let the recovery code take 3916 * over to see whether anything can be done 3917 * about it ... 3918 */ 3919 bge_fm_ereport(bgep, 3920 DDI_FM_DEVICE_BADINT_LIMIT); 3921 goto chip_stop; 3922 } 3923 } 3924 3925 /* 3926 * Reenable assertion of #INTA, unless there's a DMA fault 3927 */ 3928 if (result == DDI_INTR_CLAIMED) { 3929 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) { 3930 bge_reg_clr32(bgep, PCI_CONF_BGE_MHCR, 3931 MHCR_MASK_PCI_INT_OUTPUT); 3932 if (bge_check_acc_handle(bgep, 3933 bgep->cfg_handle) != DDI_FM_OK) 3934 goto chip_stop; 3935 } 3936 } 3937 } 3938 3939 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 3940 goto chip_stop; 3941 3942 mutex_exit(bgep->genlock); 3943 return (result); 3944 3945 chip_stop: 3946 #ifdef BGE_IPMI_ASF 3947 if (bgep->asf_enabled && bgep->asf_status == ASF_STAT_RUN) { 3948 /* 3949 * We must stop ASF heart beat before 3950 * bge_chip_stop(), otherwise some 3951 * computers (ex. IBM HS20 blade 3952 * server) may crash. 3953 */ 3954 bge_asf_update_status(bgep); 3955 bge_asf_stop_timer(bgep); 3956 bgep->asf_status = ASF_STAT_STOP; 3957 3958 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 3959 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 3960 } 3961 #endif 3962 bge_chip_stop(bgep, B_TRUE); 3963 (void) bge_check_acc_handle(bgep, bgep->io_handle); 3964 mutex_exit(bgep->genlock); 3965 return (result); 3966 } 3967 3968 /* 3969 * ========== Factotum, implemented as a softint handler ========== 3970 */ 3971 3972 #undef BGE_DBG 3973 #define BGE_DBG BGE_DBG_FACT /* debug flag for this code */ 3974 3975 static void bge_factotum_error_handler(bge_t *bgep); 3976 #pragma no_inline(bge_factotum_error_handler) 3977 3978 static void 3979 bge_factotum_error_handler(bge_t *bgep) 3980 { 3981 uint32_t flow; 3982 uint32_t rdma; 3983 uint32_t wdma; 3984 uint32_t tmac; 3985 uint32_t rmac; 3986 uint32_t rxrs; 3987 uint32_t txrs = 0; 3988 3989 ASSERT(mutex_owned(bgep->genlock)); 3990 3991 /* 3992 * Read all the registers that show the possible 3993 * reasons for the ERROR bit to be asserted 3994 */ 3995 flow = bge_reg_get32(bgep, FLOW_ATTN_REG); 3996 rdma = bge_reg_get32(bgep, READ_DMA_STATUS_REG); 3997 wdma = bge_reg_get32(bgep, WRITE_DMA_STATUS_REG); 3998 tmac = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 3999 rmac = bge_reg_get32(bgep, RECEIVE_MAC_STATUS_REG); 4000 rxrs = bge_reg_get32(bgep, RX_RISC_STATE_REG); 4001 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4002 txrs = bge_reg_get32(bgep, TX_RISC_STATE_REG); 4003 4004 BGE_DEBUG(("factotum($%p) flow 0x%x rdma 0x%x wdma 0x%x", 4005 (void *)bgep, flow, rdma, wdma)); 4006 BGE_DEBUG(("factotum($%p) tmac 0x%x rmac 0x%x rxrs 0x%08x txrs 0x%08x", 4007 (void *)bgep, tmac, rmac, rxrs, txrs)); 4008 4009 /* 4010 * For now, just clear all the errors ... 4011 */ 4012 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4013 bge_reg_put32(bgep, TX_RISC_STATE_REG, ~0); 4014 bge_reg_put32(bgep, RX_RISC_STATE_REG, ~0); 4015 bge_reg_put32(bgep, RECEIVE_MAC_STATUS_REG, ~0); 4016 bge_reg_put32(bgep, WRITE_DMA_STATUS_REG, ~0); 4017 bge_reg_put32(bgep, READ_DMA_STATUS_REG, ~0); 4018 bge_reg_put32(bgep, FLOW_ATTN_REG, ~0); 4019 } 4020 4021 /* 4022 * Handler for hardware link state change. 4023 * 4024 * When this routine is called, the hardware link state has changed 4025 * and the new state is reflected in the param_* variables. Here 4026 * we must update the softstate, reprogram the MAC to match, and 4027 * record the change in the log and/or on the console. 4028 */ 4029 static void bge_factotum_link_handler(bge_t *bgep); 4030 #pragma no_inline(bge_factotum_link_handler) 4031 4032 static void 4033 bge_factotum_link_handler(bge_t *bgep) 4034 { 4035 void (*logfn)(bge_t *bgep, const char *fmt, ...); 4036 const char *msg; 4037 hrtime_t deltat; 4038 4039 ASSERT(mutex_owned(bgep->genlock)); 4040 4041 /* 4042 * Update the s/w link_state 4043 */ 4044 if (bgep->param_link_up) 4045 bgep->link_state = LINK_STATE_UP; 4046 else 4047 bgep->link_state = LINK_STATE_DOWN; 4048 4049 /* 4050 * Reprogram the MAC modes to match 4051 */ 4052 bge_sync_mac_modes(bgep); 4053 4054 /* 4055 * Finally, we have to decide whether to write a message 4056 * on the console or only in the log. If the PHY has 4057 * been reprogrammed (at user request) "recently", then 4058 * the message only goes in the log. Otherwise it's an 4059 * "unexpected" event, and it goes on the console as well. 4060 */ 4061 deltat = bgep->phys_event_time - bgep->phys_write_time; 4062 if (deltat > BGE_LINK_SETTLE_TIME) 4063 msg = ""; 4064 else if (bgep->param_link_up) 4065 msg = bgep->link_up_msg; 4066 else 4067 msg = bgep->link_down_msg; 4068 4069 logfn = (msg == NULL || *msg == '\0') ? bge_notice : bge_log; 4070 (*logfn)(bgep, "link %s%s", bgep->link_mode_msg, msg); 4071 } 4072 4073 static boolean_t bge_factotum_link_check(bge_t *bgep, int *dma_state); 4074 #pragma no_inline(bge_factotum_link_check) 4075 4076 static boolean_t 4077 bge_factotum_link_check(bge_t *bgep, int *dma_state) 4078 { 4079 boolean_t check; 4080 uint64_t flags; 4081 uint32_t tmac_status; 4082 4083 ASSERT(mutex_owned(bgep->genlock)); 4084 4085 /* 4086 * Get & clear the writable status bits in the Tx status register 4087 * (some bits are write-1-to-clear, others are just readonly). 4088 */ 4089 tmac_status = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 4090 bge_reg_put32(bgep, TRANSMIT_MAC_STATUS_REG, tmac_status); 4091 4092 /* 4093 * Get & clear the ERROR and LINK_CHANGED bits from the status block 4094 */ 4095 *dma_state = bge_status_sync(bgep, STATUS_FLAG_ERROR | 4096 STATUS_FLAG_LINK_CHANGED, &flags); 4097 if (*dma_state != DDI_FM_OK) 4098 return (B_FALSE); 4099 4100 /* 4101 * Clear any errors flagged in the status block ... 4102 */ 4103 if (flags & STATUS_FLAG_ERROR) 4104 bge_factotum_error_handler(bgep); 4105 4106 /* 4107 * We need to check the link status if: 4108 * the status block says there's been a link change 4109 * or there's any discrepancy between the various 4110 * flags indicating the link state (link_state, 4111 * param_link_up, and the LINK STATE bit in the 4112 * Transmit MAC status register). 4113 */ 4114 check = (flags & STATUS_FLAG_LINK_CHANGED) != 0; 4115 switch (bgep->link_state) { 4116 case LINK_STATE_UP: 4117 check |= (bgep->param_link_up == B_FALSE); 4118 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) == 0); 4119 break; 4120 4121 case LINK_STATE_DOWN: 4122 check |= (bgep->param_link_up != B_FALSE); 4123 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) != 0); 4124 break; 4125 4126 default: 4127 check = B_TRUE; 4128 break; 4129 } 4130 4131 /* 4132 * If <check> is false, we're sure the link hasn't changed. 4133 * If true, however, it's not yet definitive; we have to call 4134 * bge_phys_check() to determine whether the link has settled 4135 * into a new state yet ... and if it has, then call the link 4136 * state change handler.But when the chip is 5700 in Dell 6650 4137 * ,even if check is false, the link may have changed.So we 4138 * have to call bge_phys_check() to determine the link state. 4139 */ 4140 if (check || bgep->chipid.device == DEVICE_ID_5700) { 4141 check = bge_phys_check(bgep); 4142 if (check) 4143 bge_factotum_link_handler(bgep); 4144 } 4145 4146 return (check); 4147 } 4148 4149 /* 4150 * Factotum routine to check for Tx stall, using the 'watchdog' counter 4151 */ 4152 static boolean_t bge_factotum_stall_check(bge_t *bgep); 4153 #pragma no_inline(bge_factotum_stall_check) 4154 4155 static boolean_t 4156 bge_factotum_stall_check(bge_t *bgep) 4157 { 4158 uint32_t dogval; 4159 4160 ASSERT(mutex_owned(bgep->genlock)); 4161 4162 /* 4163 * Specific check for Tx stall ... 4164 * 4165 * The 'watchdog' counter is incremented whenever a packet 4166 * is queued, reset to 1 when some (but not all) buffers 4167 * are reclaimed, reset to 0 (disabled) when all buffers 4168 * are reclaimed, and shifted left here. If it exceeds the 4169 * threshold value, the chip is assumed to have stalled and 4170 * is put into the ERROR state. The factotum will then reset 4171 * it on the next pass. 4172 * 4173 * All of which should ensure that we don't get into a state 4174 * where packets are left pending indefinitely! 4175 */ 4176 dogval = bge_atomic_shl32(&bgep->watchdog, 1); 4177 if (dogval < bge_watchdog_count) 4178 return (B_FALSE); 4179 4180 BGE_REPORT((bgep, "Tx stall detected, watchdog code 0x%x", dogval)); 4181 bge_fm_ereport(bgep, DDI_FM_DEVICE_STALL); 4182 return (B_TRUE); 4183 } 4184 4185 /* 4186 * The factotum is woken up when there's something to do that we'd rather 4187 * not do from inside a hardware interrupt handler or high-level cyclic. 4188 * Its two main tasks are: 4189 * reset & restart the chip after an error 4190 * check the link status whenever necessary 4191 */ 4192 uint_t bge_chip_factotum(caddr_t arg); 4193 #pragma no_inline(bge_chip_factotum) 4194 4195 uint_t 4196 bge_chip_factotum(caddr_t arg) 4197 { 4198 bge_t *bgep; 4199 uint_t result; 4200 boolean_t error; 4201 boolean_t linkchg; 4202 int dma_state; 4203 4204 bgep = (bge_t *)arg; 4205 4206 BGE_TRACE(("bge_chip_factotum($%p)", (void *)bgep)); 4207 4208 mutex_enter(bgep->softintrlock); 4209 if (bgep->factotum_flag == 0) { 4210 mutex_exit(bgep->softintrlock); 4211 return (DDI_INTR_UNCLAIMED); 4212 } 4213 bgep->factotum_flag = 0; 4214 mutex_exit(bgep->softintrlock); 4215 4216 result = DDI_INTR_CLAIMED; 4217 error = B_FALSE; 4218 linkchg = B_FALSE; 4219 4220 mutex_enter(bgep->genlock); 4221 switch (bgep->bge_chip_state) { 4222 default: 4223 break; 4224 4225 case BGE_CHIP_RUNNING: 4226 linkchg = bge_factotum_link_check(bgep, &dma_state); 4227 error = bge_factotum_stall_check(bgep); 4228 if (dma_state != DDI_FM_OK) { 4229 bgep->bge_dma_error = B_TRUE; 4230 error = B_TRUE; 4231 } 4232 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4233 error = B_TRUE; 4234 if (error) 4235 bgep->bge_chip_state = BGE_CHIP_ERROR; 4236 break; 4237 4238 case BGE_CHIP_ERROR: 4239 error = B_TRUE; 4240 break; 4241 4242 case BGE_CHIP_FAULT: 4243 /* 4244 * Fault detected, time to reset ... 4245 */ 4246 if (bge_autorecover) { 4247 if (!(bgep->progress & PROGRESS_BUFS)) { 4248 /* 4249 * if we can't allocate the ring buffers, 4250 * try later 4251 */ 4252 if (bge_alloc_bufs(bgep) != DDI_SUCCESS) { 4253 mutex_exit(bgep->genlock); 4254 return (result); 4255 } 4256 bgep->progress |= PROGRESS_BUFS; 4257 } 4258 if (!(bgep->progress & PROGRESS_INTR)) { 4259 bge_init_rings(bgep); 4260 bge_intr_enable(bgep); 4261 bgep->progress |= PROGRESS_INTR; 4262 } 4263 if (!(bgep->progress & PROGRESS_KSTATS)) { 4264 bge_init_kstats(bgep, 4265 ddi_get_instance(bgep->devinfo)); 4266 bgep->progress |= PROGRESS_KSTATS; 4267 } 4268 4269 BGE_REPORT((bgep, "automatic recovery activated")); 4270 4271 if (bge_restart(bgep, B_FALSE) != DDI_SUCCESS) { 4272 bgep->bge_chip_state = BGE_CHIP_ERROR; 4273 error = B_TRUE; 4274 } 4275 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != 4276 DDI_FM_OK) { 4277 bgep->bge_chip_state = BGE_CHIP_ERROR; 4278 error = B_TRUE; 4279 } 4280 if (bge_check_acc_handle(bgep, bgep->io_handle) != 4281 DDI_FM_OK) { 4282 bgep->bge_chip_state = BGE_CHIP_ERROR; 4283 error = B_TRUE; 4284 } 4285 if (error == B_FALSE) { 4286 #ifdef BGE_IPMI_ASF 4287 if (bgep->asf_enabled && 4288 bgep->asf_status != ASF_STAT_RUN) { 4289 bgep->asf_timeout_id = timeout( 4290 bge_asf_heartbeat, (void *)bgep, 4291 drv_usectohz( 4292 BGE_ASF_HEARTBEAT_INTERVAL)); 4293 bgep->asf_status = ASF_STAT_RUN; 4294 } 4295 #endif 4296 ddi_fm_service_impact(bgep->devinfo, 4297 DDI_SERVICE_RESTORED); 4298 } 4299 } 4300 break; 4301 } 4302 4303 4304 /* 4305 * If an error is detected, stop the chip now, marking it as 4306 * faulty, so that it will be reset next time through ... 4307 * 4308 * Note that if intr_running is set, then bge_intr() has dropped 4309 * genlock to call bge_receive/bge_recycle. Can't stop the chip at 4310 * this point so have to wait until the next time the factotum runs. 4311 */ 4312 if (error && !bgep->bge_intr_running) { 4313 #ifdef BGE_IPMI_ASF 4314 if (bgep->asf_enabled && (bgep->asf_status == ASF_STAT_RUN)) { 4315 /* 4316 * We must stop ASF heart beat before bge_chip_stop(), 4317 * otherwise some computers (ex. IBM HS20 blade server) 4318 * may crash. 4319 */ 4320 bge_asf_update_status(bgep); 4321 bge_asf_stop_timer(bgep); 4322 bgep->asf_status = ASF_STAT_STOP; 4323 4324 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 4325 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 4326 } 4327 #endif 4328 bge_chip_stop(bgep, B_TRUE); 4329 (void) bge_check_acc_handle(bgep, bgep->io_handle); 4330 } 4331 mutex_exit(bgep->genlock); 4332 4333 /* 4334 * If the link state changed, tell the world about it. 4335 * Note: can't do this while still holding the mutex. 4336 */ 4337 if (linkchg) 4338 mac_link_update(bgep->mh, bgep->link_state); 4339 4340 return (result); 4341 } 4342 4343 /* 4344 * High-level cyclic handler 4345 * 4346 * This routine schedules a (low-level) softint callback to the 4347 * factotum, and prods the chip to update the status block (which 4348 * will cause a hardware interrupt when complete). 4349 */ 4350 void bge_chip_cyclic(void *arg); 4351 #pragma no_inline(bge_chip_cyclic) 4352 4353 void 4354 bge_chip_cyclic(void *arg) 4355 { 4356 bge_t *bgep; 4357 4358 bgep = arg; 4359 4360 switch (bgep->bge_chip_state) { 4361 default: 4362 return; 4363 4364 case BGE_CHIP_RUNNING: 4365 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, COALESCE_NOW); 4366 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4367 ddi_fm_service_impact(bgep->devinfo, 4368 DDI_SERVICE_UNAFFECTED); 4369 break; 4370 4371 case BGE_CHIP_FAULT: 4372 case BGE_CHIP_ERROR: 4373 break; 4374 } 4375 4376 bge_wake_factotum(bgep); 4377 } 4378 4379 4380 /* 4381 * ========== Ioctl subfunctions ========== 4382 */ 4383 4384 #undef BGE_DBG 4385 #define BGE_DBG BGE_DBG_PPIO /* debug flag for this code */ 4386 4387 #if BGE_DEBUGGING || BGE_DO_PPIO 4388 4389 static void bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 4390 #pragma no_inline(bge_chip_peek_cfg) 4391 4392 static void 4393 bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 4394 { 4395 uint64_t regval; 4396 uint64_t regno; 4397 4398 BGE_TRACE(("bge_chip_peek_cfg($%p, $%p)", 4399 (void *)bgep, (void *)ppd)); 4400 4401 regno = ppd->pp_acc_offset; 4402 4403 switch (ppd->pp_acc_size) { 4404 case 1: 4405 regval = pci_config_get8(bgep->cfg_handle, regno); 4406 break; 4407 4408 case 2: 4409 regval = pci_config_get16(bgep->cfg_handle, regno); 4410 break; 4411 4412 case 4: 4413 regval = pci_config_get32(bgep->cfg_handle, regno); 4414 break; 4415 4416 case 8: 4417 regval = pci_config_get64(bgep->cfg_handle, regno); 4418 break; 4419 } 4420 4421 ppd->pp_acc_data = regval; 4422 } 4423 4424 static void bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 4425 #pragma no_inline(bge_chip_poke_cfg) 4426 4427 static void 4428 bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 4429 { 4430 uint64_t regval; 4431 uint64_t regno; 4432 4433 BGE_TRACE(("bge_chip_poke_cfg($%p, $%p)", 4434 (void *)bgep, (void *)ppd)); 4435 4436 regno = ppd->pp_acc_offset; 4437 regval = ppd->pp_acc_data; 4438 4439 switch (ppd->pp_acc_size) { 4440 case 1: 4441 pci_config_put8(bgep->cfg_handle, regno, regval); 4442 break; 4443 4444 case 2: 4445 pci_config_put16(bgep->cfg_handle, regno, regval); 4446 break; 4447 4448 case 4: 4449 pci_config_put32(bgep->cfg_handle, regno, regval); 4450 break; 4451 4452 case 8: 4453 pci_config_put64(bgep->cfg_handle, regno, regval); 4454 break; 4455 } 4456 } 4457 4458 static void bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd); 4459 #pragma no_inline(bge_chip_peek_reg) 4460 4461 static void 4462 bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd) 4463 { 4464 uint64_t regval; 4465 void *regaddr; 4466 4467 BGE_TRACE(("bge_chip_peek_reg($%p, $%p)", 4468 (void *)bgep, (void *)ppd)); 4469 4470 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 4471 4472 switch (ppd->pp_acc_size) { 4473 case 1: 4474 regval = ddi_get8(bgep->io_handle, regaddr); 4475 break; 4476 4477 case 2: 4478 regval = ddi_get16(bgep->io_handle, regaddr); 4479 break; 4480 4481 case 4: 4482 regval = ddi_get32(bgep->io_handle, regaddr); 4483 break; 4484 4485 case 8: 4486 regval = ddi_get64(bgep->io_handle, regaddr); 4487 break; 4488 } 4489 4490 ppd->pp_acc_data = regval; 4491 } 4492 4493 static void bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd); 4494 #pragma no_inline(bge_chip_peek_reg) 4495 4496 static void 4497 bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd) 4498 { 4499 uint64_t regval; 4500 void *regaddr; 4501 4502 BGE_TRACE(("bge_chip_poke_reg($%p, $%p)", 4503 (void *)bgep, (void *)ppd)); 4504 4505 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 4506 regval = ppd->pp_acc_data; 4507 4508 switch (ppd->pp_acc_size) { 4509 case 1: 4510 ddi_put8(bgep->io_handle, regaddr, regval); 4511 break; 4512 4513 case 2: 4514 ddi_put16(bgep->io_handle, regaddr, regval); 4515 break; 4516 4517 case 4: 4518 ddi_put32(bgep->io_handle, regaddr, regval); 4519 break; 4520 4521 case 8: 4522 ddi_put64(bgep->io_handle, regaddr, regval); 4523 break; 4524 } 4525 BGE_PCICHK(bgep); 4526 } 4527 4528 static void bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd); 4529 #pragma no_inline(bge_chip_peek_nic) 4530 4531 static void 4532 bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd) 4533 { 4534 uint64_t regoff; 4535 uint64_t regval; 4536 void *regaddr; 4537 4538 BGE_TRACE(("bge_chip_peek_nic($%p, $%p)", 4539 (void *)bgep, (void *)ppd)); 4540 4541 regoff = ppd->pp_acc_offset; 4542 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 4543 regoff &= MWBAR_GRANULE_MASK; 4544 regoff += NIC_MEM_WINDOW_OFFSET; 4545 regaddr = PIO_ADDR(bgep, regoff); 4546 4547 switch (ppd->pp_acc_size) { 4548 case 1: 4549 regval = ddi_get8(bgep->io_handle, regaddr); 4550 break; 4551 4552 case 2: 4553 regval = ddi_get16(bgep->io_handle, regaddr); 4554 break; 4555 4556 case 4: 4557 regval = ddi_get32(bgep->io_handle, regaddr); 4558 break; 4559 4560 case 8: 4561 regval = ddi_get64(bgep->io_handle, regaddr); 4562 break; 4563 } 4564 4565 ppd->pp_acc_data = regval; 4566 } 4567 4568 static void bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd); 4569 #pragma no_inline(bge_chip_poke_nic) 4570 4571 static void 4572 bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd) 4573 { 4574 uint64_t regoff; 4575 uint64_t regval; 4576 void *regaddr; 4577 4578 BGE_TRACE(("bge_chip_poke_nic($%p, $%p)", 4579 (void *)bgep, (void *)ppd)); 4580 4581 regoff = ppd->pp_acc_offset; 4582 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 4583 regoff &= MWBAR_GRANULE_MASK; 4584 regoff += NIC_MEM_WINDOW_OFFSET; 4585 regaddr = PIO_ADDR(bgep, regoff); 4586 regval = ppd->pp_acc_data; 4587 4588 switch (ppd->pp_acc_size) { 4589 case 1: 4590 ddi_put8(bgep->io_handle, regaddr, regval); 4591 break; 4592 4593 case 2: 4594 ddi_put16(bgep->io_handle, regaddr, regval); 4595 break; 4596 4597 case 4: 4598 ddi_put32(bgep->io_handle, regaddr, regval); 4599 break; 4600 4601 case 8: 4602 ddi_put64(bgep->io_handle, regaddr, regval); 4603 break; 4604 } 4605 BGE_PCICHK(bgep); 4606 } 4607 4608 static void bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd); 4609 #pragma no_inline(bge_chip_peek_mii) 4610 4611 static void 4612 bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd) 4613 { 4614 BGE_TRACE(("bge_chip_peek_mii($%p, $%p)", 4615 (void *)bgep, (void *)ppd)); 4616 4617 ppd->pp_acc_data = bge_mii_get16(bgep, ppd->pp_acc_offset/2); 4618 } 4619 4620 static void bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd); 4621 #pragma no_inline(bge_chip_poke_mii) 4622 4623 static void 4624 bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd) 4625 { 4626 BGE_TRACE(("bge_chip_poke_mii($%p, $%p)", 4627 (void *)bgep, (void *)ppd)); 4628 4629 bge_mii_put16(bgep, ppd->pp_acc_offset/2, ppd->pp_acc_data); 4630 } 4631 4632 #if BGE_SEE_IO32 4633 4634 static void bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 4635 #pragma no_inline(bge_chip_peek_seeprom) 4636 4637 static void 4638 bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 4639 { 4640 uint32_t data; 4641 int err; 4642 4643 BGE_TRACE(("bge_chip_peek_seeprom($%p, $%p)", 4644 (void *)bgep, (void *)ppd)); 4645 4646 err = bge_nvmem_rw32(bgep, BGE_SEE_READ, ppd->pp_acc_offset, &data); 4647 ppd->pp_acc_data = err ? ~0ull : data; 4648 } 4649 4650 static void bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 4651 #pragma no_inline(bge_chip_poke_seeprom) 4652 4653 static void 4654 bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 4655 { 4656 uint32_t data; 4657 4658 BGE_TRACE(("bge_chip_poke_seeprom($%p, $%p)", 4659 (void *)bgep, (void *)ppd)); 4660 4661 data = ppd->pp_acc_data; 4662 (void) bge_nvmem_rw32(bgep, BGE_SEE_WRITE, ppd->pp_acc_offset, &data); 4663 } 4664 #endif /* BGE_SEE_IO32 */ 4665 4666 #if BGE_FLASH_IO32 4667 4668 static void bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd); 4669 #pragma no_inline(bge_chip_peek_flash) 4670 4671 static void 4672 bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd) 4673 { 4674 uint32_t data; 4675 int err; 4676 4677 BGE_TRACE(("bge_chip_peek_flash($%p, $%p)", 4678 (void *)bgep, (void *)ppd)); 4679 4680 err = bge_nvmem_rw32(bgep, BGE_FLASH_READ, ppd->pp_acc_offset, &data); 4681 ppd->pp_acc_data = err ? ~0ull : data; 4682 } 4683 4684 static void bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd); 4685 #pragma no_inline(bge_chip_poke_flash) 4686 4687 static void 4688 bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd) 4689 { 4690 uint32_t data; 4691 4692 BGE_TRACE(("bge_chip_poke_flash($%p, $%p)", 4693 (void *)bgep, (void *)ppd)); 4694 4695 data = ppd->pp_acc_data; 4696 (void) bge_nvmem_rw32(bgep, BGE_FLASH_WRITE, 4697 ppd->pp_acc_offset, &data); 4698 } 4699 #endif /* BGE_FLASH_IO32 */ 4700 4701 static void bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd); 4702 #pragma no_inline(bge_chip_peek_mem) 4703 4704 static void 4705 bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd) 4706 { 4707 uint64_t regval; 4708 void *vaddr; 4709 4710 BGE_TRACE(("bge_chip_peek_bge($%p, $%p)", 4711 (void *)bgep, (void *)ppd)); 4712 4713 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4714 4715 switch (ppd->pp_acc_size) { 4716 case 1: 4717 regval = *(uint8_t *)vaddr; 4718 break; 4719 4720 case 2: 4721 regval = *(uint16_t *)vaddr; 4722 break; 4723 4724 case 4: 4725 regval = *(uint32_t *)vaddr; 4726 break; 4727 4728 case 8: 4729 regval = *(uint64_t *)vaddr; 4730 break; 4731 } 4732 4733 BGE_DEBUG(("bge_chip_peek_mem($%p, $%p) peeked 0x%llx from $%p", 4734 (void *)bgep, (void *)ppd, regval, vaddr)); 4735 4736 ppd->pp_acc_data = regval; 4737 } 4738 4739 static void bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd); 4740 #pragma no_inline(bge_chip_poke_mem) 4741 4742 static void 4743 bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd) 4744 { 4745 uint64_t regval; 4746 void *vaddr; 4747 4748 BGE_TRACE(("bge_chip_poke_mem($%p, $%p)", 4749 (void *)bgep, (void *)ppd)); 4750 4751 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4752 regval = ppd->pp_acc_data; 4753 4754 BGE_DEBUG(("bge_chip_poke_mem($%p, $%p) poking 0x%llx at $%p", 4755 (void *)bgep, (void *)ppd, regval, vaddr)); 4756 4757 switch (ppd->pp_acc_size) { 4758 case 1: 4759 *(uint8_t *)vaddr = (uint8_t)regval; 4760 break; 4761 4762 case 2: 4763 *(uint16_t *)vaddr = (uint16_t)regval; 4764 break; 4765 4766 case 4: 4767 *(uint32_t *)vaddr = (uint32_t)regval; 4768 break; 4769 4770 case 8: 4771 *(uint64_t *)vaddr = (uint64_t)regval; 4772 break; 4773 } 4774 } 4775 4776 static enum ioc_reply bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 4777 struct iocblk *iocp); 4778 #pragma no_inline(bge_pp_ioctl) 4779 4780 static enum ioc_reply 4781 bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 4782 { 4783 void (*ppfn)(bge_t *bgep, bge_peekpoke_t *ppd); 4784 bge_peekpoke_t *ppd; 4785 dma_area_t *areap; 4786 uint64_t sizemask; 4787 uint64_t mem_va; 4788 uint64_t maxoff; 4789 boolean_t peek; 4790 4791 switch (cmd) { 4792 default: 4793 /* NOTREACHED */ 4794 bge_error(bgep, "bge_pp_ioctl: invalid cmd 0x%x", cmd); 4795 return (IOC_INVAL); 4796 4797 case BGE_PEEK: 4798 peek = B_TRUE; 4799 break; 4800 4801 case BGE_POKE: 4802 peek = B_FALSE; 4803 break; 4804 } 4805 4806 /* 4807 * Validate format of ioctl 4808 */ 4809 if (iocp->ioc_count != sizeof (bge_peekpoke_t)) 4810 return (IOC_INVAL); 4811 if (mp->b_cont == NULL) 4812 return (IOC_INVAL); 4813 ppd = (bge_peekpoke_t *)mp->b_cont->b_rptr; 4814 4815 /* 4816 * Validate request parameters 4817 */ 4818 switch (ppd->pp_acc_space) { 4819 default: 4820 return (IOC_INVAL); 4821 4822 case BGE_PP_SPACE_CFG: 4823 /* 4824 * Config space 4825 */ 4826 sizemask = 8|4|2|1; 4827 mem_va = 0; 4828 maxoff = PCI_CONF_HDR_SIZE; 4829 ppfn = peek ? bge_chip_peek_cfg : bge_chip_poke_cfg; 4830 break; 4831 4832 case BGE_PP_SPACE_REG: 4833 /* 4834 * Memory-mapped I/O space 4835 */ 4836 sizemask = 8|4|2|1; 4837 mem_va = 0; 4838 maxoff = RIAAR_REGISTER_MAX; 4839 ppfn = peek ? bge_chip_peek_reg : bge_chip_poke_reg; 4840 break; 4841 4842 case BGE_PP_SPACE_NIC: 4843 /* 4844 * NIC on-chip memory 4845 */ 4846 sizemask = 8|4|2|1; 4847 mem_va = 0; 4848 maxoff = MWBAR_ONCHIP_MAX; 4849 ppfn = peek ? bge_chip_peek_nic : bge_chip_poke_nic; 4850 break; 4851 4852 case BGE_PP_SPACE_MII: 4853 /* 4854 * PHY's MII registers 4855 * NB: all PHY registers are two bytes, but the 4856 * addresses increment in ones (word addressing). 4857 * So we scale the address here, then undo the 4858 * transformation inside the peek/poke functions. 4859 */ 4860 ppd->pp_acc_offset *= 2; 4861 sizemask = 2; 4862 mem_va = 0; 4863 maxoff = (MII_MAXREG+1)*2; 4864 ppfn = peek ? bge_chip_peek_mii : bge_chip_poke_mii; 4865 break; 4866 4867 #if BGE_SEE_IO32 4868 case BGE_PP_SPACE_SEEPROM: 4869 /* 4870 * Attached SEEPROM(s), if any. 4871 * NB: we use the high-order bits of the 'address' as 4872 * a device select to accommodate multiple SEEPROMS, 4873 * If each one is the maximum size (64kbytes), this 4874 * makes them appear contiguous. Otherwise, there may 4875 * be holes in the mapping. ENxS doesn't have any 4876 * SEEPROMs anyway ... 4877 */ 4878 sizemask = 4; 4879 mem_va = 0; 4880 maxoff = SEEPROM_DEV_AND_ADDR_MASK; 4881 ppfn = peek ? bge_chip_peek_seeprom : bge_chip_poke_seeprom; 4882 break; 4883 #endif /* BGE_SEE_IO32 */ 4884 4885 #if BGE_FLASH_IO32 4886 case BGE_PP_SPACE_FLASH: 4887 /* 4888 * Attached Flash device (if any); a maximum of one device 4889 * is currently supported. But it can be up to 1MB (unlike 4890 * the 64k limit on SEEPROMs) so why would you need more ;-) 4891 */ 4892 sizemask = 4; 4893 mem_va = 0; 4894 maxoff = NVM_FLASH_ADDR_MASK; 4895 ppfn = peek ? bge_chip_peek_flash : bge_chip_poke_flash; 4896 break; 4897 #endif /* BGE_FLASH_IO32 */ 4898 4899 case BGE_PP_SPACE_BGE: 4900 /* 4901 * BGE data structure! 4902 */ 4903 sizemask = 8|4|2|1; 4904 mem_va = (uintptr_t)bgep; 4905 maxoff = sizeof (*bgep); 4906 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 4907 break; 4908 4909 case BGE_PP_SPACE_STATUS: 4910 case BGE_PP_SPACE_STATISTICS: 4911 case BGE_PP_SPACE_TXDESC: 4912 case BGE_PP_SPACE_TXBUFF: 4913 case BGE_PP_SPACE_RXDESC: 4914 case BGE_PP_SPACE_RXBUFF: 4915 /* 4916 * Various DMA_AREAs 4917 */ 4918 switch (ppd->pp_acc_space) { 4919 case BGE_PP_SPACE_TXDESC: 4920 areap = &bgep->tx_desc; 4921 break; 4922 case BGE_PP_SPACE_TXBUFF: 4923 areap = &bgep->tx_buff[0]; 4924 break; 4925 case BGE_PP_SPACE_RXDESC: 4926 areap = &bgep->rx_desc[0]; 4927 break; 4928 case BGE_PP_SPACE_RXBUFF: 4929 areap = &bgep->rx_buff[0]; 4930 break; 4931 case BGE_PP_SPACE_STATUS: 4932 areap = &bgep->status_block; 4933 break; 4934 case BGE_PP_SPACE_STATISTICS: 4935 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 4936 areap = &bgep->statistics; 4937 break; 4938 } 4939 4940 sizemask = 8|4|2|1; 4941 mem_va = (uintptr_t)areap->mem_va; 4942 maxoff = areap->alength; 4943 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 4944 break; 4945 } 4946 4947 switch (ppd->pp_acc_size) { 4948 default: 4949 return (IOC_INVAL); 4950 4951 case 8: 4952 case 4: 4953 case 2: 4954 case 1: 4955 if ((ppd->pp_acc_size & sizemask) == 0) 4956 return (IOC_INVAL); 4957 break; 4958 } 4959 4960 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 4961 return (IOC_INVAL); 4962 4963 if (ppd->pp_acc_offset >= maxoff) 4964 return (IOC_INVAL); 4965 4966 if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff) 4967 return (IOC_INVAL); 4968 4969 /* 4970 * All OK - go do it! 4971 */ 4972 ppd->pp_acc_offset += mem_va; 4973 (*ppfn)(bgep, ppd); 4974 return (peek ? IOC_REPLY : IOC_ACK); 4975 } 4976 4977 static enum ioc_reply bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 4978 struct iocblk *iocp); 4979 #pragma no_inline(bge_diag_ioctl) 4980 4981 static enum ioc_reply 4982 bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 4983 { 4984 ASSERT(mutex_owned(bgep->genlock)); 4985 4986 switch (cmd) { 4987 default: 4988 /* NOTREACHED */ 4989 bge_error(bgep, "bge_diag_ioctl: invalid cmd 0x%x", cmd); 4990 return (IOC_INVAL); 4991 4992 case BGE_DIAG: 4993 /* 4994 * Currently a no-op 4995 */ 4996 return (IOC_ACK); 4997 4998 case BGE_PEEK: 4999 case BGE_POKE: 5000 return (bge_pp_ioctl(bgep, cmd, mp, iocp)); 5001 5002 case BGE_PHY_RESET: 5003 return (IOC_RESTART_ACK); 5004 5005 case BGE_SOFT_RESET: 5006 case BGE_HARD_RESET: 5007 /* 5008 * Reset and reinitialise the 570x hardware 5009 */ 5010 (void) bge_restart(bgep, cmd == BGE_HARD_RESET); 5011 return (IOC_ACK); 5012 } 5013 5014 /* NOTREACHED */ 5015 } 5016 5017 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 5018 5019 static enum ioc_reply bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5020 struct iocblk *iocp); 5021 #pragma no_inline(bge_mii_ioctl) 5022 5023 static enum ioc_reply 5024 bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5025 { 5026 struct bge_mii_rw *miirwp; 5027 5028 /* 5029 * Validate format of ioctl 5030 */ 5031 if (iocp->ioc_count != sizeof (struct bge_mii_rw)) 5032 return (IOC_INVAL); 5033 if (mp->b_cont == NULL) 5034 return (IOC_INVAL); 5035 miirwp = (struct bge_mii_rw *)mp->b_cont->b_rptr; 5036 5037 /* 5038 * Validate request parameters ... 5039 */ 5040 if (miirwp->mii_reg > MII_MAXREG) 5041 return (IOC_INVAL); 5042 5043 switch (cmd) { 5044 default: 5045 /* NOTREACHED */ 5046 bge_error(bgep, "bge_mii_ioctl: invalid cmd 0x%x", cmd); 5047 return (IOC_INVAL); 5048 5049 case BGE_MII_READ: 5050 miirwp->mii_data = bge_mii_get16(bgep, miirwp->mii_reg); 5051 return (IOC_REPLY); 5052 5053 case BGE_MII_WRITE: 5054 bge_mii_put16(bgep, miirwp->mii_reg, miirwp->mii_data); 5055 return (IOC_ACK); 5056 } 5057 5058 /* NOTREACHED */ 5059 } 5060 5061 #if BGE_SEE_IO32 5062 5063 static enum ioc_reply bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5064 struct iocblk *iocp); 5065 #pragma no_inline(bge_see_ioctl) 5066 5067 static enum ioc_reply 5068 bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5069 { 5070 struct bge_see_rw *seerwp; 5071 5072 /* 5073 * Validate format of ioctl 5074 */ 5075 if (iocp->ioc_count != sizeof (struct bge_see_rw)) 5076 return (IOC_INVAL); 5077 if (mp->b_cont == NULL) 5078 return (IOC_INVAL); 5079 seerwp = (struct bge_see_rw *)mp->b_cont->b_rptr; 5080 5081 /* 5082 * Validate request parameters ... 5083 */ 5084 if (seerwp->see_addr & ~SEEPROM_DEV_AND_ADDR_MASK) 5085 return (IOC_INVAL); 5086 5087 switch (cmd) { 5088 default: 5089 /* NOTREACHED */ 5090 bge_error(bgep, "bge_see_ioctl: invalid cmd 0x%x", cmd); 5091 return (IOC_INVAL); 5092 5093 case BGE_SEE_READ: 5094 case BGE_SEE_WRITE: 5095 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 5096 seerwp->see_addr, &seerwp->see_data); 5097 return (IOC_REPLY); 5098 } 5099 5100 /* NOTREACHED */ 5101 } 5102 5103 #endif /* BGE_SEE_IO32 */ 5104 5105 #if BGE_FLASH_IO32 5106 5107 static enum ioc_reply bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5108 struct iocblk *iocp); 5109 #pragma no_inline(bge_flash_ioctl) 5110 5111 static enum ioc_reply 5112 bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5113 { 5114 struct bge_flash_rw *flashrwp; 5115 5116 /* 5117 * Validate format of ioctl 5118 */ 5119 if (iocp->ioc_count != sizeof (struct bge_flash_rw)) 5120 return (IOC_INVAL); 5121 if (mp->b_cont == NULL) 5122 return (IOC_INVAL); 5123 flashrwp = (struct bge_flash_rw *)mp->b_cont->b_rptr; 5124 5125 /* 5126 * Validate request parameters ... 5127 */ 5128 if (flashrwp->flash_addr & ~NVM_FLASH_ADDR_MASK) 5129 return (IOC_INVAL); 5130 5131 switch (cmd) { 5132 default: 5133 /* NOTREACHED */ 5134 bge_error(bgep, "bge_flash_ioctl: invalid cmd 0x%x", cmd); 5135 return (IOC_INVAL); 5136 5137 case BGE_FLASH_READ: 5138 case BGE_FLASH_WRITE: 5139 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 5140 flashrwp->flash_addr, &flashrwp->flash_data); 5141 return (IOC_REPLY); 5142 } 5143 5144 /* NOTREACHED */ 5145 } 5146 5147 #endif /* BGE_FLASH_IO32 */ 5148 5149 enum ioc_reply bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, 5150 struct iocblk *iocp); 5151 #pragma no_inline(bge_chip_ioctl) 5152 5153 enum ioc_reply 5154 bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 5155 { 5156 int cmd; 5157 5158 BGE_TRACE(("bge_chip_ioctl($%p, $%p, $%p, $%p)", 5159 (void *)bgep, (void *)wq, (void *)mp, (void *)iocp)); 5160 5161 ASSERT(mutex_owned(bgep->genlock)); 5162 5163 cmd = iocp->ioc_cmd; 5164 switch (cmd) { 5165 default: 5166 /* NOTREACHED */ 5167 bge_error(bgep, "bge_chip_ioctl: invalid cmd 0x%x", cmd); 5168 return (IOC_INVAL); 5169 5170 case BGE_DIAG: 5171 case BGE_PEEK: 5172 case BGE_POKE: 5173 case BGE_PHY_RESET: 5174 case BGE_SOFT_RESET: 5175 case BGE_HARD_RESET: 5176 #if BGE_DEBUGGING || BGE_DO_PPIO 5177 return (bge_diag_ioctl(bgep, cmd, mp, iocp)); 5178 #else 5179 return (IOC_INVAL); 5180 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 5181 5182 case BGE_MII_READ: 5183 case BGE_MII_WRITE: 5184 return (bge_mii_ioctl(bgep, cmd, mp, iocp)); 5185 5186 #if BGE_SEE_IO32 5187 case BGE_SEE_READ: 5188 case BGE_SEE_WRITE: 5189 return (bge_see_ioctl(bgep, cmd, mp, iocp)); 5190 #endif /* BGE_SEE_IO32 */ 5191 5192 #if BGE_FLASH_IO32 5193 case BGE_FLASH_READ: 5194 case BGE_FLASH_WRITE: 5195 return (bge_flash_ioctl(bgep, cmd, mp, iocp)); 5196 #endif /* BGE_FLASH_IO32 */ 5197 } 5198 5199 /* NOTREACHED */ 5200 } 5201 5202 void 5203 bge_chip_blank(void *arg, time_t ticks, uint_t count) 5204 { 5205 bge_t *bgep = arg; 5206 5207 mutex_enter(bgep->genlock); 5208 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, ticks); 5209 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, count); 5210 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5211 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 5212 mutex_exit(bgep->genlock); 5213 } 5214 5215 #ifdef BGE_IPMI_ASF 5216 5217 uint32_t 5218 bge_nic_read32(bge_t *bgep, bge_regno_t addr) 5219 { 5220 uint32_t data; 5221 5222 if (!bgep->asf_wordswapped) { 5223 /* a workaround word swap error */ 5224 if (addr & 4) 5225 addr = addr - 4; 5226 else 5227 addr = addr + 4; 5228 } 5229 5230 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr); 5231 data = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR); 5232 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0); 5233 5234 return (data); 5235 } 5236 5237 5238 void 5239 bge_asf_update_status(bge_t *bgep) 5240 { 5241 uint32_t event; 5242 5243 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_ALIVE); 5244 bge_nic_put32(bgep, BGE_CMD_LENGTH_MAILBOX, 4); 5245 bge_nic_put32(bgep, BGE_CMD_DATA_MAILBOX, 3); 5246 5247 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5248 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 5249 } 5250 5251 5252 /* 5253 * The driver is supposed to notify ASF that the OS is still running 5254 * every three seconds, otherwise the management server may attempt 5255 * to reboot the machine. If it hasn't actually failed, this is 5256 * not a desirable result. However, this isn't running as a real-time 5257 * thread, and even if it were, it might not be able to generate the 5258 * heartbeat in a timely manner due to system load. As it isn't a 5259 * significant strain on the machine, we will set the interval to half 5260 * of the required value. 5261 */ 5262 void 5263 bge_asf_heartbeat(void *arg) 5264 { 5265 bge_t *bgep = (bge_t *)arg; 5266 5267 mutex_enter(bgep->genlock); 5268 bge_asf_update_status((bge_t *)bgep); 5269 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5270 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 5271 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) 5272 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 5273 mutex_exit(bgep->genlock); 5274 ((bge_t *)bgep)->asf_timeout_id = timeout(bge_asf_heartbeat, bgep, 5275 drv_usectohz(BGE_ASF_HEARTBEAT_INTERVAL)); 5276 } 5277 5278 5279 void 5280 bge_asf_stop_timer(bge_t *bgep) 5281 { 5282 timeout_id_t tmp_id = 0; 5283 5284 while ((bgep->asf_timeout_id != 0) && 5285 (tmp_id != bgep->asf_timeout_id)) { 5286 tmp_id = bgep->asf_timeout_id; 5287 (void) untimeout(tmp_id); 5288 } 5289 bgep->asf_timeout_id = 0; 5290 } 5291 5292 5293 5294 /* 5295 * This function should be placed at the earliest position of bge_attach(). 5296 */ 5297 void 5298 bge_asf_get_config(bge_t *bgep) 5299 { 5300 uint32_t nicsig; 5301 uint32_t niccfg; 5302 5303 nicsig = bge_nic_read32(bgep, BGE_NIC_DATA_SIG_ADDR); 5304 if (nicsig == BGE_NIC_DATA_SIG) { 5305 niccfg = bge_nic_read32(bgep, BGE_NIC_DATA_NIC_CFG_ADDR); 5306 if (niccfg & BGE_NIC_CFG_ENABLE_ASF) 5307 /* 5308 * Here, we don't consider BAXTER, because BGE haven't 5309 * supported BAXTER (that is 5752). Also, as I know, 5310 * BAXTER doesn't support ASF feature. 5311 */ 5312 bgep->asf_enabled = B_TRUE; 5313 else 5314 bgep->asf_enabled = B_FALSE; 5315 } else 5316 bgep->asf_enabled = B_FALSE; 5317 } 5318 5319 5320 void 5321 bge_asf_pre_reset_operations(bge_t *bgep, uint32_t mode) 5322 { 5323 uint32_t tries; 5324 uint32_t event; 5325 5326 ASSERT(bgep->asf_enabled); 5327 5328 /* Issues "pause firmware" command and wait for ACK */ 5329 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_PAUSE_FW); 5330 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5331 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 5332 5333 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5334 tries = 0; 5335 while ((event & RRER_ASF_EVENT) && (tries < 100)) { 5336 drv_usecwait(1); 5337 tries ++; 5338 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5339 } 5340 5341 bge_nic_put32(bgep, BGE_FIRMWARE_MAILBOX, 5342 BGE_MAGIC_NUM_FIRMWARE_INIT_DONE); 5343 5344 if (bgep->asf_newhandshake) { 5345 switch (mode) { 5346 case BGE_INIT_RESET: 5347 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5348 BGE_DRV_STATE_START); 5349 break; 5350 case BGE_SHUTDOWN_RESET: 5351 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5352 BGE_DRV_STATE_UNLOAD); 5353 break; 5354 case BGE_SUSPEND_RESET: 5355 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5356 BGE_DRV_STATE_SUSPEND); 5357 break; 5358 default: 5359 break; 5360 } 5361 } 5362 } 5363 5364 5365 void 5366 bge_asf_post_reset_old_mode(bge_t *bgep, uint32_t mode) 5367 { 5368 switch (mode) { 5369 case BGE_INIT_RESET: 5370 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5371 BGE_DRV_STATE_START); 5372 break; 5373 case BGE_SHUTDOWN_RESET: 5374 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5375 BGE_DRV_STATE_UNLOAD); 5376 break; 5377 case BGE_SUSPEND_RESET: 5378 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5379 BGE_DRV_STATE_SUSPEND); 5380 break; 5381 default: 5382 break; 5383 } 5384 } 5385 5386 5387 void 5388 bge_asf_post_reset_new_mode(bge_t *bgep, uint32_t mode) 5389 { 5390 switch (mode) { 5391 case BGE_INIT_RESET: 5392 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5393 BGE_DRV_STATE_START_DONE); 5394 break; 5395 case BGE_SHUTDOWN_RESET: 5396 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5397 BGE_DRV_STATE_UNLOAD_DONE); 5398 break; 5399 default: 5400 break; 5401 } 5402 } 5403 5404 #endif /* BGE_IPMI_ASF */ 5405