1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved. 24 */ 25 26 #include "bge_impl.h" 27 28 #define PIO_ADDR(bgep, offset) ((void *)((caddr_t)(bgep)->io_regs+(offset))) 29 30 /* 31 * Future features ... ? 32 */ 33 #define BGE_CFG_IO8 1 /* 8/16-bit cfg space BIS/BIC */ 34 #define BGE_IND_IO32 1 /* indirect access code */ 35 #define BGE_SEE_IO32 1 /* SEEPROM access code */ 36 #define BGE_FLASH_IO32 1 /* FLASH access code */ 37 38 /* 39 * BGE MSI tunable: 40 * 41 * By default MSI is enabled on all supported platforms but it is disabled 42 * for some Broadcom chips due to known MSI hardware issues. Currently MSI 43 * is enabled only for 5714C A2 and 5715C A2 broadcom chips. 44 */ 45 boolean_t bge_enable_msi = B_TRUE; 46 47 /* 48 * PCI-X/PCI-E relaxed ordering tunable for OS/Nexus driver 49 */ 50 boolean_t bge_relaxed_ordering = B_TRUE; 51 52 /* 53 * Property names 54 */ 55 static char knownids_propname[] = "bge-known-subsystems"; 56 57 /* 58 * Patchable globals: 59 * 60 * bge_autorecover 61 * Enables/disables automatic recovery after fault detection 62 * 63 * bge_mlcr_default 64 * Value to program into the MLCR; controls the chip's GPIO pins 65 * 66 * bge_dma_{rd,wr}prio 67 * Relative priorities of DMA reads & DMA writes respectively. 68 * These may each be patched to any value 0-3. Equal values 69 * will give "fair" (round-robin) arbitration for PCI access. 70 * Unequal values will give one or the other function priority. 71 * 72 * bge_dma_rwctrl 73 * Value to put in the Read/Write DMA control register. See 74 * the Broadcom PRM for things you can fiddle with in this 75 * register ... 76 * 77 * bge_{tx,rx}_{count,ticks}_{norm,intr} 78 * Send/receive interrupt coalescing parameters. Counts are 79 * #s of descriptors, ticks are in microseconds. *norm* values 80 * apply between status updates/interrupts; the *intr* values 81 * refer to the 'during-interrupt' versions - see the PRM. 82 * 83 * NOTE: these values have been determined by measurement. They 84 * differ significantly from the values recommended in the PRM. 85 */ 86 static uint32_t bge_autorecover = 1; 87 static uint32_t bge_mlcr_default_5714 = MLCR_DEFAULT_5714; 88 89 static uint32_t bge_dma_rdprio = 1; 90 static uint32_t bge_dma_wrprio = 0; 91 static uint32_t bge_dma_rwctrl = PDRWCR_VAR_DEFAULT; 92 static uint32_t bge_dma_rwctrl_5721 = PDRWCR_VAR_5721; 93 static uint32_t bge_dma_rwctrl_5714 = PDRWCR_VAR_5714; 94 static uint32_t bge_dma_rwctrl_5715 = PDRWCR_VAR_5715; 95 96 uint32_t bge_rx_ticks_norm = 128; 97 uint32_t bge_tx_ticks_norm = 2048; /* 8 for FJ2+ !?!? */ 98 uint32_t bge_rx_count_norm = 8; 99 uint32_t bge_tx_count_norm = 128; 100 101 static uint32_t bge_rx_ticks_intr = 128; 102 static uint32_t bge_tx_ticks_intr = 0; /* 8 for FJ2+ !?!? */ 103 static uint32_t bge_rx_count_intr = 2; 104 static uint32_t bge_tx_count_intr = 0; 105 106 /* 107 * Memory pool configuration parameters. 108 * 109 * These are generally specific to each member of the chip family, since 110 * each one may have a different memory size/configuration. 111 * 112 * Setting the mbuf pool length for a specific type of chip to 0 inhibits 113 * the driver from programming the various registers; instead they are left 114 * at their hardware defaults. This is the preferred option for later chips 115 * (5705+), whereas the older chips *required* these registers to be set, 116 * since the h/w default was 0 ;-( 117 */ 118 static uint32_t bge_mbuf_pool_base = MBUF_POOL_BASE_DEFAULT; 119 static uint32_t bge_mbuf_pool_base_5704 = MBUF_POOL_BASE_5704; 120 static uint32_t bge_mbuf_pool_base_5705 = MBUF_POOL_BASE_5705; 121 static uint32_t bge_mbuf_pool_base_5721 = MBUF_POOL_BASE_5721; 122 static uint32_t bge_mbuf_pool_len = MBUF_POOL_LENGTH_DEFAULT; 123 static uint32_t bge_mbuf_pool_len_5704 = MBUF_POOL_LENGTH_5704; 124 static uint32_t bge_mbuf_pool_len_5705 = 0; /* use h/w default */ 125 static uint32_t bge_mbuf_pool_len_5721 = 0; 126 127 /* 128 * Various high and low water marks, thresholds, etc ... 129 * 130 * Note: these are taken from revision 7 of the PRM, and some are different 131 * from both the values in earlier PRMs *and* those determined experimentally 132 * and used in earlier versions of this driver ... 133 */ 134 static uint32_t bge_mbuf_hi_water = MBUF_HIWAT_DEFAULT; 135 static uint32_t bge_mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_DEFAULT; 136 static uint32_t bge_mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_DEFAULT; 137 138 static uint32_t bge_dmad_lo_water = DMAD_POOL_LOWAT_DEFAULT; 139 static uint32_t bge_dmad_hi_water = DMAD_POOL_HIWAT_DEFAULT; 140 static uint32_t bge_lowat_recv_frames = LOWAT_MAX_RECV_FRAMES_DEFAULT; 141 142 static uint32_t bge_replenish_std = STD_RCV_BD_REPLENISH_DEFAULT; 143 static uint32_t bge_replenish_mini = MINI_RCV_BD_REPLENISH_DEFAULT; 144 static uint32_t bge_replenish_jumbo = JUMBO_RCV_BD_REPLENISH_DEFAULT; 145 146 static uint32_t bge_watchdog_count = 1 << 16; 147 static uint16_t bge_dma_miss_limit = 20; 148 149 static uint32_t bge_stop_start_on_sync = 0; 150 151 /* 152 * bge_intr_max_loop controls the maximum loop number within bge_intr. 153 * When loading NIC with heavy network traffic, it is useful. 154 * Increasing this value could have positive effect to throughput, 155 * but it might also increase ticks of a bge ISR stick on CPU, which might 156 * lead to bad UI interactive experience. So tune this with caution. 157 */ 158 static int bge_intr_max_loop = 1; 159 160 /* 161 * ========== Low-level chip & ring buffer manipulation ========== 162 */ 163 164 #define BGE_DBG BGE_DBG_REGS /* debug flag for this code */ 165 166 167 /* 168 * Config space read-modify-write routines 169 */ 170 171 #if BGE_CFG_IO8 172 173 static void bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits); 174 #pragma inline(bge_cfg_clr16) 175 176 static void 177 bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits) 178 { 179 uint16_t regval; 180 181 BGE_TRACE(("bge_cfg_clr16($%p, 0x%lx, 0x%x)", 182 (void *)bgep, regno, bits)); 183 184 regval = pci_config_get16(bgep->cfg_handle, regno); 185 186 BGE_DEBUG(("bge_cfg_clr16($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 187 (void *)bgep, regno, bits, regval, regval & ~bits)); 188 189 regval &= ~bits; 190 pci_config_put16(bgep->cfg_handle, regno, regval); 191 } 192 193 #endif /* BGE_CFG_IO8 */ 194 195 static void bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 196 #pragma inline(bge_cfg_clr32) 197 198 static void 199 bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 200 { 201 uint32_t regval; 202 203 BGE_TRACE(("bge_cfg_clr32($%p, 0x%lx, 0x%x)", 204 (void *)bgep, regno, bits)); 205 206 regval = pci_config_get32(bgep->cfg_handle, regno); 207 208 BGE_DEBUG(("bge_cfg_clr32($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 209 (void *)bgep, regno, bits, regval, regval & ~bits)); 210 211 regval &= ~bits; 212 pci_config_put32(bgep->cfg_handle, regno, regval); 213 } 214 215 #if BGE_IND_IO32 216 217 /* 218 * Indirect access to registers & RISC scratchpads, using config space 219 * accesses only. 220 * 221 * This isn't currently used, but someday we might want to use it for 222 * restoring the Subsystem Device/Vendor registers (which aren't directly 223 * writable in Config Space), or for downloading firmware into the RISCs 224 * 225 * In any case there are endian issues to be resolved before this code is 226 * enabled; the bizarre way that bytes get twisted by this chip AND by 227 * the PCI bridge in SPARC systems mean that we shouldn't enable it until 228 * it's been thoroughly tested for all access sizes on all supported 229 * architectures (SPARC *and* x86!). 230 */ 231 uint32_t bge_ind_get32(bge_t *bgep, bge_regno_t regno); 232 #pragma inline(bge_ind_get32) 233 234 uint32_t 235 bge_ind_get32(bge_t *bgep, bge_regno_t regno) 236 { 237 uint32_t val; 238 239 BGE_TRACE(("bge_ind_get32($%p, 0x%lx)", (void *)bgep, regno)); 240 241 #ifdef __sparc 242 if (DEVICE_5717_SERIES_CHIPSETS(bgep)) 243 regno = LE_32(regno); 244 #endif 245 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 246 val = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_RIADR); 247 248 BGE_DEBUG(("bge_ind_get32($%p, 0x%lx) => 0x%x", 249 (void *)bgep, regno, val)); 250 251 val = LE_32(val); 252 253 return (val); 254 } 255 256 void bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val); 257 #pragma inline(bge_ind_put32) 258 259 void 260 bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val) 261 { 262 BGE_TRACE(("bge_ind_put32($%p, 0x%lx, 0x%x)", 263 (void *)bgep, regno, val)); 264 265 val = LE_32(val); 266 #ifdef __sparc 267 if (DEVICE_5717_SERIES_CHIPSETS(bgep)) 268 regno = LE_32(regno); 269 #endif 270 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 271 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIADR, val); 272 } 273 274 #endif /* BGE_IND_IO32 */ 275 276 #if BGE_DEBUGGING 277 278 static void bge_pci_check(bge_t *bgep); 279 #pragma no_inline(bge_pci_check) 280 281 static void 282 bge_pci_check(bge_t *bgep) 283 { 284 uint16_t pcistatus; 285 286 pcistatus = pci_config_get16(bgep->cfg_handle, PCI_CONF_STAT); 287 if ((pcistatus & (PCI_STAT_R_MAST_AB | PCI_STAT_R_TARG_AB)) != 0) 288 BGE_DEBUG(("bge_pci_check($%p): PCI status 0x%x", 289 (void *)bgep, pcistatus)); 290 } 291 292 #endif /* BGE_DEBUGGING */ 293 294 /* 295 * Perform first-stage chip (re-)initialisation, using only config-space 296 * accesses: 297 * 298 * + Read the vendor/device/revision/subsystem/cache-line-size registers, 299 * returning the data in the structure pointed to by <idp>. 300 * + Configure the target-mode endianness (swap) options. 301 * + Disable interrupts and enable Memory Space accesses. 302 * + Enable or disable Bus Mastering according to the <enable_dma> flag. 303 * 304 * This sequence is adapted from Broadcom document 570X-PG102-R, 305 * page 102, steps 1-3, 6-8 and 11-13. The omitted parts of the sequence 306 * are 4 and 5 (Reset Core and wait) which are handled elsewhere. 307 * 308 * This function MUST be called before any non-config-space accesses 309 * are made; on this first call <enable_dma> is B_FALSE, and it 310 * effectively performs steps 3-1(!) of the initialisation sequence 311 * (the rest are not required but should be harmless). 312 * 313 * It MUST also be called after a chip reset, as this disables 314 * Memory Space cycles! In this case, <enable_dma> is B_TRUE, and 315 * it is effectively performing steps 6-8. 316 */ 317 void bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma); 318 #pragma no_inline(bge_chip_cfg_init) 319 320 void 321 bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma) 322 { 323 ddi_acc_handle_t handle; 324 uint16_t command; 325 uint32_t mhcr; 326 uint16_t value16; 327 int i; 328 329 BGE_TRACE(("bge_chip_cfg_init($%p, $%p, %d)", 330 (void *)bgep, (void *)cidp, enable_dma)); 331 332 /* 333 * Step 3: save PCI cache line size and subsystem vendor ID 334 * 335 * Read all the config-space registers that characterise the 336 * chip, specifically vendor/device/revision/subsystem vendor 337 * and subsystem device id. We expect (but don't check) that 338 * (vendor == VENDOR_ID_BROADCOM) && (device == DEVICE_ID_5704) 339 * 340 * Also save all bus-transaction related registers (cache-line 341 * size, bus-grant/latency parameters, etc). Some of these are 342 * cleared by reset, so we'll have to restore them later. This 343 * comes from the Broadcom document 570X-PG102-R ... 344 * 345 * Note: Broadcom document 570X-PG102-R seems to be in error 346 * here w.r.t. the offsets of the Subsystem Vendor ID and 347 * Subsystem (Device) ID registers, which are the opposite way 348 * round according to the PCI standard. For good measure, we 349 * save/restore both anyway. 350 */ 351 handle = bgep->cfg_handle; 352 353 /* 354 * For some chipsets (e.g., BCM5718), if MHCR_ENABLE_ENDIAN_BYTE_SWAP 355 * has been set in PCI_CONF_COMM already, we need to write the 356 * byte-swapped value to it. So we just write zero first for simplicity. 357 */ 358 cidp->device = pci_config_get16(handle, PCI_CONF_DEVID); 359 if (DEVICE_5717_SERIES_CHIPSETS(bgep)) 360 pci_config_put32(handle, PCI_CONF_BGE_MHCR, 0); 361 mhcr = pci_config_get32(handle, PCI_CONF_BGE_MHCR); 362 cidp->asic_rev = mhcr & MHCR_CHIP_REV_MASK; 363 cidp->businfo = pci_config_get32(handle, PCI_CONF_BGE_PCISTATE); 364 cidp->command = pci_config_get16(handle, PCI_CONF_COMM); 365 366 cidp->vendor = pci_config_get16(handle, PCI_CONF_VENID); 367 cidp->subven = pci_config_get16(handle, PCI_CONF_SUBVENID); 368 cidp->subdev = pci_config_get16(handle, PCI_CONF_SUBSYSID); 369 cidp->revision = pci_config_get8(handle, PCI_CONF_REVID); 370 cidp->clsize = pci_config_get8(handle, PCI_CONF_CACHE_LINESZ); 371 cidp->latency = pci_config_get8(handle, PCI_CONF_LATENCY_TIMER); 372 373 BGE_DEBUG(("bge_chip_cfg_init: %s bus is %s and %s; #INTA is %s", 374 cidp->businfo & PCISTATE_BUS_IS_PCI ? "PCI" : "PCI-X", 375 cidp->businfo & PCISTATE_BUS_IS_FAST ? "fast" : "slow", 376 cidp->businfo & PCISTATE_BUS_IS_32_BIT ? "narrow" : "wide", 377 cidp->businfo & PCISTATE_INTA_STATE ? "high" : "low")); 378 BGE_DEBUG(("bge_chip_cfg_init: vendor 0x%x device 0x%x revision 0x%x", 379 cidp->vendor, cidp->device, cidp->revision)); 380 BGE_DEBUG(("bge_chip_cfg_init: subven 0x%x subdev 0x%x asic_rev 0x%x", 381 cidp->subven, cidp->subdev, cidp->asic_rev)); 382 BGE_DEBUG(("bge_chip_cfg_init: clsize %d latency %d command 0x%x", 383 cidp->clsize, cidp->latency, cidp->command)); 384 385 /* 386 * Step 2 (also step 6): disable and clear interrupts. 387 * Steps 11-13: configure PIO endianness options, and enable 388 * indirect register access. We'll also select any other 389 * options controlled by the MHCR (e.g. tagged status, mask 390 * interrupt mode) at this stage ... 391 * 392 * Note: internally, the chip is 64-bit and BIG-endian, but 393 * since it talks to the host over a (LITTLE-endian) PCI bus, 394 * it normally swaps bytes around at the PCI interface. 395 * However, the PCI host bridge on SPARC systems normally 396 * swaps the byte lanes around too, since SPARCs are also 397 * BIG-endian. So it turns out that on SPARC, the right 398 * option is to tell the chip to swap (and the host bridge 399 * will swap back again), whereas on x86 we ask the chip 400 * NOT to swap, so the natural little-endianness of the 401 * PCI bus is assumed. Then the only thing that doesn't 402 * automatically work right is access to an 8-byte register 403 * by a little-endian host; but we don't want to set the 404 * MHCR_ENABLE_REGISTER_WORD_SWAP bit because then 4-byte 405 * accesses don't go where expected ;-( So we live with 406 * that, and perform word-swaps in software in the few cases 407 * where a chip register is defined as an 8-byte value -- 408 * see the code below for details ... 409 * 410 * Note: the meaning of the 'MASK_INTERRUPT_MODE' bit isn't 411 * very clear in the register description in the PRM, but 412 * Broadcom document 570X-PG104-R page 248 explains a little 413 * more (under "Broadcom Mask Mode"). The bit changes the way 414 * the MASK_PCI_INT_OUTPUT bit works: with MASK_INTERRUPT_MODE 415 * clear, the chip interprets MASK_PCI_INT_OUTPUT in the same 416 * way as the 5700 did, which isn't very convenient. Setting 417 * the MASK_INTERRUPT_MODE bit makes the MASK_PCI_INT_OUTPUT 418 * bit do just what its name says -- MASK the PCI #INTA output 419 * (i.e. deassert the signal at the pin) leaving all internal 420 * state unchanged. This is much more convenient for our 421 * interrupt handler, so we set MASK_INTERRUPT_MODE here. 422 * 423 * Note: the inconvenient semantics of the interrupt mailbox 424 * (nonzero disables and acknowledges/clears the interrupt, 425 * zero enables AND CLEARS it) would make race conditions 426 * likely in the interrupt handler: 427 * 428 * (1) acknowledge & disable interrupts 429 * (2) while (more to do) 430 * process packets 431 * (3) enable interrupts -- also clears pending 432 * 433 * If the chip received more packets and internally generated 434 * an interrupt between the check at (2) and the mbox write 435 * at (3), this interrupt would be lost :-( 436 * 437 * The best way to avoid this is to use TAGGED STATUS mode, 438 * where the chip includes a unique tag in each status block 439 * update, and the host, when re-enabling interrupts, passes 440 * the last tag it saw back to the chip; then the chip can 441 * see whether the host is truly up to date, and regenerate 442 * its interrupt if not. 443 */ 444 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 445 MHCR_ENABLE_TAGGED_STATUS_MODE | 446 MHCR_MASK_INTERRUPT_MODE | 447 MHCR_CLEAR_INTERRUPT_INTA; 448 449 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 450 mhcr |= MHCR_MASK_PCI_INT_OUTPUT; 451 452 #ifdef _BIG_ENDIAN 453 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 454 #endif /* _BIG_ENDIAN */ 455 456 if (DEVICE_5717_SERIES_CHIPSETS(bgep)) 457 pci_config_put32(handle, PCI_CONF_BGE_MHCR, 0); 458 pci_config_put32(handle, PCI_CONF_BGE_MHCR, mhcr); 459 460 #ifdef BGE_IPMI_ASF 461 bgep->asf_wordswapped = B_FALSE; 462 #endif 463 /* 464 * Step 1 (also step 7): Enable PCI Memory Space accesses 465 * Disable Memory Write/Invalidate 466 * Enable or disable Bus Mastering 467 * 468 * Note that all other bits are taken from the original value saved 469 * the first time through here, rather than from the current register 470 * value, 'cos that will have been cleared by a soft RESET since. 471 * In this way we preserve the OBP/nexus-parent's preferred settings 472 * of the parity-error and system-error enable bits across multiple 473 * chip RESETs. 474 */ 475 command = bgep->chipid.command | PCI_COMM_MAE; 476 command &= ~(PCI_COMM_ME|PCI_COMM_MEMWR_INVAL); 477 if (enable_dma) 478 command |= PCI_COMM_ME; 479 /* 480 * on BCM5714 revision A0, false parity error gets generated 481 * due to a logic bug. Provide a workaround by disabling parity 482 * error. 483 */ 484 if (((cidp->device == DEVICE_ID_5714C) || 485 (cidp->device == DEVICE_ID_5714S)) && 486 (cidp->revision == REVISION_ID_5714_A0)) { 487 command &= ~PCI_COMM_PARITY_DETECT; 488 } 489 pci_config_put16(handle, PCI_CONF_COMM, command); 490 491 /* 492 * On some PCI-E device, there were instances when 493 * the device was still link training. 494 */ 495 if (bgep->chipid.pci_type == BGE_PCI_E) { 496 i = 0; 497 value16 = pci_config_get16(handle, PCI_CONF_COMM); 498 while ((value16 != command) && (i < 100)) { 499 drv_usecwait(200); 500 value16 = pci_config_get16(handle, PCI_CONF_COMM); 501 ++i; 502 } 503 } 504 505 /* 506 * Clear any remaining error status bits 507 */ 508 pci_config_put16(handle, PCI_CONF_STAT, ~0); 509 510 /* 511 * Do following if and only if the device is NOT BCM5714C OR 512 * BCM5715C 513 */ 514 if (!((cidp->device == DEVICE_ID_5714C) || 515 (cidp->device == DEVICE_ID_5715C))) { 516 /* 517 * Make sure these indirect-access registers are sane 518 * rather than random after power-up or reset 519 */ 520 pci_config_put32(handle, PCI_CONF_BGE_RIAAR, 0); 521 pci_config_put32(handle, PCI_CONF_BGE_MWBAR, 0); 522 } 523 /* 524 * Step 8: Disable PCI-X/PCI-E Relaxed Ordering 525 */ 526 bge_cfg_clr16(bgep, PCIX_CONF_COMM, PCIX_COMM_RELAXED); 527 528 if (cidp->pci_type == BGE_PCI_E) { 529 if (DEVICE_5723_SERIES_CHIPSETS(bgep)) { 530 bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL_5723, 531 DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED); 532 } else 533 bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL, 534 DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED); 535 } 536 } 537 538 #ifdef __amd64 539 /* 540 * Distinguish CPU types 541 * 542 * These use to distinguish AMD64 or Intel EM64T of CPU running mode. 543 * If CPU runs on Intel EM64T mode,the 64bit operation cannot works fine 544 * for PCI-Express based network interface card. This is the work-around 545 * for those nics. 546 */ 547 static boolean_t bge_get_em64t_type(void); 548 #pragma inline(bge_get_em64t_type) 549 550 static boolean_t 551 bge_get_em64t_type(void) 552 { 553 554 return (x86_vendor == X86_VENDOR_Intel); 555 } 556 #endif 557 558 /* 559 * Operating register get/set access routines 560 */ 561 562 uint32_t bge_reg_get32(bge_t *bgep, bge_regno_t regno); 563 #pragma inline(bge_reg_get32) 564 565 uint32_t 566 bge_reg_get32(bge_t *bgep, bge_regno_t regno) 567 { 568 BGE_TRACE(("bge_reg_get32($%p, 0x%lx)", 569 (void *)bgep, regno)); 570 571 return (ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno))); 572 } 573 574 void bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data); 575 #pragma inline(bge_reg_put32) 576 577 void 578 bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data) 579 { 580 BGE_TRACE(("bge_reg_put32($%p, 0x%lx, 0x%x)", 581 (void *)bgep, regno, data)); 582 583 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), data); 584 BGE_PCICHK(bgep); 585 } 586 587 void bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 588 #pragma inline(bge_reg_set32) 589 590 void 591 bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 592 { 593 uint32_t regval; 594 595 BGE_TRACE(("bge_reg_set32($%p, 0x%lx, 0x%x)", 596 (void *)bgep, regno, bits)); 597 598 regval = bge_reg_get32(bgep, regno); 599 regval |= bits; 600 bge_reg_put32(bgep, regno, regval); 601 } 602 603 void bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 604 #pragma inline(bge_reg_clr32) 605 606 void 607 bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 608 { 609 uint32_t regval; 610 611 BGE_TRACE(("bge_reg_clr32($%p, 0x%lx, 0x%x)", 612 (void *)bgep, regno, bits)); 613 614 regval = bge_reg_get32(bgep, regno); 615 regval &= ~bits; 616 bge_reg_put32(bgep, regno, regval); 617 } 618 619 static uint64_t bge_reg_get64(bge_t *bgep, bge_regno_t regno); 620 #pragma inline(bge_reg_get64) 621 622 static uint64_t 623 bge_reg_get64(bge_t *bgep, bge_regno_t regno) 624 { 625 uint64_t regval; 626 627 #ifdef __amd64 628 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type() || 629 DEVICE_5717_SERIES_CHIPSETS(bgep)) { 630 regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4)); 631 regval <<= 32; 632 regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 633 } else { 634 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 635 } 636 #elif defined(__sparc) 637 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || 638 DEVICE_5717_SERIES_CHIPSETS(bgep)) { 639 regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 640 regval <<= 32; 641 regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4)); 642 } else { 643 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 644 } 645 #else 646 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 647 #endif 648 649 #ifdef _LITTLE_ENDIAN 650 regval = (regval >> 32) | (regval << 32); 651 #endif /* _LITTLE_ENDIAN */ 652 653 BGE_TRACE(("bge_reg_get64($%p, 0x%lx) = 0x%016llx", 654 (void *)bgep, regno, regval)); 655 656 return (regval); 657 } 658 659 static void bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data); 660 #pragma inline(bge_reg_put64) 661 662 static void 663 bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data) 664 { 665 BGE_TRACE(("bge_reg_put64($%p, 0x%lx, 0x%016llx)", 666 (void *)bgep, regno, data)); 667 668 #ifdef _LITTLE_ENDIAN 669 data = ((data >> 32) | (data << 32)); 670 #endif /* _LITTLE_ENDIAN */ 671 672 #ifdef __amd64 673 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type() || 674 DEVICE_5717_SERIES_CHIPSETS(bgep)) { 675 ddi_put32(bgep->io_handle, 676 PIO_ADDR(bgep, regno), (uint32_t)data); 677 BGE_PCICHK(bgep); 678 ddi_put32(bgep->io_handle, 679 PIO_ADDR(bgep, regno + 4), (uint32_t)(data >> 32)); 680 681 } else { 682 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 683 } 684 #elif defined(__sparc) 685 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || 686 DEVICE_5717_SERIES_CHIPSETS(bgep)) { 687 ddi_put32(bgep->io_handle, 688 PIO_ADDR(bgep, regno + 4), (uint32_t)data); 689 BGE_PCICHK(bgep); 690 ddi_put32(bgep->io_handle, 691 PIO_ADDR(bgep, regno), (uint32_t)(data >> 32)); 692 } else { 693 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 694 } 695 #else 696 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 697 #endif 698 699 BGE_PCICHK(bgep); 700 } 701 702 /* 703 * The DDI doesn't provide get/put functions for 128 bit data 704 * so we put RCBs out as two 64-bit chunks instead. 705 */ 706 static void bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 707 #pragma inline(bge_reg_putrcb) 708 709 static void 710 bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 711 { 712 uint64_t *p; 713 714 BGE_TRACE(("bge_reg_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 715 (void *)bgep, addr, rcbp->host_ring_addr, 716 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 717 718 ASSERT((addr % sizeof (*rcbp)) == 0); 719 720 p = (void *)rcbp; 721 bge_reg_put64(bgep, addr, *p++); 722 bge_reg_put64(bgep, addr+8, *p); 723 } 724 725 void bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data); 726 #pragma inline(bge_mbx_put) 727 728 void 729 bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data) 730 { 731 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) 732 regno += INTERRUPT_LP_MBOX_0_REG - INTERRUPT_MBOX_0_REG + 4; 733 734 BGE_TRACE(("bge_mbx_put($%p, 0x%lx, 0x%016llx)", 735 (void *)bgep, regno, data)); 736 737 /* 738 * Mailbox registers are nominally 64 bits on the 5701, but 739 * the MSW isn't used. On the 5703, they're only 32 bits 740 * anyway. So here we just write the lower(!) 32 bits - 741 * remembering that the chip is big-endian, even though the 742 * PCI bus is little-endian ... 743 */ 744 #ifdef _BIG_ENDIAN 745 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno+4), (uint32_t)data); 746 #else 747 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), (uint32_t)data); 748 #endif /* _BIG_ENDIAN */ 749 BGE_PCICHK(bgep); 750 } 751 752 uint32_t bge_mbx_get(bge_t *bgep, bge_regno_t regno); 753 #pragma inline(bge_mbx_get) 754 755 uint32_t 756 bge_mbx_get(bge_t *bgep, bge_regno_t regno) 757 { 758 uint32_t val32; 759 760 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) 761 regno += INTERRUPT_LP_MBOX_0_REG - INTERRUPT_MBOX_0_REG + 4; 762 763 BGE_TRACE(("bge_mbx_get($%p, 0x%lx)", 764 (void *)bgep, regno)); 765 766 #ifdef _BIG_ENDIAN 767 val32 = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno+4)); 768 #else 769 val32 = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 770 #endif /* _BIG_ENDIAN */ 771 BGE_PCICHK(bgep); 772 773 BGE_DEBUG(("bge_mbx_get($%p, 0x%lx) => 0x%08x", 774 (void *)bgep, regno, val32)); 775 776 return (val32); 777 } 778 779 780 #if BGE_DEBUGGING 781 782 void bge_led_mark(bge_t *bgep); 783 #pragma no_inline(bge_led_mark) 784 785 void 786 bge_led_mark(bge_t *bgep) 787 { 788 uint32_t led_ctrl = LED_CONTROL_OVERRIDE_LINK | 789 LED_CONTROL_1000MBPS_LED | 790 LED_CONTROL_100MBPS_LED | 791 LED_CONTROL_10MBPS_LED; 792 793 /* 794 * Blink all three LINK LEDs on simultaneously, then all off, 795 * then restore to automatic hardware control. This is used 796 * in laboratory testing to trigger a logic analyser or scope. 797 */ 798 bge_reg_set32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 799 led_ctrl ^= LED_CONTROL_OVERRIDE_LINK; 800 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 801 led_ctrl = LED_CONTROL_OVERRIDE_LINK; 802 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 803 } 804 805 #endif /* BGE_DEBUGGING */ 806 807 /* 808 * NIC on-chip memory access routines 809 * 810 * Only 32K of NIC memory is visible at a time, controlled by the 811 * Memory Window Base Address Register (in PCI config space). Once 812 * this is set, the 32K region of NIC-local memory that it refers 813 * to can be directly addressed in the upper 32K of the 64K of PCI 814 * memory space used for the device. 815 */ 816 817 static void bge_nic_setwin(bge_t *bgep, bge_regno_t base); 818 #pragma inline(bge_nic_setwin) 819 820 static void 821 bge_nic_setwin(bge_t *bgep, bge_regno_t base) 822 { 823 chip_id_t *cidp; 824 825 BGE_TRACE(("bge_nic_setwin($%p, 0x%lx)", 826 (void *)bgep, base)); 827 828 ASSERT((base & MWBAR_GRANULE_MASK) == 0); 829 830 /* 831 * Don't do repeated zero data writes, 832 * if the device is BCM5714C/15C. 833 */ 834 cidp = &bgep->chipid; 835 if ((cidp->device == DEVICE_ID_5714C) || 836 (cidp->device == DEVICE_ID_5715C)) { 837 if (bgep->lastWriteZeroData && (base == (bge_regno_t)0)) 838 return; 839 /* Adjust lastWriteZeroData */ 840 bgep->lastWriteZeroData = ((base == (bge_regno_t)0) ? 841 B_TRUE : B_FALSE); 842 } 843 #ifdef __sparc 844 if (DEVICE_5717_SERIES_CHIPSETS(bgep)) 845 base = LE_32(base); 846 #endif 847 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, base); 848 } 849 850 static uint32_t bge_nic_get32(bge_t *bgep, bge_regno_t addr); 851 #pragma inline(bge_nic_get32) 852 853 static uint32_t 854 bge_nic_get32(bge_t *bgep, bge_regno_t addr) 855 { 856 uint32_t data; 857 858 #if defined(BGE_IPMI_ASF) && !defined(__sparc) 859 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 860 /* workaround for word swap error */ 861 if (addr & 4) 862 addr = addr - 4; 863 else 864 addr = addr + 4; 865 } 866 #endif 867 868 #ifdef __sparc 869 data = bge_nic_read32(bgep, addr); 870 #else 871 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 872 addr &= MWBAR_GRANULE_MASK; 873 addr += NIC_MEM_WINDOW_OFFSET; 874 875 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 876 #endif 877 878 BGE_TRACE(("bge_nic_get32($%p, 0x%lx) = 0x%08x", 879 (void *)bgep, addr, data)); 880 881 return (data); 882 } 883 884 void bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data); 885 #pragma inline(bge_nic_put32) 886 887 void 888 bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data) 889 { 890 BGE_TRACE(("bge_nic_put32($%p, 0x%lx, 0x%08x)", 891 (void *)bgep, addr, data)); 892 893 #if defined(BGE_IPMI_ASF) && !defined(__sparc) 894 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 895 /* workaround for word swap error */ 896 if (addr & 4) 897 addr = addr - 4; 898 else 899 addr = addr + 4; 900 } 901 #endif 902 903 #ifdef __sparc 904 if (DEVICE_5717_SERIES_CHIPSETS(bgep)) 905 addr = LE_32(addr); 906 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr); 907 data = LE_32(data); 908 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR, data); 909 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0); 910 #else 911 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 912 addr &= MWBAR_GRANULE_MASK; 913 addr += NIC_MEM_WINDOW_OFFSET; 914 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), data); 915 BGE_PCICHK(bgep); 916 #endif 917 } 918 919 static uint64_t bge_nic_get64(bge_t *bgep, bge_regno_t addr); 920 #pragma inline(bge_nic_get64) 921 922 static uint64_t 923 bge_nic_get64(bge_t *bgep, bge_regno_t addr) 924 { 925 uint64_t data; 926 927 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 928 addr &= MWBAR_GRANULE_MASK; 929 addr += NIC_MEM_WINDOW_OFFSET; 930 931 #ifdef __amd64 932 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type() || 933 DEVICE_5717_SERIES_CHIPSETS(bgep)) { 934 data = ddi_get32(bgep->io_handle, 935 PIO_ADDR(bgep, addr + 4)); 936 data <<= 32; 937 data |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 938 } else { 939 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 940 } 941 #elif defined(__sparc) 942 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || 943 DEVICE_5717_SERIES_CHIPSETS(bgep)) { 944 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 945 data <<= 32; 946 data |= ddi_get32(bgep->io_handle, 947 PIO_ADDR(bgep, addr + 4)); 948 } else { 949 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 950 } 951 #else 952 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 953 #endif 954 955 BGE_TRACE(("bge_nic_get64($%p, 0x%lx) = 0x%016llx", 956 (void *)bgep, addr, data)); 957 958 return (data); 959 } 960 961 static void bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data); 962 #pragma inline(bge_nic_put64) 963 964 static void 965 bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data) 966 { 967 BGE_TRACE(("bge_nic_put64($%p, 0x%lx, 0x%016llx)", 968 (void *)bgep, addr, data)); 969 970 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 971 addr &= MWBAR_GRANULE_MASK; 972 addr += NIC_MEM_WINDOW_OFFSET; 973 974 #ifdef __amd64 975 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type() || 976 DEVICE_5717_SERIES_CHIPSETS(bgep)) { 977 ddi_put32(bgep->io_handle, 978 PIO_ADDR(bgep, addr + 4), (uint32_t)data); 979 BGE_PCICHK(bgep); 980 ddi_put32(bgep->io_handle, 981 PIO_ADDR(bgep, addr), (uint32_t)(data >> 32)); 982 } else { 983 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 984 } 985 #elif defined(__sparc) 986 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || 987 DEVICE_5717_SERIES_CHIPSETS(bgep)) { 988 ddi_put32(bgep->io_handle, 989 PIO_ADDR(bgep, addr + 4), (uint32_t)data); 990 BGE_PCICHK(bgep); 991 ddi_put32(bgep->io_handle, 992 PIO_ADDR(bgep, addr), (uint32_t)(data >> 32)); 993 } else { 994 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 995 } 996 #else 997 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 998 #endif 999 1000 BGE_PCICHK(bgep); 1001 } 1002 1003 /* 1004 * The DDI doesn't provide get/put functions for 128 bit data 1005 * so we put RCBs out as two 64-bit chunks instead. 1006 */ 1007 static void bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 1008 #pragma inline(bge_nic_putrcb) 1009 1010 static void 1011 bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 1012 { 1013 uint64_t *p; 1014 1015 BGE_TRACE(("bge_nic_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 1016 (void *)bgep, addr, rcbp->host_ring_addr, 1017 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 1018 1019 ASSERT((addr % sizeof (*rcbp)) == 0); 1020 1021 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 1022 addr &= MWBAR_GRANULE_MASK; 1023 addr += NIC_MEM_WINDOW_OFFSET; 1024 1025 p = (void *)rcbp; 1026 #ifdef __amd64 1027 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type() || 1028 DEVICE_5717_SERIES_CHIPSETS(bgep)) { 1029 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), 1030 (uint32_t)(*p)); 1031 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4), 1032 (uint32_t)(*p++ >> 32)); 1033 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8), 1034 (uint32_t)(*p)); 1035 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12), 1036 (uint32_t)(*p >> 32)); 1037 1038 } else { 1039 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 1040 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr+8), *p); 1041 } 1042 #elif defined(__sparc) 1043 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || 1044 DEVICE_5717_SERIES_CHIPSETS(bgep)) { 1045 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4), 1046 (uint32_t)(*p)); 1047 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), 1048 (uint32_t)(*p++ >> 32)); 1049 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12), 1050 (uint32_t)(*p)); 1051 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8), 1052 (uint32_t)(*p >> 32)); 1053 } else { 1054 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 1055 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p); 1056 } 1057 #else 1058 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 1059 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p); 1060 #endif 1061 1062 BGE_PCICHK(bgep); 1063 } 1064 1065 static void bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes); 1066 #pragma inline(bge_nic_zero) 1067 1068 static void 1069 bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes) 1070 { 1071 BGE_TRACE(("bge_nic_zero($%p, 0x%lx, 0x%x)", 1072 (void *)bgep, addr, nbytes)); 1073 1074 ASSERT((addr & ~MWBAR_GRANULE_MASK) == 1075 ((addr+nbytes) & ~MWBAR_GRANULE_MASK)); 1076 1077 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 1078 addr &= MWBAR_GRANULE_MASK; 1079 addr += NIC_MEM_WINDOW_OFFSET; 1080 1081 (void) ddi_device_zero(bgep->io_handle, PIO_ADDR(bgep, addr), 1082 nbytes, 1, DDI_DATA_SZ08_ACC); 1083 BGE_PCICHK(bgep); 1084 } 1085 1086 /* 1087 * MII (PHY) register get/set access routines 1088 * 1089 * These use the chip's MII auto-access method, controlled by the 1090 * MII Communication register at 0x044c, so the CPU doesn't have 1091 * to fiddle with the individual bits. 1092 */ 1093 1094 #undef BGE_DBG 1095 #define BGE_DBG BGE_DBG_MII /* debug flag for this code */ 1096 1097 static uint16_t bge_mii_access(bge_t *bgep, bge_regno_t regno, 1098 uint16_t data, uint32_t cmd); 1099 #pragma no_inline(bge_mii_access) 1100 1101 static uint16_t 1102 bge_mii_access(bge_t *bgep, bge_regno_t regno, uint16_t data, uint32_t cmd) 1103 { 1104 uint32_t timeout; 1105 uint32_t regval1; 1106 uint32_t regval2; 1107 1108 BGE_TRACE(("bge_mii_access($%p, 0x%lx, 0x%x, 0x%x)", 1109 (void *)bgep, regno, data, cmd)); 1110 1111 ASSERT(mutex_owned(bgep->genlock)); 1112 1113 /* 1114 * Assemble the command ... 1115 */ 1116 cmd |= data << MI_COMMS_DATA_SHIFT; 1117 cmd |= regno << MI_COMMS_REGISTER_SHIFT; 1118 cmd |= bgep->phy_mii_addr << MI_COMMS_ADDRESS_SHIFT; 1119 cmd |= MI_COMMS_START; 1120 1121 /* 1122 * Wait for any command already in progress ... 1123 * 1124 * Note: this *shouldn't* ever find that there is a command 1125 * in progress, because we already hold the <genlock> mutex. 1126 * Nonetheless, we have sometimes seen the MI_COMMS_START 1127 * bit set here -- it seems that the chip can initiate MII 1128 * accesses internally, even with polling OFF. 1129 */ 1130 regval1 = regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1131 for (timeout = 100; ; ) { 1132 if ((regval2 & MI_COMMS_START) == 0) { 1133 bge_reg_put32(bgep, MI_COMMS_REG, cmd); 1134 break; 1135 } 1136 if (--timeout == 0) 1137 break; 1138 drv_usecwait(10); 1139 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1140 } 1141 1142 if (timeout == 0) 1143 return ((uint16_t)~0u); 1144 1145 if (timeout != 100) 1146 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1147 "MI_COMMS_START set for %d us; 0x%x->0x%x", 1148 cmd, 10*(100-timeout), regval1, regval2)); 1149 1150 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1151 for (timeout = 1000; ; ) { 1152 if ((regval1 & MI_COMMS_START) == 0) 1153 break; 1154 if (--timeout == 0) 1155 break; 1156 drv_usecwait(10); 1157 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1158 } 1159 1160 /* 1161 * Drop out early if the READ FAILED bit is set -- this chip 1162 * could be a 5703/4S, with a SerDes instead of a PHY! 1163 */ 1164 if (regval2 & MI_COMMS_READ_FAILED) 1165 return ((uint16_t)~0u); 1166 1167 if (timeout == 0) 1168 return ((uint16_t)~0u); 1169 1170 /* 1171 * The PRM says to wait 5us after seeing the START bit clear 1172 * and then re-read the register to get the final value of the 1173 * data field, in order to avoid a race condition where the 1174 * START bit is clear but the data field isn't yet valid. 1175 * 1176 * Note: we don't actually seem to be encounter this race; 1177 * except when the START bit is seen set again (see below), 1178 * the data field doesn't change during this 5us interval. 1179 */ 1180 drv_usecwait(5); 1181 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1182 1183 /* 1184 * Unfortunately, when following the PRMs instructions above, 1185 * we have occasionally seen the START bit set again(!) in the 1186 * value read after the 5us delay. This seems to be due to the 1187 * chip autonomously starting another MII access internally. 1188 * In such cases, the command/data/etc fields relate to the 1189 * internal command, rather than the one that we thought had 1190 * just finished. So in this case, we fall back to returning 1191 * the data from the original read that showed START clear. 1192 */ 1193 if (regval2 & MI_COMMS_START) { 1194 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1195 "MI_COMMS_START set after transaction; 0x%x->0x%x", 1196 cmd, regval1, regval2)); 1197 regval2 = regval1; 1198 } 1199 1200 if (regval2 & MI_COMMS_START) 1201 return ((uint16_t)~0u); 1202 1203 if (regval2 & MI_COMMS_READ_FAILED) 1204 return ((uint16_t)~0u); 1205 1206 return ((regval2 & MI_COMMS_DATA_MASK) >> MI_COMMS_DATA_SHIFT); 1207 } 1208 1209 uint16_t bge_mii_get16(bge_t *bgep, bge_regno_t regno); 1210 #pragma no_inline(bge_mii_get16) 1211 1212 uint16_t 1213 bge_mii_get16(bge_t *bgep, bge_regno_t regno) 1214 { 1215 BGE_TRACE(("bge_mii_get16($%p, 0x%lx)", 1216 (void *)bgep, regno)); 1217 1218 ASSERT(mutex_owned(bgep->genlock)); 1219 1220 if (DEVICE_5906_SERIES_CHIPSETS(bgep) && ((regno == MII_AUX_CONTROL) || 1221 (regno == MII_MSCONTROL))) 1222 return (0); 1223 1224 return (bge_mii_access(bgep, regno, 0, MI_COMMS_COMMAND_READ)); 1225 } 1226 1227 void bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data); 1228 #pragma no_inline(bge_mii_put16) 1229 1230 void 1231 bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data) 1232 { 1233 BGE_TRACE(("bge_mii_put16($%p, 0x%lx, 0x%x)", 1234 (void *)bgep, regno, data)); 1235 1236 ASSERT(mutex_owned(bgep->genlock)); 1237 1238 if (DEVICE_5906_SERIES_CHIPSETS(bgep) && ((regno == MII_AUX_CONTROL) || 1239 (regno == MII_MSCONTROL))) 1240 return; 1241 1242 (void) bge_mii_access(bgep, regno, data, MI_COMMS_COMMAND_WRITE); 1243 } 1244 1245 #undef BGE_DBG 1246 #define BGE_DBG BGE_DBG_SEEPROM /* debug flag for this code */ 1247 1248 #if BGE_SEE_IO32 || BGE_FLASH_IO32 1249 1250 /* 1251 * Basic SEEPROM get/set access routine 1252 * 1253 * This uses the chip's SEEPROM auto-access method, controlled by the 1254 * Serial EEPROM Address/Data Registers at 0x6838/683c, so the CPU 1255 * doesn't have to fiddle with the individual bits. 1256 * 1257 * The caller should hold <genlock> and *also* have already acquired 1258 * the right to access the SEEPROM, via bge_nvmem_acquire() above. 1259 * 1260 * Return value: 1261 * 0 on success, 1262 * ENODATA on access timeout (maybe retryable: device may just be busy) 1263 * EPROTO on other h/w or s/w errors. 1264 * 1265 * <*dp> is an input to a SEEPROM_ACCESS_WRITE operation, or an output 1266 * from a (successful) SEEPROM_ACCESS_READ. 1267 */ 1268 static int bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1269 uint32_t *dp); 1270 #pragma no_inline(bge_seeprom_access) 1271 1272 static int 1273 bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1274 { 1275 uint32_t tries; 1276 uint32_t regval; 1277 1278 ASSERT(mutex_owned(bgep->genlock)); 1279 1280 /* 1281 * On the newer chips that support both SEEPROM & Flash, we need 1282 * to specifically enable SEEPROM access (Flash is the default). 1283 * On older chips, we don't; SEEPROM is the only NVtype supported, 1284 * and the NVM control registers don't exist ... 1285 */ 1286 switch (bgep->chipid.nvtype) { 1287 case BGE_NVTYPE_NONE: 1288 case BGE_NVTYPE_UNKNOWN: 1289 _NOTE(NOTREACHED) 1290 case BGE_NVTYPE_SEEPROM: 1291 break; 1292 1293 case BGE_NVTYPE_LEGACY_SEEPROM: 1294 case BGE_NVTYPE_UNBUFFERED_FLASH: 1295 case BGE_NVTYPE_BUFFERED_FLASH: 1296 default: 1297 bge_reg_set32(bgep, NVM_CONFIG1_REG, 1298 NVM_CFG1_LEGACY_SEEPROM_MODE); 1299 break; 1300 } 1301 1302 /* 1303 * Check there's no command in progress. 1304 * 1305 * Note: this *shouldn't* ever find that there is a command 1306 * in progress, because we already hold the <genlock> mutex. 1307 * Also, to ensure we don't have a conflict with the chip's 1308 * internal firmware or a process accessing the same (shared) 1309 * SEEPROM through the other port of a 5704, we've already 1310 * been through the "software arbitration" protocol. 1311 * So this is just a final consistency check: we shouldn't 1312 * see EITHER the START bit (command started but not complete) 1313 * OR the COMPLETE bit (command completed but not cleared). 1314 */ 1315 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1316 if (regval & SEEPROM_ACCESS_START) 1317 return (EPROTO); 1318 if (regval & SEEPROM_ACCESS_COMPLETE) 1319 return (EPROTO); 1320 1321 /* 1322 * Assemble the command ... 1323 */ 1324 cmd |= addr & SEEPROM_ACCESS_ADDRESS_MASK; 1325 addr >>= SEEPROM_ACCESS_ADDRESS_SIZE; 1326 addr <<= SEEPROM_ACCESS_DEVID_SHIFT; 1327 cmd |= addr & SEEPROM_ACCESS_DEVID_MASK; 1328 cmd |= SEEPROM_ACCESS_START; 1329 cmd |= SEEPROM_ACCESS_COMPLETE; 1330 cmd |= regval & SEEPROM_ACCESS_HALFCLOCK_MASK; 1331 1332 bge_reg_put32(bgep, SERIAL_EEPROM_DATA_REG, *dp); 1333 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, cmd); 1334 1335 /* 1336 * By observation, a successful access takes ~20us on a 5703/4, 1337 * but apparently much longer (up to 1000us) on the obsolescent 1338 * BCM5700/BCM5701. We want to be sure we don't get any false 1339 * timeouts here; but OTOH, we don't want a bogus access to lock 1340 * out interrupts for longer than necessary. So we'll allow up 1341 * to 1000us ... 1342 */ 1343 for (tries = 0; tries < 1000; ++tries) { 1344 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1345 if (regval & SEEPROM_ACCESS_COMPLETE) 1346 break; 1347 drv_usecwait(1); 1348 } 1349 1350 if (regval & SEEPROM_ACCESS_COMPLETE) { 1351 /* 1352 * All OK; read the SEEPROM data register, then write back 1353 * the value read from the address register in order to 1354 * clear the <complete> bit and leave the SEEPROM access 1355 * state machine idle, ready for the next access ... 1356 */ 1357 BGE_DEBUG(("bge_seeprom_access: complete after %d us", tries)); 1358 *dp = bge_reg_get32(bgep, SERIAL_EEPROM_DATA_REG); 1359 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, regval); 1360 return (0); 1361 } 1362 1363 /* 1364 * Hmm ... what happened here? 1365 * 1366 * Most likely, the user addressed a non-existent SEEPROM. Or 1367 * maybe the SEEPROM was busy internally (e.g. processing a write) 1368 * and didn't respond to being addressed. Either way, it's left 1369 * the SEEPROM access state machine wedged. So we'll reset it 1370 * before we leave, so it's ready for next time ... 1371 */ 1372 BGE_DEBUG(("bge_seeprom_access: timed out after %d us", tries)); 1373 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 1374 return (ENODATA); 1375 } 1376 1377 /* 1378 * Basic Flash get/set access routine 1379 * 1380 * These use the chip's Flash auto-access method, controlled by the 1381 * Flash Access Registers at 0x7000-701c, so the CPU doesn't have to 1382 * fiddle with the individual bits. 1383 * 1384 * The caller should hold <genlock> and *also* have already acquired 1385 * the right to access the Flash, via bge_nvmem_acquire() above. 1386 * 1387 * Return value: 1388 * 0 on success, 1389 * ENODATA on access timeout (maybe retryable: device may just be busy) 1390 * ENODEV if the NVmem device is missing or otherwise unusable 1391 * 1392 * <*dp> is an input to a NVM_FLASH_CMD_WR operation, or an output 1393 * from a (successful) NVM_FLASH_CMD_RD. 1394 */ 1395 static int bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1396 uint32_t *dp); 1397 #pragma no_inline(bge_flash_access) 1398 1399 static int 1400 bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1401 { 1402 uint32_t tries; 1403 uint32_t regval; 1404 1405 ASSERT(mutex_owned(bgep->genlock)); 1406 1407 /* 1408 * On the newer chips that support both SEEPROM & Flash, we need 1409 * to specifically disable SEEPROM access while accessing Flash. 1410 * The older chips don't support Flash, and the NVM registers don't 1411 * exist, so we shouldn't be here at all! 1412 */ 1413 switch (bgep->chipid.nvtype) { 1414 case BGE_NVTYPE_NONE: 1415 case BGE_NVTYPE_UNKNOWN: 1416 _NOTE(NOTREACHED) 1417 case BGE_NVTYPE_SEEPROM: 1418 return (ENODEV); 1419 1420 case BGE_NVTYPE_LEGACY_SEEPROM: 1421 case BGE_NVTYPE_UNBUFFERED_FLASH: 1422 case BGE_NVTYPE_BUFFERED_FLASH: 1423 default: 1424 bge_reg_clr32(bgep, NVM_CONFIG1_REG, 1425 NVM_CFG1_LEGACY_SEEPROM_MODE); 1426 break; 1427 } 1428 1429 /* 1430 * Assemble the command ... 1431 */ 1432 addr &= NVM_FLASH_ADDR_MASK; 1433 cmd |= NVM_FLASH_CMD_DOIT; 1434 cmd |= NVM_FLASH_CMD_FIRST; 1435 cmd |= NVM_FLASH_CMD_LAST; 1436 cmd |= NVM_FLASH_CMD_DONE; 1437 1438 bge_reg_put32(bgep, NVM_FLASH_WRITE_REG, *dp); 1439 bge_reg_put32(bgep, NVM_FLASH_ADDR_REG, addr); 1440 bge_reg_put32(bgep, NVM_FLASH_CMD_REG, cmd); 1441 1442 /* 1443 * Allow up to 1000ms ... 1444 */ 1445 for (tries = 0; tries < 1000; ++tries) { 1446 regval = bge_reg_get32(bgep, NVM_FLASH_CMD_REG); 1447 if (regval & NVM_FLASH_CMD_DONE) 1448 break; 1449 drv_usecwait(1); 1450 } 1451 1452 if (regval & NVM_FLASH_CMD_DONE) { 1453 /* 1454 * All OK; read the data from the Flash read register 1455 */ 1456 BGE_DEBUG(("bge_flash_access: complete after %d us", tries)); 1457 *dp = bge_reg_get32(bgep, NVM_FLASH_READ_REG); 1458 return (0); 1459 } 1460 1461 /* 1462 * Hmm ... what happened here? 1463 * 1464 * Most likely, the user addressed a non-existent Flash. Or 1465 * maybe the Flash was busy internally (e.g. processing a write) 1466 * and didn't respond to being addressed. Either way, there's 1467 * nothing we can here ... 1468 */ 1469 BGE_DEBUG(("bge_flash_access: timed out after %d us", tries)); 1470 return (ENODATA); 1471 } 1472 1473 /* 1474 * The next two functions regulate access to the NVram (if fitted). 1475 * 1476 * On a 5704 (dual core) chip, there's only one SEEPROM and one Flash 1477 * (SPI) interface, but they can be accessed through either port. These 1478 * are managed by different instance of this driver and have no software 1479 * state in common. 1480 * 1481 * In addition (and even on a single core chip) the chip's internal 1482 * firmware can access the SEEPROM/Flash, most notably after a RESET 1483 * when it may download code to run internally. 1484 * 1485 * So we need to arbitrate between these various software agents. For 1486 * this purpose, the chip provides the Software Arbitration Register, 1487 * which implements hardware(!) arbitration. 1488 * 1489 * This functionality didn't exist on older (5700/5701) chips, so there's 1490 * nothing we can do by way of arbitration on those; also, if there's no 1491 * SEEPROM/Flash fitted (or we couldn't determine what type), there's also 1492 * nothing to do. 1493 * 1494 * The internal firmware appears to use Request 0, which is the highest 1495 * priority. So we'd like to use Request 2, leaving one higher and one 1496 * lower for any future developments ... but apparently this doesn't 1497 * always work. So for now, the code uses Request 1 ;-( 1498 */ 1499 1500 #define NVM_READ_REQ NVM_READ_REQ1 1501 #define NVM_RESET_REQ NVM_RESET_REQ1 1502 #define NVM_SET_REQ NVM_SET_REQ1 1503 1504 static void bge_nvmem_relinquish(bge_t *bgep); 1505 #pragma no_inline(bge_nvmem_relinquish) 1506 1507 static void 1508 bge_nvmem_relinquish(bge_t *bgep) 1509 { 1510 ASSERT(mutex_owned(bgep->genlock)); 1511 1512 switch (bgep->chipid.nvtype) { 1513 case BGE_NVTYPE_NONE: 1514 case BGE_NVTYPE_UNKNOWN: 1515 _NOTE(NOTREACHED) 1516 return; 1517 1518 case BGE_NVTYPE_SEEPROM: 1519 /* 1520 * No arbitration performed, no release needed 1521 */ 1522 return; 1523 1524 case BGE_NVTYPE_LEGACY_SEEPROM: 1525 case BGE_NVTYPE_UNBUFFERED_FLASH: 1526 case BGE_NVTYPE_BUFFERED_FLASH: 1527 default: 1528 break; 1529 } 1530 1531 /* 1532 * Our own request should be present (whether or not granted) ... 1533 */ 1534 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1535 1536 /* 1537 * ... this will make it go away. 1538 */ 1539 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_RESET_REQ); 1540 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1541 } 1542 1543 /* 1544 * Arbitrate for access to the NVmem, if necessary 1545 * 1546 * Return value: 1547 * 0 on success 1548 * EAGAIN if the device is in use (retryable) 1549 * ENODEV if the NVmem device is missing or otherwise unusable 1550 */ 1551 static int bge_nvmem_acquire(bge_t *bgep); 1552 #pragma no_inline(bge_nvmem_acquire) 1553 1554 static int 1555 bge_nvmem_acquire(bge_t *bgep) 1556 { 1557 uint32_t regval; 1558 uint32_t tries; 1559 1560 ASSERT(mutex_owned(bgep->genlock)); 1561 1562 switch (bgep->chipid.nvtype) { 1563 case BGE_NVTYPE_NONE: 1564 case BGE_NVTYPE_UNKNOWN: 1565 /* 1566 * Access denied: no (recognisable) device fitted 1567 */ 1568 return (ENODEV); 1569 1570 case BGE_NVTYPE_SEEPROM: 1571 /* 1572 * Access granted: no arbitration needed (or possible) 1573 */ 1574 return (0); 1575 1576 case BGE_NVTYPE_LEGACY_SEEPROM: 1577 case BGE_NVTYPE_UNBUFFERED_FLASH: 1578 case BGE_NVTYPE_BUFFERED_FLASH: 1579 default: 1580 /* 1581 * Access conditional: conduct arbitration protocol 1582 */ 1583 break; 1584 } 1585 1586 /* 1587 * We're holding the per-port mutex <genlock>, so no-one other 1588 * thread can be attempting to access the NVmem through *this* 1589 * port. But it could be in use by the *other* port (of a 5704), 1590 * or by the chip's internal firmware, so we have to go through 1591 * the full (hardware) arbitration protocol ... 1592 * 1593 * Note that *because* we're holding <genlock>, the interrupt handler 1594 * won't be able to progress. So we're only willing to spin for a 1595 * fairly short time. Specifically: 1596 * 1597 * We *must* wait long enough for the hardware to resolve all 1598 * requests and determine the winner. Fortunately, this is 1599 * "almost instantaneous", even as observed by GHz CPUs. 1600 * 1601 * A successful access by another Solaris thread (via either 1602 * port) typically takes ~20us. So waiting a bit longer than 1603 * that will give a good chance of success, if the other user 1604 * *is* another thread on the other port. 1605 * 1606 * However, the internal firmware can hold on to the NVmem 1607 * for *much* longer: at least 10 milliseconds just after a 1608 * RESET, and maybe even longer if the NVmem actually contains 1609 * code to download and run on the internal CPUs. 1610 * 1611 * So, we'll allow 50us; if that's not enough then it's up to the 1612 * caller to retry later (hence the choice of return code EAGAIN). 1613 */ 1614 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1615 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_SET_REQ); 1616 1617 for (tries = 0; tries < 50; ++tries) { 1618 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1619 if (regval & NVM_WON_REQ1) 1620 break; 1621 drv_usecwait(1); 1622 } 1623 1624 if (regval & NVM_WON_REQ1) { 1625 BGE_DEBUG(("bge_nvmem_acquire: won after %d us", tries)); 1626 return (0); 1627 } 1628 1629 /* 1630 * Somebody else must be accessing the NVmem, so abandon our 1631 * attempt take control of it. The caller can try again later ... 1632 */ 1633 BGE_DEBUG(("bge_nvmem_acquire: lost after %d us", tries)); 1634 bge_nvmem_relinquish(bgep); 1635 return (EAGAIN); 1636 } 1637 1638 /* 1639 * This code assumes that the GPIO1 bit has been wired up to the NVmem 1640 * write protect line in such a way that the NVmem is protected when 1641 * GPIO1 is an input, or is an output but driven high. Thus, to make the 1642 * NVmem writable we have to change GPIO1 to an output AND drive it low. 1643 * 1644 * Note: there's only one set of GPIO pins on a 5704, even though they 1645 * can be accessed through either port. So the chip has to resolve what 1646 * happens if the two ports program a single pin differently ... the rule 1647 * it uses is that if the ports disagree about the *direction* of a pin, 1648 * "output" wins over "input", but if they disagree about its *value* as 1649 * an output, then the pin is TRISTATED instead! In such a case, no-one 1650 * wins, and the external signal does whatever the external circuitry 1651 * defines as the default -- which we've assumed is the PROTECTED state. 1652 * So, we always change GPIO1 back to being an *input* whenever we're not 1653 * specifically using it to unprotect the NVmem. This allows either port 1654 * to update the NVmem, although obviously only one at a time! 1655 * 1656 * The caller should hold <genlock> and *also* have already acquired the 1657 * right to access the NVmem, via bge_nvmem_acquire() above. 1658 */ 1659 static void bge_nvmem_protect(bge_t *bgep, boolean_t protect); 1660 #pragma inline(bge_nvmem_protect) 1661 1662 static void 1663 bge_nvmem_protect(bge_t *bgep, boolean_t protect) 1664 { 1665 uint32_t regval; 1666 1667 ASSERT(mutex_owned(bgep->genlock)); 1668 1669 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 1670 if (protect) { 1671 regval |= MLCR_MISC_PINS_OUTPUT_1; 1672 regval &= ~MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1673 } else { 1674 regval &= ~MLCR_MISC_PINS_OUTPUT_1; 1675 regval |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1676 } 1677 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, regval); 1678 } 1679 1680 /* 1681 * Now put it all together ... 1682 * 1683 * Try to acquire control of the NVmem; if successful, then: 1684 * unprotect it (if we want to write to it) 1685 * perform the requested access 1686 * reprotect it (after a write) 1687 * relinquish control 1688 * 1689 * Return value: 1690 * 0 on success, 1691 * EAGAIN if the device is in use (retryable) 1692 * ENODATA on access timeout (maybe retryable: device may just be busy) 1693 * ENODEV if the NVmem device is missing or otherwise unusable 1694 * EPROTO on other h/w or s/w errors. 1695 */ 1696 static int 1697 bge_nvmem_rw32(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1698 { 1699 int err; 1700 1701 if ((err = bge_nvmem_acquire(bgep)) == 0) { 1702 switch (cmd) { 1703 case BGE_SEE_READ: 1704 err = bge_seeprom_access(bgep, 1705 SEEPROM_ACCESS_READ, addr, dp); 1706 break; 1707 1708 case BGE_SEE_WRITE: 1709 bge_nvmem_protect(bgep, B_FALSE); 1710 err = bge_seeprom_access(bgep, 1711 SEEPROM_ACCESS_WRITE, addr, dp); 1712 bge_nvmem_protect(bgep, B_TRUE); 1713 break; 1714 1715 case BGE_FLASH_READ: 1716 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1717 DEVICE_5723_SERIES_CHIPSETS(bgep) || 1718 DEVICE_5717_SERIES_CHIPSETS(bgep) || 1719 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1720 bge_reg_set32(bgep, NVM_ACCESS_REG, 1721 NVM_ACCESS_ENABLE); 1722 } 1723 err = bge_flash_access(bgep, 1724 NVM_FLASH_CMD_RD, addr, dp); 1725 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1726 DEVICE_5723_SERIES_CHIPSETS(bgep) || 1727 DEVICE_5717_SERIES_CHIPSETS(bgep) || 1728 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1729 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1730 NVM_ACCESS_ENABLE); 1731 } 1732 break; 1733 1734 case BGE_FLASH_WRITE: 1735 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1736 DEVICE_5723_SERIES_CHIPSETS(bgep) || 1737 DEVICE_5717_SERIES_CHIPSETS(bgep) || 1738 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1739 bge_reg_set32(bgep, NVM_ACCESS_REG, 1740 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1741 } 1742 bge_nvmem_protect(bgep, B_FALSE); 1743 err = bge_flash_access(bgep, 1744 NVM_FLASH_CMD_WR, addr, dp); 1745 bge_nvmem_protect(bgep, B_TRUE); 1746 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1747 DEVICE_5723_SERIES_CHIPSETS(bgep) || 1748 DEVICE_5717_SERIES_CHIPSETS(bgep) || 1749 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1750 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1751 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1752 } 1753 1754 break; 1755 1756 default: 1757 _NOTE(NOTREACHED) 1758 break; 1759 } 1760 bge_nvmem_relinquish(bgep); 1761 } 1762 1763 BGE_DEBUG(("bge_nvmem_rw32: err %d", err)); 1764 return (err); 1765 } 1766 1767 /* 1768 * Attempt to get a MAC address from the SEEPROM or Flash, if any 1769 */ 1770 static uint64_t bge_get_nvmac(bge_t *bgep); 1771 #pragma no_inline(bge_get_nvmac) 1772 1773 static uint64_t 1774 bge_get_nvmac(bge_t *bgep) 1775 { 1776 uint32_t mac_high; 1777 uint32_t mac_low; 1778 uint32_t addr; 1779 uint32_t cmd; 1780 uint64_t mac; 1781 1782 BGE_TRACE(("bge_get_nvmac($%p)", 1783 (void *)bgep)); 1784 1785 switch (bgep->chipid.nvtype) { 1786 case BGE_NVTYPE_NONE: 1787 case BGE_NVTYPE_UNKNOWN: 1788 default: 1789 return (0ULL); 1790 1791 case BGE_NVTYPE_SEEPROM: 1792 case BGE_NVTYPE_LEGACY_SEEPROM: 1793 cmd = BGE_SEE_READ; 1794 break; 1795 1796 case BGE_NVTYPE_UNBUFFERED_FLASH: 1797 case BGE_NVTYPE_BUFFERED_FLASH: 1798 cmd = BGE_FLASH_READ; 1799 break; 1800 } 1801 1802 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) 1803 addr = NVMEM_DATA_MAC_ADDRESS_5906; 1804 else 1805 addr = NVMEM_DATA_MAC_ADDRESS; 1806 1807 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_high)) 1808 return (0ULL); 1809 addr += 4; 1810 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_low)) 1811 return (0ULL); 1812 1813 /* 1814 * The Broadcom chip is natively BIG-endian, so that's how the 1815 * MAC address is represented in NVmem. We may need to swap it 1816 * around on a little-endian host ... 1817 */ 1818 #ifdef _BIG_ENDIAN 1819 mac = mac_high; 1820 mac = mac << 32; 1821 mac |= mac_low; 1822 #else 1823 mac = BGE_BSWAP_32(mac_high); 1824 mac = mac << 32; 1825 mac |= BGE_BSWAP_32(mac_low); 1826 #endif /* _BIG_ENDIAN */ 1827 1828 return (mac); 1829 } 1830 1831 #else /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1832 1833 /* 1834 * Dummy version for when we're not supporting NVmem access 1835 */ 1836 static uint64_t bge_get_nvmac(bge_t *bgep); 1837 #pragma inline(bge_get_nvmac) 1838 1839 static uint64_t 1840 bge_get_nvmac(bge_t *bgep) 1841 { 1842 _NOTE(ARGUNUSED(bgep)) 1843 return (0ULL); 1844 } 1845 1846 #endif /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1847 1848 /* 1849 * Determine the type of NVmem that is (or may be) attached to this chip, 1850 */ 1851 static enum bge_nvmem_type bge_nvmem_id(bge_t *bgep); 1852 #pragma no_inline(bge_nvmem_id) 1853 1854 static enum bge_nvmem_type 1855 bge_nvmem_id(bge_t *bgep) 1856 { 1857 enum bge_nvmem_type nvtype; 1858 uint32_t config1; 1859 1860 BGE_TRACE(("bge_nvmem_id($%p)", 1861 (void *)bgep)); 1862 1863 switch (bgep->chipid.device) { 1864 default: 1865 /* 1866 * We shouldn't get here; it means we don't recognise 1867 * the chip, which means we don't know how to determine 1868 * what sort of NVmem (if any) it has. So we'll say 1869 * NONE, to disable the NVmem access code ... 1870 */ 1871 nvtype = BGE_NVTYPE_NONE; 1872 break; 1873 1874 case DEVICE_ID_5700: 1875 case DEVICE_ID_5700x: 1876 case DEVICE_ID_5701: 1877 /* 1878 * These devices support *only* SEEPROMs 1879 */ 1880 nvtype = BGE_NVTYPE_SEEPROM; 1881 break; 1882 1883 case DEVICE_ID_5702: 1884 case DEVICE_ID_5702fe: 1885 case DEVICE_ID_5703C: 1886 case DEVICE_ID_5703S: 1887 case DEVICE_ID_5704C: 1888 case DEVICE_ID_5704S: 1889 case DEVICE_ID_5704: 1890 case DEVICE_ID_5705M: 1891 case DEVICE_ID_5705C: 1892 case DEVICE_ID_5705_2: 1893 case DEVICE_ID_5718: 1894 case DEVICE_ID_5780: 1895 case DEVICE_ID_5782: 1896 case DEVICE_ID_5785: 1897 case DEVICE_ID_5787: 1898 case DEVICE_ID_5787M: 1899 case DEVICE_ID_5788: 1900 case DEVICE_ID_5789: 1901 case DEVICE_ID_5751: 1902 case DEVICE_ID_5751M: 1903 case DEVICE_ID_5752: 1904 case DEVICE_ID_5752M: 1905 case DEVICE_ID_5754: 1906 case DEVICE_ID_5755: 1907 case DEVICE_ID_5755M: 1908 case DEVICE_ID_5756M: 1909 case DEVICE_ID_5721: 1910 case DEVICE_ID_5722: 1911 case DEVICE_ID_5723: 1912 case DEVICE_ID_5761: 1913 case DEVICE_ID_5761E: 1914 case DEVICE_ID_5764: 1915 case DEVICE_ID_5714C: 1916 case DEVICE_ID_5714S: 1917 case DEVICE_ID_5715C: 1918 case DEVICE_ID_5715S: 1919 config1 = bge_reg_get32(bgep, NVM_CONFIG1_REG); 1920 if (config1 & NVM_CFG1_FLASH_MODE) 1921 if (config1 & NVM_CFG1_BUFFERED_MODE) 1922 nvtype = BGE_NVTYPE_BUFFERED_FLASH; 1923 else 1924 nvtype = BGE_NVTYPE_UNBUFFERED_FLASH; 1925 else 1926 nvtype = BGE_NVTYPE_LEGACY_SEEPROM; 1927 break; 1928 case DEVICE_ID_5906: 1929 case DEVICE_ID_5906M: 1930 nvtype = BGE_NVTYPE_BUFFERED_FLASH; 1931 break; 1932 } 1933 1934 return (nvtype); 1935 } 1936 1937 #undef BGE_DBG 1938 #define BGE_DBG BGE_DBG_CHIP /* debug flag for this code */ 1939 1940 static void 1941 bge_init_recv_rule(bge_t *bgep) 1942 { 1943 bge_recv_rule_t *rulep = bgep->recv_rules; 1944 uint32_t i; 1945 1946 /* 1947 * Initialize receive rule registers. 1948 * Note that rules may persist across each bge_m_start/stop() call. 1949 */ 1950 for (i = 0; i < RECV_RULES_NUM_MAX; i++, rulep++) { 1951 bge_reg_put32(bgep, RECV_RULE_MASK_REG(i), rulep->mask_value); 1952 bge_reg_put32(bgep, RECV_RULE_CONTROL_REG(i), rulep->control); 1953 } 1954 } 1955 1956 /* 1957 * Using the values captured by bge_chip_cfg_init(), and additional probes 1958 * as required, characterise the chip fully: determine the label by which 1959 * to refer to this chip, the correct settings for various registers, and 1960 * of course whether the device and/or subsystem are supported! 1961 */ 1962 int bge_chip_id_init(bge_t *bgep); 1963 #pragma no_inline(bge_chip_id_init) 1964 1965 int 1966 bge_chip_id_init(bge_t *bgep) 1967 { 1968 char buf[MAXPATHLEN]; /* any risk of stack overflow? */ 1969 boolean_t sys_ok; 1970 boolean_t dev_ok; 1971 chip_id_t *cidp; 1972 uint32_t subid; 1973 char *devname; 1974 char *sysname; 1975 int *ids; 1976 int err; 1977 uint_t i; 1978 1979 sys_ok = dev_ok = B_FALSE; 1980 cidp = &bgep->chipid; 1981 1982 /* 1983 * Check the PCI device ID to determine the generic chip type and 1984 * select parameters that depend on this. 1985 * 1986 * Note: because the SPARC platforms in general don't fit the 1987 * SEEPROM 'behind' the chip, the PCI revision ID register reads 1988 * as zero - which is why we use <asic_rev> rather than <revision> 1989 * below ... 1990 * 1991 * Note: in general we can't distinguish between the Copper/SerDes 1992 * versions by ID alone, as some Copper devices (e.g. some but not 1993 * all 5703Cs) have the same ID as the SerDes equivalents. So we 1994 * treat them the same here, and the MII code works out the media 1995 * type later on ... 1996 */ 1997 cidp->mbuf_base = bge_mbuf_pool_base; 1998 cidp->mbuf_length = bge_mbuf_pool_len; 1999 cidp->recv_slots = BGE_RECV_SLOTS_USED; 2000 cidp->bge_dma_rwctrl = bge_dma_rwctrl; 2001 cidp->pci_type = BGE_PCI_X; 2002 cidp->statistic_type = BGE_STAT_BLK; 2003 cidp->mbuf_lo_water_rdma = bge_mbuf_lo_water_rdma; 2004 cidp->mbuf_lo_water_rmac = bge_mbuf_lo_water_rmac; 2005 cidp->mbuf_hi_water = bge_mbuf_hi_water; 2006 cidp->rx_ticks_norm = bge_rx_ticks_norm; 2007 cidp->rx_count_norm = bge_rx_count_norm; 2008 cidp->tx_ticks_norm = bge_tx_ticks_norm; 2009 cidp->tx_count_norm = bge_tx_count_norm; 2010 cidp->mask_pci_int = MHCR_MASK_PCI_INT_OUTPUT; 2011 2012 if (cidp->rx_rings == 0 || cidp->rx_rings > BGE_RECV_RINGS_MAX) 2013 cidp->rx_rings = BGE_RECV_RINGS_DEFAULT; 2014 if (cidp->tx_rings == 0 || cidp->tx_rings > BGE_SEND_RINGS_MAX) 2015 cidp->tx_rings = BGE_SEND_RINGS_DEFAULT; 2016 2017 cidp->msi_enabled = B_FALSE; 2018 2019 switch (cidp->device) { 2020 case DEVICE_ID_5718: 2021 cidp->chip_label = 5718; 2022 cidp->msi_enabled = bge_enable_msi; 2023 #ifdef __sparc 2024 cidp->mask_pci_int = LE_32(MHCR_MASK_PCI_INT_OUTPUT); 2025 #endif 2026 cidp->bge_dma_rwctrl = LE_32(PDRWCR_VAR_5717); 2027 cidp->pci_type = BGE_PCI_E; 2028 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2029 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5717; 2030 cidp->mbuf_hi_water = MBUF_HIWAT_5717; 2031 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2032 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2033 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2034 cidp->bge_mlcr_default = MLCR_DEFAULT_5717; 2035 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2036 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2037 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2038 cidp->statistic_type = BGE_STAT_REG; 2039 dev_ok = B_TRUE; 2040 break; 2041 2042 case DEVICE_ID_5700: 2043 case DEVICE_ID_5700x: 2044 cidp->chip_label = 5700; 2045 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2046 break; 2047 2048 case DEVICE_ID_5701: 2049 cidp->chip_label = 5701; 2050 dev_ok = B_TRUE; 2051 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2052 break; 2053 2054 case DEVICE_ID_5702: 2055 case DEVICE_ID_5702fe: 2056 cidp->chip_label = 5702; 2057 dev_ok = B_TRUE; 2058 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2059 cidp->pci_type = BGE_PCI; 2060 break; 2061 2062 case DEVICE_ID_5703C: 2063 case DEVICE_ID_5703S: 2064 case DEVICE_ID_5703: 2065 /* 2066 * Revision A0 of the 5703/5793 had various errata 2067 * that we can't or don't work around, so it's not 2068 * supported, but all later versions are 2069 */ 2070 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5793 : 5703; 2071 if (bgep->chipid.asic_rev != MHCR_CHIP_REV_5703_A0) 2072 dev_ok = B_TRUE; 2073 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2074 break; 2075 2076 case DEVICE_ID_5704C: 2077 case DEVICE_ID_5704S: 2078 case DEVICE_ID_5704: 2079 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5794 : 5704; 2080 cidp->mbuf_base = bge_mbuf_pool_base_5704; 2081 cidp->mbuf_length = bge_mbuf_pool_len_5704; 2082 dev_ok = B_TRUE; 2083 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2084 break; 2085 2086 case DEVICE_ID_5705C: 2087 case DEVICE_ID_5705M: 2088 case DEVICE_ID_5705MA3: 2089 case DEVICE_ID_5705F: 2090 case DEVICE_ID_5705_2: 2091 case DEVICE_ID_5754: 2092 if (cidp->device == DEVICE_ID_5754) { 2093 cidp->chip_label = 5754; 2094 cidp->pci_type = BGE_PCI_E; 2095 } else { 2096 cidp->chip_label = 5705; 2097 cidp->pci_type = BGE_PCI; 2098 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2099 } 2100 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2101 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2102 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2103 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2104 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2105 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2106 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2107 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2108 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2109 cidp->statistic_type = BGE_STAT_REG; 2110 dev_ok = B_TRUE; 2111 break; 2112 2113 case DEVICE_ID_5906: 2114 case DEVICE_ID_5906M: 2115 cidp->chip_label = 5906; 2116 cidp->pci_type = BGE_PCI_E; 2117 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5906; 2118 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5906; 2119 cidp->mbuf_hi_water = MBUF_HIWAT_5906; 2120 cidp->mbuf_base = bge_mbuf_pool_base; 2121 cidp->mbuf_length = bge_mbuf_pool_len; 2122 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2123 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2124 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2125 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2126 cidp->statistic_type = BGE_STAT_REG; 2127 dev_ok = B_TRUE; 2128 break; 2129 2130 case DEVICE_ID_5753: 2131 cidp->chip_label = 5753; 2132 cidp->pci_type = BGE_PCI_E; 2133 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2134 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2135 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2136 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2137 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2138 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2139 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2140 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2141 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2142 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2143 cidp->statistic_type = BGE_STAT_REG; 2144 dev_ok = B_TRUE; 2145 break; 2146 2147 case DEVICE_ID_5755: 2148 case DEVICE_ID_5755M: 2149 cidp->chip_label = 5755; 2150 cidp->pci_type = BGE_PCI_E; 2151 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2152 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2153 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2154 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2155 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2156 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2157 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2158 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2159 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2160 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2161 if (cidp->device == DEVICE_ID_5755M) 2162 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2163 cidp->statistic_type = BGE_STAT_REG; 2164 dev_ok = B_TRUE; 2165 break; 2166 2167 case DEVICE_ID_5756M: 2168 /* 2169 * This is nearly identical to the 5755M. 2170 * (Actually reports the 5755 chip ID.) 2171 */ 2172 cidp->chip_label = 5756; 2173 cidp->pci_type = BGE_PCI_E; 2174 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2175 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2176 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2177 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2178 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2179 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2180 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2181 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2182 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2183 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2184 cidp->statistic_type = BGE_STAT_REG; 2185 dev_ok = B_TRUE; 2186 break; 2187 2188 case DEVICE_ID_5787: 2189 case DEVICE_ID_5787M: 2190 cidp->chip_label = 5787; 2191 cidp->pci_type = BGE_PCI_E; 2192 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2193 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2194 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2195 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2196 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2197 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2198 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2199 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2200 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2201 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2202 cidp->statistic_type = BGE_STAT_REG; 2203 dev_ok = B_TRUE; 2204 break; 2205 2206 case DEVICE_ID_5723: 2207 case DEVICE_ID_5761: 2208 case DEVICE_ID_5761E: 2209 cidp->msi_enabled = bge_enable_msi; 2210 /* 2211 * We don't use MSI for BCM5764 and BCM5785, as the 2212 * status block may fail to update when the network 2213 * traffic is heavy. 2214 */ 2215 /* FALLTHRU */ 2216 case DEVICE_ID_5785: 2217 case DEVICE_ID_5764: 2218 if (cidp->device == DEVICE_ID_5723) 2219 cidp->chip_label = 5723; 2220 else if (cidp->device == DEVICE_ID_5764) 2221 cidp->chip_label = 5764; 2222 else if (cidp->device == DEVICE_ID_5785) 2223 cidp->chip_label = 5785; 2224 else 2225 cidp->chip_label = 5761; 2226 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2227 cidp->pci_type = BGE_PCI_E; 2228 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2229 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2230 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2231 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2232 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2233 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2234 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2235 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2236 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2237 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2238 cidp->statistic_type = BGE_STAT_REG; 2239 dev_ok = B_TRUE; 2240 break; 2241 2242 /* PCI-X device, identical to 5714 */ 2243 case DEVICE_ID_5780: 2244 cidp->chip_label = 5780; 2245 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2246 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2247 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2248 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2249 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2250 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2251 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2252 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2253 cidp->statistic_type = BGE_STAT_REG; 2254 dev_ok = B_TRUE; 2255 break; 2256 2257 case DEVICE_ID_5782: 2258 /* 2259 * Apart from the label, we treat this as a 5705(?) 2260 */ 2261 cidp->chip_label = 5782; 2262 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2263 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2264 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2265 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2266 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2267 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2268 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2269 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2270 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2271 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2272 cidp->statistic_type = BGE_STAT_REG; 2273 dev_ok = B_TRUE; 2274 break; 2275 2276 case DEVICE_ID_5788: 2277 /* 2278 * Apart from the label, we treat this as a 5705(?) 2279 */ 2280 cidp->chip_label = 5788; 2281 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2282 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2283 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2284 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2285 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2286 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2287 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2288 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2289 cidp->statistic_type = BGE_STAT_REG; 2290 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2291 dev_ok = B_TRUE; 2292 break; 2293 2294 case DEVICE_ID_5714C: 2295 if (cidp->revision >= REVISION_ID_5714_A2) 2296 cidp->msi_enabled = bge_enable_msi; 2297 /* FALLTHRU */ 2298 case DEVICE_ID_5714S: 2299 cidp->chip_label = 5714; 2300 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2301 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2302 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2303 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2304 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2305 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2306 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5714; 2307 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2308 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2309 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2310 cidp->pci_type = BGE_PCI_E; 2311 cidp->statistic_type = BGE_STAT_REG; 2312 dev_ok = B_TRUE; 2313 break; 2314 2315 case DEVICE_ID_5715C: 2316 case DEVICE_ID_5715S: 2317 cidp->chip_label = 5715; 2318 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2319 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2320 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2321 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2322 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2323 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2324 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5715; 2325 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2326 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2327 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2328 cidp->pci_type = BGE_PCI_E; 2329 cidp->statistic_type = BGE_STAT_REG; 2330 if (cidp->revision >= REVISION_ID_5715_A2) 2331 cidp->msi_enabled = bge_enable_msi; 2332 dev_ok = B_TRUE; 2333 break; 2334 2335 case DEVICE_ID_5721: 2336 cidp->chip_label = 5721; 2337 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2338 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2339 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2340 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2341 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2342 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2343 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2344 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2345 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2346 cidp->pci_type = BGE_PCI_E; 2347 cidp->statistic_type = BGE_STAT_REG; 2348 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2349 dev_ok = B_TRUE; 2350 break; 2351 2352 case DEVICE_ID_5722: 2353 cidp->chip_label = 5722; 2354 cidp->pci_type = BGE_PCI_E; 2355 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2356 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2357 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2358 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2359 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2360 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2361 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2362 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2363 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2364 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2365 cidp->statistic_type = BGE_STAT_REG; 2366 dev_ok = B_TRUE; 2367 break; 2368 2369 case DEVICE_ID_5751: 2370 case DEVICE_ID_5751M: 2371 cidp->chip_label = 5751; 2372 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2373 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2374 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2375 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2376 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2377 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2378 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2379 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2380 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2381 cidp->pci_type = BGE_PCI_E; 2382 cidp->statistic_type = BGE_STAT_REG; 2383 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2384 dev_ok = B_TRUE; 2385 break; 2386 2387 case DEVICE_ID_5752: 2388 case DEVICE_ID_5752M: 2389 cidp->chip_label = 5752; 2390 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2391 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2392 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2393 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2394 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2395 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2396 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2397 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2398 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2399 cidp->pci_type = BGE_PCI_E; 2400 cidp->statistic_type = BGE_STAT_REG; 2401 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2402 dev_ok = B_TRUE; 2403 break; 2404 2405 case DEVICE_ID_5789: 2406 cidp->chip_label = 5789; 2407 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2408 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2409 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2410 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2411 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2412 cidp->tx_rings = BGE_RECV_RINGS_MAX_5705; 2413 cidp->pci_type = BGE_PCI_E; 2414 cidp->statistic_type = BGE_STAT_REG; 2415 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2416 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2417 cidp->msi_enabled = B_TRUE; 2418 dev_ok = B_TRUE; 2419 break; 2420 2421 } 2422 2423 /* 2424 * Setup the default jumbo parameter. 2425 */ 2426 cidp->ethmax_size = ETHERMAX; 2427 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_DEFAULT; 2428 cidp->std_buf_size = BGE_STD_BUFF_SIZE; 2429 2430 /* 2431 * If jumbo is enabled and this kind of chipset supports jumbo feature, 2432 * setup below jumbo specific parameters. 2433 * 2434 * For BCM5714/5715, there is only one standard receive ring. So the 2435 * std buffer size should be set to BGE_JUMBO_BUFF_SIZE when jumbo 2436 * feature is enabled. 2437 */ 2438 if (!(cidp->flags & CHIP_FLAG_NO_JUMBO) && 2439 (cidp->default_mtu > BGE_DEFAULT_MTU)) { 2440 if (DEVICE_5714_SERIES_CHIPSETS(bgep)) { 2441 cidp->mbuf_lo_water_rdma = 2442 RDMA_MBUF_LOWAT_5714_JUMBO; 2443 cidp->mbuf_lo_water_rmac = 2444 MAC_RX_MBUF_LOWAT_5714_JUMBO; 2445 cidp->mbuf_hi_water = MBUF_HIWAT_5714_JUMBO; 2446 cidp->jumbo_slots = 0; 2447 cidp->std_buf_size = BGE_JUMBO_BUFF_SIZE; 2448 } else { 2449 cidp->mbuf_lo_water_rdma = 2450 RDMA_MBUF_LOWAT_JUMBO; 2451 cidp->mbuf_lo_water_rmac = 2452 MAC_RX_MBUF_LOWAT_JUMBO; 2453 cidp->mbuf_hi_water = MBUF_HIWAT_JUMBO; 2454 cidp->jumbo_slots = BGE_JUMBO_SLOTS_USED; 2455 } 2456 cidp->recv_jumbo_size = BGE_JUMBO_BUFF_SIZE; 2457 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_JUMBO; 2458 cidp->ethmax_size = cidp->default_mtu + 2459 sizeof (struct ether_header); 2460 } 2461 2462 /* 2463 * Identify the NV memory type: SEEPROM or Flash? 2464 */ 2465 cidp->nvtype = bge_nvmem_id(bgep); 2466 2467 /* 2468 * Now, we want to check whether this device is part of a 2469 * supported subsystem (e.g., on the motherboard of a Sun 2470 * branded platform). 2471 * 2472 * Rule 1: If the Subsystem Vendor ID is "Sun", then it's OK ;-) 2473 */ 2474 if (cidp->subven == VENDOR_ID_SUN) 2475 sys_ok = B_TRUE; 2476 2477 /* 2478 * Rule 2: If it's on the list on known subsystems, then it's OK. 2479 * Note: 0x14e41647 should *not* appear in the list, but the code 2480 * doesn't enforce that. 2481 */ 2482 err = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, bgep->devinfo, 2483 DDI_PROP_DONTPASS, knownids_propname, &ids, &i); 2484 if (err == DDI_PROP_SUCCESS) { 2485 /* 2486 * Got the list; scan for a matching subsystem vendor/device 2487 */ 2488 subid = (cidp->subven << 16) | cidp->subdev; 2489 while (i--) 2490 if (ids[i] == subid) 2491 sys_ok = B_TRUE; 2492 ddi_prop_free(ids); 2493 } 2494 2495 /* 2496 * Rule 3: If it's a Taco/ENWS motherboard device, then it's OK 2497 * 2498 * Unfortunately, early SunBlade 1500s and 2500s didn't reprogram 2499 * the Subsystem Vendor ID, so it defaults to Broadcom. Therefore, 2500 * we have to check specially for the exact device paths to the 2501 * motherboard devices on those platforms ;-( 2502 * 2503 * Note: we can't just use the "supported-subsystems" mechanism 2504 * above, because the entry would have to be 0x14e41647 -- which 2505 * would then accept *any* plugin card that *didn't* contain a 2506 * (valid) SEEPROM ;-( 2507 */ 2508 sysname = ddi_node_name(ddi_root_node()); 2509 devname = ddi_pathname(bgep->devinfo, buf); 2510 ASSERT(strlen(devname) > 0); 2511 if (strcmp(sysname, "SUNW,Sun-Blade-1500") == 0) /* Taco */ 2512 if (strcmp(devname, "/pci@1f,700000/network@2") == 0) 2513 sys_ok = B_TRUE; 2514 if (strcmp(sysname, "SUNW,Sun-Blade-2500") == 0) /* ENWS */ 2515 if (strcmp(devname, "/pci@1c,600000/network@3") == 0) 2516 sys_ok = B_TRUE; 2517 2518 /* 2519 * Now check what we've discovered: is this truly a supported 2520 * chip on (the motherboard of) a supported platform? 2521 * 2522 * Possible problems here: 2523 * 1) it's a completely unheard-of chip 2524 * 2) it's a recognised but unsupported chip (e.g. 5701, 5703C-A0) 2525 * 3) it's a chip we would support if it were on the motherboard 2526 * of a Sun platform, but this one isn't ;-( 2527 */ 2528 if (cidp->chip_label == 0) 2529 bge_problem(bgep, 2530 "Device 'pci%04x,%04x' not recognized (%d?)", 2531 cidp->vendor, cidp->device, cidp->device); 2532 else if (!dev_ok) 2533 bge_problem(bgep, 2534 "Device 'pci%04x,%04x' (%d) revision %d not supported", 2535 cidp->vendor, cidp->device, cidp->chip_label, 2536 cidp->revision); 2537 #if BGE_DEBUGGING 2538 else if (!sys_ok) 2539 bge_problem(bgep, 2540 "%d-based subsystem 'pci%04x,%04x' not validated", 2541 cidp->chip_label, cidp->subven, cidp->subdev); 2542 #endif 2543 else 2544 cidp->flags |= CHIP_FLAG_SUPPORTED; 2545 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 2546 return (EIO); 2547 return (0); 2548 } 2549 2550 void 2551 bge_chip_msi_trig(bge_t *bgep) 2552 { 2553 uint32_t regval; 2554 2555 regval = bgep->param_msi_cnt<<4; 2556 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, regval); 2557 BGE_DEBUG(("bge_chip_msi_trig:data = %d", regval)); 2558 } 2559 2560 /* 2561 * Various registers that control the chip's internal engines (state 2562 * machines) have a <reset> and <enable> bits (fortunately, in the 2563 * same place in each such register :-). 2564 * 2565 * To reset the state machine, the <reset> bit must be written with 1; 2566 * it will then read back as 1 while the reset is in progress, but 2567 * self-clear to 0 when the reset completes. 2568 * 2569 * To enable a state machine, one must set the <enable> bit, which 2570 * will continue to read back as 0 until the state machine is running. 2571 * 2572 * To disable a state machine, the <enable> bit must be cleared, but 2573 * it will continue to read back as 1 until the state machine actually 2574 * stops. 2575 * 2576 * This routine implements polling for completion of a reset, enable 2577 * or disable operation, returning B_TRUE on success (bit reached the 2578 * required state) or B_FALSE on timeout (200*100us == 20ms). 2579 */ 2580 static boolean_t bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 2581 uint32_t mask, uint32_t val); 2582 #pragma no_inline(bge_chip_poll_engine) 2583 2584 static boolean_t 2585 bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 2586 uint32_t mask, uint32_t val) 2587 { 2588 uint32_t regval; 2589 uint32_t n; 2590 2591 BGE_TRACE(("bge_chip_poll_engine($%p, 0x%lx, 0x%x, 0x%x)", 2592 (void *)bgep, regno, mask, val)); 2593 2594 for (n = 200; n; --n) { 2595 regval = bge_reg_get32(bgep, regno); 2596 if ((regval & mask) == val) 2597 return (B_TRUE); 2598 drv_usecwait(100); 2599 } 2600 2601 bge_problem(bgep, "bge_chip_poll_engine failed: regno = 0x%lx", regno); 2602 bge_fm_ereport(bgep, DDI_FM_DEVICE_NO_RESPONSE); 2603 return (B_FALSE); 2604 } 2605 2606 /* 2607 * Various registers that control the chip's internal engines (state 2608 * machines) have a <reset> bit (fortunately, in the same place in 2609 * each such register :-). To reset the state machine, this bit must 2610 * be written with 1; it will then read back as 1 while the reset is 2611 * in progress, but self-clear to 0 when the reset completes. 2612 * 2613 * This code sets the bit, then polls for it to read back as zero. 2614 * The return value is B_TRUE on success (reset bit cleared itself), 2615 * or B_FALSE if the state machine didn't recover :( 2616 * 2617 * NOTE: the Core reset is similar to other resets, except that we 2618 * can't poll for completion, since the Core reset disables memory 2619 * access! So we just have to assume that it will all complete in 2620 * 100us. See Broadcom document 570X-PG102-R, p102, steps 4-5. 2621 */ 2622 static boolean_t bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno); 2623 #pragma no_inline(bge_chip_reset_engine) 2624 2625 static boolean_t 2626 bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno) 2627 { 2628 uint32_t regval; 2629 uint32_t val32; 2630 2631 regval = bge_reg_get32(bgep, regno); 2632 2633 BGE_TRACE(("bge_chip_reset_engine($%p, 0x%lx)", 2634 (void *)bgep, regno)); 2635 BGE_DEBUG(("bge_chip_reset_engine: 0x%lx before reset = 0x%08x", 2636 regno, regval)); 2637 2638 regval |= STATE_MACHINE_RESET_BIT; 2639 2640 switch (regno) { 2641 case MISC_CONFIG_REG: 2642 /* 2643 * BCM5714/5721/5751 pcie chip special case. In order to avoid 2644 * resetting PCIE block and bringing PCIE link down, bit 29 2645 * in the register needs to be set first, and then set it again 2646 * while the reset bit is written. 2647 * See:P500 of 57xx-PG102-RDS.pdf. 2648 */ 2649 if (DEVICE_5705_SERIES_CHIPSETS(bgep)|| 2650 DEVICE_5717_SERIES_CHIPSETS(bgep)|| 2651 DEVICE_5721_SERIES_CHIPSETS(bgep)|| 2652 DEVICE_5723_SERIES_CHIPSETS(bgep)|| 2653 DEVICE_5714_SERIES_CHIPSETS(bgep)|| 2654 DEVICE_5906_SERIES_CHIPSETS(bgep)) { 2655 regval |= MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE; 2656 if (bgep->chipid.pci_type == BGE_PCI_E) { 2657 if (bgep->chipid.asic_rev == 2658 MHCR_CHIP_REV_5751_A0 || 2659 bgep->chipid.asic_rev == 2660 MHCR_CHIP_REV_5721_A0 || 2661 bgep->chipid.asic_rev == 2662 MHCR_CHIP_REV_5755_A0) { 2663 val32 = bge_reg_get32(bgep, 2664 PHY_TEST_CTRL_REG); 2665 if (val32 == (PHY_PCIE_SCRAM_MODE | 2666 PHY_PCIE_LTASS_MODE)) 2667 bge_reg_put32(bgep, 2668 PHY_TEST_CTRL_REG, 2669 PHY_PCIE_SCRAM_MODE); 2670 val32 = pci_config_get32 2671 (bgep->cfg_handle, 2672 PCI_CONF_BGE_CLKCTL); 2673 val32 |= CLKCTL_PCIE_A0_FIX; 2674 pci_config_put32(bgep->cfg_handle, 2675 PCI_CONF_BGE_CLKCTL, val32); 2676 } 2677 bge_reg_set32(bgep, regno, 2678 MISC_CONFIG_GRC_RESET_DISABLE); 2679 regval |= MISC_CONFIG_GRC_RESET_DISABLE; 2680 } 2681 } 2682 2683 /* 2684 * Special case - causes Core reset 2685 * 2686 * On SPARC v9 we want to ensure that we don't start 2687 * timing until the I/O access has actually reached 2688 * the chip, otherwise we might make the next access 2689 * too early. And we can't just force the write out 2690 * by following it with a read (even to config space) 2691 * because that would cause the fault we're trying 2692 * to avoid. Hence the need for membar_sync() here. 2693 */ 2694 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), regval); 2695 #ifdef __sparcv9 2696 membar_sync(); 2697 #endif /* __sparcv9 */ 2698 /* 2699 * On some platforms,system need about 300us for 2700 * link setup. 2701 */ 2702 drv_usecwait(300); 2703 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) { 2704 bge_reg_set32(bgep, VCPU_STATUS_REG, VCPU_DRV_RESET); 2705 bge_reg_clr32( 2706 bgep, VCPU_EXT_CTL, VCPU_EXT_CTL_HALF); 2707 } 2708 2709 if (bgep->chipid.pci_type == BGE_PCI_E) { 2710 /* PCI-E device need more reset time */ 2711 drv_usecwait(120000); 2712 2713 /* Set PCIE max payload size and clear error status. */ 2714 if ((bgep->chipid.chip_label == 5721) || 2715 (bgep->chipid.chip_label == 5751) || 2716 (bgep->chipid.chip_label == 5752) || 2717 (bgep->chipid.chip_label == 5789) || 2718 (bgep->chipid.chip_label == 5906)) { 2719 pci_config_put16(bgep->cfg_handle, 2720 PCI_CONF_DEV_CTRL, READ_REQ_SIZE_MAX); 2721 pci_config_put16(bgep->cfg_handle, 2722 PCI_CONF_DEV_STUS, DEVICE_ERROR_STUS); 2723 } 2724 2725 if ((bgep->chipid.chip_label == 5723) || 2726 (bgep->chipid.chip_label == 5761)) { 2727 pci_config_put16(bgep->cfg_handle, 2728 PCI_CONF_DEV_CTRL_5723, READ_REQ_SIZE_MAX); 2729 pci_config_put16(bgep->cfg_handle, 2730 PCI_CONF_DEV_STUS_5723, DEVICE_ERROR_STUS); 2731 } 2732 } 2733 2734 BGE_PCICHK(bgep); 2735 return (B_TRUE); 2736 2737 default: 2738 bge_reg_put32(bgep, regno, regval); 2739 return (bge_chip_poll_engine(bgep, regno, 2740 STATE_MACHINE_RESET_BIT, 0)); 2741 } 2742 } 2743 2744 /* 2745 * Various registers that control the chip's internal engines (state 2746 * machines) have an <enable> bit (fortunately, in the same place in 2747 * each such register :-). To stop the state machine, this bit must 2748 * be written with 0, then polled to see when the state machine has 2749 * actually stopped. 2750 * 2751 * The return value is B_TRUE on success (enable bit cleared), or 2752 * B_FALSE if the state machine didn't stop :( 2753 */ 2754 static boolean_t bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, 2755 uint32_t morebits); 2756 #pragma no_inline(bge_chip_disable_engine) 2757 2758 static boolean_t 2759 bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 2760 { 2761 uint32_t regval; 2762 2763 BGE_TRACE(("bge_chip_disable_engine($%p, 0x%lx, 0x%x)", 2764 (void *)bgep, regno, morebits)); 2765 2766 switch (regno) { 2767 case FTQ_RESET_REG: 2768 /* 2769 * For Schumacher's bugfix CR6490108 2770 */ 2771 #ifdef BGE_IPMI_ASF 2772 #ifdef BGE_NETCONSOLE 2773 if (bgep->asf_enabled) 2774 return (B_TRUE); 2775 #endif 2776 #endif 2777 /* 2778 * Not quite like the others; it doesn't 2779 * have an <enable> bit, but instead we 2780 * have to set and then clear all the bits 2781 */ 2782 bge_reg_put32(bgep, regno, ~(uint32_t)0); 2783 drv_usecwait(100); 2784 bge_reg_put32(bgep, regno, 0); 2785 return (B_TRUE); 2786 2787 default: 2788 regval = bge_reg_get32(bgep, regno); 2789 regval &= ~STATE_MACHINE_ENABLE_BIT; 2790 regval &= ~morebits; 2791 bge_reg_put32(bgep, regno, regval); 2792 return (bge_chip_poll_engine(bgep, regno, 2793 STATE_MACHINE_ENABLE_BIT, 0)); 2794 } 2795 } 2796 2797 /* 2798 * Various registers that control the chip's internal engines (state 2799 * machines) have an <enable> bit (fortunately, in the same place in 2800 * each such register :-). To start the state machine, this bit must 2801 * be written with 1, then polled to see when the state machine has 2802 * actually started. 2803 * 2804 * The return value is B_TRUE on success (enable bit set), or 2805 * B_FALSE if the state machine didn't start :( 2806 */ 2807 static boolean_t bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, 2808 uint32_t morebits); 2809 #pragma no_inline(bge_chip_enable_engine) 2810 2811 static boolean_t 2812 bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 2813 { 2814 uint32_t regval; 2815 2816 BGE_TRACE(("bge_chip_enable_engine($%p, 0x%lx, 0x%x)", 2817 (void *)bgep, regno, morebits)); 2818 2819 switch (regno) { 2820 case FTQ_RESET_REG: 2821 #ifdef BGE_IPMI_ASF 2822 #ifdef BGE_NETCONSOLE 2823 if (bgep->asf_enabled) 2824 return (B_TRUE); 2825 #endif 2826 #endif 2827 /* 2828 * Not quite like the others; it doesn't 2829 * have an <enable> bit, but instead we 2830 * have to set and then clear all the bits 2831 */ 2832 bge_reg_put32(bgep, regno, ~(uint32_t)0); 2833 drv_usecwait(100); 2834 bge_reg_put32(bgep, regno, 0); 2835 return (B_TRUE); 2836 2837 default: 2838 regval = bge_reg_get32(bgep, regno); 2839 regval |= STATE_MACHINE_ENABLE_BIT; 2840 regval |= morebits; 2841 bge_reg_put32(bgep, regno, regval); 2842 return (bge_chip_poll_engine(bgep, regno, 2843 STATE_MACHINE_ENABLE_BIT, STATE_MACHINE_ENABLE_BIT)); 2844 } 2845 } 2846 2847 /* 2848 * Reprogram the Ethernet, Transmit, and Receive MAC 2849 * modes to match the param_* variables 2850 */ 2851 void bge_sync_mac_modes(bge_t *bgep); 2852 #pragma no_inline(bge_sync_mac_modes) 2853 2854 void 2855 bge_sync_mac_modes(bge_t *bgep) 2856 { 2857 uint32_t macmode; 2858 uint32_t regval; 2859 2860 ASSERT(mutex_owned(bgep->genlock)); 2861 2862 /* 2863 * Reprogram the Ethernet MAC mode ... 2864 */ 2865 macmode = regval = bge_reg_get32(bgep, ETHERNET_MAC_MODE_REG); 2866 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 2867 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) 2868 if (DEVICE_5714_SERIES_CHIPSETS(bgep)) 2869 macmode |= ETHERNET_MODE_LINK_POLARITY; 2870 else 2871 macmode &= ~ETHERNET_MODE_LINK_POLARITY; 2872 else 2873 macmode |= ETHERNET_MODE_LINK_POLARITY; 2874 macmode &= ~ETHERNET_MODE_PORTMODE_MASK; 2875 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 2876 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) { 2877 if (DEVICE_5714_SERIES_CHIPSETS(bgep)) 2878 macmode |= ETHERNET_MODE_PORTMODE_GMII; 2879 else 2880 macmode |= ETHERNET_MODE_PORTMODE_TBI; 2881 } else if (bgep->param_link_speed == 10 || 2882 bgep->param_link_speed == 100) 2883 macmode |= ETHERNET_MODE_PORTMODE_MII; 2884 else 2885 macmode |= ETHERNET_MODE_PORTMODE_GMII; 2886 if (bgep->param_link_duplex == LINK_DUPLEX_HALF) 2887 macmode |= ETHERNET_MODE_HALF_DUPLEX; 2888 else 2889 macmode &= ~ETHERNET_MODE_HALF_DUPLEX; 2890 if (bgep->param_loop_mode == BGE_LOOP_INTERNAL_MAC) 2891 macmode |= ETHERNET_MODE_MAC_LOOPBACK; 2892 else 2893 macmode &= ~ETHERNET_MODE_MAC_LOOPBACK; 2894 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, macmode); 2895 BGE_DEBUG(("bge_sync_mac_modes($%p) Ethernet MAC mode 0x%x => 0x%x", 2896 (void *)bgep, regval, macmode)); 2897 2898 /* 2899 * ... the Transmit MAC mode ... 2900 */ 2901 macmode = regval = bge_reg_get32(bgep, TRANSMIT_MAC_MODE_REG); 2902 if (bgep->param_link_tx_pause) 2903 macmode |= TRANSMIT_MODE_FLOW_CONTROL; 2904 else 2905 macmode &= ~TRANSMIT_MODE_FLOW_CONTROL; 2906 bge_reg_put32(bgep, TRANSMIT_MAC_MODE_REG, macmode); 2907 BGE_DEBUG(("bge_sync_mac_modes($%p) Transmit MAC mode 0x%x => 0x%x", 2908 (void *)bgep, regval, macmode)); 2909 2910 /* 2911 * ... and the Receive MAC mode 2912 */ 2913 macmode = regval = bge_reg_get32(bgep, RECEIVE_MAC_MODE_REG); 2914 if (bgep->param_link_rx_pause) 2915 macmode |= RECEIVE_MODE_FLOW_CONTROL; 2916 else 2917 macmode &= ~RECEIVE_MODE_FLOW_CONTROL; 2918 bge_reg_put32(bgep, RECEIVE_MAC_MODE_REG, macmode); 2919 BGE_DEBUG(("bge_sync_mac_modes($%p) Receive MAC mode 0x%x => 0x%x", 2920 (void *)bgep, regval, macmode)); 2921 2922 /* 2923 * For BCM5785, we need to configure the link status in the MI Status 2924 * register with a write command when auto-polling is disabled. 2925 */ 2926 if (bgep->chipid.device == DEVICE_ID_5785) 2927 if (bgep->param_link_speed == 10) 2928 bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK 2929 | MI_STATUS_10MBPS); 2930 else 2931 bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK); 2932 } 2933 2934 /* 2935 * bge_chip_sync() -- program the chip with the unicast MAC address, 2936 * the multicast hash table, the required level of promiscuity, and 2937 * the current loopback mode ... 2938 */ 2939 #ifdef BGE_IPMI_ASF 2940 int bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive); 2941 #else 2942 int bge_chip_sync(bge_t *bgep); 2943 #endif 2944 #pragma no_inline(bge_chip_sync) 2945 2946 int 2947 #ifdef BGE_IPMI_ASF 2948 bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive) 2949 #else 2950 bge_chip_sync(bge_t *bgep) 2951 #endif 2952 { 2953 void (*opfn)(bge_t *bgep, bge_regno_t reg, uint32_t bits); 2954 boolean_t promisc; 2955 uint64_t macaddr; 2956 uint32_t fill = 0; 2957 int i, j; 2958 int retval = DDI_SUCCESS; 2959 2960 BGE_TRACE(("bge_chip_sync($%p)", 2961 (void *)bgep)); 2962 2963 ASSERT(mutex_owned(bgep->genlock)); 2964 2965 promisc = B_FALSE; 2966 fill = ~(uint32_t)0; 2967 2968 if (bgep->promisc) 2969 promisc = B_TRUE; 2970 else 2971 fill = (uint32_t)0; 2972 2973 /* 2974 * If the TX/RX MAC engines are already running, we should stop 2975 * them (and reset the RX engine) before changing the parameters. 2976 * If they're not running, this will have no effect ... 2977 * 2978 * NOTE: this is currently disabled by default because stopping 2979 * and restarting the Tx engine may cause an outgoing packet in 2980 * transit to be truncated. Also, stopping and restarting the 2981 * Rx engine seems to not work correctly on the 5705. Testing 2982 * has not (yet!) revealed any problems with NOT stopping and 2983 * restarting these engines (and Broadcom say their drivers don't 2984 * do this), but if it is found to cause problems, this variable 2985 * can be patched to re-enable the old behaviour ... 2986 */ 2987 if (bge_stop_start_on_sync) { 2988 #ifdef BGE_IPMI_ASF 2989 if (!bgep->asf_enabled) { 2990 if (!bge_chip_disable_engine(bgep, 2991 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG)) 2992 retval = DDI_FAILURE; 2993 } else { 2994 if (!bge_chip_disable_engine(bgep, 2995 RECEIVE_MAC_MODE_REG, 0)) 2996 retval = DDI_FAILURE; 2997 } 2998 #else 2999 if (!bge_chip_disable_engine(bgep, RECEIVE_MAC_MODE_REG, 3000 RECEIVE_MODE_KEEP_VLAN_TAG)) 3001 retval = DDI_FAILURE; 3002 #endif 3003 if (!bge_chip_disable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 3004 retval = DDI_FAILURE; 3005 if (!bge_chip_reset_engine(bgep, RECEIVE_MAC_MODE_REG)) 3006 retval = DDI_FAILURE; 3007 } 3008 3009 /* 3010 * Reprogram the hashed multicast address table ... 3011 */ 3012 for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i) 3013 bge_reg_put32(bgep, MAC_HASH_REG(i), 0); 3014 3015 for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i) 3016 bge_reg_put32(bgep, MAC_HASH_REG(i), 3017 bgep->mcast_hash[i] | fill); 3018 3019 #ifdef BGE_IPMI_ASF 3020 if (!bgep->asf_enabled || !asf_keeplive) { 3021 #endif 3022 /* 3023 * Transform the MAC address(es) from host to chip format, then 3024 * reprogram the transmit random backoff seed and the unicast 3025 * MAC address(es) ... 3026 */ 3027 for (j = 0; j < MAC_ADDRESS_REGS_MAX; j++) { 3028 for (i = 0, macaddr = 0ull; 3029 i < ETHERADDRL; ++i) { 3030 macaddr <<= 8; 3031 macaddr |= bgep->curr_addr[j].addr[i]; 3032 } 3033 fill += (macaddr >> 16) + (macaddr & 0xffffffff); 3034 bge_reg_put64(bgep, MAC_ADDRESS_REG(j), macaddr); 3035 3036 BGE_DEBUG(("bge_chip_sync($%p) " 3037 "setting MAC address %012llx", 3038 (void *)bgep, macaddr)); 3039 } 3040 #ifdef BGE_IPMI_ASF 3041 } 3042 #endif 3043 /* 3044 * Set random seed of backoff interval 3045 * - Writing zero means no backoff interval 3046 */ 3047 fill = ((fill >> 20) + (fill >> 10) + fill) & 0x3ff; 3048 if (fill == 0) 3049 fill = 1; 3050 bge_reg_put32(bgep, MAC_TX_RANDOM_BACKOFF_REG, fill); 3051 3052 /* 3053 * Set or clear the PROMISCUOUS mode bit 3054 */ 3055 opfn = promisc ? bge_reg_set32 : bge_reg_clr32; 3056 (*opfn)(bgep, RECEIVE_MAC_MODE_REG, RECEIVE_MODE_PROMISCUOUS); 3057 3058 /* 3059 * Sync the rest of the MAC modes too ... 3060 */ 3061 bge_sync_mac_modes(bgep); 3062 3063 /* 3064 * Restart RX/TX MAC engines if required ... 3065 */ 3066 if (bgep->bge_chip_state == BGE_CHIP_RUNNING) { 3067 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 3068 retval = DDI_FAILURE; 3069 #ifdef BGE_IPMI_ASF 3070 if (!bgep->asf_enabled) { 3071 if (!bge_chip_enable_engine(bgep, 3072 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG)) 3073 retval = DDI_FAILURE; 3074 } else { 3075 if (!bge_chip_enable_engine(bgep, 3076 RECEIVE_MAC_MODE_REG, 0)) 3077 retval = DDI_FAILURE; 3078 } 3079 #else 3080 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 3081 RECEIVE_MODE_KEEP_VLAN_TAG)) 3082 retval = DDI_FAILURE; 3083 #endif 3084 } 3085 return (retval); 3086 } 3087 3088 /* 3089 * This array defines the sequence of state machine control registers 3090 * in which the <enable> bit must be cleared to bring the chip to a 3091 * clean stop. Taken from Broadcom document 570X-PG102-R, p116. 3092 */ 3093 static bge_regno_t shutdown_engine_regs[] = { 3094 RECEIVE_MAC_MODE_REG, 3095 RCV_BD_INITIATOR_MODE_REG, 3096 RCV_LIST_PLACEMENT_MODE_REG, 3097 RCV_LIST_SELECTOR_MODE_REG, /* BCM5704 series only */ 3098 RCV_DATA_BD_INITIATOR_MODE_REG, 3099 RCV_DATA_COMPLETION_MODE_REG, 3100 RCV_BD_COMPLETION_MODE_REG, 3101 3102 SEND_BD_SELECTOR_MODE_REG, 3103 SEND_BD_INITIATOR_MODE_REG, 3104 SEND_DATA_INITIATOR_MODE_REG, 3105 READ_DMA_MODE_REG, 3106 SEND_DATA_COMPLETION_MODE_REG, 3107 DMA_COMPLETION_MODE_REG, /* BCM5704 series only */ 3108 SEND_BD_COMPLETION_MODE_REG, 3109 TRANSMIT_MAC_MODE_REG, 3110 3111 HOST_COALESCE_MODE_REG, 3112 WRITE_DMA_MODE_REG, 3113 MBUF_CLUSTER_FREE_MODE_REG, /* BCM5704 series only */ 3114 FTQ_RESET_REG, /* special - see code */ 3115 BUFFER_MANAGER_MODE_REG, /* BCM5704 series only */ 3116 MEMORY_ARBITER_MODE_REG, /* BCM5704 series only */ 3117 BGE_REGNO_NONE /* terminator */ 3118 }; 3119 3120 #ifndef __sparc 3121 static bge_regno_t quiesce_regs[] = { 3122 READ_DMA_MODE_REG, 3123 DMA_COMPLETION_MODE_REG, 3124 WRITE_DMA_MODE_REG, 3125 BGE_REGNO_NONE 3126 }; 3127 3128 void bge_chip_stop_nonblocking(bge_t *bgep); 3129 #pragma no_inline(bge_chip_stop_nonblocking) 3130 3131 /* 3132 * This function is called by bge_quiesce(). We 3133 * turn off all the DMA engines here. 3134 */ 3135 void 3136 bge_chip_stop_nonblocking(bge_t *bgep) 3137 { 3138 bge_regno_t *rbp; 3139 3140 /* 3141 * Flag that no more activity may be initiated 3142 */ 3143 bgep->progress &= ~PROGRESS_READY; 3144 3145 rbp = quiesce_regs; 3146 while (*rbp != BGE_REGNO_NONE) { 3147 (void) bge_chip_disable_engine(bgep, *rbp, 0); 3148 ++rbp; 3149 } 3150 3151 bgep->bge_chip_state = BGE_CHIP_STOPPED; 3152 } 3153 3154 #endif 3155 3156 /* 3157 * bge_chip_stop() -- stop all chip processing 3158 * 3159 * If the <fault> parameter is B_TRUE, we're stopping the chip because 3160 * we've detected a problem internally; otherwise, this is a normal 3161 * (clean) stop (at user request i.e. the last STREAM has been closed). 3162 */ 3163 void bge_chip_stop(bge_t *bgep, boolean_t fault); 3164 #pragma no_inline(bge_chip_stop) 3165 3166 void 3167 bge_chip_stop(bge_t *bgep, boolean_t fault) 3168 { 3169 bge_regno_t regno; 3170 bge_regno_t *rbp; 3171 boolean_t ok; 3172 3173 BGE_TRACE(("bge_chip_stop($%p)", 3174 (void *)bgep)); 3175 3176 ASSERT(mutex_owned(bgep->genlock)); 3177 3178 rbp = shutdown_engine_regs; 3179 /* 3180 * When driver try to shutdown the BCM5705/5788/5721/5751/ 3181 * 5752/5714 and 5715 chipsets,the buffer manager and the mem 3182 * -ory arbiter should not be disabled. 3183 */ 3184 for (ok = B_TRUE; (regno = *rbp) != BGE_REGNO_NONE; ++rbp) { 3185 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3186 ok &= bge_chip_disable_engine(bgep, regno, 0); 3187 else if ((regno != RCV_LIST_SELECTOR_MODE_REG) && 3188 (regno != DMA_COMPLETION_MODE_REG) && 3189 (regno != MBUF_CLUSTER_FREE_MODE_REG)&& 3190 (regno != BUFFER_MANAGER_MODE_REG) && 3191 (regno != MEMORY_ARBITER_MODE_REG)) 3192 ok &= bge_chip_disable_engine(bgep, 3193 regno, 0); 3194 } 3195 3196 if (!ok && !fault) 3197 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 3198 3199 /* 3200 * Finally, disable (all) MAC events & clear the MAC status 3201 */ 3202 bge_reg_put32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 0); 3203 bge_reg_put32(bgep, ETHERNET_MAC_STATUS_REG, ~0); 3204 3205 /* 3206 * if we're stopping the chip because of a detected fault then do 3207 * appropriate actions 3208 */ 3209 if (fault) { 3210 if (bgep->bge_chip_state != BGE_CHIP_FAULT) { 3211 bgep->bge_chip_state = BGE_CHIP_FAULT; 3212 if (!bgep->manual_reset) 3213 ddi_fm_service_impact(bgep->devinfo, 3214 DDI_SERVICE_LOST); 3215 if (bgep->bge_dma_error) { 3216 /* 3217 * need to free buffers in case the fault was 3218 * due to a memory error in a buffer - got to 3219 * do a fair bit of tidying first 3220 */ 3221 if (bgep->progress & PROGRESS_KSTATS) { 3222 bge_fini_kstats(bgep); 3223 bgep->progress &= ~PROGRESS_KSTATS; 3224 } 3225 if (bgep->progress & PROGRESS_INTR) { 3226 bge_intr_disable(bgep); 3227 rw_enter(bgep->errlock, RW_WRITER); 3228 bge_fini_rings(bgep); 3229 rw_exit(bgep->errlock); 3230 bgep->progress &= ~PROGRESS_INTR; 3231 } 3232 if (bgep->progress & PROGRESS_BUFS) { 3233 bge_free_bufs(bgep); 3234 bgep->progress &= ~PROGRESS_BUFS; 3235 } 3236 bgep->bge_dma_error = B_FALSE; 3237 } 3238 } 3239 } else 3240 bgep->bge_chip_state = BGE_CHIP_STOPPED; 3241 } 3242 3243 /* 3244 * Poll for completion of chip's ROM firmware; also, at least on the 3245 * first time through, find and return the hardware MAC address, if any. 3246 */ 3247 static uint64_t bge_poll_firmware(bge_t *bgep); 3248 #pragma no_inline(bge_poll_firmware) 3249 3250 static uint64_t 3251 bge_poll_firmware(bge_t *bgep) 3252 { 3253 uint64_t magic; 3254 uint64_t mac; 3255 uint32_t gen, val; 3256 uint32_t i; 3257 3258 /* 3259 * Step 19: poll for firmware completion (GENCOMM port set 3260 * to the ones complement of T3_MAGIC_NUMBER). 3261 * 3262 * While we're at it, we also read the MAC address register; 3263 * at some stage the firmware will load this with the 3264 * factory-set value. 3265 * 3266 * When both the magic number and the MAC address are set, 3267 * we're done; but we impose a time limit of one second 3268 * (1000*1000us) in case the firmware fails in some fashion 3269 * or the SEEPROM that provides that MAC address isn't fitted. 3270 * 3271 * After the first time through (chip state != INITIAL), we 3272 * don't need the MAC address to be set (we've already got it 3273 * or not, from the first time), so we don't wait for it, but 3274 * we still have to wait for the T3_MAGIC_NUMBER. 3275 * 3276 * Note: the magic number is only a 32-bit quantity, but the NIC 3277 * memory is 64-bit (and big-endian) internally. Addressing the 3278 * GENCOMM word as "the upper half of a 64-bit quantity" makes 3279 * it work correctly on both big- and little-endian hosts. 3280 */ 3281 if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) == 3282 MHCR_CHIP_ASIC_REV_5906) { 3283 for (i = 0; i < 1000; ++i) { 3284 drv_usecwait(1000); 3285 val = bge_reg_get32(bgep, VCPU_STATUS_REG); 3286 if (val & VCPU_INIT_DONE) 3287 break; 3288 } 3289 BGE_DEBUG(("bge_poll_firmware($%p): return after %d loops", 3290 (void *)bgep, i)); 3291 mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0)); 3292 } else { 3293 for (i = 0; i < 1000; ++i) { 3294 drv_usecwait(1000); 3295 gen = bge_nic_get64(bgep, NIC_MEM_GENCOMM) >> 32; 3296 if (i == 0 && DEVICE_5704_SERIES_CHIPSETS(bgep)) 3297 drv_usecwait(100000); 3298 mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0)); 3299 #ifdef BGE_IPMI_ASF 3300 if (!bgep->asf_enabled) { 3301 #endif 3302 if (gen != ~T3_MAGIC_NUMBER) 3303 continue; 3304 #ifdef BGE_IPMI_ASF 3305 } 3306 #endif 3307 if (mac != 0ULL) 3308 break; 3309 if (bgep->bge_chip_state != BGE_CHIP_INITIAL) 3310 break; 3311 } 3312 } 3313 3314 magic = bge_nic_get64(bgep, NIC_MEM_GENCOMM); 3315 BGE_DEBUG(("bge_poll_firmware($%p): PXE magic 0x%x after %d loops", 3316 (void *)bgep, gen, i)); 3317 BGE_DEBUG(("bge_poll_firmware: MAC %016llx, GENCOMM %016llx", 3318 mac, magic)); 3319 3320 return (mac); 3321 } 3322 3323 /* 3324 * Maximum times of trying to get the NVRAM access lock 3325 * by calling bge_nvmem_acquire() 3326 */ 3327 #define MAX_TRY_NVMEM_ACQUIRE 10000 3328 3329 #ifdef BGE_IPMI_ASF 3330 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode); 3331 #else 3332 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma); 3333 #endif 3334 #pragma no_inline(bge_chip_reset) 3335 3336 int 3337 #ifdef BGE_IPMI_ASF 3338 bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode) 3339 #else 3340 bge_chip_reset(bge_t *bgep, boolean_t enable_dma) 3341 #endif 3342 { 3343 chip_id_t chipid; 3344 uint64_t mac; 3345 uint64_t magic; 3346 uint32_t modeflags; 3347 uint32_t mhcr; 3348 uint32_t sx0; 3349 uint32_t i, tries; 3350 #ifdef BGE_IPMI_ASF 3351 uint32_t mailbox; 3352 #endif 3353 int retval = DDI_SUCCESS; 3354 3355 BGE_TRACE(("bge_chip_reset($%p, %d)", 3356 (void *)bgep, enable_dma)); 3357 3358 ASSERT(mutex_owned(bgep->genlock)); 3359 3360 BGE_DEBUG(("bge_chip_reset($%p, %d): current state is %d", 3361 (void *)bgep, enable_dma, bgep->bge_chip_state)); 3362 3363 /* 3364 * Do we need to stop the chip cleanly before resetting? 3365 */ 3366 switch (bgep->bge_chip_state) { 3367 default: 3368 _NOTE(NOTREACHED) 3369 return (DDI_FAILURE); 3370 3371 case BGE_CHIP_INITIAL: 3372 case BGE_CHIP_STOPPED: 3373 case BGE_CHIP_RESET: 3374 break; 3375 3376 case BGE_CHIP_RUNNING: 3377 case BGE_CHIP_ERROR: 3378 case BGE_CHIP_FAULT: 3379 bge_chip_stop(bgep, B_FALSE); 3380 break; 3381 } 3382 3383 #ifdef BGE_IPMI_ASF 3384 if (bgep->asf_enabled) { 3385 #ifdef __sparc 3386 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 3387 MHCR_ENABLE_TAGGED_STATUS_MODE | 3388 MHCR_MASK_INTERRUPT_MODE | 3389 MHCR_MASK_PCI_INT_OUTPUT | 3390 MHCR_CLEAR_INTERRUPT_INTA | 3391 MHCR_ENABLE_ENDIAN_WORD_SWAP | 3392 MHCR_ENABLE_ENDIAN_BYTE_SWAP; 3393 if (DEVICE_5717_SERIES_CHIPSETS(bgep)) 3394 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, 3395 0); 3396 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr); 3397 bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG, 3398 bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG) | 3399 MEMORY_ARBITER_ENABLE); 3400 #endif 3401 if (asf_mode == ASF_MODE_INIT) { 3402 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 3403 } else if (asf_mode == ASF_MODE_SHUTDOWN) { 3404 bge_asf_pre_reset_operations(bgep, BGE_SHUTDOWN_RESET); 3405 } 3406 } 3407 #endif 3408 /* 3409 * Adapted from Broadcom document 570X-PG102-R, pp 102-116. 3410 * Updated to reflect Broadcom document 570X-PG104-R, pp 146-159. 3411 * 3412 * Before reset Core clock,it is 3413 * also required to initialize the Memory Arbiter as specified in step9 3414 * and Misc Host Control Register as specified in step-13 3415 * Step 4-5: reset Core clock & wait for completion 3416 * Steps 6-8: are done by bge_chip_cfg_init() 3417 * put the T3_MAGIC_NUMBER into the GENCOMM port before reset 3418 */ 3419 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 3420 retval = DDI_FAILURE; 3421 3422 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 3423 MHCR_ENABLE_TAGGED_STATUS_MODE | 3424 MHCR_MASK_INTERRUPT_MODE | 3425 MHCR_MASK_PCI_INT_OUTPUT | 3426 MHCR_CLEAR_INTERRUPT_INTA; 3427 #ifdef _BIG_ENDIAN 3428 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 3429 #endif /* _BIG_ENDIAN */ 3430 if (DEVICE_5717_SERIES_CHIPSETS(bgep)) 3431 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, 0); 3432 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr); 3433 #ifdef BGE_IPMI_ASF 3434 if (bgep->asf_enabled) 3435 bgep->asf_wordswapped = B_FALSE; 3436 #endif 3437 /* 3438 * NVRAM Corruption Workaround 3439 */ 3440 for (tries = 0; tries < MAX_TRY_NVMEM_ACQUIRE; tries++) 3441 if (bge_nvmem_acquire(bgep) != EAGAIN) 3442 break; 3443 if (tries >= MAX_TRY_NVMEM_ACQUIRE) 3444 BGE_DEBUG(("%s: fail to acquire nvram lock", 3445 bgep->ifname)); 3446 3447 #ifdef BGE_IPMI_ASF 3448 if (!bgep->asf_enabled) { 3449 #endif 3450 magic = (uint64_t)T3_MAGIC_NUMBER << 32; 3451 bge_nic_put64(bgep, NIC_MEM_GENCOMM, magic); 3452 #ifdef BGE_IPMI_ASF 3453 } 3454 #endif 3455 3456 if (!bge_chip_reset_engine(bgep, MISC_CONFIG_REG)) 3457 retval = DDI_FAILURE; 3458 bge_chip_cfg_init(bgep, &chipid, enable_dma); 3459 3460 /* 3461 * Step 8a: This may belong elsewhere, but BCM5721 needs 3462 * a bit set to avoid a fifo overflow/underflow bug. 3463 */ 3464 if ((bgep->chipid.chip_label == 5721) || 3465 (bgep->chipid.chip_label == 5751) || 3466 (bgep->chipid.chip_label == 5752) || 3467 (bgep->chipid.chip_label == 5755) || 3468 (bgep->chipid.chip_label == 5756) || 3469 (bgep->chipid.chip_label == 5789) || 3470 (bgep->chipid.chip_label == 5906)) 3471 bge_reg_set32(bgep, TLP_CONTROL_REG, TLP_DATA_FIFO_PROTECT); 3472 3473 3474 /* 3475 * Step 9: enable MAC memory arbiter,bit30 and bit31 of 5714/5715 should 3476 * not be changed. 3477 */ 3478 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 3479 retval = DDI_FAILURE; 3480 3481 /* 3482 * Steps 10-11: configure PIO endianness options and 3483 * enable indirect register access -- already done 3484 * Steps 12-13: enable writing to the PCI state & clock 3485 * control registers -- not required; we aren't going to 3486 * use those features. 3487 * Steps 14-15: Configure DMA endianness options. See 3488 * the comments on the setting of the MHCR above. 3489 */ 3490 #ifdef _BIG_ENDIAN 3491 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME | 3492 MODE_WORD_SWAP_NONFRAME | MODE_BYTE_SWAP_NONFRAME; 3493 #else 3494 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME; 3495 #endif /* _BIG_ENDIAN */ 3496 #ifdef BGE_IPMI_ASF 3497 if (bgep->asf_enabled) 3498 modeflags |= MODE_HOST_STACK_UP; 3499 #endif 3500 bge_reg_put32(bgep, MODE_CONTROL_REG, modeflags); 3501 3502 #ifdef BGE_IPMI_ASF 3503 if (bgep->asf_enabled) { 3504 #ifdef __sparc 3505 bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG, 3506 MEMORY_ARBITER_ENABLE | 3507 bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG)); 3508 #endif 3509 3510 #ifdef BGE_NETCONSOLE 3511 if (!bgep->asf_newhandshake) { 3512 if ((asf_mode == ASF_MODE_INIT) || 3513 (asf_mode == ASF_MODE_POST_INIT)) { 3514 bge_asf_post_reset_old_mode(bgep, 3515 BGE_INIT_RESET); 3516 } else { 3517 bge_asf_post_reset_old_mode(bgep, 3518 BGE_SHUTDOWN_RESET); 3519 } 3520 } 3521 #endif 3522 3523 /* Wait for NVRAM init */ 3524 i = 0; 3525 drv_usecwait(5000); 3526 mailbox = bge_nic_get32(bgep, BGE_FIRMWARE_MAILBOX); 3527 3528 while ((mailbox != (uint32_t) 3529 ~BGE_MAGIC_NUM_FIRMWARE_INIT_DONE) && 3530 (i < 10000)) { 3531 drv_usecwait(100); 3532 mailbox = bge_nic_get32(bgep, 3533 BGE_FIRMWARE_MAILBOX); 3534 i++; 3535 } 3536 3537 #ifndef BGE_NETCONSOLE 3538 if (!bgep->asf_newhandshake) { 3539 if ((asf_mode == ASF_MODE_INIT) || 3540 (asf_mode == ASF_MODE_POST_INIT)) { 3541 3542 bge_asf_post_reset_old_mode(bgep, 3543 BGE_INIT_RESET); 3544 } else { 3545 bge_asf_post_reset_old_mode(bgep, 3546 BGE_SHUTDOWN_RESET); 3547 } 3548 } 3549 #endif 3550 } 3551 #endif 3552 /* 3553 * Steps 16-17: poll for firmware completion 3554 */ 3555 mac = bge_poll_firmware(bgep); 3556 3557 /* 3558 * Step 18: enable external memory -- doesn't apply. 3559 * 3560 * However we take the opportunity to set the MLCR anyway, as 3561 * this register also controls the SEEPROM auto-access method 3562 * which we may want to use later ... 3563 * 3564 * The proper value here depends on the way the chip is wired 3565 * into the circuit board, as this register *also* controls which 3566 * of the "Miscellaneous I/O" pins are driven as outputs and the 3567 * values driven onto those pins! 3568 * 3569 * See also step 74 in the PRM ... 3570 */ 3571 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, 3572 bgep->chipid.bge_mlcr_default); 3573 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 3574 3575 /* 3576 * Step 20: clear the Ethernet MAC mode register 3577 */ 3578 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, 0); 3579 3580 /* 3581 * Step 21: restore cache-line-size, latency timer, and 3582 * subsystem ID registers to their original values (not 3583 * those read into the local structure <chipid>, 'cos 3584 * that was after they were cleared by the RESET). 3585 * 3586 * Note: the Subsystem Vendor/Device ID registers are not 3587 * directly writable in config space, so we use the shadow 3588 * copy in "Page Zero" of register space to restore them 3589 * both in one go ... 3590 */ 3591 pci_config_put8(bgep->cfg_handle, PCI_CONF_CACHE_LINESZ, 3592 bgep->chipid.clsize); 3593 pci_config_put8(bgep->cfg_handle, PCI_CONF_LATENCY_TIMER, 3594 bgep->chipid.latency); 3595 bge_reg_put32(bgep, PCI_CONF_SUBVENID, 3596 (bgep->chipid.subdev << 16) | bgep->chipid.subven); 3597 3598 /* 3599 * The SEND INDEX registers should be reset to zero by the 3600 * global chip reset; if they're not, there'll be trouble 3601 * later on. 3602 */ 3603 sx0 = bge_reg_get32(bgep, NIC_DIAG_SEND_INDEX_REG(0)); 3604 if (sx0 != 0) { 3605 BGE_REPORT((bgep, "SEND INDEX - device didn't RESET")); 3606 bge_fm_ereport(bgep, DDI_FM_DEVICE_INVAL_STATE); 3607 retval = DDI_FAILURE; 3608 } 3609 3610 /* Enable MSI code */ 3611 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 3612 bge_reg_set32(bgep, MSI_MODE_REG, 3613 MSI_PRI_HIGHEST|MSI_MSI_ENABLE|MSI_ERROR_ATTENTION); 3614 3615 /* 3616 * On the first time through, save the factory-set MAC address 3617 * (if any). If bge_poll_firmware() above didn't return one 3618 * (from a chip register) consider looking in the attached NV 3619 * memory device, if any. Once we have it, we save it in both 3620 * register-image (64-bit) and byte-array forms. All-zero and 3621 * all-one addresses are not valid, and we refuse to stash those. 3622 */ 3623 if (bgep->bge_chip_state == BGE_CHIP_INITIAL) { 3624 if (mac == 0ULL) 3625 mac = bge_get_nvmac(bgep); 3626 if (mac != 0ULL && mac != ~0ULL) { 3627 bgep->chipid.hw_mac_addr = mac; 3628 for (i = ETHERADDRL; i-- != 0; ) { 3629 bgep->chipid.vendor_addr.addr[i] = (uchar_t)mac; 3630 mac >>= 8; 3631 } 3632 bgep->chipid.vendor_addr.set = B_TRUE; 3633 } 3634 } 3635 3636 #ifdef BGE_IPMI_ASF 3637 if (bgep->asf_enabled && bgep->asf_newhandshake) { 3638 if (asf_mode != ASF_MODE_NONE) { 3639 if ((asf_mode == ASF_MODE_INIT) || 3640 (asf_mode == ASF_MODE_POST_INIT)) { 3641 3642 bge_asf_post_reset_new_mode(bgep, 3643 BGE_INIT_RESET); 3644 } else { 3645 bge_asf_post_reset_new_mode(bgep, 3646 BGE_SHUTDOWN_RESET); 3647 } 3648 } 3649 } 3650 #endif 3651 3652 /* 3653 * Record the new state 3654 */ 3655 bgep->chip_resets += 1; 3656 bgep->bge_chip_state = BGE_CHIP_RESET; 3657 return (retval); 3658 } 3659 3660 /* 3661 * bge_chip_start() -- start the chip transmitting and/or receiving, 3662 * including enabling interrupts 3663 */ 3664 int bge_chip_start(bge_t *bgep, boolean_t reset_phys); 3665 #pragma no_inline(bge_chip_start) 3666 3667 void 3668 bge_chip_coalesce_update(bge_t *bgep) 3669 { 3670 bge_reg_put32(bgep, SEND_COALESCE_MAX_BD_REG, 3671 bgep->chipid.tx_count_norm); 3672 bge_reg_put32(bgep, SEND_COALESCE_TICKS_REG, 3673 bgep->chipid.tx_ticks_norm); 3674 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, 3675 bgep->chipid.rx_count_norm); 3676 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, 3677 bgep->chipid.rx_ticks_norm); 3678 } 3679 3680 int 3681 bge_chip_start(bge_t *bgep, boolean_t reset_phys) 3682 { 3683 uint32_t coalmode; 3684 uint32_t ledctl; 3685 uint32_t mtu; 3686 uint32_t maxring; 3687 uint32_t stats_mask; 3688 uint32_t dma_wrprio; 3689 uint64_t ring; 3690 uint32_t regval; 3691 int retval = DDI_SUCCESS; 3692 3693 BGE_TRACE(("bge_chip_start($%p)", 3694 (void *)bgep)); 3695 3696 ASSERT(mutex_owned(bgep->genlock)); 3697 ASSERT(bgep->bge_chip_state == BGE_CHIP_RESET); 3698 3699 /* 3700 * Taken from Broadcom document 570X-PG102-R, pp 102-116. 3701 * The document specifies 95 separate steps to fully 3702 * initialise the chip!!!! 3703 * 3704 * The reset code above has already got us as far as step 3705 * 21, so we continue with ... 3706 * 3707 * Step 22: clear the MAC statistics block 3708 * (0x0300-0x0aff in NIC-local memory) 3709 */ 3710 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 3711 bge_nic_zero(bgep, NIC_MEM_STATISTICS, 3712 NIC_MEM_STATISTICS_SIZE); 3713 3714 /* 3715 * Step 23: clear the status block (in host memory) 3716 */ 3717 DMA_ZERO(bgep->status_block); 3718 3719 /* 3720 * Step 24: set DMA read/write control register 3721 */ 3722 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_PDRWCR, 3723 bgep->chipid.bge_dma_rwctrl); 3724 3725 /* 3726 * Step 25: Configure DMA endianness -- already done (16/17) 3727 * Step 26: Configure Host-Based Send Rings 3728 * Step 27: Indicate Host Stack Up 3729 */ 3730 bge_reg_set32(bgep, MODE_CONTROL_REG, 3731 MODE_HOST_SEND_BDS | 3732 MODE_HOST_STACK_UP); 3733 3734 /* 3735 * Step 28: Configure checksum options: 3736 * Solaris supports the hardware default checksum options. 3737 * 3738 * Workaround for Incorrect pseudo-header checksum calculation. 3739 */ 3740 if (bgep->chipid.flags & CHIP_FLAG_PARTIAL_CSUM) 3741 bge_reg_set32(bgep, MODE_CONTROL_REG, 3742 MODE_SEND_NO_PSEUDO_HDR_CSUM); 3743 3744 /* 3745 * Step 29: configure Timer Prescaler. The value is always the 3746 * same: the Core Clock frequency in MHz (66), minus 1, shifted 3747 * into bits 7-1. Don't set bit 0, 'cos that's the RESET bit 3748 * for the whole chip! 3749 */ 3750 regval = bge_reg_get32(bgep, MISC_CONFIG_REG); 3751 regval = (regval & 0xffffff00) | MISC_CONFIG_DEFAULT; 3752 bge_reg_put32(bgep, MISC_CONFIG_REG, regval); 3753 3754 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) { 3755 drv_usecwait(40); 3756 /* put PHY into ready state */ 3757 bge_reg_clr32(bgep, MISC_CONFIG_REG, MISC_CONFIG_EPHY_IDDQ); 3758 (void) bge_reg_get32(bgep, MISC_CONFIG_REG); /* flush */ 3759 drv_usecwait(40); 3760 } 3761 3762 /* 3763 * Steps 30-31: Configure MAC local memory pool & DMA pool registers 3764 * 3765 * If the mbuf_length is specified as 0, we just leave these at 3766 * their hardware defaults, rather than explicitly setting them. 3767 * As the Broadcom HRM,driver better not change the parameters 3768 * when the chipsets is 5705/5788/5721/5751/5714 and 5715. 3769 */ 3770 if ((bgep->chipid.mbuf_length != 0) && 3771 (DEVICE_5704_SERIES_CHIPSETS(bgep))) { 3772 bge_reg_put32(bgep, MBUF_POOL_BASE_REG, 3773 bgep->chipid.mbuf_base); 3774 bge_reg_put32(bgep, MBUF_POOL_LENGTH_REG, 3775 bgep->chipid.mbuf_length); 3776 bge_reg_put32(bgep, DMAD_POOL_BASE_REG, 3777 DMAD_POOL_BASE_DEFAULT); 3778 bge_reg_put32(bgep, DMAD_POOL_LENGTH_REG, 3779 DMAD_POOL_LENGTH_DEFAULT); 3780 } 3781 3782 /* 3783 * Step 32: configure MAC memory pool watermarks 3784 */ 3785 bge_reg_put32(bgep, RDMA_MBUF_LOWAT_REG, 3786 bgep->chipid.mbuf_lo_water_rdma); 3787 bge_reg_put32(bgep, MAC_RX_MBUF_LOWAT_REG, 3788 bgep->chipid.mbuf_lo_water_rmac); 3789 bge_reg_put32(bgep, MBUF_HIWAT_REG, 3790 bgep->chipid.mbuf_hi_water); 3791 3792 /* 3793 * Step 33: configure DMA resource watermarks 3794 */ 3795 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3796 bge_reg_put32(bgep, DMAD_POOL_LOWAT_REG, 3797 bge_dmad_lo_water); 3798 bge_reg_put32(bgep, DMAD_POOL_HIWAT_REG, 3799 bge_dmad_hi_water); 3800 } 3801 bge_reg_put32(bgep, LOWAT_MAX_RECV_FRAMES_REG, bge_lowat_recv_frames); 3802 3803 /* 3804 * Steps 34-36: enable buffer manager & internal h/w queues 3805 */ 3806 if (!bge_chip_enable_engine(bgep, BUFFER_MANAGER_MODE_REG, 3807 STATE_MACHINE_ATTN_ENABLE_BIT)) 3808 retval = DDI_FAILURE; 3809 if (!bge_chip_enable_engine(bgep, FTQ_RESET_REG, 0)) 3810 retval = DDI_FAILURE; 3811 3812 /* 3813 * Steps 37-39: initialise Receive Buffer (Producer) RCBs 3814 */ 3815 if (DEVICE_5717_SERIES_CHIPSETS(bgep)) { 3816 buff_ring_t *brp = &bgep->buff[BGE_STD_BUFF_RING]; 3817 bge_reg_put64(bgep, STD_RCV_BD_RING_RCB_REG, 3818 brp->desc.cookie.dmac_laddress); 3819 bge_reg_put32(bgep, STD_RCV_BD_RING_RCB_REG + 8, 3820 (brp->desc.nslots) << 16 | brp->buf[0].size << 2); 3821 bge_reg_put32(bgep, STD_RCV_BD_RING_RCB_REG + 0xc, 3822 NIC_MEM_SHADOW_BUFF_STD_5717); 3823 } else 3824 bge_reg_putrcb(bgep, STD_RCV_BD_RING_RCB_REG, 3825 &bgep->buff[BGE_STD_BUFF_RING].hw_rcb); 3826 3827 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3828 bge_reg_putrcb(bgep, JUMBO_RCV_BD_RING_RCB_REG, 3829 &bgep->buff[BGE_JUMBO_BUFF_RING].hw_rcb); 3830 bge_reg_putrcb(bgep, MINI_RCV_BD_RING_RCB_REG, 3831 &bgep->buff[BGE_MINI_BUFF_RING].hw_rcb); 3832 } 3833 3834 /* 3835 * Step 40: set Receive Buffer Descriptor Ring replenish thresholds 3836 */ 3837 bge_reg_put32(bgep, STD_RCV_BD_REPLENISH_REG, bge_replenish_std); 3838 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3839 bge_reg_put32(bgep, JUMBO_RCV_BD_REPLENISH_REG, 3840 bge_replenish_jumbo); 3841 bge_reg_put32(bgep, MINI_RCV_BD_REPLENISH_REG, 3842 bge_replenish_mini); 3843 } 3844 3845 /* 3846 * Steps 41-43: clear Send Ring Producer Indices and initialise 3847 * Send Producer Rings (0x0100-0x01ff in NIC-local memory) 3848 */ 3849 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3850 maxring = BGE_SEND_RINGS_MAX; 3851 else 3852 maxring = BGE_SEND_RINGS_MAX_5705; 3853 for (ring = 0; ring < maxring; ++ring) { 3854 bge_mbx_put(bgep, SEND_RING_HOST_INDEX_REG(ring), 0); 3855 bge_mbx_put(bgep, SEND_RING_NIC_INDEX_REG(ring), 0); 3856 bge_nic_putrcb(bgep, NIC_MEM_SEND_RING(ring), 3857 &bgep->send[ring].hw_rcb); 3858 } 3859 3860 /* 3861 * Steps 44-45: initialise Receive Return Rings 3862 * (0x0200-0x02ff in NIC-local memory) 3863 */ 3864 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3865 maxring = BGE_RECV_RINGS_MAX; 3866 else 3867 maxring = BGE_RECV_RINGS_MAX_5705; 3868 for (ring = 0; ring < maxring; ++ring) 3869 bge_nic_putrcb(bgep, NIC_MEM_RECV_RING(ring), 3870 &bgep->recv[ring].hw_rcb); 3871 3872 /* 3873 * Step 46: initialise Receive Buffer (Producer) Ring indexes 3874 */ 3875 bge_mbx_put(bgep, RECV_STD_PROD_INDEX_REG, 0); 3876 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3877 bge_mbx_put(bgep, RECV_JUMBO_PROD_INDEX_REG, 0); 3878 bge_mbx_put(bgep, RECV_MINI_PROD_INDEX_REG, 0); 3879 } 3880 /* 3881 * Step 47: configure the MAC unicast address 3882 * Step 48: configure the random backoff seed 3883 * Step 96: set up multicast filters 3884 */ 3885 #ifdef BGE_IPMI_ASF 3886 if (bge_chip_sync(bgep, B_FALSE) == DDI_FAILURE) 3887 #else 3888 if (bge_chip_sync(bgep) == DDI_FAILURE) 3889 #endif 3890 retval = DDI_FAILURE; 3891 3892 /* 3893 * Step 49: configure the MTU 3894 */ 3895 mtu = bgep->chipid.ethmax_size+ETHERFCSL+VLAN_TAGSZ; 3896 bge_reg_put32(bgep, MAC_RX_MTU_SIZE_REG, mtu); 3897 3898 /* 3899 * Step 50: configure the IPG et al 3900 */ 3901 bge_reg_put32(bgep, MAC_TX_LENGTHS_REG, MAC_TX_LENGTHS_DEFAULT); 3902 3903 /* 3904 * Step 51: configure the default Rx Return Ring 3905 */ 3906 bge_reg_put32(bgep, RCV_RULES_CONFIG_REG, RCV_RULES_CONFIG_DEFAULT); 3907 3908 /* 3909 * Steps 52-54: configure Receive List Placement, 3910 * and enable Receive List Placement Statistics 3911 */ 3912 bge_reg_put32(bgep, RCV_LP_CONFIG_REG, 3913 RCV_LP_CONFIG(bgep->chipid.rx_rings)); 3914 switch (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev)) { 3915 case MHCR_CHIP_ASIC_REV_5700: 3916 case MHCR_CHIP_ASIC_REV_5701: 3917 case MHCR_CHIP_ASIC_REV_5703: 3918 case MHCR_CHIP_ASIC_REV_5704: 3919 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, ~0); 3920 break; 3921 case MHCR_CHIP_ASIC_REV_5705: 3922 break; 3923 default: 3924 stats_mask = bge_reg_get32(bgep, RCV_LP_STATS_ENABLE_MASK_REG); 3925 stats_mask &= ~RCV_LP_STATS_DISABLE_MACTQ; 3926 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, stats_mask); 3927 break; 3928 } 3929 bge_reg_set32(bgep, RCV_LP_STATS_CONTROL_REG, RCV_LP_STATS_ENABLE); 3930 3931 if (bgep->chipid.rx_rings > 1) 3932 bge_init_recv_rule(bgep); 3933 3934 /* 3935 * Steps 55-56: enable Send Data Initiator Statistics 3936 */ 3937 bge_reg_put32(bgep, SEND_INIT_STATS_ENABLE_MASK_REG, ~0); 3938 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3939 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 3940 SEND_INIT_STATS_ENABLE | SEND_INIT_STATS_FASTER); 3941 } else { 3942 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 3943 SEND_INIT_STATS_ENABLE); 3944 } 3945 /* 3946 * Steps 57-58: stop (?) the Host Coalescing Engine 3947 */ 3948 if (!bge_chip_disable_engine(bgep, HOST_COALESCE_MODE_REG, ~0)) 3949 retval = DDI_FAILURE; 3950 3951 /* 3952 * Steps 59-62: initialise Host Coalescing parameters 3953 */ 3954 bge_chip_coalesce_update(bgep); 3955 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3956 bge_reg_put32(bgep, SEND_COALESCE_INT_BD_REG, 3957 bge_tx_count_intr); 3958 bge_reg_put32(bgep, SEND_COALESCE_INT_TICKS_REG, 3959 bge_tx_ticks_intr); 3960 bge_reg_put32(bgep, RCV_COALESCE_INT_BD_REG, 3961 bge_rx_count_intr); 3962 bge_reg_put32(bgep, RCV_COALESCE_INT_TICKS_REG, 3963 bge_rx_ticks_intr); 3964 } 3965 3966 /* 3967 * Steps 63-64: initialise status block & statistics 3968 * host memory addresses 3969 * The statistic block does not exist in some chipsets 3970 * Step 65: initialise Statistics Coalescing Tick Counter 3971 */ 3972 bge_reg_put64(bgep, STATUS_BLOCK_HOST_ADDR_REG, 3973 bgep->status_block.cookie.dmac_laddress); 3974 3975 /* 3976 * Steps 66-67: initialise status block & statistics 3977 * NIC-local memory addresses 3978 */ 3979 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3980 bge_reg_put64(bgep, STATISTICS_HOST_ADDR_REG, 3981 bgep->statistics.cookie.dmac_laddress); 3982 bge_reg_put32(bgep, STATISTICS_TICKS_REG, 3983 STATISTICS_TICKS_DEFAULT); 3984 bge_reg_put32(bgep, STATUS_BLOCK_BASE_ADDR_REG, 3985 NIC_MEM_STATUS_BLOCK); 3986 bge_reg_put32(bgep, STATISTICS_BASE_ADDR_REG, 3987 NIC_MEM_STATISTICS); 3988 } 3989 3990 /* 3991 * Steps 68-71: start the Host Coalescing Engine, the Receive BD 3992 * Completion Engine, the Receive List Placement Engine, and the 3993 * Receive List selector.Pay attention:0x3400 is not exist in BCM5714 3994 * and BCM5715. 3995 */ 3996 if (bgep->chipid.tx_rings <= COALESCE_64_BYTE_RINGS && 3997 bgep->chipid.rx_rings <= COALESCE_64_BYTE_RINGS) 3998 coalmode = COALESCE_64_BYTE_STATUS; 3999 else 4000 coalmode = 0; 4001 if (DEVICE_5717_SERIES_CHIPSETS(bgep)) 4002 coalmode = COALESCE_CLR_TICKS_RX; 4003 if (!bge_chip_enable_engine(bgep, HOST_COALESCE_MODE_REG, coalmode)) 4004 retval = DDI_FAILURE; 4005 if (!bge_chip_enable_engine(bgep, RCV_BD_COMPLETION_MODE_REG, 4006 STATE_MACHINE_ATTN_ENABLE_BIT)) 4007 retval = DDI_FAILURE; 4008 if (!bge_chip_enable_engine(bgep, RCV_LIST_PLACEMENT_MODE_REG, 0)) 4009 retval = DDI_FAILURE; 4010 4011 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4012 if (!bge_chip_enable_engine(bgep, RCV_LIST_SELECTOR_MODE_REG, 4013 STATE_MACHINE_ATTN_ENABLE_BIT)) 4014 retval = DDI_FAILURE; 4015 4016 /* 4017 * Step 72: Enable MAC DMA engines 4018 * Step 73: Clear & enable MAC statistics 4019 */ 4020 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 4021 ETHERNET_MODE_ENABLE_FHDE | 4022 ETHERNET_MODE_ENABLE_RDE | 4023 ETHERNET_MODE_ENABLE_TDE); 4024 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 4025 ETHERNET_MODE_ENABLE_TX_STATS | 4026 ETHERNET_MODE_ENABLE_RX_STATS | 4027 ETHERNET_MODE_CLEAR_TX_STATS | 4028 ETHERNET_MODE_CLEAR_RX_STATS); 4029 4030 /* 4031 * Step 74: configure the MLCR (Miscellaneous Local Control 4032 * Register); not required, as we set up the MLCR in step 10 4033 * (part of the reset code) above. 4034 * 4035 * Step 75: clear Interrupt Mailbox 0 4036 */ 4037 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 0); 4038 4039 /* 4040 * Steps 76-87: Gentlemen, start your engines ... 4041 * 4042 * Enable the DMA Completion Engine, the Write DMA Engine, 4043 * the Read DMA Engine, Receive Data Completion Engine, 4044 * the MBuf Cluster Free Engine, the Send Data Completion Engine, 4045 * the Send BD Completion Engine, the Receive BD Initiator Engine, 4046 * the Receive Data Initiator Engine, the Send Data Initiator Engine, 4047 * the Send BD Initiator Engine, and the Send BD Selector Engine. 4048 * 4049 * Beware exhaust fumes? 4050 */ 4051 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4052 if (!bge_chip_enable_engine(bgep, DMA_COMPLETION_MODE_REG, 0)) 4053 retval = DDI_FAILURE; 4054 dma_wrprio = (bge_dma_wrprio << DMA_PRIORITY_SHIFT) | 4055 ALL_DMA_ATTN_BITS; 4056 if ((MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) == 4057 MHCR_CHIP_ASIC_REV_5755) || 4058 (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) == 4059 MHCR_CHIP_ASIC_REV_5723) || 4060 (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) == 4061 MHCR_CHIP_ASIC_REV_5906)) { 4062 dma_wrprio |= DMA_STATUS_TAG_FIX_CQ12384; 4063 } 4064 if (!bge_chip_enable_engine(bgep, WRITE_DMA_MODE_REG, 4065 dma_wrprio)) 4066 retval = DDI_FAILURE; 4067 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || 4068 DEVICE_5717_SERIES_CHIPSETS(bgep)) 4069 bge_dma_rdprio = 0; 4070 if (!bge_chip_enable_engine(bgep, READ_DMA_MODE_REG, 4071 (bge_dma_rdprio << DMA_PRIORITY_SHIFT) | ALL_DMA_ATTN_BITS)) 4072 retval = DDI_FAILURE; 4073 if (!bge_chip_enable_engine(bgep, RCV_DATA_COMPLETION_MODE_REG, 4074 STATE_MACHINE_ATTN_ENABLE_BIT)) 4075 retval = DDI_FAILURE; 4076 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4077 if (!bge_chip_enable_engine(bgep, 4078 MBUF_CLUSTER_FREE_MODE_REG, 0)) 4079 retval = DDI_FAILURE; 4080 if (!bge_chip_enable_engine(bgep, SEND_DATA_COMPLETION_MODE_REG, 0)) 4081 retval = DDI_FAILURE; 4082 if (!bge_chip_enable_engine(bgep, SEND_BD_COMPLETION_MODE_REG, 4083 STATE_MACHINE_ATTN_ENABLE_BIT)) 4084 retval = DDI_FAILURE; 4085 if (!bge_chip_enable_engine(bgep, RCV_BD_INITIATOR_MODE_REG, 4086 RCV_BD_DISABLED_RING_ATTN)) 4087 retval = DDI_FAILURE; 4088 if (!bge_chip_enable_engine(bgep, RCV_DATA_BD_INITIATOR_MODE_REG, 4089 RCV_DATA_BD_ILL_RING_ATTN)) 4090 retval = DDI_FAILURE; 4091 if (!bge_chip_enable_engine(bgep, SEND_DATA_INITIATOR_MODE_REG, 0)) 4092 retval = DDI_FAILURE; 4093 if (!bge_chip_enable_engine(bgep, SEND_BD_INITIATOR_MODE_REG, 4094 STATE_MACHINE_ATTN_ENABLE_BIT)) 4095 retval = DDI_FAILURE; 4096 if (!bge_chip_enable_engine(bgep, SEND_BD_SELECTOR_MODE_REG, 4097 STATE_MACHINE_ATTN_ENABLE_BIT)) 4098 retval = DDI_FAILURE; 4099 4100 /* 4101 * Step 88: download firmware -- doesn't apply 4102 * Steps 89-90: enable Transmit & Receive MAC Engines 4103 */ 4104 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 4105 retval = DDI_FAILURE; 4106 #ifdef BGE_IPMI_ASF 4107 if (!bgep->asf_enabled) { 4108 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 4109 RECEIVE_MODE_KEEP_VLAN_TAG)) 4110 retval = DDI_FAILURE; 4111 } else { 4112 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 0)) 4113 retval = DDI_FAILURE; 4114 } 4115 #else 4116 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 4117 RECEIVE_MODE_KEEP_VLAN_TAG)) 4118 retval = DDI_FAILURE; 4119 #endif 4120 4121 /* 4122 * Step 91: disable auto-polling of PHY status 4123 */ 4124 bge_reg_put32(bgep, MI_MODE_REG, MI_MODE_DEFAULT); 4125 4126 /* 4127 * Step 92: configure D0 power state (not required) 4128 * Step 93: initialise LED control register () 4129 */ 4130 ledctl = LED_CONTROL_DEFAULT; 4131 switch (bgep->chipid.device) { 4132 case DEVICE_ID_5700: 4133 case DEVICE_ID_5700x: 4134 case DEVICE_ID_5701: 4135 /* 4136 * Switch to 5700 (MAC) mode on these older chips 4137 */ 4138 ledctl &= ~LED_CONTROL_LED_MODE_MASK; 4139 ledctl |= LED_CONTROL_LED_MODE_5700; 4140 break; 4141 4142 default: 4143 break; 4144 } 4145 bge_reg_put32(bgep, ETHERNET_MAC_LED_CONTROL_REG, ledctl); 4146 4147 /* 4148 * Step 94: activate link 4149 */ 4150 bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK); 4151 4152 /* 4153 * Step 95: set up physical layer (PHY/SerDes) 4154 * restart autoneg (if required) 4155 */ 4156 if (reset_phys) 4157 if (bge_phys_update(bgep) == DDI_FAILURE) 4158 retval = DDI_FAILURE; 4159 4160 /* 4161 * Extra step (DSG): hand over all the Receive Buffers to the chip 4162 */ 4163 for (ring = 0; ring < BGE_BUFF_RINGS_USED; ++ring) 4164 bge_mbx_put(bgep, bgep->buff[ring].chip_mbx_reg, 4165 bgep->buff[ring].rf_next); 4166 4167 /* 4168 * MSI bits:The least significant MSI 16-bit word. 4169 * ISR will be triggered different. 4170 */ 4171 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 4172 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 0x70); 4173 4174 /* 4175 * Extra step (DSG): select which interrupts are enabled 4176 * 4177 * Program the Ethernet MAC engine to signal attention on 4178 * Link Change events, then enable interrupts on MAC, DMA, 4179 * and FLOW attention signals. 4180 */ 4181 bge_reg_set32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 4182 ETHERNET_EVENT_LINK_INT | 4183 ETHERNET_STATUS_PCS_ERROR_INT); 4184 #ifdef BGE_IPMI_ASF 4185 if (bgep->asf_enabled) { 4186 bge_reg_set32(bgep, MODE_CONTROL_REG, 4187 MODE_INT_ON_FLOW_ATTN | 4188 MODE_INT_ON_DMA_ATTN | 4189 MODE_HOST_STACK_UP| 4190 MODE_INT_ON_MAC_ATTN); 4191 } else { 4192 #endif 4193 bge_reg_set32(bgep, MODE_CONTROL_REG, 4194 MODE_INT_ON_FLOW_ATTN | 4195 MODE_INT_ON_DMA_ATTN | 4196 MODE_INT_ON_MAC_ATTN); 4197 #ifdef BGE_IPMI_ASF 4198 } 4199 #endif 4200 4201 /* 4202 * Step 97: enable PCI interrupts!!! 4203 */ 4204 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 4205 bge_cfg_clr32(bgep, PCI_CONF_BGE_MHCR, 4206 bgep->chipid.mask_pci_int); 4207 4208 /* 4209 * All done! 4210 */ 4211 bgep->bge_chip_state = BGE_CHIP_RUNNING; 4212 return (retval); 4213 } 4214 4215 4216 /* 4217 * ========== Hardware interrupt handler ========== 4218 */ 4219 4220 #undef BGE_DBG 4221 #define BGE_DBG BGE_DBG_INT /* debug flag for this code */ 4222 4223 /* 4224 * Sync the status block, then atomically clear the specified bits in 4225 * the <flags-and-tag> field of the status block. 4226 * the <flags> word of the status block, returning the value of the 4227 * <tag> and the <flags> before the bits were cleared. 4228 */ 4229 static int bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags); 4230 #pragma inline(bge_status_sync) 4231 4232 static int 4233 bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags) 4234 { 4235 bge_status_t *bsp; 4236 int retval; 4237 4238 BGE_TRACE(("bge_status_sync($%p, 0x%llx)", 4239 (void *)bgep, bits)); 4240 4241 ASSERT(bgep->bge_guard == BGE_GUARD); 4242 4243 DMA_SYNC(bgep->status_block, DDI_DMA_SYNC_FORKERNEL); 4244 retval = bge_check_dma_handle(bgep, bgep->status_block.dma_hdl); 4245 if (retval != DDI_FM_OK) 4246 return (retval); 4247 4248 bsp = DMA_VPTR(bgep->status_block); 4249 *flags = bge_atomic_clr64(&bsp->flags_n_tag, bits); 4250 4251 BGE_DEBUG(("bge_status_sync($%p, 0x%llx) returning 0x%llx", 4252 (void *)bgep, bits, *flags)); 4253 4254 return (retval); 4255 } 4256 4257 void bge_wake_factotum(bge_t *bgep); 4258 #pragma inline(bge_wake_factotum) 4259 4260 void 4261 bge_wake_factotum(bge_t *bgep) 4262 { 4263 mutex_enter(bgep->softintrlock); 4264 if (bgep->factotum_flag == 0) { 4265 bgep->factotum_flag = 1; 4266 ddi_trigger_softintr(bgep->factotum_id); 4267 } 4268 mutex_exit(bgep->softintrlock); 4269 } 4270 4271 /* 4272 * bge_intr() -- handle chip interrupts 4273 */ 4274 uint_t bge_intr(caddr_t arg1, caddr_t arg2); 4275 #pragma no_inline(bge_intr) 4276 4277 uint_t 4278 bge_intr(caddr_t arg1, caddr_t arg2) 4279 { 4280 bge_t *bgep = (void *)arg1; /* private device info */ 4281 bge_status_t *bsp; 4282 uint64_t flags; 4283 uint32_t regval; 4284 uint_t result; 4285 int retval, loop_cnt = 0; 4286 4287 BGE_TRACE(("bge_intr($%p) ($%p)", arg1, arg2)); 4288 4289 /* 4290 * GLD v2 checks that s/w setup is complete before passing 4291 * interrupts to this routine, thus eliminating the old 4292 * (and well-known) race condition around ddi_add_intr() 4293 */ 4294 ASSERT(bgep->progress & PROGRESS_HWINT); 4295 4296 result = DDI_INTR_UNCLAIMED; 4297 mutex_enter(bgep->genlock); 4298 4299 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) { 4300 /* 4301 * Check whether chip's says it's asserting #INTA; 4302 * if not, don't process or claim the interrupt. 4303 * 4304 * Note that the PCI signal is active low, so the 4305 * bit is *zero* when the interrupt is asserted. 4306 */ 4307 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 4308 if (!(DEVICE_5717_SERIES_CHIPSETS(bgep)) && 4309 (regval & MLCR_INTA_STATE)) { 4310 if (bge_check_acc_handle(bgep, bgep->io_handle) 4311 != DDI_FM_OK) 4312 goto chip_stop; 4313 mutex_exit(bgep->genlock); 4314 return (result); 4315 } 4316 4317 /* 4318 * Block further PCI interrupts ... 4319 */ 4320 bge_reg_set32(bgep, PCI_CONF_BGE_MHCR, 4321 bgep->chipid.mask_pci_int); 4322 4323 } else { 4324 /* 4325 * Check MSI status 4326 */ 4327 regval = bge_reg_get32(bgep, MSI_STATUS_REG); 4328 if (regval & MSI_ERROR_ATTENTION) { 4329 BGE_REPORT((bgep, "msi error attention," 4330 " status=0x%x", regval)); 4331 bge_reg_put32(bgep, MSI_STATUS_REG, regval); 4332 } 4333 } 4334 4335 result = DDI_INTR_CLAIMED; 4336 4337 BGE_DEBUG(("bge_intr($%p) ($%p) regval 0x%08x", arg1, arg2, regval)); 4338 4339 /* 4340 * Sync the status block and grab the flags-n-tag from it. 4341 * We count the number of interrupts where there doesn't 4342 * seem to have been a DMA update of the status block; if 4343 * it *has* been updated, the counter will be cleared in 4344 * the while() loop below ... 4345 */ 4346 bgep->missed_dmas += 1; 4347 bsp = DMA_VPTR(bgep->status_block); 4348 for (loop_cnt = 0; loop_cnt < bge_intr_max_loop; loop_cnt++) { 4349 if (bgep->bge_chip_state != BGE_CHIP_RUNNING) { 4350 /* 4351 * bge_chip_stop() may have freed dma area etc 4352 * while we were in this interrupt handler - 4353 * better not call bge_status_sync() 4354 */ 4355 (void) bge_check_acc_handle(bgep, 4356 bgep->io_handle); 4357 mutex_exit(bgep->genlock); 4358 return (DDI_INTR_CLAIMED); 4359 } 4360 retval = bge_status_sync(bgep, STATUS_FLAG_UPDATED, 4361 &flags); 4362 if (retval != DDI_FM_OK) { 4363 bgep->bge_dma_error = B_TRUE; 4364 goto chip_stop; 4365 } 4366 4367 if (!(flags & STATUS_FLAG_UPDATED)) 4368 break; 4369 4370 /* 4371 * Tell the chip that we're processing the interrupt 4372 */ 4373 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 4374 INTERRUPT_MBOX_DISABLE(flags)); 4375 if (bge_check_acc_handle(bgep, bgep->io_handle) != 4376 DDI_FM_OK) 4377 goto chip_stop; 4378 4379 /* 4380 * Drop the mutex while we: 4381 * Receive any newly-arrived packets 4382 * Recycle any newly-finished send buffers 4383 */ 4384 bgep->bge_intr_running = B_TRUE; 4385 mutex_exit(bgep->genlock); 4386 bge_receive(bgep, bsp); 4387 (void) bge_recycle(bgep, bsp); 4388 mutex_enter(bgep->genlock); 4389 bgep->bge_intr_running = B_FALSE; 4390 4391 /* 4392 * Tell the chip we've finished processing, and 4393 * give it the tag that we got from the status 4394 * block earlier, so that it knows just how far 4395 * we've gone. If it's got more for us to do, 4396 * it will now update the status block and try 4397 * to assert an interrupt (but we've got the 4398 * #INTA blocked at present). If we see the 4399 * update, we'll loop around to do some more. 4400 * Eventually we'll get out of here ... 4401 */ 4402 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 4403 INTERRUPT_MBOX_ENABLE(flags)); 4404 if (bgep->chipid.pci_type == BGE_PCI_E) 4405 (void) bge_mbx_get(bgep, INTERRUPT_MBOX_0_REG); 4406 bgep->missed_dmas = 0; 4407 } 4408 4409 /* 4410 * Check for exceptional conditions that we need to handle 4411 * 4412 * Link status changed 4413 * Status block not updated 4414 */ 4415 if (flags & STATUS_FLAG_LINK_CHANGED) 4416 bge_wake_factotum(bgep); 4417 4418 if (bgep->missed_dmas) { 4419 /* 4420 * Probably due to the internal status tag not 4421 * being reset. Force a status block update now; 4422 * this should ensure that we get an update and 4423 * a new interrupt. After that, we should be in 4424 * sync again ... 4425 */ 4426 BGE_REPORT((bgep, "interrupt: flags 0x%llx - " 4427 "not updated?", flags)); 4428 bgep->missed_updates++; 4429 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 4430 COALESCE_NOW); 4431 4432 if (bgep->missed_dmas >= bge_dma_miss_limit) { 4433 /* 4434 * If this happens multiple times in a row, 4435 * it means DMA is just not working. Maybe 4436 * the chip's failed, or maybe there's a 4437 * problem on the PCI bus or in the host-PCI 4438 * bridge (Tomatillo). 4439 * 4440 * At all events, we want to stop further 4441 * interrupts and let the recovery code take 4442 * over to see whether anything can be done 4443 * about it ... 4444 */ 4445 bge_fm_ereport(bgep, 4446 DDI_FM_DEVICE_BADINT_LIMIT); 4447 goto chip_stop; 4448 } 4449 } 4450 4451 /* 4452 * Reenable assertion of #INTA, unless there's a DMA fault 4453 */ 4454 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) { 4455 bge_reg_clr32(bgep, PCI_CONF_BGE_MHCR, 4456 bgep->chipid.mask_pci_int); 4457 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != 4458 DDI_FM_OK) 4459 goto chip_stop; 4460 } 4461 4462 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4463 goto chip_stop; 4464 4465 mutex_exit(bgep->genlock); 4466 return (result); 4467 4468 chip_stop: 4469 #ifdef BGE_IPMI_ASF 4470 if (bgep->asf_enabled && bgep->asf_status == ASF_STAT_RUN) { 4471 /* 4472 * We must stop ASF heart beat before 4473 * bge_chip_stop(), otherwise some 4474 * computers (ex. IBM HS20 blade 4475 * server) may crash. 4476 */ 4477 bge_asf_update_status(bgep); 4478 bge_asf_stop_timer(bgep); 4479 bgep->asf_status = ASF_STAT_STOP; 4480 4481 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 4482 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 4483 } 4484 #endif 4485 bge_chip_stop(bgep, B_TRUE); 4486 (void) bge_check_acc_handle(bgep, bgep->io_handle); 4487 mutex_exit(bgep->genlock); 4488 return (result); 4489 } 4490 4491 /* 4492 * ========== Factotum, implemented as a softint handler ========== 4493 */ 4494 4495 #undef BGE_DBG 4496 #define BGE_DBG BGE_DBG_FACT /* debug flag for this code */ 4497 4498 static void bge_factotum_error_handler(bge_t *bgep); 4499 #pragma no_inline(bge_factotum_error_handler) 4500 4501 static void 4502 bge_factotum_error_handler(bge_t *bgep) 4503 { 4504 uint32_t flow; 4505 uint32_t rdma; 4506 uint32_t wdma; 4507 uint32_t tmac; 4508 uint32_t rmac; 4509 uint32_t rxrs; 4510 uint32_t txrs = 0; 4511 4512 ASSERT(mutex_owned(bgep->genlock)); 4513 4514 /* 4515 * Read all the registers that show the possible 4516 * reasons for the ERROR bit to be asserted 4517 */ 4518 flow = bge_reg_get32(bgep, FLOW_ATTN_REG); 4519 rdma = bge_reg_get32(bgep, READ_DMA_STATUS_REG); 4520 wdma = bge_reg_get32(bgep, WRITE_DMA_STATUS_REG); 4521 tmac = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 4522 rmac = bge_reg_get32(bgep, RECEIVE_MAC_STATUS_REG); 4523 rxrs = bge_reg_get32(bgep, RX_RISC_STATE_REG); 4524 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4525 txrs = bge_reg_get32(bgep, TX_RISC_STATE_REG); 4526 4527 BGE_DEBUG(("factotum($%p) flow 0x%x rdma 0x%x wdma 0x%x", 4528 (void *)bgep, flow, rdma, wdma)); 4529 BGE_DEBUG(("factotum($%p) tmac 0x%x rmac 0x%x rxrs 0x%08x txrs 0x%08x", 4530 (void *)bgep, tmac, rmac, rxrs, txrs)); 4531 4532 /* 4533 * For now, just clear all the errors ... 4534 */ 4535 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4536 bge_reg_put32(bgep, TX_RISC_STATE_REG, ~0); 4537 bge_reg_put32(bgep, RX_RISC_STATE_REG, ~0); 4538 bge_reg_put32(bgep, RECEIVE_MAC_STATUS_REG, ~0); 4539 bge_reg_put32(bgep, WRITE_DMA_STATUS_REG, ~0); 4540 bge_reg_put32(bgep, READ_DMA_STATUS_REG, ~0); 4541 bge_reg_put32(bgep, FLOW_ATTN_REG, ~0); 4542 } 4543 4544 /* 4545 * Handler for hardware link state change. 4546 * 4547 * When this routine is called, the hardware link state has changed 4548 * and the new state is reflected in the param_* variables. Here 4549 * we must update the softstate and reprogram the MAC to match. 4550 */ 4551 static void bge_factotum_link_handler(bge_t *bgep); 4552 #pragma no_inline(bge_factotum_link_handler) 4553 4554 static void 4555 bge_factotum_link_handler(bge_t *bgep) 4556 { 4557 ASSERT(mutex_owned(bgep->genlock)); 4558 4559 /* 4560 * Update the s/w link_state 4561 */ 4562 if (bgep->param_link_up) 4563 bgep->link_state = LINK_STATE_UP; 4564 else 4565 bgep->link_state = LINK_STATE_DOWN; 4566 4567 /* 4568 * Reprogram the MAC modes to match 4569 */ 4570 bge_sync_mac_modes(bgep); 4571 } 4572 4573 static boolean_t bge_factotum_link_check(bge_t *bgep, int *dma_state); 4574 #pragma no_inline(bge_factotum_link_check) 4575 4576 static boolean_t 4577 bge_factotum_link_check(bge_t *bgep, int *dma_state) 4578 { 4579 boolean_t check; 4580 uint64_t flags; 4581 uint32_t tmac_status; 4582 4583 ASSERT(mutex_owned(bgep->genlock)); 4584 4585 /* 4586 * Get & clear the writable status bits in the Tx status register 4587 * (some bits are write-1-to-clear, others are just readonly). 4588 */ 4589 tmac_status = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 4590 bge_reg_put32(bgep, TRANSMIT_MAC_STATUS_REG, tmac_status); 4591 4592 /* 4593 * Get & clear the ERROR and LINK_CHANGED bits from the status block 4594 */ 4595 *dma_state = bge_status_sync(bgep, STATUS_FLAG_ERROR | 4596 STATUS_FLAG_LINK_CHANGED, &flags); 4597 if (*dma_state != DDI_FM_OK) 4598 return (B_FALSE); 4599 4600 /* 4601 * Clear any errors flagged in the status block ... 4602 */ 4603 if (flags & STATUS_FLAG_ERROR) 4604 bge_factotum_error_handler(bgep); 4605 4606 /* 4607 * We need to check the link status if: 4608 * the status block says there's been a link change 4609 * or there's any discrepancy between the various 4610 * flags indicating the link state (link_state, 4611 * param_link_up, and the LINK STATE bit in the 4612 * Transmit MAC status register). 4613 */ 4614 check = (flags & STATUS_FLAG_LINK_CHANGED) != 0; 4615 switch (bgep->link_state) { 4616 case LINK_STATE_UP: 4617 check |= (bgep->param_link_up == B_FALSE); 4618 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) == 0); 4619 break; 4620 4621 case LINK_STATE_DOWN: 4622 check |= (bgep->param_link_up != B_FALSE); 4623 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) != 0); 4624 break; 4625 4626 default: 4627 check = B_TRUE; 4628 break; 4629 } 4630 4631 /* 4632 * If <check> is false, we're sure the link hasn't changed. 4633 * If true, however, it's not yet definitive; we have to call 4634 * bge_phys_check() to determine whether the link has settled 4635 * into a new state yet ... and if it has, then call the link 4636 * state change handler.But when the chip is 5700 in Dell 6650 4637 * ,even if check is false, the link may have changed.So we 4638 * have to call bge_phys_check() to determine the link state. 4639 */ 4640 if (check || bgep->chipid.device == DEVICE_ID_5700) { 4641 check = bge_phys_check(bgep); 4642 if (check) 4643 bge_factotum_link_handler(bgep); 4644 } 4645 4646 return (check); 4647 } 4648 4649 /* 4650 * Factotum routine to check for Tx stall, using the 'watchdog' counter 4651 */ 4652 static boolean_t bge_factotum_stall_check(bge_t *bgep); 4653 #pragma no_inline(bge_factotum_stall_check) 4654 4655 static boolean_t 4656 bge_factotum_stall_check(bge_t *bgep) 4657 { 4658 uint32_t dogval; 4659 bge_status_t *bsp; 4660 uint64_t now = gethrtime(); 4661 4662 if ((now - bgep->timestamp) < BGE_CYCLIC_PERIOD) 4663 return (B_FALSE); 4664 4665 bgep->timestamp = now; 4666 4667 ASSERT(mutex_owned(bgep->genlock)); 4668 4669 /* 4670 * Specific check for Tx stall ... 4671 * 4672 * The 'watchdog' counter is incremented whenever a packet 4673 * is queued, reset to 1 when some (but not all) buffers 4674 * are reclaimed, reset to 0 (disabled) when all buffers 4675 * are reclaimed, and shifted left here. If it exceeds the 4676 * threshold value, the chip is assumed to have stalled and 4677 * is put into the ERROR state. The factotum will then reset 4678 * it on the next pass. 4679 * 4680 * All of which should ensure that we don't get into a state 4681 * where packets are left pending indefinitely! 4682 */ 4683 dogval = bge_atomic_shl32(&bgep->watchdog, 1); 4684 bsp = DMA_VPTR(bgep->status_block); 4685 if (dogval < bge_watchdog_count || bge_recycle(bgep, bsp)) 4686 return (B_FALSE); 4687 4688 #if !defined(BGE_NETCONSOLE) 4689 BGE_REPORT((bgep, "Tx stall detected, watchdog code 0x%x", dogval)); 4690 #endif 4691 bge_fm_ereport(bgep, DDI_FM_DEVICE_STALL); 4692 return (B_TRUE); 4693 } 4694 4695 /* 4696 * The factotum is woken up when there's something to do that we'd rather 4697 * not do from inside a hardware interrupt handler or high-level cyclic. 4698 * Its two main tasks are: 4699 * reset & restart the chip after an error 4700 * check the link status whenever necessary 4701 */ 4702 uint_t bge_chip_factotum(caddr_t arg); 4703 #pragma no_inline(bge_chip_factotum) 4704 4705 uint_t 4706 bge_chip_factotum(caddr_t arg) 4707 { 4708 bge_t *bgep; 4709 uint_t result; 4710 boolean_t error; 4711 boolean_t linkchg; 4712 int dma_state; 4713 4714 bgep = (void *)arg; 4715 4716 BGE_TRACE(("bge_chip_factotum($%p)", (void *)bgep)); 4717 4718 mutex_enter(bgep->softintrlock); 4719 if (bgep->factotum_flag == 0) { 4720 mutex_exit(bgep->softintrlock); 4721 return (DDI_INTR_UNCLAIMED); 4722 } 4723 bgep->factotum_flag = 0; 4724 mutex_exit(bgep->softintrlock); 4725 4726 result = DDI_INTR_CLAIMED; 4727 error = B_FALSE; 4728 linkchg = B_FALSE; 4729 4730 mutex_enter(bgep->genlock); 4731 switch (bgep->bge_chip_state) { 4732 default: 4733 break; 4734 4735 case BGE_CHIP_RUNNING: 4736 linkchg = bge_factotum_link_check(bgep, &dma_state); 4737 error = bge_factotum_stall_check(bgep); 4738 if (dma_state != DDI_FM_OK) { 4739 bgep->bge_dma_error = B_TRUE; 4740 error = B_TRUE; 4741 } 4742 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4743 error = B_TRUE; 4744 if (error) 4745 bgep->bge_chip_state = BGE_CHIP_ERROR; 4746 break; 4747 4748 case BGE_CHIP_ERROR: 4749 error = B_TRUE; 4750 break; 4751 4752 case BGE_CHIP_FAULT: 4753 /* 4754 * Fault detected, time to reset ... 4755 */ 4756 if (bge_autorecover) { 4757 if (!(bgep->progress & PROGRESS_BUFS)) { 4758 /* 4759 * if we can't allocate the ring buffers, 4760 * try later 4761 */ 4762 if (bge_alloc_bufs(bgep) != DDI_SUCCESS) { 4763 mutex_exit(bgep->genlock); 4764 return (result); 4765 } 4766 bgep->progress |= PROGRESS_BUFS; 4767 } 4768 if (!(bgep->progress & PROGRESS_INTR)) { 4769 bge_init_rings(bgep); 4770 bge_intr_enable(bgep); 4771 bgep->progress |= PROGRESS_INTR; 4772 } 4773 if (!(bgep->progress & PROGRESS_KSTATS)) { 4774 bge_init_kstats(bgep, 4775 ddi_get_instance(bgep->devinfo)); 4776 bgep->progress |= PROGRESS_KSTATS; 4777 } 4778 4779 BGE_REPORT((bgep, "automatic recovery activated")); 4780 4781 if (bge_restart(bgep, B_FALSE) != DDI_SUCCESS) { 4782 bgep->bge_chip_state = BGE_CHIP_ERROR; 4783 error = B_TRUE; 4784 } 4785 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != 4786 DDI_FM_OK) { 4787 bgep->bge_chip_state = BGE_CHIP_ERROR; 4788 error = B_TRUE; 4789 } 4790 if (bge_check_acc_handle(bgep, bgep->io_handle) != 4791 DDI_FM_OK) { 4792 bgep->bge_chip_state = BGE_CHIP_ERROR; 4793 error = B_TRUE; 4794 } 4795 if (error == B_FALSE) { 4796 #ifdef BGE_IPMI_ASF 4797 if (bgep->asf_enabled && 4798 bgep->asf_status != ASF_STAT_RUN) { 4799 bgep->asf_timeout_id = timeout( 4800 bge_asf_heartbeat, (void *)bgep, 4801 drv_usectohz( 4802 BGE_ASF_HEARTBEAT_INTERVAL)); 4803 bgep->asf_status = ASF_STAT_RUN; 4804 } 4805 #endif 4806 if (!bgep->manual_reset) { 4807 ddi_fm_service_impact(bgep->devinfo, 4808 DDI_SERVICE_RESTORED); 4809 } 4810 } 4811 } 4812 break; 4813 } 4814 4815 4816 /* 4817 * If an error is detected, stop the chip now, marking it as 4818 * faulty, so that it will be reset next time through ... 4819 * 4820 * Note that if intr_running is set, then bge_intr() has dropped 4821 * genlock to call bge_receive/bge_recycle. Can't stop the chip at 4822 * this point so have to wait until the next time the factotum runs. 4823 */ 4824 if (error && !bgep->bge_intr_running) { 4825 #ifdef BGE_IPMI_ASF 4826 if (bgep->asf_enabled && (bgep->asf_status == ASF_STAT_RUN)) { 4827 /* 4828 * We must stop ASF heart beat before bge_chip_stop(), 4829 * otherwise some computers (ex. IBM HS20 blade server) 4830 * may crash. 4831 */ 4832 bge_asf_update_status(bgep); 4833 bge_asf_stop_timer(bgep); 4834 bgep->asf_status = ASF_STAT_STOP; 4835 4836 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 4837 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 4838 } 4839 #endif 4840 bge_chip_stop(bgep, B_TRUE); 4841 (void) bge_check_acc_handle(bgep, bgep->io_handle); 4842 } 4843 mutex_exit(bgep->genlock); 4844 4845 /* 4846 * If the link state changed, tell the world about it. 4847 * Note: can't do this while still holding the mutex. 4848 */ 4849 if (bgep->link_update_timer == BGE_LINK_UPDATE_TIMEOUT && 4850 bgep->link_state != LINK_STATE_UNKNOWN) 4851 linkchg = B_TRUE; 4852 else if (bgep->link_update_timer < BGE_LINK_UPDATE_TIMEOUT && 4853 bgep->link_state == LINK_STATE_DOWN) 4854 linkchg = B_FALSE; 4855 4856 if (linkchg) { 4857 mac_link_update(bgep->mh, bgep->link_state); 4858 bgep->link_update_timer = BGE_LINK_UPDATE_DONE; 4859 } 4860 if (bgep->manual_reset) { 4861 bgep->manual_reset = B_FALSE; 4862 } 4863 4864 return (result); 4865 } 4866 4867 /* 4868 * High-level cyclic handler 4869 * 4870 * This routine schedules a (low-level) softint callback to the 4871 * factotum, and prods the chip to update the status block (which 4872 * will cause a hardware interrupt when complete). 4873 */ 4874 void bge_chip_cyclic(void *arg); 4875 #pragma no_inline(bge_chip_cyclic) 4876 4877 void 4878 bge_chip_cyclic(void *arg) 4879 { 4880 bge_t *bgep; 4881 4882 bgep = arg; 4883 4884 switch (bgep->bge_chip_state) { 4885 default: 4886 return; 4887 4888 case BGE_CHIP_RUNNING: 4889 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, COALESCE_NOW); 4890 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4891 ddi_fm_service_impact(bgep->devinfo, 4892 DDI_SERVICE_UNAFFECTED); 4893 4894 if (bgep->link_update_timer < BGE_LINK_UPDATE_TIMEOUT) 4895 bgep->link_update_timer++; 4896 4897 break; 4898 4899 case BGE_CHIP_FAULT: 4900 case BGE_CHIP_ERROR: 4901 break; 4902 } 4903 4904 bge_wake_factotum(bgep); 4905 } 4906 4907 4908 /* 4909 * ========== Ioctl subfunctions ========== 4910 */ 4911 4912 #undef BGE_DBG 4913 #define BGE_DBG BGE_DBG_PPIO /* debug flag for this code */ 4914 4915 #if BGE_DEBUGGING || BGE_DO_PPIO 4916 4917 static void bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 4918 #pragma no_inline(bge_chip_peek_cfg) 4919 4920 static void 4921 bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 4922 { 4923 uint64_t regval; 4924 uint64_t regno; 4925 4926 BGE_TRACE(("bge_chip_peek_cfg($%p, $%p)", 4927 (void *)bgep, (void *)ppd)); 4928 4929 regno = ppd->pp_acc_offset; 4930 4931 switch (ppd->pp_acc_size) { 4932 case 1: 4933 regval = pci_config_get8(bgep->cfg_handle, regno); 4934 break; 4935 4936 case 2: 4937 regval = pci_config_get16(bgep->cfg_handle, regno); 4938 break; 4939 4940 case 4: 4941 regval = pci_config_get32(bgep->cfg_handle, regno); 4942 break; 4943 4944 case 8: 4945 regval = pci_config_get64(bgep->cfg_handle, regno); 4946 break; 4947 } 4948 4949 ppd->pp_acc_data = regval; 4950 } 4951 4952 static void bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 4953 #pragma no_inline(bge_chip_poke_cfg) 4954 4955 static void 4956 bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 4957 { 4958 uint64_t regval; 4959 uint64_t regno; 4960 4961 BGE_TRACE(("bge_chip_poke_cfg($%p, $%p)", 4962 (void *)bgep, (void *)ppd)); 4963 4964 regno = ppd->pp_acc_offset; 4965 regval = ppd->pp_acc_data; 4966 4967 switch (ppd->pp_acc_size) { 4968 case 1: 4969 pci_config_put8(bgep->cfg_handle, regno, regval); 4970 break; 4971 4972 case 2: 4973 pci_config_put16(bgep->cfg_handle, regno, regval); 4974 break; 4975 4976 case 4: 4977 pci_config_put32(bgep->cfg_handle, regno, regval); 4978 break; 4979 4980 case 8: 4981 pci_config_put64(bgep->cfg_handle, regno, regval); 4982 break; 4983 } 4984 } 4985 4986 static void bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd); 4987 #pragma no_inline(bge_chip_peek_reg) 4988 4989 static void 4990 bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd) 4991 { 4992 uint64_t regval; 4993 void *regaddr; 4994 4995 BGE_TRACE(("bge_chip_peek_reg($%p, $%p)", 4996 (void *)bgep, (void *)ppd)); 4997 4998 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 4999 5000 switch (ppd->pp_acc_size) { 5001 case 1: 5002 regval = ddi_get8(bgep->io_handle, regaddr); 5003 break; 5004 5005 case 2: 5006 regval = ddi_get16(bgep->io_handle, regaddr); 5007 break; 5008 5009 case 4: 5010 regval = ddi_get32(bgep->io_handle, regaddr); 5011 break; 5012 5013 case 8: 5014 regval = ddi_get64(bgep->io_handle, regaddr); 5015 break; 5016 } 5017 5018 ppd->pp_acc_data = regval; 5019 } 5020 5021 static void bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd); 5022 #pragma no_inline(bge_chip_peek_reg) 5023 5024 static void 5025 bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd) 5026 { 5027 uint64_t regval; 5028 void *regaddr; 5029 5030 BGE_TRACE(("bge_chip_poke_reg($%p, $%p)", 5031 (void *)bgep, (void *)ppd)); 5032 5033 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 5034 regval = ppd->pp_acc_data; 5035 5036 switch (ppd->pp_acc_size) { 5037 case 1: 5038 ddi_put8(bgep->io_handle, regaddr, regval); 5039 break; 5040 5041 case 2: 5042 ddi_put16(bgep->io_handle, regaddr, regval); 5043 break; 5044 5045 case 4: 5046 ddi_put32(bgep->io_handle, regaddr, regval); 5047 break; 5048 5049 case 8: 5050 ddi_put64(bgep->io_handle, regaddr, regval); 5051 break; 5052 } 5053 BGE_PCICHK(bgep); 5054 } 5055 5056 static void bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd); 5057 #pragma no_inline(bge_chip_peek_nic) 5058 5059 static void 5060 bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd) 5061 { 5062 uint64_t regoff; 5063 uint64_t regval; 5064 void *regaddr; 5065 5066 BGE_TRACE(("bge_chip_peek_nic($%p, $%p)", 5067 (void *)bgep, (void *)ppd)); 5068 5069 regoff = ppd->pp_acc_offset; 5070 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 5071 regoff &= MWBAR_GRANULE_MASK; 5072 regoff += NIC_MEM_WINDOW_OFFSET; 5073 regaddr = PIO_ADDR(bgep, regoff); 5074 5075 switch (ppd->pp_acc_size) { 5076 case 1: 5077 regval = ddi_get8(bgep->io_handle, regaddr); 5078 break; 5079 5080 case 2: 5081 regval = ddi_get16(bgep->io_handle, regaddr); 5082 break; 5083 5084 case 4: 5085 regval = ddi_get32(bgep->io_handle, regaddr); 5086 break; 5087 5088 case 8: 5089 regval = ddi_get64(bgep->io_handle, regaddr); 5090 break; 5091 } 5092 5093 ppd->pp_acc_data = regval; 5094 } 5095 5096 static void bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd); 5097 #pragma no_inline(bge_chip_poke_nic) 5098 5099 static void 5100 bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd) 5101 { 5102 uint64_t regoff; 5103 uint64_t regval; 5104 void *regaddr; 5105 5106 BGE_TRACE(("bge_chip_poke_nic($%p, $%p)", 5107 (void *)bgep, (void *)ppd)); 5108 5109 regoff = ppd->pp_acc_offset; 5110 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 5111 regoff &= MWBAR_GRANULE_MASK; 5112 regoff += NIC_MEM_WINDOW_OFFSET; 5113 regaddr = PIO_ADDR(bgep, regoff); 5114 regval = ppd->pp_acc_data; 5115 5116 switch (ppd->pp_acc_size) { 5117 case 1: 5118 ddi_put8(bgep->io_handle, regaddr, regval); 5119 break; 5120 5121 case 2: 5122 ddi_put16(bgep->io_handle, regaddr, regval); 5123 break; 5124 5125 case 4: 5126 ddi_put32(bgep->io_handle, regaddr, regval); 5127 break; 5128 5129 case 8: 5130 ddi_put64(bgep->io_handle, regaddr, regval); 5131 break; 5132 } 5133 BGE_PCICHK(bgep); 5134 } 5135 5136 static void bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd); 5137 #pragma no_inline(bge_chip_peek_mii) 5138 5139 static void 5140 bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd) 5141 { 5142 BGE_TRACE(("bge_chip_peek_mii($%p, $%p)", 5143 (void *)bgep, (void *)ppd)); 5144 5145 ppd->pp_acc_data = bge_mii_get16(bgep, ppd->pp_acc_offset/2); 5146 } 5147 5148 static void bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd); 5149 #pragma no_inline(bge_chip_poke_mii) 5150 5151 static void 5152 bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd) 5153 { 5154 BGE_TRACE(("bge_chip_poke_mii($%p, $%p)", 5155 (void *)bgep, (void *)ppd)); 5156 5157 bge_mii_put16(bgep, ppd->pp_acc_offset/2, ppd->pp_acc_data); 5158 } 5159 5160 #if BGE_SEE_IO32 5161 5162 static void bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 5163 #pragma no_inline(bge_chip_peek_seeprom) 5164 5165 static void 5166 bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 5167 { 5168 uint32_t data; 5169 int err; 5170 5171 BGE_TRACE(("bge_chip_peek_seeprom($%p, $%p)", 5172 (void *)bgep, (void *)ppd)); 5173 5174 err = bge_nvmem_rw32(bgep, BGE_SEE_READ, ppd->pp_acc_offset, &data); 5175 ppd->pp_acc_data = err ? ~0ull : data; 5176 } 5177 5178 static void bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 5179 #pragma no_inline(bge_chip_poke_seeprom) 5180 5181 static void 5182 bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 5183 { 5184 uint32_t data; 5185 5186 BGE_TRACE(("bge_chip_poke_seeprom($%p, $%p)", 5187 (void *)bgep, (void *)ppd)); 5188 5189 data = ppd->pp_acc_data; 5190 (void) bge_nvmem_rw32(bgep, BGE_SEE_WRITE, ppd->pp_acc_offset, &data); 5191 } 5192 #endif /* BGE_SEE_IO32 */ 5193 5194 #if BGE_FLASH_IO32 5195 5196 static void bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd); 5197 #pragma no_inline(bge_chip_peek_flash) 5198 5199 static void 5200 bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd) 5201 { 5202 uint32_t data; 5203 int err; 5204 5205 BGE_TRACE(("bge_chip_peek_flash($%p, $%p)", 5206 (void *)bgep, (void *)ppd)); 5207 5208 err = bge_nvmem_rw32(bgep, BGE_FLASH_READ, ppd->pp_acc_offset, &data); 5209 ppd->pp_acc_data = err ? ~0ull : data; 5210 } 5211 5212 static void bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd); 5213 #pragma no_inline(bge_chip_poke_flash) 5214 5215 static void 5216 bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd) 5217 { 5218 uint32_t data; 5219 5220 BGE_TRACE(("bge_chip_poke_flash($%p, $%p)", 5221 (void *)bgep, (void *)ppd)); 5222 5223 data = ppd->pp_acc_data; 5224 (void) bge_nvmem_rw32(bgep, BGE_FLASH_WRITE, 5225 ppd->pp_acc_offset, &data); 5226 } 5227 #endif /* BGE_FLASH_IO32 */ 5228 5229 static void bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd); 5230 #pragma no_inline(bge_chip_peek_mem) 5231 5232 static void 5233 bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd) 5234 { 5235 uint64_t regval; 5236 void *vaddr; 5237 5238 BGE_TRACE(("bge_chip_peek_bge($%p, $%p)", 5239 (void *)bgep, (void *)ppd)); 5240 5241 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 5242 5243 switch (ppd->pp_acc_size) { 5244 case 1: 5245 regval = *(uint8_t *)vaddr; 5246 break; 5247 5248 case 2: 5249 regval = *(uint16_t *)vaddr; 5250 break; 5251 5252 case 4: 5253 regval = *(uint32_t *)vaddr; 5254 break; 5255 5256 case 8: 5257 regval = *(uint64_t *)vaddr; 5258 break; 5259 } 5260 5261 BGE_DEBUG(("bge_chip_peek_mem($%p, $%p) peeked 0x%llx from $%p", 5262 (void *)bgep, (void *)ppd, regval, vaddr)); 5263 5264 ppd->pp_acc_data = regval; 5265 } 5266 5267 static void bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd); 5268 #pragma no_inline(bge_chip_poke_mem) 5269 5270 static void 5271 bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd) 5272 { 5273 uint64_t regval; 5274 void *vaddr; 5275 5276 BGE_TRACE(("bge_chip_poke_mem($%p, $%p)", 5277 (void *)bgep, (void *)ppd)); 5278 5279 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 5280 regval = ppd->pp_acc_data; 5281 5282 BGE_DEBUG(("bge_chip_poke_mem($%p, $%p) poking 0x%llx at $%p", 5283 (void *)bgep, (void *)ppd, regval, vaddr)); 5284 5285 switch (ppd->pp_acc_size) { 5286 case 1: 5287 *(uint8_t *)vaddr = (uint8_t)regval; 5288 break; 5289 5290 case 2: 5291 *(uint16_t *)vaddr = (uint16_t)regval; 5292 break; 5293 5294 case 4: 5295 *(uint32_t *)vaddr = (uint32_t)regval; 5296 break; 5297 5298 case 8: 5299 *(uint64_t *)vaddr = (uint64_t)regval; 5300 break; 5301 } 5302 } 5303 5304 static enum ioc_reply bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5305 struct iocblk *iocp); 5306 #pragma no_inline(bge_pp_ioctl) 5307 5308 static enum ioc_reply 5309 bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5310 { 5311 void (*ppfn)(bge_t *bgep, bge_peekpoke_t *ppd); 5312 bge_peekpoke_t *ppd; 5313 dma_area_t *areap; 5314 uint64_t sizemask; 5315 uint64_t mem_va; 5316 uint64_t maxoff; 5317 boolean_t peek; 5318 5319 switch (cmd) { 5320 default: 5321 /* NOTREACHED */ 5322 bge_error(bgep, "bge_pp_ioctl: invalid cmd 0x%x", cmd); 5323 return (IOC_INVAL); 5324 5325 case BGE_PEEK: 5326 peek = B_TRUE; 5327 break; 5328 5329 case BGE_POKE: 5330 peek = B_FALSE; 5331 break; 5332 } 5333 5334 /* 5335 * Validate format of ioctl 5336 */ 5337 if (iocp->ioc_count != sizeof (bge_peekpoke_t)) 5338 return (IOC_INVAL); 5339 if (mp->b_cont == NULL) 5340 return (IOC_INVAL); 5341 ppd = (void *)mp->b_cont->b_rptr; 5342 5343 /* 5344 * Validate request parameters 5345 */ 5346 switch (ppd->pp_acc_space) { 5347 default: 5348 return (IOC_INVAL); 5349 5350 case BGE_PP_SPACE_CFG: 5351 /* 5352 * Config space 5353 */ 5354 sizemask = 8|4|2|1; 5355 mem_va = 0; 5356 maxoff = PCI_CONF_HDR_SIZE; 5357 ppfn = peek ? bge_chip_peek_cfg : bge_chip_poke_cfg; 5358 break; 5359 5360 case BGE_PP_SPACE_REG: 5361 /* 5362 * Memory-mapped I/O space 5363 */ 5364 sizemask = 8|4|2|1; 5365 mem_va = 0; 5366 maxoff = RIAAR_REGISTER_MAX; 5367 ppfn = peek ? bge_chip_peek_reg : bge_chip_poke_reg; 5368 break; 5369 5370 case BGE_PP_SPACE_NIC: 5371 /* 5372 * NIC on-chip memory 5373 */ 5374 sizemask = 8|4|2|1; 5375 mem_va = 0; 5376 maxoff = MWBAR_ONCHIP_MAX; 5377 ppfn = peek ? bge_chip_peek_nic : bge_chip_poke_nic; 5378 break; 5379 5380 case BGE_PP_SPACE_MII: 5381 /* 5382 * PHY's MII registers 5383 * NB: all PHY registers are two bytes, but the 5384 * addresses increment in ones (word addressing). 5385 * So we scale the address here, then undo the 5386 * transformation inside the peek/poke functions. 5387 */ 5388 ppd->pp_acc_offset *= 2; 5389 sizemask = 2; 5390 mem_va = 0; 5391 maxoff = (MII_MAXREG+1)*2; 5392 ppfn = peek ? bge_chip_peek_mii : bge_chip_poke_mii; 5393 break; 5394 5395 #if BGE_SEE_IO32 5396 case BGE_PP_SPACE_SEEPROM: 5397 /* 5398 * Attached SEEPROM(s), if any. 5399 * NB: we use the high-order bits of the 'address' as 5400 * a device select to accommodate multiple SEEPROMS, 5401 * If each one is the maximum size (64kbytes), this 5402 * makes them appear contiguous. Otherwise, there may 5403 * be holes in the mapping. ENxS doesn't have any 5404 * SEEPROMs anyway ... 5405 */ 5406 sizemask = 4; 5407 mem_va = 0; 5408 maxoff = SEEPROM_DEV_AND_ADDR_MASK; 5409 ppfn = peek ? bge_chip_peek_seeprom : bge_chip_poke_seeprom; 5410 break; 5411 #endif /* BGE_SEE_IO32 */ 5412 5413 #if BGE_FLASH_IO32 5414 case BGE_PP_SPACE_FLASH: 5415 /* 5416 * Attached Flash device (if any); a maximum of one device 5417 * is currently supported. But it can be up to 1MB (unlike 5418 * the 64k limit on SEEPROMs) so why would you need more ;-) 5419 */ 5420 sizemask = 4; 5421 mem_va = 0; 5422 maxoff = NVM_FLASH_ADDR_MASK; 5423 ppfn = peek ? bge_chip_peek_flash : bge_chip_poke_flash; 5424 break; 5425 #endif /* BGE_FLASH_IO32 */ 5426 5427 case BGE_PP_SPACE_BGE: 5428 /* 5429 * BGE data structure! 5430 */ 5431 sizemask = 8|4|2|1; 5432 mem_va = (uintptr_t)bgep; 5433 maxoff = sizeof (*bgep); 5434 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 5435 break; 5436 5437 case BGE_PP_SPACE_STATUS: 5438 case BGE_PP_SPACE_STATISTICS: 5439 case BGE_PP_SPACE_TXDESC: 5440 case BGE_PP_SPACE_TXBUFF: 5441 case BGE_PP_SPACE_RXDESC: 5442 case BGE_PP_SPACE_RXBUFF: 5443 /* 5444 * Various DMA_AREAs 5445 */ 5446 switch (ppd->pp_acc_space) { 5447 case BGE_PP_SPACE_TXDESC: 5448 areap = &bgep->tx_desc; 5449 break; 5450 case BGE_PP_SPACE_TXBUFF: 5451 areap = &bgep->tx_buff[0]; 5452 break; 5453 case BGE_PP_SPACE_RXDESC: 5454 areap = &bgep->rx_desc[0]; 5455 break; 5456 case BGE_PP_SPACE_RXBUFF: 5457 areap = &bgep->rx_buff[0]; 5458 break; 5459 case BGE_PP_SPACE_STATUS: 5460 areap = &bgep->status_block; 5461 break; 5462 case BGE_PP_SPACE_STATISTICS: 5463 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 5464 areap = &bgep->statistics; 5465 break; 5466 } 5467 5468 sizemask = 8|4|2|1; 5469 mem_va = (uintptr_t)areap->mem_va; 5470 maxoff = areap->alength; 5471 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 5472 break; 5473 } 5474 5475 switch (ppd->pp_acc_size) { 5476 default: 5477 return (IOC_INVAL); 5478 5479 case 8: 5480 case 4: 5481 case 2: 5482 case 1: 5483 if ((ppd->pp_acc_size & sizemask) == 0) 5484 return (IOC_INVAL); 5485 break; 5486 } 5487 5488 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 5489 return (IOC_INVAL); 5490 5491 if (ppd->pp_acc_offset >= maxoff) 5492 return (IOC_INVAL); 5493 5494 if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff) 5495 return (IOC_INVAL); 5496 5497 /* 5498 * All OK - go do it! 5499 */ 5500 ppd->pp_acc_offset += mem_va; 5501 (*ppfn)(bgep, ppd); 5502 return (peek ? IOC_REPLY : IOC_ACK); 5503 } 5504 5505 static enum ioc_reply bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5506 struct iocblk *iocp); 5507 #pragma no_inline(bge_diag_ioctl) 5508 5509 static enum ioc_reply 5510 bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5511 { 5512 ASSERT(mutex_owned(bgep->genlock)); 5513 5514 switch (cmd) { 5515 default: 5516 /* NOTREACHED */ 5517 bge_error(bgep, "bge_diag_ioctl: invalid cmd 0x%x", cmd); 5518 return (IOC_INVAL); 5519 5520 case BGE_DIAG: 5521 /* 5522 * Currently a no-op 5523 */ 5524 return (IOC_ACK); 5525 5526 case BGE_PEEK: 5527 case BGE_POKE: 5528 return (bge_pp_ioctl(bgep, cmd, mp, iocp)); 5529 5530 case BGE_PHY_RESET: 5531 return (IOC_RESTART_ACK); 5532 5533 case BGE_SOFT_RESET: 5534 case BGE_HARD_RESET: 5535 /* 5536 * Reset and reinitialise the 570x hardware 5537 */ 5538 bgep->bge_chip_state = BGE_CHIP_FAULT; 5539 ddi_trigger_softintr(bgep->factotum_id); 5540 (void) bge_restart(bgep, cmd == BGE_HARD_RESET); 5541 return (IOC_ACK); 5542 } 5543 5544 /* NOTREACHED */ 5545 } 5546 5547 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 5548 5549 static enum ioc_reply bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5550 struct iocblk *iocp); 5551 #pragma no_inline(bge_mii_ioctl) 5552 5553 static enum ioc_reply 5554 bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5555 { 5556 struct bge_mii_rw *miirwp; 5557 5558 /* 5559 * Validate format of ioctl 5560 */ 5561 if (iocp->ioc_count != sizeof (struct bge_mii_rw)) 5562 return (IOC_INVAL); 5563 if (mp->b_cont == NULL) 5564 return (IOC_INVAL); 5565 miirwp = (void *)mp->b_cont->b_rptr; 5566 5567 /* 5568 * Validate request parameters ... 5569 */ 5570 if (miirwp->mii_reg > MII_MAXREG) 5571 return (IOC_INVAL); 5572 5573 switch (cmd) { 5574 default: 5575 /* NOTREACHED */ 5576 bge_error(bgep, "bge_mii_ioctl: invalid cmd 0x%x", cmd); 5577 return (IOC_INVAL); 5578 5579 case BGE_MII_READ: 5580 miirwp->mii_data = bge_mii_get16(bgep, miirwp->mii_reg); 5581 return (IOC_REPLY); 5582 5583 case BGE_MII_WRITE: 5584 bge_mii_put16(bgep, miirwp->mii_reg, miirwp->mii_data); 5585 return (IOC_ACK); 5586 } 5587 5588 /* NOTREACHED */ 5589 } 5590 5591 #if BGE_SEE_IO32 5592 5593 static enum ioc_reply bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5594 struct iocblk *iocp); 5595 #pragma no_inline(bge_see_ioctl) 5596 5597 static enum ioc_reply 5598 bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5599 { 5600 struct bge_see_rw *seerwp; 5601 5602 /* 5603 * Validate format of ioctl 5604 */ 5605 if (iocp->ioc_count != sizeof (struct bge_see_rw)) 5606 return (IOC_INVAL); 5607 if (mp->b_cont == NULL) 5608 return (IOC_INVAL); 5609 seerwp = (void *)mp->b_cont->b_rptr; 5610 5611 /* 5612 * Validate request parameters ... 5613 */ 5614 if (seerwp->see_addr & ~SEEPROM_DEV_AND_ADDR_MASK) 5615 return (IOC_INVAL); 5616 5617 switch (cmd) { 5618 default: 5619 /* NOTREACHED */ 5620 bge_error(bgep, "bge_see_ioctl: invalid cmd 0x%x", cmd); 5621 return (IOC_INVAL); 5622 5623 case BGE_SEE_READ: 5624 case BGE_SEE_WRITE: 5625 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 5626 seerwp->see_addr, &seerwp->see_data); 5627 return (IOC_REPLY); 5628 } 5629 5630 /* NOTREACHED */ 5631 } 5632 5633 #endif /* BGE_SEE_IO32 */ 5634 5635 #if BGE_FLASH_IO32 5636 5637 static enum ioc_reply bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5638 struct iocblk *iocp); 5639 #pragma no_inline(bge_flash_ioctl) 5640 5641 static enum ioc_reply 5642 bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5643 { 5644 struct bge_flash_rw *flashrwp; 5645 5646 /* 5647 * Validate format of ioctl 5648 */ 5649 if (iocp->ioc_count != sizeof (struct bge_flash_rw)) 5650 return (IOC_INVAL); 5651 if (mp->b_cont == NULL) 5652 return (IOC_INVAL); 5653 flashrwp = (void *)mp->b_cont->b_rptr; 5654 5655 /* 5656 * Validate request parameters ... 5657 */ 5658 if (flashrwp->flash_addr & ~NVM_FLASH_ADDR_MASK) 5659 return (IOC_INVAL); 5660 5661 switch (cmd) { 5662 default: 5663 /* NOTREACHED */ 5664 bge_error(bgep, "bge_flash_ioctl: invalid cmd 0x%x", cmd); 5665 return (IOC_INVAL); 5666 5667 case BGE_FLASH_READ: 5668 case BGE_FLASH_WRITE: 5669 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 5670 flashrwp->flash_addr, &flashrwp->flash_data); 5671 return (IOC_REPLY); 5672 } 5673 5674 /* NOTREACHED */ 5675 } 5676 5677 #endif /* BGE_FLASH_IO32 */ 5678 5679 enum ioc_reply bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, 5680 struct iocblk *iocp); 5681 #pragma no_inline(bge_chip_ioctl) 5682 5683 enum ioc_reply 5684 bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 5685 { 5686 int cmd; 5687 5688 BGE_TRACE(("bge_chip_ioctl($%p, $%p, $%p, $%p)", 5689 (void *)bgep, (void *)wq, (void *)mp, (void *)iocp)); 5690 5691 ASSERT(mutex_owned(bgep->genlock)); 5692 5693 cmd = iocp->ioc_cmd; 5694 switch (cmd) { 5695 default: 5696 /* NOTREACHED */ 5697 bge_error(bgep, "bge_chip_ioctl: invalid cmd 0x%x", cmd); 5698 return (IOC_INVAL); 5699 5700 case BGE_DIAG: 5701 case BGE_PEEK: 5702 case BGE_POKE: 5703 case BGE_PHY_RESET: 5704 case BGE_SOFT_RESET: 5705 case BGE_HARD_RESET: 5706 #if BGE_DEBUGGING || BGE_DO_PPIO 5707 return (bge_diag_ioctl(bgep, cmd, mp, iocp)); 5708 #else 5709 return (IOC_INVAL); 5710 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 5711 5712 case BGE_MII_READ: 5713 case BGE_MII_WRITE: 5714 return (bge_mii_ioctl(bgep, cmd, mp, iocp)); 5715 5716 #if BGE_SEE_IO32 5717 case BGE_SEE_READ: 5718 case BGE_SEE_WRITE: 5719 return (bge_see_ioctl(bgep, cmd, mp, iocp)); 5720 #endif /* BGE_SEE_IO32 */ 5721 5722 #if BGE_FLASH_IO32 5723 case BGE_FLASH_READ: 5724 case BGE_FLASH_WRITE: 5725 return (bge_flash_ioctl(bgep, cmd, mp, iocp)); 5726 #endif /* BGE_FLASH_IO32 */ 5727 } 5728 5729 /* NOTREACHED */ 5730 } 5731 5732 /* ARGSUSED */ 5733 void 5734 bge_chip_blank(void *arg, time_t ticks, uint_t count, int flag) 5735 { 5736 recv_ring_t *rrp = arg; 5737 bge_t *bgep = rrp->bgep; 5738 5739 mutex_enter(bgep->genlock); 5740 rrp->poll_flag = flag; 5741 #ifdef NOT_YET 5742 /* 5743 * XXX-Sunay: Since most broadcom cards support only one 5744 * interrupt but multiple rx rings, we can't disable the 5745 * physical interrupt. This need to be done via capability 5746 * negotiation depending on the NIC. 5747 */ 5748 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, ticks); 5749 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, count); 5750 #endif 5751 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5752 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 5753 mutex_exit(bgep->genlock); 5754 } 5755 5756 #ifdef BGE_IPMI_ASF 5757 5758 uint32_t 5759 bge_nic_read32(bge_t *bgep, bge_regno_t addr) 5760 { 5761 uint32_t data; 5762 5763 #ifndef __sparc 5764 if (!bgep->asf_wordswapped) { 5765 /* a workaround word swap error */ 5766 if (addr & 4) 5767 addr = addr - 4; 5768 else 5769 addr = addr + 4; 5770 } 5771 #else 5772 if (DEVICE_5717_SERIES_CHIPSETS(bgep)) 5773 addr = LE_32(addr); 5774 #endif 5775 5776 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr); 5777 data = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR); 5778 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0); 5779 5780 data = LE_32(data); 5781 5782 BGE_DEBUG(("bge_nic_read32($%p, 0x%x) => 0x%x", 5783 (void *)bgep, addr, data)); 5784 5785 return (data); 5786 } 5787 5788 void 5789 bge_asf_update_status(bge_t *bgep) 5790 { 5791 uint32_t event; 5792 5793 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_ALIVE); 5794 bge_nic_put32(bgep, BGE_CMD_LENGTH_MAILBOX, 4); 5795 bge_nic_put32(bgep, BGE_CMD_DATA_MAILBOX, 3); 5796 5797 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5798 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 5799 } 5800 5801 5802 /* 5803 * The driver is supposed to notify ASF that the OS is still running 5804 * every three seconds, otherwise the management server may attempt 5805 * to reboot the machine. If it hasn't actually failed, this is 5806 * not a desirable result. However, this isn't running as a real-time 5807 * thread, and even if it were, it might not be able to generate the 5808 * heartbeat in a timely manner due to system load. As it isn't a 5809 * significant strain on the machine, we will set the interval to half 5810 * of the required value. 5811 */ 5812 void 5813 bge_asf_heartbeat(void *arg) 5814 { 5815 bge_t *bgep = (bge_t *)arg; 5816 5817 mutex_enter(bgep->genlock); 5818 bge_asf_update_status((bge_t *)bgep); 5819 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5820 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 5821 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) 5822 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 5823 mutex_exit(bgep->genlock); 5824 ((bge_t *)bgep)->asf_timeout_id = timeout(bge_asf_heartbeat, bgep, 5825 drv_usectohz(BGE_ASF_HEARTBEAT_INTERVAL)); 5826 } 5827 5828 5829 void 5830 bge_asf_stop_timer(bge_t *bgep) 5831 { 5832 timeout_id_t tmp_id = 0; 5833 5834 while ((bgep->asf_timeout_id != 0) && 5835 (tmp_id != bgep->asf_timeout_id)) { 5836 tmp_id = bgep->asf_timeout_id; 5837 (void) untimeout(tmp_id); 5838 } 5839 bgep->asf_timeout_id = 0; 5840 } 5841 5842 5843 5844 /* 5845 * This function should be placed at the earliest position of bge_attach(). 5846 */ 5847 void 5848 bge_asf_get_config(bge_t *bgep) 5849 { 5850 uint32_t nicsig; 5851 uint32_t niccfg; 5852 5853 bgep->asf_enabled = B_FALSE; 5854 nicsig = bge_nic_read32(bgep, BGE_NIC_DATA_SIG_ADDR); 5855 if (nicsig == BGE_NIC_DATA_SIG) { 5856 niccfg = bge_nic_read32(bgep, BGE_NIC_DATA_NIC_CFG_ADDR); 5857 if (niccfg & BGE_NIC_CFG_ENABLE_ASF) 5858 /* 5859 * Here, we don't consider BAXTER, because BGE haven't 5860 * supported BAXTER (that is 5752). Also, as I know, 5861 * BAXTER doesn't support ASF feature. 5862 */ 5863 bgep->asf_enabled = B_TRUE; 5864 else 5865 bgep->asf_enabled = B_FALSE; 5866 } else 5867 bgep->asf_enabled = B_FALSE; 5868 } 5869 5870 5871 void 5872 bge_asf_pre_reset_operations(bge_t *bgep, uint32_t mode) 5873 { 5874 uint32_t tries; 5875 uint32_t event; 5876 5877 ASSERT(bgep->asf_enabled); 5878 5879 /* Issues "pause firmware" command and wait for ACK */ 5880 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_PAUSE_FW); 5881 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5882 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 5883 5884 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5885 tries = 0; 5886 while ((event & RRER_ASF_EVENT) && (tries < 100)) { 5887 drv_usecwait(1); 5888 tries ++; 5889 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5890 } 5891 5892 bge_nic_put32(bgep, BGE_FIRMWARE_MAILBOX, 5893 BGE_MAGIC_NUM_FIRMWARE_INIT_DONE); 5894 5895 if (bgep->asf_newhandshake) { 5896 switch (mode) { 5897 case BGE_INIT_RESET: 5898 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5899 BGE_DRV_STATE_START); 5900 break; 5901 case BGE_SHUTDOWN_RESET: 5902 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5903 BGE_DRV_STATE_UNLOAD); 5904 break; 5905 case BGE_SUSPEND_RESET: 5906 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5907 BGE_DRV_STATE_SUSPEND); 5908 break; 5909 default: 5910 break; 5911 } 5912 } 5913 } 5914 5915 5916 void 5917 bge_asf_post_reset_old_mode(bge_t *bgep, uint32_t mode) 5918 { 5919 switch (mode) { 5920 case BGE_INIT_RESET: 5921 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5922 BGE_DRV_STATE_START); 5923 break; 5924 case BGE_SHUTDOWN_RESET: 5925 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5926 BGE_DRV_STATE_UNLOAD); 5927 break; 5928 case BGE_SUSPEND_RESET: 5929 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5930 BGE_DRV_STATE_SUSPEND); 5931 break; 5932 default: 5933 break; 5934 } 5935 } 5936 5937 5938 void 5939 bge_asf_post_reset_new_mode(bge_t *bgep, uint32_t mode) 5940 { 5941 switch (mode) { 5942 case BGE_INIT_RESET: 5943 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5944 BGE_DRV_STATE_START_DONE); 5945 break; 5946 case BGE_SHUTDOWN_RESET: 5947 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5948 BGE_DRV_STATE_UNLOAD_DONE); 5949 break; 5950 default: 5951 break; 5952 } 5953 } 5954 5955 #endif /* BGE_IPMI_ASF */ 5956