1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #include "bge_impl.h" 28 29 #define PIO_ADDR(bgep, offset) ((void *)((caddr_t)(bgep)->io_regs+(offset))) 30 31 /* 32 * Future features ... ? 33 */ 34 #define BGE_CFG_IO8 1 /* 8/16-bit cfg space BIS/BIC */ 35 #define BGE_IND_IO32 1 /* indirect access code */ 36 #define BGE_SEE_IO32 1 /* SEEPROM access code */ 37 #define BGE_FLASH_IO32 1 /* FLASH access code */ 38 39 /* 40 * BGE MSI tunable: 41 * 42 * By default MSI is enabled on all supported platforms but it is disabled 43 * for some Broadcom chips due to known MSI hardware issues. Currently MSI 44 * is enabled only for 5714C A2 and 5715C A2 broadcom chips. 45 */ 46 boolean_t bge_enable_msi = B_TRUE; 47 48 /* 49 * PCI-X/PCI-E relaxed ordering tunable for OS/Nexus driver 50 */ 51 boolean_t bge_relaxed_ordering = B_TRUE; 52 53 /* 54 * Property names 55 */ 56 static char knownids_propname[] = "bge-known-subsystems"; 57 58 /* 59 * Patchable globals: 60 * 61 * bge_autorecover 62 * Enables/disables automatic recovery after fault detection 63 * 64 * bge_mlcr_default 65 * Value to program into the MLCR; controls the chip's GPIO pins 66 * 67 * bge_dma_{rd,wr}prio 68 * Relative priorities of DMA reads & DMA writes respectively. 69 * These may each be patched to any value 0-3. Equal values 70 * will give "fair" (round-robin) arbitration for PCI access. 71 * Unequal values will give one or the other function priority. 72 * 73 * bge_dma_rwctrl 74 * Value to put in the Read/Write DMA control register. See 75 * the Broadcom PRM for things you can fiddle with in this 76 * register ... 77 * 78 * bge_{tx,rx}_{count,ticks}_{norm,intr} 79 * Send/receive interrupt coalescing parameters. Counts are 80 * #s of descriptors, ticks are in microseconds. *norm* values 81 * apply between status updates/interrupts; the *intr* values 82 * refer to the 'during-interrupt' versions - see the PRM. 83 * 84 * NOTE: these values have been determined by measurement. They 85 * differ significantly from the values recommended in the PRM. 86 */ 87 static uint32_t bge_autorecover = 1; 88 static uint32_t bge_mlcr_default_5714 = MLCR_DEFAULT_5714; 89 90 static uint32_t bge_dma_rdprio = 1; 91 static uint32_t bge_dma_wrprio = 0; 92 static uint32_t bge_dma_rwctrl = PDRWCR_VAR_DEFAULT; 93 static uint32_t bge_dma_rwctrl_5721 = PDRWCR_VAR_5721; 94 static uint32_t bge_dma_rwctrl_5714 = PDRWCR_VAR_5714; 95 static uint32_t bge_dma_rwctrl_5715 = PDRWCR_VAR_5715; 96 97 uint32_t bge_rx_ticks_norm = 128; 98 uint32_t bge_tx_ticks_norm = 2048; /* 8 for FJ2+ !?!? */ 99 uint32_t bge_rx_count_norm = 8; 100 uint32_t bge_tx_count_norm = 128; 101 102 static uint32_t bge_rx_ticks_intr = 128; 103 static uint32_t bge_tx_ticks_intr = 0; /* 8 for FJ2+ !?!? */ 104 static uint32_t bge_rx_count_intr = 2; 105 static uint32_t bge_tx_count_intr = 0; 106 107 /* 108 * Memory pool configuration parameters. 109 * 110 * These are generally specific to each member of the chip family, since 111 * each one may have a different memory size/configuration. 112 * 113 * Setting the mbuf pool length for a specific type of chip to 0 inhibits 114 * the driver from programming the various registers; instead they are left 115 * at their hardware defaults. This is the preferred option for later chips 116 * (5705+), whereas the older chips *required* these registers to be set, 117 * since the h/w default was 0 ;-( 118 */ 119 static uint32_t bge_mbuf_pool_base = MBUF_POOL_BASE_DEFAULT; 120 static uint32_t bge_mbuf_pool_base_5704 = MBUF_POOL_BASE_5704; 121 static uint32_t bge_mbuf_pool_base_5705 = MBUF_POOL_BASE_5705; 122 static uint32_t bge_mbuf_pool_base_5721 = MBUF_POOL_BASE_5721; 123 static uint32_t bge_mbuf_pool_len = MBUF_POOL_LENGTH_DEFAULT; 124 static uint32_t bge_mbuf_pool_len_5704 = MBUF_POOL_LENGTH_5704; 125 static uint32_t bge_mbuf_pool_len_5705 = 0; /* use h/w default */ 126 static uint32_t bge_mbuf_pool_len_5721 = 0; 127 128 /* 129 * Various high and low water marks, thresholds, etc ... 130 * 131 * Note: these are taken from revision 7 of the PRM, and some are different 132 * from both the values in earlier PRMs *and* those determined experimentally 133 * and used in earlier versions of this driver ... 134 */ 135 static uint32_t bge_mbuf_hi_water = MBUF_HIWAT_DEFAULT; 136 static uint32_t bge_mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_DEFAULT; 137 static uint32_t bge_mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_DEFAULT; 138 139 static uint32_t bge_dmad_lo_water = DMAD_POOL_LOWAT_DEFAULT; 140 static uint32_t bge_dmad_hi_water = DMAD_POOL_HIWAT_DEFAULT; 141 static uint32_t bge_lowat_recv_frames = LOWAT_MAX_RECV_FRAMES_DEFAULT; 142 143 static uint32_t bge_replenish_std = STD_RCV_BD_REPLENISH_DEFAULT; 144 static uint32_t bge_replenish_mini = MINI_RCV_BD_REPLENISH_DEFAULT; 145 static uint32_t bge_replenish_jumbo = JUMBO_RCV_BD_REPLENISH_DEFAULT; 146 147 static uint32_t bge_watchdog_count = 1 << 16; 148 static uint16_t bge_dma_miss_limit = 20; 149 150 static uint32_t bge_stop_start_on_sync = 0; 151 152 boolean_t bge_jumbo_enable = B_TRUE; 153 154 /* 155 * bge_intr_max_loop controls the maximum loop number within bge_intr. 156 * When loading NIC with heavy network traffic, it is useful. 157 * Increasing this value could have positive effect to throughput, 158 * but it might also increase ticks of a bge ISR stick on CPU, which might 159 * lead to bad UI interactive experience. So tune this with caution. 160 */ 161 static int bge_intr_max_loop = 1; 162 163 /* 164 * ========== Low-level chip & ring buffer manipulation ========== 165 */ 166 167 #define BGE_DBG BGE_DBG_REGS /* debug flag for this code */ 168 169 170 /* 171 * Config space read-modify-write routines 172 */ 173 174 #if BGE_CFG_IO8 175 176 static void bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits); 177 #pragma inline(bge_cfg_clr16) 178 179 static void 180 bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits) 181 { 182 uint16_t regval; 183 184 BGE_TRACE(("bge_cfg_clr16($%p, 0x%lx, 0x%x)", 185 (void *)bgep, regno, bits)); 186 187 regval = pci_config_get16(bgep->cfg_handle, regno); 188 189 BGE_DEBUG(("bge_cfg_clr16($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 190 (void *)bgep, regno, bits, regval, regval & ~bits)); 191 192 regval &= ~bits; 193 pci_config_put16(bgep->cfg_handle, regno, regval); 194 } 195 196 #endif /* BGE_CFG_IO8 */ 197 198 static void bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 199 #pragma inline(bge_cfg_clr32) 200 201 static void 202 bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 203 { 204 uint32_t regval; 205 206 BGE_TRACE(("bge_cfg_clr32($%p, 0x%lx, 0x%x)", 207 (void *)bgep, regno, bits)); 208 209 regval = pci_config_get32(bgep->cfg_handle, regno); 210 211 BGE_DEBUG(("bge_cfg_clr32($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 212 (void *)bgep, regno, bits, regval, regval & ~bits)); 213 214 regval &= ~bits; 215 pci_config_put32(bgep->cfg_handle, regno, regval); 216 } 217 218 #if BGE_IND_IO32 219 220 /* 221 * Indirect access to registers & RISC scratchpads, using config space 222 * accesses only. 223 * 224 * This isn't currently used, but someday we might want to use it for 225 * restoring the Subsystem Device/Vendor registers (which aren't directly 226 * writable in Config Space), or for downloading firmware into the RISCs 227 * 228 * In any case there are endian issues to be resolved before this code is 229 * enabled; the bizarre way that bytes get twisted by this chip AND by 230 * the PCI bridge in SPARC systems mean that we shouldn't enable it until 231 * it's been thoroughly tested for all access sizes on all supported 232 * architectures (SPARC *and* x86!). 233 */ 234 uint32_t bge_ind_get32(bge_t *bgep, bge_regno_t regno); 235 #pragma inline(bge_ind_get32) 236 237 uint32_t 238 bge_ind_get32(bge_t *bgep, bge_regno_t regno) 239 { 240 uint32_t val; 241 242 BGE_TRACE(("bge_ind_get32($%p, 0x%lx)", (void *)bgep, regno)); 243 244 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 245 val = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_RIADR); 246 247 BGE_DEBUG(("bge_ind_get32($%p, 0x%lx) => 0x%x", 248 (void *)bgep, regno, val)); 249 250 val = LE_32(val); 251 252 return (val); 253 } 254 255 void bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val); 256 #pragma inline(bge_ind_put32) 257 258 void 259 bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val) 260 { 261 BGE_TRACE(("bge_ind_put32($%p, 0x%lx, 0x%x)", 262 (void *)bgep, regno, val)); 263 264 val = LE_32(val); 265 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 266 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIADR, val); 267 } 268 269 #endif /* BGE_IND_IO32 */ 270 271 #if BGE_DEBUGGING 272 273 static void bge_pci_check(bge_t *bgep); 274 #pragma no_inline(bge_pci_check) 275 276 static void 277 bge_pci_check(bge_t *bgep) 278 { 279 uint16_t pcistatus; 280 281 pcistatus = pci_config_get16(bgep->cfg_handle, PCI_CONF_STAT); 282 if ((pcistatus & (PCI_STAT_R_MAST_AB | PCI_STAT_R_TARG_AB)) != 0) 283 BGE_DEBUG(("bge_pci_check($%p): PCI status 0x%x", 284 (void *)bgep, pcistatus)); 285 } 286 287 #endif /* BGE_DEBUGGING */ 288 289 /* 290 * Perform first-stage chip (re-)initialisation, using only config-space 291 * accesses: 292 * 293 * + Read the vendor/device/revision/subsystem/cache-line-size registers, 294 * returning the data in the structure pointed to by <idp>. 295 * + Configure the target-mode endianness (swap) options. 296 * + Disable interrupts and enable Memory Space accesses. 297 * + Enable or disable Bus Mastering according to the <enable_dma> flag. 298 * 299 * This sequence is adapted from Broadcom document 570X-PG102-R, 300 * page 102, steps 1-3, 6-8 and 11-13. The omitted parts of the sequence 301 * are 4 and 5 (Reset Core and wait) which are handled elsewhere. 302 * 303 * This function MUST be called before any non-config-space accesses 304 * are made; on this first call <enable_dma> is B_FALSE, and it 305 * effectively performs steps 3-1(!) of the initialisation sequence 306 * (the rest are not required but should be harmless). 307 * 308 * It MUST also be called after a chip reset, as this disables 309 * Memory Space cycles! In this case, <enable_dma> is B_TRUE, and 310 * it is effectively performing steps 6-8. 311 */ 312 void bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma); 313 #pragma no_inline(bge_chip_cfg_init) 314 315 void 316 bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma) 317 { 318 ddi_acc_handle_t handle; 319 uint16_t command; 320 uint32_t mhcr; 321 uint16_t value16; 322 int i; 323 324 BGE_TRACE(("bge_chip_cfg_init($%p, $%p, %d)", 325 (void *)bgep, (void *)cidp, enable_dma)); 326 327 /* 328 * Step 3: save PCI cache line size and subsystem vendor ID 329 * 330 * Read all the config-space registers that characterise the 331 * chip, specifically vendor/device/revision/subsystem vendor 332 * and subsystem device id. We expect (but don't check) that 333 * (vendor == VENDOR_ID_BROADCOM) && (device == DEVICE_ID_5704) 334 * 335 * Also save all bus-transaction related registers (cache-line 336 * size, bus-grant/latency parameters, etc). Some of these are 337 * cleared by reset, so we'll have to restore them later. This 338 * comes from the Broadcom document 570X-PG102-R ... 339 * 340 * Note: Broadcom document 570X-PG102-R seems to be in error 341 * here w.r.t. the offsets of the Subsystem Vendor ID and 342 * Subsystem (Device) ID registers, which are the opposite way 343 * round according to the PCI standard. For good measure, we 344 * save/restore both anyway. 345 */ 346 handle = bgep->cfg_handle; 347 348 mhcr = pci_config_get32(handle, PCI_CONF_BGE_MHCR); 349 cidp->asic_rev = mhcr & MHCR_CHIP_REV_MASK; 350 cidp->businfo = pci_config_get32(handle, PCI_CONF_BGE_PCISTATE); 351 cidp->command = pci_config_get16(handle, PCI_CONF_COMM); 352 353 cidp->vendor = pci_config_get16(handle, PCI_CONF_VENID); 354 cidp->device = pci_config_get16(handle, PCI_CONF_DEVID); 355 cidp->subven = pci_config_get16(handle, PCI_CONF_SUBVENID); 356 cidp->subdev = pci_config_get16(handle, PCI_CONF_SUBSYSID); 357 cidp->revision = pci_config_get8(handle, PCI_CONF_REVID); 358 cidp->clsize = pci_config_get8(handle, PCI_CONF_CACHE_LINESZ); 359 cidp->latency = pci_config_get8(handle, PCI_CONF_LATENCY_TIMER); 360 361 BGE_DEBUG(("bge_chip_cfg_init: %s bus is %s and %s; #INTA is %s", 362 cidp->businfo & PCISTATE_BUS_IS_PCI ? "PCI" : "PCI-X", 363 cidp->businfo & PCISTATE_BUS_IS_FAST ? "fast" : "slow", 364 cidp->businfo & PCISTATE_BUS_IS_32_BIT ? "narrow" : "wide", 365 cidp->businfo & PCISTATE_INTA_STATE ? "high" : "low")); 366 BGE_DEBUG(("bge_chip_cfg_init: vendor 0x%x device 0x%x revision 0x%x", 367 cidp->vendor, cidp->device, cidp->revision)); 368 BGE_DEBUG(("bge_chip_cfg_init: subven 0x%x subdev 0x%x asic_rev 0x%x", 369 cidp->subven, cidp->subdev, cidp->asic_rev)); 370 BGE_DEBUG(("bge_chip_cfg_init: clsize %d latency %d command 0x%x", 371 cidp->clsize, cidp->latency, cidp->command)); 372 373 /* 374 * Step 2 (also step 6): disable and clear interrupts. 375 * Steps 11-13: configure PIO endianness options, and enable 376 * indirect register access. We'll also select any other 377 * options controlled by the MHCR (e.g. tagged status, mask 378 * interrupt mode) at this stage ... 379 * 380 * Note: internally, the chip is 64-bit and BIG-endian, but 381 * since it talks to the host over a (LITTLE-endian) PCI bus, 382 * it normally swaps bytes around at the PCI interface. 383 * However, the PCI host bridge on SPARC systems normally 384 * swaps the byte lanes around too, since SPARCs are also 385 * BIG-endian. So it turns out that on SPARC, the right 386 * option is to tell the chip to swap (and the host bridge 387 * will swap back again), whereas on x86 we ask the chip 388 * NOT to swap, so the natural little-endianness of the 389 * PCI bus is assumed. Then the only thing that doesn't 390 * automatically work right is access to an 8-byte register 391 * by a little-endian host; but we don't want to set the 392 * MHCR_ENABLE_REGISTER_WORD_SWAP bit because then 4-byte 393 * accesses don't go where expected ;-( So we live with 394 * that, and perform word-swaps in software in the few cases 395 * where a chip register is defined as an 8-byte value -- 396 * see the code below for details ... 397 * 398 * Note: the meaning of the 'MASK_INTERRUPT_MODE' bit isn't 399 * very clear in the register description in the PRM, but 400 * Broadcom document 570X-PG104-R page 248 explains a little 401 * more (under "Broadcom Mask Mode"). The bit changes the way 402 * the MASK_PCI_INT_OUTPUT bit works: with MASK_INTERRUPT_MODE 403 * clear, the chip interprets MASK_PCI_INT_OUTPUT in the same 404 * way as the 5700 did, which isn't very convenient. Setting 405 * the MASK_INTERRUPT_MODE bit makes the MASK_PCI_INT_OUTPUT 406 * bit do just what its name says -- MASK the PCI #INTA output 407 * (i.e. deassert the signal at the pin) leaving all internal 408 * state unchanged. This is much more convenient for our 409 * interrupt handler, so we set MASK_INTERRUPT_MODE here. 410 * 411 * Note: the inconvenient semantics of the interrupt mailbox 412 * (nonzero disables and acknowledges/clears the interrupt, 413 * zero enables AND CLEARS it) would make race conditions 414 * likely in the interrupt handler: 415 * 416 * (1) acknowledge & disable interrupts 417 * (2) while (more to do) 418 * process packets 419 * (3) enable interrupts -- also clears pending 420 * 421 * If the chip received more packets and internally generated 422 * an interrupt between the check at (2) and the mbox write 423 * at (3), this interrupt would be lost :-( 424 * 425 * The best way to avoid this is to use TAGGED STATUS mode, 426 * where the chip includes a unique tag in each status block 427 * update, and the host, when re-enabling interrupts, passes 428 * the last tag it saw back to the chip; then the chip can 429 * see whether the host is truly up to date, and regenerate 430 * its interrupt if not. 431 */ 432 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 433 MHCR_ENABLE_TAGGED_STATUS_MODE | 434 MHCR_MASK_INTERRUPT_MODE | 435 MHCR_CLEAR_INTERRUPT_INTA; 436 437 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 438 mhcr |= MHCR_MASK_PCI_INT_OUTPUT; 439 440 #ifdef _BIG_ENDIAN 441 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 442 #endif /* _BIG_ENDIAN */ 443 444 pci_config_put32(handle, PCI_CONF_BGE_MHCR, mhcr); 445 446 #ifdef BGE_IPMI_ASF 447 bgep->asf_wordswapped = B_FALSE; 448 #endif 449 /* 450 * Step 1 (also step 7): Enable PCI Memory Space accesses 451 * Disable Memory Write/Invalidate 452 * Enable or disable Bus Mastering 453 * 454 * Note that all other bits are taken from the original value saved 455 * the first time through here, rather than from the current register 456 * value, 'cos that will have been cleared by a soft RESET since. 457 * In this way we preserve the OBP/nexus-parent's preferred settings 458 * of the parity-error and system-error enable bits across multiple 459 * chip RESETs. 460 */ 461 command = bgep->chipid.command | PCI_COMM_MAE; 462 command &= ~(PCI_COMM_ME|PCI_COMM_MEMWR_INVAL); 463 if (enable_dma) 464 command |= PCI_COMM_ME; 465 /* 466 * on BCM5714 revision A0, false parity error gets generated 467 * due to a logic bug. Provide a workaround by disabling parity 468 * error. 469 */ 470 if (((cidp->device == DEVICE_ID_5714C) || 471 (cidp->device == DEVICE_ID_5714S)) && 472 (cidp->revision == REVISION_ID_5714_A0)) { 473 command &= ~PCI_COMM_PARITY_DETECT; 474 } 475 pci_config_put16(handle, PCI_CONF_COMM, command); 476 477 /* 478 * On some PCI-E device, there were instances when 479 * the device was still link training. 480 */ 481 if (bgep->chipid.pci_type == BGE_PCI_E) { 482 i = 0; 483 value16 = pci_config_get16(handle, PCI_CONF_COMM); 484 while ((value16 != command) && (i < 100)) { 485 drv_usecwait(200); 486 value16 = pci_config_get16(handle, PCI_CONF_COMM); 487 ++i; 488 } 489 } 490 491 /* 492 * Clear any remaining error status bits 493 */ 494 pci_config_put16(handle, PCI_CONF_STAT, ~0); 495 496 /* 497 * Do following if and only if the device is NOT BCM5714C OR 498 * BCM5715C 499 */ 500 if (!((cidp->device == DEVICE_ID_5714C) || 501 (cidp->device == DEVICE_ID_5715C))) { 502 /* 503 * Make sure these indirect-access registers are sane 504 * rather than random after power-up or reset 505 */ 506 pci_config_put32(handle, PCI_CONF_BGE_RIAAR, 0); 507 pci_config_put32(handle, PCI_CONF_BGE_MWBAR, 0); 508 } 509 /* 510 * Step 8: Disable PCI-X/PCI-E Relaxed Ordering 511 */ 512 bge_cfg_clr16(bgep, PCIX_CONF_COMM, PCIX_COMM_RELAXED); 513 514 if (cidp->pci_type == BGE_PCI_E) 515 bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL, 516 DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED); 517 } 518 519 #ifdef __amd64 520 /* 521 * Distinguish CPU types 522 * 523 * These use to distinguish AMD64 or Intel EM64T of CPU running mode. 524 * If CPU runs on Intel EM64T mode,the 64bit operation cannot works fine 525 * for PCI-Express based network interface card. This is the work-around 526 * for those nics. 527 */ 528 static boolean_t bge_get_em64t_type(void); 529 #pragma inline(bge_get_em64t_type) 530 531 static boolean_t 532 bge_get_em64t_type(void) 533 { 534 535 return (x86_vendor == X86_VENDOR_Intel); 536 } 537 #endif 538 539 /* 540 * Operating register get/set access routines 541 */ 542 543 uint32_t bge_reg_get32(bge_t *bgep, bge_regno_t regno); 544 #pragma inline(bge_reg_get32) 545 546 uint32_t 547 bge_reg_get32(bge_t *bgep, bge_regno_t regno) 548 { 549 BGE_TRACE(("bge_reg_get32($%p, 0x%lx)", 550 (void *)bgep, regno)); 551 552 return (ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno))); 553 } 554 555 void bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data); 556 #pragma inline(bge_reg_put32) 557 558 void 559 bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data) 560 { 561 BGE_TRACE(("bge_reg_put32($%p, 0x%lx, 0x%x)", 562 (void *)bgep, regno, data)); 563 564 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), data); 565 BGE_PCICHK(bgep); 566 } 567 568 void bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 569 #pragma inline(bge_reg_set32) 570 571 void 572 bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 573 { 574 uint32_t regval; 575 576 BGE_TRACE(("bge_reg_set32($%p, 0x%lx, 0x%x)", 577 (void *)bgep, regno, bits)); 578 579 regval = bge_reg_get32(bgep, regno); 580 regval |= bits; 581 bge_reg_put32(bgep, regno, regval); 582 } 583 584 void bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 585 #pragma inline(bge_reg_clr32) 586 587 void 588 bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 589 { 590 uint32_t regval; 591 592 BGE_TRACE(("bge_reg_clr32($%p, 0x%lx, 0x%x)", 593 (void *)bgep, regno, bits)); 594 595 regval = bge_reg_get32(bgep, regno); 596 regval &= ~bits; 597 bge_reg_put32(bgep, regno, regval); 598 } 599 600 static uint64_t bge_reg_get64(bge_t *bgep, bge_regno_t regno); 601 #pragma inline(bge_reg_get64) 602 603 static uint64_t 604 bge_reg_get64(bge_t *bgep, bge_regno_t regno) 605 { 606 uint64_t regval; 607 608 #ifdef __amd64 609 if (bge_get_em64t_type()) { 610 regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4)); 611 regval <<= 32; 612 regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 613 } else { 614 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 615 } 616 #else 617 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 618 #endif 619 620 #ifdef _LITTLE_ENDIAN 621 regval = (regval >> 32) | (regval << 32); 622 #endif /* _LITTLE_ENDIAN */ 623 624 BGE_TRACE(("bge_reg_get64($%p, 0x%lx) = 0x%016llx", 625 (void *)bgep, regno, regval)); 626 627 return (regval); 628 } 629 630 static void bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data); 631 #pragma inline(bge_reg_put64) 632 633 static void 634 bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data) 635 { 636 BGE_TRACE(("bge_reg_put64($%p, 0x%lx, 0x%016llx)", 637 (void *)bgep, regno, data)); 638 639 #ifdef _LITTLE_ENDIAN 640 data = ((data >> 32) | (data << 32)); 641 #endif /* _LITTLE_ENDIAN */ 642 643 #ifdef __amd64 644 if (bge_get_em64t_type()) { 645 ddi_put32(bgep->io_handle, 646 PIO_ADDR(bgep, regno), (uint32_t)data); 647 BGE_PCICHK(bgep); 648 ddi_put32(bgep->io_handle, 649 PIO_ADDR(bgep, regno + 4), (uint32_t)(data >> 32)); 650 651 } else { 652 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 653 } 654 #else 655 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 656 #endif 657 658 BGE_PCICHK(bgep); 659 } 660 661 /* 662 * The DDI doesn't provide get/put functions for 128 bit data 663 * so we put RCBs out as two 64-bit chunks instead. 664 */ 665 static void bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 666 #pragma inline(bge_reg_putrcb) 667 668 static void 669 bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 670 { 671 uint64_t *p; 672 673 BGE_TRACE(("bge_reg_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 674 (void *)bgep, addr, rcbp->host_ring_addr, 675 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 676 677 ASSERT((addr % sizeof (*rcbp)) == 0); 678 679 p = (void *)rcbp; 680 bge_reg_put64(bgep, addr, *p++); 681 bge_reg_put64(bgep, addr+8, *p); 682 } 683 684 void bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data); 685 #pragma inline(bge_mbx_put) 686 687 void 688 bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data) 689 { 690 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) 691 regno += INTERRUPT_LP_MBOX_0_REG - INTERRUPT_MBOX_0_REG + 4; 692 693 BGE_TRACE(("bge_mbx_put($%p, 0x%lx, 0x%016llx)", 694 (void *)bgep, regno, data)); 695 696 /* 697 * Mailbox registers are nominally 64 bits on the 5701, but 698 * the MSW isn't used. On the 5703, they're only 32 bits 699 * anyway. So here we just write the lower(!) 32 bits - 700 * remembering that the chip is big-endian, even though the 701 * PCI bus is little-endian ... 702 */ 703 #ifdef _BIG_ENDIAN 704 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno+4), (uint32_t)data); 705 #else 706 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), (uint32_t)data); 707 #endif /* _BIG_ENDIAN */ 708 BGE_PCICHK(bgep); 709 } 710 711 uint32_t bge_mbx_get(bge_t *bgep, bge_regno_t regno); 712 #pragma inline(bge_mbx_get) 713 714 uint32_t 715 bge_mbx_get(bge_t *bgep, bge_regno_t regno) 716 { 717 uint32_t val32; 718 719 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) 720 regno += INTERRUPT_LP_MBOX_0_REG - INTERRUPT_MBOX_0_REG + 4; 721 722 BGE_TRACE(("bge_mbx_get($%p, 0x%lx)", 723 (void *)bgep, regno)); 724 725 #ifdef _BIG_ENDIAN 726 val32 = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno+4)); 727 #else 728 val32 = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 729 #endif /* _BIG_ENDIAN */ 730 BGE_PCICHK(bgep); 731 732 return (val32); 733 } 734 735 736 #if BGE_DEBUGGING 737 738 void bge_led_mark(bge_t *bgep); 739 #pragma no_inline(bge_led_mark) 740 741 void 742 bge_led_mark(bge_t *bgep) 743 { 744 uint32_t led_ctrl = LED_CONTROL_OVERRIDE_LINK | 745 LED_CONTROL_1000MBPS_LED | 746 LED_CONTROL_100MBPS_LED | 747 LED_CONTROL_10MBPS_LED; 748 749 /* 750 * Blink all three LINK LEDs on simultaneously, then all off, 751 * then restore to automatic hardware control. This is used 752 * in laboratory testing to trigger a logic analyser or scope. 753 */ 754 bge_reg_set32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 755 led_ctrl ^= LED_CONTROL_OVERRIDE_LINK; 756 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 757 led_ctrl = LED_CONTROL_OVERRIDE_LINK; 758 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 759 } 760 761 #endif /* BGE_DEBUGGING */ 762 763 /* 764 * NIC on-chip memory access routines 765 * 766 * Only 32K of NIC memory is visible at a time, controlled by the 767 * Memory Window Base Address Register (in PCI config space). Once 768 * this is set, the 32K region of NIC-local memory that it refers 769 * to can be directly addressed in the upper 32K of the 64K of PCI 770 * memory space used for the device. 771 */ 772 773 static void bge_nic_setwin(bge_t *bgep, bge_regno_t base); 774 #pragma inline(bge_nic_setwin) 775 776 static void 777 bge_nic_setwin(bge_t *bgep, bge_regno_t base) 778 { 779 chip_id_t *cidp; 780 781 BGE_TRACE(("bge_nic_setwin($%p, 0x%lx)", 782 (void *)bgep, base)); 783 784 ASSERT((base & MWBAR_GRANULE_MASK) == 0); 785 786 /* 787 * Don't do repeated zero data writes, 788 * if the device is BCM5714C/15C. 789 */ 790 cidp = &bgep->chipid; 791 if ((cidp->device == DEVICE_ID_5714C) || 792 (cidp->device == DEVICE_ID_5715C)) { 793 if (bgep->lastWriteZeroData && (base == (bge_regno_t)0)) 794 return; 795 /* Adjust lastWriteZeroData */ 796 bgep->lastWriteZeroData = ((base == (bge_regno_t)0) ? 797 B_TRUE : B_FALSE); 798 } 799 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, base); 800 } 801 802 static uint32_t bge_nic_get32(bge_t *bgep, bge_regno_t addr); 803 #pragma inline(bge_nic_get32) 804 805 static uint32_t 806 bge_nic_get32(bge_t *bgep, bge_regno_t addr) 807 { 808 uint32_t data; 809 810 #if defined(BGE_IPMI_ASF) && !defined(__sparc) 811 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 812 /* workaround for word swap error */ 813 if (addr & 4) 814 addr = addr - 4; 815 else 816 addr = addr + 4; 817 } 818 #endif 819 820 #ifdef __sparc 821 data = bge_nic_read32(bgep, addr); 822 #else 823 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 824 addr &= MWBAR_GRANULE_MASK; 825 addr += NIC_MEM_WINDOW_OFFSET; 826 827 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 828 #endif 829 830 BGE_TRACE(("bge_nic_get32($%p, 0x%lx) = 0x%08x", 831 (void *)bgep, addr, data)); 832 833 return (data); 834 } 835 836 void bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data); 837 #pragma inline(bge_nic_put32) 838 839 void 840 bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data) 841 { 842 BGE_TRACE(("bge_nic_put32($%p, 0x%lx, 0x%08x)", 843 (void *)bgep, addr, data)); 844 845 #if defined(BGE_IPMI_ASF) && !defined(__sparc) 846 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 847 /* workaround for word swap error */ 848 if (addr & 4) 849 addr = addr - 4; 850 else 851 addr = addr + 4; 852 } 853 #endif 854 855 #ifdef __sparc 856 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr); 857 data = LE_32(data); 858 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR, data); 859 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0); 860 #else 861 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 862 addr &= MWBAR_GRANULE_MASK; 863 addr += NIC_MEM_WINDOW_OFFSET; 864 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), data); 865 BGE_PCICHK(bgep); 866 #endif 867 } 868 869 static uint64_t bge_nic_get64(bge_t *bgep, bge_regno_t addr); 870 #pragma inline(bge_nic_get64) 871 872 static uint64_t 873 bge_nic_get64(bge_t *bgep, bge_regno_t addr) 874 { 875 uint64_t data; 876 877 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 878 addr &= MWBAR_GRANULE_MASK; 879 addr += NIC_MEM_WINDOW_OFFSET; 880 881 #ifdef __amd64 882 if (bge_get_em64t_type()) { 883 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 884 data <<= 32; 885 data |= ddi_get32(bgep->io_handle, 886 PIO_ADDR(bgep, addr + 4)); 887 } else { 888 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 889 } 890 #else 891 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 892 #endif 893 894 BGE_TRACE(("bge_nic_get64($%p, 0x%lx) = 0x%016llx", 895 (void *)bgep, addr, data)); 896 897 return (data); 898 } 899 900 static void bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data); 901 #pragma inline(bge_nic_put64) 902 903 static void 904 bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data) 905 { 906 BGE_TRACE(("bge_nic_put64($%p, 0x%lx, 0x%016llx)", 907 (void *)bgep, addr, data)); 908 909 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 910 addr &= MWBAR_GRANULE_MASK; 911 addr += NIC_MEM_WINDOW_OFFSET; 912 913 #ifdef __amd64 914 if (bge_get_em64t_type()) { 915 ddi_put32(bgep->io_handle, 916 PIO_ADDR(bgep, addr), (uint32_t)data); 917 BGE_PCICHK(bgep); 918 ddi_put32(bgep->io_handle, 919 PIO_ADDR(bgep, addr + 4), (uint32_t)(data >> 32)); 920 } else { 921 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 922 } 923 #else 924 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 925 #endif 926 927 BGE_PCICHK(bgep); 928 } 929 930 /* 931 * The DDI doesn't provide get/put functions for 128 bit data 932 * so we put RCBs out as two 64-bit chunks instead. 933 */ 934 static void bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 935 #pragma inline(bge_nic_putrcb) 936 937 static void 938 bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 939 { 940 uint64_t *p; 941 942 BGE_TRACE(("bge_nic_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 943 (void *)bgep, addr, rcbp->host_ring_addr, 944 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 945 946 ASSERT((addr % sizeof (*rcbp)) == 0); 947 948 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 949 addr &= MWBAR_GRANULE_MASK; 950 addr += NIC_MEM_WINDOW_OFFSET; 951 952 p = (void *)rcbp; 953 #ifdef __amd64 954 if (bge_get_em64t_type()) { 955 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), 956 (uint32_t)(*p)); 957 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4), 958 (uint32_t)(*p >> 32)); 959 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8), 960 (uint32_t)(*(p + 1))); 961 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12), 962 (uint32_t)(*p >> 32)); 963 964 } else { 965 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 966 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr+8), *p); 967 } 968 #else 969 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 970 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p); 971 #endif 972 973 BGE_PCICHK(bgep); 974 } 975 976 static void bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes); 977 #pragma inline(bge_nic_zero) 978 979 static void 980 bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes) 981 { 982 BGE_TRACE(("bge_nic_zero($%p, 0x%lx, 0x%x)", 983 (void *)bgep, addr, nbytes)); 984 985 ASSERT((addr & ~MWBAR_GRANULE_MASK) == 986 ((addr+nbytes) & ~MWBAR_GRANULE_MASK)); 987 988 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 989 addr &= MWBAR_GRANULE_MASK; 990 addr += NIC_MEM_WINDOW_OFFSET; 991 992 (void) ddi_device_zero(bgep->io_handle, PIO_ADDR(bgep, addr), 993 nbytes, 1, DDI_DATA_SZ08_ACC); 994 BGE_PCICHK(bgep); 995 } 996 997 /* 998 * MII (PHY) register get/set access routines 999 * 1000 * These use the chip's MII auto-access method, controlled by the 1001 * MII Communication register at 0x044c, so the CPU doesn't have 1002 * to fiddle with the individual bits. 1003 */ 1004 1005 #undef BGE_DBG 1006 #define BGE_DBG BGE_DBG_MII /* debug flag for this code */ 1007 1008 static uint16_t bge_mii_access(bge_t *bgep, bge_regno_t regno, 1009 uint16_t data, uint32_t cmd); 1010 #pragma no_inline(bge_mii_access) 1011 1012 static uint16_t 1013 bge_mii_access(bge_t *bgep, bge_regno_t regno, uint16_t data, uint32_t cmd) 1014 { 1015 uint32_t timeout; 1016 uint32_t regval1; 1017 uint32_t regval2; 1018 1019 BGE_TRACE(("bge_mii_access($%p, 0x%lx, 0x%x, 0x%x)", 1020 (void *)bgep, regno, data, cmd)); 1021 1022 ASSERT(mutex_owned(bgep->genlock)); 1023 1024 /* 1025 * Assemble the command ... 1026 */ 1027 cmd |= data << MI_COMMS_DATA_SHIFT; 1028 cmd |= regno << MI_COMMS_REGISTER_SHIFT; 1029 cmd |= bgep->phy_mii_addr << MI_COMMS_ADDRESS_SHIFT; 1030 cmd |= MI_COMMS_START; 1031 1032 /* 1033 * Wait for any command already in progress ... 1034 * 1035 * Note: this *shouldn't* ever find that there is a command 1036 * in progress, because we already hold the <genlock> mutex. 1037 * Nonetheless, we have sometimes seen the MI_COMMS_START 1038 * bit set here -- it seems that the chip can initiate MII 1039 * accesses internally, even with polling OFF. 1040 */ 1041 regval1 = regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1042 for (timeout = 100; ; ) { 1043 if ((regval2 & MI_COMMS_START) == 0) { 1044 bge_reg_put32(bgep, MI_COMMS_REG, cmd); 1045 break; 1046 } 1047 if (--timeout == 0) 1048 break; 1049 drv_usecwait(10); 1050 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1051 } 1052 1053 if (timeout == 0) 1054 return ((uint16_t)~0u); 1055 1056 if (timeout != 100) 1057 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1058 "MI_COMMS_START set for %d us; 0x%x->0x%x", 1059 cmd, 10*(100-timeout), regval1, regval2)); 1060 1061 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1062 for (timeout = 1000; ; ) { 1063 if ((regval1 & MI_COMMS_START) == 0) 1064 break; 1065 if (--timeout == 0) 1066 break; 1067 drv_usecwait(10); 1068 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1069 } 1070 1071 /* 1072 * Drop out early if the READ FAILED bit is set -- this chip 1073 * could be a 5703/4S, with a SerDes instead of a PHY! 1074 */ 1075 if (regval2 & MI_COMMS_READ_FAILED) 1076 return ((uint16_t)~0u); 1077 1078 if (timeout == 0) 1079 return ((uint16_t)~0u); 1080 1081 /* 1082 * The PRM says to wait 5us after seeing the START bit clear 1083 * and then re-read the register to get the final value of the 1084 * data field, in order to avoid a race condition where the 1085 * START bit is clear but the data field isn't yet valid. 1086 * 1087 * Note: we don't actually seem to be encounter this race; 1088 * except when the START bit is seen set again (see below), 1089 * the data field doesn't change during this 5us interval. 1090 */ 1091 drv_usecwait(5); 1092 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1093 1094 /* 1095 * Unfortunately, when following the PRMs instructions above, 1096 * we have occasionally seen the START bit set again(!) in the 1097 * value read after the 5us delay. This seems to be due to the 1098 * chip autonomously starting another MII access internally. 1099 * In such cases, the command/data/etc fields relate to the 1100 * internal command, rather than the one that we thought had 1101 * just finished. So in this case, we fall back to returning 1102 * the data from the original read that showed START clear. 1103 */ 1104 if (regval2 & MI_COMMS_START) { 1105 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1106 "MI_COMMS_START set after transaction; 0x%x->0x%x", 1107 cmd, regval1, regval2)); 1108 regval2 = regval1; 1109 } 1110 1111 if (regval2 & MI_COMMS_START) 1112 return ((uint16_t)~0u); 1113 1114 if (regval2 & MI_COMMS_READ_FAILED) 1115 return ((uint16_t)~0u); 1116 1117 return ((regval2 & MI_COMMS_DATA_MASK) >> MI_COMMS_DATA_SHIFT); 1118 } 1119 1120 uint16_t bge_mii_get16(bge_t *bgep, bge_regno_t regno); 1121 #pragma no_inline(bge_mii_get16) 1122 1123 uint16_t 1124 bge_mii_get16(bge_t *bgep, bge_regno_t regno) 1125 { 1126 BGE_TRACE(("bge_mii_get16($%p, 0x%lx)", 1127 (void *)bgep, regno)); 1128 1129 ASSERT(mutex_owned(bgep->genlock)); 1130 1131 if (DEVICE_5906_SERIES_CHIPSETS(bgep) && ((regno == MII_AUX_CONTROL) || 1132 (regno == MII_1000BASE_T_CONTROL))) 1133 return (0); 1134 1135 return (bge_mii_access(bgep, regno, 0, MI_COMMS_COMMAND_READ)); 1136 } 1137 1138 void bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data); 1139 #pragma no_inline(bge_mii_put16) 1140 1141 void 1142 bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data) 1143 { 1144 BGE_TRACE(("bge_mii_put16($%p, 0x%lx, 0x%x)", 1145 (void *)bgep, regno, data)); 1146 1147 ASSERT(mutex_owned(bgep->genlock)); 1148 1149 if (DEVICE_5906_SERIES_CHIPSETS(bgep) && ((regno == MII_AUX_CONTROL) || 1150 (regno == MII_1000BASE_T_CONTROL))) 1151 return; 1152 1153 (void) bge_mii_access(bgep, regno, data, MI_COMMS_COMMAND_WRITE); 1154 } 1155 1156 #undef BGE_DBG 1157 #define BGE_DBG BGE_DBG_SEEPROM /* debug flag for this code */ 1158 1159 #if BGE_SEE_IO32 || BGE_FLASH_IO32 1160 1161 /* 1162 * Basic SEEPROM get/set access routine 1163 * 1164 * This uses the chip's SEEPROM auto-access method, controlled by the 1165 * Serial EEPROM Address/Data Registers at 0x6838/683c, so the CPU 1166 * doesn't have to fiddle with the individual bits. 1167 * 1168 * The caller should hold <genlock> and *also* have already acquired 1169 * the right to access the SEEPROM, via bge_nvmem_acquire() above. 1170 * 1171 * Return value: 1172 * 0 on success, 1173 * ENODATA on access timeout (maybe retryable: device may just be busy) 1174 * EPROTO on other h/w or s/w errors. 1175 * 1176 * <*dp> is an input to a SEEPROM_ACCESS_WRITE operation, or an output 1177 * from a (successful) SEEPROM_ACCESS_READ. 1178 */ 1179 static int bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1180 uint32_t *dp); 1181 #pragma no_inline(bge_seeprom_access) 1182 1183 static int 1184 bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1185 { 1186 uint32_t tries; 1187 uint32_t regval; 1188 1189 ASSERT(mutex_owned(bgep->genlock)); 1190 1191 /* 1192 * On the newer chips that support both SEEPROM & Flash, we need 1193 * to specifically enable SEEPROM access (Flash is the default). 1194 * On older chips, we don't; SEEPROM is the only NVtype supported, 1195 * and the NVM control registers don't exist ... 1196 */ 1197 switch (bgep->chipid.nvtype) { 1198 case BGE_NVTYPE_NONE: 1199 case BGE_NVTYPE_UNKNOWN: 1200 _NOTE(NOTREACHED) 1201 case BGE_NVTYPE_SEEPROM: 1202 break; 1203 1204 case BGE_NVTYPE_LEGACY_SEEPROM: 1205 case BGE_NVTYPE_UNBUFFERED_FLASH: 1206 case BGE_NVTYPE_BUFFERED_FLASH: 1207 default: 1208 bge_reg_set32(bgep, NVM_CONFIG1_REG, 1209 NVM_CFG1_LEGACY_SEEPROM_MODE); 1210 break; 1211 } 1212 1213 /* 1214 * Check there's no command in progress. 1215 * 1216 * Note: this *shouldn't* ever find that there is a command 1217 * in progress, because we already hold the <genlock> mutex. 1218 * Also, to ensure we don't have a conflict with the chip's 1219 * internal firmware or a process accessing the same (shared) 1220 * SEEPROM through the other port of a 5704, we've already 1221 * been through the "software arbitration" protocol. 1222 * So this is just a final consistency check: we shouldn't 1223 * see EITHER the START bit (command started but not complete) 1224 * OR the COMPLETE bit (command completed but not cleared). 1225 */ 1226 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1227 if (regval & SEEPROM_ACCESS_START) 1228 return (EPROTO); 1229 if (regval & SEEPROM_ACCESS_COMPLETE) 1230 return (EPROTO); 1231 1232 /* 1233 * Assemble the command ... 1234 */ 1235 cmd |= addr & SEEPROM_ACCESS_ADDRESS_MASK; 1236 addr >>= SEEPROM_ACCESS_ADDRESS_SIZE; 1237 addr <<= SEEPROM_ACCESS_DEVID_SHIFT; 1238 cmd |= addr & SEEPROM_ACCESS_DEVID_MASK; 1239 cmd |= SEEPROM_ACCESS_START; 1240 cmd |= SEEPROM_ACCESS_COMPLETE; 1241 cmd |= regval & SEEPROM_ACCESS_HALFCLOCK_MASK; 1242 1243 bge_reg_put32(bgep, SERIAL_EEPROM_DATA_REG, *dp); 1244 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, cmd); 1245 1246 /* 1247 * By observation, a successful access takes ~20us on a 5703/4, 1248 * but apparently much longer (up to 1000us) on the obsolescent 1249 * BCM5700/BCM5701. We want to be sure we don't get any false 1250 * timeouts here; but OTOH, we don't want a bogus access to lock 1251 * out interrupts for longer than necessary. So we'll allow up 1252 * to 1000us ... 1253 */ 1254 for (tries = 0; tries < 1000; ++tries) { 1255 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1256 if (regval & SEEPROM_ACCESS_COMPLETE) 1257 break; 1258 drv_usecwait(1); 1259 } 1260 1261 if (regval & SEEPROM_ACCESS_COMPLETE) { 1262 /* 1263 * All OK; read the SEEPROM data register, then write back 1264 * the value read from the address register in order to 1265 * clear the <complete> bit and leave the SEEPROM access 1266 * state machine idle, ready for the next access ... 1267 */ 1268 BGE_DEBUG(("bge_seeprom_access: complete after %d us", tries)); 1269 *dp = bge_reg_get32(bgep, SERIAL_EEPROM_DATA_REG); 1270 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, regval); 1271 return (0); 1272 } 1273 1274 /* 1275 * Hmm ... what happened here? 1276 * 1277 * Most likely, the user addressed a non-existent SEEPROM. Or 1278 * maybe the SEEPROM was busy internally (e.g. processing a write) 1279 * and didn't respond to being addressed. Either way, it's left 1280 * the SEEPROM access state machine wedged. So we'll reset it 1281 * before we leave, so it's ready for next time ... 1282 */ 1283 BGE_DEBUG(("bge_seeprom_access: timed out after %d us", tries)); 1284 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 1285 return (ENODATA); 1286 } 1287 1288 /* 1289 * Basic Flash get/set access routine 1290 * 1291 * These use the chip's Flash auto-access method, controlled by the 1292 * Flash Access Registers at 0x7000-701c, so the CPU doesn't have to 1293 * fiddle with the individual bits. 1294 * 1295 * The caller should hold <genlock> and *also* have already acquired 1296 * the right to access the Flash, via bge_nvmem_acquire() above. 1297 * 1298 * Return value: 1299 * 0 on success, 1300 * ENODATA on access timeout (maybe retryable: device may just be busy) 1301 * ENODEV if the NVmem device is missing or otherwise unusable 1302 * 1303 * <*dp> is an input to a NVM_FLASH_CMD_WR operation, or an output 1304 * from a (successful) NVM_FLASH_CMD_RD. 1305 */ 1306 static int bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1307 uint32_t *dp); 1308 #pragma no_inline(bge_flash_access) 1309 1310 static int 1311 bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1312 { 1313 uint32_t tries; 1314 uint32_t regval; 1315 1316 ASSERT(mutex_owned(bgep->genlock)); 1317 1318 /* 1319 * On the newer chips that support both SEEPROM & Flash, we need 1320 * to specifically disable SEEPROM access while accessing Flash. 1321 * The older chips don't support Flash, and the NVM registers don't 1322 * exist, so we shouldn't be here at all! 1323 */ 1324 switch (bgep->chipid.nvtype) { 1325 case BGE_NVTYPE_NONE: 1326 case BGE_NVTYPE_UNKNOWN: 1327 _NOTE(NOTREACHED) 1328 case BGE_NVTYPE_SEEPROM: 1329 return (ENODEV); 1330 1331 case BGE_NVTYPE_LEGACY_SEEPROM: 1332 case BGE_NVTYPE_UNBUFFERED_FLASH: 1333 case BGE_NVTYPE_BUFFERED_FLASH: 1334 default: 1335 bge_reg_clr32(bgep, NVM_CONFIG1_REG, 1336 NVM_CFG1_LEGACY_SEEPROM_MODE); 1337 break; 1338 } 1339 1340 /* 1341 * Assemble the command ... 1342 */ 1343 addr &= NVM_FLASH_ADDR_MASK; 1344 cmd |= NVM_FLASH_CMD_DOIT; 1345 cmd |= NVM_FLASH_CMD_FIRST; 1346 cmd |= NVM_FLASH_CMD_LAST; 1347 cmd |= NVM_FLASH_CMD_DONE; 1348 1349 bge_reg_put32(bgep, NVM_FLASH_WRITE_REG, *dp); 1350 bge_reg_put32(bgep, NVM_FLASH_ADDR_REG, addr); 1351 bge_reg_put32(bgep, NVM_FLASH_CMD_REG, cmd); 1352 1353 /* 1354 * Allow up to 1000ms ... 1355 */ 1356 for (tries = 0; tries < 1000; ++tries) { 1357 regval = bge_reg_get32(bgep, NVM_FLASH_CMD_REG); 1358 if (regval & NVM_FLASH_CMD_DONE) 1359 break; 1360 drv_usecwait(1); 1361 } 1362 1363 if (regval & NVM_FLASH_CMD_DONE) { 1364 /* 1365 * All OK; read the data from the Flash read register 1366 */ 1367 BGE_DEBUG(("bge_flash_access: complete after %d us", tries)); 1368 *dp = bge_reg_get32(bgep, NVM_FLASH_READ_REG); 1369 return (0); 1370 } 1371 1372 /* 1373 * Hmm ... what happened here? 1374 * 1375 * Most likely, the user addressed a non-existent Flash. Or 1376 * maybe the Flash was busy internally (e.g. processing a write) 1377 * and didn't respond to being addressed. Either way, there's 1378 * nothing we can here ... 1379 */ 1380 BGE_DEBUG(("bge_flash_access: timed out after %d us", tries)); 1381 return (ENODATA); 1382 } 1383 1384 /* 1385 * The next two functions regulate access to the NVram (if fitted). 1386 * 1387 * On a 5704 (dual core) chip, there's only one SEEPROM and one Flash 1388 * (SPI) interface, but they can be accessed through either port. These 1389 * are managed by different instance of this driver and have no software 1390 * state in common. 1391 * 1392 * In addition (and even on a single core chip) the chip's internal 1393 * firmware can access the SEEPROM/Flash, most notably after a RESET 1394 * when it may download code to run internally. 1395 * 1396 * So we need to arbitrate between these various software agents. For 1397 * this purpose, the chip provides the Software Arbitration Register, 1398 * which implements hardware(!) arbitration. 1399 * 1400 * This functionality didn't exist on older (5700/5701) chips, so there's 1401 * nothing we can do by way of arbitration on those; also, if there's no 1402 * SEEPROM/Flash fitted (or we couldn't determine what type), there's also 1403 * nothing to do. 1404 * 1405 * The internal firmware appears to use Request 0, which is the highest 1406 * priority. So we'd like to use Request 2, leaving one higher and one 1407 * lower for any future developments ... but apparently this doesn't 1408 * always work. So for now, the code uses Request 1 ;-( 1409 */ 1410 1411 #define NVM_READ_REQ NVM_READ_REQ1 1412 #define NVM_RESET_REQ NVM_RESET_REQ1 1413 #define NVM_SET_REQ NVM_SET_REQ1 1414 1415 static void bge_nvmem_relinquish(bge_t *bgep); 1416 #pragma no_inline(bge_nvmem_relinquish) 1417 1418 static void 1419 bge_nvmem_relinquish(bge_t *bgep) 1420 { 1421 ASSERT(mutex_owned(bgep->genlock)); 1422 1423 switch (bgep->chipid.nvtype) { 1424 case BGE_NVTYPE_NONE: 1425 case BGE_NVTYPE_UNKNOWN: 1426 _NOTE(NOTREACHED) 1427 return; 1428 1429 case BGE_NVTYPE_SEEPROM: 1430 /* 1431 * No arbitration performed, no release needed 1432 */ 1433 return; 1434 1435 case BGE_NVTYPE_LEGACY_SEEPROM: 1436 case BGE_NVTYPE_UNBUFFERED_FLASH: 1437 case BGE_NVTYPE_BUFFERED_FLASH: 1438 default: 1439 break; 1440 } 1441 1442 /* 1443 * Our own request should be present (whether or not granted) ... 1444 */ 1445 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1446 1447 /* 1448 * ... this will make it go away. 1449 */ 1450 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_RESET_REQ); 1451 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1452 } 1453 1454 /* 1455 * Arbitrate for access to the NVmem, if necessary 1456 * 1457 * Return value: 1458 * 0 on success 1459 * EAGAIN if the device is in use (retryable) 1460 * ENODEV if the NVmem device is missing or otherwise unusable 1461 */ 1462 static int bge_nvmem_acquire(bge_t *bgep); 1463 #pragma no_inline(bge_nvmem_acquire) 1464 1465 static int 1466 bge_nvmem_acquire(bge_t *bgep) 1467 { 1468 uint32_t regval; 1469 uint32_t tries; 1470 1471 ASSERT(mutex_owned(bgep->genlock)); 1472 1473 switch (bgep->chipid.nvtype) { 1474 case BGE_NVTYPE_NONE: 1475 case BGE_NVTYPE_UNKNOWN: 1476 /* 1477 * Access denied: no (recognisable) device fitted 1478 */ 1479 return (ENODEV); 1480 1481 case BGE_NVTYPE_SEEPROM: 1482 /* 1483 * Access granted: no arbitration needed (or possible) 1484 */ 1485 return (0); 1486 1487 case BGE_NVTYPE_LEGACY_SEEPROM: 1488 case BGE_NVTYPE_UNBUFFERED_FLASH: 1489 case BGE_NVTYPE_BUFFERED_FLASH: 1490 default: 1491 /* 1492 * Access conditional: conduct arbitration protocol 1493 */ 1494 break; 1495 } 1496 1497 /* 1498 * We're holding the per-port mutex <genlock>, so no-one other 1499 * thread can be attempting to access the NVmem through *this* 1500 * port. But it could be in use by the *other* port (of a 5704), 1501 * or by the chip's internal firmware, so we have to go through 1502 * the full (hardware) arbitration protocol ... 1503 * 1504 * Note that *because* we're holding <genlock>, the interrupt handler 1505 * won't be able to progress. So we're only willing to spin for a 1506 * fairly short time. Specifically: 1507 * 1508 * We *must* wait long enough for the hardware to resolve all 1509 * requests and determine the winner. Fortunately, this is 1510 * "almost instantaneous", even as observed by GHz CPUs. 1511 * 1512 * A successful access by another Solaris thread (via either 1513 * port) typically takes ~20us. So waiting a bit longer than 1514 * that will give a good chance of success, if the other user 1515 * *is* another thread on the other port. 1516 * 1517 * However, the internal firmware can hold on to the NVmem 1518 * for *much* longer: at least 10 milliseconds just after a 1519 * RESET, and maybe even longer if the NVmem actually contains 1520 * code to download and run on the internal CPUs. 1521 * 1522 * So, we'll allow 50us; if that's not enough then it's up to the 1523 * caller to retry later (hence the choice of return code EAGAIN). 1524 */ 1525 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1526 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_SET_REQ); 1527 1528 for (tries = 0; tries < 50; ++tries) { 1529 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1530 if (regval & NVM_WON_REQ1) 1531 break; 1532 drv_usecwait(1); 1533 } 1534 1535 if (regval & NVM_WON_REQ1) { 1536 BGE_DEBUG(("bge_nvmem_acquire: won after %d us", tries)); 1537 return (0); 1538 } 1539 1540 /* 1541 * Somebody else must be accessing the NVmem, so abandon our 1542 * attempt take control of it. The caller can try again later ... 1543 */ 1544 BGE_DEBUG(("bge_nvmem_acquire: lost after %d us", tries)); 1545 bge_nvmem_relinquish(bgep); 1546 return (EAGAIN); 1547 } 1548 1549 /* 1550 * This code assumes that the GPIO1 bit has been wired up to the NVmem 1551 * write protect line in such a way that the NVmem is protected when 1552 * GPIO1 is an input, or is an output but driven high. Thus, to make the 1553 * NVmem writable we have to change GPIO1 to an output AND drive it low. 1554 * 1555 * Note: there's only one set of GPIO pins on a 5704, even though they 1556 * can be accessed through either port. So the chip has to resolve what 1557 * happens if the two ports program a single pin differently ... the rule 1558 * it uses is that if the ports disagree about the *direction* of a pin, 1559 * "output" wins over "input", but if they disagree about its *value* as 1560 * an output, then the pin is TRISTATED instead! In such a case, no-one 1561 * wins, and the external signal does whatever the external circuitry 1562 * defines as the default -- which we've assumed is the PROTECTED state. 1563 * So, we always change GPIO1 back to being an *input* whenever we're not 1564 * specifically using it to unprotect the NVmem. This allows either port 1565 * to update the NVmem, although obviously only one at a time! 1566 * 1567 * The caller should hold <genlock> and *also* have already acquired the 1568 * right to access the NVmem, via bge_nvmem_acquire() above. 1569 */ 1570 static void bge_nvmem_protect(bge_t *bgep, boolean_t protect); 1571 #pragma inline(bge_nvmem_protect) 1572 1573 static void 1574 bge_nvmem_protect(bge_t *bgep, boolean_t protect) 1575 { 1576 uint32_t regval; 1577 1578 ASSERT(mutex_owned(bgep->genlock)); 1579 1580 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 1581 if (protect) { 1582 regval |= MLCR_MISC_PINS_OUTPUT_1; 1583 regval &= ~MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1584 } else { 1585 regval &= ~MLCR_MISC_PINS_OUTPUT_1; 1586 regval |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1587 } 1588 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, regval); 1589 } 1590 1591 /* 1592 * Now put it all together ... 1593 * 1594 * Try to acquire control of the NVmem; if successful, then: 1595 * unprotect it (if we want to write to it) 1596 * perform the requested access 1597 * reprotect it (after a write) 1598 * relinquish control 1599 * 1600 * Return value: 1601 * 0 on success, 1602 * EAGAIN if the device is in use (retryable) 1603 * ENODATA on access timeout (maybe retryable: device may just be busy) 1604 * ENODEV if the NVmem device is missing or otherwise unusable 1605 * EPROTO on other h/w or s/w errors. 1606 */ 1607 static int 1608 bge_nvmem_rw32(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1609 { 1610 int err; 1611 1612 if ((err = bge_nvmem_acquire(bgep)) == 0) { 1613 switch (cmd) { 1614 case BGE_SEE_READ: 1615 err = bge_seeprom_access(bgep, 1616 SEEPROM_ACCESS_READ, addr, dp); 1617 break; 1618 1619 case BGE_SEE_WRITE: 1620 bge_nvmem_protect(bgep, B_FALSE); 1621 err = bge_seeprom_access(bgep, 1622 SEEPROM_ACCESS_WRITE, addr, dp); 1623 bge_nvmem_protect(bgep, B_TRUE); 1624 break; 1625 1626 case BGE_FLASH_READ: 1627 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1628 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1629 bge_reg_set32(bgep, NVM_ACCESS_REG, 1630 NVM_ACCESS_ENABLE); 1631 } 1632 err = bge_flash_access(bgep, 1633 NVM_FLASH_CMD_RD, addr, dp); 1634 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1635 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1636 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1637 NVM_ACCESS_ENABLE); 1638 } 1639 break; 1640 1641 case BGE_FLASH_WRITE: 1642 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1643 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1644 bge_reg_set32(bgep, NVM_ACCESS_REG, 1645 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1646 } 1647 bge_nvmem_protect(bgep, B_FALSE); 1648 err = bge_flash_access(bgep, 1649 NVM_FLASH_CMD_WR, addr, dp); 1650 bge_nvmem_protect(bgep, B_TRUE); 1651 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1652 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1653 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1654 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1655 } 1656 1657 break; 1658 1659 default: 1660 _NOTE(NOTREACHED) 1661 break; 1662 } 1663 bge_nvmem_relinquish(bgep); 1664 } 1665 1666 BGE_DEBUG(("bge_nvmem_rw32: err %d", err)); 1667 return (err); 1668 } 1669 1670 /* 1671 * Attempt to get a MAC address from the SEEPROM or Flash, if any 1672 */ 1673 static uint64_t bge_get_nvmac(bge_t *bgep); 1674 #pragma no_inline(bge_get_nvmac) 1675 1676 static uint64_t 1677 bge_get_nvmac(bge_t *bgep) 1678 { 1679 uint32_t mac_high; 1680 uint32_t mac_low; 1681 uint32_t addr; 1682 uint32_t cmd; 1683 uint64_t mac; 1684 1685 BGE_TRACE(("bge_get_nvmac($%p)", 1686 (void *)bgep)); 1687 1688 switch (bgep->chipid.nvtype) { 1689 case BGE_NVTYPE_NONE: 1690 case BGE_NVTYPE_UNKNOWN: 1691 default: 1692 return (0ULL); 1693 1694 case BGE_NVTYPE_SEEPROM: 1695 case BGE_NVTYPE_LEGACY_SEEPROM: 1696 cmd = BGE_SEE_READ; 1697 break; 1698 1699 case BGE_NVTYPE_UNBUFFERED_FLASH: 1700 case BGE_NVTYPE_BUFFERED_FLASH: 1701 cmd = BGE_FLASH_READ; 1702 break; 1703 } 1704 1705 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) 1706 addr = NVMEM_DATA_MAC_ADDRESS_5906; 1707 else 1708 addr = NVMEM_DATA_MAC_ADDRESS; 1709 1710 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_high)) 1711 return (0ULL); 1712 addr += 4; 1713 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_low)) 1714 return (0ULL); 1715 1716 /* 1717 * The Broadcom chip is natively BIG-endian, so that's how the 1718 * MAC address is represented in NVmem. We may need to swap it 1719 * around on a little-endian host ... 1720 */ 1721 #ifdef _BIG_ENDIAN 1722 mac = mac_high; 1723 mac = mac << 32; 1724 mac |= mac_low; 1725 #else 1726 mac = BGE_BSWAP_32(mac_high); 1727 mac = mac << 32; 1728 mac |= BGE_BSWAP_32(mac_low); 1729 #endif /* _BIG_ENDIAN */ 1730 1731 return (mac); 1732 } 1733 1734 #else /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1735 1736 /* 1737 * Dummy version for when we're not supporting NVmem access 1738 */ 1739 static uint64_t bge_get_nvmac(bge_t *bgep); 1740 #pragma inline(bge_get_nvmac) 1741 1742 static uint64_t 1743 bge_get_nvmac(bge_t *bgep) 1744 { 1745 _NOTE(ARGUNUSED(bgep)) 1746 return (0ULL); 1747 } 1748 1749 #endif /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1750 1751 /* 1752 * Determine the type of NVmem that is (or may be) attached to this chip, 1753 */ 1754 static enum bge_nvmem_type bge_nvmem_id(bge_t *bgep); 1755 #pragma no_inline(bge_nvmem_id) 1756 1757 static enum bge_nvmem_type 1758 bge_nvmem_id(bge_t *bgep) 1759 { 1760 enum bge_nvmem_type nvtype; 1761 uint32_t config1; 1762 1763 BGE_TRACE(("bge_nvmem_id($%p)", 1764 (void *)bgep)); 1765 1766 switch (bgep->chipid.device) { 1767 default: 1768 /* 1769 * We shouldn't get here; it means we don't recognise 1770 * the chip, which means we don't know how to determine 1771 * what sort of NVmem (if any) it has. So we'll say 1772 * NONE, to disable the NVmem access code ... 1773 */ 1774 nvtype = BGE_NVTYPE_NONE; 1775 break; 1776 1777 case DEVICE_ID_5700: 1778 case DEVICE_ID_5700x: 1779 case DEVICE_ID_5701: 1780 /* 1781 * These devices support *only* SEEPROMs 1782 */ 1783 nvtype = BGE_NVTYPE_SEEPROM; 1784 break; 1785 1786 case DEVICE_ID_5702: 1787 case DEVICE_ID_5702fe: 1788 case DEVICE_ID_5703C: 1789 case DEVICE_ID_5703S: 1790 case DEVICE_ID_5704C: 1791 case DEVICE_ID_5704S: 1792 case DEVICE_ID_5704: 1793 case DEVICE_ID_5705M: 1794 case DEVICE_ID_5705C: 1795 case DEVICE_ID_5705_2: 1796 case DEVICE_ID_5706: 1797 case DEVICE_ID_5780: 1798 case DEVICE_ID_5782: 1799 case DEVICE_ID_5787: 1800 case DEVICE_ID_5787M: 1801 case DEVICE_ID_5788: 1802 case DEVICE_ID_5789: 1803 case DEVICE_ID_5751: 1804 case DEVICE_ID_5751M: 1805 case DEVICE_ID_5752: 1806 case DEVICE_ID_5752M: 1807 case DEVICE_ID_5754: 1808 case DEVICE_ID_5755: 1809 case DEVICE_ID_5755M: 1810 case DEVICE_ID_5756M: 1811 case DEVICE_ID_5721: 1812 case DEVICE_ID_5722: 1813 case DEVICE_ID_5714C: 1814 case DEVICE_ID_5714S: 1815 case DEVICE_ID_5715C: 1816 case DEVICE_ID_5715S: 1817 config1 = bge_reg_get32(bgep, NVM_CONFIG1_REG); 1818 if (config1 & NVM_CFG1_FLASH_MODE) 1819 if (config1 & NVM_CFG1_BUFFERED_MODE) 1820 nvtype = BGE_NVTYPE_BUFFERED_FLASH; 1821 else 1822 nvtype = BGE_NVTYPE_UNBUFFERED_FLASH; 1823 else 1824 nvtype = BGE_NVTYPE_LEGACY_SEEPROM; 1825 break; 1826 case DEVICE_ID_5906: 1827 case DEVICE_ID_5906M: 1828 nvtype = BGE_NVTYPE_BUFFERED_FLASH; 1829 break; 1830 } 1831 1832 return (nvtype); 1833 } 1834 1835 #undef BGE_DBG 1836 #define BGE_DBG BGE_DBG_CHIP /* debug flag for this code */ 1837 1838 static void 1839 bge_init_recv_rule(bge_t *bgep) 1840 { 1841 bge_recv_rule_t *rulep = bgep->recv_rules; 1842 uint32_t i; 1843 1844 /* 1845 * Initialize receive rule registers. 1846 * Note that rules may persist across each bge_m_start/stop() call. 1847 */ 1848 for (i = 0; i < RECV_RULES_NUM_MAX; i++, rulep++) { 1849 bge_reg_put32(bgep, RECV_RULE_MASK_REG(i), rulep->mask_value); 1850 bge_reg_put32(bgep, RECV_RULE_CONTROL_REG(i), rulep->control); 1851 } 1852 } 1853 1854 /* 1855 * Using the values captured by bge_chip_cfg_init(), and additional probes 1856 * as required, characterise the chip fully: determine the label by which 1857 * to refer to this chip, the correct settings for various registers, and 1858 * of course whether the device and/or subsystem are supported! 1859 */ 1860 int bge_chip_id_init(bge_t *bgep); 1861 #pragma no_inline(bge_chip_id_init) 1862 1863 int 1864 bge_chip_id_init(bge_t *bgep) 1865 { 1866 char buf[MAXPATHLEN]; /* any risk of stack overflow? */ 1867 boolean_t sys_ok; 1868 boolean_t dev_ok; 1869 chip_id_t *cidp; 1870 uint32_t subid; 1871 char *devname; 1872 char *sysname; 1873 int *ids; 1874 int err; 1875 uint_t i; 1876 1877 sys_ok = dev_ok = B_FALSE; 1878 cidp = &bgep->chipid; 1879 1880 /* 1881 * Check the PCI device ID to determine the generic chip type and 1882 * select parameters that depend on this. 1883 * 1884 * Note: because the SPARC platforms in general don't fit the 1885 * SEEPROM 'behind' the chip, the PCI revision ID register reads 1886 * as zero - which is why we use <asic_rev> rather than <revision> 1887 * below ... 1888 * 1889 * Note: in general we can't distinguish between the Copper/SerDes 1890 * versions by ID alone, as some Copper devices (e.g. some but not 1891 * all 5703Cs) have the same ID as the SerDes equivalents. So we 1892 * treat them the same here, and the MII code works out the media 1893 * type later on ... 1894 */ 1895 cidp->mbuf_base = bge_mbuf_pool_base; 1896 cidp->mbuf_length = bge_mbuf_pool_len; 1897 cidp->recv_slots = BGE_RECV_SLOTS_USED; 1898 cidp->bge_dma_rwctrl = bge_dma_rwctrl; 1899 cidp->pci_type = BGE_PCI_X; 1900 cidp->statistic_type = BGE_STAT_BLK; 1901 cidp->mbuf_lo_water_rdma = bge_mbuf_lo_water_rdma; 1902 cidp->mbuf_lo_water_rmac = bge_mbuf_lo_water_rmac; 1903 cidp->mbuf_hi_water = bge_mbuf_hi_water; 1904 cidp->rx_ticks_norm = bge_rx_ticks_norm; 1905 cidp->rx_count_norm = bge_rx_count_norm; 1906 1907 if (cidp->rx_rings == 0 || cidp->rx_rings > BGE_RECV_RINGS_MAX) 1908 cidp->rx_rings = BGE_RECV_RINGS_DEFAULT; 1909 if (cidp->tx_rings == 0 || cidp->tx_rings > BGE_SEND_RINGS_MAX) 1910 cidp->tx_rings = BGE_SEND_RINGS_DEFAULT; 1911 1912 cidp->msi_enabled = B_FALSE; 1913 1914 switch (cidp->device) { 1915 case DEVICE_ID_5700: 1916 case DEVICE_ID_5700x: 1917 cidp->chip_label = 5700; 1918 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1919 break; 1920 1921 case DEVICE_ID_5701: 1922 cidp->chip_label = 5701; 1923 dev_ok = B_TRUE; 1924 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1925 break; 1926 1927 case DEVICE_ID_5702: 1928 case DEVICE_ID_5702fe: 1929 cidp->chip_label = 5702; 1930 dev_ok = B_TRUE; 1931 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1932 cidp->pci_type = BGE_PCI; 1933 break; 1934 1935 case DEVICE_ID_5703C: 1936 case DEVICE_ID_5703S: 1937 case DEVICE_ID_5703: 1938 /* 1939 * Revision A0 of the 5703/5793 had various errata 1940 * that we can't or don't work around, so it's not 1941 * supported, but all later versions are 1942 */ 1943 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5793 : 5703; 1944 if (bgep->chipid.asic_rev != MHCR_CHIP_REV_5703_A0) 1945 dev_ok = B_TRUE; 1946 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1947 break; 1948 1949 case DEVICE_ID_5704C: 1950 case DEVICE_ID_5704S: 1951 case DEVICE_ID_5704: 1952 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5794 : 5704; 1953 cidp->mbuf_base = bge_mbuf_pool_base_5704; 1954 cidp->mbuf_length = bge_mbuf_pool_len_5704; 1955 dev_ok = B_TRUE; 1956 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1957 break; 1958 1959 case DEVICE_ID_5705C: 1960 case DEVICE_ID_5705M: 1961 case DEVICE_ID_5705MA3: 1962 case DEVICE_ID_5705F: 1963 case DEVICE_ID_5705_2: 1964 case DEVICE_ID_5754: 1965 if (cidp->device == DEVICE_ID_5754) { 1966 cidp->chip_label = 5754; 1967 cidp->pci_type = BGE_PCI_E; 1968 } else { 1969 cidp->chip_label = 5705; 1970 cidp->pci_type = BGE_PCI; 1971 } 1972 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 1973 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 1974 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 1975 cidp->mbuf_base = bge_mbuf_pool_base_5705; 1976 cidp->mbuf_length = bge_mbuf_pool_len_5705; 1977 cidp->recv_slots = BGE_RECV_SLOTS_5705; 1978 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 1979 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 1980 cidp->flags |= CHIP_FLAG_NO_JUMBO; 1981 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1982 cidp->statistic_type = BGE_STAT_REG; 1983 dev_ok = B_TRUE; 1984 break; 1985 1986 case DEVICE_ID_5906: 1987 case DEVICE_ID_5906M: 1988 cidp->chip_label = 5906; 1989 cidp->pci_type = BGE_PCI_E; 1990 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5906; 1991 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5906; 1992 cidp->mbuf_hi_water = MBUF_HIWAT_5906; 1993 cidp->mbuf_base = bge_mbuf_pool_base; 1994 cidp->mbuf_length = bge_mbuf_pool_len; 1995 cidp->recv_slots = BGE_RECV_SLOTS_5705; 1996 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 1997 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 1998 cidp->flags |= CHIP_FLAG_NO_JUMBO; 1999 cidp->statistic_type = BGE_STAT_REG; 2000 dev_ok = B_TRUE; 2001 break; 2002 2003 case DEVICE_ID_5753: 2004 cidp->chip_label = 5753; 2005 cidp->pci_type = BGE_PCI_E; 2006 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2007 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2008 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2009 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2010 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2011 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2012 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2013 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2014 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2015 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2016 cidp->statistic_type = BGE_STAT_REG; 2017 dev_ok = B_TRUE; 2018 break; 2019 2020 case DEVICE_ID_5755: 2021 case DEVICE_ID_5755M: 2022 cidp->chip_label = 5755; 2023 cidp->pci_type = BGE_PCI_E; 2024 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2025 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2026 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2027 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2028 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2029 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2030 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2031 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2032 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2033 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2034 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2035 cidp->statistic_type = BGE_STAT_REG; 2036 dev_ok = B_TRUE; 2037 break; 2038 2039 case DEVICE_ID_5756M: 2040 /* 2041 * This is nearly identical to the 5755M. 2042 * (Actually reports the 5755 chip ID.) 2043 */ 2044 cidp->chip_label = 5756; 2045 cidp->pci_type = BGE_PCI_E; 2046 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2047 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2048 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2049 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2050 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2051 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2052 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2053 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2054 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2055 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2056 cidp->statistic_type = BGE_STAT_REG; 2057 dev_ok = B_TRUE; 2058 break; 2059 2060 case DEVICE_ID_5787: 2061 case DEVICE_ID_5787M: 2062 cidp->chip_label = 5787; 2063 cidp->pci_type = BGE_PCI_E; 2064 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2065 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2066 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2067 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2068 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2069 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2070 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2071 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2072 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2073 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2074 cidp->statistic_type = BGE_STAT_REG; 2075 dev_ok = B_TRUE; 2076 break; 2077 2078 case DEVICE_ID_5706: 2079 cidp->chip_label = 5706; 2080 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2081 break; 2082 2083 case DEVICE_ID_5780: 2084 cidp->chip_label = 5780; 2085 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2086 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2087 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2088 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2089 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2090 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2091 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2092 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2093 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2094 cidp->statistic_type = BGE_STAT_REG; 2095 cidp->pci_type = BGE_PCI; 2096 dev_ok = B_TRUE; 2097 break; 2098 2099 case DEVICE_ID_5782: 2100 /* 2101 * Apart from the label, we treat this as a 5705(?) 2102 */ 2103 cidp->chip_label = 5782; 2104 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2105 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2106 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2107 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2108 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2109 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2110 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2111 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2112 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2113 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2114 cidp->statistic_type = BGE_STAT_REG; 2115 dev_ok = B_TRUE; 2116 break; 2117 2118 case DEVICE_ID_5788: 2119 /* 2120 * Apart from the label, we treat this as a 5705(?) 2121 */ 2122 cidp->chip_label = 5788; 2123 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2124 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2125 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2126 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2127 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2128 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2129 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2130 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2131 cidp->statistic_type = BGE_STAT_REG; 2132 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2133 dev_ok = B_TRUE; 2134 break; 2135 2136 case DEVICE_ID_5714C: 2137 if (cidp->revision >= REVISION_ID_5714_A2) 2138 cidp->msi_enabled = bge_enable_msi; 2139 /* FALLTHRU */ 2140 case DEVICE_ID_5714S: 2141 cidp->chip_label = 5714; 2142 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2143 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2144 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2145 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2146 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2147 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2148 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5714; 2149 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2150 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2151 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2152 cidp->pci_type = BGE_PCI_E; 2153 cidp->statistic_type = BGE_STAT_REG; 2154 dev_ok = B_TRUE; 2155 break; 2156 2157 case DEVICE_ID_5715C: 2158 case DEVICE_ID_5715S: 2159 cidp->chip_label = 5715; 2160 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2161 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2162 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2163 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2164 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2165 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2166 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5715; 2167 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2168 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2169 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2170 cidp->pci_type = BGE_PCI_E; 2171 cidp->statistic_type = BGE_STAT_REG; 2172 if (cidp->revision >= REVISION_ID_5715_A2) 2173 cidp->msi_enabled = bge_enable_msi; 2174 dev_ok = B_TRUE; 2175 break; 2176 2177 case DEVICE_ID_5721: 2178 cidp->chip_label = 5721; 2179 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2180 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2181 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2182 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2183 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2184 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2185 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2186 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2187 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2188 cidp->pci_type = BGE_PCI_E; 2189 cidp->statistic_type = BGE_STAT_REG; 2190 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2191 dev_ok = B_TRUE; 2192 break; 2193 2194 case DEVICE_ID_5722: 2195 cidp->chip_label = 5722; 2196 cidp->pci_type = BGE_PCI_E; 2197 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2198 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2199 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2200 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2201 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2202 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2203 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2204 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2205 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2206 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2207 cidp->statistic_type = BGE_STAT_REG; 2208 dev_ok = B_TRUE; 2209 break; 2210 2211 case DEVICE_ID_5751: 2212 case DEVICE_ID_5751M: 2213 cidp->chip_label = 5751; 2214 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2215 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2216 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2217 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2218 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2219 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2220 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2221 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2222 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2223 cidp->pci_type = BGE_PCI_E; 2224 cidp->statistic_type = BGE_STAT_REG; 2225 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2226 dev_ok = B_TRUE; 2227 break; 2228 2229 case DEVICE_ID_5752: 2230 case DEVICE_ID_5752M: 2231 cidp->chip_label = 5752; 2232 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2233 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2234 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2235 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2236 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2237 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2238 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2239 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2240 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2241 cidp->pci_type = BGE_PCI_E; 2242 cidp->statistic_type = BGE_STAT_REG; 2243 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2244 dev_ok = B_TRUE; 2245 break; 2246 2247 case DEVICE_ID_5789: 2248 cidp->chip_label = 5789; 2249 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2250 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2251 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2252 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2253 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2254 cidp->tx_rings = BGE_RECV_RINGS_MAX_5705; 2255 cidp->pci_type = BGE_PCI_E; 2256 cidp->statistic_type = BGE_STAT_REG; 2257 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2258 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2259 cidp->msi_enabled = B_TRUE; 2260 dev_ok = B_TRUE; 2261 break; 2262 2263 } 2264 2265 /* 2266 * Setup the default jumbo parameter. 2267 */ 2268 cidp->ethmax_size = ETHERMAX; 2269 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_DEFAULT; 2270 cidp->std_buf_size = BGE_STD_BUFF_SIZE; 2271 2272 /* 2273 * If jumbo is enabled and this kind of chipset supports jumbo feature, 2274 * setup below jumbo specific parameters. 2275 * 2276 * For BCM5714/5715, there is only one standard receive ring. So the 2277 * std buffer size should be set to BGE_JUMBO_BUFF_SIZE when jumbo 2278 * feature is enabled. 2279 */ 2280 if (bge_jumbo_enable && 2281 !(cidp->flags & CHIP_FLAG_NO_JUMBO) && 2282 (cidp->default_mtu > BGE_DEFAULT_MTU) && 2283 (cidp->default_mtu <= BGE_MAXIMUM_MTU)) { 2284 if (DEVICE_5714_SERIES_CHIPSETS(bgep)) { 2285 cidp->mbuf_lo_water_rdma = 2286 RDMA_MBUF_LOWAT_5714_JUMBO; 2287 cidp->mbuf_lo_water_rmac = 2288 MAC_RX_MBUF_LOWAT_5714_JUMBO; 2289 cidp->mbuf_hi_water = MBUF_HIWAT_5714_JUMBO; 2290 cidp->jumbo_slots = 0; 2291 cidp->std_buf_size = BGE_JUMBO_BUFF_SIZE; 2292 } else { 2293 cidp->mbuf_lo_water_rdma = 2294 RDMA_MBUF_LOWAT_JUMBO; 2295 cidp->mbuf_lo_water_rmac = 2296 MAC_RX_MBUF_LOWAT_JUMBO; 2297 cidp->mbuf_hi_water = MBUF_HIWAT_JUMBO; 2298 cidp->jumbo_slots = BGE_JUMBO_SLOTS_USED; 2299 } 2300 cidp->recv_jumbo_size = BGE_JUMBO_BUFF_SIZE; 2301 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_JUMBO; 2302 cidp->ethmax_size = cidp->default_mtu + 2303 sizeof (struct ether_header); 2304 } 2305 2306 /* 2307 * Identify the NV memory type: SEEPROM or Flash? 2308 */ 2309 cidp->nvtype = bge_nvmem_id(bgep); 2310 2311 /* 2312 * Now, we want to check whether this device is part of a 2313 * supported subsystem (e.g., on the motherboard of a Sun 2314 * branded platform). 2315 * 2316 * Rule 1: If the Subsystem Vendor ID is "Sun", then it's OK ;-) 2317 */ 2318 if (cidp->subven == VENDOR_ID_SUN) 2319 sys_ok = B_TRUE; 2320 2321 /* 2322 * Rule 2: If it's on the list on known subsystems, then it's OK. 2323 * Note: 0x14e41647 should *not* appear in the list, but the code 2324 * doesn't enforce that. 2325 */ 2326 err = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, bgep->devinfo, 2327 DDI_PROP_DONTPASS, knownids_propname, &ids, &i); 2328 if (err == DDI_PROP_SUCCESS) { 2329 /* 2330 * Got the list; scan for a matching subsystem vendor/device 2331 */ 2332 subid = (cidp->subven << 16) | cidp->subdev; 2333 while (i--) 2334 if (ids[i] == subid) 2335 sys_ok = B_TRUE; 2336 ddi_prop_free(ids); 2337 } 2338 2339 /* 2340 * Rule 3: If it's a Taco/ENWS motherboard device, then it's OK 2341 * 2342 * Unfortunately, early SunBlade 1500s and 2500s didn't reprogram 2343 * the Subsystem Vendor ID, so it defaults to Broadcom. Therefore, 2344 * we have to check specially for the exact device paths to the 2345 * motherboard devices on those platforms ;-( 2346 * 2347 * Note: we can't just use the "supported-subsystems" mechanism 2348 * above, because the entry would have to be 0x14e41647 -- which 2349 * would then accept *any* plugin card that *didn't* contain a 2350 * (valid) SEEPROM ;-( 2351 */ 2352 sysname = ddi_node_name(ddi_root_node()); 2353 devname = ddi_pathname(bgep->devinfo, buf); 2354 ASSERT(strlen(devname) > 0); 2355 if (strcmp(sysname, "SUNW,Sun-Blade-1500") == 0) /* Taco */ 2356 if (strcmp(devname, "/pci@1f,700000/network@2") == 0) 2357 sys_ok = B_TRUE; 2358 if (strcmp(sysname, "SUNW,Sun-Blade-2500") == 0) /* ENWS */ 2359 if (strcmp(devname, "/pci@1c,600000/network@3") == 0) 2360 sys_ok = B_TRUE; 2361 2362 /* 2363 * Now check what we've discovered: is this truly a supported 2364 * chip on (the motherboard of) a supported platform? 2365 * 2366 * Possible problems here: 2367 * 1) it's a completely unheard-of chip (e.g. 5761) 2368 * 2) it's a recognised but unsupported chip (e.g. 5701, 5703C-A0) 2369 * 3) it's a chip we would support if it were on the motherboard 2370 * of a Sun platform, but this one isn't ;-( 2371 */ 2372 if (cidp->chip_label == 0) 2373 bge_problem(bgep, 2374 "Device 'pci%04x,%04x' not recognized (%d?)", 2375 cidp->vendor, cidp->device, cidp->device); 2376 else if (!dev_ok) 2377 bge_problem(bgep, 2378 "Device 'pci%04x,%04x' (%d) revision %d not supported", 2379 cidp->vendor, cidp->device, cidp->chip_label, 2380 cidp->revision); 2381 #if BGE_DEBUGGING 2382 else if (!sys_ok) 2383 bge_problem(bgep, 2384 "%d-based subsystem 'pci%04x,%04x' not validated", 2385 cidp->chip_label, cidp->subven, cidp->subdev); 2386 #endif 2387 else 2388 cidp->flags |= CHIP_FLAG_SUPPORTED; 2389 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 2390 return (EIO); 2391 return (0); 2392 } 2393 2394 void 2395 bge_chip_msi_trig(bge_t *bgep) 2396 { 2397 uint32_t regval; 2398 2399 regval = bgep->param_msi_cnt<<4; 2400 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, regval); 2401 BGE_DEBUG(("bge_chip_msi_trig:data = %d", regval)); 2402 } 2403 2404 /* 2405 * Various registers that control the chip's internal engines (state 2406 * machines) have a <reset> and <enable> bits (fortunately, in the 2407 * same place in each such register :-). 2408 * 2409 * To reset the state machine, the <reset> bit must be written with 1; 2410 * it will then read back as 1 while the reset is in progress, but 2411 * self-clear to 0 when the reset completes. 2412 * 2413 * To enable a state machine, one must set the <enable> bit, which 2414 * will continue to read back as 0 until the state machine is running. 2415 * 2416 * To disable a state machine, the <enable> bit must be cleared, but 2417 * it will continue to read back as 1 until the state machine actually 2418 * stops. 2419 * 2420 * This routine implements polling for completion of a reset, enable 2421 * or disable operation, returning B_TRUE on success (bit reached the 2422 * required state) or B_FALSE on timeout (200*100us == 20ms). 2423 */ 2424 static boolean_t bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 2425 uint32_t mask, uint32_t val); 2426 #pragma no_inline(bge_chip_poll_engine) 2427 2428 static boolean_t 2429 bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 2430 uint32_t mask, uint32_t val) 2431 { 2432 uint32_t regval; 2433 uint32_t n; 2434 2435 BGE_TRACE(("bge_chip_poll_engine($%p, 0x%lx, 0x%x, 0x%x)", 2436 (void *)bgep, regno, mask, val)); 2437 2438 for (n = 200; n; --n) { 2439 regval = bge_reg_get32(bgep, regno); 2440 if ((regval & mask) == val) 2441 return (B_TRUE); 2442 drv_usecwait(100); 2443 } 2444 2445 bge_fm_ereport(bgep, DDI_FM_DEVICE_NO_RESPONSE); 2446 return (B_FALSE); 2447 } 2448 2449 /* 2450 * Various registers that control the chip's internal engines (state 2451 * machines) have a <reset> bit (fortunately, in the same place in 2452 * each such register :-). To reset the state machine, this bit must 2453 * be written with 1; it will then read back as 1 while the reset is 2454 * in progress, but self-clear to 0 when the reset completes. 2455 * 2456 * This code sets the bit, then polls for it to read back as zero. 2457 * The return value is B_TRUE on success (reset bit cleared itself), 2458 * or B_FALSE if the state machine didn't recover :( 2459 * 2460 * NOTE: the Core reset is similar to other resets, except that we 2461 * can't poll for completion, since the Core reset disables memory 2462 * access! So we just have to assume that it will all complete in 2463 * 100us. See Broadcom document 570X-PG102-R, p102, steps 4-5. 2464 */ 2465 static boolean_t bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno); 2466 #pragma no_inline(bge_chip_reset_engine) 2467 2468 static boolean_t 2469 bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno) 2470 { 2471 uint32_t regval; 2472 uint32_t val32; 2473 2474 regval = bge_reg_get32(bgep, regno); 2475 2476 BGE_TRACE(("bge_chip_reset_engine($%p, 0x%lx)", 2477 (void *)bgep, regno)); 2478 BGE_DEBUG(("bge_chip_reset_engine: 0x%lx before reset = 0x%08x", 2479 regno, regval)); 2480 2481 regval |= STATE_MACHINE_RESET_BIT; 2482 2483 switch (regno) { 2484 case MISC_CONFIG_REG: 2485 /* 2486 * BCM5714/5721/5751 pcie chip special case. In order to avoid 2487 * resetting PCIE block and bringing PCIE link down, bit 29 2488 * in the register needs to be set first, and then set it again 2489 * while the reset bit is written. 2490 * See:P500 of 57xx-PG102-RDS.pdf. 2491 */ 2492 if (DEVICE_5705_SERIES_CHIPSETS(bgep)|| 2493 DEVICE_5721_SERIES_CHIPSETS(bgep)|| 2494 DEVICE_5714_SERIES_CHIPSETS(bgep)|| 2495 DEVICE_5906_SERIES_CHIPSETS(bgep)) { 2496 regval |= MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE; 2497 if (bgep->chipid.pci_type == BGE_PCI_E) { 2498 if (bgep->chipid.asic_rev == 2499 MHCR_CHIP_REV_5751_A0 || 2500 bgep->chipid.asic_rev == 2501 MHCR_CHIP_REV_5721_A0 || 2502 bgep->chipid.asic_rev == 2503 MHCR_CHIP_REV_5755_A0) { 2504 val32 = bge_reg_get32(bgep, 2505 PHY_TEST_CTRL_REG); 2506 if (val32 == (PHY_PCIE_SCRAM_MODE | 2507 PHY_PCIE_LTASS_MODE)) 2508 bge_reg_put32(bgep, 2509 PHY_TEST_CTRL_REG, 2510 PHY_PCIE_SCRAM_MODE); 2511 val32 = pci_config_get32 2512 (bgep->cfg_handle, 2513 PCI_CONF_BGE_CLKCTL); 2514 val32 |= CLKCTL_PCIE_A0_FIX; 2515 pci_config_put32(bgep->cfg_handle, 2516 PCI_CONF_BGE_CLKCTL, val32); 2517 } 2518 bge_reg_set32(bgep, regno, 2519 MISC_CONFIG_GRC_RESET_DISABLE); 2520 regval |= MISC_CONFIG_GRC_RESET_DISABLE; 2521 } 2522 } 2523 2524 /* 2525 * Special case - causes Core reset 2526 * 2527 * On SPARC v9 we want to ensure that we don't start 2528 * timing until the I/O access has actually reached 2529 * the chip, otherwise we might make the next access 2530 * too early. And we can't just force the write out 2531 * by following it with a read (even to config space) 2532 * because that would cause the fault we're trying 2533 * to avoid. Hence the need for membar_sync() here. 2534 */ 2535 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), regval); 2536 #ifdef __sparcv9 2537 membar_sync(); 2538 #endif /* __sparcv9 */ 2539 /* 2540 * On some platforms,system need about 300us for 2541 * link setup. 2542 */ 2543 drv_usecwait(300); 2544 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) { 2545 bge_reg_set32(bgep, VCPU_STATUS_REG, VCPU_DRV_RESET); 2546 bge_reg_clr32( 2547 bgep, VCPU_EXT_CTL, VCPU_EXT_CTL_HALF); 2548 } 2549 2550 if (bgep->chipid.pci_type == BGE_PCI_E) { 2551 /* PCI-E device need more reset time */ 2552 drv_usecwait(120000); 2553 2554 /* Set PCIE max payload size and clear error status. */ 2555 if ((bgep->chipid.chip_label == 5721) || 2556 (bgep->chipid.chip_label == 5751) || 2557 (bgep->chipid.chip_label == 5752) || 2558 (bgep->chipid.chip_label == 5789) || 2559 (bgep->chipid.chip_label == 5906)) { 2560 pci_config_put16(bgep->cfg_handle, 2561 PCI_CONF_DEV_CTRL, READ_REQ_SIZE_MAX); 2562 pci_config_put16(bgep->cfg_handle, 2563 PCI_CONF_DEV_STUS, DEVICE_ERROR_STUS); 2564 } 2565 } 2566 2567 BGE_PCICHK(bgep); 2568 return (B_TRUE); 2569 2570 default: 2571 bge_reg_put32(bgep, regno, regval); 2572 return (bge_chip_poll_engine(bgep, regno, 2573 STATE_MACHINE_RESET_BIT, 0)); 2574 } 2575 } 2576 2577 /* 2578 * Various registers that control the chip's internal engines (state 2579 * machines) have an <enable> bit (fortunately, in the same place in 2580 * each such register :-). To stop the state machine, this bit must 2581 * be written with 0, then polled to see when the state machine has 2582 * actually stopped. 2583 * 2584 * The return value is B_TRUE on success (enable bit cleared), or 2585 * B_FALSE if the state machine didn't stop :( 2586 */ 2587 static boolean_t bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, 2588 uint32_t morebits); 2589 #pragma no_inline(bge_chip_disable_engine) 2590 2591 static boolean_t 2592 bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 2593 { 2594 uint32_t regval; 2595 2596 BGE_TRACE(("bge_chip_disable_engine($%p, 0x%lx, 0x%x)", 2597 (void *)bgep, regno, morebits)); 2598 2599 switch (regno) { 2600 case FTQ_RESET_REG: 2601 /* 2602 * For Schumacher's bugfix CR6490108 2603 */ 2604 #ifdef BGE_IPMI_ASF 2605 #ifdef BGE_NETCONSOLE 2606 if (bgep->asf_enabled) 2607 return (B_TRUE); 2608 #endif 2609 #endif 2610 /* 2611 * Not quite like the others; it doesn't 2612 * have an <enable> bit, but instead we 2613 * have to set and then clear all the bits 2614 */ 2615 bge_reg_put32(bgep, regno, ~(uint32_t)0); 2616 drv_usecwait(100); 2617 bge_reg_put32(bgep, regno, 0); 2618 return (B_TRUE); 2619 2620 default: 2621 regval = bge_reg_get32(bgep, regno); 2622 regval &= ~STATE_MACHINE_ENABLE_BIT; 2623 regval &= ~morebits; 2624 bge_reg_put32(bgep, regno, regval); 2625 return (bge_chip_poll_engine(bgep, regno, 2626 STATE_MACHINE_ENABLE_BIT, 0)); 2627 } 2628 } 2629 2630 /* 2631 * Various registers that control the chip's internal engines (state 2632 * machines) have an <enable> bit (fortunately, in the same place in 2633 * each such register :-). To start the state machine, this bit must 2634 * be written with 1, then polled to see when the state machine has 2635 * actually started. 2636 * 2637 * The return value is B_TRUE on success (enable bit set), or 2638 * B_FALSE if the state machine didn't start :( 2639 */ 2640 static boolean_t bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, 2641 uint32_t morebits); 2642 #pragma no_inline(bge_chip_enable_engine) 2643 2644 static boolean_t 2645 bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 2646 { 2647 uint32_t regval; 2648 2649 BGE_TRACE(("bge_chip_enable_engine($%p, 0x%lx, 0x%x)", 2650 (void *)bgep, regno, morebits)); 2651 2652 switch (regno) { 2653 case FTQ_RESET_REG: 2654 #ifdef BGE_IPMI_ASF 2655 #ifdef BGE_NETCONSOLE 2656 if (bgep->asf_enabled) 2657 return (B_TRUE); 2658 #endif 2659 #endif 2660 /* 2661 * Not quite like the others; it doesn't 2662 * have an <enable> bit, but instead we 2663 * have to set and then clear all the bits 2664 */ 2665 bge_reg_put32(bgep, regno, ~(uint32_t)0); 2666 drv_usecwait(100); 2667 bge_reg_put32(bgep, regno, 0); 2668 return (B_TRUE); 2669 2670 default: 2671 regval = bge_reg_get32(bgep, regno); 2672 regval |= STATE_MACHINE_ENABLE_BIT; 2673 regval |= morebits; 2674 bge_reg_put32(bgep, regno, regval); 2675 return (bge_chip_poll_engine(bgep, regno, 2676 STATE_MACHINE_ENABLE_BIT, STATE_MACHINE_ENABLE_BIT)); 2677 } 2678 } 2679 2680 /* 2681 * Reprogram the Ethernet, Transmit, and Receive MAC 2682 * modes to match the param_* variables 2683 */ 2684 void bge_sync_mac_modes(bge_t *bgep); 2685 #pragma no_inline(bge_sync_mac_modes) 2686 2687 void 2688 bge_sync_mac_modes(bge_t *bgep) 2689 { 2690 uint32_t macmode; 2691 uint32_t regval; 2692 2693 ASSERT(mutex_owned(bgep->genlock)); 2694 2695 /* 2696 * Reprogram the Ethernet MAC mode ... 2697 */ 2698 macmode = regval = bge_reg_get32(bgep, ETHERNET_MAC_MODE_REG); 2699 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 2700 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) 2701 if (DEVICE_5714_SERIES_CHIPSETS(bgep)) 2702 macmode |= ETHERNET_MODE_LINK_POLARITY; 2703 else 2704 macmode &= ~ETHERNET_MODE_LINK_POLARITY; 2705 else 2706 macmode |= ETHERNET_MODE_LINK_POLARITY; 2707 macmode &= ~ETHERNET_MODE_PORTMODE_MASK; 2708 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 2709 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) { 2710 if (DEVICE_5714_SERIES_CHIPSETS(bgep)) 2711 macmode |= ETHERNET_MODE_PORTMODE_GMII; 2712 else 2713 macmode |= ETHERNET_MODE_PORTMODE_TBI; 2714 } else if (bgep->param_link_speed == 10 || 2715 bgep->param_link_speed == 100) 2716 macmode |= ETHERNET_MODE_PORTMODE_MII; 2717 else 2718 macmode |= ETHERNET_MODE_PORTMODE_GMII; 2719 if (bgep->param_link_duplex == LINK_DUPLEX_HALF) 2720 macmode |= ETHERNET_MODE_HALF_DUPLEX; 2721 else 2722 macmode &= ~ETHERNET_MODE_HALF_DUPLEX; 2723 if (bgep->param_loop_mode == BGE_LOOP_INTERNAL_MAC) 2724 macmode |= ETHERNET_MODE_MAC_LOOPBACK; 2725 else 2726 macmode &= ~ETHERNET_MODE_MAC_LOOPBACK; 2727 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, macmode); 2728 BGE_DEBUG(("bge_sync_mac_modes($%p) Ethernet MAC mode 0x%x => 0x%x", 2729 (void *)bgep, regval, macmode)); 2730 2731 /* 2732 * ... the Transmit MAC mode ... 2733 */ 2734 macmode = regval = bge_reg_get32(bgep, TRANSMIT_MAC_MODE_REG); 2735 if (bgep->param_link_tx_pause) 2736 macmode |= TRANSMIT_MODE_FLOW_CONTROL; 2737 else 2738 macmode &= ~TRANSMIT_MODE_FLOW_CONTROL; 2739 bge_reg_put32(bgep, TRANSMIT_MAC_MODE_REG, macmode); 2740 BGE_DEBUG(("bge_sync_mac_modes($%p) Transmit MAC mode 0x%x => 0x%x", 2741 (void *)bgep, regval, macmode)); 2742 2743 /* 2744 * ... and the Receive MAC mode 2745 */ 2746 macmode = regval = bge_reg_get32(bgep, RECEIVE_MAC_MODE_REG); 2747 if (bgep->param_link_rx_pause) 2748 macmode |= RECEIVE_MODE_FLOW_CONTROL; 2749 else 2750 macmode &= ~RECEIVE_MODE_FLOW_CONTROL; 2751 bge_reg_put32(bgep, RECEIVE_MAC_MODE_REG, macmode); 2752 BGE_DEBUG(("bge_sync_mac_modes($%p) Receive MAC mode 0x%x => 0x%x", 2753 (void *)bgep, regval, macmode)); 2754 } 2755 2756 /* 2757 * bge_chip_sync() -- program the chip with the unicast MAC address, 2758 * the multicast hash table, the required level of promiscuity, and 2759 * the current loopback mode ... 2760 */ 2761 #ifdef BGE_IPMI_ASF 2762 int bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive); 2763 #else 2764 int bge_chip_sync(bge_t *bgep); 2765 #endif 2766 #pragma no_inline(bge_chip_sync) 2767 2768 int 2769 #ifdef BGE_IPMI_ASF 2770 bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive) 2771 #else 2772 bge_chip_sync(bge_t *bgep) 2773 #endif 2774 { 2775 void (*opfn)(bge_t *bgep, bge_regno_t reg, uint32_t bits); 2776 boolean_t promisc; 2777 uint64_t macaddr; 2778 uint32_t fill = 0; 2779 int i, j; 2780 int retval = DDI_SUCCESS; 2781 2782 BGE_TRACE(("bge_chip_sync($%p)", 2783 (void *)bgep)); 2784 2785 ASSERT(mutex_owned(bgep->genlock)); 2786 2787 promisc = B_FALSE; 2788 fill = ~(uint32_t)0; 2789 2790 if (bgep->promisc) 2791 promisc = B_TRUE; 2792 else 2793 fill = (uint32_t)0; 2794 2795 /* 2796 * If the TX/RX MAC engines are already running, we should stop 2797 * them (and reset the RX engine) before changing the parameters. 2798 * If they're not running, this will have no effect ... 2799 * 2800 * NOTE: this is currently disabled by default because stopping 2801 * and restarting the Tx engine may cause an outgoing packet in 2802 * transit to be truncated. Also, stopping and restarting the 2803 * Rx engine seems to not work correctly on the 5705. Testing 2804 * has not (yet!) revealed any problems with NOT stopping and 2805 * restarting these engines (and Broadcom say their drivers don't 2806 * do this), but if it is found to cause problems, this variable 2807 * can be patched to re-enable the old behaviour ... 2808 */ 2809 if (bge_stop_start_on_sync) { 2810 #ifdef BGE_IPMI_ASF 2811 if (!bgep->asf_enabled) { 2812 if (!bge_chip_disable_engine(bgep, 2813 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG)) 2814 retval = DDI_FAILURE; 2815 } else { 2816 if (!bge_chip_disable_engine(bgep, 2817 RECEIVE_MAC_MODE_REG, 0)) 2818 retval = DDI_FAILURE; 2819 } 2820 #else 2821 if (!bge_chip_disable_engine(bgep, RECEIVE_MAC_MODE_REG, 2822 RECEIVE_MODE_KEEP_VLAN_TAG)) 2823 retval = DDI_FAILURE; 2824 #endif 2825 if (!bge_chip_disable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 2826 retval = DDI_FAILURE; 2827 if (!bge_chip_reset_engine(bgep, RECEIVE_MAC_MODE_REG)) 2828 retval = DDI_FAILURE; 2829 } 2830 2831 /* 2832 * Reprogram the hashed multicast address table ... 2833 */ 2834 for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i) 2835 bge_reg_put32(bgep, MAC_HASH_REG(i), 0); 2836 2837 for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i) 2838 bge_reg_put32(bgep, MAC_HASH_REG(i), 2839 bgep->mcast_hash[i] | fill); 2840 2841 #ifdef BGE_IPMI_ASF 2842 if (!bgep->asf_enabled || !asf_keeplive) { 2843 #endif 2844 /* 2845 * Transform the MAC address(es) from host to chip format, then 2846 * reprogram the transmit random backoff seed and the unicast 2847 * MAC address(es) ... 2848 */ 2849 for (j = 0; j < MAC_ADDRESS_REGS_MAX; j++) { 2850 for (i = 0, macaddr = 0ull; 2851 i < ETHERADDRL; ++i) { 2852 macaddr <<= 8; 2853 macaddr |= bgep->curr_addr[j].addr[i]; 2854 } 2855 fill += (macaddr >> 16) + (macaddr & 0xffffffff); 2856 bge_reg_put64(bgep, MAC_ADDRESS_REG(j), macaddr); 2857 2858 BGE_DEBUG(("bge_chip_sync($%p) " 2859 "setting MAC address %012llx", 2860 (void *)bgep, macaddr)); 2861 } 2862 #ifdef BGE_IPMI_ASF 2863 } 2864 #endif 2865 /* 2866 * Set random seed of backoff interval 2867 * - Writing zero means no backoff interval 2868 */ 2869 fill = ((fill >> 20) + (fill >> 10) + fill) & 0x3ff; 2870 if (fill == 0) 2871 fill = 1; 2872 bge_reg_put32(bgep, MAC_TX_RANDOM_BACKOFF_REG, fill); 2873 2874 /* 2875 * Set or clear the PROMISCUOUS mode bit 2876 */ 2877 opfn = promisc ? bge_reg_set32 : bge_reg_clr32; 2878 (*opfn)(bgep, RECEIVE_MAC_MODE_REG, RECEIVE_MODE_PROMISCUOUS); 2879 2880 /* 2881 * Sync the rest of the MAC modes too ... 2882 */ 2883 bge_sync_mac_modes(bgep); 2884 2885 /* 2886 * Restart RX/TX MAC engines if required ... 2887 */ 2888 if (bgep->bge_chip_state == BGE_CHIP_RUNNING) { 2889 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 2890 retval = DDI_FAILURE; 2891 #ifdef BGE_IPMI_ASF 2892 if (!bgep->asf_enabled) { 2893 if (!bge_chip_enable_engine(bgep, 2894 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG)) 2895 retval = DDI_FAILURE; 2896 } else { 2897 if (!bge_chip_enable_engine(bgep, 2898 RECEIVE_MAC_MODE_REG, 0)) 2899 retval = DDI_FAILURE; 2900 } 2901 #else 2902 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 2903 RECEIVE_MODE_KEEP_VLAN_TAG)) 2904 retval = DDI_FAILURE; 2905 #endif 2906 } 2907 return (retval); 2908 } 2909 2910 /* 2911 * This array defines the sequence of state machine control registers 2912 * in which the <enable> bit must be cleared to bring the chip to a 2913 * clean stop. Taken from Broadcom document 570X-PG102-R, p116. 2914 */ 2915 static bge_regno_t shutdown_engine_regs[] = { 2916 RECEIVE_MAC_MODE_REG, 2917 RCV_BD_INITIATOR_MODE_REG, 2918 RCV_LIST_PLACEMENT_MODE_REG, 2919 RCV_LIST_SELECTOR_MODE_REG, /* BCM5704 series only */ 2920 RCV_DATA_BD_INITIATOR_MODE_REG, 2921 RCV_DATA_COMPLETION_MODE_REG, 2922 RCV_BD_COMPLETION_MODE_REG, 2923 2924 SEND_BD_SELECTOR_MODE_REG, 2925 SEND_BD_INITIATOR_MODE_REG, 2926 SEND_DATA_INITIATOR_MODE_REG, 2927 READ_DMA_MODE_REG, 2928 SEND_DATA_COMPLETION_MODE_REG, 2929 DMA_COMPLETION_MODE_REG, /* BCM5704 series only */ 2930 SEND_BD_COMPLETION_MODE_REG, 2931 TRANSMIT_MAC_MODE_REG, 2932 2933 HOST_COALESCE_MODE_REG, 2934 WRITE_DMA_MODE_REG, 2935 MBUF_CLUSTER_FREE_MODE_REG, /* BCM5704 series only */ 2936 FTQ_RESET_REG, /* special - see code */ 2937 BUFFER_MANAGER_MODE_REG, /* BCM5704 series only */ 2938 MEMORY_ARBITER_MODE_REG, /* BCM5704 series only */ 2939 BGE_REGNO_NONE /* terminator */ 2940 }; 2941 2942 #ifndef __sparc 2943 static bge_regno_t quiesce_regs[] = { 2944 READ_DMA_MODE_REG, 2945 DMA_COMPLETION_MODE_REG, 2946 WRITE_DMA_MODE_REG, 2947 BGE_REGNO_NONE 2948 }; 2949 2950 void bge_chip_stop_nonblocking(bge_t *bgep); 2951 #pragma no_inline(bge_chip_stop_nonblocking) 2952 2953 /* 2954 * This function is called by bge_quiesce(). We 2955 * turn off all the DMA engines here. 2956 */ 2957 void 2958 bge_chip_stop_nonblocking(bge_t *bgep) 2959 { 2960 bge_regno_t *rbp; 2961 2962 /* 2963 * Flag that no more activity may be initiated 2964 */ 2965 bgep->progress &= ~PROGRESS_READY; 2966 2967 rbp = quiesce_regs; 2968 while (*rbp != BGE_REGNO_NONE) { 2969 (void) bge_chip_disable_engine(bgep, *rbp, 0); 2970 ++rbp; 2971 } 2972 2973 bgep->bge_chip_state = BGE_CHIP_STOPPED; 2974 } 2975 2976 #endif 2977 2978 /* 2979 * bge_chip_stop() -- stop all chip processing 2980 * 2981 * If the <fault> parameter is B_TRUE, we're stopping the chip because 2982 * we've detected a problem internally; otherwise, this is a normal 2983 * (clean) stop (at user request i.e. the last STREAM has been closed). 2984 */ 2985 void bge_chip_stop(bge_t *bgep, boolean_t fault); 2986 #pragma no_inline(bge_chip_stop) 2987 2988 void 2989 bge_chip_stop(bge_t *bgep, boolean_t fault) 2990 { 2991 bge_regno_t regno; 2992 bge_regno_t *rbp; 2993 boolean_t ok; 2994 2995 BGE_TRACE(("bge_chip_stop($%p)", 2996 (void *)bgep)); 2997 2998 ASSERT(mutex_owned(bgep->genlock)); 2999 3000 rbp = shutdown_engine_regs; 3001 /* 3002 * When driver try to shutdown the BCM5705/5788/5721/5751/ 3003 * 5752/5714 and 5715 chipsets,the buffer manager and the mem 3004 * -ory arbiter should not be disabled. 3005 */ 3006 for (ok = B_TRUE; (regno = *rbp) != BGE_REGNO_NONE; ++rbp) { 3007 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3008 ok &= bge_chip_disable_engine(bgep, regno, 0); 3009 else if ((regno != RCV_LIST_SELECTOR_MODE_REG) && 3010 (regno != DMA_COMPLETION_MODE_REG) && 3011 (regno != MBUF_CLUSTER_FREE_MODE_REG)&& 3012 (regno != BUFFER_MANAGER_MODE_REG) && 3013 (regno != MEMORY_ARBITER_MODE_REG)) 3014 ok &= bge_chip_disable_engine(bgep, 3015 regno, 0); 3016 } 3017 3018 if (!ok && !fault) 3019 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 3020 3021 /* 3022 * Finally, disable (all) MAC events & clear the MAC status 3023 */ 3024 bge_reg_put32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 0); 3025 bge_reg_put32(bgep, ETHERNET_MAC_STATUS_REG, ~0); 3026 3027 /* 3028 * if we're stopping the chip because of a detected fault then do 3029 * appropriate actions 3030 */ 3031 if (fault) { 3032 if (bgep->bge_chip_state != BGE_CHIP_FAULT) { 3033 bgep->bge_chip_state = BGE_CHIP_FAULT; 3034 if (!bgep->manual_reset) 3035 ddi_fm_service_impact(bgep->devinfo, 3036 DDI_SERVICE_LOST); 3037 if (bgep->bge_dma_error) { 3038 /* 3039 * need to free buffers in case the fault was 3040 * due to a memory error in a buffer - got to 3041 * do a fair bit of tidying first 3042 */ 3043 if (bgep->progress & PROGRESS_KSTATS) { 3044 bge_fini_kstats(bgep); 3045 bgep->progress &= ~PROGRESS_KSTATS; 3046 } 3047 if (bgep->progress & PROGRESS_INTR) { 3048 bge_intr_disable(bgep); 3049 rw_enter(bgep->errlock, RW_WRITER); 3050 bge_fini_rings(bgep); 3051 rw_exit(bgep->errlock); 3052 bgep->progress &= ~PROGRESS_INTR; 3053 } 3054 if (bgep->progress & PROGRESS_BUFS) { 3055 bge_free_bufs(bgep); 3056 bgep->progress &= ~PROGRESS_BUFS; 3057 } 3058 bgep->bge_dma_error = B_FALSE; 3059 } 3060 } 3061 } else 3062 bgep->bge_chip_state = BGE_CHIP_STOPPED; 3063 } 3064 3065 /* 3066 * Poll for completion of chip's ROM firmware; also, at least on the 3067 * first time through, find and return the hardware MAC address, if any. 3068 */ 3069 static uint64_t bge_poll_firmware(bge_t *bgep); 3070 #pragma no_inline(bge_poll_firmware) 3071 3072 static uint64_t 3073 bge_poll_firmware(bge_t *bgep) 3074 { 3075 uint64_t magic; 3076 uint64_t mac; 3077 uint32_t gen, val; 3078 uint32_t i; 3079 3080 /* 3081 * Step 19: poll for firmware completion (GENCOMM port set 3082 * to the ones complement of T3_MAGIC_NUMBER). 3083 * 3084 * While we're at it, we also read the MAC address register; 3085 * at some stage the firmware will load this with the 3086 * factory-set value. 3087 * 3088 * When both the magic number and the MAC address are set, 3089 * we're done; but we impose a time limit of one second 3090 * (1000*1000us) in case the firmware fails in some fashion 3091 * or the SEEPROM that provides that MAC address isn't fitted. 3092 * 3093 * After the first time through (chip state != INITIAL), we 3094 * don't need the MAC address to be set (we've already got it 3095 * or not, from the first time), so we don't wait for it, but 3096 * we still have to wait for the T3_MAGIC_NUMBER. 3097 * 3098 * Note: the magic number is only a 32-bit quantity, but the NIC 3099 * memory is 64-bit (and big-endian) internally. Addressing the 3100 * GENCOMM word as "the upper half of a 64-bit quantity" makes 3101 * it work correctly on both big- and little-endian hosts. 3102 */ 3103 if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) == 3104 MHCR_CHIP_ASIC_REV_5906) { 3105 for (i = 0; i < 1000; ++i) { 3106 drv_usecwait(1000); 3107 val = bge_reg_get32(bgep, VCPU_STATUS_REG); 3108 if (val & VCPU_INIT_DONE) 3109 break; 3110 } 3111 BGE_DEBUG(("bge_poll_firmware($%p): return after %d loops", 3112 (void *)bgep, i)); 3113 mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0)); 3114 } else { 3115 for (i = 0; i < 1000; ++i) { 3116 drv_usecwait(1000); 3117 gen = bge_nic_get64(bgep, NIC_MEM_GENCOMM) >> 32; 3118 if (i == 0 && DEVICE_5704_SERIES_CHIPSETS(bgep)) 3119 drv_usecwait(100000); 3120 mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0)); 3121 #ifdef BGE_IPMI_ASF 3122 if (!bgep->asf_enabled) { 3123 #endif 3124 if (gen != ~T3_MAGIC_NUMBER) 3125 continue; 3126 #ifdef BGE_IPMI_ASF 3127 } 3128 #endif 3129 if (mac != 0ULL) 3130 break; 3131 if (bgep->bge_chip_state != BGE_CHIP_INITIAL) 3132 break; 3133 } 3134 } 3135 3136 magic = bge_nic_get64(bgep, NIC_MEM_GENCOMM); 3137 BGE_DEBUG(("bge_poll_firmware($%p): PXE magic 0x%x after %d loops", 3138 (void *)bgep, gen, i)); 3139 BGE_DEBUG(("bge_poll_firmware: MAC %016llx, GENCOMM %016llx", 3140 mac, magic)); 3141 3142 return (mac); 3143 } 3144 3145 /* 3146 * Maximum times of trying to get the NVRAM access lock 3147 * by calling bge_nvmem_acquire() 3148 */ 3149 #define MAX_TRY_NVMEM_ACQUIRE 10000 3150 3151 #ifdef BGE_IPMI_ASF 3152 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode); 3153 #else 3154 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma); 3155 #endif 3156 #pragma no_inline(bge_chip_reset) 3157 3158 int 3159 #ifdef BGE_IPMI_ASF 3160 bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode) 3161 #else 3162 bge_chip_reset(bge_t *bgep, boolean_t enable_dma) 3163 #endif 3164 { 3165 chip_id_t chipid; 3166 uint64_t mac; 3167 uint64_t magic; 3168 uint32_t modeflags; 3169 uint32_t mhcr; 3170 uint32_t sx0; 3171 uint32_t i, tries; 3172 #ifdef BGE_IPMI_ASF 3173 uint32_t mailbox; 3174 #endif 3175 int retval = DDI_SUCCESS; 3176 3177 BGE_TRACE(("bge_chip_reset($%p, %d)", 3178 (void *)bgep, enable_dma)); 3179 3180 ASSERT(mutex_owned(bgep->genlock)); 3181 3182 BGE_DEBUG(("bge_chip_reset($%p, %d): current state is %d", 3183 (void *)bgep, enable_dma, bgep->bge_chip_state)); 3184 3185 /* 3186 * Do we need to stop the chip cleanly before resetting? 3187 */ 3188 switch (bgep->bge_chip_state) { 3189 default: 3190 _NOTE(NOTREACHED) 3191 return (DDI_FAILURE); 3192 3193 case BGE_CHIP_INITIAL: 3194 case BGE_CHIP_STOPPED: 3195 case BGE_CHIP_RESET: 3196 break; 3197 3198 case BGE_CHIP_RUNNING: 3199 case BGE_CHIP_ERROR: 3200 case BGE_CHIP_FAULT: 3201 bge_chip_stop(bgep, B_FALSE); 3202 break; 3203 } 3204 3205 #ifdef BGE_IPMI_ASF 3206 if (bgep->asf_enabled) { 3207 #ifdef __sparc 3208 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 3209 MHCR_ENABLE_TAGGED_STATUS_MODE | 3210 MHCR_MASK_INTERRUPT_MODE | 3211 MHCR_MASK_PCI_INT_OUTPUT | 3212 MHCR_CLEAR_INTERRUPT_INTA | 3213 MHCR_ENABLE_ENDIAN_WORD_SWAP | 3214 MHCR_ENABLE_ENDIAN_BYTE_SWAP; 3215 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr); 3216 bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG, 3217 bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG) | 3218 MEMORY_ARBITER_ENABLE); 3219 #endif 3220 if (asf_mode == ASF_MODE_INIT) { 3221 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 3222 } else if (asf_mode == ASF_MODE_SHUTDOWN) { 3223 bge_asf_pre_reset_operations(bgep, BGE_SHUTDOWN_RESET); 3224 } 3225 } 3226 #endif 3227 /* 3228 * Adapted from Broadcom document 570X-PG102-R, pp 102-116. 3229 * Updated to reflect Broadcom document 570X-PG104-R, pp 146-159. 3230 * 3231 * Before reset Core clock,it is 3232 * also required to initialize the Memory Arbiter as specified in step9 3233 * and Misc Host Control Register as specified in step-13 3234 * Step 4-5: reset Core clock & wait for completion 3235 * Steps 6-8: are done by bge_chip_cfg_init() 3236 * put the T3_MAGIC_NUMBER into the GENCOMM port before reset 3237 */ 3238 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 3239 retval = DDI_FAILURE; 3240 3241 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 3242 MHCR_ENABLE_TAGGED_STATUS_MODE | 3243 MHCR_MASK_INTERRUPT_MODE | 3244 MHCR_MASK_PCI_INT_OUTPUT | 3245 MHCR_CLEAR_INTERRUPT_INTA; 3246 #ifdef _BIG_ENDIAN 3247 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 3248 #endif /* _BIG_ENDIAN */ 3249 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr); 3250 #ifdef BGE_IPMI_ASF 3251 if (bgep->asf_enabled) 3252 bgep->asf_wordswapped = B_FALSE; 3253 #endif 3254 /* 3255 * NVRAM Corruption Workaround 3256 */ 3257 for (tries = 0; tries < MAX_TRY_NVMEM_ACQUIRE; tries++) 3258 if (bge_nvmem_acquire(bgep) != EAGAIN) 3259 break; 3260 if (tries >= MAX_TRY_NVMEM_ACQUIRE) 3261 BGE_DEBUG(("%s: fail to acquire nvram lock", 3262 bgep->ifname)); 3263 3264 #ifdef BGE_IPMI_ASF 3265 if (!bgep->asf_enabled) { 3266 #endif 3267 magic = (uint64_t)T3_MAGIC_NUMBER << 32; 3268 bge_nic_put64(bgep, NIC_MEM_GENCOMM, magic); 3269 #ifdef BGE_IPMI_ASF 3270 } 3271 #endif 3272 3273 if (!bge_chip_reset_engine(bgep, MISC_CONFIG_REG)) 3274 retval = DDI_FAILURE; 3275 bge_chip_cfg_init(bgep, &chipid, enable_dma); 3276 3277 /* 3278 * Step 8a: This may belong elsewhere, but BCM5721 needs 3279 * a bit set to avoid a fifo overflow/underflow bug. 3280 */ 3281 if ((bgep->chipid.chip_label == 5721) || 3282 (bgep->chipid.chip_label == 5751) || 3283 (bgep->chipid.chip_label == 5752) || 3284 (bgep->chipid.chip_label == 5755) || 3285 (bgep->chipid.chip_label == 5756) || 3286 (bgep->chipid.chip_label == 5789) || 3287 (bgep->chipid.chip_label == 5906)) 3288 bge_reg_set32(bgep, TLP_CONTROL_REG, TLP_DATA_FIFO_PROTECT); 3289 3290 3291 /* 3292 * Step 9: enable MAC memory arbiter,bit30 and bit31 of 5714/5715 should 3293 * not be changed. 3294 */ 3295 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 3296 retval = DDI_FAILURE; 3297 3298 /* 3299 * Steps 10-11: configure PIO endianness options and 3300 * enable indirect register access -- already done 3301 * Steps 12-13: enable writing to the PCI state & clock 3302 * control registers -- not required; we aren't going to 3303 * use those features. 3304 * Steps 14-15: Configure DMA endianness options. See 3305 * the comments on the setting of the MHCR above. 3306 */ 3307 #ifdef _BIG_ENDIAN 3308 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME | 3309 MODE_WORD_SWAP_NONFRAME | MODE_BYTE_SWAP_NONFRAME; 3310 #else 3311 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME; 3312 #endif /* _BIG_ENDIAN */ 3313 #ifdef BGE_IPMI_ASF 3314 if (bgep->asf_enabled) 3315 modeflags |= MODE_HOST_STACK_UP; 3316 #endif 3317 bge_reg_put32(bgep, MODE_CONTROL_REG, modeflags); 3318 3319 #ifdef BGE_IPMI_ASF 3320 if (bgep->asf_enabled) { 3321 #ifdef __sparc 3322 bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG, 3323 MEMORY_ARBITER_ENABLE | 3324 bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG)); 3325 #endif 3326 3327 #ifdef BGE_NETCONSOLE 3328 if (!bgep->asf_newhandshake) { 3329 if ((asf_mode == ASF_MODE_INIT) || 3330 (asf_mode == ASF_MODE_POST_INIT)) { 3331 bge_asf_post_reset_old_mode(bgep, 3332 BGE_INIT_RESET); 3333 } else { 3334 bge_asf_post_reset_old_mode(bgep, 3335 BGE_SHUTDOWN_RESET); 3336 } 3337 } 3338 #endif 3339 3340 /* Wait for NVRAM init */ 3341 i = 0; 3342 drv_usecwait(5000); 3343 mailbox = bge_nic_get32(bgep, BGE_FIRMWARE_MAILBOX); 3344 3345 while ((mailbox != (uint32_t) 3346 ~BGE_MAGIC_NUM_FIRMWARE_INIT_DONE) && 3347 (i < 10000)) { 3348 drv_usecwait(100); 3349 mailbox = bge_nic_get32(bgep, 3350 BGE_FIRMWARE_MAILBOX); 3351 i++; 3352 } 3353 3354 #ifndef BGE_NETCONSOLE 3355 if (!bgep->asf_newhandshake) { 3356 if ((asf_mode == ASF_MODE_INIT) || 3357 (asf_mode == ASF_MODE_POST_INIT)) { 3358 3359 bge_asf_post_reset_old_mode(bgep, 3360 BGE_INIT_RESET); 3361 } else { 3362 bge_asf_post_reset_old_mode(bgep, 3363 BGE_SHUTDOWN_RESET); 3364 } 3365 } 3366 #endif 3367 } 3368 #endif 3369 /* 3370 * Steps 16-17: poll for firmware completion 3371 */ 3372 mac = bge_poll_firmware(bgep); 3373 3374 /* 3375 * Step 18: enable external memory -- doesn't apply. 3376 * 3377 * However we take the opportunity to set the MLCR anyway, as 3378 * this register also controls the SEEPROM auto-access method 3379 * which we may want to use later ... 3380 * 3381 * The proper value here depends on the way the chip is wired 3382 * into the circuit board, as this register *also* controls which 3383 * of the "Miscellaneous I/O" pins are driven as outputs and the 3384 * values driven onto those pins! 3385 * 3386 * See also step 74 in the PRM ... 3387 */ 3388 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, 3389 bgep->chipid.bge_mlcr_default); 3390 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 3391 3392 /* 3393 * Step 20: clear the Ethernet MAC mode register 3394 */ 3395 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, 0); 3396 3397 /* 3398 * Step 21: restore cache-line-size, latency timer, and 3399 * subsystem ID registers to their original values (not 3400 * those read into the local structure <chipid>, 'cos 3401 * that was after they were cleared by the RESET). 3402 * 3403 * Note: the Subsystem Vendor/Device ID registers are not 3404 * directly writable in config space, so we use the shadow 3405 * copy in "Page Zero" of register space to restore them 3406 * both in one go ... 3407 */ 3408 pci_config_put8(bgep->cfg_handle, PCI_CONF_CACHE_LINESZ, 3409 bgep->chipid.clsize); 3410 pci_config_put8(bgep->cfg_handle, PCI_CONF_LATENCY_TIMER, 3411 bgep->chipid.latency); 3412 bge_reg_put32(bgep, PCI_CONF_SUBVENID, 3413 (bgep->chipid.subdev << 16) | bgep->chipid.subven); 3414 3415 /* 3416 * The SEND INDEX registers should be reset to zero by the 3417 * global chip reset; if they're not, there'll be trouble 3418 * later on. 3419 */ 3420 sx0 = bge_reg_get32(bgep, NIC_DIAG_SEND_INDEX_REG(0)); 3421 if (sx0 != 0) { 3422 BGE_REPORT((bgep, "SEND INDEX - device didn't RESET")); 3423 bge_fm_ereport(bgep, DDI_FM_DEVICE_INVAL_STATE); 3424 retval = DDI_FAILURE; 3425 } 3426 3427 /* Enable MSI code */ 3428 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 3429 bge_reg_set32(bgep, MSI_MODE_REG, 3430 MSI_PRI_HIGHEST|MSI_MSI_ENABLE|MSI_ERROR_ATTENTION); 3431 3432 /* 3433 * On the first time through, save the factory-set MAC address 3434 * (if any). If bge_poll_firmware() above didn't return one 3435 * (from a chip register) consider looking in the attached NV 3436 * memory device, if any. Once we have it, we save it in both 3437 * register-image (64-bit) and byte-array forms. All-zero and 3438 * all-one addresses are not valid, and we refuse to stash those. 3439 */ 3440 if (bgep->bge_chip_state == BGE_CHIP_INITIAL) { 3441 if (mac == 0ULL) 3442 mac = bge_get_nvmac(bgep); 3443 if (mac != 0ULL && mac != ~0ULL) { 3444 bgep->chipid.hw_mac_addr = mac; 3445 for (i = ETHERADDRL; i-- != 0; ) { 3446 bgep->chipid.vendor_addr.addr[i] = (uchar_t)mac; 3447 mac >>= 8; 3448 } 3449 bgep->chipid.vendor_addr.set = B_TRUE; 3450 } 3451 } 3452 3453 #ifdef BGE_IPMI_ASF 3454 if (bgep->asf_enabled && bgep->asf_newhandshake) { 3455 if (asf_mode != ASF_MODE_NONE) { 3456 if ((asf_mode == ASF_MODE_INIT) || 3457 (asf_mode == ASF_MODE_POST_INIT)) { 3458 3459 bge_asf_post_reset_new_mode(bgep, 3460 BGE_INIT_RESET); 3461 } else { 3462 bge_asf_post_reset_new_mode(bgep, 3463 BGE_SHUTDOWN_RESET); 3464 } 3465 } 3466 } 3467 #endif 3468 3469 /* 3470 * Record the new state 3471 */ 3472 bgep->chip_resets += 1; 3473 bgep->bge_chip_state = BGE_CHIP_RESET; 3474 return (retval); 3475 } 3476 3477 /* 3478 * bge_chip_start() -- start the chip transmitting and/or receiving, 3479 * including enabling interrupts 3480 */ 3481 int bge_chip_start(bge_t *bgep, boolean_t reset_phys); 3482 #pragma no_inline(bge_chip_start) 3483 3484 int 3485 bge_chip_start(bge_t *bgep, boolean_t reset_phys) 3486 { 3487 uint32_t coalmode; 3488 uint32_t ledctl; 3489 uint32_t mtu; 3490 uint32_t maxring; 3491 uint32_t stats_mask; 3492 uint32_t dma_wrprio; 3493 uint64_t ring; 3494 int retval = DDI_SUCCESS; 3495 3496 BGE_TRACE(("bge_chip_start($%p)", 3497 (void *)bgep)); 3498 3499 ASSERT(mutex_owned(bgep->genlock)); 3500 ASSERT(bgep->bge_chip_state == BGE_CHIP_RESET); 3501 3502 /* 3503 * Taken from Broadcom document 570X-PG102-R, pp 102-116. 3504 * The document specifies 95 separate steps to fully 3505 * initialise the chip!!!! 3506 * 3507 * The reset code above has already got us as far as step 3508 * 21, so we continue with ... 3509 * 3510 * Step 22: clear the MAC statistics block 3511 * (0x0300-0x0aff in NIC-local memory) 3512 */ 3513 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 3514 bge_nic_zero(bgep, NIC_MEM_STATISTICS, 3515 NIC_MEM_STATISTICS_SIZE); 3516 3517 /* 3518 * Step 23: clear the status block (in host memory) 3519 */ 3520 DMA_ZERO(bgep->status_block); 3521 3522 /* 3523 * Step 24: set DMA read/write control register 3524 */ 3525 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_PDRWCR, 3526 bgep->chipid.bge_dma_rwctrl); 3527 3528 /* 3529 * Step 25: Configure DMA endianness -- already done (16/17) 3530 * Step 26: Configure Host-Based Send Rings 3531 * Step 27: Indicate Host Stack Up 3532 */ 3533 bge_reg_set32(bgep, MODE_CONTROL_REG, 3534 MODE_HOST_SEND_BDS | 3535 MODE_HOST_STACK_UP); 3536 3537 /* 3538 * Step 28: Configure checksum options: 3539 * Solaris supports the hardware default checksum options. 3540 * 3541 * Workaround for Incorrect pseudo-header checksum calculation. 3542 */ 3543 if (bgep->chipid.flags & CHIP_FLAG_PARTIAL_CSUM) 3544 bge_reg_set32(bgep, MODE_CONTROL_REG, 3545 MODE_SEND_NO_PSEUDO_HDR_CSUM); 3546 3547 /* 3548 * Step 29: configure Timer Prescaler. The value is always the 3549 * same: the Core Clock frequency in MHz (66), minus 1, shifted 3550 * into bits 7-1. Don't set bit 0, 'cos that's the RESET bit 3551 * for the whole chip! 3552 */ 3553 bge_reg_put32(bgep, MISC_CONFIG_REG, MISC_CONFIG_DEFAULT); 3554 3555 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) { 3556 drv_usecwait(40); 3557 /* put PHY into ready state */ 3558 bge_reg_clr32(bgep, MISC_CONFIG_REG, MISC_CONFIG_EPHY_IDDQ); 3559 (void) bge_reg_get32(bgep, MISC_CONFIG_REG); /* flush */ 3560 drv_usecwait(40); 3561 } 3562 3563 /* 3564 * Steps 30-31: Configure MAC local memory pool & DMA pool registers 3565 * 3566 * If the mbuf_length is specified as 0, we just leave these at 3567 * their hardware defaults, rather than explicitly setting them. 3568 * As the Broadcom HRM,driver better not change the parameters 3569 * when the chipsets is 5705/5788/5721/5751/5714 and 5715. 3570 */ 3571 if ((bgep->chipid.mbuf_length != 0) && 3572 (DEVICE_5704_SERIES_CHIPSETS(bgep))) { 3573 bge_reg_put32(bgep, MBUF_POOL_BASE_REG, 3574 bgep->chipid.mbuf_base); 3575 bge_reg_put32(bgep, MBUF_POOL_LENGTH_REG, 3576 bgep->chipid.mbuf_length); 3577 bge_reg_put32(bgep, DMAD_POOL_BASE_REG, 3578 DMAD_POOL_BASE_DEFAULT); 3579 bge_reg_put32(bgep, DMAD_POOL_LENGTH_REG, 3580 DMAD_POOL_LENGTH_DEFAULT); 3581 } 3582 3583 /* 3584 * Step 32: configure MAC memory pool watermarks 3585 */ 3586 bge_reg_put32(bgep, RDMA_MBUF_LOWAT_REG, 3587 bgep->chipid.mbuf_lo_water_rdma); 3588 bge_reg_put32(bgep, MAC_RX_MBUF_LOWAT_REG, 3589 bgep->chipid.mbuf_lo_water_rmac); 3590 bge_reg_put32(bgep, MBUF_HIWAT_REG, 3591 bgep->chipid.mbuf_hi_water); 3592 3593 /* 3594 * Step 33: configure DMA resource watermarks 3595 */ 3596 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3597 bge_reg_put32(bgep, DMAD_POOL_LOWAT_REG, 3598 bge_dmad_lo_water); 3599 bge_reg_put32(bgep, DMAD_POOL_HIWAT_REG, 3600 bge_dmad_hi_water); 3601 } 3602 bge_reg_put32(bgep, LOWAT_MAX_RECV_FRAMES_REG, bge_lowat_recv_frames); 3603 3604 /* 3605 * Steps 34-36: enable buffer manager & internal h/w queues 3606 */ 3607 if (!bge_chip_enable_engine(bgep, BUFFER_MANAGER_MODE_REG, 3608 STATE_MACHINE_ATTN_ENABLE_BIT)) 3609 retval = DDI_FAILURE; 3610 if (!bge_chip_enable_engine(bgep, FTQ_RESET_REG, 0)) 3611 retval = DDI_FAILURE; 3612 3613 /* 3614 * Steps 37-39: initialise Receive Buffer (Producer) RCBs 3615 */ 3616 bge_reg_putrcb(bgep, STD_RCV_BD_RING_RCB_REG, 3617 &bgep->buff[BGE_STD_BUFF_RING].hw_rcb); 3618 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3619 bge_reg_putrcb(bgep, JUMBO_RCV_BD_RING_RCB_REG, 3620 &bgep->buff[BGE_JUMBO_BUFF_RING].hw_rcb); 3621 bge_reg_putrcb(bgep, MINI_RCV_BD_RING_RCB_REG, 3622 &bgep->buff[BGE_MINI_BUFF_RING].hw_rcb); 3623 } 3624 3625 /* 3626 * Step 40: set Receive Buffer Descriptor Ring replenish thresholds 3627 */ 3628 bge_reg_put32(bgep, STD_RCV_BD_REPLENISH_REG, bge_replenish_std); 3629 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3630 bge_reg_put32(bgep, JUMBO_RCV_BD_REPLENISH_REG, 3631 bge_replenish_jumbo); 3632 bge_reg_put32(bgep, MINI_RCV_BD_REPLENISH_REG, 3633 bge_replenish_mini); 3634 } 3635 3636 /* 3637 * Steps 41-43: clear Send Ring Producer Indices and initialise 3638 * Send Producer Rings (0x0100-0x01ff in NIC-local memory) 3639 */ 3640 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3641 maxring = BGE_SEND_RINGS_MAX; 3642 else 3643 maxring = BGE_SEND_RINGS_MAX_5705; 3644 for (ring = 0; ring < maxring; ++ring) { 3645 bge_mbx_put(bgep, SEND_RING_HOST_INDEX_REG(ring), 0); 3646 bge_mbx_put(bgep, SEND_RING_NIC_INDEX_REG(ring), 0); 3647 bge_nic_putrcb(bgep, NIC_MEM_SEND_RING(ring), 3648 &bgep->send[ring].hw_rcb); 3649 } 3650 3651 /* 3652 * Steps 44-45: initialise Receive Return Rings 3653 * (0x0200-0x02ff in NIC-local memory) 3654 */ 3655 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3656 maxring = BGE_RECV_RINGS_MAX; 3657 else 3658 maxring = BGE_RECV_RINGS_MAX_5705; 3659 for (ring = 0; ring < maxring; ++ring) 3660 bge_nic_putrcb(bgep, NIC_MEM_RECV_RING(ring), 3661 &bgep->recv[ring].hw_rcb); 3662 3663 /* 3664 * Step 46: initialise Receive Buffer (Producer) Ring indexes 3665 */ 3666 bge_mbx_put(bgep, RECV_STD_PROD_INDEX_REG, 0); 3667 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3668 bge_mbx_put(bgep, RECV_JUMBO_PROD_INDEX_REG, 0); 3669 bge_mbx_put(bgep, RECV_MINI_PROD_INDEX_REG, 0); 3670 } 3671 /* 3672 * Step 47: configure the MAC unicast address 3673 * Step 48: configure the random backoff seed 3674 * Step 96: set up multicast filters 3675 */ 3676 #ifdef BGE_IPMI_ASF 3677 if (bge_chip_sync(bgep, B_FALSE) == DDI_FAILURE) 3678 #else 3679 if (bge_chip_sync(bgep) == DDI_FAILURE) 3680 #endif 3681 retval = DDI_FAILURE; 3682 3683 /* 3684 * Step 49: configure the MTU 3685 */ 3686 mtu = bgep->chipid.ethmax_size+ETHERFCSL+VLAN_TAGSZ; 3687 bge_reg_put32(bgep, MAC_RX_MTU_SIZE_REG, mtu); 3688 3689 /* 3690 * Step 50: configure the IPG et al 3691 */ 3692 bge_reg_put32(bgep, MAC_TX_LENGTHS_REG, MAC_TX_LENGTHS_DEFAULT); 3693 3694 /* 3695 * Step 51: configure the default Rx Return Ring 3696 */ 3697 bge_reg_put32(bgep, RCV_RULES_CONFIG_REG, RCV_RULES_CONFIG_DEFAULT); 3698 3699 /* 3700 * Steps 52-54: configure Receive List Placement, 3701 * and enable Receive List Placement Statistics 3702 */ 3703 bge_reg_put32(bgep, RCV_LP_CONFIG_REG, 3704 RCV_LP_CONFIG(bgep->chipid.rx_rings)); 3705 switch (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev)) { 3706 case MHCR_CHIP_ASIC_REV_5700: 3707 case MHCR_CHIP_ASIC_REV_5701: 3708 case MHCR_CHIP_ASIC_REV_5703: 3709 case MHCR_CHIP_ASIC_REV_5704: 3710 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, ~0); 3711 break; 3712 case MHCR_CHIP_ASIC_REV_5705: 3713 break; 3714 default: 3715 stats_mask = bge_reg_get32(bgep, RCV_LP_STATS_ENABLE_MASK_REG); 3716 stats_mask &= ~RCV_LP_STATS_DISABLE_MACTQ; 3717 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, stats_mask); 3718 break; 3719 } 3720 bge_reg_set32(bgep, RCV_LP_STATS_CONTROL_REG, RCV_LP_STATS_ENABLE); 3721 3722 if (bgep->chipid.rx_rings > 1) 3723 bge_init_recv_rule(bgep); 3724 3725 /* 3726 * Steps 55-56: enable Send Data Initiator Statistics 3727 */ 3728 bge_reg_put32(bgep, SEND_INIT_STATS_ENABLE_MASK_REG, ~0); 3729 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3730 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 3731 SEND_INIT_STATS_ENABLE | SEND_INIT_STATS_FASTER); 3732 } else { 3733 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 3734 SEND_INIT_STATS_ENABLE); 3735 } 3736 /* 3737 * Steps 57-58: stop (?) the Host Coalescing Engine 3738 */ 3739 if (!bge_chip_disable_engine(bgep, HOST_COALESCE_MODE_REG, ~0)) 3740 retval = DDI_FAILURE; 3741 3742 /* 3743 * Steps 59-62: initialise Host Coalescing parameters 3744 */ 3745 bge_reg_put32(bgep, SEND_COALESCE_MAX_BD_REG, bge_tx_count_norm); 3746 bge_reg_put32(bgep, SEND_COALESCE_TICKS_REG, bge_tx_ticks_norm); 3747 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, bge_rx_count_norm); 3748 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, bge_rx_ticks_norm); 3749 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3750 bge_reg_put32(bgep, SEND_COALESCE_INT_BD_REG, 3751 bge_tx_count_intr); 3752 bge_reg_put32(bgep, SEND_COALESCE_INT_TICKS_REG, 3753 bge_tx_ticks_intr); 3754 bge_reg_put32(bgep, RCV_COALESCE_INT_BD_REG, 3755 bge_rx_count_intr); 3756 bge_reg_put32(bgep, RCV_COALESCE_INT_TICKS_REG, 3757 bge_rx_ticks_intr); 3758 } 3759 3760 /* 3761 * Steps 63-64: initialise status block & statistics 3762 * host memory addresses 3763 * The statistic block does not exist in some chipsets 3764 * Step 65: initialise Statistics Coalescing Tick Counter 3765 */ 3766 bge_reg_put64(bgep, STATUS_BLOCK_HOST_ADDR_REG, 3767 bgep->status_block.cookie.dmac_laddress); 3768 3769 /* 3770 * Steps 66-67: initialise status block & statistics 3771 * NIC-local memory addresses 3772 */ 3773 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3774 bge_reg_put64(bgep, STATISTICS_HOST_ADDR_REG, 3775 bgep->statistics.cookie.dmac_laddress); 3776 bge_reg_put32(bgep, STATISTICS_TICKS_REG, 3777 STATISTICS_TICKS_DEFAULT); 3778 bge_reg_put32(bgep, STATUS_BLOCK_BASE_ADDR_REG, 3779 NIC_MEM_STATUS_BLOCK); 3780 bge_reg_put32(bgep, STATISTICS_BASE_ADDR_REG, 3781 NIC_MEM_STATISTICS); 3782 } 3783 3784 /* 3785 * Steps 68-71: start the Host Coalescing Engine, the Receive BD 3786 * Completion Engine, the Receive List Placement Engine, and the 3787 * Receive List selector.Pay attention:0x3400 is not exist in BCM5714 3788 * and BCM5715. 3789 */ 3790 if (bgep->chipid.tx_rings <= COALESCE_64_BYTE_RINGS && 3791 bgep->chipid.rx_rings <= COALESCE_64_BYTE_RINGS) 3792 coalmode = COALESCE_64_BYTE_STATUS; 3793 else 3794 coalmode = 0; 3795 if (!bge_chip_enable_engine(bgep, HOST_COALESCE_MODE_REG, coalmode)) 3796 retval = DDI_FAILURE; 3797 if (!bge_chip_enable_engine(bgep, RCV_BD_COMPLETION_MODE_REG, 3798 STATE_MACHINE_ATTN_ENABLE_BIT)) 3799 retval = DDI_FAILURE; 3800 if (!bge_chip_enable_engine(bgep, RCV_LIST_PLACEMENT_MODE_REG, 0)) 3801 retval = DDI_FAILURE; 3802 3803 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3804 if (!bge_chip_enable_engine(bgep, RCV_LIST_SELECTOR_MODE_REG, 3805 STATE_MACHINE_ATTN_ENABLE_BIT)) 3806 retval = DDI_FAILURE; 3807 3808 /* 3809 * Step 72: Enable MAC DMA engines 3810 * Step 73: Clear & enable MAC statistics 3811 */ 3812 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 3813 ETHERNET_MODE_ENABLE_FHDE | 3814 ETHERNET_MODE_ENABLE_RDE | 3815 ETHERNET_MODE_ENABLE_TDE); 3816 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 3817 ETHERNET_MODE_ENABLE_TX_STATS | 3818 ETHERNET_MODE_ENABLE_RX_STATS | 3819 ETHERNET_MODE_CLEAR_TX_STATS | 3820 ETHERNET_MODE_CLEAR_RX_STATS); 3821 3822 /* 3823 * Step 74: configure the MLCR (Miscellaneous Local Control 3824 * Register); not required, as we set up the MLCR in step 10 3825 * (part of the reset code) above. 3826 * 3827 * Step 75: clear Interrupt Mailbox 0 3828 */ 3829 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 0); 3830 3831 /* 3832 * Steps 76-87: Gentlemen, start your engines ... 3833 * 3834 * Enable the DMA Completion Engine, the Write DMA Engine, 3835 * the Read DMA Engine, Receive Data Completion Engine, 3836 * the MBuf Cluster Free Engine, the Send Data Completion Engine, 3837 * the Send BD Completion Engine, the Receive BD Initiator Engine, 3838 * the Receive Data Initiator Engine, the Send Data Initiator Engine, 3839 * the Send BD Initiator Engine, and the Send BD Selector Engine. 3840 * 3841 * Beware exhaust fumes? 3842 */ 3843 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3844 if (!bge_chip_enable_engine(bgep, DMA_COMPLETION_MODE_REG, 0)) 3845 retval = DDI_FAILURE; 3846 dma_wrprio = (bge_dma_wrprio << DMA_PRIORITY_SHIFT) | 3847 ALL_DMA_ATTN_BITS; 3848 if ((MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) == 3849 MHCR_CHIP_ASIC_REV_5755) || 3850 (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) == 3851 MHCR_CHIP_ASIC_REV_5906)) { 3852 dma_wrprio |= DMA_STATUS_TAG_FIX_CQ12384; 3853 } 3854 if (!bge_chip_enable_engine(bgep, WRITE_DMA_MODE_REG, 3855 dma_wrprio)) 3856 retval = DDI_FAILURE; 3857 if (!bge_chip_enable_engine(bgep, READ_DMA_MODE_REG, 3858 (bge_dma_rdprio << DMA_PRIORITY_SHIFT) | ALL_DMA_ATTN_BITS)) 3859 retval = DDI_FAILURE; 3860 if (!bge_chip_enable_engine(bgep, RCV_DATA_COMPLETION_MODE_REG, 3861 STATE_MACHINE_ATTN_ENABLE_BIT)) 3862 retval = DDI_FAILURE; 3863 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3864 if (!bge_chip_enable_engine(bgep, 3865 MBUF_CLUSTER_FREE_MODE_REG, 0)) 3866 retval = DDI_FAILURE; 3867 if (!bge_chip_enable_engine(bgep, SEND_DATA_COMPLETION_MODE_REG, 0)) 3868 retval = DDI_FAILURE; 3869 if (!bge_chip_enable_engine(bgep, SEND_BD_COMPLETION_MODE_REG, 3870 STATE_MACHINE_ATTN_ENABLE_BIT)) 3871 retval = DDI_FAILURE; 3872 if (!bge_chip_enable_engine(bgep, RCV_BD_INITIATOR_MODE_REG, 3873 RCV_BD_DISABLED_RING_ATTN)) 3874 retval = DDI_FAILURE; 3875 if (!bge_chip_enable_engine(bgep, RCV_DATA_BD_INITIATOR_MODE_REG, 3876 RCV_DATA_BD_ILL_RING_ATTN)) 3877 retval = DDI_FAILURE; 3878 if (!bge_chip_enable_engine(bgep, SEND_DATA_INITIATOR_MODE_REG, 0)) 3879 retval = DDI_FAILURE; 3880 if (!bge_chip_enable_engine(bgep, SEND_BD_INITIATOR_MODE_REG, 3881 STATE_MACHINE_ATTN_ENABLE_BIT)) 3882 retval = DDI_FAILURE; 3883 if (!bge_chip_enable_engine(bgep, SEND_BD_SELECTOR_MODE_REG, 3884 STATE_MACHINE_ATTN_ENABLE_BIT)) 3885 retval = DDI_FAILURE; 3886 3887 /* 3888 * Step 88: download firmware -- doesn't apply 3889 * Steps 89-90: enable Transmit & Receive MAC Engines 3890 */ 3891 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 3892 retval = DDI_FAILURE; 3893 #ifdef BGE_IPMI_ASF 3894 if (!bgep->asf_enabled) { 3895 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 3896 RECEIVE_MODE_KEEP_VLAN_TAG)) 3897 retval = DDI_FAILURE; 3898 } else { 3899 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 0)) 3900 retval = DDI_FAILURE; 3901 } 3902 #else 3903 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 3904 RECEIVE_MODE_KEEP_VLAN_TAG)) 3905 retval = DDI_FAILURE; 3906 #endif 3907 3908 /* 3909 * Step 91: disable auto-polling of PHY status 3910 */ 3911 bge_reg_put32(bgep, MI_MODE_REG, MI_MODE_DEFAULT); 3912 3913 /* 3914 * Step 92: configure D0 power state (not required) 3915 * Step 93: initialise LED control register () 3916 */ 3917 ledctl = LED_CONTROL_DEFAULT; 3918 switch (bgep->chipid.device) { 3919 case DEVICE_ID_5700: 3920 case DEVICE_ID_5700x: 3921 case DEVICE_ID_5701: 3922 /* 3923 * Switch to 5700 (MAC) mode on these older chips 3924 */ 3925 ledctl &= ~LED_CONTROL_LED_MODE_MASK; 3926 ledctl |= LED_CONTROL_LED_MODE_5700; 3927 break; 3928 3929 default: 3930 break; 3931 } 3932 bge_reg_put32(bgep, ETHERNET_MAC_LED_CONTROL_REG, ledctl); 3933 3934 /* 3935 * Step 94: activate link 3936 */ 3937 bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK); 3938 3939 /* 3940 * Step 95: set up physical layer (PHY/SerDes) 3941 * restart autoneg (if required) 3942 */ 3943 if (reset_phys) 3944 if (bge_phys_update(bgep) == DDI_FAILURE) 3945 retval = DDI_FAILURE; 3946 3947 /* 3948 * Extra step (DSG): hand over all the Receive Buffers to the chip 3949 */ 3950 for (ring = 0; ring < BGE_BUFF_RINGS_USED; ++ring) 3951 bge_mbx_put(bgep, bgep->buff[ring].chip_mbx_reg, 3952 bgep->buff[ring].rf_next); 3953 3954 /* 3955 * MSI bits:The least significant MSI 16-bit word. 3956 * ISR will be triggered different. 3957 */ 3958 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 3959 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 0x70); 3960 3961 /* 3962 * Extra step (DSG): select which interrupts are enabled 3963 * 3964 * Program the Ethernet MAC engine to signal attention on 3965 * Link Change events, then enable interrupts on MAC, DMA, 3966 * and FLOW attention signals. 3967 */ 3968 bge_reg_set32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 3969 ETHERNET_EVENT_LINK_INT | 3970 ETHERNET_STATUS_PCS_ERROR_INT); 3971 #ifdef BGE_IPMI_ASF 3972 if (bgep->asf_enabled) { 3973 bge_reg_set32(bgep, MODE_CONTROL_REG, 3974 MODE_INT_ON_FLOW_ATTN | 3975 MODE_INT_ON_DMA_ATTN | 3976 MODE_HOST_STACK_UP| 3977 MODE_INT_ON_MAC_ATTN); 3978 } else { 3979 #endif 3980 bge_reg_set32(bgep, MODE_CONTROL_REG, 3981 MODE_INT_ON_FLOW_ATTN | 3982 MODE_INT_ON_DMA_ATTN | 3983 MODE_INT_ON_MAC_ATTN); 3984 #ifdef BGE_IPMI_ASF 3985 } 3986 #endif 3987 3988 /* 3989 * Step 97: enable PCI interrupts!!! 3990 */ 3991 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 3992 bge_cfg_clr32(bgep, PCI_CONF_BGE_MHCR, 3993 MHCR_MASK_PCI_INT_OUTPUT); 3994 3995 /* 3996 * All done! 3997 */ 3998 bgep->bge_chip_state = BGE_CHIP_RUNNING; 3999 return (retval); 4000 } 4001 4002 4003 /* 4004 * ========== Hardware interrupt handler ========== 4005 */ 4006 4007 #undef BGE_DBG 4008 #define BGE_DBG BGE_DBG_INT /* debug flag for this code */ 4009 4010 /* 4011 * Sync the status block, then atomically clear the specified bits in 4012 * the <flags-and-tag> field of the status block. 4013 * the <flags> word of the status block, returning the value of the 4014 * <tag> and the <flags> before the bits were cleared. 4015 */ 4016 static int bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags); 4017 #pragma inline(bge_status_sync) 4018 4019 static int 4020 bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags) 4021 { 4022 bge_status_t *bsp; 4023 int retval; 4024 4025 BGE_TRACE(("bge_status_sync($%p, 0x%llx)", 4026 (void *)bgep, bits)); 4027 4028 ASSERT(bgep->bge_guard == BGE_GUARD); 4029 4030 DMA_SYNC(bgep->status_block, DDI_DMA_SYNC_FORKERNEL); 4031 retval = bge_check_dma_handle(bgep, bgep->status_block.dma_hdl); 4032 if (retval != DDI_FM_OK) 4033 return (retval); 4034 4035 bsp = DMA_VPTR(bgep->status_block); 4036 *flags = bge_atomic_clr64(&bsp->flags_n_tag, bits); 4037 4038 BGE_DEBUG(("bge_status_sync($%p, 0x%llx) returning 0x%llx", 4039 (void *)bgep, bits, *flags)); 4040 4041 return (retval); 4042 } 4043 4044 void bge_wake_factotum(bge_t *bgep); 4045 #pragma inline(bge_wake_factotum) 4046 4047 void 4048 bge_wake_factotum(bge_t *bgep) 4049 { 4050 mutex_enter(bgep->softintrlock); 4051 if (bgep->factotum_flag == 0) { 4052 bgep->factotum_flag = 1; 4053 ddi_trigger_softintr(bgep->factotum_id); 4054 } 4055 mutex_exit(bgep->softintrlock); 4056 } 4057 4058 /* 4059 * bge_intr() -- handle chip interrupts 4060 */ 4061 uint_t bge_intr(caddr_t arg1, caddr_t arg2); 4062 #pragma no_inline(bge_intr) 4063 4064 uint_t 4065 bge_intr(caddr_t arg1, caddr_t arg2) 4066 { 4067 bge_t *bgep = (void *)arg1; /* private device info */ 4068 bge_status_t *bsp; 4069 uint64_t flags; 4070 uint32_t regval; 4071 uint_t result; 4072 int retval, loop_cnt = 0; 4073 4074 BGE_TRACE(("bge_intr($%p) ($%p)", arg1, arg2)); 4075 4076 /* 4077 * GLD v2 checks that s/w setup is complete before passing 4078 * interrupts to this routine, thus eliminating the old 4079 * (and well-known) race condition around ddi_add_intr() 4080 */ 4081 ASSERT(bgep->progress & PROGRESS_HWINT); 4082 4083 result = DDI_INTR_UNCLAIMED; 4084 mutex_enter(bgep->genlock); 4085 4086 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) { 4087 /* 4088 * Check whether chip's says it's asserting #INTA; 4089 * if not, don't process or claim the interrupt. 4090 * 4091 * Note that the PCI signal is active low, so the 4092 * bit is *zero* when the interrupt is asserted. 4093 */ 4094 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 4095 if (regval & MLCR_INTA_STATE) { 4096 if (bge_check_acc_handle(bgep, bgep->io_handle) 4097 != DDI_FM_OK) 4098 goto chip_stop; 4099 mutex_exit(bgep->genlock); 4100 return (result); 4101 } 4102 4103 /* 4104 * Block further PCI interrupts ... 4105 */ 4106 bge_reg_set32(bgep, PCI_CONF_BGE_MHCR, 4107 MHCR_MASK_PCI_INT_OUTPUT); 4108 4109 } else { 4110 /* 4111 * Check MSI status 4112 */ 4113 regval = bge_reg_get32(bgep, MSI_STATUS_REG); 4114 if (regval & MSI_ERROR_ATTENTION) { 4115 BGE_REPORT((bgep, "msi error attention," 4116 " status=0x%x", regval)); 4117 bge_reg_put32(bgep, MSI_STATUS_REG, regval); 4118 } 4119 } 4120 4121 result = DDI_INTR_CLAIMED; 4122 4123 BGE_DEBUG(("bge_intr($%p) ($%p) regval 0x%08x", arg1, arg2, regval)); 4124 4125 /* 4126 * Sync the status block and grab the flags-n-tag from it. 4127 * We count the number of interrupts where there doesn't 4128 * seem to have been a DMA update of the status block; if 4129 * it *has* been updated, the counter will be cleared in 4130 * the while() loop below ... 4131 */ 4132 bgep->missed_dmas += 1; 4133 bsp = DMA_VPTR(bgep->status_block); 4134 for (loop_cnt = 0; loop_cnt < bge_intr_max_loop; loop_cnt++) { 4135 if (bgep->bge_chip_state != BGE_CHIP_RUNNING) { 4136 /* 4137 * bge_chip_stop() may have freed dma area etc 4138 * while we were in this interrupt handler - 4139 * better not call bge_status_sync() 4140 */ 4141 (void) bge_check_acc_handle(bgep, 4142 bgep->io_handle); 4143 mutex_exit(bgep->genlock); 4144 return (DDI_INTR_CLAIMED); 4145 } 4146 retval = bge_status_sync(bgep, STATUS_FLAG_UPDATED, 4147 &flags); 4148 if (retval != DDI_FM_OK) { 4149 bgep->bge_dma_error = B_TRUE; 4150 goto chip_stop; 4151 } 4152 4153 if (!(flags & STATUS_FLAG_UPDATED)) 4154 break; 4155 4156 /* 4157 * Tell the chip that we're processing the interrupt 4158 */ 4159 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 4160 INTERRUPT_MBOX_DISABLE(flags)); 4161 if (bge_check_acc_handle(bgep, bgep->io_handle) != 4162 DDI_FM_OK) 4163 goto chip_stop; 4164 4165 /* 4166 * Drop the mutex while we: 4167 * Receive any newly-arrived packets 4168 * Recycle any newly-finished send buffers 4169 */ 4170 bgep->bge_intr_running = B_TRUE; 4171 mutex_exit(bgep->genlock); 4172 bge_receive(bgep, bsp); 4173 bge_recycle(bgep, bsp); 4174 mutex_enter(bgep->genlock); 4175 bgep->bge_intr_running = B_FALSE; 4176 4177 /* 4178 * Tell the chip we've finished processing, and 4179 * give it the tag that we got from the status 4180 * block earlier, so that it knows just how far 4181 * we've gone. If it's got more for us to do, 4182 * it will now update the status block and try 4183 * to assert an interrupt (but we've got the 4184 * #INTA blocked at present). If we see the 4185 * update, we'll loop around to do some more. 4186 * Eventually we'll get out of here ... 4187 */ 4188 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 4189 INTERRUPT_MBOX_ENABLE(flags)); 4190 if (bgep->chipid.pci_type == BGE_PCI_E) 4191 (void) bge_mbx_get(bgep, INTERRUPT_MBOX_0_REG); 4192 bgep->missed_dmas = 0; 4193 } 4194 4195 /* 4196 * Check for exceptional conditions that we need to handle 4197 * 4198 * Link status changed 4199 * Status block not updated 4200 */ 4201 if (flags & STATUS_FLAG_LINK_CHANGED) 4202 bge_wake_factotum(bgep); 4203 4204 if (bgep->missed_dmas) { 4205 /* 4206 * Probably due to the internal status tag not 4207 * being reset. Force a status block update now; 4208 * this should ensure that we get an update and 4209 * a new interrupt. After that, we should be in 4210 * sync again ... 4211 */ 4212 BGE_REPORT((bgep, "interrupt: flags 0x%llx - " 4213 "not updated?", flags)); 4214 bgep->missed_updates++; 4215 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 4216 COALESCE_NOW); 4217 4218 if (bgep->missed_dmas >= bge_dma_miss_limit) { 4219 /* 4220 * If this happens multiple times in a row, 4221 * it means DMA is just not working. Maybe 4222 * the chip's failed, or maybe there's a 4223 * problem on the PCI bus or in the host-PCI 4224 * bridge (Tomatillo). 4225 * 4226 * At all events, we want to stop further 4227 * interrupts and let the recovery code take 4228 * over to see whether anything can be done 4229 * about it ... 4230 */ 4231 bge_fm_ereport(bgep, 4232 DDI_FM_DEVICE_BADINT_LIMIT); 4233 goto chip_stop; 4234 } 4235 } 4236 4237 /* 4238 * Reenable assertion of #INTA, unless there's a DMA fault 4239 */ 4240 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) { 4241 bge_reg_clr32(bgep, PCI_CONF_BGE_MHCR, 4242 MHCR_MASK_PCI_INT_OUTPUT); 4243 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != 4244 DDI_FM_OK) 4245 goto chip_stop; 4246 } 4247 4248 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4249 goto chip_stop; 4250 4251 mutex_exit(bgep->genlock); 4252 return (result); 4253 4254 chip_stop: 4255 #ifdef BGE_IPMI_ASF 4256 if (bgep->asf_enabled && bgep->asf_status == ASF_STAT_RUN) { 4257 /* 4258 * We must stop ASF heart beat before 4259 * bge_chip_stop(), otherwise some 4260 * computers (ex. IBM HS20 blade 4261 * server) may crash. 4262 */ 4263 bge_asf_update_status(bgep); 4264 bge_asf_stop_timer(bgep); 4265 bgep->asf_status = ASF_STAT_STOP; 4266 4267 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 4268 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 4269 } 4270 #endif 4271 bge_chip_stop(bgep, B_TRUE); 4272 (void) bge_check_acc_handle(bgep, bgep->io_handle); 4273 mutex_exit(bgep->genlock); 4274 return (result); 4275 } 4276 4277 /* 4278 * ========== Factotum, implemented as a softint handler ========== 4279 */ 4280 4281 #undef BGE_DBG 4282 #define BGE_DBG BGE_DBG_FACT /* debug flag for this code */ 4283 4284 static void bge_factotum_error_handler(bge_t *bgep); 4285 #pragma no_inline(bge_factotum_error_handler) 4286 4287 static void 4288 bge_factotum_error_handler(bge_t *bgep) 4289 { 4290 uint32_t flow; 4291 uint32_t rdma; 4292 uint32_t wdma; 4293 uint32_t tmac; 4294 uint32_t rmac; 4295 uint32_t rxrs; 4296 uint32_t txrs = 0; 4297 4298 ASSERT(mutex_owned(bgep->genlock)); 4299 4300 /* 4301 * Read all the registers that show the possible 4302 * reasons for the ERROR bit to be asserted 4303 */ 4304 flow = bge_reg_get32(bgep, FLOW_ATTN_REG); 4305 rdma = bge_reg_get32(bgep, READ_DMA_STATUS_REG); 4306 wdma = bge_reg_get32(bgep, WRITE_DMA_STATUS_REG); 4307 tmac = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 4308 rmac = bge_reg_get32(bgep, RECEIVE_MAC_STATUS_REG); 4309 rxrs = bge_reg_get32(bgep, RX_RISC_STATE_REG); 4310 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4311 txrs = bge_reg_get32(bgep, TX_RISC_STATE_REG); 4312 4313 BGE_DEBUG(("factotum($%p) flow 0x%x rdma 0x%x wdma 0x%x", 4314 (void *)bgep, flow, rdma, wdma)); 4315 BGE_DEBUG(("factotum($%p) tmac 0x%x rmac 0x%x rxrs 0x%08x txrs 0x%08x", 4316 (void *)bgep, tmac, rmac, rxrs, txrs)); 4317 4318 /* 4319 * For now, just clear all the errors ... 4320 */ 4321 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4322 bge_reg_put32(bgep, TX_RISC_STATE_REG, ~0); 4323 bge_reg_put32(bgep, RX_RISC_STATE_REG, ~0); 4324 bge_reg_put32(bgep, RECEIVE_MAC_STATUS_REG, ~0); 4325 bge_reg_put32(bgep, WRITE_DMA_STATUS_REG, ~0); 4326 bge_reg_put32(bgep, READ_DMA_STATUS_REG, ~0); 4327 bge_reg_put32(bgep, FLOW_ATTN_REG, ~0); 4328 } 4329 4330 /* 4331 * Handler for hardware link state change. 4332 * 4333 * When this routine is called, the hardware link state has changed 4334 * and the new state is reflected in the param_* variables. Here 4335 * we must update the softstate and reprogram the MAC to match. 4336 */ 4337 static void bge_factotum_link_handler(bge_t *bgep); 4338 #pragma no_inline(bge_factotum_link_handler) 4339 4340 static void 4341 bge_factotum_link_handler(bge_t *bgep) 4342 { 4343 ASSERT(mutex_owned(bgep->genlock)); 4344 4345 /* 4346 * Update the s/w link_state 4347 */ 4348 if (bgep->param_link_up) 4349 bgep->link_state = LINK_STATE_UP; 4350 else 4351 bgep->link_state = LINK_STATE_DOWN; 4352 4353 /* 4354 * Reprogram the MAC modes to match 4355 */ 4356 bge_sync_mac_modes(bgep); 4357 } 4358 4359 static boolean_t bge_factotum_link_check(bge_t *bgep, int *dma_state); 4360 #pragma no_inline(bge_factotum_link_check) 4361 4362 static boolean_t 4363 bge_factotum_link_check(bge_t *bgep, int *dma_state) 4364 { 4365 boolean_t check; 4366 uint64_t flags; 4367 uint32_t tmac_status; 4368 4369 ASSERT(mutex_owned(bgep->genlock)); 4370 4371 /* 4372 * Get & clear the writable status bits in the Tx status register 4373 * (some bits are write-1-to-clear, others are just readonly). 4374 */ 4375 tmac_status = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 4376 bge_reg_put32(bgep, TRANSMIT_MAC_STATUS_REG, tmac_status); 4377 4378 /* 4379 * Get & clear the ERROR and LINK_CHANGED bits from the status block 4380 */ 4381 *dma_state = bge_status_sync(bgep, STATUS_FLAG_ERROR | 4382 STATUS_FLAG_LINK_CHANGED, &flags); 4383 if (*dma_state != DDI_FM_OK) 4384 return (B_FALSE); 4385 4386 /* 4387 * Clear any errors flagged in the status block ... 4388 */ 4389 if (flags & STATUS_FLAG_ERROR) 4390 bge_factotum_error_handler(bgep); 4391 4392 /* 4393 * We need to check the link status if: 4394 * the status block says there's been a link change 4395 * or there's any discrepancy between the various 4396 * flags indicating the link state (link_state, 4397 * param_link_up, and the LINK STATE bit in the 4398 * Transmit MAC status register). 4399 */ 4400 check = (flags & STATUS_FLAG_LINK_CHANGED) != 0; 4401 switch (bgep->link_state) { 4402 case LINK_STATE_UP: 4403 check |= (bgep->param_link_up == B_FALSE); 4404 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) == 0); 4405 break; 4406 4407 case LINK_STATE_DOWN: 4408 check |= (bgep->param_link_up != B_FALSE); 4409 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) != 0); 4410 break; 4411 4412 default: 4413 check = B_TRUE; 4414 break; 4415 } 4416 4417 /* 4418 * If <check> is false, we're sure the link hasn't changed. 4419 * If true, however, it's not yet definitive; we have to call 4420 * bge_phys_check() to determine whether the link has settled 4421 * into a new state yet ... and if it has, then call the link 4422 * state change handler.But when the chip is 5700 in Dell 6650 4423 * ,even if check is false, the link may have changed.So we 4424 * have to call bge_phys_check() to determine the link state. 4425 */ 4426 if (check || bgep->chipid.device == DEVICE_ID_5700) { 4427 check = bge_phys_check(bgep); 4428 if (check) 4429 bge_factotum_link_handler(bgep); 4430 } 4431 4432 return (check); 4433 } 4434 4435 /* 4436 * Factotum routine to check for Tx stall, using the 'watchdog' counter 4437 */ 4438 static boolean_t bge_factotum_stall_check(bge_t *bgep); 4439 #pragma no_inline(bge_factotum_stall_check) 4440 4441 static boolean_t 4442 bge_factotum_stall_check(bge_t *bgep) 4443 { 4444 uint32_t dogval; 4445 4446 ASSERT(mutex_owned(bgep->genlock)); 4447 4448 /* 4449 * Specific check for Tx stall ... 4450 * 4451 * The 'watchdog' counter is incremented whenever a packet 4452 * is queued, reset to 1 when some (but not all) buffers 4453 * are reclaimed, reset to 0 (disabled) when all buffers 4454 * are reclaimed, and shifted left here. If it exceeds the 4455 * threshold value, the chip is assumed to have stalled and 4456 * is put into the ERROR state. The factotum will then reset 4457 * it on the next pass. 4458 * 4459 * All of which should ensure that we don't get into a state 4460 * where packets are left pending indefinitely! 4461 */ 4462 dogval = bge_atomic_shl32(&bgep->watchdog, 1); 4463 if (dogval < bge_watchdog_count) 4464 return (B_FALSE); 4465 4466 #if !defined(BGE_NETCONSOLE) 4467 BGE_REPORT((bgep, "Tx stall detected, watchdog code 0x%x", dogval)); 4468 #endif 4469 bge_fm_ereport(bgep, DDI_FM_DEVICE_STALL); 4470 return (B_TRUE); 4471 } 4472 4473 /* 4474 * The factotum is woken up when there's something to do that we'd rather 4475 * not do from inside a hardware interrupt handler or high-level cyclic. 4476 * Its two main tasks are: 4477 * reset & restart the chip after an error 4478 * check the link status whenever necessary 4479 */ 4480 uint_t bge_chip_factotum(caddr_t arg); 4481 #pragma no_inline(bge_chip_factotum) 4482 4483 uint_t 4484 bge_chip_factotum(caddr_t arg) 4485 { 4486 bge_t *bgep; 4487 uint_t result; 4488 boolean_t error; 4489 boolean_t linkchg; 4490 int dma_state; 4491 4492 bgep = (void *)arg; 4493 4494 BGE_TRACE(("bge_chip_factotum($%p)", (void *)bgep)); 4495 4496 mutex_enter(bgep->softintrlock); 4497 if (bgep->factotum_flag == 0) { 4498 mutex_exit(bgep->softintrlock); 4499 return (DDI_INTR_UNCLAIMED); 4500 } 4501 bgep->factotum_flag = 0; 4502 mutex_exit(bgep->softintrlock); 4503 4504 result = DDI_INTR_CLAIMED; 4505 error = B_FALSE; 4506 linkchg = B_FALSE; 4507 4508 mutex_enter(bgep->genlock); 4509 switch (bgep->bge_chip_state) { 4510 default: 4511 break; 4512 4513 case BGE_CHIP_RUNNING: 4514 linkchg = bge_factotum_link_check(bgep, &dma_state); 4515 error = bge_factotum_stall_check(bgep); 4516 if (dma_state != DDI_FM_OK) { 4517 bgep->bge_dma_error = B_TRUE; 4518 error = B_TRUE; 4519 } 4520 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4521 error = B_TRUE; 4522 if (error) 4523 bgep->bge_chip_state = BGE_CHIP_ERROR; 4524 break; 4525 4526 case BGE_CHIP_ERROR: 4527 error = B_TRUE; 4528 break; 4529 4530 case BGE_CHIP_FAULT: 4531 /* 4532 * Fault detected, time to reset ... 4533 */ 4534 if (bge_autorecover) { 4535 if (!(bgep->progress & PROGRESS_BUFS)) { 4536 /* 4537 * if we can't allocate the ring buffers, 4538 * try later 4539 */ 4540 if (bge_alloc_bufs(bgep) != DDI_SUCCESS) { 4541 mutex_exit(bgep->genlock); 4542 return (result); 4543 } 4544 bgep->progress |= PROGRESS_BUFS; 4545 } 4546 if (!(bgep->progress & PROGRESS_INTR)) { 4547 bge_init_rings(bgep); 4548 bge_intr_enable(bgep); 4549 bgep->progress |= PROGRESS_INTR; 4550 } 4551 if (!(bgep->progress & PROGRESS_KSTATS)) { 4552 bge_init_kstats(bgep, 4553 ddi_get_instance(bgep->devinfo)); 4554 bgep->progress |= PROGRESS_KSTATS; 4555 } 4556 4557 BGE_REPORT((bgep, "automatic recovery activated")); 4558 4559 if (bge_restart(bgep, B_FALSE) != DDI_SUCCESS) { 4560 bgep->bge_chip_state = BGE_CHIP_ERROR; 4561 error = B_TRUE; 4562 } 4563 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != 4564 DDI_FM_OK) { 4565 bgep->bge_chip_state = BGE_CHIP_ERROR; 4566 error = B_TRUE; 4567 } 4568 if (bge_check_acc_handle(bgep, bgep->io_handle) != 4569 DDI_FM_OK) { 4570 bgep->bge_chip_state = BGE_CHIP_ERROR; 4571 error = B_TRUE; 4572 } 4573 if (error == B_FALSE) { 4574 #ifdef BGE_IPMI_ASF 4575 if (bgep->asf_enabled && 4576 bgep->asf_status != ASF_STAT_RUN) { 4577 bgep->asf_timeout_id = timeout( 4578 bge_asf_heartbeat, (void *)bgep, 4579 drv_usectohz( 4580 BGE_ASF_HEARTBEAT_INTERVAL)); 4581 bgep->asf_status = ASF_STAT_RUN; 4582 } 4583 #endif 4584 if (!bgep->manual_reset) { 4585 ddi_fm_service_impact(bgep->devinfo, 4586 DDI_SERVICE_RESTORED); 4587 } 4588 } 4589 } 4590 break; 4591 } 4592 4593 4594 /* 4595 * If an error is detected, stop the chip now, marking it as 4596 * faulty, so that it will be reset next time through ... 4597 * 4598 * Note that if intr_running is set, then bge_intr() has dropped 4599 * genlock to call bge_receive/bge_recycle. Can't stop the chip at 4600 * this point so have to wait until the next time the factotum runs. 4601 */ 4602 if (error && !bgep->bge_intr_running) { 4603 #ifdef BGE_IPMI_ASF 4604 if (bgep->asf_enabled && (bgep->asf_status == ASF_STAT_RUN)) { 4605 /* 4606 * We must stop ASF heart beat before bge_chip_stop(), 4607 * otherwise some computers (ex. IBM HS20 blade server) 4608 * may crash. 4609 */ 4610 bge_asf_update_status(bgep); 4611 bge_asf_stop_timer(bgep); 4612 bgep->asf_status = ASF_STAT_STOP; 4613 4614 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 4615 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 4616 } 4617 #endif 4618 bge_chip_stop(bgep, B_TRUE); 4619 (void) bge_check_acc_handle(bgep, bgep->io_handle); 4620 } 4621 mutex_exit(bgep->genlock); 4622 4623 /* 4624 * If the link state changed, tell the world about it. 4625 * Note: can't do this while still holding the mutex. 4626 */ 4627 if (bgep->link_update_timer == BGE_LINK_UPDATE_TIMEOUT && 4628 bgep->link_state != LINK_STATE_UNKNOWN) 4629 linkchg = B_TRUE; 4630 else if (bgep->link_update_timer < BGE_LINK_UPDATE_TIMEOUT && 4631 bgep->link_state == LINK_STATE_DOWN) 4632 linkchg = B_FALSE; 4633 4634 if (linkchg) { 4635 mac_link_update(bgep->mh, bgep->link_state); 4636 bgep->link_update_timer = BGE_LINK_UPDATE_DONE; 4637 } 4638 if (bgep->manual_reset) { 4639 bgep->manual_reset = B_FALSE; 4640 } 4641 4642 return (result); 4643 } 4644 4645 /* 4646 * High-level cyclic handler 4647 * 4648 * This routine schedules a (low-level) softint callback to the 4649 * factotum, and prods the chip to update the status block (which 4650 * will cause a hardware interrupt when complete). 4651 */ 4652 void bge_chip_cyclic(void *arg); 4653 #pragma no_inline(bge_chip_cyclic) 4654 4655 void 4656 bge_chip_cyclic(void *arg) 4657 { 4658 bge_t *bgep; 4659 4660 bgep = arg; 4661 4662 switch (bgep->bge_chip_state) { 4663 default: 4664 return; 4665 4666 case BGE_CHIP_RUNNING: 4667 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, COALESCE_NOW); 4668 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4669 ddi_fm_service_impact(bgep->devinfo, 4670 DDI_SERVICE_UNAFFECTED); 4671 4672 if (bgep->link_update_timer < BGE_LINK_UPDATE_TIMEOUT) 4673 bgep->link_update_timer++; 4674 4675 break; 4676 4677 case BGE_CHIP_FAULT: 4678 case BGE_CHIP_ERROR: 4679 break; 4680 } 4681 4682 bge_wake_factotum(bgep); 4683 } 4684 4685 4686 /* 4687 * ========== Ioctl subfunctions ========== 4688 */ 4689 4690 #undef BGE_DBG 4691 #define BGE_DBG BGE_DBG_PPIO /* debug flag for this code */ 4692 4693 #if BGE_DEBUGGING || BGE_DO_PPIO 4694 4695 static void bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 4696 #pragma no_inline(bge_chip_peek_cfg) 4697 4698 static void 4699 bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 4700 { 4701 uint64_t regval; 4702 uint64_t regno; 4703 4704 BGE_TRACE(("bge_chip_peek_cfg($%p, $%p)", 4705 (void *)bgep, (void *)ppd)); 4706 4707 regno = ppd->pp_acc_offset; 4708 4709 switch (ppd->pp_acc_size) { 4710 case 1: 4711 regval = pci_config_get8(bgep->cfg_handle, regno); 4712 break; 4713 4714 case 2: 4715 regval = pci_config_get16(bgep->cfg_handle, regno); 4716 break; 4717 4718 case 4: 4719 regval = pci_config_get32(bgep->cfg_handle, regno); 4720 break; 4721 4722 case 8: 4723 regval = pci_config_get64(bgep->cfg_handle, regno); 4724 break; 4725 } 4726 4727 ppd->pp_acc_data = regval; 4728 } 4729 4730 static void bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 4731 #pragma no_inline(bge_chip_poke_cfg) 4732 4733 static void 4734 bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 4735 { 4736 uint64_t regval; 4737 uint64_t regno; 4738 4739 BGE_TRACE(("bge_chip_poke_cfg($%p, $%p)", 4740 (void *)bgep, (void *)ppd)); 4741 4742 regno = ppd->pp_acc_offset; 4743 regval = ppd->pp_acc_data; 4744 4745 switch (ppd->pp_acc_size) { 4746 case 1: 4747 pci_config_put8(bgep->cfg_handle, regno, regval); 4748 break; 4749 4750 case 2: 4751 pci_config_put16(bgep->cfg_handle, regno, regval); 4752 break; 4753 4754 case 4: 4755 pci_config_put32(bgep->cfg_handle, regno, regval); 4756 break; 4757 4758 case 8: 4759 pci_config_put64(bgep->cfg_handle, regno, regval); 4760 break; 4761 } 4762 } 4763 4764 static void bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd); 4765 #pragma no_inline(bge_chip_peek_reg) 4766 4767 static void 4768 bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd) 4769 { 4770 uint64_t regval; 4771 void *regaddr; 4772 4773 BGE_TRACE(("bge_chip_peek_reg($%p, $%p)", 4774 (void *)bgep, (void *)ppd)); 4775 4776 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 4777 4778 switch (ppd->pp_acc_size) { 4779 case 1: 4780 regval = ddi_get8(bgep->io_handle, regaddr); 4781 break; 4782 4783 case 2: 4784 regval = ddi_get16(bgep->io_handle, regaddr); 4785 break; 4786 4787 case 4: 4788 regval = ddi_get32(bgep->io_handle, regaddr); 4789 break; 4790 4791 case 8: 4792 regval = ddi_get64(bgep->io_handle, regaddr); 4793 break; 4794 } 4795 4796 ppd->pp_acc_data = regval; 4797 } 4798 4799 static void bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd); 4800 #pragma no_inline(bge_chip_peek_reg) 4801 4802 static void 4803 bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd) 4804 { 4805 uint64_t regval; 4806 void *regaddr; 4807 4808 BGE_TRACE(("bge_chip_poke_reg($%p, $%p)", 4809 (void *)bgep, (void *)ppd)); 4810 4811 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 4812 regval = ppd->pp_acc_data; 4813 4814 switch (ppd->pp_acc_size) { 4815 case 1: 4816 ddi_put8(bgep->io_handle, regaddr, regval); 4817 break; 4818 4819 case 2: 4820 ddi_put16(bgep->io_handle, regaddr, regval); 4821 break; 4822 4823 case 4: 4824 ddi_put32(bgep->io_handle, regaddr, regval); 4825 break; 4826 4827 case 8: 4828 ddi_put64(bgep->io_handle, regaddr, regval); 4829 break; 4830 } 4831 BGE_PCICHK(bgep); 4832 } 4833 4834 static void bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd); 4835 #pragma no_inline(bge_chip_peek_nic) 4836 4837 static void 4838 bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd) 4839 { 4840 uint64_t regoff; 4841 uint64_t regval; 4842 void *regaddr; 4843 4844 BGE_TRACE(("bge_chip_peek_nic($%p, $%p)", 4845 (void *)bgep, (void *)ppd)); 4846 4847 regoff = ppd->pp_acc_offset; 4848 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 4849 regoff &= MWBAR_GRANULE_MASK; 4850 regoff += NIC_MEM_WINDOW_OFFSET; 4851 regaddr = PIO_ADDR(bgep, regoff); 4852 4853 switch (ppd->pp_acc_size) { 4854 case 1: 4855 regval = ddi_get8(bgep->io_handle, regaddr); 4856 break; 4857 4858 case 2: 4859 regval = ddi_get16(bgep->io_handle, regaddr); 4860 break; 4861 4862 case 4: 4863 regval = ddi_get32(bgep->io_handle, regaddr); 4864 break; 4865 4866 case 8: 4867 regval = ddi_get64(bgep->io_handle, regaddr); 4868 break; 4869 } 4870 4871 ppd->pp_acc_data = regval; 4872 } 4873 4874 static void bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd); 4875 #pragma no_inline(bge_chip_poke_nic) 4876 4877 static void 4878 bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd) 4879 { 4880 uint64_t regoff; 4881 uint64_t regval; 4882 void *regaddr; 4883 4884 BGE_TRACE(("bge_chip_poke_nic($%p, $%p)", 4885 (void *)bgep, (void *)ppd)); 4886 4887 regoff = ppd->pp_acc_offset; 4888 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 4889 regoff &= MWBAR_GRANULE_MASK; 4890 regoff += NIC_MEM_WINDOW_OFFSET; 4891 regaddr = PIO_ADDR(bgep, regoff); 4892 regval = ppd->pp_acc_data; 4893 4894 switch (ppd->pp_acc_size) { 4895 case 1: 4896 ddi_put8(bgep->io_handle, regaddr, regval); 4897 break; 4898 4899 case 2: 4900 ddi_put16(bgep->io_handle, regaddr, regval); 4901 break; 4902 4903 case 4: 4904 ddi_put32(bgep->io_handle, regaddr, regval); 4905 break; 4906 4907 case 8: 4908 ddi_put64(bgep->io_handle, regaddr, regval); 4909 break; 4910 } 4911 BGE_PCICHK(bgep); 4912 } 4913 4914 static void bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd); 4915 #pragma no_inline(bge_chip_peek_mii) 4916 4917 static void 4918 bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd) 4919 { 4920 BGE_TRACE(("bge_chip_peek_mii($%p, $%p)", 4921 (void *)bgep, (void *)ppd)); 4922 4923 ppd->pp_acc_data = bge_mii_get16(bgep, ppd->pp_acc_offset/2); 4924 } 4925 4926 static void bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd); 4927 #pragma no_inline(bge_chip_poke_mii) 4928 4929 static void 4930 bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd) 4931 { 4932 BGE_TRACE(("bge_chip_poke_mii($%p, $%p)", 4933 (void *)bgep, (void *)ppd)); 4934 4935 bge_mii_put16(bgep, ppd->pp_acc_offset/2, ppd->pp_acc_data); 4936 } 4937 4938 #if BGE_SEE_IO32 4939 4940 static void bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 4941 #pragma no_inline(bge_chip_peek_seeprom) 4942 4943 static void 4944 bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 4945 { 4946 uint32_t data; 4947 int err; 4948 4949 BGE_TRACE(("bge_chip_peek_seeprom($%p, $%p)", 4950 (void *)bgep, (void *)ppd)); 4951 4952 err = bge_nvmem_rw32(bgep, BGE_SEE_READ, ppd->pp_acc_offset, &data); 4953 ppd->pp_acc_data = err ? ~0ull : data; 4954 } 4955 4956 static void bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 4957 #pragma no_inline(bge_chip_poke_seeprom) 4958 4959 static void 4960 bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 4961 { 4962 uint32_t data; 4963 4964 BGE_TRACE(("bge_chip_poke_seeprom($%p, $%p)", 4965 (void *)bgep, (void *)ppd)); 4966 4967 data = ppd->pp_acc_data; 4968 (void) bge_nvmem_rw32(bgep, BGE_SEE_WRITE, ppd->pp_acc_offset, &data); 4969 } 4970 #endif /* BGE_SEE_IO32 */ 4971 4972 #if BGE_FLASH_IO32 4973 4974 static void bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd); 4975 #pragma no_inline(bge_chip_peek_flash) 4976 4977 static void 4978 bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd) 4979 { 4980 uint32_t data; 4981 int err; 4982 4983 BGE_TRACE(("bge_chip_peek_flash($%p, $%p)", 4984 (void *)bgep, (void *)ppd)); 4985 4986 err = bge_nvmem_rw32(bgep, BGE_FLASH_READ, ppd->pp_acc_offset, &data); 4987 ppd->pp_acc_data = err ? ~0ull : data; 4988 } 4989 4990 static void bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd); 4991 #pragma no_inline(bge_chip_poke_flash) 4992 4993 static void 4994 bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd) 4995 { 4996 uint32_t data; 4997 4998 BGE_TRACE(("bge_chip_poke_flash($%p, $%p)", 4999 (void *)bgep, (void *)ppd)); 5000 5001 data = ppd->pp_acc_data; 5002 (void) bge_nvmem_rw32(bgep, BGE_FLASH_WRITE, 5003 ppd->pp_acc_offset, &data); 5004 } 5005 #endif /* BGE_FLASH_IO32 */ 5006 5007 static void bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd); 5008 #pragma no_inline(bge_chip_peek_mem) 5009 5010 static void 5011 bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd) 5012 { 5013 uint64_t regval; 5014 void *vaddr; 5015 5016 BGE_TRACE(("bge_chip_peek_bge($%p, $%p)", 5017 (void *)bgep, (void *)ppd)); 5018 5019 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 5020 5021 switch (ppd->pp_acc_size) { 5022 case 1: 5023 regval = *(uint8_t *)vaddr; 5024 break; 5025 5026 case 2: 5027 regval = *(uint16_t *)vaddr; 5028 break; 5029 5030 case 4: 5031 regval = *(uint32_t *)vaddr; 5032 break; 5033 5034 case 8: 5035 regval = *(uint64_t *)vaddr; 5036 break; 5037 } 5038 5039 BGE_DEBUG(("bge_chip_peek_mem($%p, $%p) peeked 0x%llx from $%p", 5040 (void *)bgep, (void *)ppd, regval, vaddr)); 5041 5042 ppd->pp_acc_data = regval; 5043 } 5044 5045 static void bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd); 5046 #pragma no_inline(bge_chip_poke_mem) 5047 5048 static void 5049 bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd) 5050 { 5051 uint64_t regval; 5052 void *vaddr; 5053 5054 BGE_TRACE(("bge_chip_poke_mem($%p, $%p)", 5055 (void *)bgep, (void *)ppd)); 5056 5057 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 5058 regval = ppd->pp_acc_data; 5059 5060 BGE_DEBUG(("bge_chip_poke_mem($%p, $%p) poking 0x%llx at $%p", 5061 (void *)bgep, (void *)ppd, regval, vaddr)); 5062 5063 switch (ppd->pp_acc_size) { 5064 case 1: 5065 *(uint8_t *)vaddr = (uint8_t)regval; 5066 break; 5067 5068 case 2: 5069 *(uint16_t *)vaddr = (uint16_t)regval; 5070 break; 5071 5072 case 4: 5073 *(uint32_t *)vaddr = (uint32_t)regval; 5074 break; 5075 5076 case 8: 5077 *(uint64_t *)vaddr = (uint64_t)regval; 5078 break; 5079 } 5080 } 5081 5082 static enum ioc_reply bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5083 struct iocblk *iocp); 5084 #pragma no_inline(bge_pp_ioctl) 5085 5086 static enum ioc_reply 5087 bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5088 { 5089 void (*ppfn)(bge_t *bgep, bge_peekpoke_t *ppd); 5090 bge_peekpoke_t *ppd; 5091 dma_area_t *areap; 5092 uint64_t sizemask; 5093 uint64_t mem_va; 5094 uint64_t maxoff; 5095 boolean_t peek; 5096 5097 switch (cmd) { 5098 default: 5099 /* NOTREACHED */ 5100 bge_error(bgep, "bge_pp_ioctl: invalid cmd 0x%x", cmd); 5101 return (IOC_INVAL); 5102 5103 case BGE_PEEK: 5104 peek = B_TRUE; 5105 break; 5106 5107 case BGE_POKE: 5108 peek = B_FALSE; 5109 break; 5110 } 5111 5112 /* 5113 * Validate format of ioctl 5114 */ 5115 if (iocp->ioc_count != sizeof (bge_peekpoke_t)) 5116 return (IOC_INVAL); 5117 if (mp->b_cont == NULL) 5118 return (IOC_INVAL); 5119 ppd = (void *)mp->b_cont->b_rptr; 5120 5121 /* 5122 * Validate request parameters 5123 */ 5124 switch (ppd->pp_acc_space) { 5125 default: 5126 return (IOC_INVAL); 5127 5128 case BGE_PP_SPACE_CFG: 5129 /* 5130 * Config space 5131 */ 5132 sizemask = 8|4|2|1; 5133 mem_va = 0; 5134 maxoff = PCI_CONF_HDR_SIZE; 5135 ppfn = peek ? bge_chip_peek_cfg : bge_chip_poke_cfg; 5136 break; 5137 5138 case BGE_PP_SPACE_REG: 5139 /* 5140 * Memory-mapped I/O space 5141 */ 5142 sizemask = 8|4|2|1; 5143 mem_va = 0; 5144 maxoff = RIAAR_REGISTER_MAX; 5145 ppfn = peek ? bge_chip_peek_reg : bge_chip_poke_reg; 5146 break; 5147 5148 case BGE_PP_SPACE_NIC: 5149 /* 5150 * NIC on-chip memory 5151 */ 5152 sizemask = 8|4|2|1; 5153 mem_va = 0; 5154 maxoff = MWBAR_ONCHIP_MAX; 5155 ppfn = peek ? bge_chip_peek_nic : bge_chip_poke_nic; 5156 break; 5157 5158 case BGE_PP_SPACE_MII: 5159 /* 5160 * PHY's MII registers 5161 * NB: all PHY registers are two bytes, but the 5162 * addresses increment in ones (word addressing). 5163 * So we scale the address here, then undo the 5164 * transformation inside the peek/poke functions. 5165 */ 5166 ppd->pp_acc_offset *= 2; 5167 sizemask = 2; 5168 mem_va = 0; 5169 maxoff = (MII_MAXREG+1)*2; 5170 ppfn = peek ? bge_chip_peek_mii : bge_chip_poke_mii; 5171 break; 5172 5173 #if BGE_SEE_IO32 5174 case BGE_PP_SPACE_SEEPROM: 5175 /* 5176 * Attached SEEPROM(s), if any. 5177 * NB: we use the high-order bits of the 'address' as 5178 * a device select to accommodate multiple SEEPROMS, 5179 * If each one is the maximum size (64kbytes), this 5180 * makes them appear contiguous. Otherwise, there may 5181 * be holes in the mapping. ENxS doesn't have any 5182 * SEEPROMs anyway ... 5183 */ 5184 sizemask = 4; 5185 mem_va = 0; 5186 maxoff = SEEPROM_DEV_AND_ADDR_MASK; 5187 ppfn = peek ? bge_chip_peek_seeprom : bge_chip_poke_seeprom; 5188 break; 5189 #endif /* BGE_SEE_IO32 */ 5190 5191 #if BGE_FLASH_IO32 5192 case BGE_PP_SPACE_FLASH: 5193 /* 5194 * Attached Flash device (if any); a maximum of one device 5195 * is currently supported. But it can be up to 1MB (unlike 5196 * the 64k limit on SEEPROMs) so why would you need more ;-) 5197 */ 5198 sizemask = 4; 5199 mem_va = 0; 5200 maxoff = NVM_FLASH_ADDR_MASK; 5201 ppfn = peek ? bge_chip_peek_flash : bge_chip_poke_flash; 5202 break; 5203 #endif /* BGE_FLASH_IO32 */ 5204 5205 case BGE_PP_SPACE_BGE: 5206 /* 5207 * BGE data structure! 5208 */ 5209 sizemask = 8|4|2|1; 5210 mem_va = (uintptr_t)bgep; 5211 maxoff = sizeof (*bgep); 5212 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 5213 break; 5214 5215 case BGE_PP_SPACE_STATUS: 5216 case BGE_PP_SPACE_STATISTICS: 5217 case BGE_PP_SPACE_TXDESC: 5218 case BGE_PP_SPACE_TXBUFF: 5219 case BGE_PP_SPACE_RXDESC: 5220 case BGE_PP_SPACE_RXBUFF: 5221 /* 5222 * Various DMA_AREAs 5223 */ 5224 switch (ppd->pp_acc_space) { 5225 case BGE_PP_SPACE_TXDESC: 5226 areap = &bgep->tx_desc; 5227 break; 5228 case BGE_PP_SPACE_TXBUFF: 5229 areap = &bgep->tx_buff[0]; 5230 break; 5231 case BGE_PP_SPACE_RXDESC: 5232 areap = &bgep->rx_desc[0]; 5233 break; 5234 case BGE_PP_SPACE_RXBUFF: 5235 areap = &bgep->rx_buff[0]; 5236 break; 5237 case BGE_PP_SPACE_STATUS: 5238 areap = &bgep->status_block; 5239 break; 5240 case BGE_PP_SPACE_STATISTICS: 5241 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 5242 areap = &bgep->statistics; 5243 break; 5244 } 5245 5246 sizemask = 8|4|2|1; 5247 mem_va = (uintptr_t)areap->mem_va; 5248 maxoff = areap->alength; 5249 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 5250 break; 5251 } 5252 5253 switch (ppd->pp_acc_size) { 5254 default: 5255 return (IOC_INVAL); 5256 5257 case 8: 5258 case 4: 5259 case 2: 5260 case 1: 5261 if ((ppd->pp_acc_size & sizemask) == 0) 5262 return (IOC_INVAL); 5263 break; 5264 } 5265 5266 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 5267 return (IOC_INVAL); 5268 5269 if (ppd->pp_acc_offset >= maxoff) 5270 return (IOC_INVAL); 5271 5272 if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff) 5273 return (IOC_INVAL); 5274 5275 /* 5276 * All OK - go do it! 5277 */ 5278 ppd->pp_acc_offset += mem_va; 5279 (*ppfn)(bgep, ppd); 5280 return (peek ? IOC_REPLY : IOC_ACK); 5281 } 5282 5283 static enum ioc_reply bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5284 struct iocblk *iocp); 5285 #pragma no_inline(bge_diag_ioctl) 5286 5287 static enum ioc_reply 5288 bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5289 { 5290 ASSERT(mutex_owned(bgep->genlock)); 5291 5292 switch (cmd) { 5293 default: 5294 /* NOTREACHED */ 5295 bge_error(bgep, "bge_diag_ioctl: invalid cmd 0x%x", cmd); 5296 return (IOC_INVAL); 5297 5298 case BGE_DIAG: 5299 /* 5300 * Currently a no-op 5301 */ 5302 return (IOC_ACK); 5303 5304 case BGE_PEEK: 5305 case BGE_POKE: 5306 return (bge_pp_ioctl(bgep, cmd, mp, iocp)); 5307 5308 case BGE_PHY_RESET: 5309 return (IOC_RESTART_ACK); 5310 5311 case BGE_SOFT_RESET: 5312 case BGE_HARD_RESET: 5313 /* 5314 * Reset and reinitialise the 570x hardware 5315 */ 5316 bgep->bge_chip_state = BGE_CHIP_FAULT; 5317 ddi_trigger_softintr(bgep->factotum_id); 5318 (void) bge_restart(bgep, cmd == BGE_HARD_RESET); 5319 return (IOC_ACK); 5320 } 5321 5322 /* NOTREACHED */ 5323 } 5324 5325 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 5326 5327 static enum ioc_reply bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5328 struct iocblk *iocp); 5329 #pragma no_inline(bge_mii_ioctl) 5330 5331 static enum ioc_reply 5332 bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5333 { 5334 struct bge_mii_rw *miirwp; 5335 5336 /* 5337 * Validate format of ioctl 5338 */ 5339 if (iocp->ioc_count != sizeof (struct bge_mii_rw)) 5340 return (IOC_INVAL); 5341 if (mp->b_cont == NULL) 5342 return (IOC_INVAL); 5343 miirwp = (void *)mp->b_cont->b_rptr; 5344 5345 /* 5346 * Validate request parameters ... 5347 */ 5348 if (miirwp->mii_reg > MII_MAXREG) 5349 return (IOC_INVAL); 5350 5351 switch (cmd) { 5352 default: 5353 /* NOTREACHED */ 5354 bge_error(bgep, "bge_mii_ioctl: invalid cmd 0x%x", cmd); 5355 return (IOC_INVAL); 5356 5357 case BGE_MII_READ: 5358 miirwp->mii_data = bge_mii_get16(bgep, miirwp->mii_reg); 5359 return (IOC_REPLY); 5360 5361 case BGE_MII_WRITE: 5362 bge_mii_put16(bgep, miirwp->mii_reg, miirwp->mii_data); 5363 return (IOC_ACK); 5364 } 5365 5366 /* NOTREACHED */ 5367 } 5368 5369 #if BGE_SEE_IO32 5370 5371 static enum ioc_reply bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5372 struct iocblk *iocp); 5373 #pragma no_inline(bge_see_ioctl) 5374 5375 static enum ioc_reply 5376 bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5377 { 5378 struct bge_see_rw *seerwp; 5379 5380 /* 5381 * Validate format of ioctl 5382 */ 5383 if (iocp->ioc_count != sizeof (struct bge_see_rw)) 5384 return (IOC_INVAL); 5385 if (mp->b_cont == NULL) 5386 return (IOC_INVAL); 5387 seerwp = (void *)mp->b_cont->b_rptr; 5388 5389 /* 5390 * Validate request parameters ... 5391 */ 5392 if (seerwp->see_addr & ~SEEPROM_DEV_AND_ADDR_MASK) 5393 return (IOC_INVAL); 5394 5395 switch (cmd) { 5396 default: 5397 /* NOTREACHED */ 5398 bge_error(bgep, "bge_see_ioctl: invalid cmd 0x%x", cmd); 5399 return (IOC_INVAL); 5400 5401 case BGE_SEE_READ: 5402 case BGE_SEE_WRITE: 5403 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 5404 seerwp->see_addr, &seerwp->see_data); 5405 return (IOC_REPLY); 5406 } 5407 5408 /* NOTREACHED */ 5409 } 5410 5411 #endif /* BGE_SEE_IO32 */ 5412 5413 #if BGE_FLASH_IO32 5414 5415 static enum ioc_reply bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5416 struct iocblk *iocp); 5417 #pragma no_inline(bge_flash_ioctl) 5418 5419 static enum ioc_reply 5420 bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5421 { 5422 struct bge_flash_rw *flashrwp; 5423 5424 /* 5425 * Validate format of ioctl 5426 */ 5427 if (iocp->ioc_count != sizeof (struct bge_flash_rw)) 5428 return (IOC_INVAL); 5429 if (mp->b_cont == NULL) 5430 return (IOC_INVAL); 5431 flashrwp = (void *)mp->b_cont->b_rptr; 5432 5433 /* 5434 * Validate request parameters ... 5435 */ 5436 if (flashrwp->flash_addr & ~NVM_FLASH_ADDR_MASK) 5437 return (IOC_INVAL); 5438 5439 switch (cmd) { 5440 default: 5441 /* NOTREACHED */ 5442 bge_error(bgep, "bge_flash_ioctl: invalid cmd 0x%x", cmd); 5443 return (IOC_INVAL); 5444 5445 case BGE_FLASH_READ: 5446 case BGE_FLASH_WRITE: 5447 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 5448 flashrwp->flash_addr, &flashrwp->flash_data); 5449 return (IOC_REPLY); 5450 } 5451 5452 /* NOTREACHED */ 5453 } 5454 5455 #endif /* BGE_FLASH_IO32 */ 5456 5457 enum ioc_reply bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, 5458 struct iocblk *iocp); 5459 #pragma no_inline(bge_chip_ioctl) 5460 5461 enum ioc_reply 5462 bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 5463 { 5464 int cmd; 5465 5466 BGE_TRACE(("bge_chip_ioctl($%p, $%p, $%p, $%p)", 5467 (void *)bgep, (void *)wq, (void *)mp, (void *)iocp)); 5468 5469 ASSERT(mutex_owned(bgep->genlock)); 5470 5471 cmd = iocp->ioc_cmd; 5472 switch (cmd) { 5473 default: 5474 /* NOTREACHED */ 5475 bge_error(bgep, "bge_chip_ioctl: invalid cmd 0x%x", cmd); 5476 return (IOC_INVAL); 5477 5478 case BGE_DIAG: 5479 case BGE_PEEK: 5480 case BGE_POKE: 5481 case BGE_PHY_RESET: 5482 case BGE_SOFT_RESET: 5483 case BGE_HARD_RESET: 5484 #if BGE_DEBUGGING || BGE_DO_PPIO 5485 return (bge_diag_ioctl(bgep, cmd, mp, iocp)); 5486 #else 5487 return (IOC_INVAL); 5488 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 5489 5490 case BGE_MII_READ: 5491 case BGE_MII_WRITE: 5492 return (bge_mii_ioctl(bgep, cmd, mp, iocp)); 5493 5494 #if BGE_SEE_IO32 5495 case BGE_SEE_READ: 5496 case BGE_SEE_WRITE: 5497 return (bge_see_ioctl(bgep, cmd, mp, iocp)); 5498 #endif /* BGE_SEE_IO32 */ 5499 5500 #if BGE_FLASH_IO32 5501 case BGE_FLASH_READ: 5502 case BGE_FLASH_WRITE: 5503 return (bge_flash_ioctl(bgep, cmd, mp, iocp)); 5504 #endif /* BGE_FLASH_IO32 */ 5505 } 5506 5507 /* NOTREACHED */ 5508 } 5509 5510 /* ARGSUSED */ 5511 void 5512 bge_chip_blank(void *arg, time_t ticks, uint_t count, int flag) 5513 { 5514 recv_ring_t *rrp = arg; 5515 bge_t *bgep = rrp->bgep; 5516 5517 mutex_enter(bgep->genlock); 5518 rrp->poll_flag = flag; 5519 #ifdef NOT_YET 5520 /* 5521 * XXX-Sunay: Since most broadcom cards support only one 5522 * interrupt but multiple rx rings, we can't disable the 5523 * physical interrupt. This need to be done via capability 5524 * negotiation depending on the NIC. 5525 */ 5526 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, ticks); 5527 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, count); 5528 #endif 5529 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5530 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 5531 mutex_exit(bgep->genlock); 5532 } 5533 5534 #ifdef BGE_IPMI_ASF 5535 5536 uint32_t 5537 bge_nic_read32(bge_t *bgep, bge_regno_t addr) 5538 { 5539 uint32_t data; 5540 5541 #ifndef __sparc 5542 if (!bgep->asf_wordswapped) { 5543 /* a workaround word swap error */ 5544 if (addr & 4) 5545 addr = addr - 4; 5546 else 5547 addr = addr + 4; 5548 } 5549 #endif 5550 5551 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr); 5552 data = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR); 5553 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0); 5554 5555 data = LE_32(data); 5556 return (data); 5557 } 5558 5559 void 5560 bge_asf_update_status(bge_t *bgep) 5561 { 5562 uint32_t event; 5563 5564 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_ALIVE); 5565 bge_nic_put32(bgep, BGE_CMD_LENGTH_MAILBOX, 4); 5566 bge_nic_put32(bgep, BGE_CMD_DATA_MAILBOX, 3); 5567 5568 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5569 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 5570 } 5571 5572 5573 /* 5574 * The driver is supposed to notify ASF that the OS is still running 5575 * every three seconds, otherwise the management server may attempt 5576 * to reboot the machine. If it hasn't actually failed, this is 5577 * not a desirable result. However, this isn't running as a real-time 5578 * thread, and even if it were, it might not be able to generate the 5579 * heartbeat in a timely manner due to system load. As it isn't a 5580 * significant strain on the machine, we will set the interval to half 5581 * of the required value. 5582 */ 5583 void 5584 bge_asf_heartbeat(void *arg) 5585 { 5586 bge_t *bgep = (bge_t *)arg; 5587 5588 mutex_enter(bgep->genlock); 5589 bge_asf_update_status((bge_t *)bgep); 5590 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5591 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 5592 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) 5593 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 5594 mutex_exit(bgep->genlock); 5595 ((bge_t *)bgep)->asf_timeout_id = timeout(bge_asf_heartbeat, bgep, 5596 drv_usectohz(BGE_ASF_HEARTBEAT_INTERVAL)); 5597 } 5598 5599 5600 void 5601 bge_asf_stop_timer(bge_t *bgep) 5602 { 5603 timeout_id_t tmp_id = 0; 5604 5605 while ((bgep->asf_timeout_id != 0) && 5606 (tmp_id != bgep->asf_timeout_id)) { 5607 tmp_id = bgep->asf_timeout_id; 5608 (void) untimeout(tmp_id); 5609 } 5610 bgep->asf_timeout_id = 0; 5611 } 5612 5613 5614 5615 /* 5616 * This function should be placed at the earliest position of bge_attach(). 5617 */ 5618 void 5619 bge_asf_get_config(bge_t *bgep) 5620 { 5621 uint32_t nicsig; 5622 uint32_t niccfg; 5623 5624 bgep->asf_enabled = B_FALSE; 5625 nicsig = bge_nic_read32(bgep, BGE_NIC_DATA_SIG_ADDR); 5626 if (nicsig == BGE_NIC_DATA_SIG) { 5627 niccfg = bge_nic_read32(bgep, BGE_NIC_DATA_NIC_CFG_ADDR); 5628 if (niccfg & BGE_NIC_CFG_ENABLE_ASF) 5629 /* 5630 * Here, we don't consider BAXTER, because BGE haven't 5631 * supported BAXTER (that is 5752). Also, as I know, 5632 * BAXTER doesn't support ASF feature. 5633 */ 5634 bgep->asf_enabled = B_TRUE; 5635 else 5636 bgep->asf_enabled = B_FALSE; 5637 } else 5638 bgep->asf_enabled = B_FALSE; 5639 } 5640 5641 5642 void 5643 bge_asf_pre_reset_operations(bge_t *bgep, uint32_t mode) 5644 { 5645 uint32_t tries; 5646 uint32_t event; 5647 5648 ASSERT(bgep->asf_enabled); 5649 5650 /* Issues "pause firmware" command and wait for ACK */ 5651 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_PAUSE_FW); 5652 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5653 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 5654 5655 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5656 tries = 0; 5657 while ((event & RRER_ASF_EVENT) && (tries < 100)) { 5658 drv_usecwait(1); 5659 tries ++; 5660 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5661 } 5662 5663 bge_nic_put32(bgep, BGE_FIRMWARE_MAILBOX, 5664 BGE_MAGIC_NUM_FIRMWARE_INIT_DONE); 5665 5666 if (bgep->asf_newhandshake) { 5667 switch (mode) { 5668 case BGE_INIT_RESET: 5669 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5670 BGE_DRV_STATE_START); 5671 break; 5672 case BGE_SHUTDOWN_RESET: 5673 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5674 BGE_DRV_STATE_UNLOAD); 5675 break; 5676 case BGE_SUSPEND_RESET: 5677 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5678 BGE_DRV_STATE_SUSPEND); 5679 break; 5680 default: 5681 break; 5682 } 5683 } 5684 } 5685 5686 5687 void 5688 bge_asf_post_reset_old_mode(bge_t *bgep, uint32_t mode) 5689 { 5690 switch (mode) { 5691 case BGE_INIT_RESET: 5692 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5693 BGE_DRV_STATE_START); 5694 break; 5695 case BGE_SHUTDOWN_RESET: 5696 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5697 BGE_DRV_STATE_UNLOAD); 5698 break; 5699 case BGE_SUSPEND_RESET: 5700 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5701 BGE_DRV_STATE_SUSPEND); 5702 break; 5703 default: 5704 break; 5705 } 5706 } 5707 5708 5709 void 5710 bge_asf_post_reset_new_mode(bge_t *bgep, uint32_t mode) 5711 { 5712 switch (mode) { 5713 case BGE_INIT_RESET: 5714 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5715 BGE_DRV_STATE_START_DONE); 5716 break; 5717 case BGE_SHUTDOWN_RESET: 5718 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5719 BGE_DRV_STATE_UNLOAD_DONE); 5720 break; 5721 default: 5722 break; 5723 } 5724 } 5725 5726 #endif /* BGE_IPMI_ASF */ 5727