1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 /* 28 * Purpose: Definitions for the via8233 driver 29 */ 30 /* 31 * This file is part of Open Sound System 32 * 33 * Copyright (C) 4Front Technologies 1996-2008. 34 * 35 * This software is released under CDDL 1.0 source license. 36 * See the COPYING file included in the main directory of this source 37 * distribution for the license terms and conditions. 38 */ 39 #ifndef AUDIOVIA823X_H 40 #define AUDIOVIA823X_H 41 42 #define AUVIA_NAME "audiovia823x" 43 44 #define VIA_VENDOR_ID 0x1106 45 #define VIA_8233_ID 0x3059 46 #define VIA_8233A_ID 0x7059 47 48 /* pci configuration registers */ 49 #define AUVIA_PCICFG 0x40 /* Via chip specific cfg reg */ 50 #define AUVIA_PCICFG_LEGACY 0x00ff0000 /* legacy enables mask */ 51 #define AUVIA_PCICFG_ACLINKEN 0x00008000 /* AC'97 link enable */ 52 #define AUVIA_PCICFG_NRST 0x00004000 /* inverse of AC'97 reset */ 53 #define AUVIA_PCICFG_ACSYNC 0x00002000 /* AC'97 sync */ 54 #define AUVIA_PCICFG_SRCEN 0x00000800 /* sample rate converter en */ 55 #define AUVIA_PCICFG_SGDEN 0x00000400 /* SGD enable */ 56 #define AUVIA_PCICFG_FMEN 0x00000200 /* FM synth enable (legacy) */ 57 #define AUVIA_PCICFG_SBEN 0x00000100 /* SB compat enable (legacy) */ 58 #define AUVIA_PCICFG_PRIVALID 0x00000001 /* primary codec ready */ 59 60 #define AUVIA_PLAY_SGD_NUM 1 61 #define AUVIA_REC_SGD_NUM 0 62 #define AUVIA_NUM_PORTC 2 63 #define AUVIA_NUM_SGD 16 /* number of fragments */ 64 65 #define AUVIA_MAX_INTRS 256 66 #define AUVIA_MIN_INTRS 24 67 #define AUVIA_INTRS 175 68 69 #define AUVIA_SGD_EOL 0x80000000 70 #define AUVIA_SGD_FLAG 0x40000000 71 72 #define CODEC_TIMEOUT_COUNT 500 73 74 #define REG_PLAYBASE 0x40 /* Multichannel SGD */ 75 #define REG_RECBASE 0x60 76 #define REG_CODEC 0x80 /* Access AC97 Codec */ 77 #define REG_GSTAT 0x84 /* Global status */ 78 79 /* REG_CODEC */ 80 #define CODEC_IN_CMD 0x01000000 /* busy in sending */ 81 #define CODEC_STA_VALID 0x02000000 /* 1:status data is valid */ 82 #define CODEC_RD 0x00800000 /* Read CODEC status */ 83 #define CODEC_WR 0x00000000 /* Write CODEC status */ 84 #define CODEC_INDEX 0x007F0000 /* Index of command register */ 85 #define CODEC_DATA 0x0000FFFF /* AC97 status register data */ 86 87 /* registers that are offsets relative to a port */ 88 #define OFF_STATUS 0x00 89 #define OFF_CTRL 0x01 90 #define OFF_PLAYFMT 0x02 91 #define OFF_RECFIFO 0x02 92 #define OFF_DMA 0x04 93 #define OFF_CHANNELS 0x08 94 #define OFF_RECFMT 0x08 95 #define OFF_COUNT 0x0C 96 97 /* bits for above offsets */ 98 #define STATUS_INTR 0x3 99 100 #define CTRL_START 0x80 101 #define CTRL_TERMINATE 0x40 102 #define CTRL_AUTOSTART 0x20 103 #define CTRL_MULTICHORDER 0x10 /* SGD 0x40 only, Center/LFE order */ 104 #define CTRL_FLAG 0x01 105 106 #define PLAYFMT_16BIT 0x80 107 #define PLAYFMT_STEREO 0x20 /* Num channels (1-6), upper nybble */ 108 #define PLAYFMT_6CH 0x60 109 #define PLAYFMT_4CH 0x40 110 111 #define RECFIFO_ENABLE 0x40 112 113 #define RECFMT_48K 0x00ffffff 114 #define RECFMT_STEREO 0x00100000 115 #define RECFMT_16BIT 0x00200000 116 117 118 typedef struct { 119 unsigned int phaddr; 120 unsigned int flags; 121 } SGD_entry; 122 123 typedef struct auvia_portc auvia_portc_t; 124 typedef struct auvia_devc auvia_devc_t; 125 126 struct auvia_portc { 127 auvia_devc_t *devc; 128 audio_engine_t *engine; 129 caddr_t base; /* base for registers */ 130 boolean_t started; 131 int nchan; 132 133 ddi_dma_handle_t sgd_dmah; /* dma for descriptors */ 134 ddi_acc_handle_t sgd_acch; 135 uint32_t sgd_paddr; 136 caddr_t sgd_kaddr; 137 138 ddi_dma_handle_t buf_dmah; /* dma for buffers */ 139 ddi_acc_handle_t buf_acch; 140 uint32_t buf_paddr; 141 caddr_t buf_kaddr; 142 size_t buf_size; 143 int syncdir; 144 145 unsigned intrs; 146 unsigned fragfr; 147 unsigned fragsz; 148 unsigned cur_frag; 149 unsigned resid; 150 151 uint64_t count; 152 153 /* helper functions */ 154 void (*reset)(auvia_portc_t *); 155 }; 156 157 158 struct auvia_devc { 159 dev_info_t *dip; 160 audio_dev_t *adev; 161 ac97_t *ac97; 162 kstat_t *ksp; 163 boolean_t suspended; 164 165 char *chip_name; 166 int chip_type; 167 #define CHIP_8233 0 168 #define CHIP_8233A 1 169 170 /* registers */ 171 ddi_acc_handle_t pcih; 172 ddi_acc_handle_t regsh; 173 caddr_t base; 174 175 kmutex_t mutex; /* For normal locking */ 176 kmutex_t low_mutex; /* For low level routines */ 177 ddi_intr_handle_t ih; 178 auvia_portc_t *portc[AUVIA_NUM_PORTC]; 179 }; 180 181 #define AUVIA_KIOP(X) ((kstat_intr_t *)(X->ksp->ks_data)) 182 183 #define INL(devc, reg) ddi_get32(devc->regsh, (void *)(reg)) 184 185 #define INB(devc, reg) ddi_get8(devc->regsh, (void *)(reg)) 186 187 #define OUTL(devc, reg, val) ddi_put32(devc->regsh, (void *)(reg), (val)) 188 189 #define OUTB(devc, reg, val) ddi_put8(devc->regsh, (void *)(reg), (val)) 190 191 #endif /* AUDIOVIA823X_H */ 192