1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 /* 28 * Purpose: Driver for the Creative Audigy LS sound card 29 */ 30 /* 31 * 32 * Copyright (C) 4Front Technologies 1996-2009. 33 */ 34 35 #include <sys/types.h> 36 #include <sys/modctl.h> 37 #include <sys/kmem.h> 38 #include <sys/conf.h> 39 #include <sys/ddi.h> 40 #include <sys/sunddi.h> 41 #include <sys/pci.h> 42 #include <sys/note.h> 43 #include <sys/audio/audio_driver.h> 44 #include <sys/audio/ac97.h> 45 46 #include "audiols.h" 47 48 static struct ddi_device_acc_attr dev_attr = { 49 DDI_DEVICE_ATTR_V0, 50 DDI_STRUCTURE_LE_ACC, 51 DDI_STRICTORDER_ACC 52 }; 53 54 static struct ddi_device_acc_attr buf_attr = { 55 DDI_DEVICE_ATTR_V0, 56 DDI_NEVERSWAP_ACC, 57 DDI_STRICTORDER_ACC 58 }; 59 60 static ddi_dma_attr_t dma_attr_buf = { 61 DMA_ATTR_V0, /* version number */ 62 0x00000000, /* low DMA address range */ 63 0xffffffff, /* high DMA address range */ 64 0x000fffff, /* DMA counter (16 bits only in Audigy LS) */ 65 4, /* DMA address alignment */ 66 0x3c, /* DMA burstsizes */ 67 4, /* min effective DMA size */ 68 0xffffffff, /* max DMA xfer size */ 69 0xffffffff, /* segment boundary */ 70 1, /* s/g length */ 71 4, /* granularity of device */ 72 0 /* Bus specific DMA flags */ 73 }; 74 75 static int audigyls_attach(dev_info_t *); 76 static int audigyls_resume(dev_info_t *); 77 static int audigyls_detach(audigyls_dev_t *); 78 static int audigyls_suspend(audigyls_dev_t *); 79 80 static int audigyls_open(void *, int, unsigned *, unsigned *, caddr_t *); 81 static void audigyls_close(void *); 82 static int audigyls_start(void *); 83 static void audigyls_stop(void *); 84 static int audigyls_format(void *); 85 static int audigyls_channels(void *); 86 static int audigyls_rate(void *); 87 static uint64_t audigyls_count(void *); 88 static void audigyls_sync(void *, unsigned); 89 static void audigyls_chinfo(void *, int, unsigned *, unsigned *); 90 91 92 static uint16_t audigyls_read_ac97(void *, uint8_t); 93 static void audigyls_write_ac97(void *, uint8_t, uint16_t); 94 static int audigyls_alloc_port(audigyls_dev_t *, int); 95 static void audigyls_start_port(audigyls_port_t *); 96 static void audigyls_stop_port(audigyls_port_t *); 97 static void audigyls_update_port(audigyls_port_t *); 98 static void audigyls_reset_port(audigyls_port_t *); 99 static void audigyls_destroy(audigyls_dev_t *); 100 static int audigyls_setup_intrs(audigyls_dev_t *); 101 static void audigyls_hwinit(audigyls_dev_t *); 102 static uint_t audigyls_intr(caddr_t, caddr_t); 103 static void audigyls_configure_mixer(audigyls_dev_t *dev); 104 105 static audio_engine_ops_t audigyls_engine_ops = { 106 AUDIO_ENGINE_VERSION, 107 audigyls_open, 108 audigyls_close, 109 audigyls_start, 110 audigyls_stop, 111 audigyls_count, 112 audigyls_format, 113 audigyls_channels, 114 audigyls_rate, 115 audigyls_sync, 116 NULL, 117 audigyls_chinfo, 118 NULL 119 }; 120 121 /* 122 * Audigy LS uses AC'97 strictly for the recording side of things. 123 * While the chip can supposedly route output to AC'97 for playback, 124 * the PCI devices use a separate I2S DAC instead. As a result we 125 * need to suppress controls that the AC'97 codec registers. 126 * 127 * Furthermore, even then the AC'97 codec offers inputs that we just 128 * aren't interested in. 129 */ 130 const char *audigyls_remove_ac97[] = { 131 AUDIO_CTRL_ID_VOLUME, 132 AUDIO_CTRL_ID_LINEOUT, 133 AUDIO_CTRL_ID_HEADPHONE, 134 AUDIO_CTRL_ID_CD, 135 AUDIO_CTRL_ID_VIDEO, 136 AUDIO_CTRL_ID_3DDEPTH, 137 AUDIO_CTRL_ID_3DENHANCE, 138 AUDIO_CTRL_ID_BEEP, 139 AUDIO_CTRL_ID_RECGAIN, 140 AUDIO_CTRL_ID_RECSRC, 141 AUDIO_CTRL_ID_LOOPBACK, 142 NULL, 143 }; 144 145 /* 146 * AC'97 sources we don't want to expose. 147 */ 148 const char *audigyls_badsrcs[] = { 149 AUDIO_PORT_VIDEO, 150 AUDIO_PORT_CD, 151 AUDIO_PORT_STEREOMIX, 152 AUDIO_PORT_MONOMIX, 153 NULL, 154 }; 155 156 static unsigned int 157 read_chan(audigyls_dev_t *dev, int reg, int chn) 158 { 159 uint32_t val; 160 161 mutex_enter(&dev->low_mutex); 162 /* Pointer */ 163 OUTL(dev, PR, (reg << 16) | (chn & 0xffff)); 164 /* Data */ 165 val = INL(dev, DR); 166 mutex_exit(&dev->low_mutex); 167 168 return (val); 169 } 170 171 static void 172 write_chan(audigyls_dev_t *dev, int reg, int chn, uint32_t value) 173 { 174 mutex_enter(&dev->low_mutex); 175 /* Pointer */ 176 OUTL(dev, PR, (reg << 16) | (chn & 0x7)); 177 /* Data */ 178 OUTL(dev, DR, value); 179 mutex_exit(&dev->low_mutex); 180 } 181 182 static unsigned int 183 read_reg(audigyls_dev_t *dev, int reg) 184 { 185 return (read_chan(dev, reg, 0)); 186 } 187 188 static void 189 write_reg(audigyls_dev_t *dev, int reg, uint32_t value) 190 { 191 write_chan(dev, reg, 0, value); 192 } 193 194 195 static uint16_t 196 audigyls_read_ac97(void *arg, uint8_t index) 197 { 198 audigyls_dev_t *dev = arg; 199 uint16_t dtemp = 0; 200 int i; 201 202 mutex_enter(&dev->low_mutex); 203 OUTB(dev, AC97A, index); 204 for (i = 0; i < 10000; i++) { 205 if (INB(dev, AC97A) & 0x80) 206 break; 207 } 208 if (i == 10000) { /* Timeout */ 209 mutex_exit(&dev->low_mutex); 210 return (0xffff); 211 } 212 dtemp = INW(dev, AC97D); 213 mutex_exit(&dev->low_mutex); 214 215 return (dtemp); 216 } 217 218 static void 219 audigyls_write_ac97(void *arg, uint8_t index, uint16_t data) 220 { 221 audigyls_dev_t *dev = arg; 222 int i; 223 224 mutex_enter(&dev->low_mutex); 225 OUTB(dev, AC97A, index); 226 for (i = 0; i < 50000; i++) { 227 if (INB(dev, AC97A) & 0x80) 228 break; 229 } 230 if (i == 50000) { 231 mutex_exit(&dev->low_mutex); 232 return; 233 } 234 OUTW(dev, AC97D, data); 235 mutex_exit(&dev->low_mutex); 236 } 237 238 static void 239 select_digital_enable(audigyls_dev_t *dev, int mode) 240 { 241 /* 242 * Set the out3/spdif combo jack format. 243 * mode0=analog rear/center, 1=spdif 244 */ 245 246 if (mode == 0) { 247 write_reg(dev, SPC, 0x00000f00); 248 } else { 249 write_reg(dev, SPC, 0x0000000f); 250 } 251 } 252 253 /* only for SBLive 7.1 */ 254 void 255 audigyls_i2c_write(audigyls_dev_t *dev, int reg, int data) 256 { 257 int i, timeout, tmp; 258 259 tmp = (reg << 9 | data) << 16; /* set the upper 16 bits */ 260 /* first write the command to the data reg */ 261 write_reg(dev, I2C_1, tmp); 262 for (i = 0; i < 20; i++) { 263 tmp = read_reg(dev, I2C_A) & ~0x6fe; 264 /* see audigyls.pdf for bits */ 265 tmp |= 0x400 | 0x100 | 0x34; 266 write_reg(dev, I2C_A, tmp); 267 /* now wait till controller sets valid bit (0x100) to 0 */ 268 timeout = 0; 269 for (;;) { 270 tmp = read_reg(dev, I2C_A); 271 if ((tmp & 0x100) == 0) 272 break; 273 274 if (timeout > 100) 275 break; 276 277 timeout++; 278 } 279 280 /* transaction aborted */ 281 if (tmp & 0x200) 282 break; 283 } 284 } 285 286 int 287 audigyls_spi_write(audigyls_dev_t *dev, int data) 288 { 289 unsigned int orig; 290 unsigned int tmp; 291 int i, valid; 292 293 tmp = read_reg(dev, SPI); 294 orig = (tmp & ~0x3ffff) | 0x30000; 295 write_reg(dev, SPI, orig | data); 296 valid = 0; 297 /* Wait for status bit to return to 0 */ 298 for (i = 0; i < 1000; i++) { 299 drv_usecwait(100); 300 tmp = read_reg(dev, SPI); 301 if (!(tmp & 0x10000)) { 302 valid = 1; 303 break; 304 } 305 } 306 if (!valid) /* Timed out */ 307 return (0); 308 309 return (1); 310 } 311 312 static void 313 audigyls_update_port(audigyls_port_t *port) 314 { 315 audigyls_dev_t *dev = port->dev; 316 uint32_t offset, n; 317 318 if (dev->suspended) 319 return; 320 321 if (port->direction == AUDIGYLS_PLAY_PORT) { 322 offset = read_chan(dev, CPFA, 0); 323 } else { 324 offset = read_chan(dev, CRFA, 2); 325 } 326 327 328 /* get the offset, and switch to frames */ 329 offset /= (2 * sizeof (uint16_t)); 330 331 if (offset >= port->offset) { 332 n = offset - port->offset; 333 } else { 334 n = offset + (port->buf_frames - port->offset); 335 } 336 port->offset = offset; 337 port->count += n; 338 } 339 340 static void 341 check_play_intr(audigyls_dev_t *dev) 342 { 343 audigyls_port_t *port = dev->port[AUDIGYLS_PLAY_PORT]; 344 345 if (!port->started) 346 return; 347 audio_engine_consume(port->engine); 348 } 349 350 static void 351 check_rec_intr(audigyls_dev_t *dev) 352 { 353 audigyls_port_t *port = dev->port[AUDIGYLS_REC_PORT]; 354 355 if (!port->started) 356 return; 357 audio_engine_produce(port->engine); 358 } 359 360 static uint_t 361 audigyls_intr(caddr_t argp, caddr_t nocare) 362 { 363 audigyls_dev_t *dev = (void *)argp; 364 uint32_t status; 365 366 _NOTE(ARGUNUSED(nocare)); 367 status = INL(dev, IPR); 368 369 if (dev->suspended) { 370 OUTL(dev, IPR, status); /* Acknowledge */ 371 return (DDI_INTR_UNCLAIMED); 372 } 373 374 if (!(status & (INTR_IT1 | INTR_PCI))) { 375 /* No audio interrupts pending */ 376 OUTL(dev, IPR, status); /* Acknowledge */ 377 return (DDI_INTR_UNCLAIMED); 378 } 379 380 check_play_intr(dev); 381 check_rec_intr(dev); 382 383 if (dev->ksp) { 384 AUDIGYLS_KIOP(dev)->intrs[KSTAT_INTR_HARD]++; 385 } 386 387 OUTL(dev, IPR, status); /* Acknowledge */ 388 return (DDI_INTR_CLAIMED); 389 } 390 391 /* 392 * Audio routines 393 */ 394 395 int 396 audigyls_open(void *arg, int flag, 397 unsigned *fragfrp, unsigned *nfragsp, caddr_t *bufp) 398 { 399 audigyls_port_t *port = arg; 400 audigyls_dev_t *dev = port->dev; 401 402 _NOTE(ARGUNUSED(flag)); 403 404 mutex_enter(&dev->mutex); 405 406 port->started = B_FALSE; 407 port->count = 0; 408 *fragfrp = port->fragfr; 409 *nfragsp = AUDIGYLS_NUM_FRAGS; 410 *bufp = port->buf_kaddr; 411 audigyls_reset_port(port); 412 mutex_exit(&dev->mutex); 413 414 return (0); 415 } 416 417 void 418 audigyls_close(void *arg) 419 { 420 audigyls_port_t *port = arg; 421 audigyls_dev_t *dev = port->dev; 422 423 mutex_enter(&dev->mutex); 424 audigyls_stop_port(port); 425 port->started = B_FALSE; 426 mutex_exit(&dev->mutex); 427 } 428 429 int 430 audigyls_start(void *arg) 431 { 432 audigyls_port_t *port = arg; 433 audigyls_dev_t *dev = port->dev; 434 435 mutex_enter(&dev->mutex); 436 if (!port->started) { 437 audigyls_start_port(port); 438 port->started = B_TRUE; 439 } 440 mutex_exit(&dev->mutex); 441 return (0); 442 } 443 444 void 445 audigyls_stop(void *arg) 446 { 447 audigyls_port_t *port = arg; 448 audigyls_dev_t *dev = port->dev; 449 450 mutex_enter(&dev->mutex); 451 if (port->started) { 452 audigyls_stop_port(port); 453 port->started = B_FALSE; 454 } 455 mutex_exit(&dev->mutex); 456 } 457 458 int 459 audigyls_format(void *arg) 460 { 461 _NOTE(ARGUNUSED(arg)); 462 463 return (AUDIO_FORMAT_S16_LE); 464 } 465 466 int 467 audigyls_channels(void *arg) 468 { 469 audigyls_port_t *port = arg; 470 471 return (port->nchan); 472 } 473 474 int 475 audigyls_rate(void *arg) 476 { 477 _NOTE(ARGUNUSED(arg)); 478 479 return (48000); 480 } 481 482 void 483 audigyls_sync(void *arg, unsigned nframes) 484 { 485 audigyls_port_t *port = arg; 486 _NOTE(ARGUNUSED(nframes)); 487 488 (void) ddi_dma_sync(port->buf_dmah, 0, 0, port->syncdir); 489 } 490 491 uint64_t 492 audigyls_count(void *arg) 493 { 494 audigyls_port_t *port = arg; 495 audigyls_dev_t *dev = port->dev; 496 uint64_t count; 497 498 mutex_enter(&dev->mutex); 499 if (!dev->suspended) 500 audigyls_update_port(port); 501 count = port->count; 502 mutex_exit(&dev->mutex); 503 return (count); 504 } 505 506 static void 507 audigyls_chinfo(void *arg, int chan, unsigned *offset, unsigned *incr) 508 { 509 audigyls_port_t *port = arg; 510 511 if (port->direction == AUDIGYLS_PLAY_PORT) { 512 *offset = (port->buf_frames * 2 * (chan / 2)) + (chan % 2); 513 *incr = 2; 514 } else { 515 *offset = chan; 516 *incr = 2; 517 } 518 } 519 520 /* private implementation bits */ 521 522 void 523 audigyls_start_port(audigyls_port_t *port) 524 { 525 audigyls_dev_t *dev = port->dev; 526 uint32_t tmp; 527 528 ASSERT(mutex_owned(&dev->mutex)); 529 530 if (dev->suspended || port->active) 531 return; 532 533 port->active = B_TRUE; 534 port->offset = 0; 535 dev->nactive++; 536 537 if (dev->nactive == 1) { 538 write_reg(dev, IT, dev->timer); 539 OUTL(dev, IER, INL(dev, IER) | INTR_IT1); 540 } 541 542 switch (port->direction) { 543 case AUDIGYLS_PLAY_PORT: 544 tmp = read_reg(dev, SA); 545 tmp |= SA_SPA(0); 546 tmp |= SA_SPA(1); 547 tmp |= SA_SPA(3); 548 write_reg(dev, SA, tmp); 549 break; 550 551 case AUDIGYLS_REC_PORT: 552 tmp = read_reg(dev, SA); 553 tmp |= SA_SRA(2); 554 write_reg(dev, SA, tmp); 555 break; 556 } 557 558 } 559 560 void 561 audigyls_stop_port(audigyls_port_t *port) 562 { 563 audigyls_dev_t *dev = port->dev; 564 uint32_t tmp; 565 566 if (dev->suspended || !port->active) 567 return; 568 569 port->active = B_FALSE; 570 dev->nactive--; 571 572 switch (port->direction) { 573 case AUDIGYLS_PLAY_PORT: 574 tmp = read_reg(dev, SA); 575 tmp &= ~SA_SPA(0); 576 tmp &= ~SA_SPA(1); 577 tmp &= ~SA_SPA(3); 578 write_reg(dev, SA, tmp); 579 break; 580 581 case AUDIGYLS_REC_PORT: 582 tmp = read_reg(dev, SA); 583 tmp &= ~SA_SRA(2); 584 write_reg(dev, SA, tmp); 585 break; 586 } 587 588 if (dev->nactive == 0) { 589 OUTL(dev, IER, INL(dev, IER) & ~INTR_IT1); 590 } 591 } 592 593 void 594 audigyls_reset_port(audigyls_port_t *port) 595 { 596 audigyls_dev_t *dev = port->dev; 597 598 ASSERT(mutex_owned(&dev->mutex)); 599 600 if (dev->suspended) 601 return; 602 603 switch (port->direction) { 604 case AUDIGYLS_PLAY_PORT: 605 write_chan(dev, PTCA, 0, 0); 606 write_chan(dev, CPFA, 0, 0); 607 write_chan(dev, CPCAV, 0, 0); 608 write_chan(dev, PTCA, 1, 0); 609 write_chan(dev, CPFA, 1, 0); 610 write_chan(dev, CPCAV, 1, 0); 611 write_chan(dev, PTCA, 3, 0); 612 write_chan(dev, CPFA, 3, 0); 613 write_chan(dev, CPCAV, 3, 0); 614 break; 615 616 case AUDIGYLS_REC_PORT: 617 write_chan(dev, CRFA, 2, 0); 618 write_chan(dev, CRCAV, 2, 0); 619 break; 620 } 621 } 622 623 int 624 audigyls_alloc_port(audigyls_dev_t *dev, int num) 625 { 626 audigyls_port_t *port; 627 size_t len; 628 ddi_dma_cookie_t cookie; 629 uint_t count; 630 int dir; 631 unsigned caps; 632 audio_dev_t *adev; 633 634 adev = dev->adev; 635 port = kmem_zalloc(sizeof (*port), KM_SLEEP); 636 dev->port[num] = port; 637 port->dev = dev; 638 port->started = B_FALSE; 639 port->direction = num; 640 641 switch (num) { 642 case AUDIGYLS_REC_PORT: 643 port->syncdir = DDI_DMA_SYNC_FORKERNEL; 644 caps = ENGINE_INPUT_CAP; 645 dir = DDI_DMA_READ; 646 port->nchan = 2; 647 break; 648 case AUDIGYLS_PLAY_PORT: 649 port->syncdir = DDI_DMA_SYNC_FORDEV; 650 caps = ENGINE_OUTPUT_CAP; 651 dir = DDI_DMA_WRITE; 652 port->nchan = 6; 653 break; 654 default: 655 return (DDI_FAILURE); 656 } 657 658 /* figure out fragment configuration */ 659 port->fragfr = 48000 / dev->intrs; 660 /* we want to make sure that we are aligning on reasonable chunks */ 661 port->fragfr = (port->fragfr + 63) & ~(63); 662 663 /* 16 bit frames */ 664 port->fragsz = port->fragfr * 2 * port->nchan; 665 port->buf_size = port->fragsz * AUDIGYLS_NUM_FRAGS; 666 port->buf_frames = port->fragfr * AUDIGYLS_NUM_FRAGS; 667 668 /* Alloc buffers */ 669 if (ddi_dma_alloc_handle(dev->dip, &dma_attr_buf, DDI_DMA_SLEEP, NULL, 670 &port->buf_dmah) != DDI_SUCCESS) { 671 audio_dev_warn(adev, "failed to allocate BUF handle"); 672 return (DDI_FAILURE); 673 } 674 675 if (ddi_dma_mem_alloc(port->buf_dmah, port->buf_size, 676 &buf_attr, DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, 677 &port->buf_kaddr, &len, &port->buf_acch) != DDI_SUCCESS) { 678 audio_dev_warn(adev, "failed to allocate BUF memory"); 679 return (DDI_FAILURE); 680 } 681 682 if (ddi_dma_addr_bind_handle(port->buf_dmah, NULL, port->buf_kaddr, 683 len, DDI_DMA_CONSISTENT | dir, DDI_DMA_SLEEP, NULL, &cookie, 684 &count) != DDI_SUCCESS) { 685 audio_dev_warn(adev, "failed binding BUF DMA handle"); 686 return (DDI_FAILURE); 687 } 688 port->buf_paddr = cookie.dmac_address; 689 690 port->engine = audio_engine_alloc(&audigyls_engine_ops, caps); 691 if (port->engine == NULL) { 692 audio_dev_warn(adev, "audio_engine_alloc failed"); 693 return (DDI_FAILURE); 694 } 695 696 audio_engine_set_private(port->engine, port); 697 audio_dev_add_engine(adev, port->engine); 698 699 return (DDI_SUCCESS); 700 } 701 702 int 703 audigyls_setup_intrs(audigyls_dev_t *dev) 704 { 705 uint_t ipri; 706 int actual; 707 int rv; 708 ddi_intr_handle_t ih[1]; 709 710 rv = ddi_intr_alloc(dev->dip, ih, DDI_INTR_TYPE_FIXED, 711 0, 1, &actual, DDI_INTR_ALLOC_STRICT); 712 if ((rv != DDI_SUCCESS) || (actual != 1)) { 713 audio_dev_warn(dev->adev, 714 "Can't alloc interrupt handle (rv %d actual %d)", 715 rv, actual); 716 return (DDI_FAILURE); 717 } 718 719 if (ddi_intr_get_pri(ih[0], &ipri) != DDI_SUCCESS) { 720 audio_dev_warn(dev->adev, "Can't get interrupt priority"); 721 (void) ddi_intr_free(ih[0]); 722 return (DDI_FAILURE); 723 } 724 725 if (ddi_intr_add_handler(ih[0], audigyls_intr, dev, NULL) != 726 DDI_SUCCESS) { 727 audio_dev_warn(dev->adev, "Can't add interrupt handler"); 728 (void) ddi_intr_free(ih[0]); 729 return (DDI_FAILURE); 730 } 731 732 dev->ih = ih[0]; 733 mutex_init(&dev->mutex, NULL, MUTEX_DRIVER, DDI_INTR_PRI(ipri)); 734 mutex_init(&dev->low_mutex, NULL, MUTEX_DRIVER, DDI_INTR_PRI(ipri)); 735 return (DDI_SUCCESS); 736 } 737 738 void 739 audigyls_del_controls(audigyls_dev_t *dev) 740 { 741 for (int i = 0; i < CTL_NUM; i++) { 742 if (dev->controls[i].ctrl) { 743 audio_dev_del_control(dev->controls[i].ctrl); 744 dev->controls[i].ctrl = NULL; 745 } 746 } 747 } 748 749 void 750 audigyls_destroy(audigyls_dev_t *dev) 751 { 752 if (dev->ih != NULL) { 753 (void) ddi_intr_disable(dev->ih); 754 (void) ddi_intr_remove_handler(dev->ih); 755 (void) ddi_intr_free(dev->ih); 756 mutex_destroy(&dev->mutex); 757 mutex_destroy(&dev->low_mutex); 758 } 759 760 if (dev->ksp) { 761 kstat_delete(dev->ksp); 762 } 763 764 for (int i = 0; i < AUDIGYLS_NUM_PORT; i++) { 765 audigyls_port_t *port = dev->port[i]; 766 if (!port) 767 continue; 768 if (port->engine) { 769 audio_dev_remove_engine(dev->adev, port->engine); 770 audio_engine_free(port->engine); 771 } 772 if (port->buf_paddr) { 773 (void) ddi_dma_unbind_handle(port->buf_dmah); 774 } 775 if (port->buf_acch) { 776 ddi_dma_mem_free(&port->buf_acch); 777 } 778 if (port->buf_dmah) { 779 ddi_dma_free_handle(&port->buf_dmah); 780 } 781 kmem_free(port, sizeof (*port)); 782 } 783 784 if (dev->ac97 != NULL) { 785 ac97_free(dev->ac97); 786 } 787 788 audigyls_del_controls(dev); 789 790 if (dev->adev != NULL) { 791 audio_dev_free(dev->adev); 792 } 793 if (dev->regsh != NULL) { 794 ddi_regs_map_free(&dev->regsh); 795 } 796 if (dev->pcih != NULL) { 797 pci_config_teardown(&dev->pcih); 798 } 799 kmem_free(dev, sizeof (*dev)); 800 } 801 802 void 803 audigyls_hwinit(audigyls_dev_t *dev) 804 { 805 static unsigned int spi_dac[] = { 806 0x00ff, 0x02ff, 0x0400, 0x520, 0x0620, 0x08ff, 0x0aff, 0x0cff, 807 0x0eff, 0x10ff, 0x1200, 0x1400, 0x1800, 0x1aff, 0x1cff, 808 0x1e00, 0x0530, 0x0602, 0x0622, 0x1400, 809 }; 810 811 uint32_t tmp; 812 int i, tries; 813 uint32_t paddr; 814 uint32_t chunksz; 815 audigyls_port_t *port; 816 817 818 /* Set the orange jack to be analog out or S/PDIF */ 819 select_digital_enable(dev, dev->digital_enable); 820 821 /* 822 * In P17, there's 8 GPIO pins. 823 * GPIO register: 0x00XXYYZZ 824 * XX: Configure GPIO to be either GPI (0) or GPO (1). 825 * YY: GPO values, applicable if the pin is configure to be GPO. 826 * ZZ: GPI values, applicable if the pin is configure to be GPI. 827 * 828 * in SB570, pin 0-4 and 6 is used as GPO and pin 5 and 7 is 829 * used as GPI. 830 * 831 * GPO0: 832 * 1 ==> Analog output 833 * 0 ==> Digital output 834 * GPO1: 835 * 1 ==> Enable output on card 836 * 0 ==> Disable output on card 837 * GPO2: 838 * 1 ==> Enable Mic Bias and Mic Path 839 * 0 ==> Disable Mic Bias and Mic Path 840 * GPO3: 841 * 1 ==> Disable SPDIF-IO output 842 * 0 ==> Enable SPDIF-IO output 843 * GPO4 and GPO6: 844 * DAC sampling rate selection: 845 * Not applicable to SB570 since DAC is controlled through SPI 846 * GPI5: 847 * 1 ==> Front Panel is not connected 848 * 0 ==> Front Panel is connected 849 * GPI7: 850 * 1 ==> Front Panel Headphone is not connected 851 * 0 ==> Front Panel Headphone is connected 852 */ 853 if (dev->ac97) 854 OUTL(dev, GPIO, 0x005f03a3); 855 else { 856 /* for SBLive 7.1 */ 857 OUTL(dev, GPIO, 0x005f4301); 858 859 audigyls_i2c_write(dev, 0x15, 0x2); 860 tries = 0; 861 again: 862 for (i = 0; i < sizeof (spi_dac); i++) { 863 if (!audigyls_spi_write(dev, spi_dac[i]) && 864 tries < 100) { 865 tries++; 866 goto again; 867 } 868 } 869 } 870 871 OUTL(dev, IER, INTR_PCI); 872 OUTL(dev, HC, 0x00000009); /* Enable audio, use 48 kHz */ 873 874 tmp = read_chan(dev, SRCTL, 0); 875 if (dev->ac97) 876 tmp |= 0xf0c81000; /* Record src0/src1 from ac97 */ 877 else 878 tmp |= 0x50c81000; /* Record src0/src1 from I2SIN */ 879 tmp &= ~0x0303c00f; /* Set sample rates to 48 kHz */ 880 write_chan(dev, SRCTL, 0, tmp); 881 882 write_reg(dev, HMIXMAP_I2S, 0x76543210); /* Default out route */ 883 write_reg(dev, AUDCTL, 0x0f0f003f); /* Enable all outputs */ 884 885 /* All audio stopped! */ 886 write_reg(dev, SA, 0); 887 888 for (i = 0; i < 4; i++) { 889 /* 890 * Reset DMA pointers and counters. Note that we do 891 * not use scatter/gather. 892 */ 893 write_chan(dev, PTBA, i, 0); 894 write_chan(dev, PTBS, i, 0); 895 write_chan(dev, PTCA, i, 0); 896 897 write_chan(dev, CPFA, i, 0); 898 write_chan(dev, PFEA, i, 0); 899 write_chan(dev, CPCAV, i, 0); 900 901 write_chan(dev, CRFA, i, 0); 902 write_chan(dev, CRCAV, i, 0); 903 } 904 905 /* 906 * The 5.1 play port made up channels 0, 1, and 3. The record 907 * port is channel 2. 908 */ 909 port = dev->port[AUDIGYLS_PLAY_PORT]; 910 paddr = port->buf_paddr; 911 chunksz = port->buf_frames * 4; 912 write_chan(dev, PFBA, 0, paddr); 913 write_chan(dev, PFBS, 0, chunksz << 16); 914 paddr += chunksz; 915 write_chan(dev, PFBA, 1, paddr); 916 write_chan(dev, PFBS, 1, chunksz << 16); 917 paddr += chunksz; 918 write_chan(dev, PFBA, 3, paddr); 919 write_chan(dev, PFBS, 3, chunksz << 16); 920 921 /* Record */ 922 port = dev->port[AUDIGYLS_REC_PORT]; 923 paddr = port->buf_paddr; 924 chunksz = port->buf_frames * 4; 925 write_chan(dev, RFBA, 2, paddr); 926 write_chan(dev, RFBS, 2, chunksz << 16); 927 928 /* Set sample rates to 48 kHz. */ 929 tmp = read_chan(dev, SRCTL, 0) & ~0x0303c00f; 930 write_chan(dev, SRCTL, 0, tmp); 931 932 write_reg(dev, SCS0, 0x02108004); /* Audio */ 933 write_reg(dev, SCS1, 0x02108004); /* Audio */ 934 write_reg(dev, SCS2, 0x02108004); /* Audio */ 935 write_reg(dev, SCS3, 0x02108004); /* Audio */ 936 } 937 938 #define PLAYCTL (AUDIO_CTRL_FLAG_RW | AUDIO_CTRL_FLAG_PLAY) 939 #define RECCTL (AUDIO_CTRL_FLAG_RW | AUDIO_CTRL_FLAG_REC) 940 #define MONCTL (AUDIO_CTRL_FLAG_RW | AUDIO_CTRL_FLAG_MONITOR) 941 #define PCMVOL (PLAYCTL | AUDIO_CTRL_FLAG_PCMVOL) 942 #define MAINVOL (PLAYCTL | AUDIO_CTRL_FLAG_MAINVOL) 943 #define RECVOL (RECCTL | AUDIO_CTRL_FLAG_RECVOL) 944 #define MONVOL (MONCTL | AUDIO_CTRL_FLAG_MONVOL) 945 946 #define MASK(nbits) ((1 << (nbits)) - 1) 947 #define SCALE(val, nbits) \ 948 ((uint8_t)((((val) * MASK(nbits)) / 100)) << (8 - (nbits))) 949 950 static uint32_t 951 audigyls_stereo_scale(uint32_t value, uint8_t bits) 952 { 953 uint8_t left, right; 954 uint32_t val; 955 956 left = (value >> 8) & 0xff; 957 right = value & 0xff; 958 959 val = (((left * ((1 << bits) - 1) / 100) << 8) | 960 (right * ((1 << bits) - 1) / 100)); 961 return (val); 962 } 963 964 static void 965 audigyls_configure_mixer(audigyls_dev_t *dev) 966 { 967 unsigned int r, v1, v2; 968 969 /* output items */ 970 /* front */ 971 r = 0xffff - audigyls_stereo_scale(dev->controls[CTL_FRONT].val, 8); 972 r = (r << 16) | r; 973 write_chan(dev, MIXVOL_I2S, 0, r); 974 975 /* surround */ 976 r = 0xffff - audigyls_stereo_scale(dev->controls[CTL_SURROUND].val, 8); 977 r = (r << 16) | r; 978 write_chan(dev, MIXVOL_I2S, 3, r); 979 980 /* center/lfe */ 981 v1 = 255 - SCALE(dev->controls[CTL_CENTER].val, 8); 982 v2 = 255 - SCALE(dev->controls[CTL_LFE].val, 8); 983 r = (v1 << 8) | v2; 984 r = (r << 16) | r; 985 write_chan(dev, MIXVOL_I2S, 1, r); 986 987 /* spread */ 988 r = dev->controls[CTL_SPREAD].val ? 0x10101010 : 0x76543210; 989 write_reg(dev, HMIXMAP_I2S, r); 990 991 /* input items */ 992 993 /* recgain */ 994 v1 = dev->controls[CTL_RECORDVOL].val; 995 if (dev->ac97_recgain && !dev->controls[CTL_LOOP].val) { 996 /* 997 * For AC'97, we use the AC'97 record gain, unless we are 998 * in loopback. 999 */ 1000 (void) ac97_control_set(dev->ac97_recgain, v1); 1001 write_reg(dev, P17RECVOLL, 0x30303030); 1002 write_reg(dev, P17RECVOLH, 0x30303030); 1003 } else { 1004 /* 1005 * Otherwise we set the P17 gain. 1006 */ 1007 r = 0xffff - audigyls_stereo_scale(v1, 8); 1008 r = r << 16 | r; 1009 write_reg(dev, P17RECVOLL, r); 1010 write_reg(dev, P17RECVOLH, r); 1011 } 1012 1013 /* monitor gain */ 1014 if (dev->ac97) { 1015 /* AC'97 monitor gain is done by the AC'97 codec */ 1016 write_chan(dev, SRCTL, 1, 0x30303030); 1017 write_reg(dev, SMIXMAP_I2S, 0x10101076); 1018 } else { 1019 /* For non-AC'97 devices, just a single master monitor gain */ 1020 r = 255 - SCALE(dev->controls[CTL_MONGAIN].val, 8); 1021 write_chan(dev, SRCTL, 1, 0xffff0000 | r << 8 | r); 1022 if (r != 0xff) { 1023 write_reg(dev, SMIXMAP_I2S, 0x10101076); 1024 } else { 1025 write_reg(dev, SMIXMAP_I2S, 0x10101010); 1026 } 1027 } 1028 1029 /* record source */ 1030 if (dev->ac97_recsrc != NULL) { 1031 (void) ac97_control_set(dev->ac97_recsrc, 1032 dev->controls[CTL_RECSRC].val); 1033 v1 = RECSEL_AC97; /* Audigy LS */ 1034 } else { 1035 switch (dev->controls[CTL_RECSRC].val) { 1036 case 1: 1037 audigyls_i2c_write(dev, 0x15, 0x2); /* Mic */ 1038 OUTL(dev, GPIO, INL(dev, GPIO) | 0x400); 1039 break; 1040 1041 case 2: 1042 audigyls_i2c_write(dev, 0x15, 0x4); /* Line */ 1043 OUTL(dev, GPIO, INL(dev, GPIO) & ~0x400); 1044 break; 1045 } 1046 v1 = RECSEL_I2SIN; /* SB 7.1 value */ 1047 } 1048 1049 /* If loopback, record what you hear instead */ 1050 1051 if (dev->controls[CTL_LOOP].val) { 1052 r = 0; 1053 v1 = RECSEL_I2SOUT; 1054 r |= (v1 << 28) | (v1 << 24) | (v1 << 20) | (v1 << 16) | v2; 1055 } else { 1056 /* 1057 * You'd think this would be the same as the logic 1058 * above, but experience shows that what you need for 1059 * loopback is different. This whole thing looks 1060 * particularly fishy to me. I suspect someone has 1061 * made a mistake somewhere. But I can't seem to 1062 * figure out where it lies. 1063 */ 1064 if (dev->ac97_recsrc != NULL) { 1065 r = 0xe4; 1066 for (int i = 0; i < 4; i++) 1067 r |= v1 << (16 + i * 3); /* Select input */ 1068 } else { 1069 r = (v1 << 28) | (v1 << 24) | (v1 << 20) | (v1 << 16) | 1070 v1; 1071 } 1072 } 1073 1074 write_reg(dev, P17RECSEL, r); 1075 } 1076 1077 static int 1078 audigyls_set_control(void *arg, uint64_t val) 1079 { 1080 audigyls_ctrl_t *pc = arg; 1081 audigyls_dev_t *dev = pc->dev; 1082 1083 switch (pc->num) { 1084 1085 case CTL_FRONT: 1086 case CTL_SURROUND: 1087 case CTL_RECORDVOL: 1088 if (((val & 0xff) > 100) || 1089 (((val & 0xff00) >> 8) > 100) || 1090 ((val & ~0xffff) != 0)) { 1091 return (EINVAL); 1092 } 1093 break; 1094 1095 case CTL_CENTER: 1096 case CTL_LFE: 1097 case CTL_MONGAIN: 1098 if (val > 100) { 1099 return (EINVAL); 1100 } 1101 break; 1102 1103 case CTL_RECSRC: 1104 if (((1U << val) & (dev->recmask)) == 0) { 1105 return (EINVAL); 1106 } 1107 break; 1108 1109 case CTL_SPREAD: 1110 case CTL_LOOP: 1111 switch (val) { 1112 case 0: 1113 case 1: 1114 break; 1115 default: 1116 return (EINVAL); 1117 } 1118 } 1119 1120 mutex_enter(&dev->mutex); 1121 pc->val = val; 1122 if (!dev->suspended) { 1123 audigyls_configure_mixer(dev); 1124 } 1125 mutex_exit(&dev->mutex); 1126 1127 return (0); 1128 } 1129 1130 static int 1131 audigyls_get_control(void *arg, uint64_t *val) 1132 { 1133 audigyls_ctrl_t *pc = arg; 1134 audigyls_dev_t *dev = pc->dev; 1135 1136 mutex_enter(&dev->mutex); 1137 *val = pc->val; 1138 mutex_exit(&dev->mutex); 1139 return (0); 1140 } 1141 1142 static void 1143 audigyls_alloc_ctrl(audigyls_dev_t *dev, uint32_t num, uint64_t val) 1144 { 1145 audio_ctrl_desc_t desc; 1146 audigyls_ctrl_t *pc; 1147 1148 bzero(&desc, sizeof (desc)); 1149 1150 pc = &dev->controls[num]; 1151 pc->num = num; 1152 pc->dev = dev; 1153 1154 1155 switch (num) { 1156 case CTL_FRONT: 1157 desc.acd_name = AUDIO_CTRL_ID_FRONT; 1158 desc.acd_type = AUDIO_CTRL_TYPE_STEREO; 1159 desc.acd_minvalue = 0; 1160 desc.acd_maxvalue = 100; 1161 desc.acd_flags = MAINVOL; 1162 break; 1163 1164 case CTL_SURROUND: 1165 desc.acd_name = AUDIO_CTRL_ID_SURROUND; 1166 desc.acd_type = AUDIO_CTRL_TYPE_STEREO; 1167 desc.acd_minvalue = 0; 1168 desc.acd_maxvalue = 100; 1169 desc.acd_flags = MAINVOL; 1170 break; 1171 1172 case CTL_CENTER: 1173 desc.acd_name = AUDIO_CTRL_ID_CENTER; 1174 desc.acd_type = AUDIO_CTRL_TYPE_MONO; 1175 desc.acd_minvalue = 0; 1176 desc.acd_maxvalue = 100; 1177 desc.acd_flags = MAINVOL; 1178 break; 1179 1180 case CTL_LFE: 1181 desc.acd_name = AUDIO_CTRL_ID_LFE; 1182 desc.acd_type = AUDIO_CTRL_TYPE_MONO; 1183 desc.acd_minvalue = 0; 1184 desc.acd_maxvalue = 100; 1185 desc.acd_flags = MAINVOL; 1186 break; 1187 1188 case CTL_RECORDVOL: 1189 desc.acd_name = AUDIO_CTRL_ID_RECGAIN; 1190 desc.acd_type = AUDIO_CTRL_TYPE_STEREO; 1191 desc.acd_minvalue = 0; 1192 desc.acd_maxvalue = 100; 1193 desc.acd_flags = RECVOL; 1194 break; 1195 1196 case CTL_RECSRC: 1197 desc.acd_name = AUDIO_CTRL_ID_RECSRC; 1198 desc.acd_type = AUDIO_CTRL_TYPE_ENUM; 1199 desc.acd_flags = RECCTL; 1200 1201 /* 1202 * For AC'97 devices, we want to expose the reasonable 1203 * AC'97 input sources, but suppress the stereomix, 1204 * because we use loopback instead. 1205 */ 1206 if (dev->ac97_recsrc) { 1207 int i, j; 1208 const char *n; 1209 const audio_ctrl_desc_t *adp; 1210 1211 adp = ac97_control_desc(dev->ac97_recsrc); 1212 for (i = 0; i < 64; i++) { 1213 n = adp->acd_enum[i]; 1214 1215 if (((adp->acd_minvalue & (1 << i)) == 0) || 1216 (n == NULL)) { 1217 continue; 1218 } 1219 for (j = 0; audigyls_badsrcs[j]; j++) { 1220 if (strcmp(n, audigyls_badsrcs[j]) 1221 == 0) { 1222 n = NULL; 1223 break; 1224 } 1225 } 1226 if (n) { 1227 desc.acd_enum[i] = n; 1228 dev->recmask |= (1 << i); 1229 } 1230 } 1231 desc.acd_minvalue = desc.acd_maxvalue = dev->recmask; 1232 } else { 1233 dev->recmask = 3; 1234 desc.acd_minvalue = 3; 1235 desc.acd_maxvalue = 3; 1236 desc.acd_enum[0] = AUDIO_PORT_MIC; 1237 desc.acd_enum[1] = AUDIO_PORT_LINEIN; 1238 } 1239 break; 1240 1241 case CTL_MONGAIN: 1242 ASSERT(!dev->ac97); 1243 desc.acd_name = AUDIO_CTRL_ID_MONGAIN; 1244 desc.acd_type = AUDIO_CTRL_TYPE_MONO; 1245 desc.acd_minvalue = 0; 1246 desc.acd_maxvalue = 100; 1247 desc.acd_flags = MONVOL; 1248 break; 1249 1250 case CTL_SPREAD: 1251 desc.acd_name = AUDIO_CTRL_ID_SPREAD; 1252 desc.acd_type = AUDIO_CTRL_TYPE_BOOLEAN; 1253 desc.acd_minvalue = 0; 1254 desc.acd_maxvalue = 1; 1255 desc.acd_flags = PLAYCTL; 1256 break; 1257 1258 case CTL_LOOP: 1259 desc.acd_name = AUDIO_CTRL_ID_LOOPBACK; 1260 desc.acd_type = AUDIO_CTRL_TYPE_BOOLEAN; 1261 desc.acd_minvalue = 0; 1262 desc.acd_maxvalue = 1; 1263 desc.acd_flags = RECCTL; 1264 break; 1265 } 1266 1267 pc->val = val; 1268 pc->ctrl = audio_dev_add_control(dev->adev, &desc, 1269 audigyls_get_control, audigyls_set_control, pc); 1270 } 1271 1272 static void 1273 audigyls_add_controls(audigyls_dev_t *dev) 1274 { 1275 (void) audio_dev_add_soft_volume(dev->adev); 1276 1277 audigyls_alloc_ctrl(dev, CTL_FRONT, 75 | (75 << 8)); 1278 audigyls_alloc_ctrl(dev, CTL_SURROUND, 75 | (75 << 8)); 1279 audigyls_alloc_ctrl(dev, CTL_CENTER, 75); 1280 audigyls_alloc_ctrl(dev, CTL_LFE, 75); 1281 audigyls_alloc_ctrl(dev, CTL_RECORDVOL, 75 | (75 << 8)); 1282 audigyls_alloc_ctrl(dev, CTL_RECSRC, 1); 1283 audigyls_alloc_ctrl(dev, CTL_SPREAD, 0); 1284 audigyls_alloc_ctrl(dev, CTL_LOOP, 0); 1285 if (!dev->ac97) { 1286 audigyls_alloc_ctrl(dev, CTL_MONGAIN, 0); 1287 } 1288 } 1289 1290 int 1291 audigyls_attach(dev_info_t *dip) 1292 { 1293 uint16_t pci_command, vendor, device; 1294 uint32_t subdevice; 1295 audigyls_dev_t *dev; 1296 ddi_acc_handle_t pcih; 1297 const char *name, *version; 1298 boolean_t ac97 = B_FALSE; 1299 1300 dev = kmem_zalloc(sizeof (*dev), KM_SLEEP); 1301 dev->dip = dip; 1302 ddi_set_driver_private(dip, dev); 1303 1304 if ((dev->adev = audio_dev_alloc(dip, 0)) == NULL) { 1305 cmn_err(CE_WARN, "audio_dev_alloc failed"); 1306 goto error; 1307 } 1308 1309 if (pci_config_setup(dip, &pcih) != DDI_SUCCESS) { 1310 audio_dev_warn(dev->adev, "pci_config_setup failed"); 1311 goto error; 1312 } 1313 dev->pcih = pcih; 1314 1315 vendor = pci_config_get16(pcih, PCI_CONF_VENID); 1316 device = pci_config_get16(pcih, PCI_CONF_DEVID); 1317 subdevice = pci_config_get16(pcih, PCI_CONF_SUBVENID); 1318 subdevice <<= 16; 1319 subdevice |= pci_config_get16(pcih, PCI_CONF_SUBSYSID); 1320 if (vendor != PCI_VENDOR_ID_CREATIVE || 1321 device != PCI_DEVICE_ID_CREATIVE_AUDIGYLS) { 1322 audio_dev_warn(dev->adev, "Hardware not recognized " 1323 "(vendor=%x, dev=%x)", vendor, device); 1324 goto error; 1325 } 1326 1327 pci_command = pci_config_get16(pcih, PCI_CONF_COMM); 1328 pci_command |= PCI_COMM_ME | PCI_COMM_IO; 1329 pci_config_put16(pcih, PCI_CONF_COMM, pci_command); 1330 1331 if ((ddi_regs_map_setup(dip, 1, &dev->base, 0, 0, &dev_attr, 1332 &dev->regsh)) != DDI_SUCCESS) { 1333 audio_dev_warn(dev->adev, "failed to map registers"); 1334 goto error; 1335 } 1336 1337 /* Function of the orange jack: 0=analog, 1=digital */ 1338 dev->digital_enable = ddi_prop_get_int(DDI_DEV_T_ANY, dev->dip, 1339 DDI_PROP_DONTPASS, "digital-enable", 0); 1340 1341 if (audigyls_setup_intrs(dev) != DDI_SUCCESS) 1342 goto error; 1343 1344 dev->intrs = ddi_prop_get_int(DDI_DEV_T_ANY, dev->dip, 1345 DDI_PROP_DONTPASS, "interrupt-rate", AUDIGYLS_INTRS); 1346 1347 /* make sure the values are good */ 1348 if (dev->intrs < AUDIGYLS_MIN_INTRS) { 1349 audio_dev_warn(dev->adev, 1350 "interrupt-rate too low, %d, reset to %d", 1351 dev->intrs, AUDIGYLS_INTRS); 1352 dev->intrs = AUDIGYLS_INTRS; 1353 } else if (dev->intrs > AUDIGYLS_MAX_INTRS) { 1354 audio_dev_warn(dev->adev, 1355 "interrupt-rate too high, %d, reset to %d", 1356 dev->intrs, AUDIGYLS_INTRS); 1357 dev->intrs = AUDIGYLS_INTRS; 1358 } 1359 1360 dev->timer = (192000 / dev->intrs) << 16; 1361 1362 switch (subdevice) { 1363 case 0x11021001: /* SB0310 */ 1364 case 0x11021002: /* SB0310 */ 1365 case 0x11021005: /* SB0310b */ 1366 name = "Creative Audigy LS"; 1367 version = "SB0310"; /* could also be SB0312 */ 1368 ac97 = B_TRUE; 1369 break; 1370 case 0x11021006: 1371 name = "Creative Sound Blaster Live! 24 bit"; 1372 version = "SB0410"; 1373 break; 1374 case 0x11021007: /* Dell OEM version */ 1375 name = "Creative Sound Blaster Live! 24 bit"; 1376 version = "SB0413"; 1377 break; 1378 case 0x1102100a: 1379 name = "Creative Audigy SE"; 1380 version = "SB0570"; 1381 break; 1382 case 0x11021011: 1383 name = "Creative Audigy SE OEM"; 1384 version = "SB0570a"; 1385 break; 1386 case 0x11021012: 1387 name = "Creative X-Fi Extreme Audio"; 1388 version = "SB0790"; 1389 break; 1390 case 0x14621009: 1391 name = "MSI K8N Diamond MB"; 1392 version = "SB0438"; 1393 break; 1394 case 0x12973038: 1395 name = "Shuttle XPC SD31P"; 1396 version = "SD31P"; 1397 break; 1398 case 0x12973041: 1399 name = "Shuttle XPC SD11G5"; 1400 version = "SD11G5"; 1401 break; 1402 default: 1403 name = "Creative Audigy LS"; 1404 version = NULL; 1405 break; 1406 } 1407 1408 audio_dev_set_description(dev->adev, name); 1409 if (version) 1410 audio_dev_set_version(dev->adev, version); 1411 1412 if (ac97) { 1413 ac97_ctrl_t *ctrl; 1414 1415 /* Original Audigy LS revision (AC97 based) */ 1416 dev->ac97 = ac97_allocate(dev->adev, dip, 1417 audigyls_read_ac97, audigyls_write_ac97, dev); 1418 if (dev->ac97 == NULL) { 1419 audio_dev_warn(dev->adev, 1420 "failed to allocate ac97 handle"); 1421 goto error; 1422 } 1423 1424 ac97_probe_controls(dev->ac97); 1425 1426 /* remove the AC'97 controls we don't want to expose */ 1427 for (int i = 0; audigyls_remove_ac97[i]; i++) { 1428 ctrl = ac97_control_find(dev->ac97, 1429 audigyls_remove_ac97[i]); 1430 if (ctrl != NULL) { 1431 ac97_control_unregister(ctrl); 1432 } 1433 } 1434 1435 dev->ac97_recgain = ac97_control_find(dev->ac97, 1436 AUDIO_CTRL_ID_RECGAIN); 1437 dev->ac97_recsrc = ac97_control_find(dev->ac97, 1438 AUDIO_CTRL_ID_RECSRC); 1439 } 1440 1441 audigyls_add_controls(dev); 1442 1443 if (dev->ac97) { 1444 ac97_register_controls(dev->ac97); 1445 } 1446 1447 if (audigyls_alloc_port(dev, AUDIGYLS_PLAY_PORT) != DDI_SUCCESS) 1448 goto error; 1449 if (audigyls_alloc_port(dev, AUDIGYLS_REC_PORT) != DDI_SUCCESS) 1450 goto error; 1451 1452 audigyls_hwinit(dev); 1453 1454 audigyls_configure_mixer(dev); 1455 1456 /* set up kernel statistics */ 1457 if ((dev->ksp = kstat_create(AUDIGYLS_NAME, ddi_get_instance(dip), 1458 AUDIGYLS_NAME, "controller", KSTAT_TYPE_INTR, 1, 1459 KSTAT_FLAG_PERSISTENT)) != NULL) { 1460 kstat_install(dev->ksp); 1461 } 1462 1463 if (audio_dev_register(dev->adev) != DDI_SUCCESS) { 1464 audio_dev_warn(dev->adev, "unable to register with framework"); 1465 goto error; 1466 } 1467 1468 (void) ddi_intr_enable(dev->ih); 1469 ddi_report_dev(dip); 1470 1471 return (DDI_SUCCESS); 1472 1473 error: 1474 audigyls_destroy(dev); 1475 return (DDI_FAILURE); 1476 } 1477 1478 int 1479 audigyls_resume(dev_info_t *dip) 1480 { 1481 audigyls_dev_t *dev; 1482 audigyls_port_t *port; 1483 1484 dev = ddi_get_driver_private(dip); 1485 1486 for (int i = 0; i < AUDIGYLS_NUM_PORT; i++) { 1487 port = dev->port[i]; 1488 audio_engine_reset(port->engine); 1489 } 1490 1491 audigyls_hwinit(dev); 1492 1493 /* allow ac97 operations again */ 1494 if (dev->ac97) 1495 ac97_resume(dev->ac97); 1496 1497 audigyls_configure_mixer(dev); 1498 1499 mutex_enter(&dev->mutex); 1500 dev->suspended = B_FALSE; 1501 1502 for (int i = 0; i < AUDIGYLS_NUM_PORT; i++) { 1503 1504 port = dev->port[i]; 1505 1506 audigyls_reset_port(port); 1507 1508 if (port->started) { 1509 audigyls_start_port(port); 1510 } 1511 } 1512 1513 mutex_exit(&dev->mutex); 1514 return (DDI_SUCCESS); 1515 } 1516 1517 int 1518 audigyls_detach(audigyls_dev_t *dev) 1519 { 1520 if (audio_dev_unregister(dev->adev) != DDI_SUCCESS) 1521 return (DDI_FAILURE); 1522 1523 audigyls_destroy(dev); 1524 return (DDI_SUCCESS); 1525 } 1526 1527 int 1528 audigyls_suspend(audigyls_dev_t *dev) 1529 { 1530 if (dev->ac97) 1531 ac97_suspend(dev->ac97); 1532 1533 mutex_enter(&dev->mutex); 1534 for (int i = 0; i < AUDIGYLS_NUM_PORT; i++) { 1535 1536 audigyls_port_t *port = dev->port[i]; 1537 audigyls_stop_port(port); 1538 } 1539 dev->suspended = B_TRUE; 1540 mutex_exit(&dev->mutex); 1541 return (DDI_SUCCESS); 1542 } 1543 1544 static int audigyls_ddi_attach(dev_info_t *, ddi_attach_cmd_t); 1545 static int audigyls_ddi_detach(dev_info_t *, ddi_detach_cmd_t); 1546 static int audigyls_ddi_quiesce(dev_info_t *); 1547 1548 static struct dev_ops audigyls_dev_ops = { 1549 DEVO_REV, /* rev */ 1550 0, /* refcnt */ 1551 NULL, /* getinfo */ 1552 nulldev, /* identify */ 1553 nulldev, /* probe */ 1554 audigyls_ddi_attach, /* attach */ 1555 audigyls_ddi_detach, /* detach */ 1556 nodev, /* reset */ 1557 NULL, /* cb_ops */ 1558 NULL, /* bus_ops */ 1559 NULL, /* power */ 1560 audigyls_ddi_quiesce, /* quiesce */ 1561 }; 1562 1563 static struct modldrv audigyls_modldrv = { 1564 &mod_driverops, /* drv_modops */ 1565 "Creative Audigy LS Audio", /* linkinfo */ 1566 &audigyls_dev_ops, /* dev_ops */ 1567 }; 1568 1569 static struct modlinkage modlinkage = { 1570 MODREV_1, 1571 { &audigyls_modldrv, NULL } 1572 }; 1573 1574 int 1575 _init(void) 1576 { 1577 int rv; 1578 1579 audio_init_ops(&audigyls_dev_ops, AUDIGYLS_NAME); 1580 if ((rv = mod_install(&modlinkage)) != 0) { 1581 audio_fini_ops(&audigyls_dev_ops); 1582 } 1583 return (rv); 1584 } 1585 1586 int 1587 _fini(void) 1588 { 1589 int rv; 1590 1591 if ((rv = mod_remove(&modlinkage)) == 0) { 1592 audio_fini_ops(&audigyls_dev_ops); 1593 } 1594 return (rv); 1595 } 1596 1597 int 1598 _info(struct modinfo *modinfop) 1599 { 1600 return (mod_info(&modlinkage, modinfop)); 1601 } 1602 1603 int 1604 audigyls_ddi_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 1605 { 1606 switch (cmd) { 1607 case DDI_ATTACH: 1608 return (audigyls_attach(dip)); 1609 1610 case DDI_RESUME: 1611 return (audigyls_resume(dip)); 1612 1613 default: 1614 return (DDI_FAILURE); 1615 } 1616 } 1617 1618 int 1619 audigyls_ddi_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 1620 { 1621 audigyls_dev_t *dev; 1622 1623 dev = ddi_get_driver_private(dip); 1624 1625 switch (cmd) { 1626 case DDI_DETACH: 1627 return (audigyls_detach(dev)); 1628 1629 case DDI_SUSPEND: 1630 return (audigyls_suspend(dev)); 1631 1632 default: 1633 return (DDI_FAILURE); 1634 } 1635 } 1636 1637 int 1638 audigyls_ddi_quiesce(dev_info_t *dip) 1639 { 1640 audigyls_dev_t *dev; 1641 uint32_t status; 1642 1643 dev = ddi_get_driver_private(dip); 1644 1645 for (int i = 0; i < AUDIGYLS_NUM_PORT; i++) { 1646 1647 audigyls_port_t *port = dev->port[i]; 1648 audigyls_stop_port(port); 1649 } 1650 1651 /* 1652 * Turn off the hardware 1653 */ 1654 1655 write_reg(dev, SA, 0); 1656 OUTL(dev, IER, 0); /* Interrupt disable */ 1657 write_reg(dev, AIE, 0); /* Disable audio interrupts */ 1658 status = INL(dev, IPR); 1659 OUTL(dev, IPR, status); /* Acknowledge */ 1660 return (DDI_SUCCESS); 1661 } 1662