1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 /* 28 * Purpose: Driver for the Creative Audigy LS sound card 29 */ 30 /* 31 * 32 * Copyright (C) 4Front Technologies 1996-2009. 33 */ 34 35 #include <sys/types.h> 36 #include <sys/modctl.h> 37 #include <sys/kmem.h> 38 #include <sys/conf.h> 39 #include <sys/ddi.h> 40 #include <sys/sunddi.h> 41 #include <sys/pci.h> 42 #include <sys/note.h> 43 #include <sys/audio/audio_driver.h> 44 #include <sys/audio/ac97.h> 45 46 #include "audiols.h" 47 48 static struct ddi_device_acc_attr dev_attr = { 49 DDI_DEVICE_ATTR_V0, 50 DDI_STRUCTURE_LE_ACC, 51 DDI_STRICTORDER_ACC 52 }; 53 54 static struct ddi_device_acc_attr buf_attr = { 55 DDI_DEVICE_ATTR_V0, 56 DDI_NEVERSWAP_ACC, 57 DDI_STRICTORDER_ACC 58 }; 59 60 static ddi_dma_attr_t dma_attr_buf = { 61 DMA_ATTR_V0, /* version number */ 62 0x00000000, /* low DMA address range */ 63 0xffffffff, /* high DMA address range */ 64 0x000fffff, /* DMA counter (16 bits only in Audigy LS) */ 65 4, /* DMA address alignment */ 66 0x3c, /* DMA burstsizes */ 67 4, /* min effective DMA size */ 68 0xffffffff, /* max DMA xfer size */ 69 0xffffffff, /* segment boundary */ 70 1, /* s/g length */ 71 4, /* granularity of device */ 72 0 /* Bus specific DMA flags */ 73 }; 74 75 static int audigyls_attach(dev_info_t *); 76 static int audigyls_resume(dev_info_t *); 77 static int audigyls_detach(audigyls_dev_t *); 78 static int audigyls_suspend(audigyls_dev_t *); 79 80 static int audigyls_open(void *, int, unsigned *, unsigned *, caddr_t *); 81 static void audigyls_close(void *); 82 static int audigyls_start(void *); 83 static void audigyls_stop(void *); 84 static int audigyls_format(void *); 85 static int audigyls_channels(void *); 86 static int audigyls_rate(void *); 87 static uint64_t audigyls_count(void *); 88 static void audigyls_sync(void *, unsigned); 89 static size_t audigyls_qlen(void *); 90 static void audigyls_chinfo(void *, int, unsigned *, unsigned *); 91 92 93 static uint16_t audigyls_read_ac97(void *, uint8_t); 94 static void audigyls_write_ac97(void *, uint8_t, uint16_t); 95 static int audigyls_alloc_port(audigyls_dev_t *, int); 96 static void audigyls_start_port(audigyls_port_t *); 97 static void audigyls_stop_port(audigyls_port_t *); 98 static void audigyls_update_port(audigyls_port_t *); 99 static void audigyls_reset_port(audigyls_port_t *); 100 static void audigyls_destroy(audigyls_dev_t *); 101 static int audigyls_setup_intrs(audigyls_dev_t *); 102 static void audigyls_hwinit(audigyls_dev_t *); 103 static uint_t audigyls_intr(caddr_t, caddr_t); 104 static void audigyls_configure_mixer(audigyls_dev_t *dev); 105 106 static audio_engine_ops_t audigyls_engine_ops = { 107 AUDIO_ENGINE_VERSION, 108 audigyls_open, 109 audigyls_close, 110 audigyls_start, 111 audigyls_stop, 112 audigyls_count, 113 audigyls_format, 114 audigyls_channels, 115 audigyls_rate, 116 audigyls_sync, 117 audigyls_qlen, 118 audigyls_chinfo 119 }; 120 121 /* 122 * Audigy LS uses AC'97 strictly for the recording side of things. 123 * While the chip can supposedly route output to AC'97 for playback, 124 * the PCI devices use a separate I2S DAC instead. As a result we 125 * need to suppress controls that the AC'97 codec registers. 126 * 127 * Furthermore, even then the AC'97 codec offers inputs that we just 128 * aren't interested in. 129 */ 130 const char *audigyls_remove_ac97[] = { 131 AUDIO_CTRL_ID_VOLUME, 132 AUDIO_CTRL_ID_LINEOUT, 133 AUDIO_CTRL_ID_HEADPHONE, 134 AUDIO_CTRL_ID_CD, 135 AUDIO_CTRL_ID_VIDEO, 136 AUDIO_CTRL_ID_3DDEPTH, 137 AUDIO_CTRL_ID_3DENHANCE, 138 AUDIO_CTRL_ID_BEEP, 139 AUDIO_CTRL_ID_RECGAIN, 140 AUDIO_CTRL_ID_RECSRC, 141 AUDIO_CTRL_ID_LOOPBACK, 142 NULL, 143 }; 144 145 /* 146 * AC'97 sources we don't want to expose. 147 */ 148 const char *audigyls_badsrcs[] = { 149 AUDIO_PORT_VIDEO, 150 AUDIO_PORT_CD, 151 AUDIO_PORT_STEREOMIX, 152 AUDIO_PORT_MONOMIX, 153 NULL, 154 }; 155 156 static unsigned int 157 read_chan(audigyls_dev_t *dev, int reg, int chn) 158 { 159 uint32_t val; 160 161 mutex_enter(&dev->low_mutex); 162 /* Pointer */ 163 OUTL(dev, PR, (reg << 16) | (chn & 0xffff)); 164 /* Data */ 165 val = INL(dev, DR); 166 mutex_exit(&dev->low_mutex); 167 168 return (val); 169 } 170 171 static void 172 write_chan(audigyls_dev_t *dev, int reg, int chn, uint32_t value) 173 { 174 mutex_enter(&dev->low_mutex); 175 /* Pointer */ 176 OUTL(dev, PR, (reg << 16) | (chn & 0x7)); 177 /* Data */ 178 OUTL(dev, DR, value); 179 mutex_exit(&dev->low_mutex); 180 } 181 182 static unsigned int 183 read_reg(audigyls_dev_t *dev, int reg) 184 { 185 return (read_chan(dev, reg, 0)); 186 } 187 188 static void 189 write_reg(audigyls_dev_t *dev, int reg, uint32_t value) 190 { 191 write_chan(dev, reg, 0, value); 192 } 193 194 195 static uint16_t 196 audigyls_read_ac97(void *arg, uint8_t index) 197 { 198 audigyls_dev_t *dev = arg; 199 uint16_t dtemp = 0; 200 int i; 201 202 mutex_enter(&dev->low_mutex); 203 OUTB(dev, AC97A, index); 204 for (i = 0; i < 10000; i++) { 205 if (INB(dev, AC97A) & 0x80) 206 break; 207 } 208 if (i == 10000) { /* Timeout */ 209 mutex_exit(&dev->low_mutex); 210 return (0xffff); 211 } 212 dtemp = INW(dev, AC97D); 213 mutex_exit(&dev->low_mutex); 214 215 return (dtemp); 216 } 217 218 static void 219 audigyls_write_ac97(void *arg, uint8_t index, uint16_t data) 220 { 221 audigyls_dev_t *dev = arg; 222 int i; 223 224 mutex_enter(&dev->low_mutex); 225 OUTB(dev, AC97A, index); 226 for (i = 0; i < 50000; i++) { 227 if (INB(dev, AC97A) & 0x80) 228 break; 229 } 230 if (i == 50000) { 231 mutex_exit(&dev->low_mutex); 232 return; 233 } 234 OUTW(dev, AC97D, data); 235 mutex_exit(&dev->low_mutex); 236 } 237 238 static void 239 select_digital_enable(audigyls_dev_t *dev, int mode) 240 { 241 /* 242 * Set the out3/spdif combo jack format. 243 * mode0=analog rear/center, 1=spdif 244 */ 245 246 if (mode == 0) { 247 write_reg(dev, SPC, 0x00000f00); 248 } else { 249 write_reg(dev, SPC, 0x0000000f); 250 } 251 } 252 253 /* only for SBLive 7.1 */ 254 void 255 audigyls_i2c_write(audigyls_dev_t *dev, int reg, int data) 256 { 257 int i, timeout, tmp; 258 259 tmp = (reg << 9 | data) << 16; /* set the upper 16 bits */ 260 /* first write the command to the data reg */ 261 write_reg(dev, I2C_1, tmp); 262 for (i = 0; i < 20; i++) { 263 tmp = read_reg(dev, I2C_A) & ~0x6fe; 264 /* see audigyls.pdf for bits */ 265 tmp |= 0x400 | 0x100 | 0x34; 266 write_reg(dev, I2C_A, tmp); 267 /* now wait till controller sets valid bit (0x100) to 0 */ 268 timeout = 0; 269 for (;;) { 270 tmp = read_reg(dev, I2C_A); 271 if ((tmp & 0x100) == 0) 272 break; 273 274 if (timeout > 100) 275 break; 276 277 timeout++; 278 } 279 280 /* transaction aborted */ 281 if (tmp & 0x200) 282 break; 283 } 284 } 285 286 int 287 audigyls_spi_write(audigyls_dev_t *dev, int data) 288 { 289 unsigned int orig; 290 unsigned int tmp; 291 int i, valid; 292 293 tmp = read_reg(dev, SPI); 294 orig = (tmp & ~0x3ffff) | 0x30000; 295 write_reg(dev, SPI, orig | data); 296 valid = 0; 297 /* Wait for status bit to return to 0 */ 298 for (i = 0; i < 1000; i++) { 299 drv_usecwait(100); 300 tmp = read_reg(dev, SPI); 301 if (!(tmp & 0x10000)) { 302 valid = 1; 303 break; 304 } 305 } 306 if (!valid) /* Timed out */ 307 return (0); 308 309 return (1); 310 } 311 312 static void 313 audigyls_update_port(audigyls_port_t *port) 314 { 315 audigyls_dev_t *dev = port->dev; 316 uint32_t offset, n; 317 318 if (dev->suspended) 319 return; 320 321 if (port->direction == AUDIGYLS_PLAY_PORT) { 322 offset = read_chan(dev, CPFA, 0); 323 } else { 324 offset = read_chan(dev, CRFA, 2); 325 } 326 327 328 /* get the offset, and switch to frames */ 329 offset /= (2 * sizeof (uint16_t)); 330 331 if (offset >= port->offset) { 332 n = offset - port->offset; 333 } else { 334 n = offset + (port->buf_frames - port->offset); 335 } 336 port->offset = offset; 337 port->count += n; 338 } 339 340 static void 341 check_play_intr(audigyls_dev_t *dev) 342 { 343 audigyls_port_t *port = dev->port[AUDIGYLS_PLAY_PORT]; 344 345 if (!port->started) 346 return; 347 audio_engine_consume(port->engine); 348 } 349 350 static void 351 check_rec_intr(audigyls_dev_t *dev) 352 { 353 audigyls_port_t *port = dev->port[AUDIGYLS_REC_PORT]; 354 355 if (!port->started) 356 return; 357 audio_engine_produce(port->engine); 358 } 359 360 static uint_t 361 audigyls_intr(caddr_t argp, caddr_t nocare) 362 { 363 audigyls_dev_t *dev = (void *)argp; 364 uint32_t status; 365 366 _NOTE(ARGUNUSED(nocare)); 367 status = INL(dev, IPR); 368 369 if (dev->suspended) { 370 OUTL(dev, IPR, status); /* Acknowledge */ 371 return (DDI_INTR_UNCLAIMED); 372 } 373 374 if (!(status & (INTR_IT1 | INTR_PCI))) { 375 /* No audio interrupts pending */ 376 OUTL(dev, IPR, status); /* Acknowledge */ 377 return (DDI_INTR_UNCLAIMED); 378 } 379 380 check_play_intr(dev); 381 check_rec_intr(dev); 382 383 if (dev->ksp) { 384 AUDIGYLS_KIOP(dev)->intrs[KSTAT_INTR_HARD]++; 385 } 386 387 OUTL(dev, IPR, status); /* Acknowledge */ 388 return (DDI_INTR_CLAIMED); 389 } 390 391 /* 392 * Audio routines 393 */ 394 395 int 396 audigyls_open(void *arg, int flag, 397 unsigned *fragfrp, unsigned *nfragsp, caddr_t *bufp) 398 { 399 audigyls_port_t *port = arg; 400 audigyls_dev_t *dev = port->dev; 401 402 _NOTE(ARGUNUSED(flag)); 403 404 mutex_enter(&dev->mutex); 405 406 port->started = B_FALSE; 407 port->count = 0; 408 *fragfrp = port->fragfr; 409 *nfragsp = AUDIGYLS_NUM_FRAGS; 410 *bufp = port->buf_kaddr; 411 audigyls_reset_port(port); 412 mutex_exit(&dev->mutex); 413 414 return (0); 415 } 416 417 void 418 audigyls_close(void *arg) 419 { 420 audigyls_port_t *port = arg; 421 audigyls_dev_t *dev = port->dev; 422 423 mutex_enter(&dev->mutex); 424 audigyls_stop_port(port); 425 port->started = B_FALSE; 426 mutex_exit(&dev->mutex); 427 } 428 429 int 430 audigyls_start(void *arg) 431 { 432 audigyls_port_t *port = arg; 433 audigyls_dev_t *dev = port->dev; 434 435 mutex_enter(&dev->mutex); 436 if (!port->started) { 437 audigyls_start_port(port); 438 port->started = B_TRUE; 439 } 440 mutex_exit(&dev->mutex); 441 return (0); 442 } 443 444 void 445 audigyls_stop(void *arg) 446 { 447 audigyls_port_t *port = arg; 448 audigyls_dev_t *dev = port->dev; 449 450 mutex_enter(&dev->mutex); 451 if (port->started) { 452 audigyls_stop_port(port); 453 port->started = B_FALSE; 454 } 455 mutex_exit(&dev->mutex); 456 } 457 458 int 459 audigyls_format(void *arg) 460 { 461 _NOTE(ARGUNUSED(arg)); 462 463 return (AUDIO_FORMAT_S16_LE); 464 } 465 466 int 467 audigyls_channels(void *arg) 468 { 469 audigyls_port_t *port = arg; 470 471 return (port->nchan); 472 } 473 474 int 475 audigyls_rate(void *arg) 476 { 477 _NOTE(ARGUNUSED(arg)); 478 479 return (48000); 480 } 481 482 void 483 audigyls_sync(void *arg, unsigned nframes) 484 { 485 audigyls_port_t *port = arg; 486 _NOTE(ARGUNUSED(nframes)); 487 488 (void) ddi_dma_sync(port->buf_dmah, 0, 0, port->syncdir); 489 } 490 491 size_t 492 audigyls_qlen(void *arg) 493 { 494 _NOTE(ARGUNUSED(arg)); 495 return (0); 496 } 497 498 uint64_t 499 audigyls_count(void *arg) 500 { 501 audigyls_port_t *port = arg; 502 audigyls_dev_t *dev = port->dev; 503 uint64_t count; 504 505 mutex_enter(&dev->mutex); 506 if (!dev->suspended) 507 audigyls_update_port(port); 508 count = port->count; 509 mutex_exit(&dev->mutex); 510 return (count); 511 } 512 513 static void 514 audigyls_chinfo(void *arg, int chan, unsigned *offset, unsigned *incr) 515 { 516 audigyls_port_t *port = arg; 517 518 if (port->direction == AUDIGYLS_PLAY_PORT) { 519 *offset = (port->buf_frames * 2 * (chan / 2)) + (chan % 2); 520 *incr = 2; 521 } else { 522 *offset = chan; 523 *incr = 2; 524 } 525 } 526 527 /* private implementation bits */ 528 529 void 530 audigyls_start_port(audigyls_port_t *port) 531 { 532 audigyls_dev_t *dev = port->dev; 533 uint32_t tmp; 534 535 ASSERT(mutex_owned(&dev->mutex)); 536 537 if (dev->suspended || port->active) 538 return; 539 540 port->active = B_TRUE; 541 port->offset = 0; 542 dev->nactive++; 543 544 if (dev->nactive == 1) { 545 write_reg(dev, IT, dev->timer); 546 OUTL(dev, IER, INL(dev, IER) | INTR_IT1); 547 } 548 549 switch (port->direction) { 550 case AUDIGYLS_PLAY_PORT: 551 tmp = read_reg(dev, SA); 552 tmp |= SA_SPA(0); 553 tmp |= SA_SPA(1); 554 tmp |= SA_SPA(3); 555 write_reg(dev, SA, tmp); 556 break; 557 558 case AUDIGYLS_REC_PORT: 559 tmp = read_reg(dev, SA); 560 tmp |= SA_SRA(2); 561 write_reg(dev, SA, tmp); 562 break; 563 } 564 565 } 566 567 void 568 audigyls_stop_port(audigyls_port_t *port) 569 { 570 audigyls_dev_t *dev = port->dev; 571 uint32_t tmp; 572 573 if (dev->suspended || !port->active) 574 return; 575 576 port->active = B_FALSE; 577 dev->nactive--; 578 579 switch (port->direction) { 580 case AUDIGYLS_PLAY_PORT: 581 tmp = read_reg(dev, SA); 582 tmp &= ~SA_SPA(0); 583 tmp &= ~SA_SPA(1); 584 tmp &= ~SA_SPA(3); 585 write_reg(dev, SA, tmp); 586 break; 587 588 case AUDIGYLS_REC_PORT: 589 tmp = read_reg(dev, SA); 590 tmp &= ~SA_SRA(2); 591 write_reg(dev, SA, tmp); 592 break; 593 } 594 595 if (dev->nactive == 0) { 596 OUTL(dev, IER, INL(dev, IER) & ~INTR_IT1); 597 } 598 } 599 600 void 601 audigyls_reset_port(audigyls_port_t *port) 602 { 603 audigyls_dev_t *dev = port->dev; 604 605 ASSERT(mutex_owned(&dev->mutex)); 606 607 if (dev->suspended) 608 return; 609 610 switch (port->direction) { 611 case AUDIGYLS_PLAY_PORT: 612 write_chan(dev, PTCA, 0, 0); 613 write_chan(dev, CPFA, 0, 0); 614 write_chan(dev, CPCAV, 0, 0); 615 write_chan(dev, PTCA, 1, 0); 616 write_chan(dev, CPFA, 1, 0); 617 write_chan(dev, CPCAV, 1, 0); 618 write_chan(dev, PTCA, 3, 0); 619 write_chan(dev, CPFA, 3, 0); 620 write_chan(dev, CPCAV, 3, 0); 621 break; 622 623 case AUDIGYLS_REC_PORT: 624 write_chan(dev, CRFA, 2, 0); 625 write_chan(dev, CRCAV, 2, 0); 626 break; 627 } 628 } 629 630 int 631 audigyls_alloc_port(audigyls_dev_t *dev, int num) 632 { 633 audigyls_port_t *port; 634 size_t len; 635 ddi_dma_cookie_t cookie; 636 uint_t count; 637 int dir; 638 unsigned caps; 639 audio_dev_t *adev; 640 641 adev = dev->adev; 642 port = kmem_zalloc(sizeof (*port), KM_SLEEP); 643 dev->port[num] = port; 644 port->dev = dev; 645 port->started = B_FALSE; 646 port->direction = num; 647 648 switch (num) { 649 case AUDIGYLS_REC_PORT: 650 port->syncdir = DDI_DMA_SYNC_FORKERNEL; 651 caps = ENGINE_INPUT_CAP; 652 dir = DDI_DMA_READ; 653 port->nchan = 2; 654 break; 655 case AUDIGYLS_PLAY_PORT: 656 port->syncdir = DDI_DMA_SYNC_FORDEV; 657 caps = ENGINE_OUTPUT_CAP; 658 dir = DDI_DMA_WRITE; 659 port->nchan = 6; 660 break; 661 default: 662 return (DDI_FAILURE); 663 } 664 665 /* figure out fragment configuration */ 666 port->fragfr = 48000 / dev->intrs; 667 /* we want to make sure that we are aligning on reasonable chunks */ 668 port->fragfr = (port->fragfr + 63) & ~(63); 669 670 /* 16 bit frames */ 671 port->fragsz = port->fragfr * 2 * port->nchan; 672 port->buf_size = port->fragsz * AUDIGYLS_NUM_FRAGS; 673 port->buf_frames = port->fragfr * AUDIGYLS_NUM_FRAGS; 674 675 /* Alloc buffers */ 676 if (ddi_dma_alloc_handle(dev->dip, &dma_attr_buf, DDI_DMA_SLEEP, NULL, 677 &port->buf_dmah) != DDI_SUCCESS) { 678 audio_dev_warn(adev, "failed to allocate BUF handle"); 679 return (DDI_FAILURE); 680 } 681 682 if (ddi_dma_mem_alloc(port->buf_dmah, port->buf_size, 683 &buf_attr, DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, 684 &port->buf_kaddr, &len, &port->buf_acch) != DDI_SUCCESS) { 685 audio_dev_warn(adev, "failed to allocate BUF memory"); 686 return (DDI_FAILURE); 687 } 688 689 if (ddi_dma_addr_bind_handle(port->buf_dmah, NULL, port->buf_kaddr, 690 len, DDI_DMA_CONSISTENT | dir, DDI_DMA_SLEEP, NULL, &cookie, 691 &count) != DDI_SUCCESS) { 692 audio_dev_warn(adev, "failed binding BUF DMA handle"); 693 return (DDI_FAILURE); 694 } 695 port->buf_paddr = cookie.dmac_address; 696 697 port->engine = audio_engine_alloc(&audigyls_engine_ops, caps); 698 if (port->engine == NULL) { 699 audio_dev_warn(adev, "audio_engine_alloc failed"); 700 return (DDI_FAILURE); 701 } 702 703 audio_engine_set_private(port->engine, port); 704 audio_dev_add_engine(adev, port->engine); 705 706 return (DDI_SUCCESS); 707 } 708 709 int 710 audigyls_setup_intrs(audigyls_dev_t *dev) 711 { 712 uint_t ipri; 713 int actual; 714 int rv; 715 ddi_intr_handle_t ih[1]; 716 717 rv = ddi_intr_alloc(dev->dip, ih, DDI_INTR_TYPE_FIXED, 718 0, 1, &actual, DDI_INTR_ALLOC_STRICT); 719 if ((rv != DDI_SUCCESS) || (actual != 1)) { 720 audio_dev_warn(dev->adev, 721 "Can't alloc interrupt handle (rv %d actual %d)", 722 rv, actual); 723 return (DDI_FAILURE); 724 } 725 726 if (ddi_intr_get_pri(ih[0], &ipri) != DDI_SUCCESS) { 727 audio_dev_warn(dev->adev, "Can't get interrupt priority"); 728 (void) ddi_intr_free(ih[0]); 729 return (DDI_FAILURE); 730 } 731 732 if (ddi_intr_add_handler(ih[0], audigyls_intr, dev, NULL) != 733 DDI_SUCCESS) { 734 audio_dev_warn(dev->adev, "Can't add interrupt handler"); 735 (void) ddi_intr_free(ih[0]); 736 return (DDI_FAILURE); 737 } 738 739 dev->ih = ih[0]; 740 mutex_init(&dev->mutex, NULL, MUTEX_DRIVER, DDI_INTR_PRI(ipri)); 741 mutex_init(&dev->low_mutex, NULL, MUTEX_DRIVER, DDI_INTR_PRI(ipri)); 742 return (DDI_SUCCESS); 743 } 744 745 void 746 audigyls_destroy(audigyls_dev_t *dev) 747 { 748 if (dev->ih != NULL) { 749 (void) ddi_intr_disable(dev->ih); 750 (void) ddi_intr_remove_handler(dev->ih); 751 (void) ddi_intr_free(dev->ih); 752 mutex_destroy(&dev->mutex); 753 mutex_destroy(&dev->low_mutex); 754 } 755 756 if (dev->ksp) { 757 kstat_delete(dev->ksp); 758 } 759 760 for (int i = 0; i < AUDIGYLS_NUM_PORT; i++) { 761 audigyls_port_t *port = dev->port[i]; 762 if (!port) 763 continue; 764 if (port->engine) { 765 audio_dev_remove_engine(dev->adev, port->engine); 766 audio_engine_free(port->engine); 767 } 768 if (port->buf_paddr) { 769 (void) ddi_dma_unbind_handle(port->buf_dmah); 770 } 771 if (port->buf_acch) { 772 ddi_dma_mem_free(&port->buf_acch); 773 } 774 if (port->buf_dmah) { 775 ddi_dma_free_handle(&port->buf_dmah); 776 } 777 kmem_free(port, sizeof (*port)); 778 } 779 780 if (dev->ac97 != NULL) { 781 ac97_free(dev->ac97); 782 } 783 if (dev->adev != NULL) { 784 audio_dev_free(dev->adev); 785 } 786 if (dev->regsh != NULL) { 787 ddi_regs_map_free(&dev->regsh); 788 } 789 if (dev->pcih != NULL) { 790 pci_config_teardown(&dev->pcih); 791 } 792 kmem_free(dev, sizeof (*dev)); 793 } 794 795 void 796 audigyls_hwinit(audigyls_dev_t *dev) 797 { 798 static unsigned int spi_dac[] = { 799 0x00ff, 0x02ff, 0x0400, 0x520, 0x0620, 0x08ff, 0x0aff, 0x0cff, 800 0x0eff, 0x10ff, 0x1200, 0x1400, 0x1800, 0x1aff, 0x1cff, 801 0x1e00, 0x0530, 0x0602, 0x0622, 0x1400, 802 }; 803 804 uint32_t tmp; 805 int i, tries; 806 uint32_t paddr; 807 uint32_t chunksz; 808 audigyls_port_t *port; 809 810 811 /* Set the orange jack to be analog out or S/PDIF */ 812 select_digital_enable(dev, dev->digital_enable); 813 814 /* 815 * In P17, there's 8 GPIO pins. 816 * GPIO register: 0x00XXYYZZ 817 * XX: Configure GPIO to be either GPI (0) or GPO (1). 818 * YY: GPO values, applicable if the pin is configure to be GPO. 819 * ZZ: GPI values, applicable if the pin is configure to be GPI. 820 * 821 * in SB570, pin 0-4 and 6 is used as GPO and pin 5 and 7 is 822 * used as GPI. 823 * 824 * GPO0: 825 * 1 ==> Analog output 826 * 0 ==> Digital output 827 * GPO1: 828 * 1 ==> Enable output on card 829 * 0 ==> Disable output on card 830 * GPO2: 831 * 1 ==> Enable Mic Bias and Mic Path 832 * 0 ==> Disable Mic Bias and Mic Path 833 * GPO3: 834 * 1 ==> Disable SPDIF-IO output 835 * 0 ==> Enable SPDIF-IO output 836 * GPO4 and GPO6: 837 * DAC sampling rate selection: 838 * Not applicable to SB570 since DAC is controlled through SPI 839 * GPI5: 840 * 1 ==> Front Panel is not connected 841 * 0 ==> Front Panel is connected 842 * GPI7: 843 * 1 ==> Front Panel Headphone is not connected 844 * 0 ==> Front Panel Headphone is connected 845 */ 846 if (dev->ac97) 847 OUTL(dev, GPIO, 0x005f03a3); 848 else { 849 /* for SBLive 7.1 */ 850 OUTL(dev, GPIO, 0x005f4301); 851 852 audigyls_i2c_write(dev, 0x15, 0x2); 853 tries = 0; 854 again: 855 for (i = 0; i < sizeof (spi_dac); i++) { 856 if (!audigyls_spi_write(dev, spi_dac[i]) && 857 tries < 100) { 858 tries++; 859 goto again; 860 } 861 } 862 } 863 864 OUTL(dev, IER, INTR_PCI); 865 OUTL(dev, HC, 0x00000009); /* Enable audio, use 48 kHz */ 866 867 tmp = read_chan(dev, SRCTL, 0); 868 if (dev->ac97) 869 tmp |= 0xf0c81000; /* Record src0/src1 from ac97 */ 870 else 871 tmp |= 0x50c81000; /* Record src0/src1 from I2SIN */ 872 tmp &= ~0x0303c00f; /* Set sample rates to 48 kHz */ 873 write_chan(dev, SRCTL, 0, tmp); 874 875 write_reg(dev, HMIXMAP_I2S, 0x76543210); /* Default out route */ 876 write_reg(dev, AUDCTL, 0x0f0f003f); /* Enable all outputs */ 877 878 /* All audio stopped! */ 879 write_reg(dev, SA, 0); 880 881 for (i = 0; i < 4; i++) { 882 /* 883 * Reset DMA pointers and counters. Note that we do 884 * not use scatter/gather. 885 */ 886 write_chan(dev, PTBA, i, 0); 887 write_chan(dev, PTBS, i, 0); 888 write_chan(dev, PTCA, i, 0); 889 890 write_chan(dev, CPFA, i, 0); 891 write_chan(dev, PFEA, i, 0); 892 write_chan(dev, CPCAV, i, 0); 893 894 write_chan(dev, CRFA, i, 0); 895 write_chan(dev, CRCAV, i, 0); 896 } 897 898 /* 899 * The 5.1 play port made up channels 0, 1, and 3. The record 900 * port is channel 2. 901 */ 902 port = dev->port[AUDIGYLS_PLAY_PORT]; 903 paddr = port->buf_paddr; 904 chunksz = port->buf_frames * 4; 905 write_chan(dev, PFBA, 0, paddr); 906 write_chan(dev, PFBS, 0, chunksz << 16); 907 paddr += chunksz; 908 write_chan(dev, PFBA, 1, paddr); 909 write_chan(dev, PFBS, 1, chunksz << 16); 910 paddr += chunksz; 911 write_chan(dev, PFBA, 3, paddr); 912 write_chan(dev, PFBS, 3, chunksz << 16); 913 914 /* Record */ 915 port = dev->port[AUDIGYLS_REC_PORT]; 916 paddr = port->buf_paddr; 917 chunksz = port->buf_frames * 4; 918 write_chan(dev, RFBA, 2, paddr); 919 write_chan(dev, RFBS, 2, chunksz << 16); 920 921 /* Set sample rates to 48 kHz. */ 922 tmp = read_chan(dev, SRCTL, 0) & ~0x0303c00f; 923 write_chan(dev, SRCTL, 0, tmp); 924 925 write_reg(dev, SCS0, 0x02108004); /* Audio */ 926 write_reg(dev, SCS1, 0x02108004); /* Audio */ 927 write_reg(dev, SCS2, 0x02108004); /* Audio */ 928 write_reg(dev, SCS3, 0x02108004); /* Audio */ 929 } 930 931 #define PLAYCTL (AUDIO_CTRL_FLAG_RW | AUDIO_CTRL_FLAG_PLAY) 932 #define RECCTL (AUDIO_CTRL_FLAG_RW | AUDIO_CTRL_FLAG_REC) 933 #define MONCTL (AUDIO_CTRL_FLAG_RW | AUDIO_CTRL_FLAG_MONITOR) 934 #define PCMVOL (PLAYCTL | AUDIO_CTRL_FLAG_PCMVOL) 935 #define MAINVOL (PLAYCTL | AUDIO_CTRL_FLAG_MAINVOL) 936 #define RECVOL (RECCTL | AUDIO_CTRL_FLAG_RECVOL) 937 #define MONVOL (MONCTL | AUDIO_CTRL_FLAG_MONVOL) 938 939 #define MASK(nbits) ((1 << (nbits)) - 1) 940 #define SCALE(val, nbits) \ 941 ((uint8_t)((((val) * MASK(nbits)) / 100)) << (8 - (nbits))) 942 943 static uint32_t 944 audigyls_stereo_scale(uint32_t value, uint8_t bits) 945 { 946 uint8_t left, right; 947 uint32_t val; 948 949 left = (value >> 8) & 0xff; 950 right = value & 0xff; 951 952 val = (((left * ((1 << bits) - 1) / 100) << 8) | 953 (right * ((1 << bits) - 1) / 100)); 954 return (val); 955 } 956 957 static void 958 audigyls_configure_mixer(audigyls_dev_t *dev) 959 { 960 unsigned int r, v1, v2; 961 962 ASSERT(mutex_owned(&dev->mutex)); 963 964 /* output items */ 965 /* front */ 966 r = 0xffff - audigyls_stereo_scale(dev->controls[CTL_FRONT].val, 8); 967 r = (r << 16) | r; 968 write_chan(dev, MIXVOL_I2S, 0, r); 969 970 /* surround */ 971 r = 0xffff - audigyls_stereo_scale(dev->controls[CTL_SURROUND].val, 8); 972 r = (r << 16) | r; 973 write_chan(dev, MIXVOL_I2S, 3, r); 974 975 /* center/lfe */ 976 v1 = 255 - SCALE(dev->controls[CTL_CENTER].val, 8); 977 v2 = 255 - SCALE(dev->controls[CTL_LFE].val, 8); 978 r = (v1 << 8) | v2; 979 r = (r << 16) | r; 980 write_chan(dev, MIXVOL_I2S, 1, r); 981 982 /* spread */ 983 r = dev->controls[CTL_SPREAD].val ? 0x10101010 : 0x76543210; 984 write_reg(dev, HMIXMAP_I2S, r); 985 986 /* input items */ 987 988 /* recgain */ 989 v1 = dev->controls[CTL_RECORDVOL].val; 990 if (dev->ac97_recgain && !dev->controls[CTL_LOOP].val) { 991 /* 992 * For AC'97, we use the AC'97 record gain, unless we are 993 * in loopback. 994 */ 995 (void) ac97_control_set(dev->ac97_recgain, v1); 996 write_reg(dev, P17RECVOLL, 0x30303030); 997 write_reg(dev, P17RECVOLH, 0x30303030); 998 } else { 999 /* 1000 * Otherwise we set the P17 gain. 1001 */ 1002 r = 0xffff - audigyls_stereo_scale(v1, 8); 1003 r = r << 16 | r; 1004 write_reg(dev, P17RECVOLL, r); 1005 write_reg(dev, P17RECVOLH, r); 1006 } 1007 1008 /* monitor gain */ 1009 if (dev->ac97) { 1010 /* AC'97 monitor gain is done by the AC'97 codec */ 1011 write_chan(dev, SRCTL, 1, 0x30303030); 1012 write_reg(dev, SMIXMAP_I2S, 0x10101076); 1013 } else { 1014 /* For non-AC'97 devices, just a single master monitor gain */ 1015 r = 255 - SCALE(dev->controls[CTL_MONGAIN].val, 8); 1016 write_chan(dev, SRCTL, 1, 0xffff0000 | r << 8 | r); 1017 if (r != 0xff) { 1018 write_reg(dev, SMIXMAP_I2S, 0x10101076); 1019 } else { 1020 write_reg(dev, SMIXMAP_I2S, 0x10101010); 1021 } 1022 } 1023 1024 /* record source */ 1025 if (dev->ac97_recsrc != NULL) { 1026 (void) ac97_control_set(dev->ac97_recsrc, 1027 dev->controls[CTL_RECSRC].val); 1028 v1 = RECSEL_AC97; /* Audigy LS */ 1029 } else { 1030 switch (dev->controls[CTL_RECSRC].val) { 1031 case 1: 1032 audigyls_i2c_write(dev, 0x15, 0x2); /* Mic */ 1033 OUTL(dev, GPIO, INL(dev, GPIO) | 0x400); 1034 break; 1035 1036 case 2: 1037 audigyls_i2c_write(dev, 0x15, 0x4); /* Line */ 1038 OUTL(dev, GPIO, INL(dev, GPIO) & ~0x400); 1039 break; 1040 } 1041 v1 = RECSEL_I2SIN; /* SB 7.1 value */ 1042 } 1043 1044 /* If loopback, record what you hear instead */ 1045 1046 if (dev->controls[CTL_LOOP].val) { 1047 r = 0; 1048 v1 = RECSEL_I2SOUT; 1049 r |= (v1 << 28) | (v1 << 24) | (v1 << 20) | (v1 << 16) | v2; 1050 } else { 1051 /* 1052 * You'd think this would be the same as the logic 1053 * above, but experience shows that what you need for 1054 * loopback is different. This whole thing looks 1055 * particularly fishy to me. I suspect someone has 1056 * made a mistake somewhere. But I can't seem to 1057 * figure out where it lies. 1058 */ 1059 r = 0xe4; 1060 for (int i = 0; i < 4; i++) 1061 r |= v1 << (16 + i * 3); /* Select input */ 1062 } 1063 1064 write_reg(dev, P17RECSEL, r); 1065 } 1066 1067 static int 1068 audigyls_set_control(void *arg, uint64_t val) 1069 { 1070 audigyls_ctrl_t *pc = arg; 1071 audigyls_dev_t *dev = pc->dev; 1072 1073 switch (pc->num) { 1074 1075 case CTL_FRONT: 1076 case CTL_SURROUND: 1077 case CTL_RECORDVOL: 1078 if (((val & 0xff) > 100) || 1079 (((val & 0xff00) >> 8) > 100) || 1080 ((val & ~0xffff) != 0)) { 1081 return (EINVAL); 1082 } 1083 break; 1084 1085 case CTL_CENTER: 1086 case CTL_LFE: 1087 case CTL_MONGAIN: 1088 if (val > 100) { 1089 return (EINVAL); 1090 } 1091 break; 1092 1093 case CTL_RECSRC: 1094 if (((1U << val) & (dev->recmask)) == 0) { 1095 return (EINVAL); 1096 } 1097 break; 1098 1099 case CTL_SPREAD: 1100 case CTL_LOOP: 1101 switch (val) { 1102 case 0: 1103 case 1: 1104 break; 1105 default: 1106 return (EINVAL); 1107 } 1108 } 1109 1110 mutex_enter(&dev->mutex); 1111 pc->val = val; 1112 if (!dev->suspended) { 1113 audigyls_configure_mixer(dev); 1114 } 1115 mutex_exit(&dev->mutex); 1116 1117 return (0); 1118 } 1119 1120 static int 1121 audigyls_get_control(void *arg, uint64_t *val) 1122 { 1123 audigyls_ctrl_t *pc = arg; 1124 audigyls_dev_t *dev = pc->dev; 1125 1126 mutex_enter(&dev->mutex); 1127 *val = pc->val; 1128 mutex_exit(&dev->mutex); 1129 return (0); 1130 } 1131 1132 static void 1133 audigyls_alloc_ctrl(audigyls_dev_t *dev, uint32_t num, uint64_t val) 1134 { 1135 audio_ctrl_desc_t desc; 1136 audigyls_ctrl_t *pc; 1137 1138 bzero(&desc, sizeof (desc)); 1139 1140 pc = &dev->controls[num]; 1141 pc->num = num; 1142 pc->dev = dev; 1143 1144 1145 switch (num) { 1146 case CTL_FRONT: 1147 desc.acd_name = AUDIO_CTRL_ID_FRONT; 1148 desc.acd_type = AUDIO_CTRL_TYPE_STEREO; 1149 desc.acd_minvalue = 0; 1150 desc.acd_maxvalue = 100; 1151 desc.acd_flags = MAINVOL; 1152 break; 1153 1154 case CTL_SURROUND: 1155 desc.acd_name = AUDIO_CTRL_ID_SURROUND; 1156 desc.acd_type = AUDIO_CTRL_TYPE_STEREO; 1157 desc.acd_minvalue = 0; 1158 desc.acd_maxvalue = 100; 1159 desc.acd_flags = MAINVOL; 1160 break; 1161 1162 case CTL_CENTER: 1163 desc.acd_name = AUDIO_CTRL_ID_CENTER; 1164 desc.acd_type = AUDIO_CTRL_TYPE_MONO; 1165 desc.acd_minvalue = 0; 1166 desc.acd_maxvalue = 100; 1167 desc.acd_flags = MAINVOL; 1168 break; 1169 1170 case CTL_LFE: 1171 desc.acd_name = AUDIO_CTRL_ID_LFE; 1172 desc.acd_type = AUDIO_CTRL_TYPE_MONO; 1173 desc.acd_minvalue = 0; 1174 desc.acd_maxvalue = 100; 1175 desc.acd_flags = MAINVOL; 1176 break; 1177 1178 case CTL_RECORDVOL: 1179 desc.acd_name = AUDIO_CTRL_ID_RECGAIN; 1180 desc.acd_type = AUDIO_CTRL_TYPE_STEREO; 1181 desc.acd_minvalue = 0; 1182 desc.acd_maxvalue = 100; 1183 desc.acd_flags = RECVOL; 1184 break; 1185 1186 case CTL_RECSRC: 1187 desc.acd_name = AUDIO_CTRL_ID_RECSRC; 1188 desc.acd_type = AUDIO_CTRL_TYPE_ENUM; 1189 desc.acd_flags = RECCTL; 1190 1191 /* 1192 * For AC'97 devices, we want to expose the reasonable 1193 * AC'97 input sources, but suppress the stereomix, 1194 * because we use loopback instead. 1195 */ 1196 if (dev->ac97_recsrc) { 1197 int i, j; 1198 const char *n; 1199 const audio_ctrl_desc_t *adp; 1200 1201 adp = ac97_control_desc(dev->ac97_recsrc); 1202 for (i = 0; i < 64; i++) { 1203 n = adp->acd_enum[i]; 1204 1205 if (((adp->acd_minvalue & (1 << i)) == 0) || 1206 (n == NULL)) { 1207 continue; 1208 } 1209 for (j = 0; audigyls_badsrcs[j]; j++) { 1210 if (strcmp(n, audigyls_badsrcs[j]) 1211 == 0) { 1212 n = NULL; 1213 break; 1214 } 1215 } 1216 if (n) { 1217 desc.acd_enum[i] = n; 1218 dev->recmask |= (1 << i); 1219 } 1220 } 1221 desc.acd_minvalue = desc.acd_maxvalue = dev->recmask; 1222 } else { 1223 dev->recmask = 3; 1224 desc.acd_minvalue = 3; 1225 desc.acd_maxvalue = 3; 1226 desc.acd_enum[0] = AUDIO_PORT_MIC; 1227 desc.acd_enum[1] = AUDIO_PORT_LINEIN; 1228 } 1229 break; 1230 1231 case CTL_MONGAIN: 1232 ASSERT(!dev->ac97); 1233 desc.acd_name = AUDIO_CTRL_ID_MONGAIN; 1234 desc.acd_type = AUDIO_CTRL_TYPE_MONO; 1235 desc.acd_minvalue = 0; 1236 desc.acd_maxvalue = 100; 1237 desc.acd_flags = MONVOL; 1238 break; 1239 1240 case CTL_SPREAD: 1241 desc.acd_name = AUDIO_CTRL_ID_SPREAD; 1242 desc.acd_type = AUDIO_CTRL_TYPE_BOOLEAN; 1243 desc.acd_minvalue = 0; 1244 desc.acd_maxvalue = 1; 1245 desc.acd_flags = PLAYCTL; 1246 break; 1247 1248 case CTL_LOOP: 1249 desc.acd_name = AUDIO_CTRL_ID_LOOPBACK; 1250 desc.acd_type = AUDIO_CTRL_TYPE_BOOLEAN; 1251 desc.acd_minvalue = 0; 1252 desc.acd_maxvalue = 1; 1253 desc.acd_flags = RECCTL; 1254 break; 1255 } 1256 1257 pc->val = val; 1258 pc->ctrl = audio_dev_add_control(dev->adev, &desc, 1259 audigyls_get_control, audigyls_set_control, pc); 1260 } 1261 1262 static void 1263 audigyls_add_controls(audigyls_dev_t *dev) 1264 { 1265 (void) audio_dev_add_soft_volume(dev->adev); 1266 1267 audigyls_alloc_ctrl(dev, CTL_FRONT, 75 | (75 << 8)); 1268 audigyls_alloc_ctrl(dev, CTL_SURROUND, 75 | (75 << 8)); 1269 audigyls_alloc_ctrl(dev, CTL_CENTER, 75); 1270 audigyls_alloc_ctrl(dev, CTL_LFE, 75); 1271 audigyls_alloc_ctrl(dev, CTL_RECORDVOL, 75 | (75 << 8)); 1272 audigyls_alloc_ctrl(dev, CTL_RECSRC, 1); 1273 audigyls_alloc_ctrl(dev, CTL_SPREAD, 0); 1274 audigyls_alloc_ctrl(dev, CTL_LOOP, 0); 1275 if (!dev->ac97) { 1276 audigyls_alloc_ctrl(dev, CTL_MONGAIN, 0); 1277 } 1278 } 1279 1280 int 1281 audigyls_attach(dev_info_t *dip) 1282 { 1283 uint16_t pci_command, vendor, device; 1284 uint32_t subdevice; 1285 audigyls_dev_t *dev; 1286 ddi_acc_handle_t pcih; 1287 const char *name, *version; 1288 boolean_t ac97 = B_FALSE; 1289 1290 dev = kmem_zalloc(sizeof (*dev), KM_SLEEP); 1291 dev->dip = dip; 1292 ddi_set_driver_private(dip, dev); 1293 1294 if ((dev->adev = audio_dev_alloc(dip, 0)) == NULL) { 1295 cmn_err(CE_WARN, "audio_dev_alloc failed"); 1296 goto error; 1297 } 1298 1299 if (pci_config_setup(dip, &pcih) != DDI_SUCCESS) { 1300 audio_dev_warn(dev->adev, "pci_config_setup failed"); 1301 goto error; 1302 } 1303 dev->pcih = pcih; 1304 1305 vendor = pci_config_get16(pcih, PCI_CONF_VENID); 1306 device = pci_config_get16(pcih, PCI_CONF_DEVID); 1307 subdevice = pci_config_get16(pcih, PCI_CONF_SUBVENID); 1308 subdevice <<= 16; 1309 subdevice |= pci_config_get16(pcih, PCI_CONF_SUBSYSID); 1310 if (vendor != PCI_VENDOR_ID_CREATIVE || 1311 device != PCI_DEVICE_ID_CREATIVE_AUDIGYLS) { 1312 audio_dev_warn(dev->adev, "Hardware not recognized " 1313 "(vendor=%x, dev=%x)", vendor, device); 1314 goto error; 1315 } 1316 1317 pci_command = pci_config_get16(pcih, PCI_CONF_COMM); 1318 pci_command |= PCI_COMM_ME | PCI_COMM_IO; 1319 pci_config_put16(pcih, PCI_CONF_COMM, pci_command); 1320 1321 if ((ddi_regs_map_setup(dip, 1, &dev->base, 0, 0, &dev_attr, 1322 &dev->regsh)) != DDI_SUCCESS) { 1323 audio_dev_warn(dev->adev, "failed to map registers"); 1324 goto error; 1325 } 1326 1327 /* Function of the orange jack: 0=analog, 1=digital */ 1328 dev->digital_enable = ddi_prop_get_int(DDI_DEV_T_ANY, dev->dip, 1329 DDI_PROP_DONTPASS, "digital-enable", 0); 1330 1331 if (audigyls_setup_intrs(dev) != DDI_SUCCESS) 1332 goto error; 1333 1334 dev->intrs = ddi_prop_get_int(DDI_DEV_T_ANY, dev->dip, 1335 DDI_PROP_DONTPASS, "interrupt-rate", AUDIGYLS_INTRS); 1336 1337 /* make sure the values are good */ 1338 if (dev->intrs < AUDIGYLS_MIN_INTRS) { 1339 audio_dev_warn(dev->adev, 1340 "interrupt-rate too low, %d, reset to %d", 1341 dev->intrs, AUDIGYLS_INTRS); 1342 dev->intrs = AUDIGYLS_INTRS; 1343 } else if (dev->intrs > AUDIGYLS_MAX_INTRS) { 1344 audio_dev_warn(dev->adev, 1345 "interrupt-rate too high, %d, reset to %d", 1346 dev->intrs, AUDIGYLS_INTRS); 1347 dev->intrs = AUDIGYLS_INTRS; 1348 } 1349 1350 dev->timer = (192000 / dev->intrs) << 16; 1351 1352 switch (subdevice) { 1353 case 0x11021001: /* SB0310 */ 1354 case 0x11021002: /* SB0310 */ 1355 case 0x11021005: /* SB0310b */ 1356 name = "Creative Audigy LS"; 1357 version = "SB0310"; /* could also be SB0312 */ 1358 ac97 = B_TRUE; 1359 break; 1360 case 0x11021006: 1361 name = "Creative Sound Blaster Live! 24 bit"; 1362 version = "SB0410"; 1363 break; 1364 case 0x11021007: /* Dell OEM version */ 1365 name = "Creative Sound Blaster Live! 24 bit"; 1366 version = "SB0413"; 1367 break; 1368 case 0x1102100a: 1369 name = "Creative Audigy SE"; 1370 version = "SB0570"; 1371 break; 1372 case 0x11021011: 1373 name = "Creative Audigy SE OEM"; 1374 version = "SB0570a"; 1375 break; 1376 case 0x11021012: 1377 name = "Creative X-Fi Extreme Audio"; 1378 version = "SB0790"; 1379 break; 1380 case 0x14621009: 1381 name = "MSI K8N Diamond MB"; 1382 version = "SB0438"; 1383 break; 1384 case 0x12973038: 1385 name = "Shuttle XPC SD31P"; 1386 version = "SD31P"; 1387 break; 1388 case 0x12973041: 1389 name = "Shuttle XPC SD11G5"; 1390 version = "SD11G5"; 1391 break; 1392 default: 1393 name = "Creative Audigy LS"; 1394 version = NULL; 1395 break; 1396 } 1397 1398 audio_dev_set_description(dev->adev, name); 1399 if (version) 1400 audio_dev_set_version(dev->adev, version); 1401 1402 if (ac97) { 1403 ac97_ctrl_t *ctrl; 1404 1405 /* Original Audigy LS revision (AC97 based) */ 1406 dev->ac97 = ac97_allocate(dev->adev, dip, 1407 audigyls_read_ac97, audigyls_write_ac97, dev); 1408 if (dev->ac97 == NULL) { 1409 audio_dev_warn(dev->adev, 1410 "failed to allocate ac97 handle"); 1411 goto error; 1412 } 1413 1414 ac97_probe_controls(dev->ac97); 1415 1416 /* remove the AC'97 controls we don't want to expose */ 1417 for (int i = 0; audigyls_remove_ac97[i]; i++) { 1418 ctrl = ac97_control_find(dev->ac97, 1419 audigyls_remove_ac97[i]); 1420 if (ctrl != NULL) { 1421 ac97_control_unregister(ctrl); 1422 } 1423 } 1424 1425 dev->ac97_recgain = ac97_control_find(dev->ac97, 1426 AUDIO_CTRL_ID_RECGAIN); 1427 dev->ac97_recsrc = ac97_control_find(dev->ac97, 1428 AUDIO_CTRL_ID_RECSRC); 1429 } 1430 1431 audigyls_add_controls(dev); 1432 1433 if (dev->ac97) { 1434 ac97_register_controls(dev->ac97); 1435 } 1436 1437 if (audigyls_alloc_port(dev, AUDIGYLS_PLAY_PORT) != DDI_SUCCESS) 1438 goto error; 1439 if (audigyls_alloc_port(dev, AUDIGYLS_REC_PORT) != DDI_SUCCESS) 1440 goto error; 1441 1442 audigyls_hwinit(dev); 1443 1444 audigyls_configure_mixer(dev); 1445 1446 /* set up kernel statistics */ 1447 if ((dev->ksp = kstat_create(AUDIGYLS_NAME, ddi_get_instance(dip), 1448 AUDIGYLS_NAME, "controller", KSTAT_TYPE_INTR, 1, 1449 KSTAT_FLAG_PERSISTENT)) != NULL) { 1450 kstat_install(dev->ksp); 1451 } 1452 1453 if (audio_dev_register(dev->adev) != DDI_SUCCESS) { 1454 audio_dev_warn(dev->adev, "unable to register with framework"); 1455 goto error; 1456 } 1457 1458 (void) ddi_intr_enable(dev->ih); 1459 ddi_report_dev(dip); 1460 1461 return (DDI_SUCCESS); 1462 1463 error: 1464 audigyls_destroy(dev); 1465 return (DDI_FAILURE); 1466 } 1467 1468 int 1469 audigyls_resume(dev_info_t *dip) 1470 { 1471 audigyls_dev_t *dev; 1472 audigyls_port_t *port; 1473 1474 dev = ddi_get_driver_private(dip); 1475 1476 for (int i = 0; i < AUDIGYLS_NUM_PORT; i++) { 1477 port = dev->port[i]; 1478 audio_engine_reset(port->engine); 1479 } 1480 1481 audigyls_hwinit(dev); 1482 1483 /* allow ac97 operations again */ 1484 if (dev->ac97) 1485 ac97_resume(dev->ac97); 1486 1487 audigyls_configure_mixer(dev); 1488 1489 mutex_enter(&dev->mutex); 1490 dev->suspended = B_FALSE; 1491 1492 for (int i = 0; i < AUDIGYLS_NUM_PORT; i++) { 1493 1494 port = dev->port[i]; 1495 1496 audigyls_reset_port(port); 1497 1498 if (port->started) { 1499 audigyls_start_port(port); 1500 } 1501 } 1502 1503 mutex_exit(&dev->mutex); 1504 return (DDI_SUCCESS); 1505 } 1506 1507 int 1508 audigyls_detach(audigyls_dev_t *dev) 1509 { 1510 if (audio_dev_unregister(dev->adev) != DDI_SUCCESS) 1511 return (DDI_FAILURE); 1512 1513 audigyls_destroy(dev); 1514 return (DDI_SUCCESS); 1515 } 1516 1517 int 1518 audigyls_suspend(audigyls_dev_t *dev) 1519 { 1520 if (dev->ac97) 1521 ac97_suspend(dev->ac97); 1522 1523 mutex_enter(&dev->mutex); 1524 for (int i = 0; i < AUDIGYLS_NUM_PORT; i++) { 1525 1526 audigyls_port_t *port = dev->port[i]; 1527 audigyls_stop_port(port); 1528 } 1529 dev->suspended = B_TRUE; 1530 mutex_exit(&dev->mutex); 1531 return (DDI_SUCCESS); 1532 } 1533 1534 static int audigyls_ddi_attach(dev_info_t *, ddi_attach_cmd_t); 1535 static int audigyls_ddi_detach(dev_info_t *, ddi_detach_cmd_t); 1536 static int audigyls_ddi_quiesce(dev_info_t *); 1537 1538 static struct dev_ops audigyls_dev_ops = { 1539 DEVO_REV, /* rev */ 1540 0, /* refcnt */ 1541 NULL, /* getinfo */ 1542 nulldev, /* identify */ 1543 nulldev, /* probe */ 1544 audigyls_ddi_attach, /* attach */ 1545 audigyls_ddi_detach, /* detach */ 1546 nodev, /* reset */ 1547 NULL, /* cb_ops */ 1548 NULL, /* bus_ops */ 1549 NULL, /* power */ 1550 audigyls_ddi_quiesce, /* quiesce */ 1551 }; 1552 1553 static struct modldrv audigyls_modldrv = { 1554 &mod_driverops, /* drv_modops */ 1555 "Creative Audigy LS Audio", /* linkinfo */ 1556 &audigyls_dev_ops, /* dev_ops */ 1557 }; 1558 1559 static struct modlinkage modlinkage = { 1560 MODREV_1, 1561 { &audigyls_modldrv, NULL } 1562 }; 1563 1564 int 1565 _init(void) 1566 { 1567 int rv; 1568 1569 audio_init_ops(&audigyls_dev_ops, AUDIGYLS_NAME); 1570 if ((rv = mod_install(&modlinkage)) != 0) { 1571 audio_fini_ops(&audigyls_dev_ops); 1572 } 1573 return (rv); 1574 } 1575 1576 int 1577 _fini(void) 1578 { 1579 int rv; 1580 1581 if ((rv = mod_remove(&modlinkage)) == 0) { 1582 audio_fini_ops(&audigyls_dev_ops); 1583 } 1584 return (rv); 1585 } 1586 1587 int 1588 _info(struct modinfo *modinfop) 1589 { 1590 return (mod_info(&modlinkage, modinfop)); 1591 } 1592 1593 int 1594 audigyls_ddi_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 1595 { 1596 switch (cmd) { 1597 case DDI_ATTACH: 1598 return (audigyls_attach(dip)); 1599 1600 case DDI_RESUME: 1601 return (audigyls_resume(dip)); 1602 1603 default: 1604 return (DDI_FAILURE); 1605 } 1606 } 1607 1608 int 1609 audigyls_ddi_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 1610 { 1611 audigyls_dev_t *dev; 1612 1613 dev = ddi_get_driver_private(dip); 1614 1615 switch (cmd) { 1616 case DDI_DETACH: 1617 return (audigyls_detach(dev)); 1618 1619 case DDI_SUSPEND: 1620 return (audigyls_suspend(dev)); 1621 1622 default: 1623 return (DDI_FAILURE); 1624 } 1625 } 1626 1627 int 1628 audigyls_ddi_quiesce(dev_info_t *dip) 1629 { 1630 audigyls_dev_t *dev; 1631 uint32_t status; 1632 1633 dev = ddi_get_driver_private(dip); 1634 1635 for (int i = 0; i < AUDIGYLS_NUM_PORT; i++) { 1636 1637 audigyls_port_t *port = dev->port[i]; 1638 audigyls_stop_port(port); 1639 } 1640 1641 /* 1642 * Turn off the hardware 1643 */ 1644 1645 write_reg(dev, SA, 0); 1646 OUTL(dev, IER, 0); /* Interrupt disable */ 1647 write_reg(dev, AIE, 0); /* Disable audio interrupts */ 1648 status = INL(dev, IPR); 1649 OUTL(dev, IPR, status); /* Acknowledge */ 1650 return (DDI_SUCCESS); 1651 } 1652