1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 /* 28 * Purpose: Driver for the Creative Audigy LS sound card 29 */ 30 /* 31 * 32 * Copyright (C) 4Front Technologies 1996-2009. 33 */ 34 35 #include <sys/types.h> 36 #include <sys/modctl.h> 37 #include <sys/kmem.h> 38 #include <sys/conf.h> 39 #include <sys/ddi.h> 40 #include <sys/sunddi.h> 41 #include <sys/pci.h> 42 #include <sys/note.h> 43 #include <sys/audio/audio_driver.h> 44 #include <sys/audio/ac97.h> 45 46 #include "audiols.h" 47 48 static struct ddi_device_acc_attr dev_attr = { 49 DDI_DEVICE_ATTR_V0, 50 DDI_STRUCTURE_LE_ACC, 51 DDI_STRICTORDER_ACC 52 }; 53 54 static struct ddi_device_acc_attr buf_attr = { 55 DDI_DEVICE_ATTR_V0, 56 DDI_NEVERSWAP_ACC, 57 DDI_STRICTORDER_ACC 58 }; 59 60 static ddi_dma_attr_t dma_attr_buf = { 61 DMA_ATTR_V0, /* version number */ 62 0x00000000, /* low DMA address range */ 63 0xffffffff, /* high DMA address range */ 64 0x000fffff, /* DMA counter (16 bits only in Audigy LS) */ 65 4, /* DMA address alignment */ 66 0x3c, /* DMA burstsizes */ 67 4, /* min effective DMA size */ 68 0xffffffff, /* max DMA xfer size */ 69 0xffffffff, /* segment boundary */ 70 1, /* s/g length */ 71 4, /* granularity of device */ 72 0 /* Bus specific DMA flags */ 73 }; 74 75 static int audigyls_attach(dev_info_t *); 76 static int audigyls_resume(dev_info_t *); 77 static int audigyls_detach(audigyls_dev_t *); 78 static int audigyls_suspend(audigyls_dev_t *); 79 80 static int audigyls_open(void *, int, unsigned *, unsigned *, caddr_t *); 81 static void audigyls_close(void *); 82 static int audigyls_start(void *); 83 static void audigyls_stop(void *); 84 static int audigyls_format(void *); 85 static int audigyls_channels(void *); 86 static int audigyls_rate(void *); 87 static uint64_t audigyls_count(void *); 88 static void audigyls_sync(void *, unsigned); 89 static size_t audigyls_qlen(void *); 90 static void audigyls_chinfo(void *, int, unsigned *, unsigned *); 91 92 93 static uint16_t audigyls_read_ac97(void *, uint8_t); 94 static void audigyls_write_ac97(void *, uint8_t, uint16_t); 95 static int audigyls_alloc_port(audigyls_dev_t *, int); 96 static void audigyls_start_port(audigyls_port_t *); 97 static void audigyls_stop_port(audigyls_port_t *); 98 static void audigyls_update_port(audigyls_port_t *); 99 static void audigyls_reset_port(audigyls_port_t *); 100 static void audigyls_destroy(audigyls_dev_t *); 101 static int audigyls_setup_intrs(audigyls_dev_t *); 102 static void audigyls_hwinit(audigyls_dev_t *); 103 static uint_t audigyls_intr(caddr_t, caddr_t); 104 static void audigyls_configure_mixer(audigyls_dev_t *dev); 105 106 static audio_engine_ops_t audigyls_engine_ops = { 107 AUDIO_ENGINE_VERSION, 108 audigyls_open, 109 audigyls_close, 110 audigyls_start, 111 audigyls_stop, 112 audigyls_count, 113 audigyls_format, 114 audigyls_channels, 115 audigyls_rate, 116 audigyls_sync, 117 audigyls_qlen, 118 audigyls_chinfo 119 }; 120 121 /* 122 * Audigy LS uses AC'97 strictly for the recording side of things. 123 * While the chip can supposedly route output to AC'97 for playback, 124 * the PCI devices use a separate I2S DAC instead. As a result we 125 * need to suppress controls that the AC'97 codec registers. 126 * 127 * Furthermore, even then the AC'97 codec offers inputs that we just 128 * aren't interested in. 129 */ 130 const char *audigyls_remove_ac97[] = { 131 AUDIO_CTRL_ID_VOLUME, 132 AUDIO_CTRL_ID_LINEOUT, 133 AUDIO_CTRL_ID_HEADPHONE, 134 AUDIO_CTRL_ID_CD, 135 AUDIO_CTRL_ID_VIDEO, 136 AUDIO_CTRL_ID_3DDEPTH, 137 AUDIO_CTRL_ID_3DENHANCE, 138 AUDIO_CTRL_ID_BEEP, 139 AUDIO_CTRL_ID_RECGAIN, 140 AUDIO_CTRL_ID_RECSRC, 141 AUDIO_CTRL_ID_LOOPBACK, 142 NULL, 143 }; 144 145 /* 146 * AC'97 sources we don't want to expose. 147 */ 148 const char *audigyls_badsrcs[] = { 149 AUDIO_PORT_VIDEO, 150 AUDIO_PORT_CD, 151 AUDIO_PORT_STEREOMIX, 152 AUDIO_PORT_MONOMIX, 153 NULL, 154 }; 155 156 static unsigned int 157 read_chan(audigyls_dev_t *dev, int reg, int chn) 158 { 159 uint32_t val; 160 161 mutex_enter(&dev->low_mutex); 162 /* Pointer */ 163 OUTL(dev, PR, (reg << 16) | (chn & 0xffff)); 164 /* Data */ 165 val = INL(dev, DR); 166 mutex_exit(&dev->low_mutex); 167 168 return (val); 169 } 170 171 static void 172 write_chan(audigyls_dev_t *dev, int reg, int chn, uint32_t value) 173 { 174 mutex_enter(&dev->low_mutex); 175 /* Pointer */ 176 OUTL(dev, PR, (reg << 16) | (chn & 0x7)); 177 /* Data */ 178 OUTL(dev, DR, value); 179 mutex_exit(&dev->low_mutex); 180 } 181 182 static unsigned int 183 read_reg(audigyls_dev_t *dev, int reg) 184 { 185 return (read_chan(dev, reg, 0)); 186 } 187 188 static void 189 write_reg(audigyls_dev_t *dev, int reg, uint32_t value) 190 { 191 write_chan(dev, reg, 0, value); 192 } 193 194 195 static uint16_t 196 audigyls_read_ac97(void *arg, uint8_t index) 197 { 198 audigyls_dev_t *dev = arg; 199 uint16_t dtemp = 0; 200 int i; 201 202 mutex_enter(&dev->low_mutex); 203 OUTB(dev, AC97A, index); 204 for (i = 0; i < 10000; i++) { 205 if (INB(dev, AC97A) & 0x80) 206 break; 207 } 208 if (i == 10000) { /* Timeout */ 209 mutex_exit(&dev->low_mutex); 210 return (0xffff); 211 } 212 dtemp = INW(dev, AC97D); 213 mutex_exit(&dev->low_mutex); 214 215 return (dtemp); 216 } 217 218 static void 219 audigyls_write_ac97(void *arg, uint8_t index, uint16_t data) 220 { 221 audigyls_dev_t *dev = arg; 222 int i; 223 224 mutex_enter(&dev->low_mutex); 225 OUTB(dev, AC97A, index); 226 for (i = 0; i < 50000; i++) { 227 if (INB(dev, AC97A) & 0x80) 228 break; 229 } 230 if (i == 50000) { 231 mutex_exit(&dev->low_mutex); 232 return; 233 } 234 OUTW(dev, AC97D, data); 235 mutex_exit(&dev->low_mutex); 236 } 237 238 static void 239 select_digital_enable(audigyls_dev_t *dev, int mode) 240 { 241 /* 242 * Set the out3/spdif combo jack format. 243 * mode0=analog rear/center, 1=spdif 244 */ 245 246 if (mode == 0) { 247 write_reg(dev, SPC, 0x00000f00); 248 } else { 249 write_reg(dev, SPC, 0x0000000f); 250 } 251 } 252 253 /* only for SBLive 7.1 */ 254 int 255 audigyls_i2c_write(audigyls_dev_t *dev, int reg, int data) 256 { 257 int i, timeout, tmp; 258 259 tmp = (reg << 9 | data) << 16; /* set the upper 16 bits */ 260 /* first write the command to the data reg */ 261 write_reg(dev, I2C_1, tmp); 262 for (i = 0; i < 20; i++) { 263 tmp = read_reg(dev, I2C_A) & ~0x6fe; 264 /* see audigyls.pdf for bits */ 265 tmp |= 0x400 | 0x100 | 0x34; 266 write_reg(dev, I2C_A, tmp); 267 /* now wait till controller sets valid bit (0x100) to 0 */ 268 timeout = 0; 269 for (;;) { 270 tmp = read_reg(dev, I2C_A); 271 if ((tmp & 0x100) == 0) 272 break; 273 274 if (timeout > 100) 275 break; 276 277 timeout++; 278 } 279 280 /* transaction aborted */ 281 if (tmp & 0x200) 282 return (0); 283 } 284 return (1); 285 } 286 287 int 288 audigyls_spi_write(audigyls_dev_t *dev, int data) 289 { 290 unsigned int orig; 291 unsigned int tmp; 292 int i, valid; 293 294 tmp = read_reg(dev, SPI); 295 orig = (tmp & ~0x3ffff) | 0x30000; 296 write_reg(dev, SPI, orig | data); 297 valid = 0; 298 /* Wait for status bit to return to 0 */ 299 for (i = 0; i < 1000; i++) { 300 drv_usecwait(100); 301 tmp = read_reg(dev, SPI); 302 if (!(tmp & 0x10000)) { 303 valid = 1; 304 break; 305 } 306 } 307 if (!valid) /* Timed out */ 308 return (0); 309 310 return (1); 311 } 312 313 static void 314 audigyls_update_port(audigyls_port_t *port) 315 { 316 audigyls_dev_t *dev = port->dev; 317 uint32_t offset, n; 318 319 if (dev->suspended) 320 return; 321 322 if (port->direction == AUDIGYLS_PLAY_PORT) { 323 offset = read_chan(dev, CPFA, 0); 324 } else { 325 offset = read_chan(dev, CRFA, 2); 326 } 327 328 329 /* get the offset, and switch to frames */ 330 offset /= (2 * sizeof (uint16_t)); 331 332 if (offset >= port->offset) { 333 n = offset - port->offset; 334 } else { 335 n = offset + (port->buf_frames - port->offset); 336 } 337 port->offset = offset; 338 port->count += n; 339 } 340 341 static void 342 check_play_intr(audigyls_dev_t *dev) 343 { 344 audigyls_port_t *port = dev->port[AUDIGYLS_PLAY_PORT]; 345 346 if (!port->started) 347 return; 348 audio_engine_consume(port->engine); 349 } 350 351 static void 352 check_rec_intr(audigyls_dev_t *dev) 353 { 354 audigyls_port_t *port = dev->port[AUDIGYLS_REC_PORT]; 355 356 if (!port->started) 357 return; 358 audio_engine_produce(port->engine); 359 } 360 361 static uint_t 362 audigyls_intr(caddr_t argp, caddr_t nocare) 363 { 364 audigyls_dev_t *dev = (void *)argp; 365 uint32_t status; 366 367 _NOTE(ARGUNUSED(nocare)); 368 status = INL(dev, IPR); 369 370 if (dev->suspended) { 371 OUTL(dev, IPR, status); /* Acknowledge */ 372 return (DDI_INTR_UNCLAIMED); 373 } 374 375 if (!(status & (INTR_IT1 | INTR_PCI))) { 376 /* No audio interrupts pending */ 377 OUTL(dev, IPR, status); /* Acknowledge */ 378 return (DDI_INTR_UNCLAIMED); 379 } 380 381 check_play_intr(dev); 382 check_rec_intr(dev); 383 384 if (dev->ksp) { 385 AUDIGYLS_KIOP(dev)->intrs[KSTAT_INTR_HARD]++; 386 } 387 388 OUTL(dev, IPR, status); /* Acknowledge */ 389 return (DDI_INTR_CLAIMED); 390 } 391 392 /* 393 * Audio routines 394 */ 395 396 int 397 audigyls_open(void *arg, int flag, 398 unsigned *fragfrp, unsigned *nfragsp, caddr_t *bufp) 399 { 400 audigyls_port_t *port = arg; 401 audigyls_dev_t *dev = port->dev; 402 403 _NOTE(ARGUNUSED(flag)); 404 405 mutex_enter(&dev->mutex); 406 407 port->started = B_FALSE; 408 port->count = 0; 409 *fragfrp = port->fragfr; 410 *nfragsp = AUDIGYLS_NUM_FRAGS; 411 *bufp = port->buf_kaddr; 412 audigyls_reset_port(port); 413 mutex_exit(&dev->mutex); 414 415 return (0); 416 } 417 418 void 419 audigyls_close(void *arg) 420 { 421 audigyls_port_t *port = arg; 422 audigyls_dev_t *dev = port->dev; 423 424 mutex_enter(&dev->mutex); 425 audigyls_stop_port(port); 426 port->started = B_FALSE; 427 mutex_exit(&dev->mutex); 428 } 429 430 int 431 audigyls_start(void *arg) 432 { 433 audigyls_port_t *port = arg; 434 audigyls_dev_t *dev = port->dev; 435 436 mutex_enter(&dev->mutex); 437 if (!port->started) { 438 audigyls_start_port(port); 439 port->started = B_TRUE; 440 } 441 mutex_exit(&dev->mutex); 442 return (0); 443 } 444 445 void 446 audigyls_stop(void *arg) 447 { 448 audigyls_port_t *port = arg; 449 audigyls_dev_t *dev = port->dev; 450 451 mutex_enter(&dev->mutex); 452 if (port->started) { 453 audigyls_stop_port(port); 454 port->started = B_FALSE; 455 } 456 mutex_exit(&dev->mutex); 457 } 458 459 int 460 audigyls_format(void *arg) 461 { 462 _NOTE(ARGUNUSED(arg)); 463 464 return (AUDIO_FORMAT_S16_LE); 465 } 466 467 int 468 audigyls_channels(void *arg) 469 { 470 audigyls_port_t *port = arg; 471 472 return (port->nchan); 473 } 474 475 int 476 audigyls_rate(void *arg) 477 { 478 _NOTE(ARGUNUSED(arg)); 479 480 return (48000); 481 } 482 483 void 484 audigyls_sync(void *arg, unsigned nframes) 485 { 486 audigyls_port_t *port = arg; 487 _NOTE(ARGUNUSED(nframes)); 488 489 (void) ddi_dma_sync(port->buf_dmah, 0, 0, port->syncdir); 490 } 491 492 size_t 493 audigyls_qlen(void *arg) 494 { 495 _NOTE(ARGUNUSED(arg)); 496 return (0); 497 } 498 499 uint64_t 500 audigyls_count(void *arg) 501 { 502 audigyls_port_t *port = arg; 503 audigyls_dev_t *dev = port->dev; 504 uint64_t count; 505 506 mutex_enter(&dev->mutex); 507 if (!dev->suspended) 508 audigyls_update_port(port); 509 count = port->count; 510 mutex_exit(&dev->mutex); 511 return (count); 512 } 513 514 static void 515 audigyls_chinfo(void *arg, int chan, unsigned *offset, unsigned *incr) 516 { 517 audigyls_port_t *port = arg; 518 519 if (port->direction == AUDIGYLS_PLAY_PORT) { 520 *offset = (port->buf_frames * 2 * (chan / 2)) + (chan % 2); 521 *incr = 2; 522 } else { 523 *offset = chan; 524 *incr = 2; 525 } 526 } 527 528 /* private implementation bits */ 529 530 void 531 audigyls_start_port(audigyls_port_t *port) 532 { 533 audigyls_dev_t *dev = port->dev; 534 uint32_t tmp; 535 536 ASSERT(mutex_owned(&dev->mutex)); 537 538 if (dev->suspended || port->active) 539 return; 540 541 port->active = B_TRUE; 542 port->offset = 0; 543 dev->nactive++; 544 545 if (dev->nactive == 1) { 546 write_reg(dev, IT, dev->timer); 547 OUTL(dev, IER, INL(dev, IER) | INTR_IT1); 548 } 549 550 switch (port->direction) { 551 case AUDIGYLS_PLAY_PORT: 552 tmp = read_reg(dev, SA); 553 tmp |= SA_SPA(0); 554 tmp |= SA_SPA(1); 555 tmp |= SA_SPA(3); 556 write_reg(dev, SA, tmp); 557 break; 558 559 case AUDIGYLS_REC_PORT: 560 tmp = read_reg(dev, SA); 561 tmp |= SA_SRA(2); 562 write_reg(dev, SA, tmp); 563 break; 564 } 565 566 } 567 568 void 569 audigyls_stop_port(audigyls_port_t *port) 570 { 571 audigyls_dev_t *dev = port->dev; 572 uint32_t tmp; 573 574 if (dev->suspended || !port->active) 575 return; 576 577 port->active = B_FALSE; 578 dev->nactive--; 579 580 switch (port->direction) { 581 case AUDIGYLS_PLAY_PORT: 582 tmp = read_reg(dev, SA); 583 tmp &= ~SA_SPA(0); 584 tmp &= ~SA_SPA(1); 585 tmp &= ~SA_SPA(3); 586 write_reg(dev, SA, tmp); 587 break; 588 589 case AUDIGYLS_REC_PORT: 590 tmp = read_reg(dev, SA); 591 tmp &= ~SA_SRA(2); 592 write_reg(dev, SA, tmp); 593 break; 594 } 595 596 if (dev->nactive == 0) { 597 OUTL(dev, IER, INL(dev, IER) & ~INTR_IT1); 598 } 599 } 600 601 void 602 audigyls_reset_port(audigyls_port_t *port) 603 { 604 audigyls_dev_t *dev = port->dev; 605 606 ASSERT(mutex_owned(&dev->mutex)); 607 608 if (dev->suspended) 609 return; 610 611 switch (port->direction) { 612 case AUDIGYLS_PLAY_PORT: 613 write_chan(dev, PTCA, 0, 0); 614 write_chan(dev, CPFA, 0, 0); 615 write_chan(dev, CPCAV, 0, 0); 616 write_chan(dev, PTCA, 1, 0); 617 write_chan(dev, CPFA, 1, 0); 618 write_chan(dev, CPCAV, 1, 0); 619 write_chan(dev, PTCA, 3, 0); 620 write_chan(dev, CPFA, 3, 0); 621 write_chan(dev, CPCAV, 3, 0); 622 break; 623 624 case AUDIGYLS_REC_PORT: 625 write_chan(dev, CRFA, 2, 0); 626 write_chan(dev, CRCAV, 2, 0); 627 break; 628 } 629 } 630 631 int 632 audigyls_alloc_port(audigyls_dev_t *dev, int num) 633 { 634 audigyls_port_t *port; 635 size_t len; 636 ddi_dma_cookie_t cookie; 637 uint_t count; 638 int dir; 639 unsigned caps; 640 audio_dev_t *adev; 641 642 adev = dev->adev; 643 port = kmem_zalloc(sizeof (*port), KM_SLEEP); 644 dev->port[num] = port; 645 port->dev = dev; 646 port->started = B_FALSE; 647 port->direction = num; 648 649 switch (num) { 650 case AUDIGYLS_REC_PORT: 651 port->syncdir = DDI_DMA_SYNC_FORKERNEL; 652 caps = ENGINE_INPUT_CAP; 653 dir = DDI_DMA_READ; 654 port->nchan = 2; 655 break; 656 case AUDIGYLS_PLAY_PORT: 657 port->syncdir = DDI_DMA_SYNC_FORDEV; 658 caps = ENGINE_OUTPUT_CAP; 659 dir = DDI_DMA_WRITE; 660 port->nchan = 6; 661 break; 662 default: 663 return (DDI_FAILURE); 664 } 665 666 /* figure out fragment configuration */ 667 port->fragfr = 48000 / dev->intrs; 668 /* we want to make sure that we are aligning on reasonable chunks */ 669 port->fragfr = (port->fragfr + 63) & ~(63); 670 671 /* 16 bit frames */ 672 port->fragsz = port->fragfr * 2 * port->nchan; 673 port->buf_size = port->fragsz * AUDIGYLS_NUM_FRAGS; 674 port->buf_frames = port->fragfr * AUDIGYLS_NUM_FRAGS; 675 676 /* Alloc buffers */ 677 if (ddi_dma_alloc_handle(dev->dip, &dma_attr_buf, DDI_DMA_SLEEP, NULL, 678 &port->buf_dmah) != DDI_SUCCESS) { 679 audio_dev_warn(adev, "failed to allocate BUF handle"); 680 return (DDI_FAILURE); 681 } 682 683 if (ddi_dma_mem_alloc(port->buf_dmah, port->buf_size, 684 &buf_attr, DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, 685 &port->buf_kaddr, &len, &port->buf_acch) != DDI_SUCCESS) { 686 audio_dev_warn(adev, "failed to allocate BUF memory"); 687 return (DDI_FAILURE); 688 } 689 690 if (ddi_dma_addr_bind_handle(port->buf_dmah, NULL, port->buf_kaddr, 691 len, DDI_DMA_CONSISTENT | dir, DDI_DMA_SLEEP, NULL, &cookie, 692 &count) != DDI_SUCCESS) { 693 audio_dev_warn(adev, "failed binding BUF DMA handle"); 694 return (DDI_FAILURE); 695 } 696 port->buf_paddr = cookie.dmac_address; 697 698 port->engine = audio_engine_alloc(&audigyls_engine_ops, caps); 699 if (port->engine == NULL) { 700 audio_dev_warn(adev, "audio_engine_alloc failed"); 701 return (DDI_FAILURE); 702 } 703 704 audio_engine_set_private(port->engine, port); 705 audio_dev_add_engine(adev, port->engine); 706 707 return (DDI_SUCCESS); 708 } 709 710 int 711 audigyls_setup_intrs(audigyls_dev_t *dev) 712 { 713 uint_t ipri; 714 int actual; 715 int rv; 716 ddi_intr_handle_t ih[1]; 717 718 rv = ddi_intr_alloc(dev->dip, ih, DDI_INTR_TYPE_FIXED, 719 0, 1, &actual, DDI_INTR_ALLOC_STRICT); 720 if ((rv != DDI_SUCCESS) || (actual != 1)) { 721 audio_dev_warn(dev->adev, 722 "Can't alloc interrupt handle (rv %d actual %d)", 723 rv, actual); 724 return (DDI_FAILURE); 725 } 726 727 if (ddi_intr_get_pri(ih[0], &ipri) != DDI_SUCCESS) { 728 audio_dev_warn(dev->adev, "Can't get interrupt priority"); 729 (void) ddi_intr_free(ih[0]); 730 return (DDI_FAILURE); 731 } 732 733 if (ddi_intr_add_handler(ih[0], audigyls_intr, dev, NULL) != 734 DDI_SUCCESS) { 735 audio_dev_warn(dev->adev, "Can't add interrupt handler"); 736 (void) ddi_intr_free(ih[0]); 737 return (DDI_FAILURE); 738 } 739 740 dev->ih = ih[0]; 741 mutex_init(&dev->mutex, NULL, MUTEX_DRIVER, DDI_INTR_PRI(ipri)); 742 mutex_init(&dev->low_mutex, NULL, MUTEX_DRIVER, DDI_INTR_PRI(ipri)); 743 return (DDI_SUCCESS); 744 } 745 746 void 747 audigyls_destroy(audigyls_dev_t *dev) 748 { 749 if (dev->ih != NULL) { 750 (void) ddi_intr_disable(dev->ih); 751 (void) ddi_intr_remove_handler(dev->ih); 752 (void) ddi_intr_free(dev->ih); 753 mutex_destroy(&dev->mutex); 754 mutex_destroy(&dev->low_mutex); 755 } 756 757 if (dev->ksp) { 758 kstat_delete(dev->ksp); 759 } 760 761 for (int i = 0; i < AUDIGYLS_NUM_PORT; i++) { 762 audigyls_port_t *port = dev->port[i]; 763 if (!port) 764 continue; 765 if (port->engine) { 766 audio_dev_remove_engine(dev->adev, port->engine); 767 audio_engine_free(port->engine); 768 } 769 if (port->buf_paddr) { 770 (void) ddi_dma_unbind_handle(port->buf_dmah); 771 } 772 if (port->buf_acch) { 773 ddi_dma_mem_free(&port->buf_acch); 774 } 775 if (port->buf_dmah) { 776 ddi_dma_free_handle(&port->buf_dmah); 777 } 778 kmem_free(port, sizeof (*port)); 779 } 780 781 if (dev->ac97 != NULL) { 782 ac97_free(dev->ac97); 783 } 784 if (dev->adev != NULL) { 785 audio_dev_free(dev->adev); 786 } 787 if (dev->regsh != NULL) { 788 ddi_regs_map_free(&dev->regsh); 789 } 790 if (dev->pcih != NULL) { 791 pci_config_teardown(&dev->pcih); 792 } 793 kmem_free(dev, sizeof (*dev)); 794 } 795 796 void 797 audigyls_hwinit(audigyls_dev_t *dev) 798 { 799 static unsigned int spi_dac[] = { 800 0x00ff, 0x02ff, 0x0400, 0x520, 0x0620, 0x08ff, 0x0aff, 0x0cff, 801 0x0eff, 0x10ff, 0x1200, 0x1400, 0x1800, 0x1aff, 0x1cff, 802 0x1e00, 0x0530, 0x0602, 0x0622, 0x1400, 803 }; 804 805 uint32_t tmp; 806 int i, tries; 807 uint32_t paddr; 808 uint32_t chunksz; 809 audigyls_port_t *port; 810 811 812 /* Set the orange jack to be analog out or S/PDIF */ 813 select_digital_enable(dev, dev->digital_enable); 814 815 /* 816 * In P17, there's 8 GPIO pins. 817 * GPIO register: 0x00XXYYZZ 818 * XX: Configure GPIO to be either GPI (0) or GPO (1). 819 * YY: GPO values, applicable if the pin is configure to be GPO. 820 * ZZ: GPI values, applicable if the pin is configure to be GPI. 821 * 822 * in SB570, pin 0-4 and 6 is used as GPO and pin 5 and 7 is 823 * used as GPI. 824 * 825 * GPO0: 826 * 1 ==> Analog output 827 * 0 ==> Digital output 828 * GPO1: 829 * 1 ==> Enable output on card 830 * 0 ==> Disable output on card 831 * GPO2: 832 * 1 ==> Enable Mic Bias and Mic Path 833 * 0 ==> Disable Mic Bias and Mic Path 834 * GPO3: 835 * 1 ==> Disable SPDIF-IO output 836 * 0 ==> Enable SPDIF-IO output 837 * GPO4 and GPO6: 838 * DAC sampling rate selection: 839 * Not applicable to SB570 since DAC is controlled through SPI 840 * GPI5: 841 * 1 ==> Front Panel is not connected 842 * 0 ==> Front Panel is connected 843 * GPI7: 844 * 1 ==> Front Panel Headphone is not connected 845 * 0 ==> Front Panel Headphone is connected 846 */ 847 if (dev->ac97) 848 OUTL(dev, GPIO, 0x005f03a3); 849 else { 850 /* for SBLive 7.1 */ 851 OUTL(dev, GPIO, 0x005f4301); 852 853 audigyls_i2c_write(dev, 0x15, 0x2); 854 tries = 0; 855 again: 856 for (i = 0; i < sizeof (spi_dac); i++) { 857 if (!audigyls_spi_write(dev, spi_dac[i]) && 858 tries < 100) { 859 tries++; 860 goto again; 861 } 862 } 863 } 864 865 OUTL(dev, IER, INTR_PCI); 866 OUTL(dev, HC, 0x00000009); /* Enable audio, use 48 kHz */ 867 868 tmp = read_chan(dev, SRCTL, 0); 869 if (dev->ac97) 870 tmp |= 0xf0c81000; /* Record src0/src1 from ac97 */ 871 else 872 tmp |= 0x50c81000; /* Record src0/src1 from I2SIN */ 873 tmp &= ~0x0303c00f; /* Set sample rates to 48 kHz */ 874 write_chan(dev, SRCTL, 0, tmp); 875 876 write_reg(dev, HMIXMAP_I2S, 0x76543210); /* Default out route */ 877 write_reg(dev, AUDCTL, 0x0f0f003f); /* Enable all outputs */ 878 879 /* All audio stopped! */ 880 write_reg(dev, SA, 0); 881 882 for (i = 0; i < 4; i++) { 883 /* 884 * Reset DMA pointers and counters. Note that we do 885 * not use scatter/gather. 886 */ 887 write_chan(dev, PTBA, i, 0); 888 write_chan(dev, PTBS, i, 0); 889 write_chan(dev, PTCA, i, 0); 890 891 write_chan(dev, CPFA, i, 0); 892 write_chan(dev, PFEA, i, 0); 893 write_chan(dev, CPCAV, i, 0); 894 895 write_chan(dev, CRFA, i, 0); 896 write_chan(dev, CRCAV, i, 0); 897 } 898 899 /* 900 * The 5.1 play port made up channels 0, 1, and 3. The record 901 * port is channel 2. 902 */ 903 port = dev->port[AUDIGYLS_PLAY_PORT]; 904 paddr = port->buf_paddr; 905 chunksz = port->buf_frames * 4; 906 write_chan(dev, PFBA, 0, paddr); 907 write_chan(dev, PFBS, 0, chunksz << 16); 908 paddr += chunksz; 909 write_chan(dev, PFBA, 1, paddr); 910 write_chan(dev, PFBS, 1, chunksz << 16); 911 paddr += chunksz; 912 write_chan(dev, PFBA, 3, paddr); 913 write_chan(dev, PFBS, 3, chunksz << 16); 914 915 /* Record */ 916 port = dev->port[AUDIGYLS_REC_PORT]; 917 paddr = port->buf_paddr; 918 chunksz = port->buf_frames * 4; 919 write_chan(dev, RFBA, 2, paddr); 920 write_chan(dev, RFBS, 2, chunksz << 16); 921 922 /* Set sample rates to 48 kHz. */ 923 tmp = read_chan(dev, SRCTL, 0) & ~0x0303c00f; 924 write_chan(dev, SRCTL, 0, tmp); 925 926 write_reg(dev, SCS0, 0x02108004); /* Audio */ 927 write_reg(dev, SCS1, 0x02108004); /* Audio */ 928 write_reg(dev, SCS2, 0x02108004); /* Audio */ 929 write_reg(dev, SCS3, 0x02108004); /* Audio */ 930 } 931 932 #define PLAYCTL (AUDIO_CTRL_FLAG_RW | AUDIO_CTRL_FLAG_PLAY) 933 #define RECCTL (AUDIO_CTRL_FLAG_RW | AUDIO_CTRL_FLAG_REC) 934 #define MONCTL (AUDIO_CTRL_FLAG_RW | AUDIO_CTRL_FLAG_MONITOR) 935 #define PCMVOL (PLAYCTL | AUDIO_CTRL_FLAG_PCMVOL) 936 #define MAINVOL (PLAYCTL | AUDIO_CTRL_FLAG_MAINVOL) 937 #define RECVOL (RECCTL | AUDIO_CTRL_FLAG_RECVOL) 938 #define MONVOL (MONCTL | AUDIO_CTRL_FLAG_MONVOL) 939 940 #define MASK(nbits) ((1 << (nbits)) - 1) 941 #define SCALE(val, nbits) \ 942 ((uint8_t)((((val) * MASK(nbits)) / 100)) << (8 - (nbits))) 943 944 static uint32_t 945 audigyls_stereo_scale(uint32_t value, uint8_t bits) 946 { 947 uint8_t left, right; 948 uint32_t val; 949 950 left = (value >> 8) & 0xff; 951 right = value & 0xff; 952 953 val = (((left * ((1 << bits) - 1) / 100) << 8) | 954 (right * ((1 << bits) - 1) / 100)); 955 return (val); 956 } 957 958 static void 959 audigyls_configure_mixer(audigyls_dev_t *dev) 960 { 961 unsigned int r, v1, v2; 962 963 ASSERT(mutex_owned(&dev->mutex)); 964 965 /* output items */ 966 /* front */ 967 r = 0xffff - audigyls_stereo_scale(dev->controls[CTL_FRONT].val, 8); 968 r = (r << 16) | r; 969 write_chan(dev, MIXVOL_I2S, 0, r); 970 971 /* surround */ 972 r = 0xffff - audigyls_stereo_scale(dev->controls[CTL_SURROUND].val, 8); 973 r = (r << 16) | r; 974 write_chan(dev, MIXVOL_I2S, 3, r); 975 976 /* center/lfe */ 977 v1 = 255 - SCALE(dev->controls[CTL_CENTER].val, 8); 978 v2 = 255 - SCALE(dev->controls[CTL_LFE].val, 8); 979 r = (v1 << 8) | v2; 980 r = (r << 16) | r; 981 write_chan(dev, MIXVOL_I2S, 1, r); 982 983 /* spread */ 984 r = dev->controls[CTL_SPREAD].val ? 0x10101010 : 0x76543210; 985 write_reg(dev, HMIXMAP_I2S, r); 986 987 /* input items */ 988 989 /* recgain */ 990 v1 = dev->controls[CTL_RECORDVOL].val; 991 if (dev->ac97_recgain && !dev->controls[CTL_LOOP].val) { 992 /* 993 * For AC'97, we use the AC'97 record gain, unless we are 994 * in loopback. 995 */ 996 ac97_control_set(dev->ac97_recgain, v1); 997 write_reg(dev, P17RECVOLL, 0x30303030); 998 write_reg(dev, P17RECVOLH, 0x30303030); 999 } else { 1000 /* 1001 * Otherwise we set the P17 gain. 1002 */ 1003 r = 0xffff - audigyls_stereo_scale(v1, 8); 1004 r = r << 16 | r; 1005 write_reg(dev, P17RECVOLL, r); 1006 write_reg(dev, P17RECVOLH, r); 1007 } 1008 1009 /* monitor gain */ 1010 if (dev->ac97) { 1011 /* AC'97 monitor gain is done by the AC'97 codec */ 1012 write_chan(dev, SRCTL, 1, 0x30303030); 1013 write_reg(dev, SMIXMAP_I2S, 0x10101076); 1014 } else { 1015 /* For non-AC'97 devices, just a single master monitor gain */ 1016 r = 255 - SCALE(dev->controls[CTL_MONGAIN].val, 8); 1017 write_chan(dev, SRCTL, 1, 0xffff0000 | r << 8 | r); 1018 if (r != 0xff) { 1019 write_reg(dev, SMIXMAP_I2S, 0x10101076); 1020 } else { 1021 write_reg(dev, SMIXMAP_I2S, 0x10101010); 1022 } 1023 } 1024 1025 /* record source */ 1026 if (dev->ac97_recsrc != NULL) { 1027 ac97_control_set(dev->ac97_recsrc, 1028 dev->controls[CTL_RECSRC].val); 1029 v1 = RECSEL_AC97; /* Audigy LS */ 1030 } else { 1031 switch (dev->controls[CTL_RECSRC].val) { 1032 case 1: 1033 audigyls_i2c_write(dev, 0x15, 0x2); /* Mic */ 1034 OUTL(dev, GPIO, INL(dev, GPIO) | 0x400); 1035 break; 1036 1037 case 2: 1038 audigyls_i2c_write(dev, 0x15, 0x4); /* Line */ 1039 OUTL(dev, GPIO, INL(dev, GPIO) & ~0x400); 1040 break; 1041 } 1042 v1 = RECSEL_I2SIN; /* SB 7.1 value */ 1043 } 1044 1045 /* If loopback, record what you hear instead */ 1046 1047 if (dev->controls[CTL_LOOP].val) { 1048 r = 0; 1049 v1 = RECSEL_I2SOUT; 1050 r |= (v1 << 28) | (v1 << 24) | (v1 << 20) | (v1 << 16) | v2; 1051 } else { 1052 /* 1053 * You'd think this would be the same as the logic 1054 * above, but experience shows that what you need for 1055 * loopback is different. This whole thing looks 1056 * particularly fishy to me. I suspect someone has 1057 * made a mistake somewhere. But I can't seem to 1058 * figure out where it lies. 1059 */ 1060 r = 0xe4; 1061 for (int i = 0; i < 4; i++) 1062 r |= v1 << (16 + i * 3); /* Select input */ 1063 } 1064 1065 write_reg(dev, P17RECSEL, r); 1066 } 1067 1068 static int 1069 audigyls_set_control(void *arg, uint64_t val) 1070 { 1071 audigyls_ctrl_t *pc = arg; 1072 audigyls_dev_t *dev = pc->dev; 1073 1074 switch (pc->num) { 1075 1076 case CTL_FRONT: 1077 case CTL_SURROUND: 1078 case CTL_RECORDVOL: 1079 if (((val & 0xff) > 100) || 1080 (((val & 0xff00) >> 8) > 100) || 1081 ((val & ~0xffff) != 0)) { 1082 return (EINVAL); 1083 } 1084 break; 1085 1086 case CTL_CENTER: 1087 case CTL_LFE: 1088 case CTL_MONGAIN: 1089 if (val > 100) { 1090 return (EINVAL); 1091 } 1092 break; 1093 1094 case CTL_RECSRC: 1095 if (((1U << val) & (dev->recmask)) == 0) { 1096 return (EINVAL); 1097 } 1098 break; 1099 1100 case CTL_SPREAD: 1101 case CTL_LOOP: 1102 switch (val) { 1103 case 0: 1104 case 1: 1105 break; 1106 default: 1107 return (EINVAL); 1108 } 1109 } 1110 1111 mutex_enter(&dev->mutex); 1112 pc->val = val; 1113 if (!dev->suspended) { 1114 audigyls_configure_mixer(dev); 1115 } 1116 mutex_exit(&dev->mutex); 1117 1118 return (0); 1119 } 1120 1121 static int 1122 audigyls_get_control(void *arg, uint64_t *val) 1123 { 1124 audigyls_ctrl_t *pc = arg; 1125 audigyls_dev_t *dev = pc->dev; 1126 1127 mutex_enter(&dev->mutex); 1128 *val = pc->val; 1129 mutex_exit(&dev->mutex); 1130 return (0); 1131 } 1132 1133 static void 1134 audigyls_alloc_ctrl(audigyls_dev_t *dev, uint32_t num, uint64_t val) 1135 { 1136 audio_ctrl_desc_t desc; 1137 audigyls_ctrl_t *pc; 1138 1139 bzero(&desc, sizeof (desc)); 1140 1141 pc = &dev->controls[num]; 1142 pc->num = num; 1143 pc->dev = dev; 1144 1145 1146 switch (num) { 1147 case CTL_FRONT: 1148 desc.acd_name = AUDIO_CTRL_ID_FRONT; 1149 desc.acd_type = AUDIO_CTRL_TYPE_STEREO; 1150 desc.acd_minvalue = 0; 1151 desc.acd_maxvalue = 100; 1152 desc.acd_flags = MAINVOL; 1153 break; 1154 1155 case CTL_SURROUND: 1156 desc.acd_name = AUDIO_CTRL_ID_SURROUND; 1157 desc.acd_type = AUDIO_CTRL_TYPE_STEREO; 1158 desc.acd_minvalue = 0; 1159 desc.acd_maxvalue = 100; 1160 desc.acd_flags = MAINVOL; 1161 break; 1162 1163 case CTL_CENTER: 1164 desc.acd_name = AUDIO_CTRL_ID_CENTER; 1165 desc.acd_type = AUDIO_CTRL_TYPE_MONO; 1166 desc.acd_minvalue = 0; 1167 desc.acd_maxvalue = 100; 1168 desc.acd_flags = MAINVOL; 1169 break; 1170 1171 case CTL_LFE: 1172 desc.acd_name = AUDIO_CTRL_ID_LFE; 1173 desc.acd_type = AUDIO_CTRL_TYPE_MONO; 1174 desc.acd_minvalue = 0; 1175 desc.acd_maxvalue = 100; 1176 desc.acd_flags = MAINVOL; 1177 break; 1178 1179 case CTL_RECORDVOL: 1180 desc.acd_name = AUDIO_CTRL_ID_RECGAIN; 1181 desc.acd_type = AUDIO_CTRL_TYPE_STEREO; 1182 desc.acd_minvalue = 0; 1183 desc.acd_maxvalue = 100; 1184 desc.acd_flags = RECVOL; 1185 break; 1186 1187 case CTL_RECSRC: 1188 desc.acd_name = AUDIO_CTRL_ID_RECSRC; 1189 desc.acd_type = AUDIO_CTRL_TYPE_ENUM; 1190 desc.acd_flags = RECCTL; 1191 1192 /* 1193 * For AC'97 devices, we want to expose the reasonable 1194 * AC'97 input sources, but suppress the stereomix, 1195 * because we use loopback instead. 1196 */ 1197 if (dev->ac97_recsrc) { 1198 int i, j; 1199 const char *n; 1200 const audio_ctrl_desc_t *adp; 1201 1202 adp = ac97_control_desc(dev->ac97_recsrc); 1203 for (i = 0; i < 64; i++) { 1204 n = adp->acd_enum[i]; 1205 1206 if (((adp->acd_minvalue & (1 << i)) == 0) || 1207 (n == NULL)) { 1208 continue; 1209 } 1210 for (j = 0; audigyls_badsrcs[j]; j++) { 1211 if (strcmp(n, audigyls_badsrcs[j]) 1212 == 0) { 1213 n = NULL; 1214 break; 1215 } 1216 } 1217 if (n) { 1218 desc.acd_enum[i] = n; 1219 dev->recmask |= (1 << i); 1220 } 1221 } 1222 desc.acd_minvalue = desc.acd_maxvalue = dev->recmask; 1223 } else { 1224 dev->recmask = 3; 1225 desc.acd_minvalue = 3; 1226 desc.acd_maxvalue = 3; 1227 desc.acd_enum[0] = AUDIO_PORT_MIC; 1228 desc.acd_enum[1] = AUDIO_PORT_LINEIN; 1229 } 1230 break; 1231 1232 case CTL_MONGAIN: 1233 ASSERT(!dev->ac97); 1234 desc.acd_name = AUDIO_CTRL_ID_MONGAIN; 1235 desc.acd_type = AUDIO_CTRL_TYPE_MONO; 1236 desc.acd_minvalue = 0; 1237 desc.acd_maxvalue = 100; 1238 desc.acd_flags = MONVOL; 1239 break; 1240 1241 case CTL_SPREAD: 1242 desc.acd_name = AUDIO_CTRL_ID_SPREAD; 1243 desc.acd_type = AUDIO_CTRL_TYPE_BOOLEAN; 1244 desc.acd_minvalue = 0; 1245 desc.acd_maxvalue = 1; 1246 desc.acd_flags = PLAYCTL; 1247 break; 1248 1249 case CTL_LOOP: 1250 desc.acd_name = AUDIO_CTRL_ID_LOOPBACK; 1251 desc.acd_type = AUDIO_CTRL_TYPE_BOOLEAN; 1252 desc.acd_minvalue = 0; 1253 desc.acd_maxvalue = 1; 1254 desc.acd_flags = RECCTL; 1255 break; 1256 } 1257 1258 pc->val = val; 1259 pc->ctrl = audio_dev_add_control(dev->adev, &desc, 1260 audigyls_get_control, audigyls_set_control, pc); 1261 } 1262 1263 static int 1264 audigyls_add_controls(audigyls_dev_t *dev) 1265 { 1266 (void) audio_dev_add_soft_volume(dev->adev); 1267 1268 audigyls_alloc_ctrl(dev, CTL_FRONT, 75 | (75 << 8)); 1269 audigyls_alloc_ctrl(dev, CTL_SURROUND, 75 | (75 << 8)); 1270 audigyls_alloc_ctrl(dev, CTL_CENTER, 75); 1271 audigyls_alloc_ctrl(dev, CTL_LFE, 75); 1272 audigyls_alloc_ctrl(dev, CTL_RECORDVOL, 75 | (75 << 8)); 1273 audigyls_alloc_ctrl(dev, CTL_RECSRC, 1); 1274 audigyls_alloc_ctrl(dev, CTL_SPREAD, 0); 1275 audigyls_alloc_ctrl(dev, CTL_LOOP, 0); 1276 if (!dev->ac97) { 1277 audigyls_alloc_ctrl(dev, CTL_MONGAIN, 0); 1278 } 1279 1280 return (DDI_SUCCESS); 1281 } 1282 1283 int 1284 audigyls_attach(dev_info_t *dip) 1285 { 1286 uint16_t pci_command, vendor, device; 1287 uint32_t subdevice; 1288 audigyls_dev_t *dev; 1289 ddi_acc_handle_t pcih; 1290 const char *name, *version; 1291 boolean_t ac97 = B_FALSE; 1292 1293 dev = kmem_zalloc(sizeof (*dev), KM_SLEEP); 1294 dev->dip = dip; 1295 ddi_set_driver_private(dip, dev); 1296 1297 if ((dev->adev = audio_dev_alloc(dip, 0)) == NULL) { 1298 cmn_err(CE_WARN, "audio_dev_alloc failed"); 1299 goto error; 1300 } 1301 1302 if (pci_config_setup(dip, &pcih) != DDI_SUCCESS) { 1303 audio_dev_warn(dev->adev, "pci_config_setup failed"); 1304 goto error; 1305 } 1306 dev->pcih = pcih; 1307 1308 vendor = pci_config_get16(pcih, PCI_CONF_VENID); 1309 device = pci_config_get16(pcih, PCI_CONF_DEVID); 1310 subdevice = pci_config_get16(pcih, PCI_CONF_SUBVENID); 1311 subdevice <<= 16; 1312 subdevice |= pci_config_get16(pcih, PCI_CONF_SUBSYSID); 1313 if (vendor != PCI_VENDOR_ID_CREATIVE || 1314 device != PCI_DEVICE_ID_CREATIVE_AUDIGYLS) { 1315 audio_dev_warn(dev->adev, "Hardware not recognized " 1316 "(vendor=%x, dev=%x)", vendor, device); 1317 goto error; 1318 } 1319 1320 pci_command = pci_config_get16(pcih, PCI_CONF_COMM); 1321 pci_command |= PCI_COMM_ME | PCI_COMM_IO; 1322 pci_config_put16(pcih, PCI_CONF_COMM, pci_command); 1323 1324 if ((ddi_regs_map_setup(dip, 1, &dev->base, 0, 0, &dev_attr, 1325 &dev->regsh)) != DDI_SUCCESS) { 1326 audio_dev_warn(dev->adev, "failed to map registers"); 1327 goto error; 1328 } 1329 1330 /* Function of the orange jack: 0=analog, 1=digital */ 1331 dev->digital_enable = ddi_prop_get_int(DDI_DEV_T_ANY, dev->dip, 1332 DDI_PROP_DONTPASS, "digital-enable", 0); 1333 1334 if (audigyls_setup_intrs(dev) != DDI_SUCCESS) 1335 goto error; 1336 1337 dev->intrs = ddi_prop_get_int(DDI_DEV_T_ANY, dev->dip, 1338 DDI_PROP_DONTPASS, "interrupt-rate", AUDIGYLS_INTRS); 1339 1340 /* make sure the values are good */ 1341 if (dev->intrs < AUDIGYLS_MIN_INTRS) { 1342 audio_dev_warn(dev->adev, 1343 "interrupt-rate too low, %d, reset to %d", 1344 dev->intrs, AUDIGYLS_INTRS); 1345 dev->intrs = AUDIGYLS_INTRS; 1346 } else if (dev->intrs > AUDIGYLS_MAX_INTRS) { 1347 audio_dev_warn(dev->adev, 1348 "interrupt-rate too high, %d, reset to %d", 1349 dev->intrs, AUDIGYLS_INTRS); 1350 dev->intrs = AUDIGYLS_INTRS; 1351 } 1352 1353 dev->timer = (192000 / dev->intrs) << 16; 1354 1355 switch (subdevice) { 1356 case 0x11021001: /* SB0310 */ 1357 case 0x11021002: /* SB0310 */ 1358 case 0x11021005: /* SB0310b */ 1359 name = "Creative Audigy LS"; 1360 version = "SB0310"; /* could also be SB0312 */ 1361 ac97 = B_TRUE; 1362 break; 1363 case 0x11021006: 1364 name = "Creative Sound Blaster Live! 24 bit"; 1365 version = "SB0410"; 1366 break; 1367 case 0x11021007: /* Dell OEM version */ 1368 name = "Creative Sound Blaster Live! 24 bit"; 1369 version = "SB0413"; 1370 break; 1371 case 0x1102100a: 1372 name = "Creative Audigy SE"; 1373 version = "SB0570"; 1374 break; 1375 case 0x11021011: 1376 name = "Creative Audigy SE OEM"; 1377 version = "SB0570a"; 1378 break; 1379 case 0x11021012: 1380 name = "Creative X-Fi Extreme Audio"; 1381 version = "SB0790"; 1382 break; 1383 case 0x14621009: 1384 name = "MSI K8N Diamond MB"; 1385 version = "SB0438"; 1386 break; 1387 case 0x12973038: 1388 name = "Shuttle XPC SD31P"; 1389 version = "SD31P"; 1390 break; 1391 case 0x12973041: 1392 name = "Shuttle XPC SD11G5"; 1393 version = "SD11G5"; 1394 break; 1395 default: 1396 name = "Creative Audigy LS"; 1397 version = NULL; 1398 break; 1399 } 1400 1401 audio_dev_set_description(dev->adev, name); 1402 if (version) 1403 audio_dev_set_version(dev->adev, version); 1404 1405 if (ac97) { 1406 ac97_ctrl_t *ctrl; 1407 1408 /* Original Audigy LS revision (AC97 based) */ 1409 dev->ac97 = ac97_allocate(dev->adev, dip, 1410 audigyls_read_ac97, audigyls_write_ac97, dev); 1411 if (dev->ac97 == NULL) { 1412 audio_dev_warn(dev->adev, 1413 "failed to allocate ac97 handle"); 1414 goto error; 1415 } 1416 1417 ac97_probe_controls(dev->ac97); 1418 1419 /* remove the AC'97 controls we don't want to expose */ 1420 for (int i = 0; audigyls_remove_ac97[i]; i++) { 1421 ctrl = ac97_control_find(dev->ac97, 1422 audigyls_remove_ac97[i]); 1423 if (ctrl != NULL) { 1424 ac97_control_unregister(ctrl); 1425 } 1426 } 1427 1428 dev->ac97_recgain = ac97_control_find(dev->ac97, 1429 AUDIO_CTRL_ID_RECGAIN); 1430 dev->ac97_recsrc = ac97_control_find(dev->ac97, 1431 AUDIO_CTRL_ID_RECSRC); 1432 } 1433 1434 audigyls_add_controls(dev); 1435 1436 if (dev->ac97) { 1437 ac97_register_controls(dev->ac97); 1438 } 1439 1440 if (audigyls_alloc_port(dev, AUDIGYLS_PLAY_PORT) != DDI_SUCCESS) 1441 goto error; 1442 if (audigyls_alloc_port(dev, AUDIGYLS_REC_PORT) != DDI_SUCCESS) 1443 goto error; 1444 1445 audigyls_hwinit(dev); 1446 1447 audigyls_configure_mixer(dev); 1448 1449 /* set up kernel statistics */ 1450 if ((dev->ksp = kstat_create(AUDIGYLS_NAME, ddi_get_instance(dip), 1451 AUDIGYLS_NAME, "controller", KSTAT_TYPE_INTR, 1, 1452 KSTAT_FLAG_PERSISTENT)) != NULL) { 1453 kstat_install(dev->ksp); 1454 } 1455 1456 if (audio_dev_register(dev->adev) != DDI_SUCCESS) { 1457 audio_dev_warn(dev->adev, "unable to register with framework"); 1458 goto error; 1459 } 1460 1461 (void) ddi_intr_enable(dev->ih); 1462 ddi_report_dev(dip); 1463 1464 return (DDI_SUCCESS); 1465 1466 error: 1467 audigyls_destroy(dev); 1468 return (DDI_FAILURE); 1469 } 1470 1471 int 1472 audigyls_resume(dev_info_t *dip) 1473 { 1474 audigyls_dev_t *dev; 1475 audigyls_port_t *port; 1476 1477 dev = ddi_get_driver_private(dip); 1478 1479 for (int i = 0; i < AUDIGYLS_NUM_PORT; i++) { 1480 port = dev->port[i]; 1481 audio_engine_reset(port->engine); 1482 } 1483 1484 audigyls_hwinit(dev); 1485 1486 /* allow ac97 operations again */ 1487 if (dev->ac97) 1488 ac97_resume(dev->ac97); 1489 1490 audigyls_configure_mixer(dev); 1491 1492 mutex_enter(&dev->mutex); 1493 dev->suspended = B_FALSE; 1494 1495 for (int i = 0; i < AUDIGYLS_NUM_PORT; i++) { 1496 1497 port = dev->port[i]; 1498 1499 audigyls_reset_port(port); 1500 1501 if (port->started) { 1502 audigyls_start_port(port); 1503 } 1504 } 1505 1506 mutex_exit(&dev->mutex); 1507 return (DDI_SUCCESS); 1508 } 1509 1510 int 1511 audigyls_detach(audigyls_dev_t *dev) 1512 { 1513 if (audio_dev_unregister(dev->adev) != DDI_SUCCESS) 1514 return (DDI_FAILURE); 1515 1516 audigyls_destroy(dev); 1517 return (DDI_SUCCESS); 1518 } 1519 1520 int 1521 audigyls_suspend(audigyls_dev_t *dev) 1522 { 1523 if (dev->ac97) 1524 ac97_suspend(dev->ac97); 1525 1526 mutex_enter(&dev->mutex); 1527 for (int i = 0; i < AUDIGYLS_NUM_PORT; i++) { 1528 1529 audigyls_port_t *port = dev->port[i]; 1530 audigyls_stop_port(port); 1531 } 1532 dev->suspended = B_TRUE; 1533 mutex_exit(&dev->mutex); 1534 return (DDI_SUCCESS); 1535 } 1536 1537 static int audigyls_ddi_attach(dev_info_t *, ddi_attach_cmd_t); 1538 static int audigyls_ddi_detach(dev_info_t *, ddi_detach_cmd_t); 1539 static int audigyls_ddi_quiesce(dev_info_t *); 1540 1541 static struct dev_ops audigyls_dev_ops = { 1542 DEVO_REV, /* rev */ 1543 0, /* refcnt */ 1544 NULL, /* getinfo */ 1545 nulldev, /* identify */ 1546 nulldev, /* probe */ 1547 audigyls_ddi_attach, /* attach */ 1548 audigyls_ddi_detach, /* detach */ 1549 nodev, /* reset */ 1550 NULL, /* cb_ops */ 1551 NULL, /* bus_ops */ 1552 NULL, /* power */ 1553 audigyls_ddi_quiesce, /* quiesce */ 1554 }; 1555 1556 static struct modldrv audigyls_modldrv = { 1557 &mod_driverops, /* drv_modops */ 1558 "Creative Audigy LS Audio", /* linkinfo */ 1559 &audigyls_dev_ops, /* dev_ops */ 1560 }; 1561 1562 static struct modlinkage modlinkage = { 1563 MODREV_1, 1564 { &audigyls_modldrv, NULL } 1565 }; 1566 1567 int 1568 _init(void) 1569 { 1570 int rv; 1571 1572 audio_init_ops(&audigyls_dev_ops, AUDIGYLS_NAME); 1573 if ((rv = mod_install(&modlinkage)) != 0) { 1574 audio_fini_ops(&audigyls_dev_ops); 1575 } 1576 return (rv); 1577 } 1578 1579 int 1580 _fini(void) 1581 { 1582 int rv; 1583 1584 if ((rv = mod_remove(&modlinkage)) == 0) { 1585 audio_fini_ops(&audigyls_dev_ops); 1586 } 1587 return (rv); 1588 } 1589 1590 int 1591 _info(struct modinfo *modinfop) 1592 { 1593 return (mod_info(&modlinkage, modinfop)); 1594 } 1595 1596 int 1597 audigyls_ddi_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 1598 { 1599 switch (cmd) { 1600 case DDI_ATTACH: 1601 return (audigyls_attach(dip)); 1602 1603 case DDI_RESUME: 1604 return (audigyls_resume(dip)); 1605 1606 default: 1607 return (DDI_FAILURE); 1608 } 1609 } 1610 1611 int 1612 audigyls_ddi_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 1613 { 1614 audigyls_dev_t *dev; 1615 1616 dev = ddi_get_driver_private(dip); 1617 1618 switch (cmd) { 1619 case DDI_DETACH: 1620 return (audigyls_detach(dev)); 1621 1622 case DDI_SUSPEND: 1623 return (audigyls_suspend(dev)); 1624 1625 default: 1626 return (DDI_FAILURE); 1627 } 1628 } 1629 1630 int 1631 audigyls_ddi_quiesce(dev_info_t *dip) 1632 { 1633 audigyls_dev_t *dev; 1634 uint32_t status; 1635 1636 dev = ddi_get_driver_private(dip); 1637 1638 for (int i = 0; i < AUDIGYLS_NUM_PORT; i++) { 1639 1640 audigyls_port_t *port = dev->port[i]; 1641 audigyls_stop_port(port); 1642 } 1643 1644 /* 1645 * Turn off the hardware 1646 */ 1647 1648 write_reg(dev, SA, 0); 1649 OUTL(dev, IER, 0); /* Interrupt disable */ 1650 write_reg(dev, AIE, 0); /* Disable audio interrupts */ 1651 status = INL(dev, IPR); 1652 OUTL(dev, IPR, status); /* Acknowledge */ 1653 return (DDI_SUCCESS); 1654 } 1655