1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 #ifndef _SYS_AUDIOHD_IMPL_H_ 26 #define _SYS_AUDIOHD_IMPL_H_ 27 28 #ifdef __cplusplus 29 extern "C" { 30 #endif 31 32 /* 33 * vendor IDs of PCI audio controllers 34 */ 35 #define AUDIOHD_VID_ATI 0x1002 36 #define AUDIOHD_VID_CIRRUS 0x1013 37 #define AUDIOHD_VID_NVIDIA 0x10de 38 #define AUDIOHD_VID_REALTEK 0x10ec 39 #define AUDIOHD_VID_CREATIVE 0x1102 40 #define AUDIOHD_VID_IDT 0x111d 41 #define AUDIOHD_VID_ANALOG 0x11d4 42 #define AUDIOHD_VID_CONEXANT 0x14f1 43 #define AUDIOHD_VID_SIGMATEL 0x8384 44 #define AUDIOHD_VID_INTEL 0x8086 45 46 /* 47 * specific audiohd controller device id 48 */ 49 #define AUDIOHD_CONTROLLER_MCP51 0x10de026c 50 51 /* 52 * codec special initial flags 53 */ 54 #define NO_GPIO 0x00000001 55 #define NO_MIXER 0x00000002 56 #define NO_SPDIF 0x00000004 57 #define EN_PIN_BEEP 0x00000008 58 59 #define AUDIOHD_INTS 50 60 #define AUDIOHD_MAX_INTS 1500 61 #define AUDIOHD_MIN_INTS 32 62 63 #define AUDIOHD_DEV_CONFIG "onboard1" 64 #define AUDIOHD_DEV_VERSION "a" 65 66 #define AUDIOHD_FMT_PCM 0x001 67 /* 68 * Only for Intel hardware: 69 * PCI Express traffic class select register in PCI configure space 70 */ 71 #define AUDIOHD_INTEL_PCI_TCSEL 0x44 72 73 /* 74 * Only for ATI SB450: 75 * MISC control register 2 76 */ 77 #define AUDIOHD_ATI_PCI_MISC2 0x42 78 #define AUDIOHD_ATI_MISC2_SNOOP 0x02 79 #define AUDIOHDC_NID(x) x 80 #define AUDIOHDC_NULL_NODE -1 81 #define AUDIOHD_NULL_CONN ((uint_t)(-1)) 82 /* 83 * currently, only the format of 48K sample rate, 16-bit 84 * 2-channel is supported. 85 */ 86 #define AUDIOHD_FMT_PCMOUT 0x0011 87 #define AUDIOHD_FMT_PCMIN 0x0011 88 89 #define AUDIOHD_EXT_AMP_MASK 0x00010000 90 #define AUDIOHD_EXT_AMP_ENABLE 0x02 91 /* NVIDIA snoop */ 92 #define AUDIOHD_NVIDIA_SNOOP 0x0f 93 94 /* Power On/Off */ 95 #define AUDIOHD_PW_D0 0 96 #define AUDIOHD_PW_D2 2 97 98 #define AUDIOHD_INTEL_TCS_MASK 0xf8 99 #define AUDIOHD_ATI_MISC2_MASK 0xf8 100 101 /* Pin speaker On/Off */ 102 #define AUDIOHD_SP_ON 1 103 #define AUDIOHD_SP_OFF 0 104 105 #define AUDIOHD_PORT_MAX 15 106 #define AUDIOHD_CODEC_MAX 16 107 #define AUDIOHD_MEMIO_LEN 0x4000 108 109 #define AUDIOHD_RETRY_TIMES 60 110 #define AUDIOHD_TEST_TIMES 500 111 #define AUDIOHD_OUTSTR_NUM_OFF 12 112 #define AUDIOHD_INSTR_NUM_OFF 8 113 114 #define AUDIOHD_CORB_SIZE_OFF 0x4e 115 116 #define AUDIOHD_URCAP_MASK 0x80 117 #define AUDIOHD_DTCCAP_MASK 0x4 118 #define AUDIOHD_UR_ENABLE_OFF 8 119 #define AUDIOHD_UR_TAG_MASK 0x1f 120 121 #define AUDIOHD_CIS_MASK 0x40000000 122 123 #define AUDIOHD_RIRB_UR_MASK 0x10 124 #define AUDIOHD_RIRB_CODEC_MASK 0xf 125 #define AUDIOHD_RIRB_WID_OFF 27 126 #define AUDIOHD_RIRB_INTRCNT 0x0 127 #define AUDIOHD_RIRB_WPMASK 0xff 128 129 #define AUDIOHD_FORM_MASK 0x0080 130 #define AUDIOHD_LEN_MASK 0x007f 131 #define AUDIOHD_PIN_CAP_MASK 0x00000010 132 #define AUDIOHD_PIN_CONF_MASK 0xc0000000 133 #define AUDIOHD_PIN_CON_MASK 3 134 #define AUDIOHD_PIN_CON_STEP 30 135 #define AUDIOHD_PIN_IO_MASK 0X0018 136 #define AUDIOHD_PIN_SEQ_MASK 0x0000000f 137 #define AUDIOHD_PIN_ASO_MASK 0x000000f0 138 #define AUDIOHD_PIN_ASO_OFF 0x4 139 #define AUDIOHD_PIN_DEV_MASK 0x00f00000 140 #define AUDIOHD_PIN_DEV_OFF 20 141 #define AUDIOHD_PIN_NUMS 6 142 #define AUDIOHD_PIN_NO_CONN 0x40000000 143 #define AUDIOHD_PIN_IN_ENABLE 0x20 144 #define AUDIOHD_PIN_OUT_ENABLE 0x40 145 #define AUDIOHD_PIN_PRES_OFF 0x20 146 #define AUDIOHD_PIN_CONTP_OFF 0x1e 147 #define AUDIOHD_PIN_CON_JACK 0 148 #define AUDIOHD_PIN_CON_FIXED 0x2 149 #define AUDIOHD_PIN_CONTP_MASK 0x3 150 #define AUDIOHD_PIN_VREF_L1 0x20 151 #define AUDIOHD_PIN_VREF_L2 0x10 152 #define AUDIOHD_PIN_VREF_L3 0x04 153 #define AUDIOHD_PIN_VREF_L4 0x02 154 #define AUDIOHD_PIN_VREF_OFF 8 155 #define AUDIOHD_PIN_VREF_MASK 0xff 156 #define AUDIOHD_PIN_CLR_MASK 0xf 157 #define AUDIOHD_PIN_CLR_OFF 12 158 159 160 #define AUDIOHD_VERB_ADDR_OFF 28 161 #define AUDIOHD_VERB_NID_OFF 20 162 #define AUDIOHD_VERB_CMD_OFF 8 163 #define AUDIOHD_VERB_CMD16_OFF 16 164 165 #define AUDIOHD_RING_MAX_SIZE 0x00ff 166 #define AUDIOHD_REC_TAG_OFF 4 167 #define AUDIOHD_PLAY_TAG_OFF 4 168 #define AUDIOHD_PLAY_CTL_OFF 2 169 #define AUDIOHD_REC_CTL_OFF 2 170 171 #define AUDIOHD_SPDIF_ON 1 172 #define AUDIOHD_SPDIF_MASK 0x00ff 173 174 #define AUDIOHD_GAIN_OFF 8 175 176 #define AUDIOHD_CODEC_STR_OFF 16 177 #define AUDIOHD_CODEC_STR_MASK 0x000000ff 178 #define AUDIOHD_CODEC_NUM_MASK 0x000000ff 179 #define AUDIOHD_CODEC_TYPE_MASK 0x000000ff 180 181 #define AUDIOHD_ROUNDUP(x, algn) (((x) + ((algn) - 1)) & ~((algn) - 1)) 182 #define AUDIOHD_FRAGFR_ALIGN 64 183 #define AUDIOHD_BDLE_BUF_ALIGN 128 184 #define AUDIOHD_CMDIO_ENT_MASK 0x00ff /* 256 entries for CORB/RIRB */ 185 #define AUDIOHD_CDBIO_CORB_LEN 1024 /* 256 entries for CORB, 1024B */ 186 #define AUDIOHD_CDBIO_RIRB_LEN 2048 /* 256 entries for RIRB, 2048B */ 187 #define AUDIOHD_BDLE_NUMS 4 /* 4 entires for record/play BD list */ 188 189 #define AUDIOHD_PORT_UNMUTE (0xffffffff) 190 191 /* 192 * Audio registers of high definition 193 */ 194 #define AUDIOHD_REG_GCAP 0x00 195 #define AUDIOHDR_GCAP_OUTSTREAMS 0xf000 196 #define AUDIOHDR_GCAP_INSTREAMS 0x0f00 197 #define AUDIOHDR_GCAP_BSTREAMS 0x00f8 198 #define AUDIOHDR_GCAP_NSDO 0x0006 199 #define AUDIOHDR_GCAP_64OK 0x0001 200 201 #define AUDIOHD_REG_VMIN 0x02 202 #define AUDIOHD_REG_VMAJ 0x03 203 #define AUDIOHD_REG_OUTPAY 0x04 204 #define AUDIOHD_REG_INPAY 0x06 205 #define AUDIOHD_REG_GCTL 0x08 206 #define AUDIOHD_REG_WAKEEN 0x0C 207 #define AUDIOHD_REG_STATESTS 0x0E 208 #define AUDIOHD_STATESTS_BIT_SDINS 0x7F 209 210 #define AUDIOHD_REG_GSTS 0x10 211 #define AUDIOHD_REG_INTCTL 0x20 212 #define AUDIOHD_INTCTL_BIT_GIE 0x80000000 213 #define AUDIOHD_INTCTL_BIT_CIE 0x40000000 214 #define AUDIOHD_INTCTL_BIT_SIE 0x3FFFFFFF 215 216 217 #define AUDIOHD_REG_INTSTS 0x24 218 #define AUDIOHD_INTSTS_BIT_GIS 0x80000000 219 #define AUDIOHD_INTSTS_BIT_CIS 0x40000000 220 #define AUDIOHD_INTSTS_BIT_SINTS (0x3fffffff) 221 222 #define AUDIOHD_REG_WALCLK 0x30 223 #define AUDIOHD_REG_SYNC 0x38 224 225 #define AUDIOHD_REG_CORBLBASE 0x40 226 #define AUDIOHD_REG_CORBUBASE 0x44 227 #define AUDIOHD_REG_CORBWP 0x48 228 #define AUDIOHD_REG_CORBRP 0x4A 229 #define AUDIOHD_REG_CORBCTL 0x4C 230 #define AUDIOHD_REG_CORBST 0x4D 231 #define AUDIOHD_REG_CORBSIZE 0x4E 232 233 #define AUDIOHD_REG_RIRBLBASE 0x50 234 #define AUDIOHD_REG_RIRBUBASE 0x54 235 #define AUDIOHD_REG_RIRBWP 0x58 236 #define AUDIOHD_REG_RINTCNT 0x5A 237 #define AUDIOHD_REG_RIRBCTL 0x5C 238 #define AUDIOHD_REG_RIRBSTS 0x5D 239 #define AUDIOHD_REG_RIRBSIZE 0x5E 240 241 #define AUDIOHD_REG_IC 0x60 242 #define AUDIOHD_REG_IR 0x64 243 #define AUDIOHD_REG_IRS 0x68 244 #define AUDIOHD_REG_DPLBASE 0x70 245 #define AUDIOHD_REG_DPUBASE 0x74 246 247 #define AUDIOHD_REG_SD_BASE 0x80 248 #define AUDIOHD_REG_SD_LEN 0x20 249 250 /* 251 * Offset of Stream Descriptor Registers 252 */ 253 #define AUDIOHD_SDREG_OFFSET_CTL 0x00 254 #define AUDIOHD_SDREG_OFFSET_STS 0x03 255 #define AUDIOHD_SDREG_OFFSET_LPIB 0x04 256 #define AUDIOHD_SDREG_OFFSET_CBL 0x08 257 #define AUDIOHD_SDREG_OFFSET_LVI 0x0c 258 #define AUDIOHD_SDREG_OFFSET_FIFOW 0x0e 259 #define AUDIOHD_SDREG_OFFSET_FIFOSIZE 0x10 260 #define AUDIOHD_SDREG_OFFSET_FORMAT 0x12 261 #define AUDIOHD_SDREG_OFFSET_BDLPL 0x18 262 #define AUDIOHD_SDREG_OFFSET_BDLPU 0x1c 263 264 /* bits for stream descriptor control reg */ 265 #define AUDIOHDR_SD_CTL_DEIE 0x000010 266 #define AUDIOHDR_SD_CTL_FEIE 0x000008 267 #define AUDIOHDR_SD_CTL_IOCE 0x000004 268 #define AUDIOHDR_SD_CTL_SRUN 0x000002 269 #define AUDIOHDR_SD_CTL_SRST 0x000001 270 #define AUDIOHDR_SD_CTL_INTS \ 271 (AUDIOHDR_SD_CTL_DEIE | \ 272 AUDIOHDR_SD_CTL_FEIE | \ 273 AUDIOHDR_SD_CTL_IOCE) 274 275 276 /* bits for stream descriptor status register */ 277 #define AUDIOHDR_SD_STS_BCIS 0x0004 278 #define AUDIOHDR_SD_STS_FIFOE 0x0008 279 #define AUDIOHDR_SD_STS_DESE 0x0010 280 #define AUDIOHDR_SD_STS_FIFORY 0x0020 281 #define AUDIOHDR_SD_STS_INTRS \ 282 (AUDIOHDR_SD_STS_BCIS | \ 283 AUDIOHDR_SD_STS_FIFOE | \ 284 AUDIOHDR_SD_STS_DESE) 285 286 287 /* bits for GCTL register */ 288 #define AUDIOHDR_GCTL_CRST 0x00000001 289 #define AUDIOHDR_GCTL_URESPE 0x00000100 290 291 /* bits for CORBRP register */ 292 #define AUDIOHDR_CORBRP_RESET 0x8000 293 #define AUDIOHDR_CORBRP_WPTR 0x00ff 294 295 /* bits for CORBCTL register */ 296 #define AUDIOHDR_CORBCTL_CMEIE 0x01 297 #define AUDIOHDR_CORBCTL_DMARUN 0x02 298 299 /* bits for CORB SIZE register */ 300 #define AUDIOHDR_CORBSZ_8 0 301 #define AUDIOHDR_CORBSZ_16 1 302 #define AUDIOHDR_CORBSZ_256 2 303 304 /* bits for RIRBCTL register */ 305 #define AUDIOHDR_RIRBCTL_RINTCTL 0x01 306 #define AUDIOHDR_RIRBCTL_DMARUN 0x02 307 #define AUDIOHDR_RIRBCTL_RIRBOIC 0x04 308 #define AUDIOHDR_RIRBCTL_RSTINT 0xfe 309 310 /* bits for RIRBWP register */ 311 #define AUDIOHDR_RIRBWP_RESET 0x8000 312 #define AUDIOHDR_RIRBWP_WPTR 0x00ff 313 314 /* bits for RIRB SIZE register */ 315 #define AUDIOHDR_RIRBSZ_8 0 316 #define AUDIOHDR_RIRBSZ_16 1 317 #define AUDIOHDR_RIRBSZ_256 2 318 319 #define AUDIOHD_BDLE_RIRB_SDI 0x0000000f 320 #define AUDIOHD_BDLE_RIRB_UNSOLICIT 0x00000010 321 322 /* HD spec: ID of Root node is 0 */ 323 #define AUDIOHDC_NODE_ROOT 0x00 324 325 /* HD spec: ID of audio function group is "1" */ 326 #define AUDIOHDC_AUDIO_FUNC_GROUP 1 327 328 /* 329 * HD audio verbs can be either 12-bit or 4-bit in length. 330 */ 331 #define AUDIOHDC_12BIT_VERB_MASK 0xfffff000 332 #define AUDIOHDC_4BIT_VERB_MASK 0xfffffff0 333 334 #define AUDIOHDC_SAMPR48000 48000 335 #define AUDIOHDC_MAX_BEEP_GEN 12000 336 #define AUDIOHDC_MIX_BEEP_GEN 47 337 #define AUDIOHDC_MUTE_BEEP_GEN 0x0 338 339 /* 340 * 12-bit verbs 341 */ 342 #define AUDIOHDC_VERB_GET_PARAM 0xf00 343 344 #define AUDIOHDC_VERB_GET_CONN_SEL 0xf01 345 #define AUDIOHDC_VERB_SET_CONN_SEL 0x701 346 347 #define AUDIOHDC_VERB_GET_CONN_LIST_ENT 0xf02 348 #define AUDIOHDC_VERB_GET_PROCESS_STATE 0xf03 349 #define AUDIOHDC_VERB_GET_SDI_SEL 0xf04 350 351 #define AUDIOHDC_VERB_GET_POWER_STATE 0xf05 352 #define AUDIOHDC_VERB_SET_POWER_STATE 0x705 353 354 #define AUDIOHDC_VERB_GET_STREAM_CHANN 0xf06 355 #define AUDIOHDC_VERB_SET_STREAM_CHANN 0x706 356 357 #define AUDIOHDC_VERB_GET_PIN_CTRL 0xf07 358 #define AUDIOHDC_VERB_SET_PIN_CTRL 0x707 359 360 #define AUDIOHDC_VERB_GET_UNS_ENABLE 0xf08 361 362 #define AUDIOHDC_VERB_GET_PIN_SENSE 0xf09 363 #define AUDIOHDC_VERB_EXEC_PIN_SENSE 0x709 364 365 #define AUDIOHDC_VERB_GET_BEEP_GEN 0xf0a 366 #define AUDIOHDC_VERB_SET_BEEP_GEN 0x70a 367 368 #define AUDIOHDC_VERB_GET_EAPD 0xf0c 369 #define AUDIOHDC_VERB_SET_EAPD 0x70c 370 371 #define AUDIOHDC_VERB_GET_DEFAULT_CONF 0xf1c 372 #define AUDIOHDC_VERB_GET_SPDIF_CTL 0xf0d 373 #define AUDIOHDC_VERB_SET_SPDIF_LCL 0x70d 374 375 #define AUDIOHDC_VERB_SET_URCTRL 0x708 376 #define AUDIOHDC_VERB_GET_PIN_SENSE 0xf09 377 378 #define AUDIOHDC_VERB_GET_GPIO_MASK 0xf16 379 #define AUDIOHDC_VERB_SET_GPIO_MASK 0x716 380 381 #define AUDIOHDC_VERB_GET_GPIO_DIREC 0xf17 382 #define AUDIOHDC_VERB_SET_GPIO_DIREC 0x717 383 384 #define AUDIOHDC_VERB_GET_GPIO_DATA 0xf15 385 #define AUDIOHDC_VERB_SET_GPIO_DATA 0x715 386 387 #define AUDIOHDC_VERB_GET_GPIO_STCK 0xf1a 388 #define AUDIOHDC_VERB_SET_GPIO_STCK 0x71a 389 390 #define AUDIOHDC_GPIO_ENABLE 0xff 391 #define AUDIOHDC_GPIO_DIRECT 0xf1 392 393 #define AUDIOHDC_GPIO_DATA_CTRL 0xff 394 #define AUDIOHDC_GPIO_STCK_CTRL 0xff 395 /* 396 * 4-bit verbs 397 */ 398 #define AUDIOHDC_VERB_GET_CONV_FMT 0xa 399 #define AUDIOHDC_VERB_SET_CONV_FMT 0x2 400 401 #define AUDIOHDC_VERB_GET_AMP_MUTE 0xb 402 #define AUDIOHDC_VERB_SET_AMP_MUTE 0x3 403 #define AUDIOHDC_VERB_SET_BEEP_VOL 0x3A0 404 405 /* 406 * parameters of nodes 407 */ 408 #define AUDIOHDC_PAR_VENDOR_ID 0x00 409 #define AUDIOHDC_PAR_SUBSYS_ID 0x01 410 #define AUDIOHDC_PAR_REV_ID 0x02 411 #define AUDIOHDC_PAR_NODE_COUNT 0x04 412 #define AUDIOHDC_PAR_FUNCTION_TYPE 0x05 413 #define AUDIOHDC_PAR_AUDIO_FG_CAP 0x08 414 #define AUDIOHDC_PAR_AUDIO_WID_CAP 0x09 415 #define AUDIOHDC_PAR_PCM 0x0a 416 #define AUDIOHDC_PAR_STREAM 0x0b 417 #define AUDIOHDC_PAR_PIN_CAP 0x0c 418 #define AUDIOHDC_PAR_INAMP_CAP 0x0d 419 #define AUDIOHDC_PAR_CONNLIST_LEN 0x0e 420 #define AUDIOHDC_PAR_POWER_STATE 0x0f 421 #define AUDIOHDC_PAR_PROC_CAP 0x10 422 #define AUDIOHDC_PAR_GPIO_CAP 0x11 423 #define AUDIOHDC_PAR_OUTAMP_CAP 0x12 424 425 /* 426 * bits for get/set amplifier gain/mute 427 */ 428 #define AUDIOHDC_AMP_SET_OUTPUT 0x8000 429 #define AUDIOHDC_AMP_SET_INPUT 0x4000 430 #define AUDIOHDC_AMP_SET_LEFT 0x2000 431 #define AUDIOHDC_AMP_SET_RIGHT 0x1000 432 #define AUDIOHDC_AMP_SET_MUTE 0x0080 433 #define AUDIOHDC_AMP_SET_LNR 0x3000 434 #define AUDIOHDC_AMP_SET_LR_INPUT 0x7000 435 #define AUDIOHDC_AMP_SET_LR_OUTPUT 0xb000 436 #define AUDIOHDC_AMP_SET_INDEX_OFFSET 8 437 #define AUDIOHDC_AMP_SET_GAIN_MASK 0x007f 438 #define AUDIOHDC_GAIN_MAX 0x7f 439 #define AUDIOHDC_GAIN_BITS 7 440 #define AUDIOHDC_GAIN_DEFAULT 0x0f 441 442 #define AUDIOHDC_AMP_GET_OUTPUT 0x8000 443 #define AUDIOHDC_AMP_GET_INPUT 0x0000 444 445 /* value used to set max volume for left output */ 446 #define AUDIOHDC_AMP_LOUT_MAX \ 447 (AUDIOHDC_AMP_SET_OUTPUT | \ 448 AUDIOHDC_AMP_SET_LEFT | \ 449 AUDIOHDC_GAIN_MAX) 450 451 /* value used to set max volume for right output */ 452 #define AUDIOHDC_AMP_ROUT_MAX \ 453 (AUDIOHDC_AMP_SET_OUTPUT | \ 454 AUDIOHDC_AMP_SET_RIGHT | \ 455 AUDIOHDC_GAIN_MAX) 456 457 458 /* 459 * Bits for pin widget control verb 460 */ 461 #define AUDIOHDC_PIN_CONTROL_HP_ENABLE 0x80 462 #define AUDIOHDC_PIN_CONTROL_OUT_ENABLE 0x40 463 #define AUDIOHDC_PIN_CONTROL_IN_ENABLE 0x20 464 465 /* 466 * Bits for Amplifier capabilities 467 */ 468 #define AUDIOHDC_AMP_CAP_MUTE_CAP 0x80000000 469 #define AUDIOHDC_AMP_CAP_STEP_SIZE 0x007f0000 470 #define AUDIOHDC_AMP_CAP_STEP_NUMS 0x00007f00 471 #define AUDIOHDC_AMP_CAP_0DB_OFFSET 0x0000007f 472 473 474 /* 475 * Bits for Audio Widget Capabilities 476 */ 477 #define AUDIOHD_WIDCAP_STEREO 0x00000001 478 #define AUDIOHD_WIDCAP_INAMP 0x00000002 479 #define AUDIOHD_WIDCAP_OUTAMP 0x00000004 480 #define AUDIOHD_WIDCAP_AMP_OVRIDE 0x00000008 481 #define AUDIOHD_WIDCAP_FMT_OVRIDE 0x00000010 482 #define AUDIOHD_WIDCAP_STRIP 0x00000020 483 #define AUDIOHD_WIDCAP_PROC_WID 0x00000040 484 #define AUDIOHD_WIDCAP_UNSOL 0x00000080 485 #define AUDIOHD_WIDCAP_CONNLIST 0x00000100 486 #define AUDIOHD_WIDCAP_DIGIT 0x00000200 487 #define AUDIOHD_WIDCAP_PWRCTRL 0x00000400 488 #define AUDIOHD_WIDCAP_LRSWAP 0x00000800 489 #define AUDIOHD_WIDCAP_TYPE 0x00f00000 490 #define AUDIOHD_WIDCAP_TO_WIDTYPE(wcap) \ 491 ((wcap & AUDIOHD_WIDCAP_TYPE) >> 20) 492 493 494 #define AUDIOHD_CODEC_FAILURE (uint32_t)(-1) 495 496 /* 497 * buffer descriptor list entry of stream descriptor 498 */ 499 typedef struct { 500 uint64_t sbde_addr; 501 uint32_t sbde_len; 502 uint32_t 503 sbde_ioc: 1, 504 reserved: 31; 505 }sd_bdle_t; 506 507 508 #define AUDIOHD_PLAY_STARTED 0x00000001 509 #define AUDIOHD_PLAY_EMPTY 0x00000002 510 #define AUDIOHD_PLAY_PAUSED 0x00000004 511 #define AUDIOHD_RECORD_STARTED 0x00000008 512 513 enum audiohda_widget_type { 514 WTYPE_AUDIO_OUT = 0, 515 WTYPE_AUDIO_IN, 516 WTYPE_AUDIO_MIX, 517 WTYPE_AUDIO_SEL, 518 WTYPE_PIN, 519 WTYPE_POWER, 520 WTYPE_VOL_KNOB, 521 WTYPE_BEEP, 522 WTYPE_VENDOR = 0xf 523 }; 524 525 enum audiohda_device_type { 526 DTYPE_LINEOUT = 0, 527 DTYPE_SPEAKER, 528 DTYPE_HP_OUT, 529 DTYPE_CD, 530 DTYPE_SPDIF_OUT, 531 DTYPE_DIGIT_OUT, 532 DTYPE_MODEM_SIDE, 533 DTYPE_MODEM_HNAD_SIDE, 534 DTYPE_LINE_IN, 535 DTYPE_AUX, 536 DTYPE_MIC_IN, 537 DTYPE_TEL, 538 DTYPE_SPDIF_IN, 539 DTYPE_DIGIT_IN, 540 DTYPE_OTHER = 0x0f, 541 }; 542 543 enum audiohd_pin_color { 544 AUDIOHD_PIN_UNKNOWN = 0, 545 AUDIOHD_PIN_BLACK, 546 AUDIOHD_PIN_GREY, 547 AUDIOHD_PIN_BLUE, 548 AUDIOHD_PIN_GREEN, 549 AUDIOHD_PIN_RED, 550 AUDIOHD_PIN_ORANGE, 551 AUDIOHD_PIN_YELLOW, 552 AUDIOHD_PIN_PURPLE, 553 AUDIOHD_PIN_PINK, 554 AUDIOHD_PIN_WHITE = 0xe, 555 AUDIOHD_PIN_OTHER = 0xf, 556 }; 557 558 #define CTRL_NUM 16 559 560 /* values for audiohd_widget.path_flags */ 561 #define AUDIOHD_PATH_DAC (1 << 0) 562 #define AUDIOHD_PATH_ADC (1 << 1) 563 #define AUDIOHD_PATH_MON (1 << 2) 564 #define AUDIOHD_PATH_NOMON (1 << 3) 565 #define AUDIOHD_PATH_BEEP (1 << 4) 566 567 typedef struct audiohd_path audiohd_path_t; 568 typedef struct audiohd_widget audiohd_widget_t; 569 typedef struct audiohd_state audiohd_state_t; 570 typedef struct audiohd_codec_info audiohd_codec_info_t; 571 typedef struct audiohd_pin audiohd_pin_t; 572 typedef struct hda_codec hda_codec_t; 573 typedef uint32_t wid_t; /* id of widget */ 574 typedef struct audiohd_entry_prop audiohd_entry_prop_t; 575 typedef enum audiohda_device_type audiohda_device_type_t; 576 typedef enum audiohd_pin_color audiohd_pin_color_t; 577 578 #define AUDIOHD_MAX_WIDGET 128 579 #define AUDIOHD_MAX_CONN 16 580 #define AUDIOHD_MAX_PINS 16 581 #define AUDIOHD_MAX_DEPTH 8 582 583 struct audiohd_entry_prop { 584 uint32_t conn_len; 585 uint32_t mask_range; 586 uint32_t mask_wid; 587 wid_t input_wid; 588 int conns_per_entry; 589 int bits_per_conn; 590 }; 591 struct audiohd_widget { 592 wid_t wid_wid; 593 hda_codec_t *codec; 594 enum audiohda_widget_type type; 595 596 uint32_t widget_cap; 597 uint32_t pcm_format; 598 uint32_t inamp_cap; 599 uint32_t outamp_cap; 600 601 uint32_t path_flags; 602 603 int out_weight; 604 int in_weight; 605 int finish; 606 607 /* 608 * wid of possible & selected input connections 609 */ 610 wid_t avail_conn[AUDIOHD_MAX_CONN]; 611 wid_t selconn; 612 /* 613 * for monitor path 614 */ 615 wid_t selmon[AUDIOHD_MAX_CONN]; 616 uint16_t used; 617 618 /* 619 * available (input) connections. 0 means this widget 620 * has fixed connection 621 */ 622 int nconns; 623 624 /* 625 * pointer to struct depending on widget type: 626 * 1. DAC audiohd_ostream_t 627 * 2. ADC audiohd_istream_t 628 * 3. PIN audiohd_pin_t 629 */ 630 void *priv; 631 }; 632 633 #define AUDIOHD_FLAG_LINEOUT (1 << 0) 634 #define AUDIOHD_FLAG_SPEAKER (1 << 1) 635 #define AUDIOHD_FLAG_HP (1 << 2) 636 #define AUDIOHD_FLAG_MONO (1 << 3) 637 638 #define AUDIOHD_MAX_MIXER 5 639 #define AUDIOHD_MAX_PIN 4 640 641 #define PORT_DAC 0 642 #define PORT_ADC 1 643 #define PORT_MAX 2 644 typedef enum { 645 PLAY = 0, 646 RECORD = 1, 647 BEEP = 2, 648 } path_type_t; 649 650 struct audiohd_path { 651 wid_t adda_wid; 652 wid_t beep_wid; 653 654 wid_t pin_wid[AUDIOHD_MAX_PINS]; 655 int sum_selconn[AUDIOHD_MAX_PINS]; 656 int mon_wid[AUDIOHD_MAX_PIN][AUDIOHD_MAX_MIXER]; 657 int pin_nums; 658 int maxmixer[AUDIOHD_MAX_PINS]; 659 660 path_type_t path_type; 661 662 wid_t mute_wid; 663 int mute_dir; 664 wid_t gain_wid; 665 int gain_dir; 666 uint32_t gain_bits; 667 668 uint32_t pin_outputs; 669 uint8_t tag; 670 671 hda_codec_t *codec; 672 673 wid_t sum_wid; 674 675 audiohd_state_t *statep; 676 }; 677 678 typedef struct audiohd_port 679 { 680 uint8_t nchan; 681 int index; 682 uint16_t regoff; 683 boolean_t started; 684 boolean_t triggered; 685 686 unsigned fragfr; 687 unsigned nframes; 688 uint64_t count; 689 int curpos; 690 int intrs; 691 692 uint_t format; 693 unsigned sync_dir; 694 695 ddi_dma_handle_t samp_dmah; 696 ddi_acc_handle_t samp_acch; 697 size_t samp_size; 698 caddr_t samp_kaddr; 699 uint64_t samp_paddr; 700 701 ddi_dma_handle_t bdl_dmah; 702 ddi_acc_handle_t bdl_acch; 703 size_t bdl_size; 704 caddr_t bdl_kaddr; 705 uint64_t bdl_paddr; 706 707 audio_engine_t *engine; 708 audiohd_state_t *statep; 709 }audiohd_port_t; 710 711 typedef struct audiohd_ctrl 712 { 713 audiohd_state_t *statep; 714 audio_ctrl_t *ctrl; 715 uint32_t num; 716 uint64_t val; 717 } audiohd_ctrl_t; 718 719 struct audiohd_pin { 720 audiohd_pin_t *next; 721 wid_t wid; 722 wid_t mute_wid; /* node used to mute this pin */ 723 int mute_dir; /* 1: input, 2: output */ 724 wid_t gain_wid; /* node for gain control */ 725 int gain_dir; /* _OUTPUT/_INPUT */ 726 uint32_t gain_bits; 727 728 uint8_t vrefvalue; /* value of VRef */ 729 730 uint32_t cap; 731 uint32_t config; 732 uint32_t ctrl; 733 uint32_t assoc; 734 uint32_t seq; 735 wid_t adc_dac_wid; /* AD/DA wid which can route to this pin */ 736 wid_t beep_wid; 737 int no_phys_conn; 738 enum audiohda_device_type device; 739 740 /* 741 * mg_dir, mg_gain, mg_wid are used to store the monitor gain control 742 * widget wid. 743 */ 744 int mg_dir[AUDIOHD_MAX_CONN]; 745 int mg_gain[AUDIOHD_MAX_CONN]; 746 int mg_wid[AUDIOHD_MAX_CONN]; 747 int num; 748 int finish; 749 750 }; 751 752 typedef struct { 753 ddi_dma_handle_t ad_dmahdl; 754 ddi_acc_handle_t ad_acchdl; 755 caddr_t ad_vaddr; /* virtual addr */ 756 uint64_t ad_paddr; /* physical addr */ 757 size_t ad_req_sz; /* required size of memory */ 758 size_t ad_real_sz; /* real size of memory */ 759 } audiohd_dma_t; 760 761 struct hda_codec { 762 uint8_t index; /* codec address */ 763 uint32_t vid; /* vendor id and device id */ 764 uint32_t revid; /* revision id */ 765 wid_t wid_afg; /* id of AFG */ 766 wid_t first_wid; /* wid of 1st subnode of AFG */ 767 wid_t last_wid; /* wid of the last subnode of AFG */ 768 int nnodes; /* # of subnodes of AFG */ 769 uint8_t nistream; 770 771 uint32_t outamp_cap; 772 uint32_t inamp_cap; 773 uint32_t stream_format; 774 uint32_t pcm_format; 775 776 audiohd_state_t *soft_statep; 777 audiohd_codec_info_t *codec_info; 778 779 /* use wid as index to the array of widget pointers */ 780 audiohd_widget_t *widget[AUDIOHD_MAX_WIDGET]; 781 782 audiohd_port_t *port[AUDIOHD_PORT_MAX]; 783 uint8_t portnum; 784 audiohd_pin_t *first_pin; 785 }; 786 787 #define AUDIOHD_MAX_ASSOC 15 788 struct audiohd_state { 789 dev_info_t *hda_dip; 790 kstat_t *hda_ksp; 791 kmutex_t hda_mutex; 792 uint32_t hda_flags; 793 794 boolean_t soft_volume; 795 796 caddr_t hda_reg_base; 797 ddi_acc_handle_t hda_pci_handle; 798 ddi_acc_handle_t hda_reg_handle; 799 800 ddi_intr_handle_t *htable; /* For array of interrupts */ 801 boolean_t intr_added; 802 int intr_type; /* What type of interrupt */ 803 int intr_rqst; /* # of request intrs count */ 804 int intr_cnt; /* # of intrs count returned */ 805 uint_t intr_pri; /* Interrupt priority */ 806 int intr_cap; /* Interrupt capabilities */ 807 boolean_t msi_enable; 808 809 audiohd_dma_t hda_dma_corb; 810 audiohd_dma_t hda_dma_rirb; 811 812 813 uint8_t hda_rirb_rp; /* read pointer for rirb */ 814 uint16_t hda_codec_mask; 815 816 817 audio_dev_t *adev; 818 uint32_t devid; 819 820 821 int hda_pint_freq; /* play intr frequence */ 822 int hda_rint_freq; /* record intr frequence */ 823 824 int hda_input_streams; /* # of input stream */ 825 int hda_output_streams; /* # of output stream */ 826 int hda_streams_nums; /* # of stream */ 827 828 uint_t hda_play_regbase; 829 uint_t hda_record_regbase; 830 831 uint_t hda_play_stag; /* tag of playback stream */ 832 uint_t hda_record_stag; /* tag of record stream */ 833 uint_t hda_play_lgain; /* left gain for playback */ 834 uint_t hda_play_rgain; /* right gain for playback */ 835 836 /* 837 * Now, for the time being, we add some fields 838 * for parsing codec topology 839 */ 840 hda_codec_t *codec[AUDIOHD_CODEC_MAX]; 841 /* 842 * Suspend/Resume used fields 843 */ 844 boolean_t suspended; 845 boolean_t monitor_unsupported; 846 847 audiohd_path_t *path[AUDIOHD_PORT_MAX]; 848 uint8_t pathnum; 849 audiohd_port_t *port[PORT_MAX]; 850 uint8_t pchan; 851 uint8_t rchan; 852 853 uint64_t inmask; 854 855 uint_t hda_out_ports; 856 uint_t in_port; 857 858 /* 859 * Controls 860 */ 861 audiohd_ctrl_t *controls[CTRL_NUM]; 862 863 /* for multichannel */ 864 uint8_t chann[AUDIOHD_MAX_ASSOC]; 865 uint8_t assoc; 866 867 }; 868 869 struct audiohd_codec_info { 870 uint32_t devid; 871 const char *buf; 872 uint32_t flags; 873 }; 874 875 /* 876 * Operation for high definition audio control system bus 877 * interface registers 878 */ 879 #define AUDIOHD_REG_GET8(reg) \ 880 ddi_get8(statep->hda_reg_handle, \ 881 (void *)((char *)statep->hda_reg_base + (reg))) 882 883 #define AUDIOHD_REG_GET16(reg) \ 884 ddi_get16(statep->hda_reg_handle, \ 885 (void *)((char *)statep->hda_reg_base + (reg))) 886 887 #define AUDIOHD_REG_GET32(reg) \ 888 ddi_get32(statep->hda_reg_handle, \ 889 (void *)((char *)statep->hda_reg_base + (reg))) 890 891 #define AUDIOHD_REG_GET64(reg) \ 892 ddi_get64(statep->hda_reg_handle, \ 893 (void *)((char *)statep->hda_reg_base + (reg))) 894 895 #define AUDIOHD_REG_SET8(reg, val) \ 896 ddi_put8(statep->hda_reg_handle, \ 897 (void *)((char *)statep->hda_reg_base + (reg)), (val)) 898 899 #define AUDIOHD_REG_SET16(reg, val) \ 900 ddi_put16(statep->hda_reg_handle, \ 901 (void *)((char *)statep->hda_reg_base + (reg)), (val)) 902 903 #define AUDIOHD_REG_SET32(reg, val) \ 904 ddi_put32(statep->hda_reg_handle, \ 905 (void *)((char *)statep->hda_reg_base + (reg)), (val)) 906 907 #define AUDIOHD_REG_SET64(reg, val) \ 908 ddi_put64(statep->hda_reg_handle, \ 909 (void *)((char *)statep->hda_reg_base + (reg)), (val)) 910 911 912 /* 913 * enable a pin widget to output 914 */ 915 #define AUDIOHD_ENABLE_PIN_OUT(statep, caddr, wid) \ 916 { \ 917 uint32_t lTmp; \ 918 \ 919 lTmp = audioha_codec_verb_get(statep, caddr, wid, \ 920 AUDIOHDC_VERB_GET_PIN_CTRL, 0); \ 921 if (lTmp == AUDIOHD_CODEC_FAILURE) \ 922 return (DDI_FAILURE); \ 923 lTmp = audioha_codec_verb_get(statep, caddr, wid, \ 924 AUDIOHDC_VERB_SET_PIN_CTRL, \ 925 (lTmp | AUDIOHDC_PIN_CONTROL_OUT_ENABLE | \ 926 AUDIOHDC_PIN_CONTROL_HP_ENABLE)); \ 927 if (lTmp == AUDIOHD_CODEC_FAILURE) \ 928 return (DDI_FAILURE); \ 929 } 930 931 /* 932 * disable output pin 933 */ 934 #define AUDIOHD_DISABLE_PIN_OUT(statep, caddr, wid) \ 935 { \ 936 uint32_t lTmp; \ 937 \ 938 lTmp = audioha_codec_verb_get(statep, caddr, wid, \ 939 AUDIOHDC_VERB_GET_PIN_CTRL, 0); \ 940 if (lTmp == AUDIOHD_CODEC_FAILURE) \ 941 return (DDI_FAILURE); \ 942 lTmp = audioha_codec_verb_get(statep, caddr, wid, \ 943 AUDIOHDC_VERB_SET_PIN_CTRL, \ 944 (lTmp & ~AUDIOHDC_PIN_CONTROL_OUT_ENABLE)); \ 945 if (lTmp == AUDIOHD_CODEC_FAILURE) \ 946 return (DDI_FAILURE); \ 947 } 948 949 /* 950 * enable a pin widget to input 951 */ 952 #define AUDIOHD_ENABLE_PIN_IN(statep, caddr, wid) \ 953 { \ 954 (void) audioha_codec_verb_get(statep, caddr, wid, \ 955 AUDIOHDC_VERB_SET_PIN_CTRL, AUDIOHDC_PIN_CONTROL_IN_ENABLE | 4); \ 956 } 957 958 959 /* 960 * disable input pin 961 */ 962 #define AUDIOHD_DISABLE_PIN_IN(statep, caddr, wid) \ 963 { \ 964 uint32_t lTmp; \ 965 \ 966 lTmp = audioha_codec_verb_get(statep, caddr, wid, \ 967 AUDIOHDC_VERB_GET_PIN_CTRL, 0); \ 968 if (lTmp == AUDIOHD_CODEC_FAILURE) \ 969 return (DDI_FAILURE); \ 970 lTmp = audioha_codec_verb_get(statep, caddr, wid, \ 971 AUDIOHDC_VERB_SET_PIN_CTRL, \ 972 (lTmp & ~AUDIOHDC_PIN_CONTROL_IN_ENABLE)); \ 973 if (lTmp == AUDIOHD_CODEC_FAILURE) \ 974 return (DDI_FAILURE); \ 975 } 976 977 /* 978 * unmute an output pin 979 */ 980 #define AUDIOHD_NODE_UNMUTE_OUT(statep, caddr, wid) \ 981 { \ 982 if (audioha_codec_4bit_verb_get(statep, \ 983 caddr, wid, AUDIOHDC_VERB_SET_AMP_MUTE, \ 984 AUDIOHDC_AMP_SET_LR_OUTPUT | AUDIOHDC_GAIN_MAX) == \ 985 AUDIOHD_CODEC_FAILURE) \ 986 return (DDI_FAILURE); \ 987 } 988 989 /* 990 * check volume adjust value of 2 channels control 991 */ 992 #define AUDIOHD_CHECK_2CHANNELS_VOLUME(value) \ 993 { \ 994 if ((value) & ~0xffff) \ 995 return (EINVAL); \ 996 if ((((value) & 0xff00) >> 8) > 100 || \ 997 ((value) & 0xff) > 100) \ 998 return (EINVAL); \ 999 } 1000 1001 /* 1002 * check volume adjust value of mono channel control 1003 */ 1004 #define AUDIOHD_CHECK_CHANNEL_VOLUME(value) \ 1005 { \ 1006 if ((value) & ~0xff) \ 1007 return (EINVAL); \ 1008 if (((value) & 0xff) > 100) \ 1009 return (EINVAL); \ 1010 } 1011 1012 #ifdef __cplusplus 1013 } 1014 #endif 1015 1016 #endif /* _SYS_AUDIOHD_IMPL_H_ */ 1017