1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 #ifndef _SYS_AUDIOHD_IMPL_H_ 26 #define _SYS_AUDIOHD_IMPL_H_ 27 28 #ifdef __cplusplus 29 extern "C" { 30 #endif 31 32 /* 33 * vendor IDs of PCI audio controllers 34 */ 35 #define AUDIOHD_VID_INTEL 0x8086 36 #define AUDIOHD_VID_ATI 0x1002 37 #define AUDIOHD_VID_NVIDIA 0x10de 38 #define AUDIOHD_VID_SIGMATEL 0x8384 39 40 /* 41 * specific codec id used by specific vendors 42 */ 43 #define AUDIOHD_CODECID_HP 0x111d7608 44 #define AUDIOHD_CODECID_ALC888 0x10ec0888 45 #define AUDIOHD_CODECID_SONY1 0x10ec0260 46 #define AUDIOHD_CODECID_SONY2 0x10ec0262 47 48 #define AUDIOHD_INTS 50 49 #define AUDIOHD_MAX_INTS 1500 50 #define AUDIOHD_MIN_INTS 32 51 52 #define AUDIOHD_DEV_CONFIG "onboard1" 53 #define AUDIOHD_DEV_VERSION "a" 54 55 #define AUDIOHD_FMT_PCM 0x001 56 /* 57 * Only for Intel hardware: 58 * PCI Express traffic class select register in PCI configure space 59 */ 60 #define AUDIOHD_INTEL_PCI_TCSEL 0x44 61 62 /* 63 * Only for ATI SB450: 64 * MISC control register 2 65 */ 66 #define AUDIOHD_ATI_PCI_MISC2 0x42 67 #define AUDIOHD_ATI_MISC2_SNOOP 0x02 68 #define AUDIOHDC_NID(x) x 69 #define AUDIOHDC_NULL_NODE -1 70 #define AUDIOHD_NULL_CONN ((uint_t)(-1)) 71 /* 72 * currently, only the format of 48K sample rate, 16-bit 73 * 2-channel is supported. 74 */ 75 #define AUDIOHD_FMT_PCMOUT 0x0011 76 #define AUDIOHD_FMT_PCMIN 0x0011 77 78 #define AUDIOHD_EXT_AMP_MASK 0x00010000 79 #define AUDIOHD_EXT_AMP_ENABLE 0x02 80 /* NVIDIA snoop */ 81 #define AUDIOHD_NVIDIA_SNOOP 0x0f 82 83 /* Power On/Off */ 84 #define AUDIOHD_PW_OFF 1 85 #define AUDIOHD_PW_ON 0 86 #define AUDIOHD_PW_D0 0 87 #define AUDIOHD_PW_D2 2 88 89 #define AUDIOHD_INTEL_TCS_MASK 0xf8 90 #define AUDIOHD_ATI_MISC2_MASK 0xf8 91 92 /* Pin speaker On/Off */ 93 #define AUDIOHD_SP_ON 1 94 #define AUDIOHD_SP_OFF 0 95 96 #define AUDIOHD_PORT_MAX 15 97 #define AUDIOHD_CODEC_MAX 16 98 #define AUDIOHD_MEMIO_LEN 0x4000 99 100 #define AUDIOHD_RETRY_TIMES 60 101 #define AUDIOHD_TEST_TIMES 500 102 #define AUDIOHD_OUTSTR_NUM_OFF 12 103 #define AUDIOHD_INSTR_NUM_OFF 8 104 105 #define AUDIOHD_CORB_SIZE_OFF 0x4e 106 107 #define AUDIOHD_URCAP_MASK 0x80 108 #define AUDIOHD_DTCCAP_MASK 0x4 109 #define AUDIOHD_UR_ENABLE_OFF 8 110 #define AUDIOHD_UR_TAG_MASK 0x1f 111 112 #define AUDIOHD_CIS_MASK 0x40000000 113 114 #define AUDIOHD_RIRB_UR_MASK 0x10 115 #define AUDIOHD_RIRB_CODEC_MASK 0xf 116 #define AUDIOHD_RIRB_WID_OFF 27 117 #define AUDIOHD_RIRB_INTRCNT 0x0 118 #define AUDIOHD_RIRB_WPMASK 0xff 119 120 #define AUDIOHD_FORM_MASK 0x0080 121 #define AUDIOHD_LEN_MASK 0x007f 122 #define AUDIOHD_PIN_CAP_MASK 0x00000010 123 #define AUDIOHD_PIN_CONF_MASK 0xc0000000 124 #define AUDIOHD_PIN_CON_MASK 3 125 #define AUDIOHD_PIN_CON_STEP 30 126 #define AUDIOHD_PIN_IO_MASK 0X0018 127 #define AUDIOHD_PIN_SEQ_MASK 0x0000000f 128 #define AUDIOHD_PIN_ASO_MASK 0x000000f0 129 #define AUDIOHD_PIN_ASO_OFF 0x4 130 #define AUDIOHD_PIN_DEV_MASK 0x00f00000 131 #define AUDIOHD_PIN_DEV_OFF 20 132 #define AUDIOHD_PIN_NUMS 6 133 #define AUDIOHD_PIN_NO_CONN 0x40000000 134 #define AUDIOHD_PIN_IN_ENABLE 0x20 135 #define AUDIOHD_PIN_OUT_ENABLE 0x40 136 #define AUDIOHD_PIN_PRES_OFF 0x20 137 #define AUDIOHD_PIN_CONTP_OFF 0x1e 138 #define AUDIOHD_PIN_CON_JACK 0 139 #define AUDIOHD_PIN_CON_FIXED 0x2 140 #define AUDIOHD_PIN_CONTP_MASK 0x3 141 #define AUDIOHD_PIN_VREF_L1 0x20 142 #define AUDIOHD_PIN_VREF_L2 0x10 143 #define AUDIOHD_PIN_VREF_L3 0x04 144 #define AUDIOHD_PIN_VREF_L4 0x02 145 #define AUDIOHD_PIN_VREF_OFF 8 146 #define AUDIOHD_PIN_VREF_MASK 0xff 147 #define AUDIOHD_PIN_CLR_MASK 0xf 148 #define AUDIOHD_PIN_CLR_OFF 12 149 150 151 #define AUDIOHD_VERB_ADDR_OFF 28 152 #define AUDIOHD_VERB_NID_OFF 20 153 #define AUDIOHD_VERB_CMD_OFF 8 154 #define AUDIOHD_VERB_CMD16_OFF 16 155 156 #define AUDIOHD_RING_MAX_SIZE 0x00ff 157 #define AUDIOHD_POS_MASK ~0x00000003 158 #define AUDIOHD_REC_TAG_OFF 4 159 #define AUDIOHD_PLAY_TAG_OFF 4 160 #define AUDIOHD_PLAY_CTL_OFF 2 161 #define AUDIOHD_REC_CTL_OFF 2 162 163 #define AUDIOHD_SPDIF_ON 1 164 #define AUDIOHD_SPDIF_MASK 0x00ff 165 166 #define AUDIOHD_GAIN_OFF 8 167 168 #define AUDIOHD_CODEC_STR_OFF 16 169 #define AUDIOHD_CODEC_STR_MASK 0x000000ff 170 #define AUDIOHD_CODEC_NUM_MASK 0x000000ff 171 #define AUDIOHD_CODEC_TYPE_MASK 0x000000ff 172 173 #define AUDIOHD_FRAGFR_ALIGN 16 174 #define AUDIOHD_BDLE_BUF_ALIGN 128 175 #define AUDIOHD_CMDIO_ENT_MASK 0x00ff /* 256 entries for CORB/RIRB */ 176 #define AUDIOHD_CDBIO_CORB_LEN 1024 /* 256 entries for CORB, 1024B */ 177 #define AUDIOHD_CDBIO_RIRB_LEN 2048 /* 256 entries for RIRB, 2048B */ 178 #define AUDIOHD_BDLE_NUMS 4 /* 4 entires for record/play BD list */ 179 180 #define AUDIOHD_PORT_UNMUTE (0xffffffff) 181 182 /* 183 * Audio registers of high definition 184 */ 185 #define AUDIOHD_REG_GCAP 0x00 186 #define AUDIOHDR_GCAP_OUTSTREAMS 0xf000 187 #define AUDIOHDR_GCAP_INSTREAMS 0x0f00 188 #define AUDIOHDR_GCAP_BSTREAMS 0x00f8 189 #define AUDIOHDR_GCAP_NSDO 0x0006 190 #define AUDIOHDR_GCAP_64OK 0x0001 191 192 #define AUDIOHD_REG_VMIN 0x02 193 #define AUDIOHD_REG_VMAJ 0x03 194 #define AUDIOHD_REG_OUTPAY 0x04 195 #define AUDIOHD_REG_INPAY 0x06 196 #define AUDIOHD_REG_GCTL 0x08 197 #define AUDIOHD_REG_WAKEEN 0x0C 198 #define AUDIOHD_REG_STATESTS 0x0E 199 #define AUDIOHD_STATESTS_BIT_SDINS 0x7F 200 201 #define AUDIOHD_REG_GSTS 0x10 202 #define AUDIOHD_REG_INTCTL 0x20 203 #define AUDIOHD_INTCTL_BIT_GIE 0x80000000 204 #define AUDIOHD_INTCTL_BIT_CIE 0x40000000 205 #define AUDIOHD_INTCTL_BIT_SIE 0x3FFFFFFF 206 207 208 #define AUDIOHD_REG_INTSTS 0x24 209 #define AUDIOHD_INTSTS_BIT_GIS 0x80000000 210 #define AUDIOHD_INTSTS_BIT_CIS 0x40000000 211 #define AUDIOHD_INTSTS_BIT_SINTS (0x3fffffff) 212 213 #define AUDIOHD_REG_WALCLK 0x30 214 #define AUDIOHD_REG_SYNC 0x38 215 216 #define AUDIOHD_REG_CORBLBASE 0x40 217 #define AUDIOHD_REG_CORBUBASE 0x44 218 #define AUDIOHD_REG_CORBWP 0x48 219 #define AUDIOHD_REG_CORBRP 0x4A 220 #define AUDIOHD_REG_CORBCTL 0x4C 221 #define AUDIOHD_REG_CORBST 0x4D 222 #define AUDIOHD_REG_CORBSIZE 0x4E 223 224 #define AUDIOHD_REG_RIRBLBASE 0x50 225 #define AUDIOHD_REG_RIRBUBASE 0x54 226 #define AUDIOHD_REG_RIRBWP 0x58 227 #define AUDIOHD_REG_RINTCNT 0x5A 228 #define AUDIOHD_REG_RIRBCTL 0x5C 229 #define AUDIOHD_REG_RIRBSTS 0x5D 230 #define AUDIOHD_REG_RIRBSIZE 0x5E 231 232 #define AUDIOHD_REG_IC 0x60 233 #define AUDIOHD_REG_IR 0x64 234 #define AUDIOHD_REG_IRS 0x68 235 #define AUDIOHD_REG_DPLBASE 0x70 236 #define AUDIOHD_REG_DPUBASE 0x74 237 238 #define AUDIOHD_REG_SD_BASE 0x80 239 #define AUDIOHD_REG_SD_LEN 0x20 240 241 /* 242 * Offset of Stream Descriptor Registers 243 */ 244 #define AUDIOHD_SDREG_OFFSET_CTL 0x00 245 #define AUDIOHD_SDREG_OFFSET_STS 0x03 246 #define AUDIOHD_SDREG_OFFSET_LPIB 0x04 247 #define AUDIOHD_SDREG_OFFSET_CBL 0x08 248 #define AUDIOHD_SDREG_OFFSET_LVI 0x0c 249 #define AUDIOHD_SDREG_OFFSET_FIFOW 0x0e 250 #define AUDIOHD_SDREG_OFFSET_FIFOSIZE 0x10 251 #define AUDIOHD_SDREG_OFFSET_FORMAT 0x12 252 #define AUDIOHD_SDREG_OFFSET_BDLPL 0x18 253 #define AUDIOHD_SDREG_OFFSET_BDLPU 0x1c 254 255 /* bits for stream descriptor control reg */ 256 #define AUDIOHDR_SD_CTL_DEIE 0x000010 257 #define AUDIOHDR_SD_CTL_FEIE 0x000008 258 #define AUDIOHDR_SD_CTL_IOCE 0x000004 259 #define AUDIOHDR_SD_CTL_SRUN 0x000002 260 #define AUDIOHDR_SD_CTL_SRST 0x000001 261 #define AUDIOHDR_SD_CTL_INTS \ 262 (AUDIOHDR_SD_CTL_DEIE | \ 263 AUDIOHDR_SD_CTL_FEIE | \ 264 AUDIOHDR_SD_CTL_IOCE) 265 266 267 /* bits for stream descriptor status register */ 268 #define AUDIOHDR_SD_STS_BCIS 0x0004 269 #define AUDIOHDR_SD_STS_FIFOE 0x0008 270 #define AUDIOHDR_SD_STS_DESE 0x0010 271 #define AUDIOHDR_SD_STS_FIFORY 0x0020 272 #define AUDIOHDR_SD_STS_INTRS \ 273 (AUDIOHDR_SD_STS_BCIS | \ 274 AUDIOHDR_SD_STS_FIFOE | \ 275 AUDIOHDR_SD_STS_DESE) 276 277 278 /* bits for GCTL register */ 279 #define AUDIOHDR_GCTL_CRST 0x00000001 280 #define AUDIOHDR_GCTL_URESPE 0x00000100 281 282 /* bits for CORBRP register */ 283 #define AUDIOHDR_CORBRP_RESET 0x8000 284 #define AUDIOHDR_CORBRP_WPTR 0x00ff 285 286 /* bits for CORBCTL register */ 287 #define AUDIOHDR_CORBCTL_CMEIE 0x01 288 #define AUDIOHDR_CORBCTL_DMARUN 0x02 289 290 /* bits for CORB SIZE register */ 291 #define AUDIOHDR_CORBSZ_8 0 292 #define AUDIOHDR_CORBSZ_16 1 293 #define AUDIOHDR_CORBSZ_256 2 294 295 /* bits for RIRBCTL register */ 296 #define AUDIOHDR_RIRBCTL_RINTCTL 0x01 297 #define AUDIOHDR_RIRBCTL_DMARUN 0x02 298 #define AUDIOHDR_RIRBCTL_RIRBOIC 0x04 299 #define AUDIOHDR_RIRBCTL_RSTINT 0xfe 300 301 /* bits for RIRBWP register */ 302 #define AUDIOHDR_RIRBWP_RESET 0x8000 303 #define AUDIOHDR_RIRBWP_WPTR 0x00ff 304 305 /* bits for RIRB SIZE register */ 306 #define AUDIOHDR_RIRBSZ_8 0 307 #define AUDIOHDR_RIRBSZ_16 1 308 #define AUDIOHDR_RIRBSZ_256 2 309 310 #define AUDIOHD_BDLE_RIRB_SDI 0x0000000f 311 #define AUDIOHD_BDLE_RIRB_UNSOLICIT 0x00000010 312 313 /* HD spec: ID of Root node is 0 */ 314 #define AUDIOHDC_NODE_ROOT 0x00 315 316 /* HD spec: ID of audio function group is "1" */ 317 #define AUDIOHDC_AUDIO_FUNC_GROUP 1 318 319 /* 320 * HD audio verbs can be either 12-bit or 4-bit in length. 321 */ 322 #define AUDIOHDC_12BIT_VERB_MASK 0xfffff000 323 #define AUDIOHDC_4BIT_VERB_MASK 0xfffffff0 324 325 #define AUDIOHDC_SAMPR48000 48000 326 #define AUDIOHDC_MAX_BEEP_GEN 12000 327 #define AUDIOHDC_MIX_BEEP_GEN 47 328 #define AUDIOHDC_MUTE_BEEP_GEN 0x0 329 330 /* 331 * 12-bit verbs 332 */ 333 #define AUDIOHDC_VERB_GET_PARAM 0xf00 334 335 #define AUDIOHDC_VERB_GET_CONN_SEL 0xf01 336 #define AUDIOHDC_VERB_SET_CONN_SEL 0x701 337 338 #define AUDIOHDC_VERB_GET_CONN_LIST_ENT 0xf02 339 #define AUDIOHDC_VERB_GET_PROCESS_STATE 0xf03 340 #define AUDIOHDC_VERB_GET_SDI_SEL 0xf04 341 342 #define AUDIOHDC_VERB_GET_POWER_STATE 0xf05 343 #define AUDIOHDC_VERB_SET_POWER_STATE 0x705 344 345 #define AUDIOHDC_VERB_GET_STREAM_CHANN 0xf06 346 #define AUDIOHDC_VERB_SET_STREAM_CHANN 0x706 347 348 #define AUDIOHDC_VERB_GET_PIN_CTRL 0xf07 349 #define AUDIOHDC_VERB_SET_PIN_CTRL 0x707 350 351 #define AUDIOHDC_VERB_GET_UNS_ENABLE 0xf08 352 353 #define AUDIOHDC_VERB_GET_PIN_SENSE 0xf09 354 #define AUDIOHDC_VERB_EXEC_PIN_SENSE 0x709 355 356 #define AUDIOHDC_VERB_GET_BEEP_GEN 0xf0a 357 #define AUDIOHDC_VERB_SET_BEEP_GEN 0x70a 358 359 #define AUDIOHDC_VERB_GET_EAPD 0xf0c 360 #define AUDIOHDC_VERB_SET_EAPD 0x70c 361 362 #define AUDIOHDC_VERB_GET_DEFAULT_CONF 0xf1c 363 #define AUDIOHDC_VERB_GET_SPDIF_CTL 0xf0d 364 #define AUDIOHDC_VERB_SET_SPDIF_LCL 0x70d 365 366 #define AUDIOHDC_VERB_SET_URCTRL 0x708 367 #define AUDIOHDC_VERB_GET_PIN_SENSE 0xf09 368 369 #define AUDIOHDC_VERB_GET_GPIO_MASK 0xf16 370 #define AUDIOHDC_VERB_SET_GPIO_MASK 0x716 371 372 #define AUDIOHDC_VERB_GET_GPIO_DIREC 0xf17 373 #define AUDIOHDC_VERB_SET_GPIO_DIREC 0x717 374 375 #define AUDIOHDC_VERB_GET_GPIO_DATA 0xf15 376 #define AUDIOHDC_VERB_SET_GPIO_DATA 0x715 377 378 #define AUDIOHDC_VERB_GET_GPIO_STCK 0xf1a 379 #define AUDIOHDC_VERB_SET_GPIO_STCK 0x71a 380 381 #define AUDIOHDC_GPIO_ENABLE 0xff 382 #define AUDIOHDC_GPIO_DIRECT 0xf1 383 384 #define AUDIOHDC_GPIO_DATA_CTRL 0xff 385 #define AUDIOHDC_GPIO_STCK_CTRL 0xff 386 /* 387 * 4-bit verbs 388 */ 389 #define AUDIOHDC_VERB_GET_CONV_FMT 0xa 390 #define AUDIOHDC_VERB_SET_CONV_FMT 0x2 391 392 #define AUDIOHDC_VERB_GET_AMP_MUTE 0xb 393 #define AUDIOHDC_VERB_SET_AMP_MUTE 0x3 394 #define AUDIOHDC_VERB_SET_BEEP_VOL 0x3A0 395 396 /* 397 * parameters of nodes 398 */ 399 #define AUDIOHDC_PAR_VENDOR_ID 0x00 400 #define AUDIOHDC_PAR_SUBSYS_ID 0x01 401 #define AUDIOHDC_PAR_REV_ID 0x02 402 #define AUDIOHDC_PAR_NODE_COUNT 0x04 403 #define AUDIOHDC_PAR_FUNCTION_TYPE 0x05 404 #define AUDIOHDC_PAR_AUDIO_FG_CAP 0x08 405 #define AUDIOHDC_PAR_AUDIO_WID_CAP 0x09 406 #define AUDIOHDC_PAR_PCM 0x0a 407 #define AUDIOHDC_PAR_STREAM 0x0b 408 #define AUDIOHDC_PAR_PIN_CAP 0x0c 409 #define AUDIOHDC_PAR_INAMP_CAP 0x0d 410 #define AUDIOHDC_PAR_CONNLIST_LEN 0x0e 411 #define AUDIOHDC_PAR_POWER_STATE 0x0f 412 #define AUDIOHDC_PAR_PROC_CAP 0x10 413 #define AUDIOHDC_PAR_GPIO_CAP 0x11 414 #define AUDIOHDC_PAR_OUTAMP_CAP 0x12 415 416 /* 417 * bits for get/set amplifier gain/mute 418 */ 419 #define AUDIOHDC_AMP_SET_OUTPUT 0x8000 420 #define AUDIOHDC_AMP_SET_INPUT 0x4000 421 #define AUDIOHDC_AMP_SET_LEFT 0x2000 422 #define AUDIOHDC_AMP_SET_RIGHT 0x1000 423 #define AUDIOHDC_AMP_SET_MUTE 0x0080 424 #define AUDIOHDC_AMP_SET_LNR 0x3000 425 #define AUDIOHDC_AMP_SET_LR_INPUT 0x7000 426 #define AUDIOHDC_AMP_SET_LR_OUTPUT 0xb000 427 #define AUDIOHDC_AMP_SET_INDEX_OFFSET 8 428 #define AUDIOHDC_AMP_SET_GAIN_MASK 0x007f 429 #define AUDIOHDC_GAIN_MAX 0x7f 430 #define AUDIOHDC_GAIN_BITS 7 431 #define AUDIOHDC_GAIN_DEFAULT 0x0f 432 433 #define AUDIOHDC_AMP_GET_OUTPUT 0x8000 434 #define AUDIOHDC_AMP_GET_INPUT 0x0000 435 436 /* value used to set max volume for left output */ 437 #define AUDIOHDC_AMP_LOUT_MAX \ 438 (AUDIOHDC_AMP_SET_OUTPUT | \ 439 AUDIOHDC_AMP_SET_LEFT | \ 440 AUDIOHDC_GAIN_MAX) 441 442 /* value used to set max volume for right output */ 443 #define AUDIOHDC_AMP_ROUT_MAX \ 444 (AUDIOHDC_AMP_SET_OUTPUT | \ 445 AUDIOHDC_AMP_SET_RIGHT | \ 446 AUDIOHDC_GAIN_MAX) 447 448 449 /* 450 * Bits for pin widget control verb 451 */ 452 #define AUDIOHDC_PIN_CONTROL_HP_ENABLE 0x80 453 #define AUDIOHDC_PIN_CONTROL_OUT_ENABLE 0x40 454 #define AUDIOHDC_PIN_CONTROL_IN_ENABLE 0x20 455 456 /* 457 * Bits for Amplifier capabilities 458 */ 459 #define AUDIOHDC_AMP_CAP_MUTE_CAP 0x80000000 460 #define AUDIOHDC_AMP_CAP_STEP_SIZE 0x007f0000 461 #define AUDIOHDC_AMP_CAP_STEP_NUMS 0x00007f00 462 #define AUDIOHDC_AMP_CAP_0DB_OFFSET 0x0000007f 463 464 465 /* 466 * Bits for Audio Widget Capabilities 467 */ 468 #define AUDIOHD_WIDCAP_STEREO 0x00000001 469 #define AUDIOHD_WIDCAP_INAMP 0x00000002 470 #define AUDIOHD_WIDCAP_OUTAMP 0x00000004 471 #define AUDIOHD_WIDCAP_AMP_OVRIDE 0x00000008 472 #define AUDIOHD_WIDCAP_FMT_OVRIDE 0x00000010 473 #define AUDIOHD_WIDCAP_STRIP 0x00000020 474 #define AUDIOHD_WIDCAP_PROC_WID 0x00000040 475 #define AUDIOHD_WIDCAP_UNSOL 0x00000080 476 #define AUDIOHD_WIDCAP_CONNLIST 0x00000100 477 #define AUDIOHD_WIDCAP_DIGIT 0x00000200 478 #define AUDIOHD_WIDCAP_PWRCTRL 0x00000400 479 #define AUDIOHD_WIDCAP_LRSWAP 0x00000800 480 #define AUDIOHD_WIDCAP_TYPE 0x00f00000 481 #define AUDIOHD_WIDCAP_TO_WIDTYPE(wcap) \ 482 ((wcap & AUDIOHD_WIDCAP_TYPE) >> 20) 483 484 485 #define AUDIOHD_CODEC_FAILURE (uint32_t)(-1) 486 487 /* 488 * buffer descriptor list entry of stream descriptor 489 */ 490 typedef struct { 491 uint64_t sbde_addr; 492 uint32_t sbde_len; 493 uint32_t 494 sbde_ioc: 1, 495 reserved: 31; 496 }sd_bdle_t; 497 498 499 #define AUDIOHD_PLAY_STARTED 0x00000001 500 #define AUDIOHD_PLAY_EMPTY 0x00000002 501 #define AUDIOHD_PLAY_PAUSED 0x00000004 502 #define AUDIOHD_RECORD_STARTED 0x00000008 503 504 enum audiohda_widget_type { 505 WTYPE_AUDIO_OUT = 0, 506 WTYPE_AUDIO_IN, 507 WTYPE_AUDIO_MIX, 508 WTYPE_AUDIO_SEL, 509 WTYPE_PIN, 510 WTYPE_POWER, 511 WTYPE_VOL_KNOB, 512 WTYPE_BEEP, 513 WTYPE_VENDOR = 0xf 514 }; 515 516 enum audiohda_device_type { 517 DTYPE_LINEOUT = 0, 518 DTYPE_SPEAKER, 519 DTYPE_HP_OUT, 520 DTYPE_CD, 521 DTYPE_SPDIF_OUT, 522 DTYPE_DIGIT_OUT, 523 DTYPE_MODEM_SIDE, 524 DTYPE_MODEM_HNAD_SIDE, 525 DTYPE_LINE_IN, 526 DTYPE_AUX, 527 DTYPE_MIC_IN, 528 DTYPE_TEL, 529 DTYPE_SPDIF_IN, 530 DTYPE_DIGIT_IN, 531 DTYPE_OTHER = 0x0f, 532 }; 533 534 enum audiohd_pin_color { 535 AUDIOHD_PIN_UNKNOWN = 0, 536 AUDIOHD_PIN_BLACK, 537 AUDIOHD_PIN_GREY, 538 AUDIOHD_PIN_BLUE, 539 AUDIOHD_PIN_GREEN, 540 AUDIOHD_PIN_RED, 541 AUDIOHD_PIN_ORANGE, 542 AUDIOHD_PIN_YELLOW, 543 AUDIOHD_PIN_PURPLE, 544 AUDIOHD_PIN_PINK, 545 AUDIOHD_PIN_WHITE = 0xe, 546 AUDIOHD_PIN_OTHER = 0xf, 547 }; 548 549 #define CTRL_NUM 16 550 551 /* values for audiohd_widget.path_flags */ 552 #define AUDIOHD_PATH_DAC (1 << 0) 553 #define AUDIOHD_PATH_ADC (1 << 1) 554 #define AUDIOHD_PATH_MON (1 << 2) 555 #define AUDIOHD_PATH_NOMON (1 << 3) 556 #define AUDIOHD_PATH_BEEP (1 << 4) 557 558 typedef struct audiohd_path audiohd_path_t; 559 typedef struct audiohd_widget audiohd_widget_t; 560 typedef struct audiohd_state audiohd_state_t; 561 typedef struct audiohd_pin audiohd_pin_t; 562 typedef struct hda_codec hda_codec_t; 563 typedef uint32_t wid_t; /* id of widget */ 564 typedef struct audiohd_entry_prop audiohd_entry_prop_t; 565 typedef enum audiohda_device_type audiohda_device_type_t; 566 typedef enum audiohd_pin_color audiohd_pin_color_t; 567 568 #define AUDIOHD_MAX_WIDGET 128 569 #define AUDIOHD_MAX_CONN 16 570 #define AUDIOHD_MAX_PINS 16 571 #define AUDIOHD_MAX_DEPTH 8 572 573 struct audiohd_entry_prop { 574 uint32_t conn_len; 575 uint32_t mask_range; 576 uint32_t mask_wid; 577 wid_t input_wid; 578 int conns_per_entry; 579 int bits_per_conn; 580 }; 581 struct audiohd_widget { 582 wid_t wid_wid; 583 hda_codec_t *codec; 584 enum audiohda_widget_type type; 585 586 uint32_t widget_cap; 587 uint32_t pcm_format; 588 uint32_t inamp_cap; 589 uint32_t outamp_cap; 590 591 uint32_t path_flags; 592 593 int out_weight; 594 int in_weight; 595 int finish; 596 597 /* 598 * wid of possible & selected input connections 599 */ 600 wid_t avail_conn[AUDIOHD_MAX_CONN]; 601 wid_t selconn; 602 /* 603 * for monitor path 604 */ 605 wid_t selmon[AUDIOHD_MAX_CONN]; 606 uint16_t used; 607 608 /* 609 * available (input) connections. 0 means this widget 610 * has fixed connection 611 */ 612 int nconns; 613 614 /* 615 * pointer to struct depending on widget type: 616 * 1. DAC audiohd_ostream_t 617 * 2. ADC audiohd_istream_t 618 * 3. PIN audiohd_pin_t 619 */ 620 void *priv; 621 }; 622 623 #define AUDIOHD_FLAG_LINEOUT (1 << 0) 624 #define AUDIOHD_FLAG_SPEAKER (1 << 1) 625 #define AUDIOHD_FLAG_HP (1 << 2) 626 #define AUDIOHD_FLAG_MONO (1 << 3) 627 628 #define AUDIOHD_MAX_MIXER 5 629 #define AUDIOHD_MAX_PIN 4 630 631 #define PORT_DAC 0 632 #define PORT_ADC 1 633 #define PORT_MAX 2 634 typedef enum { 635 PLAY = 0, 636 RECORD = 1, 637 BEEP = 2, 638 } path_type_t; 639 640 struct audiohd_path { 641 wid_t adda_wid; 642 wid_t beep_wid; 643 644 wid_t pin_wid[AUDIOHD_MAX_PINS]; 645 int sum_selconn[AUDIOHD_MAX_PINS]; 646 int mon_wid[AUDIOHD_MAX_PIN][AUDIOHD_MAX_MIXER]; 647 int pin_nums; 648 int maxmixer[AUDIOHD_MAX_PINS]; 649 650 path_type_t path_type; 651 652 wid_t mute_wid; 653 int mute_dir; 654 wid_t gain_wid; 655 int gain_dir; 656 uint32_t gain_bits; 657 658 uint32_t pin_outputs; 659 uint8_t tag; 660 661 hda_codec_t *codec; 662 663 wid_t sum_wid; 664 665 audiohd_state_t *statep; 666 }; 667 668 typedef struct audiohd_port 669 { 670 uint8_t nchan; 671 int index; 672 uint16_t regoff; 673 boolean_t started; 674 boolean_t triggered; 675 676 unsigned fragfr; 677 unsigned nframes; 678 uint64_t count; 679 int curpos; 680 int len; 681 int intrs; 682 683 uint_t format; 684 unsigned sync_dir; 685 686 ddi_dma_handle_t samp_dmah; 687 ddi_acc_handle_t samp_acch; 688 size_t samp_size; 689 caddr_t samp_kaddr; 690 uint64_t samp_paddr; 691 692 ddi_dma_handle_t bdl_dmah; 693 ddi_acc_handle_t bdl_acch; 694 size_t bdl_size; 695 caddr_t bdl_kaddr; 696 uint64_t bdl_paddr; 697 698 audio_engine_t *engine; 699 audiohd_state_t *statep; 700 }audiohd_port_t; 701 702 typedef struct audiohd_ctrl 703 { 704 audiohd_state_t *statep; 705 audio_ctrl_t *ctrl; 706 uint32_t num; 707 uint64_t val; 708 } audiohd_ctrl_t; 709 710 struct audiohd_pin { 711 audiohd_pin_t *next; 712 wid_t wid; 713 wid_t mute_wid; /* node used to mute this pin */ 714 int mute_dir; /* 1: input, 2: output */ 715 wid_t gain_wid; /* node for gain control */ 716 int gain_dir; /* _OUTPUT/_INPUT */ 717 uint32_t gain_bits; 718 719 uint8_t vrefvalue; /* value of VRef */ 720 721 uint32_t cap; 722 uint32_t config; 723 uint32_t ctrl; 724 uint32_t assoc; 725 uint32_t seq; 726 wid_t adc_dac_wid; /* AD/DA wid which can route to this pin */ 727 wid_t beep_wid; 728 int no_phys_conn; 729 enum audiohda_device_type device; 730 731 /* 732 * mg_dir, mg_gain, mg_wid are used to store the monitor gain control 733 * widget wid. 734 */ 735 int mg_dir[AUDIOHD_MAX_CONN]; 736 int mg_gain[AUDIOHD_MAX_CONN]; 737 int mg_wid[AUDIOHD_MAX_CONN]; 738 int num; 739 int finish; 740 741 }; 742 743 typedef struct { 744 ddi_dma_handle_t ad_dmahdl; 745 ddi_acc_handle_t ad_acchdl; 746 caddr_t ad_vaddr; /* virtual addr */ 747 uint64_t ad_paddr; /* physical addr */ 748 size_t ad_req_sz; /* required size of memory */ 749 size_t ad_real_sz; /* real size of memory */ 750 } audiohd_dma_t; 751 752 struct hda_codec { 753 uint8_t index; /* codec address */ 754 uint32_t vid; /* vendor id and device id */ 755 uint32_t revid; /* revision id */ 756 wid_t wid_afg; /* id of AFG */ 757 wid_t first_wid; /* wid of 1st subnode of AFG */ 758 wid_t last_wid; /* wid of the last subnode of AFG */ 759 int nnodes; /* # of subnodes of AFG */ 760 uint8_t nistream; 761 762 uint32_t outamp_cap; 763 uint32_t inamp_cap; 764 uint32_t stream_format; 765 uint32_t pcm_format; 766 767 audiohd_state_t *soft_statep; 768 769 /* use wid as index to the array of widget pointers */ 770 audiohd_widget_t *widget[AUDIOHD_MAX_WIDGET]; 771 772 773 audiohd_port_t *port[AUDIOHD_PORT_MAX]; 774 uint8_t portnum; 775 audiohd_pin_t *first_pin; 776 }; 777 778 #define AUDIOHD_MAX_ASSOC 15 779 struct audiohd_state { 780 dev_info_t *hda_dip; 781 kstat_t *hda_ksp; 782 kmutex_t hda_mutex; 783 uint32_t hda_flags; 784 785 boolean_t soft_volume; 786 boolean_t intr_added; 787 788 caddr_t hda_reg_base; 789 ddi_acc_handle_t hda_pci_handle; 790 ddi_acc_handle_t hda_reg_handle; 791 ddi_iblock_cookie_t hda_intr_cookie; 792 793 audiohd_dma_t hda_dma_corb; 794 audiohd_dma_t hda_dma_rirb; 795 796 797 uint8_t hda_rirb_rp; /* read pointer for rirb */ 798 uint16_t hda_codec_mask; 799 800 801 audio_dev_t *adev; 802 803 804 int hda_pint_freq; /* play intr frequence */ 805 int hda_rint_freq; /* record intr frequence */ 806 807 int hda_input_streams; /* # of input stream */ 808 int hda_output_streams; /* # of output stream */ 809 int hda_streams_nums; /* # of stream */ 810 811 uint_t hda_play_regbase; 812 uint_t hda_record_regbase; 813 814 uint_t hda_play_stag; /* tag of playback stream */ 815 uint_t hda_record_stag; /* tag of record stream */ 816 uint_t hda_play_lgain; /* left gain for playback */ 817 uint_t hda_play_rgain; /* right gain for playback */ 818 819 /* 820 * Now, for the time being, we add some fields 821 * for parsing codec topology 822 */ 823 hda_codec_t *codec[AUDIOHD_CODEC_MAX]; 824 /* 825 * Suspend/Resume used fields 826 */ 827 boolean_t suspended; 828 boolean_t monitor_unsupported; 829 830 audiohd_path_t *path[AUDIOHD_PORT_MAX]; 831 uint8_t pathnum; 832 audiohd_port_t *port[PORT_MAX]; 833 uint8_t pchan; 834 uint8_t rchan; 835 836 uint64_t inmask; 837 838 uint_t hda_out_ports; 839 uint_t in_port; 840 841 /* 842 * Controls 843 */ 844 audiohd_ctrl_t *controls[CTRL_NUM]; 845 846 /* for multichannel */ 847 uint8_t chann[AUDIOHD_MAX_ASSOC]; 848 uint8_t assoc; 849 850 }; 851 852 853 /* 854 * Operation for high definition audio control system bus 855 * interface registers 856 */ 857 #define AUDIOHD_REG_GET8(reg) \ 858 ddi_get8(statep->hda_reg_handle, \ 859 (void *)((char *)statep->hda_reg_base + (reg))) 860 861 #define AUDIOHD_REG_GET16(reg) \ 862 ddi_get16(statep->hda_reg_handle, \ 863 (void *)((char *)statep->hda_reg_base + (reg))) 864 865 #define AUDIOHD_REG_GET32(reg) \ 866 ddi_get32(statep->hda_reg_handle, \ 867 (void *)((char *)statep->hda_reg_base + (reg))) 868 869 #define AUDIOHD_REG_GET64(reg) \ 870 ddi_get64(statep->hda_reg_handle, \ 871 (void *)((char *)statep->hda_reg_base + (reg))) 872 873 #define AUDIOHD_REG_SET8(reg, val) \ 874 ddi_put8(statep->hda_reg_handle, \ 875 (void *)((char *)statep->hda_reg_base + (reg)), (val)) 876 877 #define AUDIOHD_REG_SET16(reg, val) \ 878 ddi_put16(statep->hda_reg_handle, \ 879 (void *)((char *)statep->hda_reg_base + (reg)), (val)) 880 881 #define AUDIOHD_REG_SET32(reg, val) \ 882 ddi_put32(statep->hda_reg_handle, \ 883 (void *)((char *)statep->hda_reg_base + (reg)), (val)) 884 885 #define AUDIOHD_REG_SET64(reg, val) \ 886 ddi_put64(statep->hda_reg_handle, \ 887 (void *)((char *)statep->hda_reg_base + (reg)), (val)) 888 889 890 /* 891 * enable a pin widget to output 892 */ 893 #define AUDIOHD_ENABLE_PIN_OUT(statep, caddr, wid) \ 894 { \ 895 uint32_t lTmp; \ 896 \ 897 lTmp = audioha_codec_verb_get(statep, caddr, wid, \ 898 AUDIOHDC_VERB_GET_PIN_CTRL, 0); \ 899 if (lTmp == AUDIOHD_CODEC_FAILURE) \ 900 return (DDI_FAILURE); \ 901 lTmp = audioha_codec_verb_get(statep, caddr, wid, \ 902 AUDIOHDC_VERB_SET_PIN_CTRL, \ 903 (lTmp | AUDIOHDC_PIN_CONTROL_OUT_ENABLE | \ 904 AUDIOHDC_PIN_CONTROL_HP_ENABLE)); \ 905 if (lTmp == AUDIOHD_CODEC_FAILURE) \ 906 return (DDI_FAILURE); \ 907 } 908 909 /* 910 * disable output pin 911 */ 912 #define AUDIOHD_DISABLE_PIN_OUT(statep, caddr, wid) \ 913 { \ 914 uint32_t lTmp; \ 915 \ 916 lTmp = audioha_codec_verb_get(statep, caddr, wid, \ 917 AUDIOHDC_VERB_GET_PIN_CTRL, 0); \ 918 if (lTmp == AUDIOHD_CODEC_FAILURE) \ 919 return (DDI_FAILURE); \ 920 lTmp = audioha_codec_verb_get(statep, caddr, wid, \ 921 AUDIOHDC_VERB_SET_PIN_CTRL, \ 922 (lTmp & ~AUDIOHDC_PIN_CONTROL_OUT_ENABLE)); \ 923 if (lTmp == AUDIOHD_CODEC_FAILURE) \ 924 return (DDI_FAILURE); \ 925 } 926 927 /* 928 * enable a pin widget to input 929 */ 930 #define AUDIOHD_ENABLE_PIN_IN(statep, caddr, wid) \ 931 { \ 932 (void) audioha_codec_verb_get(statep, caddr, wid, \ 933 AUDIOHDC_VERB_SET_PIN_CTRL, AUDIOHDC_PIN_CONTROL_IN_ENABLE | 4); \ 934 } 935 936 937 /* 938 * disable input pin 939 */ 940 #define AUDIOHD_DISABLE_PIN_IN(statep, caddr, wid) \ 941 { \ 942 uint32_t lTmp; \ 943 \ 944 lTmp = audioha_codec_verb_get(statep, caddr, wid, \ 945 AUDIOHDC_VERB_GET_PIN_CTRL, 0); \ 946 if (lTmp == AUDIOHD_CODEC_FAILURE) \ 947 return (DDI_FAILURE); \ 948 lTmp = audioha_codec_verb_get(statep, caddr, wid, \ 949 AUDIOHDC_VERB_SET_PIN_CTRL, \ 950 (lTmp & ~AUDIOHDC_PIN_CONTROL_IN_ENABLE)); \ 951 if (lTmp == AUDIOHD_CODEC_FAILURE) \ 952 return (DDI_FAILURE); \ 953 } 954 955 /* 956 * unmute an output pin 957 */ 958 #define AUDIOHD_NODE_UNMUTE_OUT(statep, caddr, wid) \ 959 { \ 960 if (audioha_codec_4bit_verb_get(statep, \ 961 caddr, wid, AUDIOHDC_VERB_SET_AMP_MUTE, \ 962 AUDIOHDC_AMP_SET_LR_OUTPUT | AUDIOHDC_GAIN_MAX) == \ 963 AUDIOHD_CODEC_FAILURE) \ 964 return (DDI_FAILURE); \ 965 } 966 967 #ifdef __cplusplus 968 } 969 #endif 970 971 #endif /* _SYS_AUDIOHD_IMPL_H_ */ 972