xref: /illumos-gate/usr/src/uts/common/io/audio/drv/audiohd/audiohd.h (revision aedf2b3bb56b025fcaf87b49ec6c8aeea07f16d7)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 #ifndef _SYS_AUDIOHD_IMPL_H_
26 #define	_SYS_AUDIOHD_IMPL_H_
27 
28 #ifdef __cplusplus
29 extern "C" {
30 #endif
31 
32 /*
33  * vendor IDs of PCI audio controllers
34  */
35 #define	AUDIOHD_VID_INTEL	0x8086
36 #define	AUDIOHD_VID_ATI		0x1002
37 #define	AUDIOHD_VID_CIRRUS	0x1013
38 #define	AUDIOHD_VID_NVIDIA	0x10de
39 #define	AUDIOHD_VID_REALTEK	0x10ec
40 #define	AUDIOHD_VID_CONEXANT	0x14f1
41 #define	AUDIOHD_VID_SIGMATEL	0x8384
42 
43 /*
44  * specific audiohd controller device id
45  */
46 #define	AUDIOHD_CONTROLLER_MCP51	0x10de026c
47 
48 /*
49  * specific codec id used by specific vendors
50  */
51 #define	AUDIOHD_CODEC_IDT7608	0x111d7608
52 #define	AUDIOHD_CODEC_IDT76B2	0x111d76b2
53 #define	AUDIOHD_CODEC_AD1981	0x11d41981
54 #define	AUDIOHD_CODEC_ALC272	0x10ec0272
55 #define	AUDIOHD_CODEC_ALC885	0x10ec0885
56 #define	AUDIOHD_CODECID_ALC888	0x10ec0888
57 #define	AUDIOHD_CODECID_SONY1	0x10ec0260
58 #define	AUDIOHD_CODECID_SONY2	0x10ec0262
59 
60 #define	AUDIOHD_INTS		50
61 #define	AUDIOHD_MAX_INTS	1500
62 #define	AUDIOHD_MIN_INTS	32
63 
64 #define	AUDIOHD_DEV_CONFIG	"onboard1"
65 #define	AUDIOHD_DEV_VERSION	"a"
66 
67 #define	AUDIOHD_FMT_PCM		0x001
68 /*
69  * Only for Intel hardware:
70  * PCI Express traffic class select register in PCI configure space
71  */
72 #define	AUDIOHD_INTEL_PCI_TCSEL 0x44
73 
74 /*
75  * Only for ATI SB450:
76  * MISC control register 2
77  */
78 #define	AUDIOHD_ATI_PCI_MISC2	0x42
79 #define	AUDIOHD_ATI_MISC2_SNOOP	0x02
80 #define	AUDIOHDC_NID(x)		x
81 #define	AUDIOHDC_NULL_NODE	-1
82 #define	AUDIOHD_NULL_CONN	((uint_t)(-1))
83 /*
84  * currently, only the format of 48K sample rate, 16-bit
85  * 2-channel is supported.
86  */
87 #define	AUDIOHD_FMT_PCMOUT	0x0011
88 #define	AUDIOHD_FMT_PCMIN	0x0011
89 
90 #define	AUDIOHD_EXT_AMP_MASK	0x00010000
91 #define	AUDIOHD_EXT_AMP_ENABLE	0x02
92 /* NVIDIA snoop */
93 #define	AUDIOHD_NVIDIA_SNOOP	0x0f
94 
95 /* Power On/Off */
96 #define	AUDIOHD_PW_OFF		1
97 #define	AUDIOHD_PW_ON		0
98 #define	AUDIOHD_PW_D0		0
99 #define	AUDIOHD_PW_D2		2
100 
101 #define	AUDIOHD_INTEL_TCS_MASK	0xf8
102 #define	AUDIOHD_ATI_MISC2_MASK	0xf8
103 
104 /* Pin speaker On/Off */
105 #define	AUDIOHD_SP_ON		1
106 #define	AUDIOHD_SP_OFF		0
107 
108 #define	AUDIOHD_PORT_MAX	15
109 #define	AUDIOHD_CODEC_MAX	16
110 #define	AUDIOHD_MEMIO_LEN	0x4000
111 
112 #define	AUDIOHD_RETRY_TIMES	60
113 #define	AUDIOHD_TEST_TIMES	500
114 #define	AUDIOHD_OUTSTR_NUM_OFF	12
115 #define	AUDIOHD_INSTR_NUM_OFF	8
116 
117 #define	AUDIOHD_CORB_SIZE_OFF	0x4e
118 
119 #define	AUDIOHD_URCAP_MASK	0x80
120 #define	AUDIOHD_DTCCAP_MASK	0x4
121 #define	AUDIOHD_UR_ENABLE_OFF	8
122 #define	AUDIOHD_UR_TAG_MASK	0x1f
123 
124 #define	AUDIOHD_CIS_MASK	0x40000000
125 
126 #define	AUDIOHD_RIRB_UR_MASK	0x10
127 #define	AUDIOHD_RIRB_CODEC_MASK	0xf
128 #define	AUDIOHD_RIRB_WID_OFF	27
129 #define	AUDIOHD_RIRB_INTRCNT	0x0
130 #define	AUDIOHD_RIRB_WPMASK	0xff
131 
132 #define	AUDIOHD_FORM_MASK	0x0080
133 #define	AUDIOHD_LEN_MASK	0x007f
134 #define	AUDIOHD_PIN_CAP_MASK	0x00000010
135 #define	AUDIOHD_PIN_CONF_MASK	0xc0000000
136 #define	AUDIOHD_PIN_CON_MASK	3
137 #define	AUDIOHD_PIN_CON_STEP	30
138 #define	AUDIOHD_PIN_IO_MASK	0X0018
139 #define	AUDIOHD_PIN_SEQ_MASK	0x0000000f
140 #define	AUDIOHD_PIN_ASO_MASK	0x000000f0
141 #define	AUDIOHD_PIN_ASO_OFF	0x4
142 #define	AUDIOHD_PIN_DEV_MASK	0x00f00000
143 #define	AUDIOHD_PIN_DEV_OFF	20
144 #define	AUDIOHD_PIN_NUMS	6
145 #define	AUDIOHD_PIN_NO_CONN	0x40000000
146 #define	AUDIOHD_PIN_IN_ENABLE	0x20
147 #define	AUDIOHD_PIN_OUT_ENABLE	0x40
148 #define	AUDIOHD_PIN_PRES_OFF	0x20
149 #define	AUDIOHD_PIN_CONTP_OFF	0x1e
150 #define	AUDIOHD_PIN_CON_JACK	0
151 #define	AUDIOHD_PIN_CON_FIXED	0x2
152 #define	AUDIOHD_PIN_CONTP_MASK	0x3
153 #define	AUDIOHD_PIN_VREF_L1	0x20
154 #define	AUDIOHD_PIN_VREF_L2	0x10
155 #define	AUDIOHD_PIN_VREF_L3	0x04
156 #define	AUDIOHD_PIN_VREF_L4	0x02
157 #define	AUDIOHD_PIN_VREF_OFF	8
158 #define	AUDIOHD_PIN_VREF_MASK	0xff
159 #define	AUDIOHD_PIN_CLR_MASK	0xf
160 #define	AUDIOHD_PIN_CLR_OFF	12
161 
162 
163 #define	AUDIOHD_VERB_ADDR_OFF	28
164 #define	AUDIOHD_VERB_NID_OFF	20
165 #define	AUDIOHD_VERB_CMD_OFF	8
166 #define	AUDIOHD_VERB_CMD16_OFF	16
167 
168 #define	AUDIOHD_RING_MAX_SIZE	0x00ff
169 #define	AUDIOHD_REC_TAG_OFF	4
170 #define	AUDIOHD_PLAY_TAG_OFF	4
171 #define	AUDIOHD_PLAY_CTL_OFF	2
172 #define	AUDIOHD_REC_CTL_OFF	2
173 
174 #define	AUDIOHD_SPDIF_ON	1
175 #define	AUDIOHD_SPDIF_MASK	0x00ff
176 
177 #define	AUDIOHD_GAIN_OFF	8
178 
179 #define	AUDIOHD_CODEC_STR_OFF	16
180 #define	AUDIOHD_CODEC_STR_MASK	0x000000ff
181 #define	AUDIOHD_CODEC_NUM_MASK	0x000000ff
182 #define	AUDIOHD_CODEC_TYPE_MASK	0x000000ff
183 
184 #define	AUDIOHD_ROUNDUP(x, algn)	(((x) + ((algn) - 1)) & ~((algn) - 1))
185 #define	AUDIOHD_FRAGFR_ALIGN	64
186 #define	AUDIOHD_BDLE_BUF_ALIGN	128
187 #define	AUDIOHD_CMDIO_ENT_MASK	0x00ff	/* 256 entries for CORB/RIRB */
188 #define	AUDIOHD_CDBIO_CORB_LEN	1024	/* 256 entries for CORB, 1024B */
189 #define	AUDIOHD_CDBIO_RIRB_LEN	2048	/* 256 entries for RIRB, 2048B */
190 #define	AUDIOHD_BDLE_NUMS	4	/* 4 entires for record/play BD list */
191 
192 #define	AUDIOHD_PORT_UNMUTE	(0xffffffff)
193 
194 /*
195  * Audio registers of high definition
196  */
197 #define	AUDIOHD_REG_GCAP		0x00
198 #define	AUDIOHDR_GCAP_OUTSTREAMS	0xf000
199 #define	AUDIOHDR_GCAP_INSTREAMS		0x0f00
200 #define	AUDIOHDR_GCAP_BSTREAMS		0x00f8
201 #define	AUDIOHDR_GCAP_NSDO		0x0006
202 #define	AUDIOHDR_GCAP_64OK		0x0001
203 
204 #define	AUDIOHD_REG_VMIN		0x02
205 #define	AUDIOHD_REG_VMAJ		0x03
206 #define	AUDIOHD_REG_OUTPAY		0x04
207 #define	AUDIOHD_REG_INPAY		0x06
208 #define	AUDIOHD_REG_GCTL		0x08
209 #define	AUDIOHD_REG_WAKEEN		0x0C
210 #define	AUDIOHD_REG_STATESTS		0x0E
211 #define	AUDIOHD_STATESTS_BIT_SDINS	0x7F
212 
213 #define	AUDIOHD_REG_GSTS		0x10
214 #define	AUDIOHD_REG_INTCTL		0x20
215 #define	AUDIOHD_INTCTL_BIT_GIE		0x80000000
216 #define	AUDIOHD_INTCTL_BIT_CIE		0x40000000
217 #define	AUDIOHD_INTCTL_BIT_SIE		0x3FFFFFFF
218 
219 
220 #define	AUDIOHD_REG_INTSTS		0x24
221 #define	AUDIOHD_INTSTS_BIT_GIS		0x80000000
222 #define	AUDIOHD_INTSTS_BIT_CIS		0x40000000
223 #define	AUDIOHD_INTSTS_BIT_SINTS	(0x3fffffff)
224 
225 #define	AUDIOHD_REG_WALCLK		0x30
226 #define	AUDIOHD_REG_SYNC		0x38
227 
228 #define	AUDIOHD_REG_CORBLBASE		0x40
229 #define	AUDIOHD_REG_CORBUBASE		0x44
230 #define	AUDIOHD_REG_CORBWP		0x48
231 #define	AUDIOHD_REG_CORBRP		0x4A
232 #define	AUDIOHD_REG_CORBCTL		0x4C
233 #define	AUDIOHD_REG_CORBST		0x4D
234 #define	AUDIOHD_REG_CORBSIZE		0x4E
235 
236 #define	AUDIOHD_REG_RIRBLBASE		0x50
237 #define	AUDIOHD_REG_RIRBUBASE		0x54
238 #define	AUDIOHD_REG_RIRBWP		0x58
239 #define	AUDIOHD_REG_RINTCNT		0x5A
240 #define	AUDIOHD_REG_RIRBCTL		0x5C
241 #define	AUDIOHD_REG_RIRBSTS		0x5D
242 #define	AUDIOHD_REG_RIRBSIZE		0x5E
243 
244 #define	AUDIOHD_REG_IC			0x60
245 #define	AUDIOHD_REG_IR			0x64
246 #define	AUDIOHD_REG_IRS			0x68
247 #define	AUDIOHD_REG_DPLBASE		0x70
248 #define	AUDIOHD_REG_DPUBASE		0x74
249 
250 #define	AUDIOHD_REG_SD_BASE		0x80
251 #define	AUDIOHD_REG_SD_LEN		0x20
252 
253 /*
254  * Offset of Stream Descriptor Registers
255  */
256 #define	AUDIOHD_SDREG_OFFSET_CTL		0x00
257 #define	AUDIOHD_SDREG_OFFSET_STS		0x03
258 #define	AUDIOHD_SDREG_OFFSET_LPIB		0x04
259 #define	AUDIOHD_SDREG_OFFSET_CBL		0x08
260 #define	AUDIOHD_SDREG_OFFSET_LVI		0x0c
261 #define	AUDIOHD_SDREG_OFFSET_FIFOW		0x0e
262 #define	AUDIOHD_SDREG_OFFSET_FIFOSIZE		0x10
263 #define	AUDIOHD_SDREG_OFFSET_FORMAT		0x12
264 #define	AUDIOHD_SDREG_OFFSET_BDLPL		0x18
265 #define	AUDIOHD_SDREG_OFFSET_BDLPU		0x1c
266 
267 /* bits for stream descriptor control reg */
268 #define	AUDIOHDR_SD_CTL_DEIE		0x000010
269 #define	AUDIOHDR_SD_CTL_FEIE		0x000008
270 #define	AUDIOHDR_SD_CTL_IOCE		0x000004
271 #define	AUDIOHDR_SD_CTL_SRUN		0x000002
272 #define	AUDIOHDR_SD_CTL_SRST		0x000001
273 #define	AUDIOHDR_SD_CTL_INTS	\
274 	(AUDIOHDR_SD_CTL_DEIE |	\
275 	AUDIOHDR_SD_CTL_FEIE |	\
276 	AUDIOHDR_SD_CTL_IOCE)
277 
278 
279 /* bits for stream descriptor status register */
280 #define	AUDIOHDR_SD_STS_BCIS		0x0004
281 #define	AUDIOHDR_SD_STS_FIFOE		0x0008
282 #define	AUDIOHDR_SD_STS_DESE		0x0010
283 #define	AUDIOHDR_SD_STS_FIFORY		0x0020
284 #define	AUDIOHDR_SD_STS_INTRS	\
285 	(AUDIOHDR_SD_STS_BCIS | \
286 	AUDIOHDR_SD_STS_FIFOE |	\
287 	AUDIOHDR_SD_STS_DESE)
288 
289 
290 /* bits for GCTL register */
291 #define	AUDIOHDR_GCTL_CRST		0x00000001
292 #define	AUDIOHDR_GCTL_URESPE		0x00000100
293 
294 /* bits for CORBRP register */
295 #define	AUDIOHDR_CORBRP_RESET		0x8000
296 #define	AUDIOHDR_CORBRP_WPTR		0x00ff
297 
298 /* bits for CORBCTL register */
299 #define	AUDIOHDR_CORBCTL_CMEIE		0x01
300 #define	AUDIOHDR_CORBCTL_DMARUN		0x02
301 
302 /* bits for CORB SIZE register */
303 #define	AUDIOHDR_CORBSZ_8		0
304 #define	AUDIOHDR_CORBSZ_16		1
305 #define	AUDIOHDR_CORBSZ_256		2
306 
307 /* bits for RIRBCTL register */
308 #define	AUDIOHDR_RIRBCTL_RINTCTL	0x01
309 #define	AUDIOHDR_RIRBCTL_DMARUN		0x02
310 #define	AUDIOHDR_RIRBCTL_RIRBOIC	0x04
311 #define	AUDIOHDR_RIRBCTL_RSTINT		0xfe
312 
313 /* bits for RIRBWP register */
314 #define	AUDIOHDR_RIRBWP_RESET		0x8000
315 #define	AUDIOHDR_RIRBWP_WPTR		0x00ff
316 
317 /* bits for RIRB SIZE register */
318 #define	AUDIOHDR_RIRBSZ_8		0
319 #define	AUDIOHDR_RIRBSZ_16		1
320 #define	AUDIOHDR_RIRBSZ_256		2
321 
322 #define	AUDIOHD_BDLE_RIRB_SDI		0x0000000f
323 #define	AUDIOHD_BDLE_RIRB_UNSOLICIT	0x00000010
324 
325 /* HD spec: ID of Root node is 0 */
326 #define	AUDIOHDC_NODE_ROOT		0x00
327 
328 /* HD spec: ID of audio function group is "1" */
329 #define	AUDIOHDC_AUDIO_FUNC_GROUP	1
330 
331 /*
332  * HD audio verbs can be either 12-bit or 4-bit in length.
333  */
334 #define	AUDIOHDC_12BIT_VERB_MASK	0xfffff000
335 #define	AUDIOHDC_4BIT_VERB_MASK		0xfffffff0
336 
337 #define	AUDIOHDC_SAMPR48000		48000
338 #define	AUDIOHDC_MAX_BEEP_GEN		12000
339 #define	AUDIOHDC_MIX_BEEP_GEN		47
340 #define	AUDIOHDC_MUTE_BEEP_GEN		0x0
341 
342 /*
343  * 12-bit verbs
344  */
345 #define	AUDIOHDC_VERB_GET_PARAM			0xf00
346 
347 #define	AUDIOHDC_VERB_GET_CONN_SEL		0xf01
348 #define	AUDIOHDC_VERB_SET_CONN_SEL		0x701
349 
350 #define	AUDIOHDC_VERB_GET_CONN_LIST_ENT		0xf02
351 #define	AUDIOHDC_VERB_GET_PROCESS_STATE		0xf03
352 #define	AUDIOHDC_VERB_GET_SDI_SEL		0xf04
353 
354 #define	AUDIOHDC_VERB_GET_POWER_STATE		0xf05
355 #define	AUDIOHDC_VERB_SET_POWER_STATE		0x705
356 
357 #define	AUDIOHDC_VERB_GET_STREAM_CHANN		0xf06
358 #define	AUDIOHDC_VERB_SET_STREAM_CHANN		0x706
359 
360 #define	AUDIOHDC_VERB_GET_PIN_CTRL		0xf07
361 #define	AUDIOHDC_VERB_SET_PIN_CTRL		0x707
362 
363 #define	AUDIOHDC_VERB_GET_UNS_ENABLE		0xf08
364 
365 #define	AUDIOHDC_VERB_GET_PIN_SENSE		0xf09
366 #define	AUDIOHDC_VERB_EXEC_PIN_SENSE		0x709
367 
368 #define	AUDIOHDC_VERB_GET_BEEP_GEN		0xf0a
369 #define	AUDIOHDC_VERB_SET_BEEP_GEN		0x70a
370 
371 #define	AUDIOHDC_VERB_GET_EAPD			0xf0c
372 #define	AUDIOHDC_VERB_SET_EAPD			0x70c
373 
374 #define	AUDIOHDC_VERB_GET_DEFAULT_CONF		0xf1c
375 #define	AUDIOHDC_VERB_GET_SPDIF_CTL		0xf0d
376 #define	AUDIOHDC_VERB_SET_SPDIF_LCL		0x70d
377 
378 #define	AUDIOHDC_VERB_SET_URCTRL		0x708
379 #define	AUDIOHDC_VERB_GET_PIN_SENSE		0xf09
380 
381 #define	AUDIOHDC_VERB_GET_GPIO_MASK		0xf16
382 #define	AUDIOHDC_VERB_SET_GPIO_MASK		0x716
383 
384 #define	AUDIOHDC_VERB_GET_GPIO_DIREC		0xf17
385 #define	AUDIOHDC_VERB_SET_GPIO_DIREC		0x717
386 
387 #define	AUDIOHDC_VERB_GET_GPIO_DATA		0xf15
388 #define	AUDIOHDC_VERB_SET_GPIO_DATA		0x715
389 
390 #define	AUDIOHDC_VERB_GET_GPIO_STCK		0xf1a
391 #define	AUDIOHDC_VERB_SET_GPIO_STCK		0x71a
392 
393 #define	AUDIOHDC_GPIO_ENABLE			0xff
394 #define	AUDIOHDC_GPIO_DIRECT			0xf1
395 
396 #define	AUDIOHDC_GPIO_DATA_CTRL			0xff
397 #define	AUDIOHDC_GPIO_STCK_CTRL			0xff
398 /*
399  * 4-bit verbs
400  */
401 #define	AUDIOHDC_VERB_GET_CONV_FMT		0xa
402 #define	AUDIOHDC_VERB_SET_CONV_FMT		0x2
403 
404 #define	AUDIOHDC_VERB_GET_AMP_MUTE		0xb
405 #define	AUDIOHDC_VERB_SET_AMP_MUTE		0x3
406 #define	AUDIOHDC_VERB_SET_BEEP_VOL		0x3A0
407 
408 /*
409  * parameters of nodes
410  */
411 #define	AUDIOHDC_PAR_VENDOR_ID			0x00
412 #define	AUDIOHDC_PAR_SUBSYS_ID			0x01
413 #define	AUDIOHDC_PAR_REV_ID			0x02
414 #define	AUDIOHDC_PAR_NODE_COUNT			0x04
415 #define	AUDIOHDC_PAR_FUNCTION_TYPE		0x05
416 #define	AUDIOHDC_PAR_AUDIO_FG_CAP		0x08
417 #define	AUDIOHDC_PAR_AUDIO_WID_CAP		0x09
418 #define	AUDIOHDC_PAR_PCM			0x0a
419 #define	AUDIOHDC_PAR_STREAM			0x0b
420 #define	AUDIOHDC_PAR_PIN_CAP			0x0c
421 #define	AUDIOHDC_PAR_INAMP_CAP			0x0d
422 #define	AUDIOHDC_PAR_CONNLIST_LEN		0x0e
423 #define	AUDIOHDC_PAR_POWER_STATE		0x0f
424 #define	AUDIOHDC_PAR_PROC_CAP			0x10
425 #define	AUDIOHDC_PAR_GPIO_CAP			0x11
426 #define	AUDIOHDC_PAR_OUTAMP_CAP			0x12
427 
428 /*
429  * bits for get/set amplifier gain/mute
430  */
431 #define	AUDIOHDC_AMP_SET_OUTPUT			0x8000
432 #define	AUDIOHDC_AMP_SET_INPUT			0x4000
433 #define	AUDIOHDC_AMP_SET_LEFT			0x2000
434 #define	AUDIOHDC_AMP_SET_RIGHT			0x1000
435 #define	AUDIOHDC_AMP_SET_MUTE			0x0080
436 #define	AUDIOHDC_AMP_SET_LNR			0x3000
437 #define	AUDIOHDC_AMP_SET_LR_INPUT		0x7000
438 #define	AUDIOHDC_AMP_SET_LR_OUTPUT		0xb000
439 #define	AUDIOHDC_AMP_SET_INDEX_OFFSET		8
440 #define	AUDIOHDC_AMP_SET_GAIN_MASK		0x007f
441 #define	AUDIOHDC_GAIN_MAX			0x7f
442 #define	AUDIOHDC_GAIN_BITS			7
443 #define	AUDIOHDC_GAIN_DEFAULT			0x0f
444 
445 #define	AUDIOHDC_AMP_GET_OUTPUT			0x8000
446 #define	AUDIOHDC_AMP_GET_INPUT			0x0000
447 
448 /* value used to set max volume for left output */
449 #define	AUDIOHDC_AMP_LOUT_MAX	\
450 	(AUDIOHDC_AMP_SET_OUTPUT | \
451 	AUDIOHDC_AMP_SET_LEFT | \
452 	AUDIOHDC_GAIN_MAX)
453 
454 /* value used to set max volume for right output */
455 #define	AUDIOHDC_AMP_ROUT_MAX	\
456 	(AUDIOHDC_AMP_SET_OUTPUT | \
457 	AUDIOHDC_AMP_SET_RIGHT | \
458 	AUDIOHDC_GAIN_MAX)
459 
460 
461 /*
462  * Bits for pin widget control verb
463  */
464 #define	AUDIOHDC_PIN_CONTROL_HP_ENABLE		0x80
465 #define	AUDIOHDC_PIN_CONTROL_OUT_ENABLE		0x40
466 #define	AUDIOHDC_PIN_CONTROL_IN_ENABLE		0x20
467 
468 /*
469  * Bits for Amplifier capabilities
470  */
471 #define	AUDIOHDC_AMP_CAP_MUTE_CAP		0x80000000
472 #define	AUDIOHDC_AMP_CAP_STEP_SIZE		0x007f0000
473 #define	AUDIOHDC_AMP_CAP_STEP_NUMS		0x00007f00
474 #define	AUDIOHDC_AMP_CAP_0DB_OFFSET		0x0000007f
475 
476 
477 /*
478  * Bits for Audio Widget Capabilities
479  */
480 #define	AUDIOHD_WIDCAP_STEREO		0x00000001
481 #define	AUDIOHD_WIDCAP_INAMP		0x00000002
482 #define	AUDIOHD_WIDCAP_OUTAMP		0x00000004
483 #define	AUDIOHD_WIDCAP_AMP_OVRIDE	0x00000008
484 #define	AUDIOHD_WIDCAP_FMT_OVRIDE	0x00000010
485 #define	AUDIOHD_WIDCAP_STRIP		0x00000020
486 #define	AUDIOHD_WIDCAP_PROC_WID		0x00000040
487 #define	AUDIOHD_WIDCAP_UNSOL		0x00000080
488 #define	AUDIOHD_WIDCAP_CONNLIST		0x00000100
489 #define	AUDIOHD_WIDCAP_DIGIT		0x00000200
490 #define	AUDIOHD_WIDCAP_PWRCTRL		0x00000400
491 #define	AUDIOHD_WIDCAP_LRSWAP		0x00000800
492 #define	AUDIOHD_WIDCAP_TYPE		0x00f00000
493 #define	AUDIOHD_WIDCAP_TO_WIDTYPE(wcap)		\
494 	((wcap & AUDIOHD_WIDCAP_TYPE) >> 20)
495 
496 
497 #define	AUDIOHD_CODEC_FAILURE	(uint32_t)(-1)
498 
499 /*
500  * buffer descriptor list entry of stream descriptor
501  */
502 typedef struct {
503 	uint64_t	sbde_addr;
504 	uint32_t	sbde_len;
505 	uint32_t
506 		sbde_ioc: 1,
507 		reserved: 31;
508 }sd_bdle_t;
509 
510 
511 #define	AUDIOHD_PLAY_STARTED		0x00000001
512 #define	AUDIOHD_PLAY_EMPTY		0x00000002
513 #define	AUDIOHD_PLAY_PAUSED		0x00000004
514 #define	AUDIOHD_RECORD_STARTED		0x00000008
515 
516 enum audiohda_widget_type {
517 	WTYPE_AUDIO_OUT = 0,
518 	WTYPE_AUDIO_IN,
519 	WTYPE_AUDIO_MIX,
520 	WTYPE_AUDIO_SEL,
521 	WTYPE_PIN,
522 	WTYPE_POWER,
523 	WTYPE_VOL_KNOB,
524 	WTYPE_BEEP,
525 	WTYPE_VENDOR = 0xf
526 };
527 
528 enum audiohda_device_type {
529 	DTYPE_LINEOUT = 0,
530 	DTYPE_SPEAKER,
531 	DTYPE_HP_OUT,
532 	DTYPE_CD,
533 	DTYPE_SPDIF_OUT,
534 	DTYPE_DIGIT_OUT,
535 	DTYPE_MODEM_SIDE,
536 	DTYPE_MODEM_HNAD_SIDE,
537 	DTYPE_LINE_IN,
538 	DTYPE_AUX,
539 	DTYPE_MIC_IN,
540 	DTYPE_TEL,
541 	DTYPE_SPDIF_IN,
542 	DTYPE_DIGIT_IN,
543 	DTYPE_OTHER = 0x0f,
544 };
545 
546 enum audiohd_pin_color {
547 	AUDIOHD_PIN_UNKNOWN = 0,
548 	AUDIOHD_PIN_BLACK,
549 	AUDIOHD_PIN_GREY,
550 	AUDIOHD_PIN_BLUE,
551 	AUDIOHD_PIN_GREEN,
552 	AUDIOHD_PIN_RED,
553 	AUDIOHD_PIN_ORANGE,
554 	AUDIOHD_PIN_YELLOW,
555 	AUDIOHD_PIN_PURPLE,
556 	AUDIOHD_PIN_PINK,
557 	AUDIOHD_PIN_WHITE = 0xe,
558 	AUDIOHD_PIN_OTHER = 0xf,
559 };
560 
561 #define	CTRL_NUM	16
562 
563 /* values for audiohd_widget.path_flags */
564 #define	AUDIOHD_PATH_DAC	(1 << 0)
565 #define	AUDIOHD_PATH_ADC	(1 << 1)
566 #define	AUDIOHD_PATH_MON	(1 << 2)
567 #define	AUDIOHD_PATH_NOMON	(1 << 3)
568 #define	AUDIOHD_PATH_BEEP	(1 << 4)
569 
570 typedef struct audiohd_path		audiohd_path_t;
571 typedef struct audiohd_widget	audiohd_widget_t;
572 typedef struct audiohd_state	audiohd_state_t;
573 typedef struct audiohd_pin	audiohd_pin_t;
574 typedef struct hda_codec	hda_codec_t;
575 typedef uint32_t	wid_t;		/* id of widget */
576 typedef	struct audiohd_entry_prop	audiohd_entry_prop_t;
577 typedef	enum audiohda_device_type	audiohda_device_type_t;
578 typedef	enum audiohd_pin_color		audiohd_pin_color_t;
579 
580 #define	AUDIOHD_MAX_WIDGET		128
581 #define	AUDIOHD_MAX_CONN		16
582 #define	AUDIOHD_MAX_PINS		16
583 #define	AUDIOHD_MAX_DEPTH		8
584 
585 struct audiohd_entry_prop {
586 	uint32_t	conn_len;
587 	uint32_t	mask_range;
588 	uint32_t	mask_wid;
589 	wid_t		input_wid;
590 	int		conns_per_entry;
591 	int		bits_per_conn;
592 };
593 struct audiohd_widget {
594 	wid_t		wid_wid;
595 	hda_codec_t	*codec;
596 	enum audiohda_widget_type type;
597 
598 	uint32_t	widget_cap;
599 	uint32_t	pcm_format;
600 	uint32_t	inamp_cap;
601 	uint32_t	outamp_cap;
602 
603 	uint32_t	path_flags;
604 
605 	int		out_weight;
606 	int		in_weight;
607 	int		finish;
608 
609 	/*
610 	 * wid of possible & selected input connections
611 	 */
612 	wid_t		avail_conn[AUDIOHD_MAX_CONN];
613 	wid_t		selconn;
614 	/*
615 	 * for monitor path
616 	 */
617 	wid_t		selmon[AUDIOHD_MAX_CONN];
618 	uint16_t 	used;
619 
620 	/*
621 	 * available (input) connections. 0 means this widget
622 	 * has fixed connection
623 	 */
624 	int		nconns;
625 
626 	/*
627 	 * pointer to struct depending on widget type:
628 	 *	1. DAC	audiohd_ostream_t
629 	 *	2. ADC	audiohd_istream_t
630 	 *	3. PIN	audiohd_pin_t
631 	 */
632 	void	*priv;
633 };
634 
635 #define	AUDIOHD_FLAG_LINEOUT		(1 << 0)
636 #define	AUDIOHD_FLAG_SPEAKER		(1 << 1)
637 #define	AUDIOHD_FLAG_HP			(1 << 2)
638 #define	AUDIOHD_FLAG_MONO		(1 << 3)
639 
640 #define	AUDIOHD_MAX_MIXER		5
641 #define	AUDIOHD_MAX_PIN			4
642 
643 #define	PORT_DAC		0
644 #define	PORT_ADC		1
645 #define	PORT_MAX		2
646 typedef enum {
647 	PLAY = 0,
648 	RECORD = 1,
649 	BEEP = 2,
650 } path_type_t;
651 
652 struct audiohd_path {
653 	wid_t			adda_wid;
654 	wid_t			beep_wid;
655 
656 	wid_t			pin_wid[AUDIOHD_MAX_PINS];
657 	int			sum_selconn[AUDIOHD_MAX_PINS];
658 	int			mon_wid[AUDIOHD_MAX_PIN][AUDIOHD_MAX_MIXER];
659 	int			pin_nums;
660 	int			maxmixer[AUDIOHD_MAX_PINS];
661 
662 	path_type_t		path_type;
663 
664 	wid_t			mute_wid;
665 	int			mute_dir;
666 	wid_t			gain_wid;
667 	int			gain_dir;
668 	uint32_t		gain_bits;
669 
670 	uint32_t		pin_outputs;
671 	uint8_t			tag;
672 
673 	hda_codec_t		*codec;
674 
675 	wid_t			sum_wid;
676 
677 	audiohd_state_t		*statep;
678 };
679 
680 typedef struct audiohd_port
681 {
682 	uint8_t			nchan;
683 	int			index;
684 	uint16_t		regoff;
685 	boolean_t		started;
686 	boolean_t		triggered;
687 
688 	unsigned		fragfr;
689 	unsigned		nframes;
690 	uint64_t		count;
691 	int			curpos;
692 	int			intrs;
693 
694 	uint_t			format;
695 	unsigned		sync_dir;
696 
697 	ddi_dma_handle_t	samp_dmah;
698 	ddi_acc_handle_t	samp_acch;
699 	size_t			samp_size;
700 	caddr_t			samp_kaddr;
701 	uint64_t		samp_paddr;
702 
703 	ddi_dma_handle_t	bdl_dmah;
704 	ddi_acc_handle_t	bdl_acch;
705 	size_t			bdl_size;
706 	caddr_t			bdl_kaddr;
707 	uint64_t		bdl_paddr;
708 
709 	audio_engine_t		*engine;
710 	audiohd_state_t		*statep;
711 }audiohd_port_t;
712 
713 typedef struct audiohd_ctrl
714 {
715 	audiohd_state_t		*statep;
716 	audio_ctrl_t		*ctrl;
717 	uint32_t		num;
718 	uint64_t		val;
719 } audiohd_ctrl_t;
720 
721 struct audiohd_pin {
722 	audiohd_pin_t	*next;
723 	wid_t		wid;
724 	wid_t		mute_wid;	/* node used to mute this pin */
725 	int		mute_dir;	/* 1: input, 2: output */
726 	wid_t		gain_wid;	/* node for gain control */
727 	int		gain_dir;	/* _OUTPUT/_INPUT */
728 	uint32_t	gain_bits;
729 
730 	uint8_t		vrefvalue;	/* value of VRef */
731 
732 	uint32_t	cap;
733 	uint32_t	config;
734 	uint32_t	ctrl;
735 	uint32_t	assoc;
736 	uint32_t	seq;
737 	wid_t		adc_dac_wid; /* AD/DA wid which can route to this pin */
738 	wid_t		beep_wid;
739 	int		no_phys_conn;
740 	enum audiohda_device_type	device;
741 
742 	/*
743 	 * mg_dir, mg_gain, mg_wid are used to store the monitor gain control
744 	 * widget wid.
745 	 */
746 	int		mg_dir[AUDIOHD_MAX_CONN];
747 	int		mg_gain[AUDIOHD_MAX_CONN];
748 	int		mg_wid[AUDIOHD_MAX_CONN];
749 	int		num;
750 	int		finish;
751 
752 };
753 
754 typedef struct {
755 	ddi_dma_handle_t	ad_dmahdl;
756 	ddi_acc_handle_t	ad_acchdl;
757 	caddr_t			ad_vaddr;	/* virtual addr */
758 	uint64_t		ad_paddr;	/* physical addr */
759 	size_t			ad_req_sz;	/* required size of memory */
760 	size_t			ad_real_sz;	/* real size of memory */
761 } audiohd_dma_t;
762 
763 struct hda_codec {
764 	uint8_t		index;		/* codec address */
765 	uint32_t	vid;		/* vendor id and device id */
766 	uint32_t	revid;		/* revision id */
767 	wid_t		wid_afg;	/* id of AFG */
768 	wid_t		first_wid;	/* wid of 1st subnode of AFG */
769 	wid_t		last_wid;	/* wid of the last subnode of AFG */
770 	int		nnodes;		/* # of subnodes of AFG */
771 	uint8_t		nistream;
772 
773 	uint32_t	outamp_cap;
774 	uint32_t	inamp_cap;
775 	uint32_t	stream_format;
776 	uint32_t	pcm_format;
777 
778 	audiohd_state_t		*soft_statep;
779 
780 	/* use wid as index to the array of widget pointers */
781 	audiohd_widget_t	*widget[AUDIOHD_MAX_WIDGET];
782 
783 
784 	audiohd_port_t		*port[AUDIOHD_PORT_MAX];
785 	uint8_t			portnum;
786 	audiohd_pin_t		*first_pin;
787 };
788 
789 #define	AUDIOHD_MAX_ASSOC	15
790 struct audiohd_state {
791 	dev_info_t	*hda_dip;
792 	kstat_t		*hda_ksp;
793 	kmutex_t	hda_mutex;
794 	uint32_t	hda_flags;
795 
796 	boolean_t	soft_volume;
797 	boolean_t	intr_added;
798 
799 	caddr_t				hda_reg_base;
800 	ddi_acc_handle_t		hda_pci_handle;
801 	ddi_acc_handle_t		hda_reg_handle;
802 
803 	ddi_intr_handle_t 	*htable; 	/* For array of interrupts */
804 	int			intr_type;	/* What type of interrupt */
805 	int			intr_rqst;	/* # of request intrs count */
806 	int			intr_cnt;	/* # of intrs count returned */
807 	uint_t			intr_pri;	/* Interrupt priority */
808 	int			intr_cap;	/* Interrupt capabilities */
809 	boolean_t		msi_enable;
810 
811 	audiohd_dma_t	hda_dma_corb;
812 	audiohd_dma_t	hda_dma_rirb;
813 
814 
815 	uint8_t		hda_rirb_rp;		/* read pointer for rirb */
816 	uint16_t	hda_codec_mask;
817 
818 
819 	audio_dev_t	*adev;
820 	uint32_t	devid;
821 
822 
823 	int		hda_pint_freq;	/* play intr frequence */
824 	int		hda_rint_freq;	/* record intr frequence */
825 
826 	int		hda_input_streams;	/* # of input stream */
827 	int		hda_output_streams;	/* # of output stream */
828 	int		hda_streams_nums;	/* # of stream */
829 
830 	uint_t		hda_play_regbase;
831 	uint_t		hda_record_regbase;
832 
833 	uint_t		hda_play_stag;		/* tag of playback stream */
834 	uint_t		hda_record_stag;	/* tag of record stream */
835 	uint_t		hda_play_lgain;		/* left gain for playback */
836 	uint_t		hda_play_rgain;		/* right gain for playback */
837 
838 	/*
839 	 * Now, for the time being, we add some fields
840 	 * for parsing codec topology
841 	 */
842 	hda_codec_t	*codec[AUDIOHD_CODEC_MAX];
843 	/*
844 	 * Suspend/Resume used fields
845 	 */
846 	boolean_t	suspended;
847 	boolean_t	monitor_unsupported;
848 
849 	audiohd_path_t	*path[AUDIOHD_PORT_MAX];
850 	uint8_t		pathnum;
851 	audiohd_port_t	*port[PORT_MAX];
852 	uint8_t		pchan;
853 	uint8_t		rchan;
854 
855 	uint64_t	inmask;
856 
857 	uint_t		hda_out_ports;
858 	uint_t		in_port;
859 
860 	/*
861 	 * Controls
862 	 */
863 	audiohd_ctrl_t		*controls[CTRL_NUM];
864 
865 	/* for multichannel */
866 	uint8_t			chann[AUDIOHD_MAX_ASSOC];
867 	uint8_t			assoc;
868 
869 };
870 
871 
872 /*
873  * Operation for high definition audio control system bus
874  * interface registers
875  */
876 #define	AUDIOHD_REG_GET8(reg)	\
877 	ddi_get8(statep->hda_reg_handle, \
878 	(void *)((char *)statep->hda_reg_base + (reg)))
879 
880 #define	AUDIOHD_REG_GET16(reg)	\
881 	ddi_get16(statep->hda_reg_handle, \
882 	(void *)((char *)statep->hda_reg_base + (reg)))
883 
884 #define	AUDIOHD_REG_GET32(reg)	\
885 	ddi_get32(statep->hda_reg_handle, \
886 	(void *)((char *)statep->hda_reg_base + (reg)))
887 
888 #define	AUDIOHD_REG_GET64(reg)	\
889 	ddi_get64(statep->hda_reg_handle, \
890 	(void *)((char *)statep->hda_reg_base + (reg)))
891 
892 #define	AUDIOHD_REG_SET8(reg, val)	\
893 	ddi_put8(statep->hda_reg_handle, \
894 	(void *)((char *)statep->hda_reg_base + (reg)), (val))
895 
896 #define	AUDIOHD_REG_SET16(reg, val)	\
897 	ddi_put16(statep->hda_reg_handle, \
898 	(void *)((char *)statep->hda_reg_base + (reg)), (val))
899 
900 #define	AUDIOHD_REG_SET32(reg, val)	\
901 	ddi_put32(statep->hda_reg_handle, \
902 	(void *)((char *)statep->hda_reg_base + (reg)), (val))
903 
904 #define	AUDIOHD_REG_SET64(reg, val)	\
905 	ddi_put64(statep->hda_reg_handle, \
906 	(void *)((char *)statep->hda_reg_base + (reg)), (val))
907 
908 
909 /*
910  * enable a pin widget to output
911  */
912 #define	AUDIOHD_ENABLE_PIN_OUT(statep, caddr, wid) \
913 { \
914 	uint32_t	lTmp; \
915 \
916 	lTmp = audioha_codec_verb_get(statep, caddr, wid, \
917 	    AUDIOHDC_VERB_GET_PIN_CTRL, 0); \
918 	if (lTmp == AUDIOHD_CODEC_FAILURE) \
919 		return (DDI_FAILURE); \
920 	lTmp = audioha_codec_verb_get(statep, caddr, wid, \
921 	    AUDIOHDC_VERB_SET_PIN_CTRL, \
922 	    (lTmp | AUDIOHDC_PIN_CONTROL_OUT_ENABLE | \
923 	    AUDIOHDC_PIN_CONTROL_HP_ENABLE)); \
924 	if (lTmp == AUDIOHD_CODEC_FAILURE) \
925 		return (DDI_FAILURE); \
926 }
927 
928 /*
929  * disable output pin
930  */
931 #define	AUDIOHD_DISABLE_PIN_OUT(statep, caddr, wid) \
932 { \
933 	uint32_t	lTmp; \
934 \
935 	lTmp = audioha_codec_verb_get(statep, caddr, wid, \
936 	    AUDIOHDC_VERB_GET_PIN_CTRL, 0); \
937 	if (lTmp == AUDIOHD_CODEC_FAILURE) \
938 		return (DDI_FAILURE); \
939 	lTmp = audioha_codec_verb_get(statep, caddr, wid, \
940 	    AUDIOHDC_VERB_SET_PIN_CTRL, \
941 	    (lTmp & ~AUDIOHDC_PIN_CONTROL_OUT_ENABLE)); \
942 	if (lTmp == AUDIOHD_CODEC_FAILURE) \
943 		return (DDI_FAILURE); \
944 }
945 
946 /*
947  * enable a pin widget to input
948  */
949 #define	AUDIOHD_ENABLE_PIN_IN(statep, caddr, wid) \
950 { \
951 	(void) audioha_codec_verb_get(statep, caddr, wid, \
952 	    AUDIOHDC_VERB_SET_PIN_CTRL, AUDIOHDC_PIN_CONTROL_IN_ENABLE | 4); \
953 }
954 
955 
956 /*
957  * disable input pin
958  */
959 #define	AUDIOHD_DISABLE_PIN_IN(statep, caddr, wid) \
960 { \
961 	uint32_t	lTmp; \
962 \
963 	lTmp = audioha_codec_verb_get(statep, caddr, wid, \
964 	    AUDIOHDC_VERB_GET_PIN_CTRL, 0); \
965 	if (lTmp == AUDIOHD_CODEC_FAILURE) \
966 		return (DDI_FAILURE); \
967 	lTmp = audioha_codec_verb_get(statep, caddr, wid, \
968 	    AUDIOHDC_VERB_SET_PIN_CTRL, \
969 	    (lTmp & ~AUDIOHDC_PIN_CONTROL_IN_ENABLE)); \
970 	if (lTmp == AUDIOHD_CODEC_FAILURE) \
971 		return (DDI_FAILURE); \
972 }
973 
974 /*
975  * unmute an output pin
976  */
977 #define	AUDIOHD_NODE_UNMUTE_OUT(statep, caddr, wid) \
978 { \
979 	if (audioha_codec_4bit_verb_get(statep, \
980 	    caddr, wid, AUDIOHDC_VERB_SET_AMP_MUTE, \
981 	    AUDIOHDC_AMP_SET_LR_OUTPUT | AUDIOHDC_GAIN_MAX) == \
982 	    AUDIOHD_CODEC_FAILURE) \
983 		return (DDI_FAILURE); \
984 }
985 
986 #ifdef __cplusplus
987 }
988 #endif
989 
990 #endif	/* _SYS_AUDIOHD_IMPL_H_ */
991