1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 #ifndef _SYS_AUDIOHD_IMPL_H_ 26 #define _SYS_AUDIOHD_IMPL_H_ 27 28 #ifdef __cplusplus 29 extern "C" { 30 #endif 31 32 /* 33 * vendor IDs of PCI audio controllers 34 */ 35 #define AUDIOHD_VID_INTEL 0x8086 36 #define AUDIOHD_VID_ATI 0x1002 37 #define AUDIOHD_VID_NVIDIA 0x10de 38 39 /* 40 * specific codec id used by specific vendors 41 */ 42 #define AUDIOHD_CODECID_HP 0x111d7608 43 #define AUDIOHD_CODECID_SONY1 0x10ec0260 44 #define AUDIOHD_CODECID_SONY2 0x10ec0262 45 46 #define AUDIO_SUCCESS (0) 47 #define AUDIO_FAILURE (-1) 48 49 #define AUDIOHD_INTS 50 50 #define AUDIOHD_MAX_INTS 1500 51 #define AUDIOHD_MIN_INTS 32 52 53 #define AUDIOHD_DEV_CONFIG "onboard1" 54 #define AUDIOHD_DEV_VERSION "a" 55 56 #define AUDIOHD_FMT_PCM 0x001 57 /* 58 * Only for Intel hardware: 59 * PCI Express traffic class select register in PCI configure space 60 */ 61 #define AUDIOHD_INTEL_PCI_TCSEL 0x44 62 63 /* 64 * Only for ATI SB450: 65 * MISC control register 2 66 */ 67 #define AUDIOHD_ATI_PCI_MISC2 0x42 68 #define AUDIOHD_ATI_MISC2_SNOOP 0x02 69 #define AUDIOHDC_NID(x) x 70 #define AUDIOHDC_NULL_NODE -1 71 #define AUDIOHD_NULL_CONN ((uint_t)(-1)) 72 /* 73 * currently, only the format of 48K sample rate, 16-bit 74 * 2-channel is supported. 75 */ 76 #define AUDIOHD_FMT_PCMOUT 0x0011 77 #define AUDIOHD_FMT_PCMIN 0x0011 78 79 #define AUDIOHD_EXT_AMP_MASK 0x00010000 80 #define AUDIOHD_EXT_AMP_ENABLE 0x02 81 /* NVIDIA snoop */ 82 #define AUDIOHD_NVIDIA_SNOOP 0x0f 83 84 /* Power On/Off */ 85 #define AUDIOHD_PW_OFF 1 86 #define AUDIOHD_PW_ON 0 87 #define AUDIOHD_PW_D0 0 88 #define AUDIOHD_PW_D2 2 89 90 #define AUDIOHD_INTEL_TCS_MASK 0xf8 91 #define AUDIOHD_ATI_MISC2_MASK 0xf8 92 93 /* Pin speaker On/Off */ 94 #define AUDIOHD_SP_ON 1 95 #define AUDIOHD_SP_OFF 0 96 97 #define AUDIOHD_PORT_MAX 15 98 #define AUDIOHD_CODEC_MAX 16 99 #define AUDIOHD_MEMIO_LEN 0x4000 100 101 #define AUDIOHD_RETRY_TIMES 60 102 #define AUDIOHD_TEST_TIMES 500 103 #define AUDIOHD_OUTSTR_NUM_OFF 12 104 #define AUDIOHD_INSTR_NUM_OFF 8 105 106 #define AUDIOHD_CORB_SIZE_OFF 0x4e 107 108 #define AUDIOHD_URCAP_MASK 0x80 109 #define AUDIOHD_DTCCAP_MASK 0x4 110 #define AUDIOHD_UR_ENABLE_OFF 8 111 #define AUDIOHD_UR_TAG_MASK 0x1f 112 113 #define AUDIOHD_CIS_MASK 0x40000000 114 115 #define AUDIOHD_RIRB_UR_MASK 0x10 116 #define AUDIOHD_RIRB_CODEC_MASK 0xf 117 #define AUDIOHD_RIRB_WID_OFF 27 118 #define AUDIOHD_RIRB_INTRCNT 0x0 119 #define AUDIOHD_RIRB_WPMASK 0xff 120 121 #define AUDIOHD_FORM_MASK 0x0080 122 #define AUDIOHD_LEN_MASK 0x007f 123 #define AUDIOHD_PIN_CAP_MASK 0x00000010 124 #define AUDIOHD_PIN_CONF_MASK 0xc0000000 125 #define AUDIOHD_PIN_CON_MASK 3 126 #define AUDIOHD_PIN_CON_STEP 30 127 #define AUDIOHD_PIN_IO_MASK 0X0018 128 #define AUDIOHD_PIN_SEQ_MASK 0x0000000f 129 #define AUDIOHD_PIN_ASO_MASK 0x000000f0 130 #define AUDIOHD_PIN_ASO_OFF 0x4 131 #define AUDIOHD_PIN_DEV_MASK 0x00f00000 132 #define AUDIOHD_PIN_DEV_OFF 20 133 #define AUDIOHD_PIN_NUMS 6 134 #define AUDIOHD_PIN_NO_CONN 0x40000000 135 #define AUDIOHD_PIN_IN_ENABLE 0x20 136 #define AUDIOHD_PIN_OUT_ENABLE 0x40 137 #define AUDIOHD_PIN_PRES_OFF 0x20 138 #define AUDIOHD_PIN_CONTP_OFF 0x1e 139 #define AUDIOHD_PIN_CON_JACK 0 140 #define AUDIOHD_PIN_CON_FIXED 0x2 141 #define AUDIOHD_PIN_CONTP_MASK 0x3 142 #define AUDIOHD_PIN_VREF_L1 0x20 143 #define AUDIOHD_PIN_VREF_L2 0x10 144 #define AUDIOHD_PIN_VREF_L3 0x04 145 #define AUDIOHD_PIN_VREF_L4 0x02 146 #define AUDIOHD_PIN_VREF_OFF 8 147 #define AUDIOHD_PIN_VREF_MASK 0xff 148 #define AUDIOHD_PIN_CLR_MASK 0xf 149 #define AUDIOHD_PIN_CLR_OFF 12 150 151 152 #define AUDIOHD_VERB_ADDR_OFF 28 153 #define AUDIOHD_VERB_NID_OFF 20 154 #define AUDIOHD_VERB_CMD_OFF 8 155 #define AUDIOHD_VERB_CMD16_OFF 16 156 157 #define AUDIOHD_RING_MAX_SIZE 0x00ff 158 #define AUDIOHD_POS_MASK ~0x00000003 159 #define AUDIOHD_REC_TAG_OFF 4 160 #define AUDIOHD_PLAY_TAG_OFF 4 161 #define AUDIOHD_PLAY_CTL_OFF 2 162 #define AUDIOHD_REC_CTL_OFF 2 163 164 #define AUDIOHD_SPDIF_ON 1 165 #define AUDIOHD_SPDIF_MASK 0x00ff 166 167 #define AUDIOHD_GAIN_OFF 8 168 169 #define AUDIOHD_CODEC_STR_OFF 16 170 #define AUDIOHD_CODEC_STR_MASK 0x000000ff 171 #define AUDIOHD_CODEC_NUM_MASK 0x000000ff 172 #define AUDIOHD_CODEC_TYPE_MASK 0x000000ff 173 174 #define AUDIOHD_FRAGFR_ALIGN 16 175 #define AUDIOHD_BDLE_BUF_ALIGN 128 176 #define AUDIOHD_CMDIO_ENT_MASK 0x00ff /* 256 entries for CORB/RIRB */ 177 #define AUDIOHD_CDBIO_CORB_LEN 1024 /* 256 entries for CORB, 1024B */ 178 #define AUDIOHD_CDBIO_RIRB_LEN 2048 /* 256 entries for RIRB, 2048B */ 179 #define AUDIOHD_BDLE_NUMS 4 /* 4 entires for record/play BD list */ 180 181 #define AUDIOHD_PORT_UNMUTE (0xffffffff) 182 183 /* 184 * Audio registers of high definition 185 */ 186 #define AUDIOHD_REG_GCAP 0x00 187 #define AUDIOHDR_GCAP_OUTSTREAMS 0xf000 188 #define AUDIOHDR_GCAP_INSTREAMS 0x0f00 189 #define AUDIOHDR_GCAP_BSTREAMS 0x00f8 190 #define AUDIOHDR_GCAP_NSDO 0x0006 191 #define AUDIOHDR_GCAP_64OK 0x0001 192 193 #define AUDIOHD_REG_VMIN 0x02 194 #define AUDIOHD_REG_VMAJ 0x03 195 #define AUDIOHD_REG_OUTPAY 0x04 196 #define AUDIOHD_REG_INPAY 0x06 197 #define AUDIOHD_REG_GCTL 0x08 198 #define AUDIOHD_REG_WAKEEN 0x0C 199 #define AUDIOHD_REG_STATESTS 0x0E 200 #define AUDIOHD_STATESTS_BIT_SDINS 0x7F 201 202 #define AUDIOHD_REG_GSTS 0x10 203 #define AUDIOHD_REG_INTCTL 0x20 204 #define AUDIOHD_INTCTL_BIT_GIE 0x80000000 205 #define AUDIOHD_INTCTL_BIT_CIE 0x40000000 206 #define AUDIOHD_INTCTL_BIT_SIE 0x3FFFFFFF 207 208 209 #define AUDIOHD_REG_INTSTS 0x24 210 #define AUDIOHD_INTSTS_BIT_GIS 0x80000000 211 #define AUDIOHD_INTSTS_BIT_CIS 0x40000000 212 #define AUDIOHD_INTSTS_BIT_SINTS (0x3fffffff) 213 214 #define AUDIOHD_REG_WALCLK 0x30 215 #define AUDIOHD_REG_SYNC 0x38 216 217 #define AUDIOHD_REG_CORBLBASE 0x40 218 #define AUDIOHD_REG_CORBUBASE 0x44 219 #define AUDIOHD_REG_CORBWP 0x48 220 #define AUDIOHD_REG_CORBRP 0x4A 221 #define AUDIOHD_REG_CORBCTL 0x4C 222 #define AUDIOHD_REG_CORBST 0x4D 223 #define AUDIOHD_REG_CORBSIZE 0x4E 224 225 #define AUDIOHD_REG_RIRBLBASE 0x50 226 #define AUDIOHD_REG_RIRBUBASE 0x54 227 #define AUDIOHD_REG_RIRBWP 0x58 228 #define AUDIOHD_REG_RINTCNT 0x5A 229 #define AUDIOHD_REG_RIRBCTL 0x5C 230 #define AUDIOHD_REG_RIRBSTS 0x5D 231 #define AUDIOHD_REG_RIRBSIZE 0x5E 232 233 #define AUDIOHD_REG_IC 0x60 234 #define AUDIOHD_REG_IR 0x64 235 #define AUDIOHD_REG_IRS 0x68 236 #define AUDIOHD_REG_DPLBASE 0x70 237 #define AUDIOHD_REG_DPUBASE 0x74 238 239 #define AUDIOHD_REG_SD_BASE 0x80 240 #define AUDIOHD_REG_SD_LEN 0x20 241 242 /* 243 * Offset of Stream Descriptor Registers 244 */ 245 #define AUDIOHD_SDREG_OFFSET_CTL 0x00 246 #define AUDIOHD_SDREG_OFFSET_STS 0x03 247 #define AUDIOHD_SDREG_OFFSET_LPIB 0x04 248 #define AUDIOHD_SDREG_OFFSET_CBL 0x08 249 #define AUDIOHD_SDREG_OFFSET_LVI 0x0c 250 #define AUDIOHD_SDREG_OFFSET_FIFOW 0x0e 251 #define AUDIOHD_SDREG_OFFSET_FIFOSIZE 0x10 252 #define AUDIOHD_SDREG_OFFSET_FORMAT 0x12 253 #define AUDIOHD_SDREG_OFFSET_BDLPL 0x18 254 #define AUDIOHD_SDREG_OFFSET_BDLPU 0x1c 255 256 /* bits for stream descriptor control reg */ 257 #define AUDIOHDR_SD_CTL_DEIE 0x000010 258 #define AUDIOHDR_SD_CTL_FEIE 0x000008 259 #define AUDIOHDR_SD_CTL_IOCE 0x000004 260 #define AUDIOHDR_SD_CTL_SRUN 0x000002 261 #define AUDIOHDR_SD_CTL_SRST 0x000001 262 #define AUDIOHDR_SD_CTL_INTS \ 263 (AUDIOHDR_SD_CTL_DEIE | \ 264 AUDIOHDR_SD_CTL_FEIE | \ 265 AUDIOHDR_SD_CTL_IOCE) 266 267 268 /* bits for stream descriptor status register */ 269 #define AUDIOHDR_SD_STS_BCIS 0x0004 270 #define AUDIOHDR_SD_STS_FIFOE 0x0008 271 #define AUDIOHDR_SD_STS_DESE 0x0010 272 #define AUDIOHDR_SD_STS_FIFORY 0x0020 273 #define AUDIOHDR_SD_STS_INTRS \ 274 (AUDIOHDR_SD_STS_BCIS | \ 275 AUDIOHDR_SD_STS_FIFOE | \ 276 AUDIOHDR_SD_STS_DESE) 277 278 279 /* bits for GCTL register */ 280 #define AUDIOHDR_GCTL_CRST 0x00000001 281 #define AUDIOHDR_GCTL_URESPE 0x00000100 282 283 /* bits for CORBRP register */ 284 #define AUDIOHDR_CORBRP_RESET 0x8000 285 #define AUDIOHDR_CORBRP_WPTR 0x00ff 286 287 /* bits for CORBCTL register */ 288 #define AUDIOHDR_CORBCTL_CMEIE 0x01 289 #define AUDIOHDR_CORBCTL_DMARUN 0x02 290 291 /* bits for CORB SIZE register */ 292 #define AUDIOHDR_CORBSZ_8 0 293 #define AUDIOHDR_CORBSZ_16 1 294 #define AUDIOHDR_CORBSZ_256 2 295 296 /* bits for RIRBCTL register */ 297 #define AUDIOHDR_RIRBCTL_RINTCTL 0x01 298 #define AUDIOHDR_RIRBCTL_DMARUN 0x02 299 #define AUDIOHDR_RIRBCTL_RIRBOIC 0x04 300 #define AUDIOHDR_RIRBCTL_RSTINT 0xfe 301 302 /* bits for RIRBWP register */ 303 #define AUDIOHDR_RIRBWP_RESET 0x8000 304 #define AUDIOHDR_RIRBWP_WPTR 0x00ff 305 306 /* bits for RIRB SIZE register */ 307 #define AUDIOHDR_RIRBSZ_8 0 308 #define AUDIOHDR_RIRBSZ_16 1 309 #define AUDIOHDR_RIRBSZ_256 2 310 311 #define AUDIOHD_BDLE_RIRB_SDI 0x0000000f 312 #define AUDIOHD_BDLE_RIRB_UNSOLICIT 0x00000010 313 314 /* HD spec: ID of Root node is 0 */ 315 #define AUDIOHDC_NODE_ROOT 0x00 316 317 /* HD spec: ID of audio function group is "1" */ 318 #define AUDIOHDC_AUDIO_FUNC_GROUP 1 319 320 /* 321 * HD audio verbs can be either 12-bit or 4-bit in length. 322 */ 323 #define AUDIOHDC_12BIT_VERB_MASK 0xfffff000 324 #define AUDIOHDC_4BIT_VERB_MASK 0xfffffff0 325 326 /* 327 * 12-bit verbs 328 */ 329 #define AUDIOHDC_VERB_GET_PARAM 0xf00 330 331 #define AUDIOHDC_VERB_GET_CONN_SEL 0xf01 332 #define AUDIOHDC_VERB_SET_CONN_SEL 0x701 333 334 #define AUDIOHDC_VERB_GET_CONN_LIST_ENT 0xf02 335 #define AUDIOHDC_VERB_GET_PROCESS_STATE 0xf03 336 #define AUDIOHDC_VERB_GET_SDI_SEL 0xf04 337 338 #define AUDIOHDC_VERB_GET_POWER_STATE 0xf05 339 #define AUDIOHDC_VERB_SET_POWER_STATE 0x705 340 341 #define AUDIOHDC_VERB_GET_STREAM_CHANN 0xf06 342 #define AUDIOHDC_VERB_SET_STREAM_CHANN 0x706 343 344 #define AUDIOHDC_VERB_GET_PIN_CTRL 0xf07 345 #define AUDIOHDC_VERB_SET_PIN_CTRL 0x707 346 347 #define AUDIOHDC_VERB_GET_UNS_ENABLE 0xf08 348 349 #define AUDIOHDC_VERB_GET_PIN_SENSE 0xf09 350 #define AUDIOHDC_VERB_EXEC_PIN_SENSE 0x709 351 352 #define AUDIOHDC_VERB_GET_BEEP_GEN 0xf0a 353 354 #define AUDIOHDC_VERB_GET_EAPD 0xf0c 355 #define AUDIOHDC_VERB_SET_EAPD 0x70c 356 357 #define AUDIOHDC_VERB_GET_DEFAULT_CONF 0xf1c 358 #define AUDIOHDC_VERB_GET_SPDIF_CTL 0xf0d 359 #define AUDIOHDC_VERB_SET_SPDIF_LCL 0x70d 360 361 #define AUDIOHDC_VERB_SET_URCTRL 0x708 362 #define AUDIOHDC_VERB_GET_PIN_SENSE 0xf09 363 364 #define AUDIOHDC_VERB_GET_GPIO_MASK 0xf16 365 #define AUDIOHDC_VERB_SET_GPIO_MASK 0x716 366 367 #define AUDIOHDC_VERB_GET_GPIO_DIREC 0xf17 368 #define AUDIOHDC_VERB_SET_GPIO_DIREC 0x717 369 370 #define AUDIOHDC_VERB_GET_GPIO_DATA 0xf15 371 #define AUDIOHDC_VERB_SET_GPIO_DATA 0x715 372 373 #define AUDIOHDC_VERB_GET_GPIO_STCK 0xf1a 374 #define AUDIOHDC_VERB_SET_GPIO_STCK 0x71a 375 376 #define AUDIOHDC_GPIO_ENABLE 0xff 377 #define AUDIOHDC_GPIO_DIRECT 0xf1 378 379 #define AUDIOHDC_GPIO_DATA_CTRL 0xff 380 #define AUDIOHDC_GPIO_STCK_CTRL 0xff 381 /* 382 * 4-bit verbs 383 */ 384 #define AUDIOHDC_VERB_GET_CONV_FMT 0xa 385 #define AUDIOHDC_VERB_SET_CONV_FMT 0x2 386 387 #define AUDIOHDC_VERB_GET_AMP_MUTE 0xb 388 #define AUDIOHDC_VERB_SET_AMP_MUTE 0x3 389 390 /* 391 * parameters of nodes 392 */ 393 #define AUDIOHDC_PAR_VENDOR_ID 0x00 394 #define AUDIOHDC_PAR_SUBSYS_ID 0x01 395 #define AUDIOHDC_PAR_REV_ID 0x02 396 #define AUDIOHDC_PAR_NODE_COUNT 0x04 397 #define AUDIOHDC_PAR_FUNCTION_TYPE 0x05 398 #define AUDIOHDC_PAR_AUDIO_FG_CAP 0x08 399 #define AUDIOHDC_PAR_AUDIO_WID_CAP 0x09 400 #define AUDIOHDC_PAR_PCM 0x0a 401 #define AUDIOHDC_PAR_STREAM 0x0b 402 #define AUDIOHDC_PAR_PIN_CAP 0x0c 403 #define AUDIOHDC_PAR_INAMP_CAP 0x0d 404 #define AUDIOHDC_PAR_CONNLIST_LEN 0x0e 405 #define AUDIOHDC_PAR_POWER_STATE 0x0f 406 #define AUDIOHDC_PAR_PROC_CAP 0x10 407 #define AUDIOHDC_PAR_GPIO_CAP 0x11 408 #define AUDIOHDC_PAR_OUTAMP_CAP 0x12 409 410 /* 411 * bits for get/set amplifier gain/mute 412 */ 413 #define AUDIOHDC_AMP_SET_OUTPUT 0x8000 414 #define AUDIOHDC_AMP_SET_INPUT 0x4000 415 #define AUDIOHDC_AMP_SET_LEFT 0x2000 416 #define AUDIOHDC_AMP_SET_RIGHT 0x1000 417 #define AUDIOHDC_AMP_SET_MUTE 0x0080 418 #define AUDIOHDC_AMP_SET_LNR 0x3000 419 #define AUDIOHDC_AMP_SET_LR_INPUT 0x7000 420 #define AUDIOHDC_AMP_SET_LR_OUTPUT 0xb000 421 #define AUDIOHDC_AMP_SET_INDEX_OFFSET 8 422 #define AUDIOHDC_AMP_SET_GAIN_MASK 0x007f 423 #define AUDIOHDC_GAIN_MAX 0x7f 424 #define AUDIOHDC_GAIN_BITS 7 425 #define AUDIOHDC_GAIN_DEFAULT 0x0f 426 427 #define AUDIOHDC_AMP_GET_OUTPUT 0x8000 428 #define AUDIOHDC_AMP_GET_INPUT 0x0000 429 430 /* value used to set max volume for left output */ 431 #define AUDIOHDC_AMP_LOUT_MAX \ 432 (AUDIOHDC_AMP_SET_OUTPUT | \ 433 AUDIOHDC_AMP_SET_LEFT | \ 434 AUDIOHDC_GAIN_MAX) 435 436 /* value used to set max volume for right output */ 437 #define AUDIOHDC_AMP_ROUT_MAX \ 438 (AUDIOHDC_AMP_SET_OUTPUT | \ 439 AUDIOHDC_AMP_SET_RIGHT | \ 440 AUDIOHDC_GAIN_MAX) 441 442 443 /* 444 * Bits for pin widget control verb 445 */ 446 #define AUDIOHDC_PIN_CONTROL_HP_ENABLE 0x80 447 #define AUDIOHDC_PIN_CONTROL_OUT_ENABLE 0x40 448 #define AUDIOHDC_PIN_CONTROL_IN_ENABLE 0x20 449 450 /* 451 * Bits for Amplifier capabilities 452 */ 453 #define AUDIOHDC_AMP_CAP_MUTE_CAP 0x80000000 454 #define AUDIOHDC_AMP_CAP_STEP_SIZE 0x007f0000 455 #define AUDIOHDC_AMP_CAP_STEP_NUMS 0x00007f00 456 #define AUDIOHDC_AMP_CAP_0DB_OFFSET 0x0000007f 457 458 459 /* 460 * Bits for Audio Widget Capabilities 461 */ 462 #define AUDIOHD_WIDCAP_STEREO 0x00000001 463 #define AUDIOHD_WIDCAP_INAMP 0x00000002 464 #define AUDIOHD_WIDCAP_OUTAMP 0x00000004 465 #define AUDIOHD_WIDCAP_AMP_OVRIDE 0x00000008 466 #define AUDIOHD_WIDCAP_FMT_OVRIDE 0x00000010 467 #define AUDIOHD_WIDCAP_STRIP 0x00000020 468 #define AUDIOHD_WIDCAP_PROC_WID 0x00000040 469 #define AUDIOHD_WIDCAP_UNSOL 0x00000080 470 #define AUDIOHD_WIDCAP_CONNLIST 0x00000100 471 #define AUDIOHD_WIDCAP_DIGIT 0x00000200 472 #define AUDIOHD_WIDCAP_PWRCTRL 0x00000400 473 #define AUDIOHD_WIDCAP_LRSWAP 0x00000800 474 #define AUDIOHD_WIDCAP_TYPE 0x00f00000 475 #define AUDIOHD_WIDCAP_TO_WIDTYPE(wcap) \ 476 ((wcap & AUDIOHD_WIDCAP_TYPE) >> 20) 477 478 479 #define AUDIOHD_CODEC_FAILURE (uint32_t)(-1) 480 481 /* 482 * buffer descriptor list entry of stream descriptor 483 */ 484 typedef struct { 485 uint64_t sbde_addr; 486 uint32_t sbde_len; 487 uint32_t 488 sbde_ioc: 1, 489 reserved: 31; 490 }sd_bdle_t; 491 492 493 #define AUDIOHD_PLAY_STARTED 0x00000001 494 #define AUDIOHD_PLAY_EMPTY 0x00000002 495 #define AUDIOHD_PLAY_PAUSED 0x00000004 496 #define AUDIOHD_RECORD_STARTED 0x00000008 497 498 enum audiohda_widget_type { 499 WTYPE_AUDIO_OUT = 0, 500 WTYPE_AUDIO_IN, 501 WTYPE_AUDIO_MIX, 502 WTYPE_AUDIO_SEL, 503 WTYPE_PIN, 504 WTYPE_POWER, 505 WTYPE_VOL_KNOB, 506 WTYPE_BEEP, 507 WTYPE_VENDOR = 0xf 508 }; 509 510 enum audiohda_device_type { 511 DTYPE_LINEOUT = 0, 512 DTYPE_SPEAKER, 513 DTYPE_HP_OUT, 514 DTYPE_CD, 515 DTYPE_SPDIF_OUT, 516 DTYPE_DIGIT_OUT, 517 DTYPE_MODEM_SIDE, 518 DTYPE_MODEM_HNAD_SIDE, 519 DTYPE_LINE_IN, 520 DTYPE_AUX, 521 DTYPE_MIC_IN, 522 DTYPE_TEL, 523 DTYPE_SPDIF_IN, 524 DTYPE_DIGIT_IN, 525 DTYPE_OTHER = 0x0f, 526 }; 527 528 enum audiohd_pin_color { 529 AUDIOHD_PIN_UNKNOWN = 0, 530 AUDIOHD_PIN_BLACK, 531 AUDIOHD_PIN_GREY, 532 AUDIOHD_PIN_BLUE, 533 AUDIOHD_PIN_GREEN, 534 AUDIOHD_PIN_RED, 535 AUDIOHD_PIN_ORANGE, 536 AUDIOHD_PIN_YELLOW, 537 AUDIOHD_PIN_PURPLE, 538 AUDIOHD_PIN_PINK, 539 AUDIOHD_PIN_WHITE = 0xe, 540 AUDIOHD_PIN_OTHER = 0xf, 541 }; 542 543 #define CTRL_NUM 15 544 545 /* values for audiohd_widget.path_flags */ 546 #define AUDIOHD_PATH_DAC (1 << 0) 547 #define AUDIOHD_PATH_ADC (1 << 1) 548 #define AUDIOHD_PATH_MON (1 << 2) 549 #define AUDIOHD_PATH_NOMON (1 << 3) 550 551 typedef struct audiohd_path audiohd_path_t; 552 typedef struct audiohd_widget audiohd_widget_t; 553 typedef struct audiohd_state audiohd_state_t; 554 typedef struct audiohd_pin audiohd_pin_t; 555 typedef struct hda_codec hda_codec_t; 556 typedef uint32_t wid_t; /* id of widget */ 557 typedef struct audiohd_entry_prop audiohd_entry_prop_t; 558 typedef enum audiohda_device_type audiohda_device_type_t; 559 typedef enum audiohd_pin_color audiohd_pin_color_t; 560 561 #define AUDIOHD_MAX_WIDGET 128 562 #define AUDIOHD_MAX_CONN 16 563 #define AUDIOHD_MAX_PINS 16 564 #define AUDIOHD_MAX_DEPTH 8 565 566 struct audiohd_entry_prop { 567 uint32_t conn_len; 568 uint32_t mask_range; 569 uint32_t mask_wid; 570 wid_t input_wid; 571 int conns_per_entry; 572 int bits_per_conn; 573 }; 574 struct audiohd_widget { 575 wid_t wid_wid; 576 hda_codec_t *codec; 577 enum audiohda_widget_type type; 578 579 uint32_t widget_cap; 580 uint32_t pcm_format; 581 uint32_t inamp_cap; 582 uint32_t outamp_cap; 583 584 uint32_t path_flags; 585 586 int out_weight; 587 int in_weight; 588 int finish; 589 590 /* 591 * wid of possible & selected input connections 592 */ 593 wid_t avail_conn[AUDIOHD_MAX_CONN]; 594 wid_t selconn; 595 /* 596 * for monitor path 597 */ 598 wid_t selmon[AUDIOHD_MAX_CONN]; 599 uint16_t used; 600 601 /* 602 * available (input) connections. 0 means this widget 603 * has fixed connection 604 */ 605 int nconns; 606 607 /* 608 * pointer to struct depending on widget type: 609 * 1. DAC audiohd_ostream_t 610 * 2. ADC audiohd_istream_t 611 * 3. PIN audiohd_pin_t 612 */ 613 void *priv; 614 }; 615 616 #define AUDIOHD_FLAG_LINEOUT (1 << 0) 617 #define AUDIOHD_FLAG_SPEAKER (1 << 1) 618 #define AUDIOHD_FLAG_HP (1 << 2) 619 #define AUDIOHD_FLAG_MONO (1 << 3) 620 621 #define AUDIOHD_MAX_MIXER 5 622 #define AUDIOHD_MAX_PIN 4 623 624 #define PORT_DAC 0 625 #define PORT_ADC 1 626 #define PORT_MAX 2 627 typedef enum { 628 PLAY = 0, 629 RECORD = 1, 630 } path_type_t; 631 632 struct audiohd_path { 633 wid_t adda_wid; 634 635 wid_t pin_wid[AUDIOHD_MAX_PINS]; 636 int sum_selconn[AUDIOHD_MAX_PINS]; 637 int mon_wid[AUDIOHD_MAX_PIN][AUDIOHD_MAX_MIXER]; 638 int pin_nums; 639 int maxmixer[AUDIOHD_MAX_PINS]; 640 641 path_type_t path_type; 642 643 wid_t mute_wid; 644 int mute_dir; 645 wid_t gain_wid; 646 int gain_dir; 647 uint32_t gain_bits; 648 649 uint32_t pin_outputs; 650 uint8_t tag; 651 652 hda_codec_t *codec; 653 654 wid_t sum_wid; 655 656 audiohd_state_t *statep; 657 }; 658 659 typedef struct audiohd_port 660 { 661 uint8_t nchan; 662 int index; 663 uint16_t regoff; 664 boolean_t started; 665 boolean_t triggered; 666 667 unsigned fragfr; 668 unsigned nframes; 669 uint64_t count; 670 int curpos; 671 int len; 672 int intrs; 673 674 uint_t format; 675 unsigned sync_dir; 676 677 ddi_dma_handle_t samp_dmah; 678 ddi_acc_handle_t samp_acch; 679 size_t samp_size; 680 caddr_t samp_kaddr; 681 uint64_t samp_paddr; 682 683 ddi_dma_handle_t bdl_dmah; 684 ddi_acc_handle_t bdl_acch; 685 size_t bdl_size; 686 caddr_t bdl_kaddr; 687 uint64_t bdl_paddr; 688 689 audio_engine_t *engine; 690 audiohd_state_t *statep; 691 }audiohd_port_t; 692 693 typedef struct audiohd_ctrl 694 { 695 audiohd_state_t *statep; 696 audio_ctrl_t *ctrl; 697 uint32_t num; 698 uint64_t val; 699 } audiohd_ctrl_t; 700 701 struct audiohd_pin { 702 audiohd_pin_t *next; 703 wid_t wid; 704 wid_t mute_wid; /* node used to mute this pin */ 705 int mute_dir; /* 1: input, 2: output */ 706 wid_t gain_wid; /* node for gain control */ 707 int gain_dir; /* _OUTPUT/_INPUT */ 708 uint32_t gain_bits; 709 710 uint8_t vrefvalue; /* value of VRef */ 711 712 uint32_t cap; 713 uint32_t config; 714 uint32_t ctrl; 715 uint32_t assoc; 716 uint32_t seq; 717 wid_t adc_dac_wid; /* AD/DA wid which can route to this pin */ 718 int no_phys_conn; 719 enum audiohda_device_type device; 720 721 /* 722 * mg_dir, mg_gain, mg_wid are used to store the monitor gain control 723 * widget wid. 724 */ 725 int mg_dir[AUDIOHD_MAX_CONN]; 726 int mg_gain[AUDIOHD_MAX_CONN]; 727 int mg_wid[AUDIOHD_MAX_CONN]; 728 int num; 729 int finish; 730 731 }; 732 733 typedef struct { 734 ddi_dma_handle_t ad_dmahdl; 735 ddi_acc_handle_t ad_acchdl; 736 caddr_t ad_vaddr; /* virtual addr */ 737 uint64_t ad_paddr; /* physical addr */ 738 size_t ad_req_sz; /* required size of memory */ 739 size_t ad_real_sz; /* real size of memory */ 740 } audiohd_dma_t; 741 742 struct hda_codec { 743 uint8_t index; /* codec address */ 744 uint32_t vid; /* vendor id and device id */ 745 uint32_t revid; /* revision id */ 746 wid_t wid_afg; /* id of AFG */ 747 wid_t first_wid; /* wid of 1st subnode of AFG */ 748 wid_t last_wid; /* wid of the last subnode of AFG */ 749 int nnodes; /* # of subnodes of AFG */ 750 uint8_t nistream; 751 752 uint32_t outamp_cap; 753 uint32_t inamp_cap; 754 uint32_t stream_format; 755 uint32_t pcm_format; 756 757 audiohd_state_t *soft_statep; 758 759 /* use wid as index to the array of widget pointers */ 760 audiohd_widget_t *widget[AUDIOHD_MAX_WIDGET]; 761 762 763 audiohd_port_t *port[AUDIOHD_PORT_MAX]; 764 uint8_t portnum; 765 audiohd_pin_t *first_pin; 766 }; 767 768 #define AUDIOHD_MAX_ASSOC 15 769 struct audiohd_state { 770 dev_info_t *hda_dip; 771 kstat_t *hda_ksp; 772 kmutex_t hda_mutex; 773 uint32_t hda_flags; 774 775 boolean_t soft_volume; 776 777 caddr_t hda_reg_base; 778 ddi_acc_handle_t hda_pci_handle; 779 ddi_acc_handle_t hda_reg_handle; 780 ddi_iblock_cookie_t hda_intr_cookie; 781 782 audiohd_dma_t hda_dma_corb; 783 audiohd_dma_t hda_dma_rirb; 784 785 786 uint8_t hda_rirb_rp; /* read pointer for rirb */ 787 uint16_t hda_codec_mask; 788 789 790 audio_dev_t *adev; 791 792 793 int hda_pint_freq; /* play intr frequence */ 794 int hda_rint_freq; /* record intr frequence */ 795 796 int hda_input_streams; /* # of input stream */ 797 int hda_output_streams; /* # of output stream */ 798 int hda_streams_nums; /* # of stream */ 799 800 uint_t hda_play_regbase; 801 uint_t hda_record_regbase; 802 803 uint_t hda_play_stag; /* tag of playback stream */ 804 uint_t hda_record_stag; /* tag of record stream */ 805 uint_t hda_play_lgain; /* left gain for playback */ 806 uint_t hda_play_rgain; /* right gain for playback */ 807 808 /* 809 * Now, for the time being, we add some fields 810 * for parsing codec topology 811 */ 812 hda_codec_t *codec[AUDIOHD_CODEC_MAX]; 813 /* 814 * Suspend/Resume used fields 815 */ 816 boolean_t suspended; 817 boolean_t monitor_unsupported; 818 819 audiohd_path_t *path[AUDIOHD_PORT_MAX]; 820 uint8_t pathnum; 821 audiohd_port_t *port[PORT_MAX]; 822 uint8_t pchan; 823 uint8_t rchan; 824 825 uint64_t inmask; 826 827 uint_t hda_out_ports; 828 uint_t in_port; 829 830 /* 831 * Controls 832 */ 833 audiohd_ctrl_t *controls[CTRL_NUM]; 834 835 /* for multichannel */ 836 uint8_t chann[AUDIOHD_MAX_ASSOC]; 837 uint8_t assoc; 838 839 }; 840 841 842 /* 843 * Operation for high definition audio control system bus 844 * interface registers 845 */ 846 #define AUDIOHD_REG_GET8(reg) \ 847 ddi_get8(statep->hda_reg_handle, \ 848 (void *)((char *)statep->hda_reg_base + (reg))) 849 850 #define AUDIOHD_REG_GET16(reg) \ 851 ddi_get16(statep->hda_reg_handle, \ 852 (void *)((char *)statep->hda_reg_base + (reg))) 853 854 #define AUDIOHD_REG_GET32(reg) \ 855 ddi_get32(statep->hda_reg_handle, \ 856 (void *)((char *)statep->hda_reg_base + (reg))) 857 858 #define AUDIOHD_REG_GET64(reg) \ 859 ddi_get64(statep->hda_reg_handle, \ 860 (void *)((char *)statep->hda_reg_base + (reg))) 861 862 #define AUDIOHD_REG_SET8(reg, val) \ 863 ddi_put8(statep->hda_reg_handle, \ 864 (void *)((char *)statep->hda_reg_base + (reg)), (val)) 865 866 #define AUDIOHD_REG_SET16(reg, val) \ 867 ddi_put16(statep->hda_reg_handle, \ 868 (void *)((char *)statep->hda_reg_base + (reg)), (val)) 869 870 #define AUDIOHD_REG_SET32(reg, val) \ 871 ddi_put32(statep->hda_reg_handle, \ 872 (void *)((char *)statep->hda_reg_base + (reg)), (val)) 873 874 #define AUDIOHD_REG_SET64(reg, val) \ 875 ddi_put64(statep->hda_reg_handle, \ 876 (void *)((char *)statep->hda_reg_base + (reg)), (val)) 877 878 879 /* 880 * enable a pin widget to output 881 */ 882 #define AUDIOHD_ENABLE_PIN_OUT(statep, caddr, wid) \ 883 { \ 884 uint32_t lTmp; \ 885 \ 886 lTmp = audioha_codec_verb_get(statep, caddr, wid, \ 887 AUDIOHDC_VERB_GET_PIN_CTRL, 0); \ 888 if (lTmp == AUDIOHD_CODEC_FAILURE) \ 889 return (AUDIO_FAILURE); \ 890 lTmp = audioha_codec_verb_get(statep, caddr, wid, \ 891 AUDIOHDC_VERB_SET_PIN_CTRL, \ 892 (lTmp | AUDIOHDC_PIN_CONTROL_OUT_ENABLE | \ 893 AUDIOHDC_PIN_CONTROL_HP_ENABLE)); \ 894 if (lTmp == AUDIOHD_CODEC_FAILURE) \ 895 return (AUDIO_FAILURE); \ 896 } 897 898 /* 899 * disable output pin 900 */ 901 #define AUDIOHD_DISABLE_PIN_OUT(statep, caddr, wid) \ 902 { \ 903 uint32_t lTmp; \ 904 \ 905 lTmp = audioha_codec_verb_get(statep, caddr, wid, \ 906 AUDIOHDC_VERB_GET_PIN_CTRL, 0); \ 907 if (lTmp == AUDIOHD_CODEC_FAILURE) \ 908 return (AUDIO_FAILURE); \ 909 lTmp = audioha_codec_verb_get(statep, caddr, wid, \ 910 AUDIOHDC_VERB_SET_PIN_CTRL, \ 911 (lTmp & ~AUDIOHDC_PIN_CONTROL_OUT_ENABLE)); \ 912 if (lTmp == AUDIOHD_CODEC_FAILURE) \ 913 return (AUDIO_FAILURE); \ 914 } 915 916 /* 917 * enable a pin widget to input 918 */ 919 #define AUDIOHD_ENABLE_PIN_IN(statep, caddr, wid) \ 920 { \ 921 (void) audioha_codec_verb_get(statep, caddr, wid, \ 922 AUDIOHDC_VERB_SET_PIN_CTRL, AUDIOHDC_PIN_CONTROL_IN_ENABLE | 4); \ 923 } 924 925 926 /* 927 * disable input pin 928 */ 929 #define AUDIOHD_DISABLE_PIN_IN(statep, caddr, wid) \ 930 { \ 931 uint32_t lTmp; \ 932 \ 933 lTmp = audioha_codec_verb_get(statep, caddr, wid, \ 934 AUDIOHDC_VERB_GET_PIN_CTRL, 0); \ 935 if (lTmp == AUDIOHD_CODEC_FAILURE) \ 936 return (AUDIO_FAILURE); \ 937 lTmp = audioha_codec_verb_get(statep, caddr, wid, \ 938 AUDIOHDC_VERB_SET_PIN_CTRL, \ 939 (lTmp & ~AUDIOHDC_PIN_CONTROL_IN_ENABLE)); \ 940 if (lTmp == AUDIOHD_CODEC_FAILURE) \ 941 return (AUDIO_FAILURE); \ 942 } 943 944 /* 945 * unmute an output pin 946 */ 947 #define AUDIOHD_NODE_UNMUTE_OUT(statep, caddr, wid) \ 948 { \ 949 if (audioha_codec_4bit_verb_get(statep, \ 950 caddr, wid, AUDIOHDC_VERB_SET_AMP_MUTE, \ 951 AUDIOHDC_AMP_SET_LR_OUTPUT | AUDIOHDC_GAIN_MAX) == \ 952 AUDIOHD_CODEC_FAILURE) \ 953 return (AUDIO_FAILURE); \ 954 } 955 956 #ifdef __cplusplus 957 } 958 #endif 959 960 #endif /* _SYS_AUDIOHD_IMPL_H_ */ 961