1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 #ifndef _SYS_AUDIOHD_IMPL_H_ 26 #define _SYS_AUDIOHD_IMPL_H_ 27 28 #ifdef __cplusplus 29 extern "C" { 30 #endif 31 32 /* 33 * vendor IDs of PCI audio controllers 34 */ 35 #define AUDIOHD_VID_ATI 0x1002 36 #define AUDIOHD_VID_CIRRUS 0x1013 37 #define AUDIOHD_VID_NVIDIA 0x10de 38 #define AUDIOHD_VID_REALTEK 0x10ec 39 #define AUDIOHD_VID_CREATIVE 0x1102 40 #define AUDIOHD_VID_IDT 0x111d 41 #define AUDIOHD_VID_ANALOG 0x11d4 42 #define AUDIOHD_VID_CONEXANT 0x14f1 43 #define AUDIOHD_VID_SIGMATEL 0x8384 44 #define AUDIOHD_VID_INTEL 0x8086 45 46 /* 47 * specific audiohd controller device id 48 */ 49 #define AUDIOHD_CONTROLLER_MCP51 0x10de026c 50 51 /* 52 * codec special initial flags 53 */ 54 #define NO_GPIO 0x00000001 55 #define NO_MIXER 0x00000002 56 #define NO_SPDIF 0x00000004 57 #define EN_PIN_BEEP 0x00000008 58 59 #define AUDIOHD_DEV_CONFIG "onboard1" 60 #define AUDIOHD_DEV_VERSION "a" 61 62 #define AUDIOHD_FMT_PCM 0x001 63 /* 64 * Only for Intel hardware: 65 * PCI Express traffic class select register in PCI configure space 66 */ 67 #define AUDIOHD_INTEL_PCI_TCSEL 0x44 68 69 /* 70 * Only for ATI SB450: 71 * MISC control register 2 72 */ 73 #define AUDIOHD_ATI_PCI_MISC2 0x42 74 #define AUDIOHD_ATI_MISC2_SNOOP 0x02 75 #define AUDIOHDC_NID(x) x 76 #define AUDIOHDC_NULL_NODE -1 77 #define AUDIOHD_NULL_CONN ((uint_t)(-1)) 78 /* 79 * currently, only the format of 48K sample rate, 16-bit 80 * 2-channel is supported. 81 */ 82 #define AUDIOHD_FMT_PCMOUT 0x0011 83 #define AUDIOHD_FMT_PCMIN 0x0011 84 85 #define AUDIOHD_EXT_AMP_MASK 0x00010000 86 #define AUDIOHD_EXT_AMP_ENABLE 0x02 87 /* NVIDIA snoop */ 88 #define AUDIOHD_NVIDIA_SNOOP 0x0f 89 90 /* Power On/Off */ 91 #define AUDIOHD_PW_D0 0 92 #define AUDIOHD_PW_D2 2 93 94 #define AUDIOHD_INTEL_TCS_MASK 0xf8 95 #define AUDIOHD_ATI_MISC2_MASK 0xf8 96 97 /* Pin speaker On/Off */ 98 #define AUDIOHD_SP_ON 1 99 #define AUDIOHD_SP_OFF 0 100 101 #define AUDIOHD_PORT_MAX 15 102 #define AUDIOHD_CODEC_MAX 16 103 #define AUDIOHD_MEMIO_LEN 0x4000 104 105 #define AUDIOHD_RETRY_TIMES 60 106 #define AUDIOHD_TEST_TIMES 500 107 #define AUDIOHD_OUTSTR_NUM_OFF 12 108 #define AUDIOHD_INSTR_NUM_OFF 8 109 110 #define AUDIOHD_CORB_SIZE_OFF 0x4e 111 112 #define AUDIOHD_URCAP_MASK 0x80 113 #define AUDIOHD_DTCCAP_MASK 0x4 114 #define AUDIOHD_UR_ENABLE_OFF 8 115 #define AUDIOHD_UR_TAG_MASK 0x3f 116 117 #define AUDIOHD_CIS_MASK 0x40000000 118 119 #define AUDIOHD_RIRB_UR_MASK 0x10 120 #define AUDIOHD_RIRB_CODEC_MASK 0xf 121 #define AUDIOHD_RIRB_WID_OFF 27 122 #define AUDIOHD_RIRB_INTRCNT 0x0 123 #define AUDIOHD_RIRB_WPMASK 0xff 124 125 #define AUDIOHD_FORM_MASK 0x0080 126 #define AUDIOHD_LEN_MASK 0x007f 127 #define AUDIOHD_PIN_CAP_MASK 0x00000010 128 #define AUDIOHD_PIN_CONF_MASK 0xc0000000 129 #define AUDIOHD_PIN_CON_MASK 3 130 #define AUDIOHD_PIN_CON_STEP 30 131 #define AUDIOHD_PIN_IO_MASK 0X0018 132 #define AUDIOHD_PIN_SEQ_MASK 0x0000000f 133 #define AUDIOHD_PIN_ASO_MASK 0x000000f0 134 #define AUDIOHD_PIN_ASO_OFF 0x4 135 #define AUDIOHD_PIN_DEV_MASK 0x00f00000 136 #define AUDIOHD_PIN_DEV_OFF 20 137 #define AUDIOHD_PIN_NUMS 6 138 #define AUDIOHD_PIN_NO_CONN 0x40000000 139 #define AUDIOHD_PIN_IN_ENABLE 0x20 140 #define AUDIOHD_PIN_OUT_ENABLE 0x40 141 #define AUDIOHD_PIN_PRES_MASK 0x80000000 142 #define AUDIOHD_PIN_CONTP_OFF 0x1e 143 #define AUDIOHD_PIN_CON_JACK 0 144 #define AUDIOHD_PIN_CON_FIXED 0x2 145 #define AUDIOHD_PIN_CONTP_MASK 0x3 146 #define AUDIOHD_PIN_VREF_L1 0x20 147 #define AUDIOHD_PIN_VREF_L2 0x10 148 #define AUDIOHD_PIN_VREF_L3 0x04 149 #define AUDIOHD_PIN_VREF_L4 0x02 150 #define AUDIOHD_PIN_VREF_OFF 8 151 #define AUDIOHD_PIN_VREF_MASK 0xff 152 #define AUDIOHD_PIN_CLR_MASK 0xf 153 #define AUDIOHD_PIN_CLR_OFF 12 154 155 #define AUDIOHD_VERB_ADDR_OFF 28 156 #define AUDIOHD_VERB_NID_OFF 20 157 #define AUDIOHD_VERB_CMD_OFF 8 158 #define AUDIOHD_VERB_CMD16_OFF 16 159 160 #define AUDIOHD_RING_MAX_SIZE 0x00ff 161 #define AUDIOHD_REC_TAG_OFF 4 162 #define AUDIOHD_PLAY_TAG_OFF 4 163 #define AUDIOHD_PLAY_CTL_OFF 2 164 #define AUDIOHD_REC_CTL_OFF 2 165 166 #define AUDIOHD_SPDIF_ON 1 167 #define AUDIOHD_SPDIF_MASK 0x00ff 168 169 #define AUDIOHD_GAIN_OFF 8 170 171 #define AUDIOHD_CODEC_STR_OFF 16 172 #define AUDIOHD_CODEC_STR_MASK 0x000000ff 173 #define AUDIOHD_CODEC_NUM_MASK 0x000000ff 174 #define AUDIOHD_CODEC_TYPE_MASK 0x000000ff 175 176 #define AUDIOHD_ROUNDUP(x, algn) (((x) + ((algn) - 1)) & ~((algn) - 1)) 177 #define AUDIOHD_BDLE_BUF_ALIGN 128 178 #define AUDIOHD_CMDIO_ENT_MASK 0x00ff /* 256 entries for CORB/RIRB */ 179 #define AUDIOHD_CDBIO_CORB_LEN 1024 /* 256 entries for CORB, 1024B */ 180 #define AUDIOHD_CDBIO_RIRB_LEN 2048 /* 256 entries for RIRB, 2048B */ 181 #define AUDIOHD_BDLE_NUMS 4 /* 4 entires for record/play BD list */ 182 183 #define AUDIOHD_PORT_UNMUTE (0xffffffff) 184 185 /* 186 * Audio registers of high definition 187 */ 188 #define AUDIOHD_REG_GCAP 0x00 189 #define AUDIOHDR_GCAP_OUTSTREAMS 0xf000 190 #define AUDIOHDR_GCAP_INSTREAMS 0x0f00 191 #define AUDIOHDR_GCAP_BSTREAMS 0x00f8 192 #define AUDIOHDR_GCAP_NSDO 0x0006 193 #define AUDIOHDR_GCAP_64OK 0x0001 194 195 #define AUDIOHD_REG_VMIN 0x02 196 #define AUDIOHD_REG_VMAJ 0x03 197 #define AUDIOHD_REG_OUTPAY 0x04 198 #define AUDIOHD_REG_INPAY 0x06 199 #define AUDIOHD_REG_GCTL 0x08 200 #define AUDIOHD_REG_WAKEEN 0x0C 201 #define AUDIOHD_REG_STATESTS 0x0E 202 #define AUDIOHD_STATESTS_BIT_SDINS 0x7F 203 204 #define AUDIOHD_REG_GSTS 0x10 205 #define AUDIOHD_REG_INTCTL 0x20 206 #define AUDIOHD_INTCTL_BIT_GIE 0x80000000 207 #define AUDIOHD_INTCTL_BIT_CIE 0x40000000 208 #define AUDIOHD_INTCTL_BIT_SIE 0x3FFFFFFF 209 210 211 #define AUDIOHD_REG_INTSTS 0x24 212 #define AUDIOHD_INTSTS_BIT_GIS 0x80000000 213 #define AUDIOHD_INTSTS_BIT_CIS 0x40000000 214 #define AUDIOHD_INTSTS_BIT_SINTS (0x3fffffff) 215 216 #define AUDIOHD_REG_WALCLK 0x30 217 #define AUDIOHD_REG_SYNC 0x38 218 219 #define AUDIOHD_REG_CORBLBASE 0x40 220 #define AUDIOHD_REG_CORBUBASE 0x44 221 #define AUDIOHD_REG_CORBWP 0x48 222 #define AUDIOHD_REG_CORBRP 0x4A 223 #define AUDIOHD_REG_CORBCTL 0x4C 224 #define AUDIOHD_REG_CORBST 0x4D 225 #define AUDIOHD_REG_CORBSIZE 0x4E 226 227 #define AUDIOHD_REG_RIRBLBASE 0x50 228 #define AUDIOHD_REG_RIRBUBASE 0x54 229 #define AUDIOHD_REG_RIRBWP 0x58 230 #define AUDIOHD_REG_RINTCNT 0x5A 231 #define AUDIOHD_REG_RIRBCTL 0x5C 232 #define AUDIOHD_REG_RIRBSTS 0x5D 233 #define AUDIOHD_REG_RIRBSIZE 0x5E 234 235 #define AUDIOHD_REG_IC 0x60 236 #define AUDIOHD_REG_IR 0x64 237 #define AUDIOHD_REG_IRS 0x68 238 #define AUDIOHD_REG_DPLBASE 0x70 239 #define AUDIOHD_REG_DPUBASE 0x74 240 241 #define AUDIOHD_REG_SD_BASE 0x80 242 #define AUDIOHD_REG_SD_LEN 0x20 243 244 /* 245 * Offset of Stream Descriptor Registers 246 */ 247 #define AUDIOHD_SDREG_OFFSET_CTL 0x00 248 #define AUDIOHD_SDREG_OFFSET_STS 0x03 249 #define AUDIOHD_SDREG_OFFSET_LPIB 0x04 250 #define AUDIOHD_SDREG_OFFSET_CBL 0x08 251 #define AUDIOHD_SDREG_OFFSET_LVI 0x0c 252 #define AUDIOHD_SDREG_OFFSET_FIFOW 0x0e 253 #define AUDIOHD_SDREG_OFFSET_FIFOSIZE 0x10 254 #define AUDIOHD_SDREG_OFFSET_FORMAT 0x12 255 #define AUDIOHD_SDREG_OFFSET_BDLPL 0x18 256 #define AUDIOHD_SDREG_OFFSET_BDLPU 0x1c 257 258 /* bits for stream descriptor control reg */ 259 #define AUDIOHDR_SD_CTL_DEIE 0x000010 260 #define AUDIOHDR_SD_CTL_FEIE 0x000008 261 #define AUDIOHDR_SD_CTL_IOCE 0x000004 262 #define AUDIOHDR_SD_CTL_SRUN 0x000002 263 #define AUDIOHDR_SD_CTL_SRST 0x000001 264 265 /* bits for stream descriptor status register */ 266 #define AUDIOHDR_SD_STS_BCIS 0x0004 267 #define AUDIOHDR_SD_STS_FIFOE 0x0008 268 #define AUDIOHDR_SD_STS_DESE 0x0010 269 #define AUDIOHDR_SD_STS_FIFORY 0x0020 270 #define AUDIOHDR_SD_STS_INTRS \ 271 (AUDIOHDR_SD_STS_BCIS | \ 272 AUDIOHDR_SD_STS_FIFOE | \ 273 AUDIOHDR_SD_STS_DESE) 274 275 276 /* bits for GCTL register */ 277 #define AUDIOHDR_GCTL_CRST 0x00000001 278 #define AUDIOHDR_GCTL_URESPE 0x00000100 279 280 /* bits for CORBRP register */ 281 #define AUDIOHDR_CORBRP_RESET 0x8000 282 #define AUDIOHDR_CORBRP_WPTR 0x00ff 283 284 /* bits for CORBCTL register */ 285 #define AUDIOHDR_CORBCTL_CMEIE 0x01 286 #define AUDIOHDR_CORBCTL_DMARUN 0x02 287 288 /* bits for CORB SIZE register */ 289 #define AUDIOHDR_CORBSZ_8 0 290 #define AUDIOHDR_CORBSZ_16 1 291 #define AUDIOHDR_CORBSZ_256 2 292 293 /* bits for RIRBCTL register */ 294 #define AUDIOHDR_RIRBCTL_RINTCTL 0x01 295 #define AUDIOHDR_RIRBCTL_DMARUN 0x02 296 #define AUDIOHDR_RIRBCTL_RIRBOIC 0x04 297 #define AUDIOHDR_RIRBCTL_RSTINT 0xfe 298 299 /* bits for RIRBWP register */ 300 #define AUDIOHDR_RIRBWP_RESET 0x8000 301 #define AUDIOHDR_RIRBWP_WPTR 0x00ff 302 303 /* bits for RIRB SIZE register */ 304 #define AUDIOHDR_RIRBSZ_8 0 305 #define AUDIOHDR_RIRBSZ_16 1 306 #define AUDIOHDR_RIRBSZ_256 2 307 308 #define AUDIOHD_BDLE_RIRB_SDI 0x0000000f 309 #define AUDIOHD_BDLE_RIRB_UNSOLICIT 0x00000010 310 311 /* HD spec: ID of Root node is 0 */ 312 #define AUDIOHDC_NODE_ROOT 0x00 313 314 /* HD spec: ID of audio function group is "1" */ 315 #define AUDIOHDC_AUDIO_FUNC_GROUP 1 316 317 /* 318 * HD audio verbs can be either 12-bit or 4-bit in length. 319 */ 320 #define AUDIOHDC_12BIT_VERB_MASK 0xfffff000 321 #define AUDIOHDC_4BIT_VERB_MASK 0xfffffff0 322 323 #define AUDIOHDC_SAMPR48000 48000 324 #define AUDIOHDC_MAX_BEEP_GEN 12000 325 #define AUDIOHDC_MIX_BEEP_GEN 47 326 #define AUDIOHDC_MUTE_BEEP_GEN 0x0 327 328 /* 329 * 12-bit verbs 330 */ 331 #define AUDIOHDC_VERB_GET_PARAM 0xf00 332 333 #define AUDIOHDC_VERB_GET_CONN_SEL 0xf01 334 #define AUDIOHDC_VERB_SET_CONN_SEL 0x701 335 336 #define AUDIOHDC_VERB_GET_CONN_LIST_ENT 0xf02 337 #define AUDIOHDC_VERB_GET_PROCESS_STATE 0xf03 338 #define AUDIOHDC_VERB_GET_SDI_SEL 0xf04 339 340 #define AUDIOHDC_VERB_GET_POWER_STATE 0xf05 341 #define AUDIOHDC_VERB_SET_POWER_STATE 0x705 342 343 #define AUDIOHDC_VERB_GET_STREAM_CHANN 0xf06 344 #define AUDIOHDC_VERB_SET_STREAM_CHANN 0x706 345 346 #define AUDIOHDC_VERB_GET_PIN_CTRL 0xf07 347 #define AUDIOHDC_VERB_SET_PIN_CTRL 0x707 348 349 #define AUDIOHDC_VERB_GET_UNS_ENABLE 0xf08 350 #define AUDIOHDC_VERB_SET_UNS_ENABLE 0x708 351 352 #define AUDIOHDC_VERB_GET_PIN_SENSE 0xf09 353 #define AUDIOHDC_VERB_GET_PIN_SENSE 0xf09 354 #define AUDIOHDC_VERB_EXEC_PIN_SENSE 0x709 355 356 #define AUDIOHDC_VERB_GET_BEEP_GEN 0xf0a 357 #define AUDIOHDC_VERB_SET_BEEP_GEN 0x70a 358 359 #define AUDIOHDC_VERB_GET_EAPD 0xf0c 360 #define AUDIOHDC_VERB_SET_EAPD 0x70c 361 362 #define AUDIOHDC_VERB_GET_DEFAULT_CONF 0xf1c 363 #define AUDIOHDC_VERB_GET_SPDIF_CTL 0xf0d 364 #define AUDIOHDC_VERB_SET_SPDIF_LCL 0x70d 365 366 #define AUDIOHDC_VERB_GET_GPIO_MASK 0xf16 367 #define AUDIOHDC_VERB_SET_GPIO_MASK 0x716 368 369 #define AUDIOHDC_VERB_GET_UNSOL_ENABLE_MASK 0xf19 370 #define AUDIOHDC_VERB_SET_UNSOL_ENABLE_MASK 0x719 371 372 #define AUDIOHDC_VERB_GET_GPIO_DIREC 0xf17 373 #define AUDIOHDC_VERB_SET_GPIO_DIREC 0x717 374 375 #define AUDIOHDC_VERB_GET_GPIO_DATA 0xf15 376 #define AUDIOHDC_VERB_SET_GPIO_DATA 0x715 377 378 #define AUDIOHDC_VERB_GET_GPIO_STCK 0xf1a 379 #define AUDIOHDC_VERB_SET_GPIO_STCK 0x71a 380 381 #define AUDIOHDC_GPIO_ENABLE 0xff 382 #define AUDIOHDC_GPIO_DIRECT 0xf1 383 384 #define AUDIOHDC_GPIO_DATA_CTRL 0xff 385 #define AUDIOHDC_GPIO_STCK_CTRL 0xff 386 /* 387 * 4-bit verbs 388 */ 389 #define AUDIOHDC_VERB_GET_CONV_FMT 0xa 390 #define AUDIOHDC_VERB_SET_CONV_FMT 0x2 391 392 #define AUDIOHDC_VERB_GET_AMP_MUTE 0xb 393 #define AUDIOHDC_VERB_SET_AMP_MUTE 0x3 394 #define AUDIOHDC_VERB_SET_BEEP_VOL 0x3A0 395 396 /* 397 * parameters of nodes 398 */ 399 #define AUDIOHDC_PAR_VENDOR_ID 0x00 400 #define AUDIOHDC_PAR_SUBSYS_ID 0x01 401 #define AUDIOHDC_PAR_REV_ID 0x02 402 #define AUDIOHDC_PAR_NODE_COUNT 0x04 403 #define AUDIOHDC_PAR_FUNCTION_TYPE 0x05 404 #define AUDIOHDC_PAR_AUDIO_FG_CAP 0x08 405 #define AUDIOHDC_PAR_AUDIO_WID_CAP 0x09 406 #define AUDIOHDC_PAR_PCM 0x0a 407 #define AUDIOHDC_PAR_STREAM 0x0b 408 #define AUDIOHDC_PAR_PIN_CAP 0x0c 409 #define AUDIOHDC_PAR_INAMP_CAP 0x0d 410 #define AUDIOHDC_PAR_CONNLIST_LEN 0x0e 411 #define AUDIOHDC_PAR_POWER_STATE 0x0f 412 #define AUDIOHDC_PAR_PROC_CAP 0x10 413 #define AUDIOHDC_PAR_GPIO_CAP 0x11 414 #define AUDIOHDC_PAR_OUTAMP_CAP 0x12 415 416 /* 417 * bits for get/set amplifier gain/mute 418 */ 419 #define AUDIOHDC_AMP_SET_OUTPUT 0x8000 420 #define AUDIOHDC_AMP_SET_INPUT 0x4000 421 #define AUDIOHDC_AMP_SET_LEFT 0x2000 422 #define AUDIOHDC_AMP_SET_RIGHT 0x1000 423 #define AUDIOHDC_AMP_SET_MUTE 0x0080 424 #define AUDIOHDC_AMP_SET_LNR 0x3000 425 #define AUDIOHDC_AMP_SET_LR_INPUT 0x7000 426 #define AUDIOHDC_AMP_SET_LR_OUTPUT 0xb000 427 #define AUDIOHDC_AMP_SET_INDEX_OFFSET 8 428 #define AUDIOHDC_AMP_SET_GAIN_MASK 0x007f 429 #define AUDIOHDC_GAIN_MAX 0x7f 430 #define AUDIOHDC_GAIN_BITS 7 431 #define AUDIOHDC_GAIN_DEFAULT 0x0f 432 433 #define AUDIOHDC_AMP_GET_OUTPUT 0x8000 434 #define AUDIOHDC_AMP_GET_INPUT 0x0000 435 436 /* value used to set max volume for left output */ 437 #define AUDIOHDC_AMP_LOUT_MAX \ 438 (AUDIOHDC_AMP_SET_OUTPUT | \ 439 AUDIOHDC_AMP_SET_LEFT | \ 440 AUDIOHDC_GAIN_MAX) 441 442 /* value used to set max volume for right output */ 443 #define AUDIOHDC_AMP_ROUT_MAX \ 444 (AUDIOHDC_AMP_SET_OUTPUT | \ 445 AUDIOHDC_AMP_SET_RIGHT | \ 446 AUDIOHDC_GAIN_MAX) 447 448 449 /* 450 * Bits for pin widget control verb 451 */ 452 #define AUDIOHDC_PIN_CONTROL_HP_ENABLE 0x80 453 #define AUDIOHDC_PIN_CONTROL_OUT_ENABLE 0x40 454 #define AUDIOHDC_PIN_CONTROL_IN_ENABLE 0x20 455 456 /* 457 * Bits for Amplifier capabilities 458 */ 459 #define AUDIOHDC_AMP_CAP_MUTE_CAP 0x80000000 460 #define AUDIOHDC_AMP_CAP_STEP_SIZE 0x007f0000 461 #define AUDIOHDC_AMP_CAP_STEP_NUMS 0x00007f00 462 #define AUDIOHDC_AMP_CAP_0DB_OFFSET 0x0000007f 463 464 465 /* 466 * Bits for Audio Widget Capabilities 467 */ 468 #define AUDIOHD_WIDCAP_STEREO 0x00000001 469 #define AUDIOHD_WIDCAP_INAMP 0x00000002 470 #define AUDIOHD_WIDCAP_OUTAMP 0x00000004 471 #define AUDIOHD_WIDCAP_AMP_OVRIDE 0x00000008 472 #define AUDIOHD_WIDCAP_FMT_OVRIDE 0x00000010 473 #define AUDIOHD_WIDCAP_STRIP 0x00000020 474 #define AUDIOHD_WIDCAP_PROC_WID 0x00000040 475 #define AUDIOHD_WIDCAP_UNSOL 0x00000080 476 #define AUDIOHD_WIDCAP_CONNLIST 0x00000100 477 #define AUDIOHD_WIDCAP_DIGIT 0x00000200 478 #define AUDIOHD_WIDCAP_PWRCTRL 0x00000400 479 #define AUDIOHD_WIDCAP_LRSWAP 0x00000800 480 #define AUDIOHD_WIDCAP_TYPE 0x00f00000 481 #define AUDIOHD_WIDCAP_TO_WIDTYPE(wcap) \ 482 ((wcap & AUDIOHD_WIDCAP_TYPE) >> 20) 483 484 485 #define AUDIOHD_CODEC_FAILURE (uint32_t)(-1) 486 487 /* 488 * buffer descriptor list entry of stream descriptor 489 */ 490 typedef struct { 491 uint64_t sbde_addr; 492 uint32_t sbde_len; 493 uint32_t 494 sbde_ioc: 1, 495 reserved: 31; 496 }sd_bdle_t; 497 498 499 #define AUDIOHD_PLAY_STARTED 0x00000001 500 #define AUDIOHD_PLAY_EMPTY 0x00000002 501 #define AUDIOHD_PLAY_PAUSED 0x00000004 502 #define AUDIOHD_RECORD_STARTED 0x00000008 503 504 enum audiohda_widget_type { 505 WTYPE_AUDIO_OUT = 0, 506 WTYPE_AUDIO_IN, 507 WTYPE_AUDIO_MIX, 508 WTYPE_AUDIO_SEL, 509 WTYPE_PIN, 510 WTYPE_POWER, 511 WTYPE_VOL_KNOB, 512 WTYPE_BEEP, 513 WTYPE_VENDOR = 0xf 514 }; 515 516 enum audiohda_device_type { 517 DTYPE_LINEOUT = 0, 518 DTYPE_SPEAKER, 519 DTYPE_HP_OUT, 520 DTYPE_CD, 521 DTYPE_SPDIF_OUT, 522 DTYPE_DIGIT_OUT, 523 DTYPE_MODEM_SIDE, 524 DTYPE_MODEM_HNAD_SIDE, 525 DTYPE_LINE_IN, 526 DTYPE_AUX, 527 DTYPE_MIC_IN, 528 DTYPE_TEL, 529 DTYPE_SPDIF_IN, 530 DTYPE_DIGIT_IN, 531 DTYPE_OTHER = 0x0f, 532 }; 533 534 enum audiohd_pin_color { 535 AUDIOHD_PIN_UNKNOWN = 0, 536 AUDIOHD_PIN_BLACK, 537 AUDIOHD_PIN_GREY, 538 AUDIOHD_PIN_BLUE, 539 AUDIOHD_PIN_GREEN, 540 AUDIOHD_PIN_RED, 541 AUDIOHD_PIN_ORANGE, 542 AUDIOHD_PIN_YELLOW, 543 AUDIOHD_PIN_PURPLE, 544 AUDIOHD_PIN_PINK, 545 AUDIOHD_PIN_WHITE = 0xe, 546 AUDIOHD_PIN_OTHER = 0xf, 547 }; 548 549 /* values for audiohd_widget.path_flags */ 550 #define AUDIOHD_PATH_DAC (1 << 0) 551 #define AUDIOHD_PATH_ADC (1 << 1) 552 #define AUDIOHD_PATH_MON (1 << 2) 553 #define AUDIOHD_PATH_NOMON (1 << 3) 554 #define AUDIOHD_PATH_BEEP (1 << 4) 555 556 typedef struct audiohd_path audiohd_path_t; 557 typedef struct audiohd_widget audiohd_widget_t; 558 typedef struct audiohd_state audiohd_state_t; 559 typedef struct audiohd_codec_info audiohd_codec_info_t; 560 typedef struct audiohd_pin audiohd_pin_t; 561 typedef struct hda_codec hda_codec_t; 562 typedef uint32_t wid_t; /* id of widget */ 563 typedef struct audiohd_entry_prop audiohd_entry_prop_t; 564 typedef enum audiohda_device_type audiohda_device_type_t; 565 typedef enum audiohd_pin_color audiohd_pin_color_t; 566 567 #define AUDIOHD_MAX_WIDGET 128 568 #define AUDIOHD_MAX_CONN 16 569 #define AUDIOHD_MAX_PINS 16 570 #define AUDIOHD_MAX_DEPTH 8 571 572 struct audiohd_entry_prop { 573 uint32_t conn_len; 574 uint32_t mask_range; 575 uint32_t mask_wid; 576 wid_t input_wid; 577 int conns_per_entry; 578 int bits_per_conn; 579 }; 580 struct audiohd_widget { 581 wid_t wid_wid; 582 hda_codec_t *codec; 583 enum audiohda_widget_type type; 584 585 uint32_t widget_cap; 586 uint32_t pcm_format; 587 uint32_t inamp_cap; 588 uint32_t outamp_cap; 589 590 uint32_t path_flags; 591 592 int out_weight; 593 int in_weight; 594 int finish; 595 596 /* 597 * wid of possible & selected input connections 598 */ 599 wid_t avail_conn[AUDIOHD_MAX_CONN]; 600 wid_t selconn; 601 /* 602 * for monitor path 603 */ 604 wid_t selmon[AUDIOHD_MAX_CONN]; 605 uint16_t used; 606 607 /* 608 * available (input) connections. 0 means this widget 609 * has fixed connection 610 */ 611 int nconns; 612 613 /* 614 * pointer to struct depending on widget type: 615 * 1. DAC audiohd_ostream_t 616 * 2. ADC audiohd_istream_t 617 * 3. PIN audiohd_pin_t 618 */ 619 void *priv; 620 }; 621 622 #define AUDIOHD_FLAG_LINEOUT (1 << 0) 623 #define AUDIOHD_FLAG_SPEAKER (1 << 1) 624 #define AUDIOHD_FLAG_HP (1 << 2) 625 #define AUDIOHD_FLAG_MONO (1 << 3) 626 627 #define AUDIOHD_MAX_MIXER 5 628 #define AUDIOHD_MAX_PIN 4 629 630 #define PORT_DAC 0 631 #define PORT_ADC 1 632 #define PORT_MAX 2 633 typedef enum { 634 PLAY = 0, 635 RECORD = 1, 636 BEEP = 2, 637 } path_type_t; 638 639 struct audiohd_path { 640 wid_t adda_wid; 641 wid_t beep_wid; 642 643 wid_t pin_wid[AUDIOHD_MAX_PINS]; 644 int sum_selconn[AUDIOHD_MAX_PINS]; 645 int mon_wid[AUDIOHD_MAX_PIN][AUDIOHD_MAX_MIXER]; 646 int pin_nums; 647 int maxmixer[AUDIOHD_MAX_PINS]; 648 649 path_type_t path_type; 650 651 wid_t mute_wid; 652 int mute_dir; 653 wid_t gain_wid; 654 int gain_dir; 655 uint32_t gain_bits; 656 657 uint32_t pin_outputs; 658 uint8_t tag; 659 660 hda_codec_t *codec; 661 662 wid_t sum_wid; 663 664 audiohd_state_t *statep; 665 }; 666 667 typedef struct audiohd_port 668 { 669 uint8_t nchan; 670 int index; 671 uint16_t regoff; 672 673 unsigned nframes; 674 size_t bufsize; 675 size_t fragsize; 676 uint64_t count; 677 int curpos; 678 679 uint_t format; 680 unsigned sync_dir; 681 682 ddi_dma_handle_t samp_dmah; 683 ddi_acc_handle_t samp_acch; 684 caddr_t samp_kaddr; 685 uint64_t samp_paddr; 686 687 ddi_dma_handle_t bdl_dmah; 688 ddi_acc_handle_t bdl_acch; 689 size_t bdl_size; 690 caddr_t bdl_kaddr; 691 uint64_t bdl_paddr; 692 693 audio_engine_t *engine; 694 audiohd_state_t *statep; 695 }audiohd_port_t; 696 697 enum { 698 CTL_VOLUME = 0, 699 CTL_FRONT, 700 CTL_SPEAKER, 701 CTL_HEADPHONE, 702 CTL_REAR, 703 CTL_CENTER, 704 CTL_SURROUND, 705 CTL_LFE, 706 CTL_IGAIN, 707 CTL_LINEIN, 708 CTL_MIC, 709 CTL_CD, 710 CTL_MONGAIN, 711 CTL_MONSRC, 712 CTL_RECSRC, 713 CTL_BEEP, 714 715 /* this one must be last */ 716 CTL_MAX 717 }; 718 719 typedef struct audiohd_ctrl 720 { 721 audiohd_state_t *statep; 722 audio_ctrl_t *ctrl; 723 int num; 724 uint64_t val; 725 } audiohd_ctrl_t; 726 727 struct audiohd_pin { 728 audiohd_pin_t *next; 729 wid_t wid; 730 wid_t mute_wid; /* node used to mute this pin */ 731 int mute_dir; /* 1: input, 2: output */ 732 wid_t gain_wid; /* node for gain control */ 733 int gain_dir; /* _OUTPUT/_INPUT */ 734 uint32_t gain_bits; 735 736 uint8_t vrefvalue; /* value of VRef */ 737 738 uint32_t cap; 739 uint32_t config; 740 uint32_t ctrl; 741 uint32_t assoc; 742 uint32_t seq; 743 wid_t adc_dac_wid; /* AD/DA wid which can route to this pin */ 744 wid_t beep_wid; 745 int no_phys_conn; 746 enum audiohda_device_type device; 747 748 /* 749 * mg_dir, mg_gain, mg_wid are used to store the monitor gain control 750 * widget wid. 751 */ 752 int mg_dir[AUDIOHD_MAX_CONN]; 753 int mg_gain[AUDIOHD_MAX_CONN]; 754 int mg_wid[AUDIOHD_MAX_CONN]; 755 int num; 756 int finish; 757 758 }; 759 760 typedef struct { 761 ddi_dma_handle_t ad_dmahdl; 762 ddi_acc_handle_t ad_acchdl; 763 caddr_t ad_vaddr; /* virtual addr */ 764 uint64_t ad_paddr; /* physical addr */ 765 size_t ad_req_sz; /* required size of memory */ 766 size_t ad_real_sz; /* real size of memory */ 767 } audiohd_dma_t; 768 769 struct hda_codec { 770 uint8_t index; /* codec address */ 771 uint32_t vid; /* vendor id and device id */ 772 uint32_t revid; /* revision id */ 773 wid_t wid_afg; /* id of AFG */ 774 wid_t first_wid; /* wid of 1st subnode of AFG */ 775 wid_t last_wid; /* wid of the last subnode of AFG */ 776 int nnodes; /* # of subnodes of AFG */ 777 uint8_t nistream; 778 779 uint32_t outamp_cap; 780 uint32_t inamp_cap; 781 uint32_t stream_format; 782 uint32_t pcm_format; 783 784 audiohd_state_t *soft_statep; 785 audiohd_codec_info_t *codec_info; 786 787 /* use wid as index to the array of widget pointers */ 788 audiohd_widget_t *widget[AUDIOHD_MAX_WIDGET]; 789 790 audiohd_port_t *port[AUDIOHD_PORT_MAX]; 791 uint8_t portnum; 792 audiohd_pin_t *first_pin; 793 }; 794 795 #define AUDIOHD_MAX_ASSOC 15 796 struct audiohd_state { 797 dev_info_t *hda_dip; 798 kstat_t *hda_ksp; 799 kmutex_t hda_mutex; 800 uint32_t hda_flags; 801 802 caddr_t hda_reg_base; 803 ddi_acc_handle_t hda_pci_handle; 804 ddi_acc_handle_t hda_reg_handle; 805 806 audiohd_dma_t hda_dma_corb; 807 audiohd_dma_t hda_dma_rirb; 808 809 uint8_t hda_rirb_rp; /* read pointer for rirb */ 810 uint16_t hda_codec_mask; 811 812 audio_dev_t *adev; 813 uint32_t devid; 814 815 int hda_input_streams; /* # of input stream */ 816 int hda_output_streams; /* # of output stream */ 817 int hda_streams_nums; /* # of stream */ 818 819 uint_t hda_play_regbase; 820 uint_t hda_record_regbase; 821 822 uint_t hda_play_stag; /* tag of playback stream */ 823 uint_t hda_record_stag; /* tag of record stream */ 824 uint_t hda_play_lgain; /* left gain for playback */ 825 uint_t hda_play_rgain; /* right gain for playback */ 826 827 /* 828 * Now, for the time being, we add some fields 829 * for parsing codec topology 830 */ 831 hda_codec_t *codec[AUDIOHD_CODEC_MAX]; 832 /* 833 * Suspend/Resume used fields 834 */ 835 boolean_t suspended; 836 837 audiohd_path_t *path[AUDIOHD_PORT_MAX]; 838 uint8_t pathnum; 839 audiohd_port_t *port[PORT_MAX]; 840 uint8_t pchan; 841 uint8_t rchan; 842 843 uint64_t inmask; 844 845 uint_t hda_out_ports; 846 uint_t in_port; 847 848 /* 849 * Controls 850 */ 851 audiohd_ctrl_t ctrls[CTL_MAX]; 852 boolean_t monitor_unsupported; 853 854 /* for multichannel */ 855 uint8_t chann[AUDIOHD_MAX_ASSOC]; 856 uint8_t assoc; 857 858 }; 859 860 struct audiohd_codec_info { 861 uint32_t devid; 862 const char *buf; 863 uint32_t flags; 864 }; 865 866 /* 867 * Operation for high definition audio control system bus 868 * interface registers 869 */ 870 #define AUDIOHD_REG_GET8(reg) \ 871 ddi_get8(statep->hda_reg_handle, \ 872 (void *)((char *)statep->hda_reg_base + (reg))) 873 874 #define AUDIOHD_REG_GET16(reg) \ 875 ddi_get16(statep->hda_reg_handle, \ 876 (void *)((char *)statep->hda_reg_base + (reg))) 877 878 #define AUDIOHD_REG_GET32(reg) \ 879 ddi_get32(statep->hda_reg_handle, \ 880 (void *)((char *)statep->hda_reg_base + (reg))) 881 882 #define AUDIOHD_REG_GET64(reg) \ 883 ddi_get64(statep->hda_reg_handle, \ 884 (void *)((char *)statep->hda_reg_base + (reg))) 885 886 #define AUDIOHD_REG_SET8(reg, val) \ 887 ddi_put8(statep->hda_reg_handle, \ 888 (void *)((char *)statep->hda_reg_base + (reg)), (val)) 889 890 #define AUDIOHD_REG_SET16(reg, val) \ 891 ddi_put16(statep->hda_reg_handle, \ 892 (void *)((char *)statep->hda_reg_base + (reg)), (val)) 893 894 #define AUDIOHD_REG_SET32(reg, val) \ 895 ddi_put32(statep->hda_reg_handle, \ 896 (void *)((char *)statep->hda_reg_base + (reg)), (val)) 897 898 #define AUDIOHD_REG_SET64(reg, val) \ 899 ddi_put64(statep->hda_reg_handle, \ 900 (void *)((char *)statep->hda_reg_base + (reg)), (val)) 901 902 903 /* 904 * enable a pin widget to input 905 */ 906 #define AUDIOHD_ENABLE_PIN_IN(statep, caddr, wid) \ 907 { \ 908 (void) audioha_codec_verb_get(statep, caddr, wid, \ 909 AUDIOHDC_VERB_SET_PIN_CTRL, AUDIOHDC_PIN_CONTROL_IN_ENABLE | 4); \ 910 } 911 912 913 /* 914 * disable input pin 915 */ 916 #define AUDIOHD_DISABLE_PIN_IN(statep, caddr, wid) \ 917 { \ 918 uint32_t lTmp; \ 919 \ 920 lTmp = audioha_codec_verb_get(statep, caddr, wid, \ 921 AUDIOHDC_VERB_GET_PIN_CTRL, 0); \ 922 if (lTmp == AUDIOHD_CODEC_FAILURE) \ 923 return (DDI_FAILURE); \ 924 lTmp = audioha_codec_verb_get(statep, caddr, wid, \ 925 AUDIOHDC_VERB_SET_PIN_CTRL, \ 926 (lTmp & ~AUDIOHDC_PIN_CONTROL_IN_ENABLE)); \ 927 if (lTmp == AUDIOHD_CODEC_FAILURE) \ 928 return (DDI_FAILURE); \ 929 } 930 931 /* 932 * unmute an output pin 933 */ 934 #define AUDIOHD_NODE_UNMUTE_OUT(statep, caddr, wid) \ 935 { \ 936 if (audioha_codec_4bit_verb_get(statep, \ 937 caddr, wid, AUDIOHDC_VERB_SET_AMP_MUTE, \ 938 AUDIOHDC_AMP_SET_LR_OUTPUT | AUDIOHDC_GAIN_MAX) == \ 939 AUDIOHD_CODEC_FAILURE) \ 940 return (DDI_FAILURE); \ 941 } 942 943 /* 944 * check volume adjust value of 2 channels control 945 */ 946 #define AUDIOHD_CHECK_2CHANNELS_VOLUME(value) \ 947 { \ 948 if ((value) & ~0xffff) \ 949 return (EINVAL); \ 950 if ((((value) & 0xff00) >> 8) > 100 || \ 951 ((value) & 0xff) > 100) \ 952 return (EINVAL); \ 953 } 954 955 /* 956 * check volume adjust value of mono channel control 957 */ 958 #define AUDIOHD_CHECK_CHANNEL_VOLUME(value) \ 959 { \ 960 if ((value) & ~0xff) \ 961 return (EINVAL); \ 962 if (((value) & 0xff) > 100) \ 963 return (EINVAL); \ 964 } 965 966 #ifdef __cplusplus 967 } 968 #endif 969 970 #endif /* _SYS_AUDIOHD_IMPL_H_ */ 971