1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 /* 26 * Purpose: Definitions for the Creative/Ensoniq AudioPCI97 driver. 27 */ 28 /* 29 * This file is part of Open Sound System 30 * 31 * Copyright (C) 4Front Technologies 1996-2008. 32 * 33 * This software is released under CDDL 1.0 source license. 34 * See the COPYING file included in the main directory of this source 35 * distribution for the license terms and conditions. 36 */ 37 38 #ifndef _AUDIOENS_H 39 #define _AUDIOENS_H 40 41 /* CONCERT PCI-SIG defines */ 42 #define CONC_PCI_VENDID 0x1274U 43 #define CONC_PCI_DEVID 0x1371U 44 45 /* Concert97 direct register offset defines */ 46 #define CONC_bDEVCTL_OFF 0x00 /* Device control/enable */ 47 #define CONC_bMISCCTL_OFF 0x01 /* Miscellaneous control */ 48 #define CONC_bGPIO_OFF 0x02 /* General purpose I/O control */ 49 #define CONC_bJOYCTL_OFF 0x03 /* Joystick control (decode) */ 50 #define CONC_dSTATUS_OFF 0x04 /* long status register */ 51 #define CONC_bINTSUMM_OFF 0x07 /* Interrupt summary status */ 52 #define CONC_bUARTDATA_OFF 0x08 /* UART data R/W - read clears RX int */ 53 #define CONC_bUARTCSTAT_OFF 0x09 /* UART control and status */ 54 #define CONC_bUARTTEST_OFF 0x0a /* UART test control reg */ 55 #define CONC_bMEMPAGE_OFF 0x0c /* Memory page select */ 56 #define CONC_dSRCIO_OFF 0x10 /* I/O ctl/stat/data for SRC RAM */ 57 #define CONC_dCODECCTL_OFF 0x14 /* CODEC control - dword read/write */ 58 #define CONC_wNMISTAT_OFF 0x18 /* Legacy NMI status */ 59 #define CONC_bNMIENA_OFF 0x1a /* Legacy NMI enable */ 60 #define CONC_bNMICTL_OFF 0x1b /* Legacy control */ 61 #define CONC_dSPDIF_OFF 0x1c /* SPDIF status control */ 62 #define CONC_bSERFMT_OFF 0x20 /* Serial device control */ 63 #define CONC_bSERCTL_OFF 0x21 /* Serial device format */ 64 #define CONC_bSKIPC_OFF 0x22 /* DAC skip count reg */ 65 #define CONC_wDAC1IC_OFF 0x24 /* Synth int count in sample frames */ 66 #define CONC_wDAC1CIC_OFF 0x26 /* Synth current int count */ 67 #define CONC_wDAC2IC_OFF 0x28 /* DAC int count in sample frames */ 68 #define CONC_wDAC2CIC_OFF 0x2a /* DAC current int count */ 69 #define CONC_wADCIC_OFF 0x2c /* ADC int count in sample frames */ 70 #define CONC_wADCCIC_OFF 0x2e /* ADC current int count */ 71 #define CONC_MEMBASE_OFF 0x30 /* Memory window base - 16 byte window */ 72 73 /* Concert memory page-banked register offset defines */ 74 #define CONC_dDAC1PADDR_OFF 0x30 /* Synth host frame PCI phys addr */ 75 #define CONC_wDAC1FC_OFF 0x34 /* Synth host frame count in DWORDS */ 76 #define CONC_wDAC1CFC_OFF 0x36 /* Synth host current frame count */ 77 #define CONC_dDAC2PADDR_OFF 0x38 /* DAC host frame PCI phys addr */ 78 #define CONC_wDAC2FC_OFF 0x3c /* DAC host frame count in DWORDS */ 79 #define CONC_wDAC2CFC_OFF 0x3e /* DAC host current frame count */ 80 #define CONC_dADCPADDR_OFF 0x30 /* ADC host frame PCI phys addr */ 81 #define CONC_wADCFC_OFF 0x34 /* ADC host frame count in DWORDS */ 82 #define CONC_wADCCFC_OFF 0x36 /* ADC host current frame count */ 83 84 /* Concert memory page number defines */ 85 #define CONC_DAC1RAM_PAGE 0x00 /* Synth host/serial I/F RAM */ 86 #define CONC_DAC2RAM_PAGE 0x04 /* DAC host/serial I/F RAM */ 87 #define CONC_ADCRAM_PAGE 0x08 /* ADC host/serial I/F RAM */ 88 #define CONC_DAC1CTL_PAGE 0x0c /* Page bank for synth host control */ 89 #define CONC_DAC2CTL_PAGE 0x0c /* Page bank for DAC host control */ 90 #define CONC_ADCCTL_PAGE 0x0d /* Page bank for ADC host control */ 91 #define CONC_FIFO0_PAGE 0x0e /* page 0 of UART "FIFO" (rx stash) */ 92 #define CONC_FIFO1_PAGE 0x0f /* page 1 of UART "FIFO" (rx stash) */ 93 94 /* SPDIF defines - only newer chips */ 95 #define CONC_SPDIF_CLKACCURACY 0x00000000U /* normal mode */ 96 #define CONC_SPDIF_SR48KHZ 0x02000000U /* 48KHZ clock, must be set */ 97 #define CONC_SPDIF_CHNO_MASK 0x00f00000U /* channel number */ 98 #define CONC_SPDIF_SRCNO_MASK 0x000f0000U /* source number */ 99 #define CONC_SPDIF_L 0x00008000U /* 0 = commercial original */ 100 #define CONC_SPDIF_CATCODE 0x00007f00U /* category code */ 101 #define CONC_SPDIF_EMPHASIS 0x00000008U /* 2 ch, 50/15 usec preemph */ 102 #define CONC_SPDIF_COPY 0x00000004U /* copy permitted */ 103 #define CONC_SPDIF_AC3 0x00000002U /* data is not pcm (AC3) */ 104 105 /* PCM format defines */ 106 #define CONC_PCM_DAC1_STEREO 0x01 107 #define CONC_PCM_DAC1_16BIT 0x02 108 #define CONC_PCM_DAC2_STEREO 0x04 109 #define CONC_PCM_DAC2_16BIT 0x08 110 #define CONC_PCM_ADC_STEREO 0x10 111 #define CONC_PCM_ADC_16BIT 0x20 112 113 /* Device Control defines */ 114 #define CONC_DEVCTL_PCICLK_DS 0x01 /* PCI Clock Disable */ 115 #define CONC_DEVCTL_XTALCLK_DS 0x02 /* Crystal Clock Disable */ 116 #define CONC_DEVCTL_JSTICK_EN 0x04 /* Joystick Enable */ 117 #define CONC_DEVCTL_UART_EN 0x08 /* UART Enable */ 118 #define CONC_DEVCTL_ADC_EN 0x10 /* ADC Enable (record) */ 119 #define CONC_DEVCTL_DAC2_EN 0x20 /* DAC2 Enable (playback) */ 120 #define CONC_DEVCTL_DAC1_EN 0x40 /* DAC1 Enabale (synth) */ 121 122 /* Misc Control defines */ 123 #define CONC_MISCCTL_PDLEV_D0 0x00 /* These bits reflect the */ 124 #define CONC_MISCCTL_PDLEV_D1 0x01 /* power down state of */ 125 #define CONC_MISCCTL_PDLEV_D2 0x02 /* the part */ 126 #define CONC_MISCCTL_PDLEV_D3 0x03 /* */ 127 #define CONC_MISCCTL_CCBINTRM_EN 0x04 /* CCB module interrupt mask */ 128 129 #define CONC_MISCCTL_SYNC_RES 0x40 /* for AC97 warm reset */ 130 131 /* Serial Control defines */ 132 #define CONC_SERCTL_DAC1IE 0x01 /* playback interrupt enable P1_INT_EN */ 133 #define CONC_SERCTL_DAC2IE 0x02 /* playback interrupt enable P2_INT_EN */ 134 #define CONC_SERCTL_ADCIE 0x04 /* record interrupt enable R1_INT_EN */ 135 #define CONC_SERCTL_DAC1PAUSE 0x08 /* playback pause */ 136 #define CONC_SERCTL_DAC2PAUSE 0x10 /* playback pause */ 137 #define CONC_SERCTL_ADCLOOP 0x80 138 #define CONC_SERCTL_DAC2LOOP 0x40 139 #define CONC_SERCTL_DAC1LOOP 0x20 140 141 /* Interrupt Status defines */ 142 #define CONC_STATUS_ADCINT 0x00000001 /* A/D interrupt pending */ 143 #define CONC_STATUS_DAC2INT 0x00000002 /* DAC2 interrupt pending */ 144 #define CONC_STATUS_DAC1INT 0x00000004 /* DAC1 interrupt pending */ 145 #define CONC_STATUS_UARTINT 0x00000008 /* UART interrupt pending */ 146 #define CONC_STATUS_PENDING 0x80000000 /* any interrupt pending */ 147 #define CONC_STATUS_SPDIF_MASK 0x18000000 148 #define CONC_STATUS_SPDIF_P1P2 0x00000000 149 #define CONC_STATUS_SPDIF_P1 0x08000000 150 #define CONC_STATUS_SPDIF_P2 0x10000000 151 #define CONC_STATUS_SPDIF_REC 0x18000000 152 #define CONC_STATUS_ECHO 0x04000000 153 #define CONC_STATUS_SPKR_MASK 0x03000000 154 #define CONC_STATUS_SPKR_2CH 0x00000000 155 #define CONC_STATUS_SPKR_4CH 0x01000000 156 #define CONC_STATUS_SPKR_P1 0x02000000 157 #define CONC_STATUS_SPKR_P2 0x03000000 158 #define CONC_STATUS_EN_SPDIF 0x00040000 159 160 /* JOYCTL register defines */ 161 #define CONC_JOYCTL_200 0x00 162 #define CONC_JOYCTL_208 0x01 163 #define CONC_JOYCTL_210 0x02 164 #define CONC_JOYCTL_218 0x03 165 #define CONC_JOYCTL_SPDIFEN_B 0x04 166 #define CONC_JOYCTL_RECEN_B 0x08 167 168 /* UARTCSTAT register masks */ 169 #define CONC_UART_RXRDY 0x01 170 #define CONC_UART_TXRDY 0x02 171 #define CONC_UART_TXINT 0x04 172 #define CONC_UART_RXINT 0x80 173 174 #define CONC_UART_CTL 0x03 175 #define CONC_UART_TXINTEN 0x20 176 #define CONC_UART_RXINTEN 0x80 177 178 /* defines for the CONCERT97 Sample Rate Converters */ 179 180 /* register/base equates for the SRC RAM */ 181 #define SRC_DAC1_FIFO 0x00 182 #define SRC_DAC2_FIFO 0x20 183 #define SRC_ADC_FIFO 0x40 184 #define SRC_ADC_VOL_L 0x6c 185 #define SRC_ADC_VOL_R 0x6d 186 #define SRC_DAC1_BASE 0x70 187 #define SRC_DAC2_BASE 0x74 188 #define SRC_ADC_BASE 0x78 189 #define SRC_DAC1_VOL_L 0x7c 190 #define SRC_DAC1_VOL_R 0x7d 191 #define SRC_DAC2_VOL_L 0x7e 192 #define SRC_DAC2_VOL_R 0x7f 193 194 #define SRC_TRUNC_N_OFF 0x00 195 #define SRC_INT_REGS_OFF 0x01 196 #define SRC_ACCUM_FRAC_OFF 0x02 197 #define SRC_VFREQ_FRAC_OFF 0x03 198 199 200 /* miscellaneous control defines */ 201 #define SRC_IOPOLL_COUNT 0x20000UL 202 #define SRC_WENABLE (1UL << 24) 203 #define SRC_BUSY (1UL << 23) 204 #define SRC_DISABLE (1UL << 22) 205 #define SRC_DAC1FREEZE (1UL << 21) 206 #define SRC_DAC2FREEZE (1UL << 20) 207 #define SRC_ADCFREEZE (1UL << 19) 208 #define SRC_CTLMASK 0x00780000UL 209 210 #endif /* _AUDIOENS_H */ 211