1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 /* 26 * Purpose: Creative/Ensoniq AudioPCI97 driver (ES1371/ES1373) 27 * 28 * This driver is used with the original Ensoniq AudioPCI97 card and many 29 * PCI based Sound Blaster cards by Creative Technologies. For example 30 * Sound Blaster PCI128 and Creative/Ectiva EV1938. 31 */ 32 33 /* 34 * This file is part of Open Sound System 35 * 36 * Copyright (C) 4Front Technologies 1996-2008. 37 * 38 * This software is released under CDDL 1.0 source license. 39 * See the COPYING file included in the main directory of this source 40 * distribution for the license terms and conditions. 41 */ 42 43 #include <sys/audio/audio_driver.h> 44 #include <sys/audio/ac97.h> 45 #include <sys/note.h> 46 #include <sys/pci.h> 47 #include "audioens.h" 48 49 /* 50 * Set the latency to 32, 64, 96, 128 clocks - some APCI97 devices exhibit 51 * garbled audio in some cases and setting the latency to higer values fixes it 52 * Values: 32, 64, 96, 128 - Default: 64 (or defined by bios) 53 */ 54 int audioens_latency = 0; 55 56 /* 57 * Enable SPDIF port on SoundBlaster 128D or Sound Blaster Digital-4.1 models 58 * Values: 1=Enable 0=Disable Default: 0 59 */ 60 int audioens_spdif = 0; 61 62 /* 63 * Note: Latest devices can support SPDIF with AC3 pass thru. 64 * However, in order to do this, one of the two DMA engines must be 65 * dedicated to this, which would prevent the card from supporting 4 66 * channel audio. For now we don't bother with the AC3 pass through 67 * mode, and instead just focus on 4 channel support. In the future, 68 * this could be selectable via a property. 69 */ 70 71 #define ENSONIQ_VENDOR_ID 0x1274 72 #define CREATIVE_VENDOR_ID 0x1102 73 #define ECTIVA_VENDOR_ID 0x1102 74 #define ENSONIQ_ES1371 0x1371 75 #define ENSONIQ_ES5880 0x8001 76 #define ENSONIQ_ES5880A 0x8002 77 #define ENSONIQ_ES5880B 0x5880 78 #define ECTIVA_ES1938 0x8938 79 80 #define DEFRATE 48000 81 #define DRVNAME "audioens" 82 83 typedef struct audioens_port 84 { 85 /* Audio parameters */ 86 int speed; 87 88 int num; 89 #define PORT_DAC 0 90 #define PORT_ADC 1 91 #define PORT_MAX PORT_ADC 92 93 caddr_t kaddr; 94 uint32_t paddr; 95 ddi_acc_handle_t acch; 96 ddi_dma_handle_t dmah; 97 int nchan; 98 unsigned nframes; 99 unsigned frameno; 100 uint64_t count; 101 102 struct audioens_dev *dev; 103 audio_engine_t *engine; 104 } audioens_port_t; 105 106 typedef struct audioens_dev 107 { 108 audio_dev_t *osdev; 109 kmutex_t mutex; 110 uint16_t devid; 111 uint8_t revision; 112 dev_info_t *dip; 113 114 audioens_port_t port[PORT_MAX + 1]; 115 116 ac97_t *ac97; 117 118 caddr_t regs; 119 ddi_acc_handle_t acch; 120 } audioens_dev_t; 121 122 static ddi_device_acc_attr_t acc_attr = { 123 DDI_DEVICE_ATTR_V0, 124 DDI_STRUCTURE_LE_ACC, 125 DDI_STRICTORDER_ACC 126 }; 127 128 static ddi_device_acc_attr_t buf_attr = { 129 DDI_DEVICE_ATTR_V0, 130 DDI_NEVERSWAP_ACC, 131 DDI_STRICTORDER_ACC 132 }; 133 134 /* 135 * The hardware appears to be able to address up to 16-bits worth of longwords, 136 * giving a total address space of 256K. But we need substantially less. 137 */ 138 #define AUDIOENS_BUF_LEN (16384) 139 140 static ddi_dma_attr_t dma_attr = { 141 DMA_ATTR_VERSION, /* dma_attr_version */ 142 0x0, /* dma_attr_addr_lo */ 143 0xffffffffU, /* dma_attr_addr_hi */ 144 0x3ffff, /* dma_attr_count_max */ 145 0x8, /* dma_attr_align */ 146 0x7f, /* dma_attr_burstsizes */ 147 0x1, /* dma_attr_minxfer */ 148 0x3ffff, /* dma_attr_maxxfer */ 149 0x3ffff, /* dma_attr_seg */ 150 0x1, /* dma_attr_sgllen */ 151 0x1, /* dma_attr_granular */ 152 0 /* dma_attr_flags */ 153 }; 154 155 #define GET8(dev, offset) \ 156 ddi_get8(dev->acch, (uint8_t *)(dev->regs + (offset))) 157 #define GET16(dev, offset) \ 158 ddi_get16(dev->acch, (uint16_t *)(void *)(dev->regs + (offset))) 159 #define GET32(dev, offset) \ 160 ddi_get32(dev->acch, (uint32_t *)(void *)(dev->regs + (offset))) 161 #define PUT8(dev, offset, v) \ 162 ddi_put8(dev->acch, (uint8_t *)(dev->regs + (offset)), v) 163 #define PUT16(dev, offset, v) \ 164 ddi_put16(dev->acch, (uint16_t *)(void *)(dev->regs + (offset)), v) 165 #define PUT32(dev, offset, v) \ 166 ddi_put32(dev->acch, (uint32_t *)(void *)(dev->regs + (offset)), v) 167 168 #define CLR8(dev, offset, v) PUT8(dev, offset, GET8(dev, offset) & ~(v)) 169 #define SET8(dev, offset, v) PUT8(dev, offset, GET8(dev, offset) | (v)) 170 #define CLR32(dev, offset, v) PUT32(dev, offset, GET32(dev, offset) & ~(v)) 171 #define SET32(dev, offset, v) PUT32(dev, offset, GET32(dev, offset) | (v)) 172 173 static void audioens_init_hw(audioens_dev_t *); 174 175 static uint16_t 176 audioens_rd97(void *dev_, uint8_t wAddr) 177 { 178 audioens_dev_t *dev = dev_; 179 int i, dtemp; 180 181 mutex_enter(&dev->mutex); 182 dtemp = GET32(dev, CONC_dCODECCTL_OFF); 183 /* wait for WIP to go away saving the current state for later */ 184 for (i = 0; i < 0x100UL; ++i) { 185 dtemp = GET32(dev, CONC_dCODECCTL_OFF); 186 if ((dtemp & (1UL << 30)) == 0) 187 break; 188 } 189 190 /* write addr w/data=0 and assert read request ... */ 191 PUT32(dev, CONC_dCODECCTL_OFF, ((int)wAddr << 16) | (1UL << 23)); 192 193 /* now wait for the data (RDY) */ 194 for (i = 0; i < 0x100UL; ++i) { 195 dtemp = GET32(dev, CONC_dCODECCTL_OFF); 196 if (dtemp & (1UL << 31)) 197 break; 198 } 199 dtemp = GET32(dev, CONC_dCODECCTL_OFF); 200 mutex_exit(&dev->mutex); 201 202 return (dtemp & 0xffff); 203 } 204 205 static void 206 audioens_wr97(void *dev_, uint8_t wAddr, uint16_t wData) 207 { 208 audioens_dev_t *dev = dev_; 209 int i, dtemp; 210 211 mutex_enter(&dev->mutex); 212 /* wait for WIP to go away */ 213 for (i = 0; i < 0x100UL; ++i) { 214 dtemp = GET32(dev, CONC_dCODECCTL_OFF); 215 if ((dtemp & (1UL << 30)) == 0) 216 break; 217 } 218 219 PUT32(dev, CONC_dCODECCTL_OFF, ((int)wAddr << 16) | wData); 220 221 mutex_exit(&dev->mutex); 222 } 223 224 static unsigned short 225 SRCRegRead(audioens_dev_t *dev, unsigned short reg) 226 { 227 int i, dtemp; 228 229 dtemp = GET32(dev, CONC_dSRCIO_OFF); 230 /* wait for ready */ 231 for (i = 0; i < SRC_IOPOLL_COUNT; ++i) { 232 dtemp = GET32(dev, CONC_dSRCIO_OFF); 233 if ((dtemp & SRC_BUSY) == 0) 234 break; 235 } 236 237 /* assert a read request */ 238 PUT32(dev, CONC_dSRCIO_OFF, (dtemp & SRC_CTLMASK) | ((int)reg << 25)); 239 240 /* now wait for the data */ 241 for (i = 0; i < SRC_IOPOLL_COUNT; ++i) { 242 dtemp = GET32(dev, CONC_dSRCIO_OFF); 243 if ((dtemp & SRC_BUSY) == 0) 244 break; 245 } 246 247 return ((unsigned short) dtemp); 248 } 249 250 static void 251 SRCRegWrite(audioens_dev_t *dev, unsigned short reg, unsigned short val) 252 { 253 int i, dtemp; 254 int writeval; 255 256 dtemp = GET32(dev, CONC_dSRCIO_OFF); 257 /* wait for ready */ 258 for (i = 0; i < SRC_IOPOLL_COUNT; ++i) { 259 dtemp = GET32(dev, CONC_dSRCIO_OFF); 260 if ((dtemp & SRC_BUSY) == 0) 261 break; 262 } 263 264 /* assert the write request */ 265 writeval = (dtemp & SRC_CTLMASK) | SRC_WENABLE | 266 ((int)reg << 25) | val; 267 PUT32(dev, CONC_dSRCIO_OFF, writeval); 268 } 269 270 static void 271 SRCSetRate(audioens_dev_t *dev, unsigned char base, unsigned short rate) 272 { 273 int i, freq, dtemp; 274 unsigned short N, truncM, truncStart; 275 276 if (base != SRC_ADC_BASE) { 277 /* freeze the channel */ 278 dtemp = (base == SRC_DAC1_BASE) ? 279 SRC_DAC1FREEZE : SRC_DAC2FREEZE; 280 for (i = 0; i < SRC_IOPOLL_COUNT; ++i) { 281 if (!(GET32(dev, CONC_dSRCIO_OFF) & SRC_BUSY)) 282 break; 283 } 284 PUT32(dev, CONC_dSRCIO_OFF, 285 (GET32(dev, CONC_dSRCIO_OFF) & SRC_CTLMASK) | dtemp); 286 287 /* calculate new frequency and write it - preserve accum */ 288 freq = ((int)rate << 16) / 3000U; 289 SRCRegWrite(dev, (unsigned short) base + SRC_INT_REGS_OFF, 290 (SRCRegRead(dev, (unsigned short) base + SRC_INT_REGS_OFF) 291 & 0x00ffU) | ((unsigned short) (freq >> 6) & 0xfc00)); 292 SRCRegWrite(dev, (unsigned short) base + SRC_VFREQ_FRAC_OFF, 293 (unsigned short) freq >> 1); 294 295 /* un-freeze the channel */ 296 for (i = 0; i < SRC_IOPOLL_COUNT; ++i) 297 if (!(GET32(dev, CONC_dSRCIO_OFF) & SRC_BUSY)) 298 break; 299 PUT32(dev, CONC_dSRCIO_OFF, 300 (GET32(dev, CONC_dSRCIO_OFF) & SRC_CTLMASK) & ~dtemp); 301 } else { 302 /* derive oversample ratio */ 303 N = rate / 3000U; 304 if (N == 15 || N == 13 || N == 11 || N == 9) 305 --N; 306 307 /* truncate the filter and write n/trunc_start */ 308 truncM = (21 * N - 1) | 1; 309 if (rate >= 24000U) { 310 if (truncM > 239) 311 truncM = 239; 312 truncStart = (239 - truncM) >> 1; 313 314 SRCRegWrite(dev, base + SRC_TRUNC_N_OFF, 315 (truncStart << 9) | (N << 4)); 316 } else { 317 if (truncM > 119) 318 truncM = 119; 319 truncStart = (119 - truncM) >> 1; 320 321 SRCRegWrite(dev, base + SRC_TRUNC_N_OFF, 322 0x8000U | (truncStart << 9) | (N << 4)); 323 } 324 325 /* calculate new frequency and write it - preserve accum */ 326 freq = ((48000UL << 16) / rate) * N; 327 SRCRegWrite(dev, base + SRC_INT_REGS_OFF, 328 (SRCRegRead(dev, (unsigned short) base + SRC_INT_REGS_OFF) 329 & 0x00ff) | ((unsigned short) (freq >> 6) & 0xfc00)); 330 SRCRegWrite(dev, base + SRC_VFREQ_FRAC_OFF, 331 (unsigned short) freq >> 1); 332 333 SRCRegWrite(dev, SRC_ADC_VOL_L, N << 8); 334 SRCRegWrite(dev, SRC_ADC_VOL_R, N << 8); 335 } 336 } 337 338 static void 339 SRCInit(audioens_dev_t *dev) 340 { 341 int i; 342 343 /* Clear all SRC RAM then init - keep SRC disabled until done */ 344 for (i = 0; i < SRC_IOPOLL_COUNT; ++i) { 345 if (!(GET32(dev, CONC_dSRCIO_OFF) & SRC_BUSY)) 346 break; 347 } 348 PUT32(dev, CONC_dSRCIO_OFF, SRC_DISABLE); 349 350 for (i = 0; i < 0x80; ++i) 351 SRCRegWrite(dev, (unsigned short) i, 0U); 352 353 SRCRegWrite(dev, SRC_DAC1_BASE + SRC_TRUNC_N_OFF, 16 << 4); 354 SRCRegWrite(dev, SRC_DAC1_BASE + SRC_INT_REGS_OFF, 16 << 10); 355 SRCRegWrite(dev, SRC_DAC2_BASE + SRC_TRUNC_N_OFF, 16 << 4); 356 SRCRegWrite(dev, SRC_DAC2_BASE + SRC_INT_REGS_OFF, 16 << 10); 357 SRCRegWrite(dev, SRC_DAC1_VOL_L, 1 << 12); 358 SRCRegWrite(dev, SRC_DAC1_VOL_R, 1 << 12); 359 SRCRegWrite(dev, SRC_DAC2_VOL_L, 1 << 12); 360 SRCRegWrite(dev, SRC_DAC2_VOL_R, 1 << 12); 361 SRCRegWrite(dev, SRC_ADC_VOL_L, 1 << 12); 362 SRCRegWrite(dev, SRC_ADC_VOL_R, 1 << 12); 363 364 /* default some rates */ 365 SRCSetRate(dev, SRC_DAC1_BASE, 48000); 366 SRCSetRate(dev, SRC_DAC2_BASE, 48000); 367 SRCSetRate(dev, SRC_ADC_BASE, 48000); 368 369 /* now enable the whole deal */ 370 for (i = 0; i < SRC_IOPOLL_COUNT; ++i) { 371 if (!(GET32(dev, CONC_dSRCIO_OFF) & SRC_BUSY)) 372 break; 373 } 374 PUT32(dev, CONC_dSRCIO_OFF, 0); 375 } 376 377 static void 378 audioens_writemem(audioens_dev_t *dev, uint32_t page, uint32_t offs, 379 uint32_t data) 380 { 381 /* Select memory page */ 382 PUT32(dev, CONC_bMEMPAGE_OFF, page); 383 PUT32(dev, offs, data); 384 } 385 386 static uint32_t 387 audioens_readmem(audioens_dev_t *dev, uint32_t page, uint32_t offs) 388 { 389 PUT32(dev, CONC_bMEMPAGE_OFF, page); /* Select memory page */ 390 return (GET32(dev, offs)); 391 } 392 393 /* 394 * Audio routines 395 */ 396 static int 397 audioens_format(void *arg) 398 { 399 _NOTE(ARGUNUSED(arg)); 400 401 /* hardware can also do AUDIO_FORMAT_U8, but no need for it */ 402 return (AUDIO_FORMAT_S16_LE); 403 } 404 405 static int 406 audioens_channels(void *arg) 407 { 408 audioens_port_t *port = arg; 409 410 return (port->nchan); 411 } 412 413 static int 414 audioens_rate(void *arg) 415 { 416 audioens_port_t *port = arg; 417 418 return (port->speed); 419 } 420 421 static int 422 audioens_open(void *arg, int flag, unsigned *nframes, caddr_t *bufp) 423 { 424 audioens_port_t *port = arg; 425 audioens_dev_t *dev = port->dev; 426 427 _NOTE(ARGUNUSED(flag)); 428 429 mutex_enter(&dev->mutex); 430 431 port->nframes = AUDIOENS_BUF_LEN / (port->nchan * sizeof (int16_t)); 432 port->count = 0; 433 434 *nframes = port->nframes; 435 *bufp = port->kaddr; 436 mutex_exit(&dev->mutex); 437 438 return (0); 439 } 440 441 static int 442 audioens_start(void *arg) 443 { 444 audioens_port_t *port = arg; 445 audioens_dev_t *dev = port->dev; 446 uint32_t tmp; 447 448 mutex_enter(&dev->mutex); 449 450 switch (port->num) { 451 case PORT_DAC: 452 /* Set physical address of the DMA buffer */ 453 audioens_writemem(dev, CONC_DAC1CTL_PAGE, CONC_dDAC1PADDR_OFF, 454 port->paddr); 455 audioens_writemem(dev, CONC_DAC2CTL_PAGE, CONC_dDAC2PADDR_OFF, 456 port->paddr + (port->nframes * sizeof (int16_t) * 2)); 457 458 /* Set DAC rate */ 459 SRCSetRate(dev, SRC_DAC1_BASE, port->speed); 460 SRCSetRate(dev, SRC_DAC2_BASE, port->speed); 461 462 /* Configure the channel setup - SPDIF only uses front */ 463 tmp = GET32(dev, CONC_dSTATUS_OFF); 464 tmp &= ~(CONC_STATUS_SPKR_MASK | CONC_STATUS_SPDIF_MASK); 465 tmp |= CONC_STATUS_SPKR_4CH | CONC_STATUS_SPDIF_P1; 466 PUT32(dev, CONC_dSTATUS_OFF, tmp); 467 468 /* Set format */ 469 PUT8(dev, CONC_bSKIPC_OFF, 0x10); 470 SET8(dev, CONC_bSERFMT_OFF, 471 CONC_PCM_DAC1_16BIT | CONC_PCM_DAC2_16BIT | 472 CONC_PCM_DAC1_STEREO | CONC_PCM_DAC2_STEREO); 473 474 /* Set the frame count */ 475 audioens_writemem(dev, CONC_DAC1CTL_PAGE, CONC_wDAC1FC_OFF, 476 port->nframes - 1); 477 audioens_writemem(dev, CONC_DAC2CTL_PAGE, CONC_wDAC2FC_OFF, 478 port->nframes - 1); 479 480 /* Set # of frames between interrupts */ 481 PUT16(dev, CONC_wDAC1IC_OFF, port->nframes - 1); 482 PUT16(dev, CONC_wDAC2IC_OFF, port->nframes - 1); 483 484 SET8(dev, CONC_bDEVCTL_OFF, 485 CONC_DEVCTL_DAC2_EN | CONC_DEVCTL_DAC1_EN); 486 487 break; 488 489 case PORT_ADC: 490 /* Set physical address of the DMA buffer */ 491 audioens_writemem(dev, CONC_ADCCTL_PAGE, CONC_dADCPADDR_OFF, 492 port->paddr); 493 494 /* Set ADC rate */ 495 SRCSetRate(dev, SRC_ADC_BASE, port->speed); 496 497 /* Set format - for input we only support 16 bit input */ 498 tmp = GET8(dev, CONC_bSERFMT_OFF); 499 tmp |= CONC_PCM_ADC_16BIT; 500 tmp |= CONC_PCM_ADC_STEREO; 501 502 PUT8(dev, CONC_bSKIPC_OFF, 0x10); 503 504 PUT8(dev, CONC_bSERFMT_OFF, tmp); 505 506 /* Set the frame count */ 507 audioens_writemem(dev, CONC_ADCCTL_PAGE, CONC_wADCFC_OFF, 508 port->nframes - 1); 509 510 /* Set # of frames between interrupts */ 511 PUT16(dev, CONC_wADCIC_OFF, port->nframes - 1); 512 513 SET8(dev, CONC_bDEVCTL_OFF, CONC_DEVCTL_ADC_EN); 514 break; 515 } 516 517 port->frameno = 0; 518 mutex_exit(&dev->mutex); 519 520 return (0); 521 } 522 523 static void 524 audioens_stop(void *arg) 525 { 526 audioens_port_t *port = arg; 527 audioens_dev_t *dev = port->dev; 528 529 mutex_enter(&dev->mutex); 530 switch (port->num) { 531 case PORT_DAC: 532 CLR8(dev, CONC_bDEVCTL_OFF, 533 CONC_DEVCTL_DAC2_EN | CONC_DEVCTL_DAC1_EN); 534 break; 535 case PORT_ADC: 536 CLR8(dev, CONC_bDEVCTL_OFF, CONC_DEVCTL_ADC_EN); 537 break; 538 } 539 mutex_exit(&dev->mutex); 540 } 541 542 static uint64_t 543 audioens_count(void *arg) 544 { 545 audioens_port_t *port = arg; 546 audioens_dev_t *dev = port->dev; 547 uint64_t val; 548 uint32_t page, offs; 549 int frameno, n; 550 551 switch (port->num) { 552 case PORT_DAC: 553 page = CONC_DAC1CTL_PAGE; 554 offs = CONC_wDAC1FC_OFF; 555 break; 556 557 case PORT_ADC: 558 page = CONC_ADCCTL_PAGE; 559 offs = CONC_wADCFC_OFF; 560 break; 561 } 562 563 mutex_enter(&dev->mutex); 564 /* 565 * Note that the current frame counter is in the high nybble. 566 */ 567 frameno = audioens_readmem(port->dev, page, offs) >> 16; 568 n = frameno >= port->frameno ? 569 frameno - port->frameno : 570 frameno + port->nframes - port->frameno; 571 port->frameno = frameno; 572 port->count += n; 573 574 val = port->count; 575 mutex_exit(&dev->mutex); 576 577 return (val); 578 } 579 580 static void 581 audioens_close(void *arg) 582 { 583 _NOTE(ARGUNUSED(arg)); 584 } 585 586 static void 587 audioens_sync(void *arg, unsigned nframes) 588 { 589 audioens_port_t *port = arg; 590 591 _NOTE(ARGUNUSED(nframes)); 592 593 if (port->num == PORT_ADC) { 594 (void) ddi_dma_sync(port->dmah, 0, 0, DDI_DMA_SYNC_FORKERNEL); 595 } else { 596 (void) ddi_dma_sync(port->dmah, 0, 0, DDI_DMA_SYNC_FORDEV); 597 } 598 } 599 600 static void 601 audioens_chinfo(void *arg, int chan, unsigned *offset, unsigned *incr) 602 { 603 audioens_port_t *port = arg; 604 605 if ((port->num == PORT_DAC) && (chan >= 2)) { 606 *offset = (port->nframes * 2) + (chan % 2); 607 *incr = 2; 608 } else { 609 *offset = chan; 610 *incr = 2; 611 } 612 } 613 614 audio_engine_ops_t audioens_engine_ops = { 615 AUDIO_ENGINE_VERSION, /* version number */ 616 audioens_open, 617 audioens_close, 618 audioens_start, 619 audioens_stop, 620 audioens_count, 621 audioens_format, 622 audioens_channels, 623 audioens_rate, 624 audioens_sync, 625 NULL, 626 audioens_chinfo, 627 NULL, 628 }; 629 630 void 631 audioens_init_hw(audioens_dev_t *dev) 632 { 633 int tmp; 634 635 if ((dev->devid == ENSONIQ_ES5880) || 636 (dev->devid == ENSONIQ_ES5880A) || 637 (dev->devid == ENSONIQ_ES5880B) || 638 (dev->devid == 0x1371 && dev->revision == 7) || 639 (dev->devid == 0x1371 && dev->revision >= 9)) { 640 641 /* Have a ES5880 so enable the codec manually */ 642 tmp = GET8(dev, CONC_bINTSUMM_OFF) & 0xff; 643 tmp |= 0x20; 644 PUT8(dev, CONC_bINTSUMM_OFF, tmp); 645 for (int i = 0; i < 2000; i++) 646 drv_usecwait(10); 647 } 648 649 SRCInit(dev); 650 651 /* 652 * Turn on CODEC (UART and joystick left disabled) 653 */ 654 tmp = GET32(dev, CONC_bDEVCTL_OFF) & 0xff; 655 tmp &= ~(CONC_DEVCTL_PCICLK_DS | CONC_DEVCTL_XTALCLK_DS); 656 PUT8(dev, CONC_bDEVCTL_OFF, tmp); 657 PUT8(dev, CONC_bUARTCSTAT_OFF, 0x00); 658 659 /* Perform AC97 codec warm reset */ 660 tmp = GET8(dev, CONC_bMISCCTL_OFF) & 0xff; 661 PUT8(dev, CONC_bMISCCTL_OFF, tmp | CONC_MISCCTL_SYNC_RES); 662 drv_usecwait(200); 663 PUT8(dev, CONC_bMISCCTL_OFF, tmp); 664 drv_usecwait(200); 665 666 if (dev->revision >= 4) { 667 /* XXX: enable SPDIF - PCM only for now */ 668 if (audioens_spdif) { 669 /* enable SPDIF */ 670 PUT32(dev, 0x04, GET32(dev, 0x04) | (1 << 18)); 671 /* SPDIF out = data from DAC */ 672 PUT32(dev, 0x00, GET32(dev, 0x00) | (1 << 26)); 673 CLR32(dev, CONC_dSPDIF_OFF, CONC_SPDIF_AC3); 674 675 } else { 676 /* disable spdif out */ 677 PUT32(dev, 0x04, GET32(dev, 0x04) & ~(1 << 18)); 678 PUT32(dev, 0x00, GET32(dev, 0x00) & ~(1 << 26)); 679 } 680 681 /* we want to run each channel independently */ 682 CLR32(dev, CONC_dSTATUS_OFF, CONC_STATUS_ECHO); 683 } 684 } 685 686 static int 687 audioens_init(audioens_dev_t *dev) 688 { 689 690 audioens_init_hw(dev); 691 692 /* 693 * On this hardware, we want to disable the internal speaker by 694 * default, if it exists. (We don't have a speakerphone on any 695 * of these cards, and no SPARC hardware uses it either!) 696 */ 697 (void) ddi_prop_update_int(DDI_DEV_T_NONE, dev->dip, AC97_PROP_SPEAKER, 698 0); 699 700 /* 701 * Init mixer 702 */ 703 704 dev->ac97 = ac97_alloc(dev->dip, audioens_rd97, audioens_wr97, dev); 705 if (dev->ac97 == NULL) 706 return (DDI_FAILURE); 707 708 if (ac97_init(dev->ac97, dev->osdev) != 0) { 709 return (DDI_FAILURE); 710 } 711 712 for (int i = 0; i <= PORT_MAX; i++) { 713 audioens_port_t *port; 714 unsigned caps; 715 unsigned dmaflags; 716 size_t rlen; 717 ddi_dma_cookie_t c; 718 unsigned ccnt; 719 720 port = &dev->port[i]; 721 port->dev = dev; 722 723 switch (i) { 724 case PORT_DAC: 725 port->nchan = 4; 726 port->speed = 48000; 727 caps = ENGINE_OUTPUT_CAP; 728 dmaflags = DDI_DMA_WRITE | DDI_DMA_CONSISTENT; 729 break; 730 731 case PORT_ADC: 732 port->nchan = 2; 733 port->speed = 48000; 734 caps = ENGINE_INPUT_CAP; 735 dmaflags = DDI_DMA_READ | DDI_DMA_CONSISTENT; 736 break; 737 } 738 739 port->num = i; 740 741 /* 742 * Allocate DMA resources. 743 */ 744 745 if (ddi_dma_alloc_handle(dev->dip, &dma_attr, DDI_DMA_SLEEP, 746 NULL, &port->dmah) != DDI_SUCCESS) { 747 audio_dev_warn(dev->osdev, 748 "port %d: dma handle allocation failed", i); 749 return (DDI_FAILURE); 750 } 751 if (ddi_dma_mem_alloc(port->dmah, AUDIOENS_BUF_LEN, &buf_attr, 752 DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, &port->kaddr, 753 &rlen, &port->acch) != DDI_SUCCESS) { 754 audio_dev_warn(dev->osdev, 755 "port %d: dma memory allocation failed", i); 756 return (DDI_FAILURE); 757 } 758 /* ensure that the buffer is zeroed out properly */ 759 bzero(port->kaddr, rlen); 760 if (ddi_dma_addr_bind_handle(port->dmah, NULL, port->kaddr, 761 AUDIOENS_BUF_LEN, dmaflags, DDI_DMA_SLEEP, NULL, 762 &c, &ccnt) != DDI_DMA_MAPPED) { 763 audio_dev_warn(dev->osdev, 764 "port %d: dma binding failed", i); 765 return (DDI_FAILURE); 766 } 767 port->paddr = c.dmac_address; 768 769 /* 770 * Allocate and configure audio engine. 771 */ 772 port->engine = audio_engine_alloc(&audioens_engine_ops, caps); 773 if (port->engine == NULL) { 774 audio_dev_warn(dev->osdev, 775 "port %d: audio_engine_alloc failed", i); 776 return (DDI_FAILURE); 777 } 778 779 audio_engine_set_private(port->engine, port); 780 audio_dev_add_engine(dev->osdev, port->engine); 781 } 782 783 /* 784 * Set up kstats for interrupt reporting. 785 */ 786 if (audio_dev_register(dev->osdev) != DDI_SUCCESS) { 787 audio_dev_warn(dev->osdev, 788 "unable to register with audio framework"); 789 return (DDI_FAILURE); 790 } 791 792 return (DDI_SUCCESS); 793 } 794 795 void 796 audioens_destroy(audioens_dev_t *dev) 797 { 798 int i; 799 800 mutex_destroy(&dev->mutex); 801 802 /* free up ports, including DMA resources for ports */ 803 for (i = 0; i <= PORT_MAX; i++) { 804 audioens_port_t *port = &dev->port[i]; 805 806 if (port->paddr != 0) 807 (void) ddi_dma_unbind_handle(port->dmah); 808 if (port->acch != NULL) 809 ddi_dma_mem_free(&port->acch); 810 if (port->dmah != NULL) 811 ddi_dma_free_handle(&port->dmah); 812 813 if (port->engine != NULL) { 814 audio_dev_remove_engine(dev->osdev, port->engine); 815 audio_engine_free(port->engine); 816 } 817 } 818 819 if (dev->acch != NULL) { 820 ddi_regs_map_free(&dev->acch); 821 } 822 823 if (dev->ac97) { 824 ac97_free(dev->ac97); 825 } 826 827 if (dev->osdev != NULL) { 828 audio_dev_free(dev->osdev); 829 } 830 831 kmem_free(dev, sizeof (*dev)); 832 } 833 834 int 835 audioens_attach(dev_info_t *dip) 836 { 837 uint16_t pci_command, vendor, device; 838 uint8_t revision; 839 audioens_dev_t *dev; 840 ddi_acc_handle_t pcih; 841 const char *chip_name; 842 const char *chip_vers; 843 844 dev = kmem_zalloc(sizeof (*dev), KM_SLEEP); 845 dev->dip = dip; 846 ddi_set_driver_private(dip, dev); 847 mutex_init(&dev->mutex, NULL, MUTEX_DRIVER, NULL); 848 849 if (pci_config_setup(dip, &pcih) != DDI_SUCCESS) { 850 audio_dev_warn(dev->osdev, "pci_config_setup failed"); 851 kmem_free(dev, sizeof (*dev)); 852 mutex_destroy(&dev->mutex); 853 return (DDI_FAILURE); 854 } 855 856 vendor = pci_config_get16(pcih, PCI_CONF_VENID); 857 device = pci_config_get16(pcih, PCI_CONF_DEVID); 858 revision = pci_config_get8(pcih, PCI_CONF_REVID); 859 860 if ((vendor != ENSONIQ_VENDOR_ID && vendor != CREATIVE_VENDOR_ID) || 861 (device != ENSONIQ_ES1371 && device != ENSONIQ_ES5880 && 862 device != ENSONIQ_ES5880A && device != ECTIVA_ES1938 && 863 device != ENSONIQ_ES5880B)) 864 goto err_exit; 865 866 chip_name = "AudioPCI97"; 867 chip_vers = "unknown"; 868 869 switch (device) { 870 case ENSONIQ_ES1371: 871 chip_name = "AudioPCI97"; 872 switch (revision) { 873 case 0x02: 874 case 0x09: 875 default: 876 chip_vers = "ES1371"; 877 break; 878 case 0x04: 879 case 0x06: 880 case 0x08: 881 chip_vers = "ES1373"; 882 break; 883 case 0x07: 884 chip_vers = "ES5880"; 885 break; 886 } 887 break; 888 889 case ENSONIQ_ES5880: 890 chip_name = "SB PCI128"; 891 chip_vers = "ES5880"; 892 break; 893 case ENSONIQ_ES5880A: 894 chip_name = "SB PCI128"; 895 chip_vers = "ES5880A"; 896 break; 897 case ENSONIQ_ES5880B: 898 chip_name = "SB PCI128"; 899 chip_vers = "ES5880B"; 900 break; 901 902 case ECTIVA_ES1938: 903 chip_name = "AudioPCI"; 904 chip_vers = "ES1938"; 905 break; 906 } 907 908 dev->revision = revision; 909 dev->devid = device; 910 911 dev->osdev = audio_dev_alloc(dip, 0); 912 if (dev->osdev == NULL) { 913 goto err_exit; 914 } 915 916 audio_dev_set_description(dev->osdev, chip_name); 917 audio_dev_set_version(dev->osdev, chip_vers); 918 919 /* set the PCI latency */ 920 if ((audioens_latency == 32) || (audioens_latency == 64) || 921 (audioens_latency == 96)) 922 pci_config_put8(pcih, PCI_CONF_LATENCY_TIMER, 923 audioens_latency); 924 925 /* activate the device */ 926 pci_command = pci_config_get16(pcih, PCI_CONF_COMM); 927 pci_command |= PCI_COMM_ME | PCI_COMM_IO; 928 pci_config_put16(pcih, PCI_CONF_COMM, pci_command); 929 930 /* map registers */ 931 if (ddi_regs_map_setup(dip, 1, &dev->regs, 0, 0, &acc_attr, 932 &dev->acch) != DDI_SUCCESS) { 933 audio_dev_warn(dev->osdev, "can't map registers"); 934 goto err_exit; 935 } 936 937 /* This allocates and configures the engines */ 938 if (audioens_init(dev) != DDI_SUCCESS) { 939 audio_dev_warn(dev->osdev, "can't init device"); 940 goto err_exit; 941 } 942 943 pci_config_teardown(&pcih); 944 945 ddi_report_dev(dip); 946 947 return (DDI_SUCCESS); 948 949 err_exit: 950 pci_config_teardown(&pcih); 951 952 audioens_destroy(dev); 953 954 return (DDI_FAILURE); 955 } 956 957 int 958 audioens_detach(audioens_dev_t *dev) 959 { 960 int tmp; 961 962 /* first unregister us from the DDI framework, might be busy */ 963 if (audio_dev_unregister(dev->osdev) != DDI_SUCCESS) 964 return (DDI_FAILURE); 965 966 mutex_enter(&dev->mutex); 967 968 tmp = GET8(dev, CONC_bSERCTL_OFF) & 969 ~(CONC_SERCTL_DAC2IE | CONC_SERCTL_DAC1IE | CONC_SERCTL_ADCIE); 970 PUT8(dev, CONC_bSERCTL_OFF, tmp); 971 PUT8(dev, CONC_bSERCTL_OFF, tmp); 972 PUT8(dev, CONC_bSERCTL_OFF, tmp); 973 PUT8(dev, CONC_bSERCTL_OFF, tmp); 974 975 tmp = GET8(dev, CONC_bDEVCTL_OFF) & 976 ~(CONC_DEVCTL_DAC2_EN | CONC_DEVCTL_ADC_EN | CONC_DEVCTL_DAC1_EN); 977 PUT8(dev, CONC_bDEVCTL_OFF, tmp); 978 PUT8(dev, CONC_bDEVCTL_OFF, tmp); 979 PUT8(dev, CONC_bDEVCTL_OFF, tmp); 980 PUT8(dev, CONC_bDEVCTL_OFF, tmp); 981 982 mutex_exit(&dev->mutex); 983 984 audioens_destroy(dev); 985 986 return (DDI_SUCCESS); 987 } 988 989 static int 990 audioens_resume(audioens_dev_t *dev) 991 { 992 /* reinitialize hardware */ 993 audioens_init_hw(dev); 994 995 /* restore AC97 state */ 996 ac97_reset(dev->ac97); 997 998 audio_dev_resume(dev->osdev); 999 1000 return (DDI_SUCCESS); 1001 } 1002 1003 static int 1004 audioens_suspend(audioens_dev_t *dev) 1005 { 1006 audio_dev_suspend(dev->osdev); 1007 1008 return (DDI_SUCCESS); 1009 } 1010 1011 static int 1012 audioens_quiesce(dev_info_t *dip) 1013 { 1014 audioens_dev_t *dev; 1015 uint8_t tmp; 1016 1017 if ((dev = ddi_get_driver_private(dip)) == NULL) { 1018 return (DDI_FAILURE); 1019 } 1020 1021 /* This disables all DMA engines and interrupts */ 1022 tmp = GET8(dev, CONC_bSERCTL_OFF) & 1023 ~(CONC_SERCTL_DAC2IE | CONC_SERCTL_DAC1IE | CONC_SERCTL_ADCIE); 1024 PUT8(dev, CONC_bSERCTL_OFF, tmp); 1025 PUT8(dev, CONC_bSERCTL_OFF, tmp); 1026 PUT8(dev, CONC_bSERCTL_OFF, tmp); 1027 PUT8(dev, CONC_bSERCTL_OFF, tmp); 1028 1029 tmp = GET8(dev, CONC_bDEVCTL_OFF) & 1030 ~(CONC_DEVCTL_DAC2_EN | CONC_DEVCTL_ADC_EN | CONC_DEVCTL_DAC1_EN); 1031 PUT8(dev, CONC_bDEVCTL_OFF, tmp); 1032 PUT8(dev, CONC_bDEVCTL_OFF, tmp); 1033 PUT8(dev, CONC_bDEVCTL_OFF, tmp); 1034 PUT8(dev, CONC_bDEVCTL_OFF, tmp); 1035 1036 return (DDI_SUCCESS); 1037 } 1038 1039 1040 static int 1041 audioens_ddi_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 1042 { 1043 audioens_dev_t *dev; 1044 1045 switch (cmd) { 1046 case DDI_ATTACH: 1047 return (audioens_attach(dip)); 1048 1049 case DDI_RESUME: 1050 if ((dev = ddi_get_driver_private(dip)) == NULL) { 1051 return (DDI_FAILURE); 1052 } 1053 return (audioens_resume(dev)); 1054 1055 default: 1056 return (DDI_FAILURE); 1057 } 1058 } 1059 1060 static int 1061 audioens_ddi_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 1062 { 1063 audioens_dev_t *dev; 1064 1065 if ((dev = ddi_get_driver_private(dip)) == NULL) { 1066 return (DDI_FAILURE); 1067 } 1068 1069 switch (cmd) { 1070 case DDI_DETACH: 1071 return (audioens_detach(dev)); 1072 1073 case DDI_SUSPEND: 1074 return (audioens_suspend(dev)); 1075 default: 1076 return (DDI_FAILURE); 1077 } 1078 } 1079 1080 static int audioens_ddi_attach(dev_info_t *, ddi_attach_cmd_t); 1081 static int audioens_ddi_detach(dev_info_t *, ddi_detach_cmd_t); 1082 1083 static struct dev_ops audioens_dev_ops = { 1084 DEVO_REV, /* rev */ 1085 0, /* refcnt */ 1086 NULL, /* getinfo */ 1087 nulldev, /* identify */ 1088 nulldev, /* probe */ 1089 audioens_ddi_attach, /* attach */ 1090 audioens_ddi_detach, /* detach */ 1091 nodev, /* reset */ 1092 NULL, /* cb_ops */ 1093 NULL, /* bus_ops */ 1094 NULL, /* power */ 1095 audioens_quiesce, /* quiesce */ 1096 }; 1097 1098 static struct modldrv audioens_modldrv = { 1099 &mod_driverops, /* drv_modops */ 1100 "Ensoniq 1371/1373 Audio", /* linkinfo */ 1101 &audioens_dev_ops, /* dev_ops */ 1102 }; 1103 1104 static struct modlinkage modlinkage = { 1105 MODREV_1, 1106 { &audioens_modldrv, NULL } 1107 }; 1108 1109 int 1110 _init(void) 1111 { 1112 int rv; 1113 1114 audio_init_ops(&audioens_dev_ops, DRVNAME); 1115 if ((rv = mod_install(&modlinkage)) != 0) { 1116 audio_fini_ops(&audioens_dev_ops); 1117 } 1118 return (rv); 1119 } 1120 1121 int 1122 _fini(void) 1123 { 1124 int rv; 1125 1126 if ((rv = mod_remove(&modlinkage)) == 0) { 1127 audio_fini_ops(&audioens_dev_ops); 1128 } 1129 return (rv); 1130 } 1131 1132 int 1133 _info(struct modinfo *modinfop) 1134 { 1135 return (mod_info(&modlinkage, modinfop)); 1136 } 1137