1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 /* 28 * Copyright (C) 4Front Technologies 1996-2009. 29 */ 30 31 /* 32 * Purpose: Driver for the Creative Sound Blaster Live! and Audigy/2/4 33 * sound cards 34 */ 35 36 #include <sys/types.h> 37 #include <sys/modctl.h> 38 #include <sys/kmem.h> 39 #include <sys/conf.h> 40 #include <sys/ddi.h> 41 #include <sys/sunddi.h> 42 #include <sys/pci.h> 43 #include <sys/note.h> 44 #include <sys/stdbool.h> 45 #include <sys/audio/audio_driver.h> 46 #include <sys/audio/ac97.h> 47 48 #include "audioemu10k.h" 49 #include <sys/promif.h> 50 51 /* 52 * Include the DSP files for emu10k1 (Live!) and emu10k2 (Audigy) 53 */ 54 #include "emu10k_gpr.h" 55 #include "emu10k1_dsp.h" 56 #include "emu10k2_dsp.h" 57 58 static struct ddi_device_acc_attr dev_attr = { 59 DDI_DEVICE_ATTR_V0, 60 DDI_STRUCTURE_LE_ACC, 61 DDI_STRICTORDER_ACC 62 }; 63 64 static struct ddi_device_acc_attr buf_attr = { 65 DDI_DEVICE_ATTR_V0, 66 DDI_NEVERSWAP_ACC, 67 DDI_STRICTORDER_ACC 68 }; 69 70 71 /* 72 * EMU10K routing stuff. 73 */ 74 #define MAX_SENDS 4 75 #define SEND_L 0 76 #define SEND_R 1 77 #define SEND_SURRL 2 78 #define SEND_SURRR 3 79 #define SEND_CEN 4 80 #define SEND_LFE 5 81 #define SEND_SIDEL 6 82 #define SEND_SIDER 7 83 84 #define SPDIF_L 20 85 #define SPDIF_R 21 86 87 /* 88 * Recording sources... we start from 16 to ensure that the 89 * record sources don't collide with AC'97 record sources in 90 * the control value. 91 */ 92 #define INPUT_AC97 1 93 #define INPUT_SPD1 2 94 #define INPUT_SPD2 3 95 #define INPUT_DIGCD 4 96 #define INPUT_AUX2 5 97 #define INPUT_LINE2 6 98 #define INPUT_STEREOMIX 7 99 100 static uint8_t front_routing[MAX_SENDS] = { 101 SEND_L, SEND_R, 0x3f, 0x3f 102 }; 103 static uint8_t surr_routing[MAX_SENDS] = { 104 SEND_SURRL, SEND_SURRR, 0x3f, 0x3f 105 }; 106 static uint8_t clfe_routing[MAX_SENDS] = { 107 SEND_CEN, SEND_LFE, 0x3f, 0x3f 108 }; 109 static uint8_t side_routing[MAX_SENDS] = { 110 SEND_SIDEL, SEND_SIDER, 0x3f, 0x3f 111 }; 112 113 /* 114 * SB Live! cannot do DMA above 2G addresses. Audigy/2/4 have special 8k page 115 * mode that supports high addresses. However, we should not need this except 116 * on SPARC. For simplicity's sake, we are only delivering this driver for 117 * x86 platforms. If SPARC support is desired, then the code will have to 118 * be modified to support full 32-bit addressing. (And again, SB Live! 119 * can't do it anyway.) 120 */ 121 122 static ddi_dma_attr_t dma_attr_buf = { 123 DMA_ATTR_V0, /* Version */ 124 0x00000000ULL, /* Address low */ 125 0x7ffffff0ULL, /* Address high */ 126 0xffffffffULL, /* Counter max */ 127 1ULL, /* Default byte align */ 128 0x7f, /* Burst size */ 129 0x1, /* Minimum xfer size */ 130 0xffffffffULL, /* Maximum xfer size */ 131 0xffffffffULL, /* Max segment size */ 132 1, /* S/G list length */ 133 1, /* Granularity */ 134 0 /* Flag */ 135 }; 136 137 static int emu10k_attach(dev_info_t *); 138 static int emu10k_resume(dev_info_t *); 139 static int emu10k_detach(emu10k_devc_t *); 140 static int emu10k_suspend(emu10k_devc_t *); 141 142 static int emu10k_open(void *, int, unsigned *, caddr_t *); 143 static void emu10k_close(void *); 144 static int emu10k_start(void *); 145 static void emu10k_stop(void *); 146 static int emu10k_format(void *); 147 static int emu10k_channels(void *); 148 static int emu10k_rate(void *); 149 static uint64_t emu10k_count(void *); 150 static void emu10k_sync(void *, unsigned); 151 static void emu10k_chinfo(void *, int, unsigned *, unsigned *); 152 153 static uint16_t emu10k_read_ac97(void *, uint8_t); 154 static void emu10k_write_ac97(void *, uint8_t, uint16_t); 155 static int emu10k_alloc_port(emu10k_devc_t *, int); 156 static void emu10k_destroy(emu10k_devc_t *); 157 static int emu10k_hwinit(emu10k_devc_t *); 158 static void emu10k_init_effects(emu10k_devc_t *); 159 160 static audio_engine_ops_t emu10k_engine_ops = { 161 AUDIO_ENGINE_VERSION, 162 emu10k_open, 163 emu10k_close, 164 emu10k_start, 165 emu10k_stop, 166 emu10k_count, 167 emu10k_format, 168 emu10k_channels, 169 emu10k_rate, 170 emu10k_sync, 171 NULL, 172 emu10k_chinfo, 173 NULL 174 }; 175 176 static uint16_t 177 emu10k_read_ac97(void *arg, uint8_t index) 178 { 179 emu10k_devc_t *devc = arg; 180 int dtemp = 0, i; 181 182 mutex_enter(&devc->mutex); 183 OUTB(devc, index, devc->regs + 0x1e); 184 for (i = 0; i < 10000; i++) 185 if (INB(devc, devc->regs + 0x1e) & 0x80) 186 break; 187 188 if (i == 1000) { 189 mutex_exit(&devc->mutex); 190 return (0); /* Timeout */ 191 } 192 dtemp = INW(devc, devc->regs + 0x1c); 193 194 mutex_exit(&devc->mutex); 195 196 return (dtemp & 0xffff); 197 } 198 199 static void 200 emu10k_write_ac97(void *arg, uint8_t index, uint16_t data) 201 { 202 emu10k_devc_t *devc = arg; 203 int i; 204 205 mutex_enter(&devc->mutex); 206 207 OUTB(devc, index, devc->regs + 0x1e); 208 for (i = 0; i < 10000; i++) 209 if (INB(devc, devc->regs + 0x1e) & 0x80) 210 break; 211 OUTW(devc, data, devc->regs + 0x1c); 212 213 mutex_exit(&devc->mutex); 214 } 215 216 static uint32_t 217 emu10k_read_reg(emu10k_devc_t *devc, int reg, int chn) 218 { 219 uint32_t ptr, ptr_addr_mask, val, mask, size, offset; 220 221 ptr_addr_mask = (devc->feature_mask & 222 (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL)) ? 223 0x0fff0000 : 0x07ff0000; 224 ptr = ((reg << 16) & ptr_addr_mask) | (chn & 0x3f); 225 OUTL(devc, ptr, devc->regs + 0x00); /* Pointer */ 226 val = INL(devc, devc->regs + 0x04); /* Data */ 227 if (reg & 0xff000000) { 228 size = (reg >> 24) & 0x3f; 229 offset = (reg >> 16) & 0x1f; 230 mask = ((1 << size) - 1) << offset; 231 val &= mask; 232 val >>= offset; 233 } 234 235 return (val); 236 } 237 238 static void 239 emu10k_write_reg(emu10k_devc_t *devc, int reg, int chn, uint32_t value) 240 { 241 uint32_t ptr, ptr_addr_mask, mask, size, offset; 242 243 ptr_addr_mask = (devc->feature_mask & 244 (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL)) ? 245 0x0fff0000 : 0x07ff0000; 246 ptr = ((reg << 16) & ptr_addr_mask) | (chn & 0x3f); 247 OUTL(devc, ptr, devc->regs + 0x00); /* Pointer */ 248 if (reg & 0xff000000) { 249 size = (reg >> 24) & 0x3f; 250 offset = (reg >> 16) & 0x1f; 251 mask = ((1 << size) - 1) << offset; 252 value <<= offset; 253 value &= mask; 254 value |= INL(devc, devc->regs + 0x04) & ~mask; /* data */ 255 } 256 OUTL(devc, value, devc->regs + 0x04); /* Data */ 257 } 258 259 static void 260 emu10k_write_routing(emu10k_devc_t *devc, int voice, unsigned char *routing) 261 { 262 int i; 263 264 ASSERT(routing != NULL); 265 266 if (devc->feature_mask & (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL)) { 267 unsigned int srda = 0; 268 269 for (i = 0; i < 4; i++) 270 srda |= routing[i] << (i * 8); 271 272 emu10k_write_reg(devc, SRDA, voice, srda); 273 } else { 274 int fxrt = 0; 275 276 for (i = 0; i < 4; i++) 277 fxrt |= routing[i] << ((i * 4) + 16); 278 emu10k_write_reg(devc, FXRT, voice, fxrt); 279 } 280 } 281 282 static void 283 emu10k_write_efx(emu10k_devc_t *devc, int reg, unsigned int value) 284 { 285 emu10k_write_reg(devc, reg, 0, value); 286 } 287 288 /* 289 * Audio routines 290 */ 291 292 static void 293 emu10k_update_output_volume(emu10k_portc_t *portc, int voice, int chn) 294 { 295 emu10k_devc_t *devc = portc->devc; 296 unsigned int tmp; 297 unsigned char send[2]; 298 299 /* 300 * Each voice operator of EMU10k has 4 sends (0=left, 1=right, 301 * 2=surround_left, 3=surround_right). The original OSS driver 302 * used all of them to spread stereo output to two different 303 * speaker pairs. This Boomer version uses only the first two 304 * sends. The other sends are set to 0. 305 * 306 * Boomer uses multiple voice pairs to play multichannel 307 * audio. This function is used to update only one of these 308 * pairs. 309 */ 310 311 send[0] = 0xff; /* Max */ 312 send[1] = 0xff; /* Max */ 313 314 /* Analog voice */ 315 if (chn == LEFT_CH) { 316 send[1] = 0; 317 } else { 318 send[0] = 0; 319 } 320 321 tmp = emu10k_read_reg(devc, PTAB, voice) & 0xffff0000; 322 emu10k_write_reg(devc, PTAB, voice, tmp | (send[0] << 8) | send[1]); 323 } 324 325 static void 326 emu10k_setup_voice(emu10k_portc_t *portc, int voice, int chn, int buf_offset) 327 { 328 emu10k_devc_t *devc = portc->devc; 329 unsigned int nCRA = 0; 330 331 unsigned int loop_start, loop_end, buf_size; 332 333 int sz; 334 int start_pos; 335 336 emu10k_write_reg(devc, VEDS, voice, 0x0); /* OFF */ 337 emu10k_write_reg(devc, VTFT, voice, 0xffff); 338 emu10k_write_reg(devc, CVCF, voice, 0xffff); 339 340 sz = 2; /* Shift value for 16 bits stereo */ 341 342 /* Size of one stereo sub buffer */ 343 buf_size = (portc->buf_size / portc->channels) * 2; 344 loop_start = (portc->memptr + buf_offset) >> sz; 345 loop_end = (portc->memptr + buf_offset + buf_size) >> sz; 346 347 /* set stereo */ 348 emu10k_write_reg(devc, CPF, voice, 0x8000); 349 350 nCRA = 28; /* Stereo (16 bits) */ 351 start_pos = loop_start + nCRA; 352 353 /* SDL, ST, CA */ 354 355 emu10k_write_reg(devc, SDL, voice, loop_end); 356 emu10k_write_reg(devc, SCSA, voice, loop_start); 357 emu10k_write_reg(devc, PTAB, voice, 0); 358 359 emu10k_update_output_volume(portc, voice, chn); /* Set volume */ 360 361 emu10k_write_reg(devc, QKBCA, voice, start_pos); 362 363 emu10k_write_reg(devc, Z1, voice, 0); 364 emu10k_write_reg(devc, Z2, voice, 0); 365 366 /* This is really a physical address */ 367 emu10k_write_reg(devc, MAPA, voice, 368 0x1fff | (devc->silence_paddr << 1)); 369 emu10k_write_reg(devc, MAPB, voice, 370 0x1fff | (devc->silence_paddr << 1)); 371 372 emu10k_write_reg(devc, VTFT, voice, 0x0000ffff); 373 emu10k_write_reg(devc, CVCF, voice, 0x0000ffff); 374 emu10k_write_reg(devc, MEHA, voice, 0); 375 emu10k_write_reg(devc, MEDS, voice, 0x7f); 376 emu10k_write_reg(devc, MLV, voice, 0x8000); 377 emu10k_write_reg(devc, VLV, voice, 0x8000); 378 emu10k_write_reg(devc, VFM, voice, 0); 379 emu10k_write_reg(devc, TMFQ, voice, 0); 380 emu10k_write_reg(devc, VVFQ, voice, 0); 381 emu10k_write_reg(devc, MEV, voice, 0x8000); 382 emu10k_write_reg(devc, VEHA, voice, 0x7f7f); /* OK */ 383 /* No volume envelope delay (OK) */ 384 emu10k_write_reg(devc, VEV, voice, 0x8000); 385 emu10k_write_reg(devc, PEFE_FILTERAMOUNT, voice, 0x7f); 386 emu10k_write_reg(devc, PEFE_PITCHAMOUNT, voice, 0x00); 387 } 388 389 int 390 emu10k_open(void *arg, int flag, unsigned *nframes, caddr_t *bufp) 391 { 392 emu10k_portc_t *portc = arg; 393 emu10k_devc_t *devc = portc->devc; 394 395 _NOTE(ARGUNUSED(flag)); 396 397 portc->active = B_FALSE; 398 *nframes = portc->nframes; 399 *bufp = portc->buf_kaddr; 400 401 mutex_enter(&devc->mutex); 402 portc->count = 0; 403 mutex_exit(&devc->mutex); 404 405 return (0); 406 } 407 408 void 409 emu10k_close(void *arg) 410 { 411 _NOTE(ARGUNUSED(arg)); 412 } 413 414 int 415 emu10k_start(void *arg) 416 { 417 emu10k_portc_t *portc = arg; 418 emu10k_devc_t *devc = portc->devc; 419 420 mutex_enter(&devc->mutex); 421 portc->reset_port(portc); 422 portc->start_port(portc); 423 mutex_exit(&devc->mutex); 424 return (0); 425 } 426 427 void 428 emu10k_stop(void *arg) 429 { 430 emu10k_portc_t *portc = arg; 431 emu10k_devc_t *devc = portc->devc; 432 433 mutex_enter(&devc->mutex); 434 portc->stop_port(portc); 435 mutex_exit(&devc->mutex); 436 } 437 438 int 439 emu10k_format(void *arg) 440 { 441 _NOTE(ARGUNUSED(arg)); 442 443 return (AUDIO_FORMAT_S16_LE); 444 } 445 446 int 447 emu10k_channels(void *arg) 448 { 449 emu10k_portc_t *portc = arg; 450 451 return (portc->channels); 452 } 453 454 int 455 emu10k_rate(void *arg) 456 { 457 _NOTE(ARGUNUSED(arg)); 458 459 return (SAMPLE_RATE); 460 } 461 462 void 463 emu10k_sync(void *arg, unsigned nframes) 464 { 465 emu10k_portc_t *portc = arg; 466 _NOTE(ARGUNUSED(nframes)); 467 468 (void) ddi_dma_sync(portc->buf_dmah, 0, 0, portc->syncdir); 469 } 470 471 uint64_t 472 emu10k_count(void *arg) 473 { 474 emu10k_portc_t *portc = arg; 475 emu10k_devc_t *devc = portc->devc; 476 uint64_t count; 477 478 mutex_enter(&devc->mutex); 479 portc->update_port(portc); 480 count = portc->count; 481 mutex_exit(&devc->mutex); 482 483 return (count); 484 } 485 486 static void 487 emu10k_chinfo(void *arg, int chan, unsigned *offset, unsigned *incr) 488 { 489 emu10k_portc_t *portc = arg; 490 491 *offset = portc->nframes * (chan / 2) * 2 + (chan % 2); 492 *incr = 2; 493 } 494 495 /* private implementation bits */ 496 497 static void 498 emu10k_set_loop_stop(emu10k_devc_t *devc, int voice, int s) 499 { 500 unsigned int tmp; 501 int offs, bit; 502 503 offs = voice / 32; 504 bit = voice % 32; 505 s = !!s; 506 507 tmp = emu10k_read_reg(devc, SOLL + offs, 0); 508 tmp &= ~(1 << bit); 509 510 if (s) 511 tmp |= (1 << bit); 512 emu10k_write_reg(devc, SOLL + offs, 0, tmp); 513 } 514 515 static unsigned int 516 emu10k_rate_to_pitch(unsigned int rate) 517 { 518 static unsigned int logMagTable[128] = { 519 0x00000, 0x02dfc, 0x05b9e, 0x088e6, 520 0x0b5d6, 0x0e26f, 0x10eb3, 0x13aa2, 521 0x1663f, 0x1918a, 0x1bc84, 0x1e72e, 522 0x2118b, 0x23b9a, 0x2655d, 0x28ed5, 523 0x2b803, 0x2e0e8, 0x30985, 0x331db, 524 0x359eb, 0x381b6, 0x3a93d, 0x3d081, 525 0x3f782, 0x41e42, 0x444c1, 0x46b01, 526 0x49101, 0x4b6c4, 0x4dc49, 0x50191, 527 0x5269e, 0x54b6f, 0x57006, 0x59463, 528 0x5b888, 0x5dc74, 0x60029, 0x623a7, 529 0x646ee, 0x66a00, 0x68cdd, 0x6af86, 530 0x6d1fa, 0x6f43c, 0x7164b, 0x73829, 531 0x759d4, 0x77b4f, 0x79c9a, 0x7bdb5, 532 0x7dea1, 0x7ff5e, 0x81fed, 0x8404e, 533 0x86082, 0x88089, 0x8a064, 0x8c014, 534 0x8df98, 0x8fef1, 0x91e20, 0x93d26, 535 0x95c01, 0x97ab4, 0x9993e, 0x9b79f, 536 0x9d5d9, 0x9f3ec, 0xa11d8, 0xa2f9d, 537 0xa4d3c, 0xa6ab5, 0xa8808, 0xaa537, 538 0xac241, 0xadf26, 0xafbe7, 0xb1885, 539 0xb3500, 0xb5157, 0xb6d8c, 0xb899f, 540 0xba58f, 0xbc15e, 0xbdd0c, 0xbf899, 541 0xc1404, 0xc2f50, 0xc4a7b, 0xc6587, 542 0xc8073, 0xc9b3f, 0xcb5ed, 0xcd07c, 543 0xceaec, 0xd053f, 0xd1f73, 0xd398a, 544 0xd5384, 0xd6d60, 0xd8720, 0xda0c3, 545 0xdba4a, 0xdd3b4, 0xded03, 0xe0636, 546 0xe1f4e, 0xe384a, 0xe512c, 0xe69f3, 547 0xe829f, 0xe9b31, 0xeb3a9, 0xecc08, 548 0xee44c, 0xefc78, 0xf148a, 0xf2c83, 549 0xf4463, 0xf5c2a, 0xf73da, 0xf8b71, 550 0xfa2f0, 0xfba57, 0xfd1a7, 0xfe8df 551 }; 552 static char logSlopeTable[128] = { 553 0x5c, 0x5c, 0x5b, 0x5a, 0x5a, 0x59, 0x58, 0x58, 554 0x57, 0x56, 0x56, 0x55, 0x55, 0x54, 0x53, 0x53, 555 0x52, 0x52, 0x51, 0x51, 0x50, 0x50, 0x4f, 0x4f, 556 0x4e, 0x4d, 0x4d, 0x4d, 0x4c, 0x4c, 0x4b, 0x4b, 557 0x4a, 0x4a, 0x49, 0x49, 0x48, 0x48, 0x47, 0x47, 558 0x47, 0x46, 0x46, 0x45, 0x45, 0x45, 0x44, 0x44, 559 0x43, 0x43, 0x43, 0x42, 0x42, 0x42, 0x41, 0x41, 560 0x41, 0x40, 0x40, 0x40, 0x3f, 0x3f, 0x3f, 0x3e, 561 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c, 0x3c, 562 0x3b, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 563 0x39, 0x39, 0x39, 0x38, 0x38, 0x38, 0x38, 0x37, 564 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x36, 0x35, 565 0x35, 0x35, 0x35, 0x34, 0x34, 0x34, 0x34, 0x34, 566 0x33, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x32, 567 0x32, 0x31, 0x31, 0x31, 0x31, 0x31, 0x30, 0x30, 568 0x30, 0x30, 0x30, 0x2f, 0x2f, 0x2f, 0x2f, 0x2f 569 }; 570 int i; 571 572 if (rate == 0) 573 return (0); /* Bail out if no leading "1" */ 574 rate *= 11185; /* Scale 48000 to 0x20002380 */ 575 for (i = 31; i > 0; i--) { 576 if (rate & 0x80000000) { /* Detect leading "1" */ 577 return (((unsigned int) (i - 15) << 20) + 578 logMagTable[0x7f & (rate >> 24)] + 579 (0x7f & (rate >> 17)) * 580 logSlopeTable[0x7f & (rate >> 24)]); 581 } 582 rate <<= 1; 583 } 584 585 return (0); /* Should never reach this point */ 586 } 587 588 static unsigned int 589 emu10k_rate_to_linearpitch(unsigned int rate) 590 { 591 rate = (rate << 8) / 375; 592 return (rate >> 1) + (rate & 1); 593 } 594 595 static void 596 emu10k_prepare_voice(emu10k_devc_t *devc, int voice) 597 { 598 unsigned int sample, initial_pitch, pitch_target; 599 unsigned int cra, cs, ccis, i; 600 601 /* setup CCR regs */ 602 cra = 64; 603 cs = 4; /* Stereo */ 604 ccis = 28; /* Stereo */ 605 sample = 0; /* 16 bit silence */ 606 607 for (i = 0; i < cs; i++) 608 emu10k_write_reg(devc, CD0 + i, voice, sample); 609 610 emu10k_write_reg(devc, CCR_CACHEINVALIDSIZE, voice, 0); 611 emu10k_write_reg(devc, CCR_READADDRESS, voice, cra); 612 emu10k_write_reg(devc, CCR_CACHEINVALIDSIZE, voice, ccis); 613 614 /* Set current pitch */ 615 emu10k_write_reg(devc, IFA, voice, 0xff00); 616 emu10k_write_reg(devc, VTFT, voice, 0xffffffff); 617 emu10k_write_reg(devc, CVCF, voice, 0xffffffff); 618 emu10k_set_loop_stop(devc, voice, 0); 619 620 pitch_target = emu10k_rate_to_linearpitch(SAMPLE_RATE); 621 initial_pitch = emu10k_rate_to_pitch(SAMPLE_RATE) >> 8; 622 emu10k_write_reg(devc, PTRX_PITCHTARGET, voice, pitch_target); 623 emu10k_write_reg(devc, CPF_CURRENTPITCH, voice, pitch_target); 624 emu10k_write_reg(devc, IP, voice, initial_pitch); 625 } 626 627 static void 628 emu10k_stop_voice(emu10k_devc_t *devc, int voice) 629 { 630 emu10k_write_reg(devc, IFA, voice, 0xffff); 631 emu10k_write_reg(devc, VTFT, voice, 0xffff); 632 emu10k_write_reg(devc, PTRX_PITCHTARGET, voice, 0); 633 emu10k_write_reg(devc, CPF_CURRENTPITCH, voice, 0); 634 emu10k_write_reg(devc, IP, voice, 0); 635 emu10k_set_loop_stop(devc, voice, 1); 636 } 637 638 static void 639 emu10k_reset_pair(emu10k_portc_t *portc, int voice, uint8_t *routing, 640 int buf_offset) 641 { 642 emu10k_devc_t *devc = portc->devc; 643 644 /* Left channel */ 645 /* Intial filter cutoff and attenuation */ 646 emu10k_write_reg(devc, IFA, voice, 0xffff); 647 /* Volume envelope decay and sustain */ 648 emu10k_write_reg(devc, VEDS, voice, 0x0); 649 /* Volume target and Filter cutoff target */ 650 emu10k_write_reg(devc, VTFT, voice, 0xffff); 651 /* Pitch target and sends A and B */ 652 emu10k_write_reg(devc, PTAB, voice, 0x0); 653 654 /* The same for right channel */ 655 emu10k_write_reg(devc, IFA, voice + 1, 0xffff); 656 emu10k_write_reg(devc, VEDS, voice + 1, 0x0); 657 emu10k_write_reg(devc, VTFT, voice + 1, 0xffff); 658 emu10k_write_reg(devc, PTAB, voice + 1, 0x0); 659 660 /* now setup the voices and go! */ 661 emu10k_setup_voice(portc, voice, LEFT_CH, buf_offset); 662 emu10k_setup_voice(portc, voice + 1, RIGHT_CH, buf_offset); 663 664 emu10k_write_routing(devc, voice, routing); 665 emu10k_write_routing(devc, voice + 1, routing); 666 } 667 668 void 669 emu10k_start_play(emu10k_portc_t *portc) 670 { 671 emu10k_devc_t *devc = portc->devc; 672 673 ASSERT(mutex_owned(&devc->mutex)); 674 emu10k_prepare_voice(devc, 0); 675 emu10k_prepare_voice(devc, 1); 676 677 emu10k_prepare_voice(devc, 2); 678 emu10k_prepare_voice(devc, 3); 679 680 emu10k_prepare_voice(devc, 4); 681 emu10k_prepare_voice(devc, 5); 682 683 emu10k_prepare_voice(devc, 6); 684 emu10k_prepare_voice(devc, 7); 685 686 /* Trigger playback on all voices */ 687 emu10k_write_reg(devc, VEDS, 0, 0x7f7f); 688 emu10k_write_reg(devc, VEDS, 1, 0x7f7f); 689 emu10k_write_reg(devc, VEDS, 2, 0x7f7f); 690 emu10k_write_reg(devc, VEDS, 3, 0x7f7f); 691 emu10k_write_reg(devc, VEDS, 4, 0x7f7f); 692 emu10k_write_reg(devc, VEDS, 5, 0x7f7f); 693 emu10k_write_reg(devc, VEDS, 6, 0x7f7f); 694 emu10k_write_reg(devc, VEDS, 7, 0x7f7f); 695 696 portc->active = B_TRUE; 697 } 698 699 void 700 emu10k_stop_play(emu10k_portc_t *portc) 701 { 702 emu10k_devc_t *devc = portc->devc; 703 704 emu10k_stop_voice(devc, 0); 705 emu10k_stop_voice(devc, 1); 706 emu10k_stop_voice(devc, 2); 707 emu10k_stop_voice(devc, 3); 708 emu10k_stop_voice(devc, 4); 709 emu10k_stop_voice(devc, 5); 710 emu10k_stop_voice(devc, 6); 711 emu10k_stop_voice(devc, 7); 712 713 portc->active = B_FALSE; 714 } 715 716 void 717 emu10k_reset_play(emu10k_portc_t *portc) 718 { 719 emu10k_devc_t *devc = portc->devc; 720 uint32_t offs; 721 722 offs = (portc->buf_size / portc->channels) * 2; 723 724 if (devc->feature_mask & SB_71) { 725 emu10k_reset_pair(portc, 0, front_routing, 0); 726 emu10k_reset_pair(portc, 2, clfe_routing, offs); 727 emu10k_reset_pair(portc, 4, surr_routing, 2 * offs); 728 emu10k_reset_pair(portc, 6, side_routing, 3 * offs); 729 } else if (devc->feature_mask & SB_51) { 730 emu10k_reset_pair(portc, 0, front_routing, 0); 731 emu10k_reset_pair(portc, 2, clfe_routing, offs); 732 emu10k_reset_pair(portc, 4, surr_routing, 2 * offs); 733 } else { 734 emu10k_reset_pair(portc, 0, front_routing, 0); 735 emu10k_reset_pair(portc, 2, surr_routing, offs); 736 } 737 738 portc->pos = 0; 739 } 740 741 uint32_t emu10k_vars[5]; 742 743 void 744 emu10k_update_play(emu10k_portc_t *portc) 745 { 746 emu10k_devc_t *devc = portc->devc; 747 uint32_t cnt, pos; 748 749 /* 750 * Note: position is given as stereo samples, i.e. frames. 751 */ 752 pos = emu10k_read_reg(devc, QKBCA, 0) & 0xffffff; 753 pos -= (portc->memptr >> 2); 754 if (pos > portc->nframes) { 755 /* 756 * This should never happen! If it happens, we should 757 * throw an FMA fault. (When we support FMA.) For now 758 * we just assume the device is stuck, and report no 759 * change in position. 760 */ 761 pos = portc->pos; 762 } 763 ASSERT(pos <= portc->nframes); 764 765 if (pos < portc->pos) { 766 cnt = (portc->nframes - portc->pos) + pos; 767 } else { 768 cnt = (pos - portc->pos); 769 } 770 ASSERT(cnt <= portc->nframes); 771 if (portc->dopos) { 772 emu10k_vars[0] = portc->pos; 773 emu10k_vars[1] = pos; 774 emu10k_vars[2] = (uint32_t)portc->count; 775 emu10k_vars[3] = cnt; 776 portc->dopos = 0; 777 } 778 portc->count += cnt; 779 portc->pos = pos; 780 } 781 782 void 783 emu10k_start_rec(emu10k_portc_t *portc) 784 { 785 emu10k_devc_t *devc = portc->devc; 786 uint32_t tmp; 787 788 tmp = 0; /* setup 48Kz */ 789 if (devc->feature_mask & (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL)) 790 tmp |= 0x30; /* Left/right channel enable */ 791 else 792 tmp |= 0x18; /* Left/right channel enable */ 793 emu10k_write_reg(devc, ADCSR, 0, tmp); /* GO */ 794 795 portc->active = B_TRUE; 796 } 797 798 void 799 emu10k_stop_rec(emu10k_portc_t *portc) 800 { 801 emu10k_devc_t *devc = portc->devc; 802 803 ASSERT(mutex_owned(&devc->mutex)); 804 emu10k_write_reg(devc, ADCSR, 0, 0); 805 806 portc->active = B_FALSE; 807 } 808 void 809 emu10k_reset_rec(emu10k_portc_t *portc) 810 { 811 emu10k_devc_t *devc = portc->devc; 812 uint32_t sz; 813 814 switch (portc->buf_size) { 815 case 4096: 816 sz = 15; 817 break; 818 case 8192: 819 sz = 19; 820 break; 821 case 16384: 822 sz = 23; 823 break; 824 case 32768: 825 sz = 27; 826 break; 827 case 65536: 828 sz = 31; 829 break; 830 } 831 emu10k_write_reg(devc, ADCBA, 0, portc->buf_paddr); 832 emu10k_write_reg(devc, ADCBS, 0, sz); 833 emu10k_write_reg(devc, ADCSR, 0, 0); /* reset for phase */ 834 portc->pos = 0; 835 } 836 837 void 838 emu10k_update_rec(emu10k_portc_t *portc) 839 { 840 emu10k_devc_t *devc = portc->devc; 841 uint32_t cnt, pos; 842 843 /* given in bytes, we divide all counts by 4 to get samples */ 844 pos = emu10k_read_reg(devc, 845 (devc->feature_mask & SB_LIVE) ? MIDX : ADCIDX, 0); 846 if (pos <= portc->pos) { 847 cnt = ((portc->buf_size) - portc->pos) >> 2; 848 cnt += (pos >> 2); 849 } else { 850 cnt = ((pos - portc->pos) >> 2); 851 } 852 portc->count += cnt; 853 portc->pos = pos; 854 } 855 856 int 857 emu10k_alloc_port(emu10k_devc_t *devc, int num) 858 { 859 emu10k_portc_t *portc; 860 size_t len; 861 ddi_dma_cookie_t cookie; 862 uint_t count; 863 int dir; 864 unsigned caps; 865 audio_dev_t *adev; 866 int i, n; 867 868 adev = devc->adev; 869 portc = kmem_zalloc(sizeof (*portc), KM_SLEEP); 870 devc->portc[num] = portc; 871 portc->devc = devc; 872 873 portc->memptr = devc->audio_memptr; 874 devc->audio_memptr += (DMABUF_SIZE + 4095) & ~4095; 875 876 switch (num) { 877 case EMU10K_REC: 878 portc->syncdir = DDI_DMA_SYNC_FORKERNEL; 879 caps = ENGINE_INPUT_CAP; 880 dir = DDI_DMA_READ; 881 portc->channels = 2; 882 portc->start_port = emu10k_start_rec; 883 portc->stop_port = emu10k_stop_rec; 884 portc->reset_port = emu10k_reset_rec; 885 portc->update_port = emu10k_update_rec; 886 /* This is the minimum record buffer size. */ 887 portc->buf_size = 4096; 888 portc->nframes = portc->buf_size / 4; 889 break; 890 case EMU10K_PLAY: 891 portc->syncdir = DDI_DMA_SYNC_FORDEV; 892 caps = ENGINE_OUTPUT_CAP; 893 dir = DDI_DMA_WRITE; 894 portc->channels = 8; 895 portc->start_port = emu10k_start_play; 896 portc->stop_port = emu10k_stop_play; 897 portc->reset_port = emu10k_reset_play; 898 portc->update_port = emu10k_update_play; 899 /* This could probably be tunable. */ 900 portc->nframes = 2048; 901 portc->buf_size = portc->nframes * portc->channels * 2; 902 break; 903 default: 904 return (DDI_FAILURE); 905 } 906 907 /* 908 * Fragments that are not powers of two don't seem to work 909 * at all with EMU10K. For simplicity's sake, we eliminate 910 * the question and fix the interrupt rate. This is also the 911 * logical minimum for record, which requires at least 4K for 912 * the record size. 913 */ 914 915 if (portc->buf_size > DMABUF_SIZE) { 916 cmn_err(CE_NOTE, "Buffer size %d is too large (max %d)", 917 (int)portc->buf_size, DMABUF_SIZE); 918 portc->buf_size = DMABUF_SIZE; 919 } 920 921 /* Alloc buffers */ 922 if (ddi_dma_alloc_handle(devc->dip, &dma_attr_buf, DDI_DMA_SLEEP, NULL, 923 &portc->buf_dmah) != DDI_SUCCESS) { 924 audio_dev_warn(adev, "failed to allocate BUF handle"); 925 return (DDI_FAILURE); 926 } 927 928 if (ddi_dma_mem_alloc(portc->buf_dmah, portc->buf_size, 929 &dev_attr, DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, 930 &portc->buf_kaddr, &len, &portc->buf_acch) != DDI_SUCCESS) { 931 audio_dev_warn(adev, "failed to allocate BUF memory"); 932 return (DDI_FAILURE); 933 } 934 935 if (ddi_dma_addr_bind_handle(portc->buf_dmah, NULL, portc->buf_kaddr, 936 len, DDI_DMA_CONSISTENT | dir, DDI_DMA_SLEEP, 937 NULL, &cookie, &count) != DDI_SUCCESS) { 938 audio_dev_warn(adev, "failed binding BUF DMA handle"); 939 return (DDI_FAILURE); 940 } 941 portc->buf_paddr = cookie.dmac_address; 942 943 if ((devc->feature_mask & SB_LIVE) && 944 (portc->buf_paddr & 0x80000000)) { 945 audio_dev_warn(adev, "Got DMA buffer beyond 2G limit."); 946 return (DDI_FAILURE); 947 } 948 949 if (num == EMU10K_PLAY) { /* Output device */ 950 n = portc->memptr / 4096; 951 /* 952 * Fill the page table 953 */ 954 for (i = 0; i < portc->buf_size / 4096; i++) { 955 FILL_PAGE_MAP_ENTRY(n + i, 956 portc->buf_paddr + i * 4096); 957 } 958 959 (void) ddi_dma_sync(devc->pt_dmah, 0, 0, DDI_DMA_SYNC_FORDEV); 960 } 961 962 portc->engine = audio_engine_alloc(&emu10k_engine_ops, caps); 963 if (portc->engine == NULL) { 964 audio_dev_warn(adev, "audio_engine_alloc failed"); 965 return (DDI_FAILURE); 966 } 967 968 audio_engine_set_private(portc->engine, portc); 969 audio_dev_add_engine(adev, portc->engine); 970 971 return (DDI_SUCCESS); 972 } 973 974 void 975 emu10k_destroy(emu10k_devc_t *devc) 976 { 977 mutex_destroy(&devc->mutex); 978 979 if (devc->silence_paddr) { 980 (void) ddi_dma_unbind_handle(devc->silence_dmah); 981 } 982 if (devc->silence_acch) { 983 ddi_dma_mem_free(&devc->silence_acch); 984 } 985 if (devc->silence_dmah) { 986 ddi_dma_free_handle(&devc->silence_dmah); 987 } 988 989 if (devc->pt_paddr) { 990 (void) ddi_dma_unbind_handle(devc->pt_dmah); 991 } 992 if (devc->pt_acch) { 993 ddi_dma_mem_free(&devc->pt_acch); 994 } 995 if (devc->pt_dmah) { 996 ddi_dma_free_handle(&devc->pt_dmah); 997 } 998 999 1000 for (int i = 0; i < CTL_MAX; i++) { 1001 emu10k_ctrl_t *ec = &devc->ctrls[i]; 1002 if (ec->ctrl != NULL) { 1003 audio_dev_del_control(ec->ctrl); 1004 ec->ctrl = NULL; 1005 } 1006 } 1007 1008 for (int i = 0; i < EMU10K_NUM_PORTC; i++) { 1009 emu10k_portc_t *portc = devc->portc[i]; 1010 if (!portc) 1011 continue; 1012 if (portc->engine) { 1013 audio_dev_remove_engine(devc->adev, portc->engine); 1014 audio_engine_free(portc->engine); 1015 } 1016 if (portc->buf_paddr) { 1017 (void) ddi_dma_unbind_handle(portc->buf_dmah); 1018 } 1019 if (portc->buf_acch) { 1020 ddi_dma_mem_free(&portc->buf_acch); 1021 } 1022 if (portc->buf_dmah) { 1023 ddi_dma_free_handle(&portc->buf_dmah); 1024 } 1025 kmem_free(portc, sizeof (*portc)); 1026 } 1027 1028 if (devc->ac97 != NULL) { 1029 ac97_free(devc->ac97); 1030 } 1031 if (devc->adev != NULL) { 1032 audio_dev_free(devc->adev); 1033 } 1034 if (devc->regsh != NULL) { 1035 ddi_regs_map_free(&devc->regsh); 1036 } 1037 if (devc->pcih != NULL) { 1038 pci_config_teardown(&devc->pcih); 1039 } 1040 1041 kmem_free(devc, sizeof (*devc)); 1042 } 1043 1044 static void 1045 emu10k_init_voice(emu10k_devc_t *devc, int voice) 1046 { 1047 emu10k_set_loop_stop(devc, voice, 1); 1048 1049 emu10k_write_reg(devc, VEDS, voice, 0x0); 1050 emu10k_write_reg(devc, IP, voice, 0x0); 1051 emu10k_write_reg(devc, VTFT, voice, 0xffff); 1052 emu10k_write_reg(devc, CVCF, voice, 0xffff); 1053 emu10k_write_reg(devc, PTAB, voice, 0x0); 1054 emu10k_write_reg(devc, CPF, voice, 0x0); 1055 emu10k_write_reg(devc, CCR, voice, 0x0); 1056 emu10k_write_reg(devc, SCSA, voice, 0x0); 1057 emu10k_write_reg(devc, SDL, voice, 0x10); 1058 emu10k_write_reg(devc, QKBCA, voice, 0x0); 1059 emu10k_write_reg(devc, Z1, voice, 0x0); 1060 emu10k_write_reg(devc, Z2, voice, 0x0); 1061 1062 if (devc->feature_mask & (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL)) 1063 emu10k_write_reg(devc, SRDA, voice, 0x03020100); 1064 else 1065 emu10k_write_reg(devc, FXRT, voice, 0x32100000); 1066 1067 emu10k_write_reg(devc, MEHA, voice, 0x0); 1068 emu10k_write_reg(devc, MEDS, voice, 0x0); 1069 emu10k_write_reg(devc, IFA, voice, 0xffff); 1070 emu10k_write_reg(devc, PEFE, voice, 0x0); 1071 emu10k_write_reg(devc, VFM, voice, 0x0); 1072 emu10k_write_reg(devc, TMFQ, voice, 24); 1073 emu10k_write_reg(devc, VVFQ, voice, 24); 1074 emu10k_write_reg(devc, TMPE, voice, 0x0); 1075 emu10k_write_reg(devc, VLV, voice, 0x0); 1076 emu10k_write_reg(devc, MLV, voice, 0x0); 1077 emu10k_write_reg(devc, VEHA, voice, 0x0); 1078 emu10k_write_reg(devc, VEV, voice, 0x0); 1079 emu10k_write_reg(devc, MEV, voice, 0x0); 1080 1081 if (devc->feature_mask & (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL)) { 1082 emu10k_write_reg(devc, CSBA, voice, 0x0); 1083 emu10k_write_reg(devc, CSDC, voice, 0x0); 1084 emu10k_write_reg(devc, CSFE, voice, 0x0); 1085 emu10k_write_reg(devc, CSHG, voice, 0x0); 1086 emu10k_write_reg(devc, SRHE, voice, 0x3f3f3f3f); 1087 } 1088 } 1089 1090 int 1091 emu10k_hwinit(emu10k_devc_t *devc) 1092 { 1093 1094 unsigned int tmp, i; 1095 unsigned int reg; 1096 1097 ASSERT(mutex_owned(&devc->mutex)); 1098 1099 emu10k_write_reg(devc, AC97SLOT, 0, AC97SLOT_CENTER | AC97SLOT_LFE); 1100 1101 OUTL(devc, 0x00000000, devc->regs + 0x0c); /* Intr disable */ 1102 OUTL(devc, HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK | 1103 HCFG_MUTEBUTTONENABLE, 1104 devc->regs + HCFG); 1105 1106 emu10k_write_reg(devc, MBS, 0, 0x0); 1107 emu10k_write_reg(devc, MBA, 0, 0x0); 1108 emu10k_write_reg(devc, FXBS, 0, 0x0); 1109 emu10k_write_reg(devc, FXBA, 0, 0x0); 1110 emu10k_write_reg(devc, ADCBS, 0, 0x0); 1111 emu10k_write_reg(devc, ADCBA, 0, 0x0); 1112 1113 /* Ensure all interrupts are disabled */ 1114 OUTL(devc, 0, devc->regs + IE); 1115 emu10k_write_reg(devc, CLIEL, 0, 0x0); 1116 emu10k_write_reg(devc, CLIEH, 0, 0x0); 1117 if (!(devc->feature_mask & SB_LIVE)) { 1118 emu10k_write_reg(devc, HLIEL, 0, 0x0); 1119 emu10k_write_reg(devc, HLIEH, 0, 0x0); 1120 } 1121 emu10k_write_reg(devc, CLIPL, 0, 0xffffffff); 1122 emu10k_write_reg(devc, CLIPH, 0, 0xffffffff); 1123 emu10k_write_reg(devc, SOLL, 0, 0xffffffff); 1124 emu10k_write_reg(devc, SOLH, 0, 0xffffffff); 1125 1126 1127 if (devc->feature_mask & (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL)) { 1128 emu10k_write_reg(devc, SOC, 0, 0xf00); /* ?? */ 1129 emu10k_write_reg(devc, AC97SLOT, 0, 0x3); /* ?? */ 1130 } 1131 1132 for (i = 0; i < 64; i++) 1133 emu10k_init_voice(devc, i); 1134 1135 emu10k_write_reg(devc, SCS0, 0, 0x2109204); 1136 emu10k_write_reg(devc, SCS1, 0, 0x2109204); 1137 emu10k_write_reg(devc, SCS2, 0, 0x2109204); 1138 1139 emu10k_write_reg(devc, PTBA, 0, devc->pt_paddr); 1140 tmp = emu10k_read_reg(devc, PTBA, 0); 1141 1142 emu10k_write_reg(devc, TCBA, 0, 0x0); 1143 emu10k_write_reg(devc, TCBS, 0, 0x4); 1144 1145 reg = 0; 1146 if (devc->feature_mask & SB_71) { 1147 reg = AC97SLOT_CENTER | AC97SLOT_LFE | AC97SLOT_REAR_LEFT | 1148 AC97SLOT_REAR_RIGHT; 1149 } else if (devc->feature_mask & SB_51) { 1150 reg = AC97SLOT_CENTER | AC97SLOT_LFE; 1151 } 1152 if (devc->feature_mask & (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL)) 1153 reg |= 0x40; 1154 emu10k_write_reg(devc, AC97SLOT, 0, reg); 1155 1156 if (devc->feature_mask & SB_AUDIGY2) { 1157 /* Enable analog outputs on Audigy2 */ 1158 int tmp; 1159 1160 /* Setup SRCMulti_I2S SamplingRate */ 1161 tmp = emu10k_read_reg(devc, EHC, 0); 1162 tmp &= 0xfffff1ff; 1163 tmp |= (0x2 << 9); 1164 emu10k_write_reg(devc, EHC, 0, tmp); 1165 /* emu10k_write_reg (devc, SOC, 0, 0x00000000); */ 1166 1167 /* Setup SRCSel (Enable Spdif,I2S SRCMulti) */ 1168 OUTL(devc, 0x600000, devc->regs + 0x20); 1169 OUTL(devc, 0x14, devc->regs + 0x24); 1170 1171 /* Setup SRCMulti Input Audio Enable */ 1172 OUTL(devc, 0x6E0000, devc->regs + 0x20); 1173 1174 OUTL(devc, 0xFF00FF00, devc->regs + 0x24); 1175 1176 /* Setup I2S ASRC Enable (HC register) */ 1177 tmp = INL(devc, devc->regs + HCFG); 1178 tmp |= 0x00000070; 1179 OUTL(devc, tmp, devc->regs + HCFG); 1180 1181 /* 1182 * Unmute Analog now. Set GPO6 to 1 for Apollo. 1183 * This has to be done after init ALice3 I2SOut beyond 48KHz. 1184 * So, sequence is important 1185 */ 1186 tmp = INL(devc, devc->regs + 0x18); 1187 tmp |= 0x0040; 1188 1189 OUTL(devc, tmp, devc->regs + 0x18); 1190 } 1191 1192 if (devc->feature_mask & SB_AUDIGY2VAL) { 1193 /* Enable analog outputs on Audigy2 */ 1194 int tmp; 1195 1196 /* Setup SRCMulti_I2S SamplingRate */ 1197 tmp = emu10k_read_reg(devc, EHC, 0); 1198 tmp &= 0xfffff1ff; 1199 tmp |= (0x2 << 9); 1200 emu10k_write_reg(devc, EHC, 0, tmp); 1201 1202 /* Setup SRCSel (Enable Spdif,I2S SRCMulti) */ 1203 OUTL(devc, 0x600000, devc->regs + 0x20); 1204 OUTL(devc, 0x14, devc->regs + 0x24); 1205 1206 /* Setup SRCMulti Input Audio Enable */ 1207 OUTL(devc, 0x7B0000, devc->regs + 0x20); 1208 OUTL(devc, 0xFF000000, devc->regs + 0x24); 1209 1210 /* SPDIF output enable */ 1211 OUTL(devc, 0x7A0000, devc->regs + 0x20); 1212 OUTL(devc, 0xFF000000, devc->regs + 0x24); 1213 1214 tmp = INL(devc, devc->regs + 0x18) & ~0x8; 1215 OUTL(devc, tmp, devc->regs + 0x18); 1216 } 1217 1218 emu10k_write_reg(devc, SOLL, 0, 0xffffffff); 1219 emu10k_write_reg(devc, SOLH, 0, 0xffffffff); 1220 1221 if (devc->feature_mask & (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL)) { 1222 unsigned int mode = 0; 1223 1224 if (devc->feature_mask & (SB_AUDIGY2|SB_AUDIGY2VAL)) 1225 mode |= HCFG_AC3ENABLE_GPSPDIF | HCFG_AC3ENABLE_CDSPDIF; 1226 OUTL(devc, 1227 HCFG_AUDIOENABLE | HCFG_AUTOMUTE | 1228 HCFG_JOYENABLE | A_HCFG_VMUTE | 1229 A_HCFG_AUTOMUTE | mode, devc->regs + HCFG); 1230 1231 OUTL(devc, INL(devc, devc->regs + 0x18) | 1232 0x0004, devc->regs + 0x18); /* GPIO (S/PDIF enable) */ 1233 1234 1235 /* enable IR port */ 1236 tmp = INL(devc, devc->regs + 0x18); 1237 OUTL(devc, tmp | A_IOCFG_GPOUT2, devc->regs + 0x18); 1238 drv_usecwait(500); 1239 OUTL(devc, tmp | A_IOCFG_GPOUT1 | A_IOCFG_GPOUT2, 1240 devc->regs + 0x18); 1241 drv_usecwait(100); 1242 OUTL(devc, tmp, devc->regs + 0x18); 1243 } else { 1244 OUTL(devc, 1245 HCFG_AUDIOENABLE | HCFG_LOCKTANKCACHE_MASK | 1246 HCFG_AUTOMUTE | HCFG_JOYENABLE, devc->regs + HCFG); 1247 } 1248 1249 1250 /* enable IR port */ 1251 tmp = INL(devc, devc->regs + HCFG); 1252 OUTL(devc, tmp | HCFG_GPOUT2, devc->regs + HCFG); 1253 drv_usecwait(500); 1254 OUTL(devc, tmp | HCFG_GPOUT1 | HCFG_GPOUT2, devc->regs + HCFG); 1255 drv_usecwait(100); 1256 OUTL(devc, tmp, devc->regs + HCFG); 1257 1258 1259 /* 1260 * Start by configuring for analog mode. 1261 */ 1262 if (devc->feature_mask & (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL)) { 1263 reg = INL(devc, devc->regs + 0x18) & ~A_IOCFG_GPOUT0; 1264 reg |= ((devc->feature_mask & SB_INVSP) ? 0x4 : 0); 1265 OUTL(devc, reg, devc->regs + 0x18); 1266 } 1267 if (devc->feature_mask & SB_LIVE) { /* SBLIVE */ 1268 reg = INL(devc, devc->regs + HCFG) & ~HCFG_GPOUT0; 1269 reg |= ((devc->feature_mask & SB_INVSP) ? HCFG_GPOUT0 : 0); 1270 OUTL(devc, reg, devc->regs + HCFG); 1271 } 1272 1273 if (devc->feature_mask & SB_AUDIGY2VAL) { 1274 OUTL(devc, INL(devc, devc->regs + 0x18) | 0x0060, 1275 devc->regs + 0x18); 1276 } else if (devc->feature_mask & SB_AUDIGY2) { 1277 OUTL(devc, INL(devc, devc->regs + 0x18) | 0x0040, 1278 devc->regs + 0x18); 1279 } else if (devc->feature_mask & SB_AUDIGY) { 1280 OUTL(devc, INL(devc, devc->regs + 0x18) | 0x0080, 1281 devc->regs + 0x18); 1282 } 1283 1284 emu10k_init_effects(devc); 1285 1286 return (DDI_SUCCESS); 1287 } 1288 1289 static const int db2lin_101[101] = { 1290 0x00000000, 1291 0x0024B53A, 0x002750CA, 0x002A1BC6, 0x002D198D, 0x00304DBA, 0x0033BC2A, 1292 0x00376901, 0x003B58AF, 0x003F8FF1, 0x004413DF, 0x0048E9EA, 0x004E17E9, 1293 0x0053A419, 0x0059952C, 0x005FF24E, 0x0066C32A, 0x006E0FFB, 0x0075E18D, 1294 0x007E414F, 0x0087395B, 0x0090D482, 0x009B1E5B, 0x00A6234F, 0x00B1F0A7, 1295 0x00BE94A1, 0x00CC1E7C, 0x00DA9E8D, 0x00EA2650, 0x00FAC881, 0x010C9931, 1296 0x011FADDC, 0x01341D87, 0x014A00D8, 0x01617235, 0x017A8DE6, 0x01957233, 1297 0x01B23F8D, 0x01D118B1, 0x01F222D4, 0x021585D1, 0x023B6C57, 0x0264041D, 1298 0x028F7E19, 0x02BE0EBD, 0x02EFEE33, 0x032558A2, 0x035E8E7A, 0x039BD4BC, 1299 0x03DD7551, 0x0423BF61, 0x046F07B5, 0x04BFA91B, 0x051604D5, 0x0572830D, 1300 0x05D59354, 0x063FAD27, 0x06B15080, 0x072B0673, 0x07AD61CD, 0x0838FFCA, 1301 0x08CE88D3, 0x096EB147, 0x0A1A3A53, 0x0AD1F2E0, 0x0B96B889, 0x0C6978A5, 1302 0x0D4B316A, 0x0E3CF31B, 0x0F3FE155, 0x10553469, 0x117E3AD9, 0x12BC5AEA, 1303 0x14111457, 0x157E0219, 0x1704DC5E, 0x18A77A97, 0x1A67D5B6, 0x1C480A87, 1304 0x1E4A5C45, 0x2071374D, 0x22BF3412, 0x25371A37, 0x27DBE3EF, 0x2AB0C18F, 1305 0x2DB91D6F, 0x30F89FFD, 0x34733433, 0x382D0C46, 0x3C2AA6BD, 0x4070D3D9, 1306 0x4504BB66, 0x49EBE2F1, 0x4F2C346F, 0x54CC0565, 0x5AD21E86, 0x6145C3E7, 1307 0x682EBDBD, 0x6F9561C4, 0x77829D4D, 1308 0x7fffffff 1309 }; 1310 1311 static int 1312 emu10k_convert_fixpoint(int val) 1313 { 1314 if (val < 0) 1315 val = 0; 1316 if (val > 100) 1317 val = 100; 1318 return (db2lin_101[val]); 1319 } 1320 1321 static void 1322 emu10k_write_gpr(emu10k_devc_t *devc, int gpr, uint32_t value) 1323 { 1324 ASSERT(gpr < MAX_GPR); 1325 devc->gpr_shadow[gpr].valid = B_TRUE; 1326 devc->gpr_shadow[gpr].value = value; 1327 emu10k_write_reg(devc, gpr + GPR0, 0, value); 1328 } 1329 1330 static int 1331 emu10k_set_stereo(void *arg, uint64_t val) 1332 { 1333 emu10k_ctrl_t *ec = arg; 1334 emu10k_devc_t *devc = ec->devc; 1335 uint32_t left, right; 1336 1337 left = (val >> 8) & 0xff; 1338 right = val & 0xff; 1339 if ((left > 100) || (right > 100) || (val & ~(0xffff))) 1340 return (EINVAL); 1341 1342 left = emu10k_convert_fixpoint(left); 1343 right = emu10k_convert_fixpoint(right); 1344 1345 mutex_enter(&devc->mutex); 1346 ec->val = val; 1347 1348 emu10k_write_gpr(devc, ec->gpr_num, left); 1349 emu10k_write_gpr(devc, ec->gpr_num + 1, right); 1350 1351 mutex_exit(&devc->mutex); 1352 return (0); 1353 } 1354 1355 static int 1356 emu10k_set_mono(void *arg, uint64_t val) 1357 { 1358 emu10k_ctrl_t *ec = arg; 1359 emu10k_devc_t *devc = ec->devc; 1360 uint32_t v; 1361 1362 if (val > 100) 1363 return (EINVAL); 1364 1365 v = emu10k_convert_fixpoint(val & 0xff); 1366 1367 mutex_enter(&devc->mutex); 1368 ec->val = val; 1369 emu10k_write_gpr(devc, ec->gpr_num, v); 1370 mutex_exit(&devc->mutex); 1371 return (0); 1372 } 1373 1374 static int 1375 emu10k_get_control(void *arg, uint64_t *val) 1376 { 1377 emu10k_ctrl_t *ec = arg; 1378 emu10k_devc_t *devc = ec->devc; 1379 1380 mutex_enter(&devc->mutex); 1381 *val = ec->val; 1382 mutex_exit(&devc->mutex); 1383 return (0); 1384 } 1385 1386 #define PLAYCTL (AUDIO_CTRL_FLAG_RW | AUDIO_CTRL_FLAG_PLAY) 1387 #define RECCTL (AUDIO_CTRL_FLAG_RW | AUDIO_CTRL_FLAG_REC) 1388 #define MONCTL (AUDIO_CTRL_FLAG_RW | AUDIO_CTRL_FLAG_MONITOR) 1389 #define MAINVOL (PLAYCTL | AUDIO_CTRL_FLAG_MAINVOL) 1390 #define PCMVOL (PLAYCTL | AUDIO_CTRL_FLAG_PCMVOL) 1391 #define RECVOL (RECCTL | AUDIO_CTRL_FLAG_RECVOL) 1392 #define MONVOL (MONCTL | AUDIO_CTRL_FLAG_MONVOL) 1393 1394 static int 1395 emu10k_get_ac97src(void *arg, uint64_t *valp) 1396 { 1397 ac97_ctrl_t *ctrl = arg; 1398 1399 return (ac97_control_get(ctrl, valp)); 1400 } 1401 1402 static int 1403 emu10k_set_ac97src(void *arg, uint64_t value) 1404 { 1405 ac97_ctrl_t *ctrl = arg; 1406 1407 return (ac97_control_set(ctrl, value)); 1408 } 1409 1410 static int 1411 emu10k_set_jack3(void *arg, uint64_t value) 1412 { 1413 emu10k_ctrl_t *ec = arg; 1414 emu10k_devc_t *devc = ec->devc; 1415 uint32_t set_val; 1416 uint32_t val; 1417 1418 set_val = ddi_ffs(value & 0xffffffffU); 1419 set_val--; 1420 mutex_enter(&devc->mutex); 1421 switch (set_val) { 1422 case 0: 1423 case 1: 1424 break; 1425 default: 1426 mutex_exit(&devc->mutex); 1427 return (EINVAL); 1428 } 1429 ec->val = value; 1430 /* center/lfe */ 1431 if (devc->feature_mask & SB_INVSP) { 1432 set_val = !set_val; 1433 } 1434 if (devc->feature_mask & (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL)) { 1435 val = INL(devc, devc->regs + 0x18); 1436 val &= ~A_IOCFG_GPOUT0; 1437 val |= set_val ? 0x44 : 0x40; 1438 OUTL(devc, val, devc->regs + 0x18); 1439 1440 } else if (devc->feature_mask & SB_LIVE) { 1441 val = INL(devc, devc->regs + HCFG); 1442 val &= ~HCFG_GPOUT0; 1443 val |= set_val ? HCFG_GPOUT0 : 0; 1444 OUTL(devc, val, devc->regs + HCFG); 1445 } 1446 mutex_exit(&devc->mutex); 1447 return (0); 1448 } 1449 1450 static int 1451 emu10k_set_recsrc(void *arg, uint64_t value) 1452 { 1453 emu10k_ctrl_t *ec = arg; 1454 emu10k_devc_t *devc = ec->devc; 1455 uint32_t set_val; 1456 1457 set_val = ddi_ffs(value & 0xffffffffU); 1458 set_val--; 1459 1460 /* 1461 * We start assuming well set up AC'97 for stereomix recording. 1462 */ 1463 switch (set_val) { 1464 case INPUT_AC97: 1465 case INPUT_SPD1: 1466 case INPUT_SPD2: 1467 case INPUT_DIGCD: 1468 case INPUT_AUX2: 1469 case INPUT_LINE2: 1470 case INPUT_STEREOMIX: 1471 break; 1472 default: 1473 return (EINVAL); 1474 } 1475 1476 mutex_enter(&devc->mutex); 1477 ec->val = value; 1478 1479 emu10k_write_gpr(devc, GPR_REC_AC97, (set_val == INPUT_AC97)); 1480 emu10k_write_gpr(devc, GPR_REC_SPDIF1, (set_val == INPUT_SPD1)); 1481 emu10k_write_gpr(devc, GPR_REC_SPDIF2, (set_val == INPUT_SPD2)); 1482 emu10k_write_gpr(devc, GPR_REC_DIGCD, (set_val == INPUT_DIGCD)); 1483 emu10k_write_gpr(devc, GPR_REC_AUX2, (set_val == INPUT_AUX2)); 1484 emu10k_write_gpr(devc, GPR_REC_LINE2, (set_val == INPUT_LINE2)); 1485 emu10k_write_gpr(devc, GPR_REC_PCM, (set_val == INPUT_STEREOMIX)); 1486 1487 mutex_exit(&devc->mutex); 1488 1489 return (0); 1490 } 1491 1492 static void 1493 emu10k_create_stereo(emu10k_devc_t *devc, int ctl, int gpr, 1494 const char *id, int flags, int defval) 1495 { 1496 emu10k_ctrl_t *ec; 1497 audio_ctrl_desc_t desc; 1498 1499 bzero(&desc, sizeof (desc)); 1500 1501 ec = &devc->ctrls[ctl]; 1502 ec->devc = devc; 1503 ec->gpr_num = gpr; 1504 1505 desc.acd_name = id; 1506 desc.acd_type = AUDIO_CTRL_TYPE_STEREO; 1507 desc.acd_minvalue = 0; 1508 desc.acd_maxvalue = 100; 1509 desc.acd_flags = flags; 1510 1511 ec->val = (defval << 8) | defval; 1512 ec->ctrl = audio_dev_add_control(devc->adev, &desc, 1513 emu10k_get_control, emu10k_set_stereo, ec); 1514 1515 mutex_enter(&devc->mutex); 1516 emu10k_write_gpr(devc, gpr, emu10k_convert_fixpoint(defval)); 1517 emu10k_write_gpr(devc, gpr + 1, emu10k_convert_fixpoint(defval)); 1518 mutex_exit(&devc->mutex); 1519 } 1520 1521 static void 1522 emu10k_create_mono(emu10k_devc_t *devc, int ctl, int gpr, 1523 const char *id, int flags, int defval) 1524 { 1525 emu10k_ctrl_t *ec; 1526 audio_ctrl_desc_t desc; 1527 1528 bzero(&desc, sizeof (desc)); 1529 1530 ec = &devc->ctrls[ctl]; 1531 ec->devc = devc; 1532 ec->gpr_num = gpr; 1533 1534 desc.acd_name = id; 1535 desc.acd_type = AUDIO_CTRL_TYPE_MONO; 1536 desc.acd_minvalue = 0; 1537 desc.acd_maxvalue = 100; 1538 desc.acd_flags = flags; 1539 1540 ec->val = defval; 1541 ec->ctrl = audio_dev_add_control(devc->adev, &desc, 1542 emu10k_get_control, emu10k_set_mono, ec); 1543 1544 mutex_enter(&devc->mutex); 1545 emu10k_write_gpr(devc, gpr, emu10k_convert_fixpoint(defval)); 1546 mutex_exit(&devc->mutex); 1547 } 1548 1549 /* 1550 * AC'97 source. The AC'97 PCM record channel is routed to our 1551 * mixer. While we could support the direct monitoring capability of 1552 * the AC'97 part itself, this would not work correctly with outputs 1553 * that are not routed via AC'97 (such as the Live Drive headphones 1554 * or digital outputs.) So we just offer the ability to select one 1555 * AC'97 source, and then offer independent ability to either monitor 1556 * or record from the AC'97 mixer's PCM record channel. 1557 */ 1558 static void 1559 emu10k_create_ac97src(emu10k_devc_t *devc) 1560 { 1561 emu10k_ctrl_t *ec; 1562 audio_ctrl_desc_t desc; 1563 ac97_ctrl_t *ac; 1564 const audio_ctrl_desc_t *acd; 1565 1566 bzero(&desc, sizeof (desc)); 1567 1568 ec = &devc->ctrls[CTL_AC97SRC]; 1569 desc.acd_name = "ac97-source"; 1570 desc.acd_type = AUDIO_CTRL_TYPE_ENUM; 1571 desc.acd_flags = RECCTL; 1572 ec->devc = devc; 1573 ac = ac97_control_find(devc->ac97, AUDIO_CTRL_ID_RECSRC); 1574 if (ac == NULL) { 1575 return; 1576 } 1577 1578 acd = ac97_control_desc(ac); 1579 1580 for (int i = 0; i < 64; i++) { 1581 const char *n; 1582 if (((acd->acd_minvalue & (1ULL << i)) == 0) || 1583 ((n = acd->acd_enum[i]) == NULL)) { 1584 continue; 1585 } 1586 desc.acd_enum[i] = acd->acd_enum[i]; 1587 /* we suppress some port options */ 1588 if ((strcmp(n, AUDIO_PORT_STEREOMIX) == 0) || 1589 (strcmp(n, AUDIO_PORT_MONOMIX) == 0) || 1590 (strcmp(n, AUDIO_PORT_VIDEO) == 0)) { 1591 continue; 1592 } 1593 desc.acd_minvalue |= (1ULL << i); 1594 desc.acd_maxvalue |= (1ULL << i); 1595 } 1596 1597 ec->ctrl = audio_dev_add_control(devc->adev, &desc, 1598 emu10k_get_ac97src, emu10k_set_ac97src, ac); 1599 } 1600 1601 /* 1602 * Record source... this one is tricky. While the chip will 1603 * conceivably let us *mix* some of the audio streams for recording, 1604 * the AC'97 inputs don't have this capability. Offering it to users 1605 * is likely to be confusing, so we offer a single record source 1606 * selection option. Its not ideal, but it ought to be good enough 1607 * for the vast majority of users. 1608 */ 1609 static void 1610 emu10k_create_recsrc(emu10k_devc_t *devc) 1611 { 1612 emu10k_ctrl_t *ec; 1613 audio_ctrl_desc_t desc; 1614 ac97_ctrl_t *ac; 1615 1616 bzero(&desc, sizeof (desc)); 1617 1618 ec = &devc->ctrls[CTL_RECSRC]; 1619 desc.acd_name = AUDIO_CTRL_ID_RECSRC; 1620 desc.acd_type = AUDIO_CTRL_TYPE_ENUM; 1621 desc.acd_flags = RECCTL; 1622 desc.acd_minvalue = 0; 1623 desc.acd_maxvalue = 0; 1624 bzero(desc.acd_enum, sizeof (desc.acd_enum)); 1625 ec->devc = devc; 1626 ac = ac97_control_find(devc->ac97, AUDIO_CTRL_ID_RECSRC); 1627 1628 /* only low order bits set by AC'97 */ 1629 ASSERT(desc.acd_minvalue == desc.acd_maxvalue); 1630 ASSERT((desc.acd_minvalue & ~0xffff) == 0); 1631 1632 /* 1633 * It would be really cool if we could detect whether these 1634 * options are all sensible on a given configuration. Units 1635 * without live-drive support, and units without a physical 1636 * live-drive, simply can't do all these. 1637 */ 1638 if (ac != NULL) { 1639 desc.acd_minvalue |= (1 << INPUT_AC97); 1640 desc.acd_maxvalue |= (1 << INPUT_AC97); 1641 desc.acd_enum[INPUT_AC97] = "ac97"; 1642 ec->val = (1 << INPUT_AC97); 1643 } else { 1644 /* next best guess */ 1645 ec->val = (1 << INPUT_LINE2); 1646 } 1647 1648 desc.acd_minvalue |= (1 << INPUT_SPD1); 1649 desc.acd_maxvalue |= (1 << INPUT_SPD1); 1650 desc.acd_enum[INPUT_SPD1] = AUDIO_PORT_SPDIFIN; 1651 1652 desc.acd_minvalue |= (1 << INPUT_SPD2); 1653 desc.acd_maxvalue |= (1 << INPUT_SPD2); 1654 desc.acd_enum[INPUT_SPD2] = "spdif2-in"; 1655 1656 desc.acd_minvalue |= (1 << INPUT_DIGCD); 1657 desc.acd_maxvalue |= (1 << INPUT_DIGCD); 1658 desc.acd_enum[INPUT_DIGCD] = "digital-cd"; 1659 1660 desc.acd_minvalue |= (1 << INPUT_AUX2); 1661 desc.acd_maxvalue |= (1 << INPUT_AUX2); 1662 desc.acd_enum[INPUT_AUX2] = AUDIO_PORT_AUX2IN; 1663 1664 desc.acd_minvalue |= (1 << INPUT_LINE2); 1665 desc.acd_maxvalue |= (1 << INPUT_LINE2); 1666 desc.acd_enum[INPUT_LINE2] = "line2-in"; 1667 1668 desc.acd_minvalue |= (1 << INPUT_STEREOMIX); 1669 desc.acd_maxvalue |= (1 << INPUT_STEREOMIX); 1670 desc.acd_enum[INPUT_STEREOMIX] = AUDIO_PORT_STEREOMIX; 1671 1672 emu10k_write_gpr(devc, GPR_REC_SPDIF1, 0); 1673 emu10k_write_gpr(devc, GPR_REC_SPDIF2, 0); 1674 emu10k_write_gpr(devc, GPR_REC_DIGCD, 0); 1675 emu10k_write_gpr(devc, GPR_REC_AUX2, 0); 1676 emu10k_write_gpr(devc, GPR_REC_LINE2, 0); 1677 emu10k_write_gpr(devc, GPR_REC_PCM, 0); 1678 emu10k_write_gpr(devc, GPR_REC_AC97, 1); 1679 1680 ec->ctrl = audio_dev_add_control(devc->adev, &desc, 1681 emu10k_get_control, emu10k_set_recsrc, ec); 1682 } 1683 1684 static void 1685 emu10k_create_jack3(emu10k_devc_t *devc) 1686 { 1687 emu10k_ctrl_t *ec; 1688 audio_ctrl_desc_t desc; 1689 1690 bzero(&desc, sizeof (desc)); 1691 1692 ec = &devc->ctrls[CTL_JACK3]; 1693 desc.acd_name = AUDIO_CTRL_ID_JACK3; 1694 desc.acd_type = AUDIO_CTRL_TYPE_ENUM; 1695 desc.acd_flags = AUDIO_CTRL_FLAG_RW; 1696 desc.acd_minvalue = 0x3; 1697 desc.acd_maxvalue = 0x3; 1698 bzero(desc.acd_enum, sizeof (desc.acd_enum)); 1699 ec->devc = devc; 1700 ec->val = 0x1; 1701 1702 desc.acd_enum[0] = AUDIO_PORT_CENLFE; 1703 desc.acd_enum[1] = AUDIO_PORT_SPDIFOUT; 1704 1705 ec->ctrl = audio_dev_add_control(devc->adev, &desc, 1706 emu10k_get_control, emu10k_set_jack3, ec); 1707 } 1708 1709 1710 static void 1711 emu10k_create_controls(emu10k_devc_t *devc) 1712 { 1713 ac97_t *ac97; 1714 ac97_ctrl_t *ac; 1715 1716 emu10k_create_mono(devc, CTL_VOLUME, GPR_VOL_PCM, 1717 AUDIO_CTRL_ID_VOLUME, PCMVOL, 75); 1718 1719 emu10k_create_stereo(devc, CTL_FRONT, GPR_VOL_FRONT, 1720 AUDIO_CTRL_ID_FRONT, MAINVOL, 100); 1721 emu10k_create_stereo(devc, CTL_SURROUND, GPR_VOL_SURR, 1722 AUDIO_CTRL_ID_SURROUND, MAINVOL, 100); 1723 if (devc->feature_mask & (SB_51 | SB_71)) { 1724 emu10k_create_mono(devc, CTL_CENTER, GPR_VOL_CEN, 1725 AUDIO_CTRL_ID_CENTER, MAINVOL, 100); 1726 emu10k_create_mono(devc, CTL_LFE, GPR_VOL_LFE, 1727 AUDIO_CTRL_ID_LFE, MAINVOL, 100); 1728 } 1729 if (devc->feature_mask & SB_71) { 1730 emu10k_create_stereo(devc, CTL_SIDE, GPR_VOL_SIDE, 1731 "side", MAINVOL, 100); 1732 } 1733 1734 emu10k_create_stereo(devc, CTL_RECGAIN, GPR_VOL_REC, 1735 AUDIO_CTRL_ID_RECGAIN, RECVOL, 50); 1736 1737 emu10k_create_ac97src(devc); 1738 emu10k_create_recsrc(devc); 1739 /* 1740 * 5.1 devices have versa jack. Note that from what we can 1741 * tell, none of the 7.1 devices have or need this versa jack, 1742 * as they all seem to have a dedicated digital I/O port. 1743 */ 1744 if ((devc->feature_mask & SB_51) && 1745 !(devc->feature_mask & SB_AUDIGY2VAL)) { 1746 emu10k_create_jack3(devc); 1747 } 1748 1749 /* these ones AC'97 can manage directly */ 1750 ac97 = devc->ac97; 1751 1752 if ((ac = ac97_control_find(ac97, AUDIO_CTRL_ID_MICBOOST)) != NULL) 1753 ac97_control_register(ac); 1754 if ((ac = ac97_control_find(ac97, AUDIO_CTRL_ID_MICGAIN)) != NULL) 1755 ac97_control_register(ac); 1756 1757 /* set any AC'97 analog outputs to full volume (no attenuation) */ 1758 if ((ac = ac97_control_find(ac97, AUDIO_CTRL_ID_FRONT)) != NULL) 1759 (void) ac97_control_set(ac, (100 << 8) | 100); 1760 if ((ac = ac97_control_find(ac97, AUDIO_CTRL_ID_LINEOUT)) != NULL) 1761 (void) ac97_control_set(ac, (100 << 8) | 100); 1762 if ((ac = ac97_control_find(ac97, AUDIO_CTRL_ID_SURROUND)) != NULL) 1763 (void) ac97_control_set(ac, (100 << 8) | 100); 1764 if ((ac = ac97_control_find(ac97, AUDIO_CTRL_ID_CENTER)) != NULL) 1765 (void) ac97_control_set(ac, 100); 1766 if ((ac = ac97_control_find(ac97, AUDIO_CTRL_ID_LFE)) != NULL) 1767 (void) ac97_control_set(ac, 100); 1768 1769 /* Monitor sources */ 1770 emu10k_create_stereo(devc, CTL_AC97, GPR_MON_AC97, 1771 "ac97-monitor", MONVOL, 0); 1772 emu10k_create_stereo(devc, CTL_SPD1, GPR_MON_SPDIF1, 1773 AUDIO_PORT_SPDIFIN, MONVOL, 0); 1774 emu10k_create_stereo(devc, CTL_DIGCD, GPR_MON_DIGCD, 1775 "digital-cd", MONVOL, 0); 1776 emu10k_create_stereo(devc, CTL_SPD1, GPR_MON_SPDIF1, 1777 AUDIO_PORT_SPDIFIN, MONVOL, 0); 1778 1779 if ((devc->feature_mask & SB_NOEXP) == 0) { 1780 /* 1781 * These ports are only available via an external 1782 * expansion box. Don't expose them for cards that 1783 * don't have support for it. 1784 */ 1785 emu10k_create_stereo(devc, CTL_HEADPH, GPR_VOL_HEADPH, 1786 AUDIO_CTRL_ID_HEADPHONE, MAINVOL, 100); 1787 emu10k_create_stereo(devc, CTL_SPD2, GPR_MON_SPDIF2, 1788 "spdif2-in", MONVOL, 0); 1789 emu10k_create_stereo(devc, CTL_LINE2, GPR_MON_LINE2, 1790 "line2-in", MONVOL, 0); 1791 emu10k_create_stereo(devc, CTL_AUX2, GPR_MON_AUX2, 1792 AUDIO_PORT_AUX2IN, MONVOL, 0); 1793 } 1794 } 1795 1796 static void 1797 emu10k_load_dsp(emu10k_devc_t *devc, uint32_t *code, int ncode, 1798 uint32_t *init, int ninit) 1799 { 1800 int i; 1801 1802 if (ncode > 1024) { 1803 audio_dev_warn(devc->adev, "DSP file size too big"); 1804 return; 1805 } 1806 if (ninit > MAX_GPR) { 1807 audio_dev_warn(devc->adev, "Too many inits"); 1808 return; 1809 } 1810 1811 /* Upload our DSP code */ 1812 for (i = 0; i < ncode; i++) { 1813 emu10k_write_efx(devc, UC0 + i, code[i]); 1814 } 1815 1816 /* Upload the initialization settings */ 1817 for (i = 0; i < ninit; i += 2) { 1818 emu10k_write_reg(devc, init[i] + GPR0, 0, init[i + 1]); 1819 } 1820 } 1821 1822 #define LIVE_NOP() \ 1823 emu10k_write_efx(devc, UC0 + (pc * 2), 0x10040); \ 1824 emu10k_write_efx(devc, UC0 + (pc * 2 + 1), 0x610040); \ 1825 pc++ 1826 #define LIVE_ACC3(r, a, x, y) /* z=w+x+y */ \ 1827 emu10k_write_efx(devc, UC0 + (pc * 2), (x << 10) | y); \ 1828 emu10k_write_efx(devc, UC0 + (pc * 2 + 1), (6 << 20) | (r << 10) | a); \ 1829 pc++ 1830 1831 #define AUDIGY_ACC3(r, a, x, y) /* z=w+x+y */ \ 1832 emu10k_write_efx(devc, UC0 + (pc * 2), (x << 12) | y); \ 1833 emu10k_write_efx(devc, UC0 + (pc * 2+1), (6 << 24) | (r << 12) | a); \ 1834 pc++ 1835 #define AUDIGY_NOP() AUDIGY_ACC3(0xc0, 0xc0, 0xc0, 0xc0) 1836 1837 static void 1838 emu10k_init_effects(emu10k_devc_t *devc) 1839 { 1840 int i; 1841 unsigned short pc; 1842 1843 ASSERT(mutex_owned(&devc->mutex)); 1844 1845 if (devc->feature_mask & (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL)) { 1846 pc = 0; 1847 for (i = 0; i < 512; i++) { 1848 AUDIGY_NOP(); 1849 } 1850 1851 for (i = 0; i < 256; i++) 1852 emu10k_write_efx(devc, GPR0 + i, 0); 1853 emu10k_write_reg(devc, AUDIGY_DBG, 0, 0); 1854 emu10k_load_dsp(devc, 1855 emu10k2_code, 1856 sizeof (emu10k2_code) / sizeof (emu10k2_code[0]), 1857 emu10k2_init, 1858 sizeof (emu10k2_init) / sizeof (emu10k2_init[0])); 1859 1860 } else { 1861 pc = 0; 1862 for (i = 0; i < 512; i++) { 1863 LIVE_NOP(); 1864 } 1865 1866 for (i = 0; i < 256; i++) 1867 emu10k_write_efx(devc, GPR0 + i, 0); 1868 emu10k_write_reg(devc, DBG, 0, 0); 1869 emu10k_load_dsp(devc, 1870 emu10k1_code, 1871 sizeof (emu10k1_code) / sizeof (emu10k1_code[0]), 1872 emu10k1_init, 1873 sizeof (emu10k1_init) / sizeof (emu10k1_init[0])); 1874 } 1875 } 1876 1877 /* mixer */ 1878 1879 static struct { 1880 uint16_t devid; 1881 uint16_t subid; 1882 const char *model; 1883 const char *prod; 1884 unsigned feature_mask; 1885 } emu10k_cards[] = { 1886 { 0x2, 0x0020, "CT4670", "Live! Value", SB_LIVE | SB_NOEXP }, 1887 { 0x2, 0x0021, "CT4621", "Live!", SB_LIVE }, 1888 { 0x2, 0x100a, "SB0220", "Live! 5.1 Digital", 1889 SB_LIVE | SB_51 | SB_NOEXP }, 1890 { 0x2, 0x8022, "CT4780", "Live! Value", SB_LIVE }, 1891 { 0x2, 0x8023, "CT4790", "PCI512", SB_LIVE | SB_NOEXP }, 1892 { 0x2, 0x8026, "CT4830", "Live! Value", SB_LIVE }, 1893 { 0x2, 0x8028, "CT4870", "Live! Value", SB_LIVE }, 1894 { 0x2, 0x8031, "CT4831", "Live! Value", SB_LIVE }, 1895 { 0x2, 0x8040, "CT4760", "Live!", SB_LIVE }, 1896 { 0x2, 0x8051, "CT4850", "Live! Value", SB_LIVE }, 1897 { 0x2, 0x8061, "SB0060", "Live! 5.1", SB_LIVE | SB_51 }, 1898 { 0x2, 0x8064, "SB0100", "Live! 5.1", SB_LIVE | SB_51 }, 1899 { 0x2, 0x8065, "SB0220", "Live! 5.1", SB_LIVE | SB_51 }, 1900 { 0x2, 0x8066, "SB0228", "Live! 5.1", SB_LIVE | SB_51 }, 1901 { 0x4, 0x0051, "SB0090", "Audigy", SB_AUDIGY | SB_51 }, 1902 { 0x4, 0x0052, "SB0160", "Audigy ES", SB_AUDIGY | SB_51 }, 1903 { 0x4, 0x0053, "SB0092", "Audigy", SB_AUDIGY | SB_51 }, 1904 { 0x4, 0x1002, "SB0240P", "Audigy 2 Platinum", 1905 SB_AUDIGY2 | SB_71 | SB_INVSP }, 1906 { 0x4, 0x1003, "SB0353", "Audigy 2 ZS", SB_AUDIGY2 | SB_71 | SB_INVSP }, 1907 { 0x4, 0x1005, "SB0280", "Audigy 2 Platinum EX", SB_AUDIGY2 | SB_71 }, 1908 { 0x4, 0x1007, "SB0240", "Audigy 2", SB_AUDIGY2 | SB_71 }, 1909 { 0x4, 0x2001, "SB0360", "Audigy 2 ZS", SB_AUDIGY2 | SB_71 | SB_INVSP }, 1910 { 0x4, 0x2002, "SB0350", "Audigy 2 ZS", SB_AUDIGY2 | SB_71 | SB_INVSP }, 1911 { 0x4, 0x2006, "SB0350", "Audigy 2", SB_AUDIGY2 | SB_71 | SB_INVSP }, 1912 { 0x4, 0x2007, "SB0380", "Audigy 4 Pro", SB_AUDIGY2 | SB_71 }, 1913 { 0x8, 0x1001, "SB0400", "Audigy 2 Value", 1914 SB_AUDIGY2VAL | SB_71 | SB_NOEXP }, 1915 { 0x8, 0x1021, "SB0610", "Audigy 4", 1916 SB_AUDIGY2VAL | SB_71 | SB_NOEXP }, 1917 { 0x8, 0x2001, "SB0530", "Audigy 2 ZS Notebook", 1918 SB_AUDIGY2VAL | SB_71 }, 1919 { 0, 0, NULL, NULL, 0 }, 1920 }; 1921 1922 int 1923 emu10k_attach(dev_info_t *dip) 1924 { 1925 uint16_t pci_command; 1926 uint16_t subid; 1927 uint16_t devid; 1928 emu10k_devc_t *devc; 1929 ddi_acc_handle_t pcih; 1930 ddi_dma_cookie_t cookie; 1931 uint_t count; 1932 ulong_t len; 1933 int i; 1934 const char *name; 1935 const char *model; 1936 char namebuf[64]; 1937 int feature_mask; 1938 1939 devc = kmem_zalloc(sizeof (*devc), KM_SLEEP); 1940 devc->dip = dip; 1941 ddi_set_driver_private(dip, devc); 1942 1943 if ((devc->adev = audio_dev_alloc(dip, 0)) == NULL) { 1944 cmn_err(CE_WARN, "audio_dev_alloc failed"); 1945 goto error; 1946 } 1947 1948 if (pci_config_setup(dip, &pcih) != DDI_SUCCESS) { 1949 audio_dev_warn(devc->adev, "pci_config_setup failed"); 1950 goto error; 1951 } 1952 devc->pcih = pcih; 1953 1954 devid = pci_config_get16(pcih, PCI_CONF_DEVID); 1955 subid = pci_config_get16(pcih, PCI_CONF_SUBSYSID); 1956 1957 pci_command = pci_config_get16(pcih, PCI_CONF_COMM); 1958 pci_command |= PCI_COMM_ME | PCI_COMM_IO; 1959 pci_config_put16(pcih, PCI_CONF_COMM, pci_command); 1960 1961 if ((ddi_regs_map_setup(dip, 1, &devc->regs, 0, 0, &dev_attr, 1962 &devc->regsh)) != DDI_SUCCESS) { 1963 audio_dev_warn(devc->adev, "failed to map registers"); 1964 goto error; 1965 } 1966 1967 switch (devid) { 1968 case PCI_DEVICE_ID_SBLIVE: 1969 name = "Live!"; 1970 model = "CT????"; 1971 feature_mask = SB_LIVE; 1972 break; 1973 1974 case PCI_DEVICE_ID_AUDIGYVALUE: 1975 name = "Audigy 2 Value"; 1976 model = "SB????"; 1977 feature_mask = SB_AUDIGY2VAL; 1978 break; 1979 1980 case PCI_DEVICE_ID_AUDIGY: 1981 if (subid >= 0x1002 && subid <= 0x2005) { 1982 name = "Audigy 2"; 1983 model = "SB????"; 1984 feature_mask = SB_AUDIGY2; 1985 } else { 1986 name = "Audigy"; 1987 model = "SB????"; 1988 feature_mask = SB_AUDIGY; 1989 } 1990 break; 1991 1992 default: 1993 audio_dev_warn(devc->adev, "Unrecognized device"); 1994 goto error; 1995 } 1996 1997 for (i = 0; emu10k_cards[i].prod; i++) { 1998 if ((devid == emu10k_cards[i].devid) && 1999 (subid == emu10k_cards[i].subid)) { 2000 name = emu10k_cards[i].prod; 2001 model = emu10k_cards[i].model; 2002 feature_mask = emu10k_cards[i].feature_mask; 2003 break; 2004 } 2005 } 2006 devc->feature_mask = feature_mask; 2007 2008 (void) snprintf(namebuf, sizeof (namebuf), "Sound Blaster %s", name); 2009 2010 audio_dev_set_description(devc->adev, namebuf); 2011 audio_dev_set_version(devc->adev, model); 2012 2013 mutex_init(&devc->mutex, NULL, MUTEX_DRIVER, 0); 2014 2015 /* allocate static page table memory */ 2016 2017 devc->max_mem = AUDIO_MEMSIZE; 2018 2019 /* SB Live/Audigy supports at most 32M of memory) */ 2020 if (devc->max_mem > 32 * 1024 * 1024) 2021 devc->max_mem = 32 * 1024 * 1024; 2022 2023 devc->max_pages = devc->max_mem / 4096; 2024 if (devc->max_pages < 1024) 2025 devc->max_pages = 1024; 2026 2027 /* Allocate page table */ 2028 if (ddi_dma_alloc_handle(devc->dip, &dma_attr_buf, DDI_DMA_SLEEP, NULL, 2029 &devc->pt_dmah) != DDI_SUCCESS) { 2030 audio_dev_warn(devc->adev, 2031 "failed to allocate page table handle"); 2032 goto error; 2033 } 2034 2035 if (ddi_dma_mem_alloc(devc->pt_dmah, devc->max_pages * 4, 2036 &dev_attr, DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, 2037 &devc->pt_kaddr, &len, &devc->pt_acch) != 2038 DDI_SUCCESS) { 2039 audio_dev_warn(devc->adev, 2040 "failed to allocate memory for page table"); 2041 goto error; 2042 } 2043 2044 if (ddi_dma_addr_bind_handle(devc->pt_dmah, NULL, 2045 devc->pt_kaddr, len, DDI_DMA_CONSISTENT | DDI_DMA_WRITE, 2046 DDI_DMA_SLEEP, NULL, &cookie, &count) != DDI_SUCCESS) { 2047 audio_dev_warn(devc->adev, 2048 "failed binding page table DMA handle"); 2049 goto error; 2050 } 2051 2052 devc->page_map = (void *)devc->pt_kaddr; 2053 devc->pt_paddr = cookie.dmac_address; 2054 bzero(devc->pt_kaddr, devc->max_pages * 4); 2055 2056 /* Allocate silent page */ 2057 if (ddi_dma_alloc_handle(devc->dip, &dma_attr_buf, DDI_DMA_SLEEP, NULL, 2058 &devc->silence_dmah) != DDI_SUCCESS) { 2059 audio_dev_warn(devc->adev, 2060 "failed to allocate silent page handle"); 2061 goto error; 2062 } 2063 2064 if (ddi_dma_mem_alloc(devc->silence_dmah, 4096, 2065 &buf_attr, DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, 2066 &devc->silence_kaddr, &len, 2067 &devc->silence_acch) != DDI_SUCCESS) { 2068 audio_dev_warn(devc->adev, 2069 "failed to allocate silent page memory"); 2070 goto error; 2071 } 2072 2073 (void) ddi_dma_sync(devc->silence_dmah, 0, 0, DDI_DMA_SYNC_FORDEV); 2074 2075 if (ddi_dma_addr_bind_handle(devc->silence_dmah, NULL, 2076 devc->silence_kaddr, len, DDI_DMA_CONSISTENT | DDI_DMA_WRITE, 2077 DDI_DMA_SLEEP, NULL, &cookie, &count) != DDI_SUCCESS) { 2078 audio_dev_warn(devc->adev, 2079 "failed binding silent page DMA handle"); 2080 goto error; 2081 } 2082 2083 devc->silence_paddr = cookie.dmac_address; 2084 bzero(devc->silence_kaddr, 4096); 2085 devc->audio_memptr = 4096; /* Skip the silence page */ 2086 2087 for (i = 0; i < devc->max_pages; i++) 2088 FILL_PAGE_MAP_ENTRY(i, devc->silence_paddr); 2089 2090 (void) ddi_dma_sync(devc->pt_dmah, 0, 0, DDI_DMA_SYNC_FORDEV); 2091 2092 devc->ac97 = ac97_allocate(devc->adev, dip, 2093 emu10k_read_ac97, emu10k_write_ac97, devc); 2094 if (devc->ac97 == NULL) { 2095 audio_dev_warn(devc->adev, "failed to allocate ac97 handle"); 2096 goto error; 2097 } 2098 2099 ac97_probe_controls(devc->ac97); 2100 2101 /* allocate voice 0 for play */ 2102 if (emu10k_alloc_port(devc, EMU10K_REC) != DDI_SUCCESS) 2103 goto error; 2104 2105 if (emu10k_alloc_port(devc, EMU10K_PLAY) != DDI_SUCCESS) 2106 goto error; 2107 2108 /* now initialize the hardware */ 2109 mutex_enter(&devc->mutex); 2110 if (emu10k_hwinit(devc) != DDI_SUCCESS) { 2111 mutex_exit(&devc->mutex); 2112 goto error; 2113 } 2114 mutex_exit(&devc->mutex); 2115 2116 emu10k_create_controls(devc); 2117 2118 if (audio_dev_register(devc->adev) != DDI_SUCCESS) { 2119 audio_dev_warn(devc->adev, "unable to register audio device"); 2120 goto error; 2121 } 2122 2123 ddi_report_dev(dip); 2124 2125 return (DDI_SUCCESS); 2126 2127 error: 2128 emu10k_destroy(devc); 2129 return (DDI_FAILURE); 2130 } 2131 2132 int 2133 emu10k_resume(dev_info_t *dip) 2134 { 2135 emu10k_devc_t *devc; 2136 2137 devc = ddi_get_driver_private(dip); 2138 2139 mutex_enter(&devc->mutex); 2140 if (emu10k_hwinit(devc) != DDI_SUCCESS) { 2141 mutex_exit(&devc->mutex); 2142 /* 2143 * In case of failure, we leave the chip suspended, 2144 * but don't panic. Audio service is not normally a a 2145 * critical service. 2146 */ 2147 audio_dev_warn(devc->adev, "FAILED to RESUME device"); 2148 return (DDI_SUCCESS); 2149 } 2150 2151 mutex_exit(&devc->mutex); 2152 2153 /* resume ac97 */ 2154 ac97_reset(devc->ac97); 2155 2156 audio_dev_resume(devc->adev); 2157 2158 return (DDI_SUCCESS); 2159 } 2160 2161 int 2162 emu10k_detach(emu10k_devc_t *devc) 2163 { 2164 if (audio_dev_unregister(devc->adev) != DDI_SUCCESS) 2165 return (DDI_FAILURE); 2166 2167 emu10k_destroy(devc); 2168 return (DDI_SUCCESS); 2169 } 2170 2171 int 2172 emu10k_suspend(emu10k_devc_t *devc) 2173 { 2174 audio_dev_suspend(devc->adev); 2175 2176 return (DDI_SUCCESS); 2177 } 2178 2179 static int emu10k_ddi_attach(dev_info_t *, ddi_attach_cmd_t); 2180 static int emu10k_ddi_detach(dev_info_t *, ddi_detach_cmd_t); 2181 static int emu10k_ddi_quiesce(dev_info_t *); 2182 2183 static struct dev_ops emu10k_dev_ops = { 2184 DEVO_REV, /* rev */ 2185 0, /* refcnt */ 2186 NULL, /* getinfo */ 2187 nulldev, /* identify */ 2188 nulldev, /* probe */ 2189 emu10k_ddi_attach, /* attach */ 2190 emu10k_ddi_detach, /* detach */ 2191 nodev, /* reset */ 2192 NULL, /* cb_ops */ 2193 NULL, /* bus_ops */ 2194 NULL, /* power */ 2195 emu10k_ddi_quiesce, /* quiesce */ 2196 }; 2197 2198 static struct modldrv emu10k_modldrv = { 2199 &mod_driverops, /* drv_modops */ 2200 "Creative EMU10K Audio", /* linkinfo */ 2201 &emu10k_dev_ops, /* dev_ops */ 2202 }; 2203 2204 static struct modlinkage modlinkage = { 2205 MODREV_1, 2206 { &emu10k_modldrv, NULL } 2207 }; 2208 2209 int 2210 _init(void) 2211 { 2212 int rv; 2213 2214 audio_init_ops(&emu10k_dev_ops, EMU10K_NAME); 2215 if ((rv = mod_install(&modlinkage)) != 0) { 2216 audio_fini_ops(&emu10k_dev_ops); 2217 } 2218 return (rv); 2219 } 2220 2221 int 2222 _fini(void) 2223 { 2224 int rv; 2225 2226 if ((rv = mod_remove(&modlinkage)) == 0) { 2227 audio_fini_ops(&emu10k_dev_ops); 2228 } 2229 return (rv); 2230 } 2231 2232 int 2233 _info(struct modinfo *modinfop) 2234 { 2235 return (mod_info(&modlinkage, modinfop)); 2236 } 2237 2238 int 2239 emu10k_ddi_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 2240 { 2241 switch (cmd) { 2242 case DDI_ATTACH: 2243 return (emu10k_attach(dip)); 2244 2245 case DDI_RESUME: 2246 return (emu10k_resume(dip)); 2247 2248 default: 2249 return (DDI_FAILURE); 2250 } 2251 } 2252 2253 int 2254 emu10k_ddi_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 2255 { 2256 emu10k_devc_t *devc; 2257 2258 devc = ddi_get_driver_private(dip); 2259 2260 switch (cmd) { 2261 case DDI_DETACH: 2262 return (emu10k_detach(devc)); 2263 2264 case DDI_SUSPEND: 2265 return (emu10k_suspend(devc)); 2266 2267 default: 2268 return (DDI_FAILURE); 2269 } 2270 } 2271 2272 int 2273 emu10k_ddi_quiesce(dev_info_t *dip) 2274 { 2275 emu10k_devc_t *devc; 2276 2277 devc = ddi_get_driver_private(dip); 2278 2279 /* stop all voices */ 2280 for (int i = 0; i < 64; i++) { 2281 emu10k_write_reg(devc, VEDS, i, 0); 2282 } 2283 for (int i = 0; i < 64; i++) { 2284 emu10k_write_reg(devc, VTFT, i, 0); 2285 emu10k_write_reg(devc, CVCF, i, 0); 2286 emu10k_write_reg(devc, PTAB, i, 0); 2287 emu10k_write_reg(devc, CPF, i, 0); 2288 } 2289 2290 /* 2291 * Turn off the hardware 2292 */ 2293 OUTL(devc, 2294 HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK | 2295 HCFG_MUTEBUTTONENABLE, devc->regs + HCFG); 2296 2297 /* stop ADC recording */ 2298 emu10k_write_reg(devc, ADCSR, 0, 0x0); 2299 emu10k_write_reg(devc, ADCBA, 0, 0x0); 2300 emu10k_write_reg(devc, ADCBA, 0, 0x0); 2301 2302 emu10k_write_reg(devc, PTBA, 0, 0); 2303 2304 return (DDI_SUCCESS); 2305 } 2306