1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 /* 28 * Copyright (C) 4Front Technologies 1996-2009. 29 */ 30 31 /* 32 * Purpose: Driver for the Creative Sound Blaster Live! and Audigy/2/4 33 * sound cards 34 */ 35 36 #include <sys/types.h> 37 #include <sys/modctl.h> 38 #include <sys/kmem.h> 39 #include <sys/conf.h> 40 #include <sys/ddi.h> 41 #include <sys/sunddi.h> 42 #include <sys/pci.h> 43 #include <sys/note.h> 44 #include <sys/stdbool.h> 45 #include <sys/audio/audio_driver.h> 46 #include <sys/audio/ac97.h> 47 48 #include "audioemu10k.h" 49 #include <sys/promif.h> 50 51 /* 52 * Include the DSP files for emu10k1 (Live!) and emu10k2 (Audigy) 53 */ 54 #include "emu10k_gpr.h" 55 #include "emu10k1_dsp.h" 56 #include "emu10k2_dsp.h" 57 58 static struct ddi_device_acc_attr dev_attr = { 59 DDI_DEVICE_ATTR_V0, 60 DDI_STRUCTURE_LE_ACC, 61 DDI_STRICTORDER_ACC 62 }; 63 64 static struct ddi_device_acc_attr buf_attr = { 65 DDI_DEVICE_ATTR_V0, 66 DDI_NEVERSWAP_ACC, 67 DDI_STRICTORDER_ACC 68 }; 69 70 71 /* 72 * EMU10K routing stuff. 73 */ 74 #define MAX_SENDS 4 75 #define SEND_L 0 76 #define SEND_R 1 77 #define SEND_SURRL 2 78 #define SEND_SURRR 3 79 #define SEND_CEN 4 80 #define SEND_LFE 5 81 #define SEND_SIDEL 6 82 #define SEND_SIDER 7 83 84 #define SPDIF_L 20 85 #define SPDIF_R 21 86 87 /* 88 * Recording sources... we start from 16 to ensure that the 89 * record sources don't collide with AC'97 record sources in 90 * the control value. 91 */ 92 #define INPUT_AC97 1 93 #define INPUT_SPD1 2 94 #define INPUT_SPD2 3 95 #define INPUT_DIGCD 4 96 #define INPUT_AUX2 5 97 #define INPUT_LINE2 6 98 #define INPUT_STEREOMIX 7 99 100 static uint8_t front_routing[MAX_SENDS] = { 101 SEND_L, SEND_R, 0x3f, 0x3f 102 }; 103 static uint8_t surr_routing[MAX_SENDS] = { 104 SEND_SURRL, SEND_SURRR, 0x3f, 0x3f 105 }; 106 static uint8_t clfe_routing[MAX_SENDS] = { 107 SEND_CEN, SEND_LFE, 0x3f, 0x3f 108 }; 109 static uint8_t side_routing[MAX_SENDS] = { 110 SEND_SIDEL, SEND_SIDER, 0x3f, 0x3f 111 }; 112 static uint8_t no_routing[MAX_SENDS] = { 113 0x3f, 0x3f, 0x3f, 0x3f 114 }; 115 116 /* 117 * SB Live! cannot do DMA above 2G addresses. Audigy/2/4 have special 8k page 118 * mode that supports high addresses. However, we should not need this except 119 * on SPARC. For simplicity's sake, we are only delivering this driver for 120 * x86 platforms. If SPARC support is desired, then the code will have to 121 * be modified to support full 32-bit addressing. (And again, SB Live! 122 * can't do it anyway.) 123 */ 124 125 static ddi_dma_attr_t dma_attr_buf = { 126 DMA_ATTR_V0, /* Version */ 127 0x00000000ULL, /* Address low */ 128 0x7ffffff0ULL, /* Address high */ 129 0xffffffffULL, /* Counter max */ 130 1ULL, /* Default byte align */ 131 0x7f, /* Burst size */ 132 0x1, /* Minimum xfer size */ 133 0xffffffffULL, /* Maximum xfer size */ 134 0xffffffffULL, /* Max segment size */ 135 1, /* S/G list length */ 136 1, /* Granularity */ 137 0 /* Flag */ 138 }; 139 140 static int emu10k_attach(dev_info_t *); 141 static int emu10k_resume(dev_info_t *); 142 static int emu10k_detach(emu10k_devc_t *); 143 static int emu10k_suspend(emu10k_devc_t *); 144 145 static int emu10k_open(void *, int, unsigned *, unsigned *, caddr_t *); 146 static void emu10k_close(void *); 147 static int emu10k_start(void *); 148 static void emu10k_stop(void *); 149 static int emu10k_format(void *); 150 static int emu10k_channels(void *); 151 static int emu10k_rate(void *); 152 static uint64_t emu10k_count(void *); 153 static void emu10k_sync(void *, unsigned); 154 static size_t emu10k_qlen(void *); 155 static void emu10k_chinfo(void *, int, unsigned *, unsigned *); 156 157 static uint16_t emu10k_read_ac97(void *, uint8_t); 158 static void emu10k_write_ac97(void *, uint8_t, uint16_t); 159 static int emu10k_alloc_port(emu10k_devc_t *, int); 160 static void emu10k_destroy(emu10k_devc_t *); 161 static int emu10k_setup_intrs(emu10k_devc_t *); 162 static int emu10k_hwinit(emu10k_devc_t *); 163 static uint_t emu10k_intr(caddr_t, caddr_t); 164 static void emu10k_init_effects(emu10k_devc_t *); 165 166 static audio_engine_ops_t emu10k_engine_ops = { 167 AUDIO_ENGINE_VERSION, 168 emu10k_open, 169 emu10k_close, 170 emu10k_start, 171 emu10k_stop, 172 emu10k_count, 173 emu10k_format, 174 emu10k_channels, 175 emu10k_rate, 176 emu10k_sync, 177 emu10k_qlen, 178 emu10k_chinfo 179 }; 180 181 static uint16_t 182 emu10k_read_ac97(void *arg, uint8_t index) 183 { 184 emu10k_devc_t *devc = arg; 185 int dtemp = 0, i; 186 187 mutex_enter(&devc->mutex); 188 OUTB(devc, index, devc->regs + 0x1e); 189 for (i = 0; i < 10000; i++) 190 if (INB(devc, devc->regs + 0x1e) & 0x80) 191 break; 192 193 if (i == 1000) { 194 mutex_exit(&devc->mutex); 195 return (0); /* Timeout */ 196 } 197 dtemp = INW(devc, devc->regs + 0x1c); 198 199 mutex_exit(&devc->mutex); 200 201 return (dtemp & 0xffff); 202 } 203 204 static void 205 emu10k_write_ac97(void *arg, uint8_t index, uint16_t data) 206 { 207 emu10k_devc_t *devc = arg; 208 int i; 209 210 mutex_enter(&devc->mutex); 211 212 OUTB(devc, index, devc->regs + 0x1e); 213 for (i = 0; i < 10000; i++) 214 if (INB(devc, devc->regs + 0x1e) & 0x80) 215 break; 216 OUTW(devc, data, devc->regs + 0x1c); 217 218 mutex_exit(&devc->mutex); 219 } 220 221 static uint32_t 222 emu10k_read_reg(emu10k_devc_t *devc, int reg, int chn) 223 { 224 uint32_t ptr, ptr_addr_mask, val, mask, size, offset; 225 226 ptr_addr_mask = (devc->feature_mask & 227 (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL)) ? 228 0x0fff0000 : 0x07ff0000; 229 ptr = ((reg << 16) & ptr_addr_mask) | (chn & 0x3f); 230 OUTL(devc, ptr, devc->regs + 0x00); /* Pointer */ 231 val = INL(devc, devc->regs + 0x04); /* Data */ 232 if (reg & 0xff000000) { 233 size = (reg >> 24) & 0x3f; 234 offset = (reg >> 16) & 0x1f; 235 mask = ((1 << size) - 1) << offset; 236 val &= mask; 237 val >>= offset; 238 } 239 240 return (val); 241 } 242 243 static void 244 emu10k_write_reg(emu10k_devc_t *devc, int reg, int chn, uint32_t value) 245 { 246 uint32_t ptr, ptr_addr_mask, mask, size, offset; 247 248 ptr_addr_mask = (devc->feature_mask & 249 (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL)) ? 250 0x0fff0000 : 0x07ff0000; 251 ptr = ((reg << 16) & ptr_addr_mask) | (chn & 0x3f); 252 OUTL(devc, ptr, devc->regs + 0x00); /* Pointer */ 253 if (reg & 0xff000000) { 254 size = (reg >> 24) & 0x3f; 255 offset = (reg >> 16) & 0x1f; 256 mask = ((1 << size) - 1) << offset; 257 value <<= offset; 258 value &= mask; 259 value |= INL(devc, devc->regs + 0x04) & ~mask; /* data */ 260 } 261 OUTL(devc, value, devc->regs + 0x04); /* Data */ 262 } 263 264 static void 265 emu10k_write_routing(emu10k_devc_t *devc, int voice, unsigned char *routing) 266 { 267 int i; 268 269 ASSERT(routing != NULL); 270 271 if (devc->feature_mask & (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL)) { 272 unsigned int srda = 0; 273 274 for (i = 0; i < 4; i++) 275 srda |= routing[i] << (i * 8); 276 277 emu10k_write_reg(devc, SRDA, voice, srda); 278 } else { 279 int fxrt = 0; 280 281 for (i = 0; i < 4; i++) 282 fxrt |= routing[i] << ((i * 4) + 16); 283 emu10k_write_reg(devc, FXRT, voice, fxrt); 284 } 285 } 286 287 static void 288 emu10k_write_efx(emu10k_devc_t *devc, int reg, unsigned int value) 289 { 290 emu10k_write_reg(devc, reg, 0, value); 291 } 292 293 static uint_t 294 emu10k_intr(caddr_t argp, caddr_t nocare) 295 { 296 emu10k_devc_t *devc = (void *) argp; 297 emu10k_portc_t *portc; 298 uint32_t status; 299 audio_engine_t *cons = NULL, *prod = NULL; 300 301 302 _NOTE(ARGUNUSED (nocare)); 303 304 mutex_enter(&devc->mutex); 305 if (devc->suspended) { 306 mutex_exit(&devc->mutex); 307 return (DDI_INTR_UNCLAIMED); 308 } 309 310 status = INL(devc, devc->regs + INTPEND); 311 312 if (status == 0) { 313 mutex_exit(&devc->mutex); 314 return (DDI_INTR_UNCLAIMED); 315 } 316 317 if (status & INT_CL) { /* channel loop */ 318 emu10k_write_reg(devc, CLIPL, 0, (1U << 8)); 319 OUTL(devc, INT_CL, devc->regs + INTPEND); 320 portc = devc->portc[EMU10K_PLAY]; 321 if (portc->active) { 322 cons = portc->engine; 323 } 324 } 325 if (status & (INT_AF|INT_AH|INT_MF|INT_MH)) { /* ADC interrupt */ 326 OUTL(devc, INT_AF|INT_AH|INT_MF|INT_MH, devc->regs + INTPEND); 327 portc = devc->portc[EMU10K_REC]; 328 if (portc->active) { 329 prod = portc->engine; 330 } 331 } 332 333 mutex_exit(&devc->mutex); 334 335 if (cons) { 336 audio_engine_consume(cons); 337 } 338 if (prod) { 339 audio_engine_produce(prod); 340 } 341 342 return (DDI_INTR_CLAIMED); 343 } 344 345 /* 346 * Audio routines 347 */ 348 349 static void 350 emu10k_update_output_volume(emu10k_portc_t *portc, int voice, int chn) 351 { 352 emu10k_devc_t *devc = portc->devc; 353 unsigned int tmp; 354 unsigned char send[2]; 355 356 /* 357 * Each voice operator of EMU10k has 4 sends (0=left, 1=right, 358 * 2=surround_left, 3=surround_right). The original OSS driver 359 * used all of them to spread stereo output to two different 360 * speaker pairs. This Boomer version uses only the first two 361 * sends. The other sends are set to 0. 362 * 363 * Boomer uses multiple voice pairs to play multichannel 364 * audio. This function is used to update only one of these 365 * pairs. 366 */ 367 368 send[0] = 0xff; /* Max */ 369 send[1] = 0xff; /* Max */ 370 371 /* Analog voice */ 372 if (chn == LEFT_CH) { 373 send[1] = 0; 374 } else { 375 send[0] = 0; 376 } 377 378 tmp = emu10k_read_reg(devc, PTAB, voice) & 0xffff0000; 379 emu10k_write_reg(devc, PTAB, voice, tmp | (send[0] << 8) | send[1]); 380 } 381 382 static void 383 emu10k_setup_voice(emu10k_portc_t *portc, int voice, int chn, int buf_offset) 384 { 385 emu10k_devc_t *devc = portc->devc; 386 unsigned int nCRA = 0; 387 388 unsigned int loop_start, loop_end, buf_size; 389 390 int sz; 391 int start_pos; 392 393 emu10k_write_reg(devc, VEDS, voice, 0x0); /* OFF */ 394 emu10k_write_reg(devc, VTFT, voice, 0xffff); 395 emu10k_write_reg(devc, CVCF, voice, 0xffff); 396 397 sz = 2; /* Shift value for 16 bits stereo */ 398 399 /* Size of one stereo sub buffer */ 400 buf_size = (portc->buf_size / portc->channels) * 2; 401 loop_start = (portc->memptr + buf_offset) >> sz; 402 loop_end = (portc->memptr + buf_offset + buf_size) >> sz; 403 404 /* set stereo */ 405 emu10k_write_reg(devc, CPF, voice, 0x8000); 406 407 nCRA = 28; /* Stereo (16 bits) */ 408 start_pos = loop_start + nCRA; 409 410 /* SDL, ST, CA */ 411 412 emu10k_write_reg(devc, SDL, voice, loop_end); 413 emu10k_write_reg(devc, SCSA, voice, loop_start); 414 emu10k_write_reg(devc, PTAB, voice, 0); 415 416 emu10k_update_output_volume(portc, voice, chn); /* Set volume */ 417 418 emu10k_write_reg(devc, QKBCA, voice, start_pos); 419 420 emu10k_write_reg(devc, Z1, voice, 0); 421 emu10k_write_reg(devc, Z2, voice, 0); 422 423 /* This is really a physical address */ 424 emu10k_write_reg(devc, MAPA, voice, 425 0x1fff | (devc->silence_paddr << 1)); 426 emu10k_write_reg(devc, MAPB, voice, 427 0x1fff | (devc->silence_paddr << 1)); 428 429 emu10k_write_reg(devc, VTFT, voice, 0x0000ffff); 430 emu10k_write_reg(devc, CVCF, voice, 0x0000ffff); 431 emu10k_write_reg(devc, MEHA, voice, 0); 432 emu10k_write_reg(devc, MEDS, voice, 0x7f); 433 emu10k_write_reg(devc, MLV, voice, 0x8000); 434 emu10k_write_reg(devc, VLV, voice, 0x8000); 435 emu10k_write_reg(devc, VFM, voice, 0); 436 emu10k_write_reg(devc, TMFQ, voice, 0); 437 emu10k_write_reg(devc, VVFQ, voice, 0); 438 emu10k_write_reg(devc, MEV, voice, 0x8000); 439 emu10k_write_reg(devc, VEHA, voice, 0x7f7f); /* OK */ 440 /* No volume envelope delay (OK) */ 441 emu10k_write_reg(devc, VEV, voice, 0x8000); 442 emu10k_write_reg(devc, PEFE_FILTERAMOUNT, voice, 0x7f); 443 emu10k_write_reg(devc, PEFE_PITCHAMOUNT, voice, 0x00); 444 } 445 446 static void 447 emu10k_setup_silence(emu10k_portc_t *portc, int voice) 448 { 449 emu10k_devc_t *devc = portc->devc; 450 451 emu10k_write_reg(devc, VEDS, voice, 0x0); /* OFF */ 452 emu10k_write_reg(devc, VTFT, voice, 0xffff); 453 emu10k_write_reg(devc, CVCF, voice, 0xffff); 454 455 /* set stereo */ 456 emu10k_write_reg(devc, CPF, voice, 0x8000); 457 458 /* SDL, ST, CA */ 459 emu10k_write_reg(devc, SDL, voice, portc->fragfr); 460 emu10k_write_reg(devc, SCSA, voice, 0); 461 emu10k_write_reg(devc, PTAB, voice, 0); 462 emu10k_write_reg(devc, QKBCA, voice, 0); 463 464 emu10k_write_reg(devc, Z1, voice, 0); 465 emu10k_write_reg(devc, Z2, voice, 0); 466 467 /* This is really a physical address */ 468 emu10k_write_reg(devc, MAPA, voice, 469 0x1fff | (devc->silence_paddr << 1)); 470 emu10k_write_reg(devc, MAPB, voice, 471 0x1fff | (devc->silence_paddr << 1)); 472 473 emu10k_write_reg(devc, VTFT, voice, 0x0000ffff); 474 emu10k_write_reg(devc, CVCF, voice, 0x0000ffff); 475 emu10k_write_reg(devc, MEHA, voice, 0); 476 emu10k_write_reg(devc, MEDS, voice, 0x7f); 477 emu10k_write_reg(devc, MLV, voice, 0x8000); 478 emu10k_write_reg(devc, VLV, voice, 0x8000); 479 emu10k_write_reg(devc, VFM, voice, 0); 480 emu10k_write_reg(devc, TMFQ, voice, 0); 481 emu10k_write_reg(devc, VVFQ, voice, 0); 482 emu10k_write_reg(devc, MEV, voice, 0x8000); 483 emu10k_write_reg(devc, VEHA, voice, 0x7f7f); /* OK */ 484 /* No volume envelope delay (OK) */ 485 emu10k_write_reg(devc, VEV, voice, 0x8000); 486 emu10k_write_reg(devc, PEFE_FILTERAMOUNT, voice, 0x7f); 487 emu10k_write_reg(devc, PEFE_PITCHAMOUNT, voice, 0x00); 488 } 489 490 int 491 emu10k_open(void *arg, int flag, 492 unsigned *fragfrp, unsigned *nfragsp, caddr_t *bufp) 493 { 494 emu10k_portc_t *portc = arg; 495 emu10k_devc_t *devc = portc->devc; 496 497 _NOTE(ARGUNUSED(flag)); 498 499 portc->started = B_FALSE; 500 portc->active = B_FALSE; 501 *fragfrp = portc->fragfr; 502 *nfragsp = portc->nfrags; 503 *bufp = portc->buf_kaddr; 504 505 mutex_enter(&devc->mutex); 506 if (!devc->suspended) 507 portc->reset_port(portc); 508 portc->count = 0; 509 mutex_exit(&devc->mutex); 510 511 return (0); 512 } 513 514 void 515 emu10k_close(void *arg) 516 { 517 emu10k_portc_t *portc = arg; 518 emu10k_devc_t *devc = portc->devc; 519 520 mutex_enter(&devc->mutex); 521 if (!devc->suspended) 522 portc->stop_port(portc); 523 portc->started = B_FALSE; 524 mutex_exit(&devc->mutex); 525 } 526 527 int 528 emu10k_start(void *arg) 529 { 530 emu10k_portc_t *portc = arg; 531 emu10k_devc_t *devc = portc->devc; 532 533 mutex_enter(&devc->mutex); 534 if (!portc->started) { 535 if (!devc->suspended) 536 portc->start_port(portc); 537 portc->started = B_TRUE; 538 } 539 mutex_exit(&devc->mutex); 540 return (0); 541 } 542 543 void 544 emu10k_stop(void *arg) 545 { 546 emu10k_portc_t *portc = arg; 547 emu10k_devc_t *devc = portc->devc; 548 549 mutex_enter(&devc->mutex); 550 if (portc->started) { 551 if (!devc->suspended) 552 portc->stop_port(portc); 553 portc->started = B_FALSE; 554 } 555 mutex_exit(&devc->mutex); 556 } 557 558 int 559 emu10k_format(void *arg) 560 { 561 _NOTE(ARGUNUSED(arg)); 562 563 return (AUDIO_FORMAT_S16_LE); 564 } 565 566 int 567 emu10k_channels(void *arg) 568 { 569 emu10k_portc_t *portc = arg; 570 571 return (portc->channels); 572 } 573 574 int 575 emu10k_rate(void *arg) 576 { 577 _NOTE(ARGUNUSED(arg)); 578 579 return (SAMPLE_RATE); 580 } 581 582 void 583 emu10k_sync(void *arg, unsigned nframes) 584 { 585 emu10k_portc_t *portc = arg; 586 _NOTE(ARGUNUSED(nframes)); 587 588 (void) ddi_dma_sync(portc->buf_dmah, 0, 0, portc->syncdir); 589 } 590 591 size_t 592 emu10k_qlen(void *arg) 593 { 594 _NOTE(ARGUNUSED (arg)); 595 return (0); 596 } 597 598 uint64_t 599 emu10k_count(void *arg) 600 { 601 emu10k_portc_t *portc = arg; 602 emu10k_devc_t *devc = portc->devc; 603 uint64_t count; 604 605 mutex_enter(&devc->mutex); 606 if (!devc->suspended) 607 portc->update_port(portc); 608 count = portc->count; 609 mutex_exit(&devc->mutex); 610 611 return (count); 612 } 613 614 static void 615 emu10k_chinfo(void *arg, int chan, unsigned *offset, unsigned *incr) 616 { 617 emu10k_portc_t *portc = arg; 618 619 *offset = portc->nframes * (chan / 2) * 2 + (chan % 2); 620 *incr = 2; 621 } 622 623 /* private implementation bits */ 624 625 static void 626 emu10k_set_loop_stop(emu10k_devc_t *devc, int voice, int s) 627 { 628 unsigned int tmp; 629 int offs, bit; 630 631 offs = voice / 32; 632 bit = voice % 32; 633 s = !!s; 634 635 tmp = emu10k_read_reg(devc, SOLL + offs, 0); 636 tmp &= ~(1 << bit); 637 638 if (s) 639 tmp |= (1 << bit); 640 emu10k_write_reg(devc, SOLL + offs, 0, tmp); 641 } 642 643 static unsigned int 644 emu10k_rate_to_pitch(unsigned int rate) 645 { 646 static unsigned int logMagTable[128] = { 647 0x00000, 0x02dfc, 0x05b9e, 0x088e6, 648 0x0b5d6, 0x0e26f, 0x10eb3, 0x13aa2, 649 0x1663f, 0x1918a, 0x1bc84, 0x1e72e, 650 0x2118b, 0x23b9a, 0x2655d, 0x28ed5, 651 0x2b803, 0x2e0e8, 0x30985, 0x331db, 652 0x359eb, 0x381b6, 0x3a93d, 0x3d081, 653 0x3f782, 0x41e42, 0x444c1, 0x46b01, 654 0x49101, 0x4b6c4, 0x4dc49, 0x50191, 655 0x5269e, 0x54b6f, 0x57006, 0x59463, 656 0x5b888, 0x5dc74, 0x60029, 0x623a7, 657 0x646ee, 0x66a00, 0x68cdd, 0x6af86, 658 0x6d1fa, 0x6f43c, 0x7164b, 0x73829, 659 0x759d4, 0x77b4f, 0x79c9a, 0x7bdb5, 660 0x7dea1, 0x7ff5e, 0x81fed, 0x8404e, 661 0x86082, 0x88089, 0x8a064, 0x8c014, 662 0x8df98, 0x8fef1, 0x91e20, 0x93d26, 663 0x95c01, 0x97ab4, 0x9993e, 0x9b79f, 664 0x9d5d9, 0x9f3ec, 0xa11d8, 0xa2f9d, 665 0xa4d3c, 0xa6ab5, 0xa8808, 0xaa537, 666 0xac241, 0xadf26, 0xafbe7, 0xb1885, 667 0xb3500, 0xb5157, 0xb6d8c, 0xb899f, 668 0xba58f, 0xbc15e, 0xbdd0c, 0xbf899, 669 0xc1404, 0xc2f50, 0xc4a7b, 0xc6587, 670 0xc8073, 0xc9b3f, 0xcb5ed, 0xcd07c, 671 0xceaec, 0xd053f, 0xd1f73, 0xd398a, 672 0xd5384, 0xd6d60, 0xd8720, 0xda0c3, 673 0xdba4a, 0xdd3b4, 0xded03, 0xe0636, 674 0xe1f4e, 0xe384a, 0xe512c, 0xe69f3, 675 0xe829f, 0xe9b31, 0xeb3a9, 0xecc08, 676 0xee44c, 0xefc78, 0xf148a, 0xf2c83, 677 0xf4463, 0xf5c2a, 0xf73da, 0xf8b71, 678 0xfa2f0, 0xfba57, 0xfd1a7, 0xfe8df 679 }; 680 static char logSlopeTable[128] = { 681 0x5c, 0x5c, 0x5b, 0x5a, 0x5a, 0x59, 0x58, 0x58, 682 0x57, 0x56, 0x56, 0x55, 0x55, 0x54, 0x53, 0x53, 683 0x52, 0x52, 0x51, 0x51, 0x50, 0x50, 0x4f, 0x4f, 684 0x4e, 0x4d, 0x4d, 0x4d, 0x4c, 0x4c, 0x4b, 0x4b, 685 0x4a, 0x4a, 0x49, 0x49, 0x48, 0x48, 0x47, 0x47, 686 0x47, 0x46, 0x46, 0x45, 0x45, 0x45, 0x44, 0x44, 687 0x43, 0x43, 0x43, 0x42, 0x42, 0x42, 0x41, 0x41, 688 0x41, 0x40, 0x40, 0x40, 0x3f, 0x3f, 0x3f, 0x3e, 689 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c, 0x3c, 690 0x3b, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 691 0x39, 0x39, 0x39, 0x38, 0x38, 0x38, 0x38, 0x37, 692 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x36, 0x35, 693 0x35, 0x35, 0x35, 0x34, 0x34, 0x34, 0x34, 0x34, 694 0x33, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x32, 695 0x32, 0x31, 0x31, 0x31, 0x31, 0x31, 0x30, 0x30, 696 0x30, 0x30, 0x30, 0x2f, 0x2f, 0x2f, 0x2f, 0x2f 697 }; 698 int i; 699 700 if (rate == 0) 701 return (0); /* Bail out if no leading "1" */ 702 rate *= 11185; /* Scale 48000 to 0x20002380 */ 703 for (i = 31; i > 0; i--) { 704 if (rate & 0x80000000) { /* Detect leading "1" */ 705 return (((unsigned int) (i - 15) << 20) + 706 logMagTable[0x7f & (rate >> 24)] + 707 (0x7f & (rate >> 17)) * 708 logSlopeTable[0x7f & (rate >> 24)]); 709 } 710 rate <<= 1; 711 } 712 713 return (0); /* Should never reach this point */ 714 } 715 716 static unsigned int 717 emu10k_rate_to_linearpitch(unsigned int rate) 718 { 719 rate = (rate << 8) / 375; 720 return (rate >> 1) + (rate & 1); 721 } 722 723 static void 724 emu10k_prepare_voice(emu10k_devc_t *devc, int voice) 725 { 726 unsigned int sample, initial_pitch, pitch_target; 727 unsigned int cra, cs, ccis, i; 728 729 /* setup CCR regs */ 730 cra = 64; 731 cs = 4; /* Stereo */ 732 ccis = 28; /* Stereo */ 733 sample = 0; /* 16 bit silence */ 734 735 for (i = 0; i < cs; i++) 736 emu10k_write_reg(devc, CD0 + i, voice, sample); 737 738 emu10k_write_reg(devc, CCR_CACHEINVALIDSIZE, voice, 0); 739 emu10k_write_reg(devc, CCR_READADDRESS, voice, cra); 740 emu10k_write_reg(devc, CCR_CACHEINVALIDSIZE, voice, ccis); 741 742 /* Set current pitch */ 743 emu10k_write_reg(devc, IFA, voice, 0xff00); 744 emu10k_write_reg(devc, VTFT, voice, 0xffffffff); 745 emu10k_write_reg(devc, CVCF, voice, 0xffffffff); 746 emu10k_set_loop_stop(devc, voice, 0); 747 748 pitch_target = emu10k_rate_to_linearpitch(SAMPLE_RATE); 749 initial_pitch = emu10k_rate_to_pitch(SAMPLE_RATE) >> 8; 750 emu10k_write_reg(devc, PTRX_PITCHTARGET, voice, pitch_target); 751 emu10k_write_reg(devc, CPF_CURRENTPITCH, voice, pitch_target); 752 emu10k_write_reg(devc, IP, voice, initial_pitch); 753 } 754 755 static void 756 emu10k_stop_voice(emu10k_devc_t *devc, int voice) 757 { 758 emu10k_write_reg(devc, IFA, voice, 0xffff); 759 emu10k_write_reg(devc, VTFT, voice, 0xffff); 760 emu10k_write_reg(devc, PTRX_PITCHTARGET, voice, 0); 761 emu10k_write_reg(devc, CPF_CURRENTPITCH, voice, 0); 762 emu10k_write_reg(devc, IP, voice, 0); 763 emu10k_set_loop_stop(devc, voice, 1); 764 } 765 766 static void 767 emu10k_reset_pair(emu10k_portc_t *portc, int voice, uint8_t *routing, 768 int buf_offset) 769 { 770 emu10k_devc_t *devc = portc->devc; 771 772 /* Left channel */ 773 /* Intial filter cutoff and attenuation */ 774 emu10k_write_reg(devc, IFA, voice, 0xffff); 775 /* Volume envelope decay and sustain */ 776 emu10k_write_reg(devc, VEDS, voice, 0x0); 777 /* Volume target and Filter cutoff target */ 778 emu10k_write_reg(devc, VTFT, voice, 0xffff); 779 /* Pitch target and sends A and B */ 780 emu10k_write_reg(devc, PTAB, voice, 0x0); 781 782 /* The same for right channel */ 783 emu10k_write_reg(devc, IFA, voice + 1, 0xffff); 784 emu10k_write_reg(devc, VEDS, voice + 1, 0x0); 785 emu10k_write_reg(devc, VTFT, voice + 1, 0xffff); 786 emu10k_write_reg(devc, PTAB, voice + 1, 0x0); 787 788 /* now setup the voices and go! */ 789 emu10k_setup_voice(portc, voice, LEFT_CH, buf_offset); 790 emu10k_setup_voice(portc, voice + 1, RIGHT_CH, buf_offset); 791 792 emu10k_write_routing(devc, voice, routing); 793 emu10k_write_routing(devc, voice + 1, routing); 794 } 795 796 void 797 emu10k_start_play(emu10k_portc_t *portc) 798 { 799 emu10k_devc_t *devc = portc->devc; 800 801 ASSERT(mutex_owned(&devc->mutex)); 802 emu10k_prepare_voice(devc, 0); 803 emu10k_prepare_voice(devc, 1); 804 805 emu10k_prepare_voice(devc, 2); 806 emu10k_prepare_voice(devc, 3); 807 808 emu10k_prepare_voice(devc, 4); 809 emu10k_prepare_voice(devc, 5); 810 811 emu10k_prepare_voice(devc, 6); 812 emu10k_prepare_voice(devc, 7); 813 814 emu10k_prepare_voice(devc, 8); 815 emu10k_prepare_voice(devc, 9); 816 817 /* arrange to receive full loop interrupts on channel 8 */ 818 emu10k_write_reg(devc, CLIEL, 0, (1U << 8)); 819 820 /* initialize our position counter... */ 821 portc->pos = 822 (emu10k_read_reg(devc, QKBCA, 0) & 0xffffff) - 823 (portc->memptr >> 2); 824 825 /* Trigger playback on all voices */ 826 emu10k_write_reg(devc, VEDS, 0, 0x7f7f); 827 emu10k_write_reg(devc, VEDS, 1, 0x7f7f); 828 emu10k_write_reg(devc, VEDS, 2, 0x7f7f); 829 emu10k_write_reg(devc, VEDS, 3, 0x7f7f); 830 emu10k_write_reg(devc, VEDS, 4, 0x7f7f); 831 emu10k_write_reg(devc, VEDS, 5, 0x7f7f); 832 emu10k_write_reg(devc, VEDS, 6, 0x7f7f); 833 emu10k_write_reg(devc, VEDS, 7, 0x7f7f); 834 emu10k_write_reg(devc, VEDS, 8, 0x7f7f); 835 emu10k_write_reg(devc, VEDS, 9, 0x7f7f); 836 837 portc->active = B_TRUE; 838 } 839 840 void 841 emu10k_stop_play(emu10k_portc_t *portc) 842 { 843 emu10k_devc_t *devc = portc->devc; 844 845 emu10k_stop_voice(devc, 0); 846 emu10k_stop_voice(devc, 1); 847 emu10k_stop_voice(devc, 2); 848 emu10k_stop_voice(devc, 3); 849 emu10k_stop_voice(devc, 4); 850 emu10k_stop_voice(devc, 5); 851 emu10k_stop_voice(devc, 6); 852 emu10k_stop_voice(devc, 7); 853 emu10k_stop_voice(devc, 8); 854 emu10k_stop_voice(devc, 9); 855 856 portc->active = B_FALSE; 857 } 858 859 void 860 emu10k_reset_play(emu10k_portc_t *portc) 861 { 862 emu10k_devc_t *devc = portc->devc; 863 uint32_t offs; 864 865 offs = (portc->buf_size / portc->channels) * 2; 866 867 if (devc->feature_mask & SB_71) { 868 emu10k_reset_pair(portc, 0, front_routing, 0); 869 emu10k_reset_pair(portc, 2, clfe_routing, offs); 870 emu10k_reset_pair(portc, 4, surr_routing, 2 * offs); 871 emu10k_reset_pair(portc, 6, side_routing, 3 * offs); 872 } else if (devc->feature_mask & SB_51) { 873 emu10k_reset_pair(portc, 0, front_routing, 0); 874 emu10k_reset_pair(portc, 2, clfe_routing, offs); 875 emu10k_reset_pair(portc, 4, surr_routing, 2 * offs); 876 } else { 877 emu10k_reset_pair(portc, 0, front_routing, 0); 878 emu10k_reset_pair(portc, 2, surr_routing, offs); 879 } 880 emu10k_setup_silence(portc, 8); 881 emu10k_setup_silence(portc, 9); 882 883 /* 884 * This way we can use voices 8 and 9 for timing, we have 885 * programmed them to be just the size of a single fragment, 886 * that way when they loop we get a clean interrupt. 887 */ 888 emu10k_write_routing(devc, 8, no_routing); 889 emu10k_write_routing(devc, 9, no_routing); 890 portc->pos = 0; 891 } 892 893 uint32_t emu10k_vars[5]; 894 895 void 896 emu10k_update_play(emu10k_portc_t *portc) 897 { 898 emu10k_devc_t *devc = portc->devc; 899 uint32_t cnt, pos; 900 901 /* 902 * Note: position is given as stereo samples, i.e. frames. 903 */ 904 pos = emu10k_read_reg(devc, QKBCA, 0) & 0xffffff; 905 pos -= (portc->memptr >> 2); 906 907 if (pos <= portc->pos) { 908 cnt = portc->nframes - portc->pos; 909 cnt += pos; 910 } else { 911 cnt = (pos - portc->pos); 912 } 913 if (portc->dopos) { 914 emu10k_vars[0] = portc->pos; 915 emu10k_vars[1] = pos; 916 emu10k_vars[2] = (uint32_t)portc->count; 917 emu10k_vars[3] = cnt; 918 portc->dopos = 0; 919 } 920 if (cnt > portc->nframes) { 921 printf("Got bogus count %u\n", cnt); 922 cnt = portc->fragfr; 923 } 924 ASSERT(cnt <= portc->nframes); 925 portc->count += cnt; 926 portc->pos = pos; 927 } 928 929 void 930 emu10k_start_rec(emu10k_portc_t *portc) 931 { 932 emu10k_devc_t *devc = portc->devc; 933 uint32_t tmp; 934 935 /* Intr enable */ 936 OUTL(devc, INL(devc, devc->regs + IE) | IE_MB | IE_AB, 937 devc->regs + IE); 938 939 tmp = 0; /* setup 48Kz */ 940 if (devc->feature_mask & (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL)) 941 tmp |= 0x30; /* Left/right channel enable */ 942 else 943 tmp |= 0x18; /* Left/right channel enable */ 944 emu10k_write_reg(devc, ADCSR, 0, tmp); /* GO */ 945 946 portc->active = B_TRUE; 947 } 948 949 void 950 emu10k_stop_rec(emu10k_portc_t *portc) 951 { 952 emu10k_devc_t *devc = portc->devc; 953 954 ASSERT(mutex_owned(&devc->mutex)); 955 emu10k_write_reg(devc, ADCSR, 0, 0); 956 957 portc->active = B_FALSE; 958 } 959 void 960 emu10k_reset_rec(emu10k_portc_t *portc) 961 { 962 emu10k_devc_t *devc = portc->devc; 963 uint32_t sz; 964 965 switch (portc->buf_size) { 966 case 4096: 967 sz = 15; 968 break; 969 case 8192: 970 sz = 19; 971 break; 972 case 16384: 973 sz = 23; 974 break; 975 case 32768: 976 sz = 27; 977 break; 978 case 65536: 979 sz = 31; 980 break; 981 } 982 emu10k_write_reg(devc, ADCBA, 0, portc->buf_paddr); 983 emu10k_write_reg(devc, ADCBS, 0, sz); 984 emu10k_write_reg(devc, ADCSR, 0, 0); /* reset for phase */ 985 portc->pos = 0; 986 OUTL(devc, INL(devc, devc->regs + IE) & ~(IE_MB | IE_AB), 987 devc->regs + IE); 988 } 989 990 void 991 emu10k_update_rec(emu10k_portc_t *portc) 992 { 993 emu10k_devc_t *devc = portc->devc; 994 uint32_t cnt, pos; 995 996 /* given in bytes, we divide all counts by 4 to get samples */ 997 pos = emu10k_read_reg(devc, 998 (devc->feature_mask & SB_LIVE) ? MIDX : ADCIDX, 0); 999 if (pos <= portc->pos) { 1000 cnt = ((portc->buf_size) - portc->pos) >> 2; 1001 cnt += (pos >> 2); 1002 } else { 1003 cnt = ((pos - portc->pos) >> 2); 1004 } 1005 portc->count += cnt; 1006 portc->pos = pos; 1007 } 1008 1009 int 1010 emu10k_alloc_port(emu10k_devc_t *devc, int num) 1011 { 1012 emu10k_portc_t *portc; 1013 size_t len; 1014 ddi_dma_cookie_t cookie; 1015 uint_t count; 1016 int dir; 1017 unsigned caps; 1018 audio_dev_t *adev; 1019 int i, n; 1020 1021 adev = devc->adev; 1022 portc = kmem_zalloc(sizeof (*portc), KM_SLEEP); 1023 devc->portc[num] = portc; 1024 portc->devc = devc; 1025 portc->started = B_FALSE; 1026 1027 portc->memptr = devc->audio_memptr; 1028 devc->audio_memptr += (DMABUF_SIZE + 4095) & ~4095; 1029 1030 switch (num) { 1031 case EMU10K_REC: 1032 portc->syncdir = DDI_DMA_SYNC_FORKERNEL; 1033 caps = ENGINE_INPUT_CAP; 1034 dir = DDI_DMA_READ; 1035 portc->channels = 2; 1036 portc->start_port = emu10k_start_rec; 1037 portc->stop_port = emu10k_stop_rec; 1038 portc->reset_port = emu10k_reset_rec; 1039 portc->update_port = emu10k_update_rec; 1040 /* This is the minimum record buffer size. */ 1041 portc->buf_size = 4096; 1042 portc->nfrags = 2; 1043 portc->nframes = 4096 / 4; 1044 portc->fragfr = portc->nframes / portc->nfrags; 1045 break; 1046 case EMU10K_PLAY: 1047 portc->syncdir = DDI_DMA_SYNC_FORDEV; 1048 caps = ENGINE_OUTPUT_CAP; 1049 dir = DDI_DMA_WRITE; 1050 portc->channels = 8; 1051 portc->start_port = emu10k_start_play; 1052 portc->stop_port = emu10k_stop_play; 1053 portc->reset_port = emu10k_reset_play; 1054 portc->update_port = emu10k_update_play; 1055 /* XXX: this could probably be tunable */ 1056 portc->nfrags = 2; 1057 portc->fragfr = 288; 1058 portc->nframes = portc->nfrags * portc->fragfr; 1059 portc->buf_size = portc->nframes * portc->channels * 2; 1060 break; 1061 default: 1062 return (DDI_FAILURE); 1063 } 1064 1065 /* 1066 * Fragments that are not powers of two don't seem to work 1067 * at all with EMU10K. For simplicity's sake, we eliminate 1068 * the question and fix the interrupt rate. This is also the 1069 * logical minimum for record, which requires at least 4K for 1070 * the record size. 1071 */ 1072 1073 if (portc->buf_size > DMABUF_SIZE) { 1074 cmn_err(CE_NOTE, "Buffer size %d is too large (max %d)", 1075 (int)portc->buf_size, DMABUF_SIZE); 1076 portc->buf_size = DMABUF_SIZE; 1077 } 1078 1079 /* Alloc buffers */ 1080 if (ddi_dma_alloc_handle(devc->dip, &dma_attr_buf, DDI_DMA_SLEEP, NULL, 1081 &portc->buf_dmah) != DDI_SUCCESS) { 1082 audio_dev_warn(adev, "failed to allocate BUF handle"); 1083 return (DDI_FAILURE); 1084 } 1085 1086 if (ddi_dma_mem_alloc(portc->buf_dmah, portc->buf_size, 1087 &dev_attr, DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, 1088 &portc->buf_kaddr, &len, &portc->buf_acch) != DDI_SUCCESS) { 1089 audio_dev_warn(adev, "failed to allocate BUF memory"); 1090 return (DDI_FAILURE); 1091 } 1092 1093 if (ddi_dma_addr_bind_handle(portc->buf_dmah, NULL, portc->buf_kaddr, 1094 len, DDI_DMA_CONSISTENT | dir, DDI_DMA_SLEEP, 1095 NULL, &cookie, &count) != DDI_SUCCESS) { 1096 audio_dev_warn(adev, "failed binding BUF DMA handle"); 1097 return (DDI_FAILURE); 1098 } 1099 portc->buf_paddr = cookie.dmac_address; 1100 1101 if ((devc->feature_mask & SB_LIVE) && 1102 (portc->buf_paddr & 0x80000000)) { 1103 audio_dev_warn(adev, "Got DMA buffer beyond 2G limit."); 1104 return (DDI_FAILURE); 1105 } 1106 1107 if (num == EMU10K_PLAY) { /* Output device */ 1108 n = portc->memptr / 4096; 1109 /* 1110 * Fill the page table 1111 */ 1112 for (i = 0; i < portc->buf_size / 4096; i++) { 1113 FILL_PAGE_MAP_ENTRY(n + i, 1114 portc->buf_paddr + i * 4096); 1115 } 1116 1117 (void) ddi_dma_sync(devc->pt_dmah, 0, 0, DDI_DMA_SYNC_FORDEV); 1118 } 1119 1120 portc->engine = audio_engine_alloc(&emu10k_engine_ops, caps); 1121 if (portc->engine == NULL) { 1122 audio_dev_warn(adev, "audio_engine_alloc failed"); 1123 return (DDI_FAILURE); 1124 } 1125 1126 audio_engine_set_private(portc->engine, portc); 1127 audio_dev_add_engine(adev, portc->engine); 1128 1129 return (DDI_SUCCESS); 1130 } 1131 1132 int 1133 emu10k_setup_intrs(emu10k_devc_t *devc) 1134 { 1135 uint_t ipri; 1136 int actual; 1137 int rv; 1138 ddi_intr_handle_t ih[1]; 1139 1140 rv = ddi_intr_alloc(devc->dip, ih, DDI_INTR_TYPE_FIXED, 1141 0, 1, &actual, DDI_INTR_ALLOC_STRICT); 1142 if ((rv != DDI_SUCCESS) || (actual != 1)) { 1143 audio_dev_warn(devc->adev, 1144 "Can't alloc interrupt handle (rv %d actual %d)", 1145 rv, actual); 1146 return (DDI_FAILURE); 1147 } 1148 1149 if (ddi_intr_get_pri(ih[0], &ipri) != DDI_SUCCESS) { 1150 audio_dev_warn(devc->adev, "Can't get interrupt priority"); 1151 (void) ddi_intr_free(ih[0]); 1152 return (DDI_FAILURE); 1153 } 1154 1155 if (ddi_intr_add_handler(ih[0], emu10k_intr, devc, NULL) != 1156 DDI_SUCCESS) { 1157 audio_dev_warn(devc->adev, "Can't add interrupt handler"); 1158 (void) ddi_intr_free(ih[0]); 1159 return (DDI_FAILURE); 1160 } 1161 1162 devc->ih = ih[0]; 1163 mutex_init(&devc->mutex, NULL, MUTEX_DRIVER, DDI_INTR_PRI(ipri)); 1164 return (DDI_SUCCESS); 1165 } 1166 1167 void 1168 emu10k_destroy(emu10k_devc_t *devc) 1169 { 1170 if (devc->ih != NULL) { 1171 (void) ddi_intr_disable(devc->ih); 1172 (void) ddi_intr_remove_handler(devc->ih); 1173 (void) ddi_intr_free(devc->ih); 1174 mutex_destroy(&devc->mutex); 1175 } 1176 1177 if (devc->ksp) { 1178 kstat_delete(devc->ksp); 1179 } 1180 1181 if (devc->silence_paddr) { 1182 (void) ddi_dma_unbind_handle(devc->silence_dmah); 1183 } 1184 if (devc->silence_acch) { 1185 ddi_dma_mem_free(&devc->silence_acch); 1186 } 1187 if (devc->silence_dmah) { 1188 ddi_dma_free_handle(&devc->silence_dmah); 1189 } 1190 1191 if (devc->pt_paddr) { 1192 (void) ddi_dma_unbind_handle(devc->pt_dmah); 1193 } 1194 if (devc->pt_acch) { 1195 ddi_dma_mem_free(&devc->pt_acch); 1196 } 1197 if (devc->pt_dmah) { 1198 ddi_dma_free_handle(&devc->pt_dmah); 1199 } 1200 1201 1202 for (int i = 0; i < CTL_MAX; i++) { 1203 emu10k_ctrl_t *ec = &devc->ctrls[i]; 1204 if (ec->ctrl != NULL) { 1205 audio_dev_del_control(ec->ctrl); 1206 ec->ctrl = NULL; 1207 } 1208 } 1209 1210 for (int i = 0; i < EMU10K_NUM_PORTC; i++) { 1211 emu10k_portc_t *portc = devc->portc[i]; 1212 if (!portc) 1213 continue; 1214 if (portc->engine) { 1215 audio_dev_remove_engine(devc->adev, portc->engine); 1216 audio_engine_free(portc->engine); 1217 } 1218 if (portc->buf_paddr) { 1219 (void) ddi_dma_unbind_handle(portc->buf_dmah); 1220 } 1221 if (portc->buf_acch) { 1222 ddi_dma_mem_free(&portc->buf_acch); 1223 } 1224 if (portc->buf_dmah) { 1225 ddi_dma_free_handle(&portc->buf_dmah); 1226 } 1227 kmem_free(portc, sizeof (*portc)); 1228 } 1229 1230 if (devc->ac97 != NULL) { 1231 ac97_free(devc->ac97); 1232 } 1233 if (devc->adev != NULL) { 1234 audio_dev_free(devc->adev); 1235 } 1236 if (devc->regsh != NULL) { 1237 ddi_regs_map_free(&devc->regsh); 1238 } 1239 if (devc->pcih != NULL) { 1240 pci_config_teardown(&devc->pcih); 1241 } 1242 1243 kmem_free(devc, sizeof (*devc)); 1244 } 1245 1246 static void 1247 emu10k_init_voice(emu10k_devc_t *devc, int voice) 1248 { 1249 emu10k_set_loop_stop(devc, voice, 1); 1250 1251 emu10k_write_reg(devc, VEDS, voice, 0x0); 1252 emu10k_write_reg(devc, IP, voice, 0x0); 1253 emu10k_write_reg(devc, VTFT, voice, 0xffff); 1254 emu10k_write_reg(devc, CVCF, voice, 0xffff); 1255 emu10k_write_reg(devc, PTAB, voice, 0x0); 1256 emu10k_write_reg(devc, CPF, voice, 0x0); 1257 emu10k_write_reg(devc, CCR, voice, 0x0); 1258 emu10k_write_reg(devc, SCSA, voice, 0x0); 1259 emu10k_write_reg(devc, SDL, voice, 0x10); 1260 emu10k_write_reg(devc, QKBCA, voice, 0x0); 1261 emu10k_write_reg(devc, Z1, voice, 0x0); 1262 emu10k_write_reg(devc, Z2, voice, 0x0); 1263 1264 if (devc->feature_mask & (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL)) 1265 emu10k_write_reg(devc, SRDA, voice, 0x03020100); 1266 else 1267 emu10k_write_reg(devc, FXRT, voice, 0x32100000); 1268 1269 emu10k_write_reg(devc, MEHA, voice, 0x0); 1270 emu10k_write_reg(devc, MEDS, voice, 0x0); 1271 emu10k_write_reg(devc, IFA, voice, 0xffff); 1272 emu10k_write_reg(devc, PEFE, voice, 0x0); 1273 emu10k_write_reg(devc, VFM, voice, 0x0); 1274 emu10k_write_reg(devc, TMFQ, voice, 24); 1275 emu10k_write_reg(devc, VVFQ, voice, 24); 1276 emu10k_write_reg(devc, TMPE, voice, 0x0); 1277 emu10k_write_reg(devc, VLV, voice, 0x0); 1278 emu10k_write_reg(devc, MLV, voice, 0x0); 1279 emu10k_write_reg(devc, VEHA, voice, 0x0); 1280 emu10k_write_reg(devc, VEV, voice, 0x0); 1281 emu10k_write_reg(devc, MEV, voice, 0x0); 1282 1283 if (devc->feature_mask & (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL)) { 1284 emu10k_write_reg(devc, CSBA, voice, 0x0); 1285 emu10k_write_reg(devc, CSDC, voice, 0x0); 1286 emu10k_write_reg(devc, CSFE, voice, 0x0); 1287 emu10k_write_reg(devc, CSHG, voice, 0x0); 1288 emu10k_write_reg(devc, SRHE, voice, 0x3f3f3f3f); 1289 } 1290 } 1291 1292 static void 1293 emu10k_refresh_mixer(emu10k_devc_t *devc) 1294 { 1295 uint32_t val; 1296 uint32_t set; 1297 1298 for (int gpr = 0; gpr < MAX_GPR; gpr++) { 1299 if (devc->gpr_shadow[gpr].valid) { 1300 emu10k_write_reg(devc, gpr + GPR0, 0, 1301 devc->gpr_shadow[gpr].value); 1302 } 1303 } 1304 1305 set = devc->ctrls[CTL_JACK3].val; 1306 if (devc->feature_mask & SB_INVSP) { 1307 set = !set; 1308 } 1309 1310 if (devc->feature_mask & (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL)) { 1311 val = INL(devc, devc->regs + 0x18); 1312 val &= ~A_IOCFG_GPOUT0; 1313 val |= set ? 0x44 : 0x40; 1314 OUTL(devc, val, devc->regs + 0x18); 1315 1316 } else if (devc->feature_mask & SB_LIVE) { 1317 val = INL(devc, devc->regs + HCFG); 1318 val &= ~HCFG_GPOUT0; 1319 val |= set ? HCFG_GPOUT0 : 0; 1320 OUTL(devc, val, devc->regs + HCFG); 1321 } 1322 } 1323 1324 int 1325 emu10k_hwinit(emu10k_devc_t *devc) 1326 { 1327 1328 unsigned int tmp, i; 1329 unsigned int reg; 1330 1331 ASSERT(mutex_owned(&devc->mutex)); 1332 1333 emu10k_write_reg(devc, AC97SLOT, 0, AC97SLOT_CENTER | AC97SLOT_LFE); 1334 1335 OUTL(devc, 0x00000000, devc->regs + 0x0c); /* Intr disable */ 1336 OUTL(devc, HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK | 1337 HCFG_MUTEBUTTONENABLE, 1338 devc->regs + HCFG); 1339 1340 emu10k_write_reg(devc, MBS, 0, 0x0); 1341 emu10k_write_reg(devc, MBA, 0, 0x0); 1342 emu10k_write_reg(devc, FXBS, 0, 0x0); 1343 emu10k_write_reg(devc, FXBA, 0, 0x0); 1344 emu10k_write_reg(devc, ADCBS, 0, 0x0); 1345 emu10k_write_reg(devc, ADCBA, 0, 0x0); 1346 1347 OUTL(devc, 0, devc->regs + IE); 1348 emu10k_write_reg(devc, CLIEL, 0, 0x0); 1349 emu10k_write_reg(devc, CLIEH, 0, 0x0); 1350 if (!(devc->feature_mask & SB_LIVE)) { 1351 emu10k_write_reg(devc, HLIEL, 0, 0x0); 1352 emu10k_write_reg(devc, HLIEH, 0, 0x0); 1353 } 1354 emu10k_write_reg(devc, CLIPL, 0, 0xffffffff); 1355 emu10k_write_reg(devc, CLIPH, 0, 0xffffffff); 1356 emu10k_write_reg(devc, SOLL, 0, 0xffffffff); 1357 emu10k_write_reg(devc, SOLH, 0, 0xffffffff); 1358 1359 1360 if (devc->feature_mask & (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL)) { 1361 emu10k_write_reg(devc, SOC, 0, 0xf00); /* ?? */ 1362 emu10k_write_reg(devc, AC97SLOT, 0, 0x3); /* ?? */ 1363 } 1364 1365 for (i = 0; i < 64; i++) 1366 emu10k_init_voice(devc, i); 1367 1368 emu10k_write_reg(devc, SCS0, 0, 0x2109204); 1369 emu10k_write_reg(devc, SCS1, 0, 0x2109204); 1370 emu10k_write_reg(devc, SCS2, 0, 0x2109204); 1371 1372 emu10k_write_reg(devc, PTBA, 0, devc->pt_paddr); 1373 tmp = emu10k_read_reg(devc, PTBA, 0); 1374 1375 emu10k_write_reg(devc, TCBA, 0, 0x0); 1376 emu10k_write_reg(devc, TCBS, 0, 0x4); 1377 1378 reg = 0; 1379 if (devc->feature_mask & SB_71) { 1380 reg = AC97SLOT_CENTER | AC97SLOT_LFE | AC97SLOT_REAR_LEFT | 1381 AC97SLOT_REAR_RIGHT; 1382 } else if (devc->feature_mask & SB_51) { 1383 reg = AC97SLOT_CENTER | AC97SLOT_LFE; 1384 } 1385 if (devc->feature_mask & (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL)) 1386 reg |= 0x40; 1387 emu10k_write_reg(devc, AC97SLOT, 0, reg); 1388 1389 if (devc->feature_mask & SB_AUDIGY2) { 1390 /* Enable analog outputs on Audigy2 */ 1391 int tmp; 1392 1393 /* Setup SRCMulti_I2S SamplingRate */ 1394 tmp = emu10k_read_reg(devc, EHC, 0); 1395 tmp &= 0xfffff1ff; 1396 tmp |= (0x2 << 9); 1397 emu10k_write_reg(devc, EHC, 0, tmp); 1398 /* emu10k_write_reg (devc, SOC, 0, 0x00000000); */ 1399 1400 /* Setup SRCSel (Enable Spdif,I2S SRCMulti) */ 1401 OUTL(devc, 0x600000, devc->regs + 0x20); 1402 OUTL(devc, 0x14, devc->regs + 0x24); 1403 1404 /* Setup SRCMulti Input Audio Enable */ 1405 OUTL(devc, 0x6E0000, devc->regs + 0x20); 1406 1407 OUTL(devc, 0xFF00FF00, devc->regs + 0x24); 1408 1409 /* Setup I2S ASRC Enable (HC register) */ 1410 tmp = INL(devc, devc->regs + HCFG); 1411 tmp |= 0x00000070; 1412 OUTL(devc, tmp, devc->regs + HCFG); 1413 1414 /* 1415 * Unmute Analog now. Set GPO6 to 1 for Apollo. 1416 * This has to be done after init ALice3 I2SOut beyond 48KHz. 1417 * So, sequence is important 1418 */ 1419 tmp = INL(devc, devc->regs + 0x18); 1420 tmp |= 0x0040; 1421 1422 OUTL(devc, tmp, devc->regs + 0x18); 1423 } 1424 1425 if (devc->feature_mask & SB_AUDIGY2VAL) { 1426 /* Enable analog outputs on Audigy2 */ 1427 int tmp; 1428 1429 /* Setup SRCMulti_I2S SamplingRate */ 1430 tmp = emu10k_read_reg(devc, EHC, 0); 1431 tmp &= 0xfffff1ff; 1432 tmp |= (0x2 << 9); 1433 emu10k_write_reg(devc, EHC, 0, tmp); 1434 1435 /* Setup SRCSel (Enable Spdif,I2S SRCMulti) */ 1436 OUTL(devc, 0x600000, devc->regs + 0x20); 1437 OUTL(devc, 0x14, devc->regs + 0x24); 1438 1439 /* Setup SRCMulti Input Audio Enable */ 1440 OUTL(devc, 0x7B0000, devc->regs + 0x20); 1441 OUTL(devc, 0xFF000000, devc->regs + 0x24); 1442 1443 /* SPDIF output enable */ 1444 OUTL(devc, 0x7A0000, devc->regs + 0x20); 1445 OUTL(devc, 0xFF000000, devc->regs + 0x24); 1446 1447 tmp = INL(devc, devc->regs + 0x18) & ~0x8; 1448 OUTL(devc, tmp, devc->regs + 0x18); 1449 } 1450 1451 emu10k_write_reg(devc, SOLL, 0, 0xffffffff); 1452 emu10k_write_reg(devc, SOLH, 0, 0xffffffff); 1453 1454 if (devc->feature_mask & (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL)) { 1455 unsigned int mode = 0; 1456 1457 if (devc->feature_mask & (SB_AUDIGY2|SB_AUDIGY2VAL)) 1458 mode |= HCFG_AC3ENABLE_GPSPDIF | HCFG_AC3ENABLE_CDSPDIF; 1459 OUTL(devc, 1460 HCFG_AUDIOENABLE | HCFG_AUTOMUTE | 1461 HCFG_JOYENABLE | A_HCFG_VMUTE | 1462 A_HCFG_AUTOMUTE | mode, devc->regs + HCFG); 1463 1464 OUTL(devc, INL(devc, devc->regs + 0x18) | 1465 0x0004, devc->regs + 0x18); /* GPIO (S/PDIF enable) */ 1466 1467 1468 /* enable IR port */ 1469 tmp = INL(devc, devc->regs + 0x18); 1470 OUTL(devc, tmp | A_IOCFG_GPOUT2, devc->regs + 0x18); 1471 drv_usecwait(500); 1472 OUTL(devc, tmp | A_IOCFG_GPOUT1 | A_IOCFG_GPOUT2, 1473 devc->regs + 0x18); 1474 drv_usecwait(100); 1475 OUTL(devc, tmp, devc->regs + 0x18); 1476 } else { 1477 OUTL(devc, 1478 HCFG_AUDIOENABLE | HCFG_LOCKTANKCACHE_MASK | 1479 HCFG_AUTOMUTE | HCFG_JOYENABLE, devc->regs + HCFG); 1480 } 1481 1482 1483 /* enable IR port */ 1484 tmp = INL(devc, devc->regs + HCFG); 1485 OUTL(devc, tmp | HCFG_GPOUT2, devc->regs + HCFG); 1486 drv_usecwait(500); 1487 OUTL(devc, tmp | HCFG_GPOUT1 | HCFG_GPOUT2, devc->regs + HCFG); 1488 drv_usecwait(100); 1489 OUTL(devc, tmp, devc->regs + HCFG); 1490 1491 1492 /* 1493 * Start by configuring for analog mode. 1494 */ 1495 if (devc->feature_mask & (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL)) { 1496 reg = INL(devc, devc->regs + 0x18) & ~A_IOCFG_GPOUT0; 1497 reg |= ((devc->feature_mask & SB_INVSP) ? 0x4 : 0); 1498 OUTL(devc, reg, devc->regs + 0x18); 1499 } 1500 if (devc->feature_mask & SB_LIVE) { /* SBLIVE */ 1501 reg = INL(devc, devc->regs + HCFG) & ~HCFG_GPOUT0; 1502 reg |= ((devc->feature_mask & SB_INVSP) ? HCFG_GPOUT0 : 0); 1503 OUTL(devc, reg, devc->regs + HCFG); 1504 } 1505 1506 if (devc->feature_mask & SB_AUDIGY2VAL) { 1507 OUTL(devc, INL(devc, devc->regs + 0x18) | 0x0060, 1508 devc->regs + 0x18); 1509 } else if (devc->feature_mask & SB_AUDIGY2) { 1510 OUTL(devc, INL(devc, devc->regs + 0x18) | 0x0040, 1511 devc->regs + 0x18); 1512 } else if (devc->feature_mask & SB_AUDIGY) { 1513 OUTL(devc, INL(devc, devc->regs + 0x18) | 0x0080, 1514 devc->regs + 0x18); 1515 } 1516 1517 emu10k_init_effects(devc); 1518 1519 return (DDI_SUCCESS); 1520 } 1521 1522 static const int db2lin_101[101] = { 1523 0x00000000, 1524 0x0024B53A, 0x002750CA, 0x002A1BC6, 0x002D198D, 0x00304DBA, 0x0033BC2A, 1525 0x00376901, 0x003B58AF, 0x003F8FF1, 0x004413DF, 0x0048E9EA, 0x004E17E9, 1526 0x0053A419, 0x0059952C, 0x005FF24E, 0x0066C32A, 0x006E0FFB, 0x0075E18D, 1527 0x007E414F, 0x0087395B, 0x0090D482, 0x009B1E5B, 0x00A6234F, 0x00B1F0A7, 1528 0x00BE94A1, 0x00CC1E7C, 0x00DA9E8D, 0x00EA2650, 0x00FAC881, 0x010C9931, 1529 0x011FADDC, 0x01341D87, 0x014A00D8, 0x01617235, 0x017A8DE6, 0x01957233, 1530 0x01B23F8D, 0x01D118B1, 0x01F222D4, 0x021585D1, 0x023B6C57, 0x0264041D, 1531 0x028F7E19, 0x02BE0EBD, 0x02EFEE33, 0x032558A2, 0x035E8E7A, 0x039BD4BC, 1532 0x03DD7551, 0x0423BF61, 0x046F07B5, 0x04BFA91B, 0x051604D5, 0x0572830D, 1533 0x05D59354, 0x063FAD27, 0x06B15080, 0x072B0673, 0x07AD61CD, 0x0838FFCA, 1534 0x08CE88D3, 0x096EB147, 0x0A1A3A53, 0x0AD1F2E0, 0x0B96B889, 0x0C6978A5, 1535 0x0D4B316A, 0x0E3CF31B, 0x0F3FE155, 0x10553469, 0x117E3AD9, 0x12BC5AEA, 1536 0x14111457, 0x157E0219, 0x1704DC5E, 0x18A77A97, 0x1A67D5B6, 0x1C480A87, 1537 0x1E4A5C45, 0x2071374D, 0x22BF3412, 0x25371A37, 0x27DBE3EF, 0x2AB0C18F, 1538 0x2DB91D6F, 0x30F89FFD, 0x34733433, 0x382D0C46, 0x3C2AA6BD, 0x4070D3D9, 1539 0x4504BB66, 0x49EBE2F1, 0x4F2C346F, 0x54CC0565, 0x5AD21E86, 0x6145C3E7, 1540 0x682EBDBD, 0x6F9561C4, 0x77829D4D, 1541 0x7fffffff 1542 }; 1543 1544 static int 1545 emu10k_convert_fixpoint(int val) 1546 { 1547 if (val < 0) 1548 val = 0; 1549 if (val > 100) 1550 val = 100; 1551 return (db2lin_101[val]); 1552 } 1553 1554 static void 1555 emu10k_write_gpr(emu10k_devc_t *devc, int gpr, uint32_t value) 1556 { 1557 ASSERT(gpr < MAX_GPR); 1558 devc->gpr_shadow[gpr].valid = B_TRUE; 1559 devc->gpr_shadow[gpr].value = value; 1560 if (!devc->suspended) { 1561 emu10k_write_reg(devc, gpr + GPR0, 0, value); 1562 } 1563 } 1564 1565 static int 1566 emu10k_set_stereo(void *arg, uint64_t val) 1567 { 1568 emu10k_ctrl_t *ec = arg; 1569 emu10k_devc_t *devc = ec->devc; 1570 uint32_t left, right; 1571 1572 left = (val >> 8) & 0xff; 1573 right = val & 0xff; 1574 if ((left > 100) || (right > 100) || (val & ~(0xffff))) 1575 return (EINVAL); 1576 1577 left = emu10k_convert_fixpoint(left); 1578 right = emu10k_convert_fixpoint(right); 1579 1580 mutex_enter(&devc->mutex); 1581 ec->val = val; 1582 1583 emu10k_write_gpr(devc, ec->gpr_num, left); 1584 emu10k_write_gpr(devc, ec->gpr_num + 1, right); 1585 1586 mutex_exit(&devc->mutex); 1587 return (0); 1588 } 1589 1590 static int 1591 emu10k_set_mono(void *arg, uint64_t val) 1592 { 1593 emu10k_ctrl_t *ec = arg; 1594 emu10k_devc_t *devc = ec->devc; 1595 uint32_t v; 1596 1597 if (val > 100) 1598 return (EINVAL); 1599 1600 v = emu10k_convert_fixpoint(val & 0xff); 1601 1602 mutex_enter(&devc->mutex); 1603 ec->val = val; 1604 emu10k_write_gpr(devc, ec->gpr_num, v); 1605 mutex_exit(&devc->mutex); 1606 return (0); 1607 } 1608 1609 static int 1610 emu10k_get_control(void *arg, uint64_t *val) 1611 { 1612 emu10k_ctrl_t *ec = arg; 1613 emu10k_devc_t *devc = ec->devc; 1614 1615 mutex_enter(&devc->mutex); 1616 *val = ec->val; 1617 mutex_exit(&devc->mutex); 1618 return (0); 1619 } 1620 1621 #define PLAYCTL (AUDIO_CTRL_FLAG_RW | AUDIO_CTRL_FLAG_PLAY) 1622 #define RECCTL (AUDIO_CTRL_FLAG_RW | AUDIO_CTRL_FLAG_REC) 1623 #define MONCTL (AUDIO_CTRL_FLAG_RW | AUDIO_CTRL_FLAG_MONITOR) 1624 #define MAINVOL (PLAYCTL | AUDIO_CTRL_FLAG_MAINVOL) 1625 #define PCMVOL (PLAYCTL | AUDIO_CTRL_FLAG_PCMVOL) 1626 #define RECVOL (RECCTL | AUDIO_CTRL_FLAG_RECVOL) 1627 #define MONVOL (MONCTL | AUDIO_CTRL_FLAG_MONVOL) 1628 1629 static int 1630 emu10k_get_ac97src(void *arg, uint64_t *valp) 1631 { 1632 ac97_ctrl_t *ctrl = arg; 1633 1634 return (ac97_control_get(ctrl, valp)); 1635 } 1636 1637 static int 1638 emu10k_set_ac97src(void *arg, uint64_t value) 1639 { 1640 ac97_ctrl_t *ctrl = arg; 1641 1642 return (ac97_control_set(ctrl, value)); 1643 } 1644 1645 static int 1646 emu10k_set_jack3(void *arg, uint64_t value) 1647 { 1648 emu10k_ctrl_t *ec = arg; 1649 emu10k_devc_t *devc = ec->devc; 1650 uint32_t set_val; 1651 uint32_t val; 1652 1653 set_val = ddi_ffs(value & 0xffffffffU); 1654 set_val--; 1655 mutex_enter(&devc->mutex); 1656 switch (set_val) { 1657 case 0: 1658 case 1: 1659 break; 1660 default: 1661 mutex_exit(&devc->mutex); 1662 return (EINVAL); 1663 } 1664 ec->val = value; 1665 /* center/lfe */ 1666 if (devc->feature_mask & SB_INVSP) { 1667 set_val = !set_val; 1668 } 1669 if (!devc->suspended) { 1670 if (devc->feature_mask & (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL)) { 1671 val = INL(devc, devc->regs + 0x18); 1672 val &= ~A_IOCFG_GPOUT0; 1673 val |= set_val ? 0x44 : 0x40; 1674 OUTL(devc, val, devc->regs + 0x18); 1675 1676 } else if (devc->feature_mask & SB_LIVE) { 1677 val = INL(devc, devc->regs + HCFG); 1678 val &= ~HCFG_GPOUT0; 1679 val |= set_val ? HCFG_GPOUT0 : 0; 1680 OUTL(devc, val, devc->regs + HCFG); 1681 } 1682 } 1683 mutex_exit(&devc->mutex); 1684 return (0); 1685 } 1686 1687 static int 1688 emu10k_set_recsrc(void *arg, uint64_t value) 1689 { 1690 emu10k_ctrl_t *ec = arg; 1691 emu10k_devc_t *devc = ec->devc; 1692 uint32_t set_val; 1693 1694 set_val = ddi_ffs(value & 0xffffffffU); 1695 set_val--; 1696 1697 /* 1698 * We start assuming well set up AC'97 for stereomix recording. 1699 */ 1700 switch (set_val) { 1701 case INPUT_AC97: 1702 case INPUT_SPD1: 1703 case INPUT_SPD2: 1704 case INPUT_DIGCD: 1705 case INPUT_AUX2: 1706 case INPUT_LINE2: 1707 case INPUT_STEREOMIX: 1708 break; 1709 default: 1710 return (EINVAL); 1711 } 1712 1713 mutex_enter(&devc->mutex); 1714 ec->val = value; 1715 1716 emu10k_write_gpr(devc, GPR_REC_AC97, (set_val == INPUT_AC97)); 1717 emu10k_write_gpr(devc, GPR_REC_SPDIF1, (set_val == INPUT_SPD1)); 1718 emu10k_write_gpr(devc, GPR_REC_SPDIF2, (set_val == INPUT_SPD2)); 1719 emu10k_write_gpr(devc, GPR_REC_DIGCD, (set_val == INPUT_DIGCD)); 1720 emu10k_write_gpr(devc, GPR_REC_AUX2, (set_val == INPUT_AUX2)); 1721 emu10k_write_gpr(devc, GPR_REC_LINE2, (set_val == INPUT_LINE2)); 1722 emu10k_write_gpr(devc, GPR_REC_PCM, (set_val == INPUT_STEREOMIX)); 1723 1724 mutex_exit(&devc->mutex); 1725 1726 return (0); 1727 } 1728 1729 static void 1730 emu10k_create_stereo(emu10k_devc_t *devc, int ctl, int gpr, 1731 const char *id, int flags, int defval) 1732 { 1733 emu10k_ctrl_t *ec; 1734 audio_ctrl_desc_t desc; 1735 1736 bzero(&desc, sizeof (desc)); 1737 1738 ec = &devc->ctrls[ctl]; 1739 ec->devc = devc; 1740 ec->gpr_num = gpr; 1741 1742 desc.acd_name = id; 1743 desc.acd_type = AUDIO_CTRL_TYPE_STEREO; 1744 desc.acd_minvalue = 0; 1745 desc.acd_maxvalue = 100; 1746 desc.acd_flags = flags; 1747 1748 ec->val = (defval << 8) | defval; 1749 ec->ctrl = audio_dev_add_control(devc->adev, &desc, 1750 emu10k_get_control, emu10k_set_stereo, ec); 1751 1752 mutex_enter(&devc->mutex); 1753 emu10k_write_gpr(devc, gpr, emu10k_convert_fixpoint(defval)); 1754 emu10k_write_gpr(devc, gpr + 1, emu10k_convert_fixpoint(defval)); 1755 mutex_exit(&devc->mutex); 1756 } 1757 1758 static void 1759 emu10k_create_mono(emu10k_devc_t *devc, int ctl, int gpr, 1760 const char *id, int flags, int defval) 1761 { 1762 emu10k_ctrl_t *ec; 1763 audio_ctrl_desc_t desc; 1764 1765 bzero(&desc, sizeof (desc)); 1766 1767 ec = &devc->ctrls[ctl]; 1768 ec->devc = devc; 1769 ec->gpr_num = gpr; 1770 1771 desc.acd_name = id; 1772 desc.acd_type = AUDIO_CTRL_TYPE_MONO; 1773 desc.acd_minvalue = 0; 1774 desc.acd_maxvalue = 100; 1775 desc.acd_flags = flags; 1776 1777 ec->val = defval; 1778 ec->ctrl = audio_dev_add_control(devc->adev, &desc, 1779 emu10k_get_control, emu10k_set_mono, ec); 1780 1781 mutex_enter(&devc->mutex); 1782 emu10k_write_gpr(devc, gpr, emu10k_convert_fixpoint(defval)); 1783 mutex_exit(&devc->mutex); 1784 } 1785 1786 /* 1787 * AC'97 source. The AC'97 PCM record channel is routed to our 1788 * mixer. While we could support the direct monitoring capability of 1789 * the AC'97 part itself, this would not work correctly with outputs 1790 * that are not routed via AC'97 (such as the Live Drive headphones 1791 * or digital outputs.) So we just offer the ability to select one 1792 * AC'97 source, and then offer independent ability to either monitor 1793 * or record from the AC'97 mixer's PCM record channel. 1794 */ 1795 static void 1796 emu10k_create_ac97src(emu10k_devc_t *devc) 1797 { 1798 emu10k_ctrl_t *ec; 1799 audio_ctrl_desc_t desc; 1800 ac97_ctrl_t *ac; 1801 const audio_ctrl_desc_t *acd; 1802 1803 bzero(&desc, sizeof (desc)); 1804 1805 ec = &devc->ctrls[CTL_AC97SRC]; 1806 desc.acd_name = "ac97-source"; 1807 desc.acd_type = AUDIO_CTRL_TYPE_ENUM; 1808 desc.acd_flags = RECCTL; 1809 ec->devc = devc; 1810 ac = ac97_control_find(devc->ac97, AUDIO_CTRL_ID_RECSRC); 1811 if (ac == NULL) { 1812 return; 1813 } 1814 1815 acd = ac97_control_desc(ac); 1816 1817 for (int i = 0; i < 64; i++) { 1818 const char *n; 1819 if (((acd->acd_minvalue & (1ULL << i)) == 0) || 1820 ((n = acd->acd_enum[i]) == NULL)) { 1821 continue; 1822 } 1823 desc.acd_enum[i] = acd->acd_enum[i]; 1824 /* we suppress some port options */ 1825 if ((strcmp(n, AUDIO_PORT_STEREOMIX) == 0) || 1826 (strcmp(n, AUDIO_PORT_MONOMIX) == 0) || 1827 (strcmp(n, AUDIO_PORT_VIDEO) == 0)) { 1828 continue; 1829 } 1830 desc.acd_minvalue |= (1ULL << i); 1831 desc.acd_maxvalue |= (1ULL << i); 1832 } 1833 1834 ec->ctrl = audio_dev_add_control(devc->adev, &desc, 1835 emu10k_get_ac97src, emu10k_set_ac97src, ac); 1836 } 1837 1838 /* 1839 * Record source... this one is tricky. While the chip will 1840 * conceivably let us *mix* some of the audio streams for recording, 1841 * the AC'97 inputs don't have this capability. Offering it to users 1842 * is likely to be confusing, so we offer a single record source 1843 * selection option. Its not ideal, but it ought to be good enough 1844 * for the vast majority of users. 1845 */ 1846 static void 1847 emu10k_create_recsrc(emu10k_devc_t *devc) 1848 { 1849 emu10k_ctrl_t *ec; 1850 audio_ctrl_desc_t desc; 1851 ac97_ctrl_t *ac; 1852 1853 bzero(&desc, sizeof (desc)); 1854 1855 ec = &devc->ctrls[CTL_RECSRC]; 1856 desc.acd_name = AUDIO_CTRL_ID_RECSRC; 1857 desc.acd_type = AUDIO_CTRL_TYPE_ENUM; 1858 desc.acd_flags = RECCTL; 1859 desc.acd_minvalue = 0; 1860 desc.acd_maxvalue = 0; 1861 bzero(desc.acd_enum, sizeof (desc.acd_enum)); 1862 ec->devc = devc; 1863 ac = ac97_control_find(devc->ac97, AUDIO_CTRL_ID_RECSRC); 1864 1865 /* only low order bits set by AC'97 */ 1866 ASSERT(desc.acd_minvalue == desc.acd_maxvalue); 1867 ASSERT((desc.acd_minvalue & ~0xffff) == 0); 1868 1869 /* 1870 * It would be really cool if we could detect whether these 1871 * options are all sensible on a given configuration. Units 1872 * without live-drive support, and units without a physical 1873 * live-drive, simply can't do all these. 1874 */ 1875 if (ac != NULL) { 1876 desc.acd_minvalue |= (1 << INPUT_AC97); 1877 desc.acd_maxvalue |= (1 << INPUT_AC97); 1878 desc.acd_enum[INPUT_AC97] = "ac97"; 1879 ec->val = (1 << INPUT_AC97); 1880 } else { 1881 /* next best guess */ 1882 ec->val = (1 << INPUT_LINE2); 1883 } 1884 1885 desc.acd_minvalue |= (1 << INPUT_SPD1); 1886 desc.acd_maxvalue |= (1 << INPUT_SPD1); 1887 desc.acd_enum[INPUT_SPD1] = AUDIO_PORT_SPDIFIN; 1888 1889 desc.acd_minvalue |= (1 << INPUT_SPD2); 1890 desc.acd_maxvalue |= (1 << INPUT_SPD2); 1891 desc.acd_enum[INPUT_SPD2] = "spdif2-in"; 1892 1893 desc.acd_minvalue |= (1 << INPUT_DIGCD); 1894 desc.acd_maxvalue |= (1 << INPUT_DIGCD); 1895 desc.acd_enum[INPUT_DIGCD] = "digital-cd"; 1896 1897 desc.acd_minvalue |= (1 << INPUT_AUX2); 1898 desc.acd_maxvalue |= (1 << INPUT_AUX2); 1899 desc.acd_enum[INPUT_AUX2] = AUDIO_PORT_AUX2IN; 1900 1901 desc.acd_minvalue |= (1 << INPUT_LINE2); 1902 desc.acd_maxvalue |= (1 << INPUT_LINE2); 1903 desc.acd_enum[INPUT_LINE2] = "line2-in"; 1904 1905 desc.acd_minvalue |= (1 << INPUT_STEREOMIX); 1906 desc.acd_maxvalue |= (1 << INPUT_STEREOMIX); 1907 desc.acd_enum[INPUT_STEREOMIX] = AUDIO_PORT_STEREOMIX; 1908 1909 emu10k_write_gpr(devc, GPR_REC_SPDIF1, 0); 1910 emu10k_write_gpr(devc, GPR_REC_SPDIF2, 0); 1911 emu10k_write_gpr(devc, GPR_REC_DIGCD, 0); 1912 emu10k_write_gpr(devc, GPR_REC_AUX2, 0); 1913 emu10k_write_gpr(devc, GPR_REC_LINE2, 0); 1914 emu10k_write_gpr(devc, GPR_REC_PCM, 0); 1915 emu10k_write_gpr(devc, GPR_REC_AC97, 1); 1916 1917 ec->ctrl = audio_dev_add_control(devc->adev, &desc, 1918 emu10k_get_control, emu10k_set_recsrc, ec); 1919 } 1920 1921 static void 1922 emu10k_create_jack3(emu10k_devc_t *devc) 1923 { 1924 emu10k_ctrl_t *ec; 1925 audio_ctrl_desc_t desc; 1926 1927 bzero(&desc, sizeof (desc)); 1928 1929 ec = &devc->ctrls[CTL_JACK3]; 1930 desc.acd_name = AUDIO_CTRL_ID_JACK3; 1931 desc.acd_type = AUDIO_CTRL_TYPE_ENUM; 1932 desc.acd_flags = AUDIO_CTRL_FLAG_RW; 1933 desc.acd_minvalue = 0x3; 1934 desc.acd_maxvalue = 0x3; 1935 bzero(desc.acd_enum, sizeof (desc.acd_enum)); 1936 ec->devc = devc; 1937 ec->val = 0x1; 1938 1939 desc.acd_enum[0] = AUDIO_PORT_CENLFE; 1940 desc.acd_enum[1] = AUDIO_PORT_SPDIFOUT; 1941 1942 ec->ctrl = audio_dev_add_control(devc->adev, &desc, 1943 emu10k_get_control, emu10k_set_jack3, ec); 1944 } 1945 1946 1947 static void 1948 emu10k_create_controls(emu10k_devc_t *devc) 1949 { 1950 ac97_t *ac97; 1951 ac97_ctrl_t *ac; 1952 1953 emu10k_create_mono(devc, CTL_VOLUME, GPR_VOL_PCM, 1954 AUDIO_CTRL_ID_VOLUME, PCMVOL, 75); 1955 1956 emu10k_create_stereo(devc, CTL_FRONT, GPR_VOL_FRONT, 1957 AUDIO_CTRL_ID_FRONT, MAINVOL, 100); 1958 emu10k_create_stereo(devc, CTL_SURROUND, GPR_VOL_SURR, 1959 AUDIO_CTRL_ID_SURROUND, MAINVOL, 100); 1960 if (devc->feature_mask & (SB_51 | SB_71)) { 1961 emu10k_create_mono(devc, CTL_CENTER, GPR_VOL_CEN, 1962 AUDIO_CTRL_ID_CENTER, MAINVOL, 100); 1963 emu10k_create_mono(devc, CTL_LFE, GPR_VOL_LFE, 1964 AUDIO_CTRL_ID_LFE, MAINVOL, 100); 1965 } 1966 if (devc->feature_mask & SB_71) { 1967 emu10k_create_stereo(devc, CTL_SIDE, GPR_VOL_SIDE, 1968 "side", MAINVOL, 100); 1969 } 1970 1971 emu10k_create_stereo(devc, CTL_RECGAIN, GPR_VOL_REC, 1972 AUDIO_CTRL_ID_RECGAIN, RECVOL, 50); 1973 1974 emu10k_create_ac97src(devc); 1975 emu10k_create_recsrc(devc); 1976 /* 1977 * 5.1 devices have versa jack. Note that from what we can 1978 * tell, none of the 7.1 devices have or need this versa jack, 1979 * as they all seem to have a dedicated digital I/O port. 1980 */ 1981 if ((devc->feature_mask & SB_51) && 1982 !(devc->feature_mask & SB_AUDIGY2VAL)) { 1983 emu10k_create_jack3(devc); 1984 } 1985 1986 /* these ones AC'97 can manage directly */ 1987 ac97 = devc->ac97; 1988 1989 if ((ac = ac97_control_find(ac97, AUDIO_CTRL_ID_MICBOOST)) != NULL) 1990 ac97_control_register(ac); 1991 if ((ac = ac97_control_find(ac97, AUDIO_CTRL_ID_MICGAIN)) != NULL) 1992 ac97_control_register(ac); 1993 1994 /* set any AC'97 analog outputs to full volume (no attenuation) */ 1995 if ((ac = ac97_control_find(ac97, AUDIO_CTRL_ID_FRONT)) != NULL) 1996 (void) ac97_control_set(ac, (100 << 8) | 100); 1997 if ((ac = ac97_control_find(ac97, AUDIO_CTRL_ID_LINEOUT)) != NULL) 1998 (void) ac97_control_set(ac, (100 << 8) | 100); 1999 if ((ac = ac97_control_find(ac97, AUDIO_CTRL_ID_SURROUND)) != NULL) 2000 (void) ac97_control_set(ac, (100 << 8) | 100); 2001 if ((ac = ac97_control_find(ac97, AUDIO_CTRL_ID_CENTER)) != NULL) 2002 (void) ac97_control_set(ac, 100); 2003 if ((ac = ac97_control_find(ac97, AUDIO_CTRL_ID_LFE)) != NULL) 2004 (void) ac97_control_set(ac, 100); 2005 2006 /* Monitor sources */ 2007 emu10k_create_stereo(devc, CTL_AC97, GPR_MON_AC97, 2008 "ac97-monitor", MONVOL, 0); 2009 emu10k_create_stereo(devc, CTL_SPD1, GPR_MON_SPDIF1, 2010 AUDIO_PORT_SPDIFIN, MONVOL, 0); 2011 emu10k_create_stereo(devc, CTL_DIGCD, GPR_MON_DIGCD, 2012 "digital-cd", MONVOL, 0); 2013 emu10k_create_stereo(devc, CTL_SPD1, GPR_MON_SPDIF1, 2014 AUDIO_PORT_SPDIFIN, MONVOL, 0); 2015 2016 if ((devc->feature_mask & SB_NOEXP) == 0) { 2017 /* 2018 * These ports are only available via an external 2019 * expansion box. Don't expose them for cards that 2020 * don't have support for it. 2021 */ 2022 emu10k_create_stereo(devc, CTL_HEADPH, GPR_VOL_HEADPH, 2023 AUDIO_CTRL_ID_HEADPHONE, MAINVOL, 100); 2024 emu10k_create_stereo(devc, CTL_SPD2, GPR_MON_SPDIF2, 2025 "spdif2-in", MONVOL, 0); 2026 emu10k_create_stereo(devc, CTL_LINE2, GPR_MON_LINE2, 2027 "line2-in", MONVOL, 0); 2028 emu10k_create_stereo(devc, CTL_AUX2, GPR_MON_AUX2, 2029 AUDIO_PORT_AUX2IN, MONVOL, 0); 2030 } 2031 } 2032 2033 static void 2034 emu10k_load_dsp(emu10k_devc_t *devc, uint32_t *code, int ncode, 2035 uint32_t *init, int ninit) 2036 { 2037 int i; 2038 2039 if (ncode > 1024) { 2040 audio_dev_warn(devc->adev, "DSP file size too big"); 2041 return; 2042 } 2043 if (ninit > MAX_GPR) { 2044 audio_dev_warn(devc->adev, "Too many inits"); 2045 return; 2046 } 2047 2048 /* Upload our DSP code */ 2049 for (i = 0; i < ncode; i++) { 2050 emu10k_write_efx(devc, UC0 + i, code[i]); 2051 } 2052 2053 /* Upload the initialization settings */ 2054 for (i = 0; i < ninit; i += 2) { 2055 emu10k_write_reg(devc, init[i] + GPR0, 0, init[i + 1]); 2056 } 2057 } 2058 2059 #define LIVE_NOP() \ 2060 emu10k_write_efx(devc, UC0 + (pc * 2), 0x10040); \ 2061 emu10k_write_efx(devc, UC0 + (pc * 2 + 1), 0x610040); \ 2062 pc++ 2063 #define LIVE_ACC3(r, a, x, y) /* z=w+x+y */ \ 2064 emu10k_write_efx(devc, UC0 + (pc * 2), (x << 10) | y); \ 2065 emu10k_write_efx(devc, UC0 + (pc * 2 + 1), (6 << 20) | (r << 10) | a); \ 2066 pc++ 2067 2068 #define AUDIGY_ACC3(r, a, x, y) /* z=w+x+y */ \ 2069 emu10k_write_efx(devc, UC0 + (pc * 2), (x << 12) | y); \ 2070 emu10k_write_efx(devc, UC0 + (pc * 2+1), (6 << 24) | (r << 12) | a); \ 2071 pc++ 2072 #define AUDIGY_NOP() AUDIGY_ACC3(0xc0, 0xc0, 0xc0, 0xc0) 2073 2074 static void 2075 emu10k_init_effects(emu10k_devc_t *devc) 2076 { 2077 int i; 2078 unsigned short pc; 2079 2080 ASSERT(mutex_owned(&devc->mutex)); 2081 2082 if (devc->feature_mask & (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL)) { 2083 pc = 0; 2084 for (i = 0; i < 512; i++) { 2085 AUDIGY_NOP(); 2086 } 2087 2088 for (i = 0; i < 256; i++) 2089 emu10k_write_efx(devc, GPR0 + i, 0); 2090 emu10k_write_reg(devc, AUDIGY_DBG, 0, 0); 2091 emu10k_load_dsp(devc, 2092 emu10k2_code, 2093 sizeof (emu10k2_code) / sizeof (emu10k2_code[0]), 2094 emu10k2_init, 2095 sizeof (emu10k2_init) / sizeof (emu10k2_init[0])); 2096 2097 } else { 2098 pc = 0; 2099 for (i = 0; i < 512; i++) { 2100 LIVE_NOP(); 2101 } 2102 2103 for (i = 0; i < 256; i++) 2104 emu10k_write_efx(devc, GPR0 + i, 0); 2105 emu10k_write_reg(devc, DBG, 0, 0); 2106 emu10k_load_dsp(devc, 2107 emu10k1_code, 2108 sizeof (emu10k1_code) / sizeof (emu10k1_code[0]), 2109 emu10k1_init, 2110 sizeof (emu10k1_init) / sizeof (emu10k1_init[0])); 2111 } 2112 } 2113 2114 /* mixer */ 2115 2116 static struct { 2117 uint16_t devid; 2118 uint16_t subid; 2119 const char *model; 2120 const char *prod; 2121 unsigned feature_mask; 2122 } emu10k_cards[] = { 2123 { 0x2, 0x0020, "CT4670", "Live! Value", SB_LIVE | SB_NOEXP }, 2124 { 0x2, 0x0021, "CT4621", "Live!", SB_LIVE }, 2125 { 0x2, 0x100a, "SB0220", "Live! 5.1 Digital", 2126 SB_LIVE | SB_51 | SB_NOEXP }, 2127 { 0x2, 0x8022, "CT4780", "Live! Value", SB_LIVE }, 2128 { 0x2, 0x8023, "CT4790", "PCI512", SB_LIVE | SB_NOEXP }, 2129 { 0x2, 0x8026, "CT4830", "Live! Value", SB_LIVE }, 2130 { 0x2, 0x8028, "CT4870", "Live! Value", SB_LIVE }, 2131 { 0x2, 0x8031, "CT4831", "Live! Value", SB_LIVE }, 2132 { 0x2, 0x8040, "CT4760", "Live!", SB_LIVE }, 2133 { 0x2, 0x8051, "CT4850", "Live! Value", SB_LIVE }, 2134 { 0x2, 0x8061, "SB0060", "Live! 5.1", SB_LIVE | SB_51 }, 2135 { 0x2, 0x8064, "SB0100", "Live! 5.1", SB_LIVE | SB_51 }, 2136 { 0x2, 0x8065, "SB0220", "Live! 5.1", SB_LIVE | SB_51 }, 2137 { 0x2, 0x8066, "SB0228", "Live! 5.1", SB_LIVE | SB_51 }, 2138 { 0x4, 0x0051, "SB0090", "Audigy", SB_AUDIGY | SB_51 }, 2139 { 0x4, 0x0052, "SB0160", "Audigy ES", SB_AUDIGY | SB_51 }, 2140 { 0x4, 0x0053, "SB0092", "Audigy", SB_AUDIGY | SB_51 }, 2141 { 0x4, 0x1002, "SB0240P", "Audigy 2 Platinum", 2142 SB_AUDIGY2 | SB_71 | SB_INVSP }, 2143 { 0x4, 0x1003, "SB0353", "Audigy 2 ZS", SB_AUDIGY2 | SB_71 | SB_INVSP }, 2144 { 0x4, 0x1005, "SB0280", "Audigy 2 Platinum EX", SB_AUDIGY2 | SB_71 }, 2145 { 0x4, 0x1007, "SB0240", "Audigy 2", SB_AUDIGY2 | SB_71 }, 2146 { 0x4, 0x2001, "SB0360", "Audigy 2 ZS", SB_AUDIGY2 | SB_71 | SB_INVSP }, 2147 { 0x4, 0x2002, "SB0350", "Audigy 2 ZS", SB_AUDIGY2 | SB_71 | SB_INVSP }, 2148 { 0x4, 0x2006, "SB0350", "Audigy 2", SB_AUDIGY2 | SB_71 | SB_INVSP }, 2149 { 0x4, 0x2007, "SB0380", "Audigy 4 Pro", SB_AUDIGY2 | SB_71 }, 2150 { 0x8, 0x1001, "SB0400", "Audigy 2 Value", 2151 SB_AUDIGY2VAL | SB_71 | SB_NOEXP }, 2152 { 0x8, 0x1021, "SB0610", "Audigy 4", 2153 SB_AUDIGY2VAL | SB_71 | SB_NOEXP }, 2154 { 0x8, 0x2001, "SB0530", "Audigy 2 ZS Notebook", 2155 SB_AUDIGY2VAL | SB_71 }, 2156 { 0, 0, NULL, NULL, 0 }, 2157 }; 2158 2159 int 2160 emu10k_attach(dev_info_t *dip) 2161 { 2162 uint16_t pci_command; 2163 uint16_t subid; 2164 uint16_t devid; 2165 emu10k_devc_t *devc; 2166 ddi_acc_handle_t pcih; 2167 ddi_dma_cookie_t cookie; 2168 uint_t count; 2169 ulong_t len; 2170 int i; 2171 const char *name; 2172 const char *model; 2173 char namebuf[64]; 2174 int feature_mask; 2175 2176 devc = kmem_zalloc(sizeof (*devc), KM_SLEEP); 2177 devc->dip = dip; 2178 ddi_set_driver_private(dip, devc); 2179 2180 if ((devc->adev = audio_dev_alloc(dip, 0)) == NULL) { 2181 cmn_err(CE_WARN, "audio_dev_alloc failed"); 2182 goto error; 2183 } 2184 2185 if (pci_config_setup(dip, &pcih) != DDI_SUCCESS) { 2186 audio_dev_warn(devc->adev, "pci_config_setup failed"); 2187 goto error; 2188 } 2189 devc->pcih = pcih; 2190 2191 devid = pci_config_get16(pcih, PCI_CONF_DEVID); 2192 subid = pci_config_get16(pcih, PCI_CONF_SUBSYSID); 2193 2194 pci_command = pci_config_get16(pcih, PCI_CONF_COMM); 2195 pci_command |= PCI_COMM_ME | PCI_COMM_IO; 2196 pci_config_put16(pcih, PCI_CONF_COMM, pci_command); 2197 2198 if ((ddi_regs_map_setup(dip, 1, &devc->regs, 0, 0, &dev_attr, 2199 &devc->regsh)) != DDI_SUCCESS) { 2200 audio_dev_warn(devc->adev, "failed to map registers"); 2201 goto error; 2202 } 2203 2204 switch (devid) { 2205 case PCI_DEVICE_ID_SBLIVE: 2206 name = "Live!"; 2207 model = "CT????"; 2208 feature_mask = SB_LIVE; 2209 break; 2210 2211 case PCI_DEVICE_ID_AUDIGYVALUE: 2212 name = "Audigy 2 Value"; 2213 model = "SB????"; 2214 feature_mask = SB_AUDIGY2VAL; 2215 break; 2216 2217 case PCI_DEVICE_ID_AUDIGY: 2218 if (subid >= 0x1002 && subid <= 0x2005) { 2219 name = "Audigy 2"; 2220 model = "SB????"; 2221 feature_mask = SB_AUDIGY2; 2222 } else { 2223 name = "Audigy"; 2224 model = "SB????"; 2225 feature_mask = SB_AUDIGY; 2226 } 2227 break; 2228 2229 default: 2230 audio_dev_warn(devc->adev, "Unrecognized device"); 2231 goto error; 2232 } 2233 2234 for (i = 0; emu10k_cards[i].prod; i++) { 2235 if ((devid == emu10k_cards[i].devid) && 2236 (subid == emu10k_cards[i].subid)) { 2237 name = emu10k_cards[i].prod; 2238 model = emu10k_cards[i].model; 2239 feature_mask = emu10k_cards[i].feature_mask; 2240 break; 2241 } 2242 } 2243 devc->feature_mask = feature_mask; 2244 2245 (void) snprintf(namebuf, sizeof (namebuf), "Sound Blaster %s", name); 2246 2247 audio_dev_set_description(devc->adev, namebuf); 2248 audio_dev_set_version(devc->adev, model); 2249 2250 if (emu10k_setup_intrs(devc) != DDI_SUCCESS) 2251 goto error; 2252 2253 /* allocate static page table memory */ 2254 2255 devc->max_mem = AUDIO_MEMSIZE; 2256 2257 /* SB Live/Audigy supports at most 32M of memory) */ 2258 if (devc->max_mem > 32 * 1024 * 1024) 2259 devc->max_mem = 32 * 1024 * 1024; 2260 2261 devc->max_pages = devc->max_mem / 4096; 2262 if (devc->max_pages < 1024) 2263 devc->max_pages = 1024; 2264 2265 /* Allocate page table */ 2266 if (ddi_dma_alloc_handle(devc->dip, &dma_attr_buf, DDI_DMA_SLEEP, NULL, 2267 &devc->pt_dmah) != DDI_SUCCESS) { 2268 audio_dev_warn(devc->adev, 2269 "failed to allocate page table handle"); 2270 return (DDI_FAILURE); 2271 } 2272 2273 if (ddi_dma_mem_alloc(devc->pt_dmah, devc->max_pages * 4, 2274 &dev_attr, DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, 2275 &devc->pt_kaddr, &len, &devc->pt_acch) != 2276 DDI_SUCCESS) { 2277 audio_dev_warn(devc->adev, 2278 "failed to allocate memory for page table"); 2279 return (DDI_FAILURE); 2280 } 2281 2282 if (ddi_dma_addr_bind_handle(devc->pt_dmah, NULL, 2283 devc->pt_kaddr, len, DDI_DMA_CONSISTENT | DDI_DMA_WRITE, 2284 DDI_DMA_SLEEP, NULL, &cookie, &count) != DDI_SUCCESS) { 2285 audio_dev_warn(devc->adev, 2286 "failed binding page table DMA handle"); 2287 return (DDI_FAILURE); 2288 } 2289 2290 devc->page_map = (void *)devc->pt_kaddr; 2291 devc->pt_paddr = cookie.dmac_address; 2292 bzero(devc->pt_kaddr, devc->max_pages * 4); 2293 2294 /* Allocate silent page */ 2295 if (ddi_dma_alloc_handle(devc->dip, &dma_attr_buf, DDI_DMA_SLEEP, NULL, 2296 &devc->silence_dmah) != DDI_SUCCESS) { 2297 audio_dev_warn(devc->adev, 2298 "failed to allocate silent page handle"); 2299 return (DDI_FAILURE); 2300 } 2301 2302 if (ddi_dma_mem_alloc(devc->silence_dmah, 4096, 2303 &buf_attr, DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, 2304 &devc->silence_kaddr, &len, 2305 &devc->silence_acch) != DDI_SUCCESS) { 2306 audio_dev_warn(devc->adev, 2307 "failed to allocate silent page memory"); 2308 return (DDI_FAILURE); 2309 } 2310 2311 (void) ddi_dma_sync(devc->silence_dmah, 0, 0, DDI_DMA_SYNC_FORDEV); 2312 2313 if (ddi_dma_addr_bind_handle(devc->silence_dmah, NULL, 2314 devc->silence_kaddr, len, DDI_DMA_CONSISTENT | DDI_DMA_WRITE, 2315 DDI_DMA_SLEEP, NULL, &cookie, &count) != DDI_SUCCESS) { 2316 audio_dev_warn(devc->adev, 2317 "failed binding silent page DMA handle"); 2318 return (DDI_FAILURE); 2319 } 2320 2321 devc->silence_paddr = cookie.dmac_address; 2322 bzero(devc->silence_kaddr, 4096); 2323 devc->audio_memptr = 4096; /* Skip the silence page */ 2324 2325 for (i = 0; i < devc->max_pages; i++) 2326 FILL_PAGE_MAP_ENTRY(i, devc->silence_paddr); 2327 2328 (void) ddi_dma_sync(devc->pt_dmah, 0, 0, DDI_DMA_SYNC_FORDEV); 2329 2330 devc->ac97 = ac97_allocate(devc->adev, dip, 2331 emu10k_read_ac97, emu10k_write_ac97, devc); 2332 if (devc->ac97 == NULL) { 2333 audio_dev_warn(devc->adev, "failed to allocate ac97 handle"); 2334 goto error; 2335 } 2336 2337 ac97_probe_controls(devc->ac97); 2338 2339 /* allocate voice 0 for play */ 2340 if (emu10k_alloc_port(devc, EMU10K_REC) != DDI_SUCCESS) 2341 goto error; 2342 2343 if (emu10k_alloc_port(devc, EMU10K_PLAY) != DDI_SUCCESS) 2344 goto error; 2345 2346 /* now initialize the hardware */ 2347 mutex_enter(&devc->mutex); 2348 if (emu10k_hwinit(devc) != DDI_SUCCESS) { 2349 mutex_exit(&devc->mutex); 2350 goto error; 2351 } 2352 mutex_exit(&devc->mutex); 2353 2354 emu10k_create_controls(devc); 2355 2356 /* set up kernel statistics */ 2357 if ((devc->ksp = kstat_create(EMU10K_NAME, ddi_get_instance(dip), 2358 EMU10K_NAME, "controller", KSTAT_TYPE_INTR, 2359 1, KSTAT_FLAG_PERSISTENT)) != NULL) { 2360 kstat_install(devc->ksp); 2361 } 2362 2363 if (audio_dev_register(devc->adev) != DDI_SUCCESS) { 2364 audio_dev_warn(devc->adev, "unable to register audio device"); 2365 goto error; 2366 } 2367 2368 (void) ddi_intr_enable(devc->ih); 2369 ddi_report_dev(dip); 2370 2371 return (DDI_SUCCESS); 2372 2373 error: 2374 emu10k_destroy(devc); 2375 return (DDI_FAILURE); 2376 } 2377 2378 int 2379 emu10k_resume(dev_info_t *dip) 2380 { 2381 emu10k_devc_t *devc; 2382 emu10k_portc_t *portc; 2383 2384 devc = ddi_get_driver_private(dip); 2385 2386 for (int i = 0; i < EMU10K_NUM_PORTC; i++) { 2387 portc = devc->portc[i]; 2388 audio_engine_reset(portc->engine); 2389 } 2390 2391 mutex_enter(&devc->mutex); 2392 if (emu10k_hwinit(devc) != DDI_SUCCESS) { 2393 mutex_exit(&devc->mutex); 2394 /* 2395 * In case of failure, we leave the chip suspended, 2396 * but don't panic. Audio service is not normally a a 2397 * critical service. 2398 */ 2399 audio_dev_warn(devc->adev, "FAILED to RESUME device"); 2400 return (DDI_SUCCESS); 2401 } 2402 2403 emu10k_refresh_mixer(devc); 2404 2405 devc->suspended = B_FALSE; 2406 2407 for (int i = 0; i < EMU10K_NUM_PORTC; i++) { 2408 2409 portc = devc->portc[i]; 2410 2411 portc->stop_port(portc); 2412 2413 portc->dopos = 1; 2414 if (portc->started) { 2415 portc->reset_port(portc); 2416 portc->start_port(portc); 2417 } 2418 } 2419 2420 mutex_exit(&devc->mutex); 2421 2422 /* resume ac97 */ 2423 ac97_resume(devc->ac97); 2424 2425 return (DDI_SUCCESS); 2426 } 2427 2428 int 2429 emu10k_detach(emu10k_devc_t *devc) 2430 { 2431 if (audio_dev_unregister(devc->adev) != DDI_SUCCESS) 2432 return (DDI_FAILURE); 2433 2434 emu10k_destroy(devc); 2435 return (DDI_SUCCESS); 2436 } 2437 2438 int 2439 emu10k_suspend(emu10k_devc_t *devc) 2440 { 2441 ac97_suspend(devc->ac97); 2442 2443 mutex_enter(&devc->mutex); 2444 2445 devc->suspended = B_TRUE; 2446 2447 emu10k_write_reg(devc, CLIEL, 0, 0); 2448 emu10k_write_reg(devc, CLIEH, 0, 0); 2449 if (!(devc->feature_mask & SB_LIVE)) { 2450 emu10k_write_reg(devc, HLIEL, 0, 0x0); 2451 emu10k_write_reg(devc, HLIEH, 0, 0x0); 2452 } 2453 OUTL(devc, 0, devc->regs + IE); /* Intr enable (all off) */ 2454 2455 for (int i = 0; i < EMU10K_NUM_PORTC; i++) { 2456 emu10k_portc_t *portc = devc->portc[i]; 2457 portc->stop_port(portc); 2458 } 2459 2460 /* stop all voices */ 2461 for (int i = 0; i < 64; i++) { 2462 emu10k_write_reg(devc, VEDS, i, 0); 2463 } 2464 for (int i = 0; i < 64; i++) { 2465 emu10k_write_reg(devc, VTFT, i, 0); 2466 emu10k_write_reg(devc, CVCF, i, 0); 2467 emu10k_write_reg(devc, PTAB, i, 0); 2468 emu10k_write_reg(devc, CPF, i, 0); 2469 } 2470 /* 2471 * Turn off the hardware 2472 */ 2473 OUTL(devc, 2474 HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK | 2475 HCFG_MUTEBUTTONENABLE, devc->regs + HCFG); 2476 2477 /* stop ADC recording */ 2478 emu10k_write_reg(devc, ADCSR, 0, 0x0); 2479 emu10k_write_reg(devc, ADCBA, 0, 0x0); 2480 emu10k_write_reg(devc, ADCBA, 0, 0x0); 2481 2482 emu10k_write_reg(devc, PTBA, 0, 0); 2483 2484 mutex_exit(&devc->mutex); 2485 2486 return (DDI_SUCCESS); 2487 } 2488 2489 static int emu10k_ddi_attach(dev_info_t *, ddi_attach_cmd_t); 2490 static int emu10k_ddi_detach(dev_info_t *, ddi_detach_cmd_t); 2491 static int emu10k_ddi_quiesce(dev_info_t *); 2492 2493 static struct dev_ops emu10k_dev_ops = { 2494 DEVO_REV, /* rev */ 2495 0, /* refcnt */ 2496 NULL, /* getinfo */ 2497 nulldev, /* identify */ 2498 nulldev, /* probe */ 2499 emu10k_ddi_attach, /* attach */ 2500 emu10k_ddi_detach, /* detach */ 2501 nodev, /* reset */ 2502 NULL, /* cb_ops */ 2503 NULL, /* bus_ops */ 2504 NULL, /* power */ 2505 emu10k_ddi_quiesce, /* quiesce */ 2506 }; 2507 2508 static struct modldrv emu10k_modldrv = { 2509 &mod_driverops, /* drv_modops */ 2510 "Creative EMU10K Audio", /* linkinfo */ 2511 &emu10k_dev_ops, /* dev_ops */ 2512 }; 2513 2514 static struct modlinkage modlinkage = { 2515 MODREV_1, 2516 { &emu10k_modldrv, NULL } 2517 }; 2518 2519 int 2520 _init(void) 2521 { 2522 int rv; 2523 2524 audio_init_ops(&emu10k_dev_ops, EMU10K_NAME); 2525 if ((rv = mod_install(&modlinkage)) != 0) { 2526 audio_fini_ops(&emu10k_dev_ops); 2527 } 2528 return (rv); 2529 } 2530 2531 int 2532 _fini(void) 2533 { 2534 int rv; 2535 2536 if ((rv = mod_remove(&modlinkage)) == 0) { 2537 audio_fini_ops(&emu10k_dev_ops); 2538 } 2539 return (rv); 2540 } 2541 2542 int 2543 _info(struct modinfo *modinfop) 2544 { 2545 return (mod_info(&modlinkage, modinfop)); 2546 } 2547 2548 int 2549 emu10k_ddi_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 2550 { 2551 switch (cmd) { 2552 case DDI_ATTACH: 2553 return (emu10k_attach(dip)); 2554 2555 case DDI_RESUME: 2556 return (emu10k_resume(dip)); 2557 2558 default: 2559 return (DDI_FAILURE); 2560 } 2561 } 2562 2563 int 2564 emu10k_ddi_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 2565 { 2566 emu10k_devc_t *devc; 2567 2568 devc = ddi_get_driver_private(dip); 2569 2570 switch (cmd) { 2571 case DDI_DETACH: 2572 return (emu10k_detach(devc)); 2573 2574 case DDI_SUSPEND: 2575 return (emu10k_suspend(devc)); 2576 2577 default: 2578 return (DDI_FAILURE); 2579 } 2580 } 2581 2582 int 2583 emu10k_ddi_quiesce(dev_info_t *dip) 2584 { 2585 emu10k_devc_t *devc; 2586 2587 devc = ddi_get_driver_private(dip); 2588 2589 /* stop all voices */ 2590 for (int i = 0; i < 64; i++) { 2591 emu10k_write_reg(devc, VEDS, i, 0); 2592 } 2593 for (int i = 0; i < 64; i++) { 2594 emu10k_write_reg(devc, VTFT, i, 0); 2595 emu10k_write_reg(devc, CVCF, i, 0); 2596 emu10k_write_reg(devc, PTAB, i, 0); 2597 emu10k_write_reg(devc, CPF, i, 0); 2598 } 2599 2600 /* 2601 * Turn off the hardware 2602 */ 2603 OUTL(devc, 0, devc->regs + IE); /* Intr enable (all off) */ 2604 OUTL(devc, 2605 HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK | 2606 HCFG_MUTEBUTTONENABLE, devc->regs + HCFG); 2607 2608 /* stop ADC recording */ 2609 emu10k_write_reg(devc, ADCSR, 0, 0x0); 2610 emu10k_write_reg(devc, ADCBA, 0, 0x0); 2611 emu10k_write_reg(devc, ADCBA, 0, 0x0); 2612 2613 emu10k_write_reg(devc, PTBA, 0, 0); 2614 2615 return (DDI_SUCCESS); 2616 } 2617