1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 /* 26 * Purpose: Driver for CMEDIA CM8738 PCI audio controller. 27 */ 28 /* 29 * This file is part of Open Sound System 30 * 31 * Copyright (C) 4Front Technologies 1996-2008. 32 * 33 * This software is released under CDDL 1.0 source license. 34 * See the COPYING file included in the main directory of this source 35 * distribution for the license terms and conditions. 36 */ 37 38 #ifndef _AUDIOCMI_H 39 #define _AUDIOCMI_H 40 41 #define CMEDIA_VENDOR_ID 0x13F6 42 #define CMEDIA_CM8738 0x0111 43 #define CMEDIA_CM8338A 0x0100 44 #define CMEDIA_CM8338B 0x0101 45 46 /* 47 * CM8338 registers definition 48 */ 49 50 #define REG_FUNCTRL0 0x00 51 #define REG_FUNCTRL1 0x04 52 #define REG_CHFORMAT 0x08 53 #define REG_INTCTRL 0x0C 54 #define REG_INTSTAT 0x10 55 #define REG_LEGACY 0x14 56 #define REG_MISC 0x18 57 #define REG_TDMAPOS 0x1C 58 #define REG_SBVER 0x20 /* 8 bit access only */ 59 #define REG_IDXDATA 0x22 /* 8 bit access only */ 60 #define REG_IDXADDR 0x23 /* 8 bit access only */ 61 #define REG_MIX2 0x24 62 #define REG_MIX3 0x25 63 #define REG_VAUX 0x26 64 #define REG_CH0_PADDR 0x80 /* buffer address (32b) */ 65 #define REG_CH0_BUFSZ 0x84 /* buffer size in samples (16b) */ 66 #define REG_CH0_FRAGSZ 0x86 /* fragment size in samples (16b) */ 67 #define REG_CH1_PADDR 0x88 68 #define REG_CH1_BUFSZ 0x8C 69 #define REG_CH1_FRAGSZ 0x8E 70 71 #define FUNCTRL0_CH1_RST BIT(19) 72 #define FUNCTRL0_CH0_RST BIT(18) 73 #define FUNCTRL0_CH1_EN BIT(17) 74 #define FUNCTRL0_CH0_EN BIT(16) 75 #define FUNCTRL0_CH1_PAUSE BIT(3) 76 #define FUNCTRL0_CH0_PAUSE BIT(2) 77 #define FUNCTRL0_CH1_REC BIT(1) 78 #define FUNCTRL0_CH0_REC BIT(0) 79 80 #define FUNCTRL1_DAC_RATE_MASK (0x7 << 13) 81 #define FUNCTRL1_DAC_RATE_48K (0x7 << 13) 82 #define FUNCTRL1_DAC_RATE_32K (0x6 << 13) 83 #define FUNCTRL1_DAC_RATE_16K (0x5 << 13) 84 #define FUNCTRL1_DAC_RATE_8K (0x4 << 13) 85 #define FUNCTRL1_DAC_RATE_44K (0x3 << 13) 86 #define FUNCTRL1_DAC_RATE_22K (0x2 << 13) 87 #define FUNCTRL1_DAC_RATE_11K (0x1 << 13) 88 #define FUNCTRL1_DAC_RATE_5K (0x0 << 13) 89 #define FUNCTRL1_ADC_RATE_MASK (0x7 << 10) 90 #define FUNCTRL1_ADC_RATE_48K (0x7 << 10) 91 #define FUNCTRL1_ADC_RATE_32K (0x6 << 10) 92 #define FUNCTRL1_ADC_RATE_16K (0x5 << 10) 93 #define FUNCTRL1_ADC_RATE_8K (0x4 << 10) 94 #define FUNCTRL1_ADC_RATE_44K (0x3 << 10) 95 #define FUNCTRL1_ADC_RATE_22K (0x2 << 10) 96 #define FUNCTRL1_ADC_RATE_11K (0x1 << 10) 97 #define FUNCTRL1_ADC_RATE_5K (0x0 << 10) 98 #define FUNCTRL1_INTRM BIT(5) /* enable MCB intr */ 99 #define FUNCTRL1_BREQ BIT(4) /* bus master enable */ 100 #define FUNCTRL1_VOICE_EN BIT(3) 101 #define FUNCTRL1_UART_EN BIT(2) 102 #define FUNCTRL1_JYSTK_EN BIT(1) 103 104 #define CHFORMAT_CH1_MASK (0x3 << 2) 105 #define CHFORMAT_CH1_16ST (0x3 << 2) 106 #define CHFORMAT_CH1_16MO (0x2 << 2) 107 #define CHFORMAT_CH1_8ST (0x1 << 2) 108 #define CHFORMAT_CH1_8MO (0x0 << 2) 109 #define CHFORMAT_CH0_MASK (0x3 << 0) 110 #define CHFORMAT_CH0_16ST (0x3 << 0) 111 #define CHFORMAT_CH0_16MO (0x2 << 0) 112 #define CHFORMAT_CH0_8ST (0x1 << 0) 113 #define CHFORMAT_CH0_8MO (0x0 << 0) 114 115 #define INTCTRL_TDMA_EN BIT(18) 116 #define INTCTRL_CH1_EN BIT(17) 117 #define INTCTRL_CH0_EN BIT(16) 118 119 #define INTSTAT_INTR BIT(31) 120 #define INTSTAT_MCB_INT BIT(26) 121 #define INTSTAT_UART_INT BIT(16) 122 #define INTSTAT_LTDMA_INT BIT(15) 123 #define INTSTAT_HTDMA_INT BIT(14) 124 #define INTSTAT_LHBTOG BIT(7) 125 #define INTSTAT_LEGDMA BIT(6) 126 #define INTSTAT_LEGHIGH BIT(5) 127 #define INTSTAT_LEGSTEREO BIT(4) 128 #define INTSTAT_CH1_BUSY BIT(3) 129 #define INTSTAT_CH0_BUSY BIT(2) 130 #define INTSTAT_CH1_INT BIT(1) 131 #define INTSTAT_CH0_INT BIT(0) 132 133 #define MISC_PWD BIT(31) /* power down */ 134 #define MISC_RESET BIT(30) 135 #define MISC_ENDBDAC BIT(23) /* dual dac */ 136 #define MISC_XCHGDAC BIT(22) /* swap front/rear dacs */ 137 #define MISC_FM_EN BIT(19) /* enable legacy FM */ 138 139 #define MIX2_FMMUTE BIT(7) 140 #define MIX2_WSMUTE BIT(6) 141 #define MIX2_WAVEIN_L BIT(3) /* for recording wave out */ 142 #define MIX2_WAVEIN_R BIT(2) /* for recording wave out */ 143 144 #define MIX3_RAUXREN BIT(7) 145 #define MIX3_RAUXLEN BIT(6) 146 #define MIX3_VAUXRM BIT(5) /* r-aux mute */ 147 #define MIX3_VAUXLM BIT(4) /* l-aux mute */ 148 #define MIX3_VADCMIC_MASK (0x7 << 1) /* rec mic volume */ 149 #define MIX3_MICGAINZ BIT(0) /* mic gain */ 150 151 #define VAUX_L_MASK 0xf0 152 #define VAUX_R_MASK 0x0f 153 154 /* Indexes via SBINDEX */ 155 #define IDX_MASTER_LEFT 0x30 156 #define IDX_MASTER_RIGHT 0x31 157 #define IDX_VOICE_LEFT 0x32 /* PCM volume */ 158 #define IDX_VOICE_RIGHT 0x33 159 #define IDX_CDDA_LEFT 0x36 160 #define IDX_CDDA_RIGHT 0x37 161 #define IDX_LINEIN_LEFT 0x38 162 #define IDX_LINEIN_RIGHT 0x39 163 #define IDX_MIC 0x3A 164 #define IDX_SPEAKER 0x3B 165 #define IDX_OUTMIX 0x3C 166 #define OUTMIX_MIC 0x01 167 #define OUTMIX_CD_R 0x02 168 #define OUTMIX_CD_L 0x04 169 #define OUTMIX_LINE_R 0x08 170 #define OUTMIX_LINE_L 0x10 171 #define IDX_INMIX_L 0x3D 172 #define IDX_INMIX_R 0x3E 173 #define INMIX_LINE_R 0x08 174 #define INMIX_LINE_L 0x10 175 #define INMIX_CD_R 0x20 176 #define INMIX_CD_L 0x40 177 #define INMIX_MIC 0x01 178 #define IDX_IGAIN_L 0x3F 179 #define IDX_IGAIN_R 0x40 180 #define IDX_OGAIN_L 0x41 181 #define IDX_OGAIN_R 0x42 182 #define IDX_AGC 0x43 183 #define IDX_TREBLE_L 0x44 184 #define IDX_TREBLE_R 0x45 185 #define IDX_BASS_L 0x46 186 #define IDX_BASS_R 0x47 187 188 189 #define IDX_EXTENSION 0xf0 190 191 #define EXTENSION_VPHONE_MASK (0x7 << 5) 192 #define EXTENSION_VPHONE_MUTE BIT(4) 193 #define EXTENSION_BEEPER_MUTE BIT(3) 194 #define EXTENSION_VADCMIC3 BIT(0) 195 196 enum { 197 SRC_MIC = 0, 198 SRC_LINE, 199 SRC_CD, 200 SRC_AUX, 201 SRC_MIX, 202 }; 203 204 enum { 205 CTL_VOLUME = 0, 206 CTL_LINEOUT, 207 CTL_SPEAKER, 208 CTL_MIC, 209 CTL_LINEIN, 210 CTL_CD, 211 CTL_AUX, 212 CTL_RECSRCS, 213 CTL_MONSRCS, 214 CTL_MICBOOST, 215 CTL_NUM 216 }; 217 218 typedef struct cmpci_port cmpci_port_t; 219 typedef struct cmpci_dev cmpci_dev_t; 220 typedef struct cmpci_ctrl cmpci_ctrl_t; 221 222 struct cmpci_ctrl { 223 cmpci_dev_t *dev; 224 audio_ctrl_t *ctrl; 225 uint64_t value; 226 }; 227 228 struct cmpci_port { 229 cmpci_dev_t *dev; 230 audio_engine_t *engine; 231 int num; 232 ddi_acc_handle_t acch; 233 ddi_dma_handle_t dmah; 234 caddr_t kaddr; 235 uint32_t paddr; 236 unsigned fragfr; 237 unsigned nfrags; 238 unsigned nframes; 239 unsigned bufsz; 240 241 boolean_t capture; 242 boolean_t open; 243 244 /* registers & bit masks */ 245 uint8_t reg_paddr; 246 uint8_t reg_bufsz; 247 uint8_t reg_fragsz; 248 249 uint32_t fc0_rst_bit; 250 uint32_t fc0_rec_bit; 251 uint32_t fc0_en_bit; 252 uint32_t int_en_bit; 253 uint32_t fc1_rate_mask; 254 uint32_t chformat_mask; 255 int sync_dir; 256 257 uint32_t offset; /* in bytes */ 258 uint64_t count; /* in bytes */ 259 260 void (*callb)(audio_engine_t *); 261 cmpci_ctrl_t controls[CTL_NUM]; 262 }; 263 264 #define PORT_MAX 2 265 266 struct cmpci_dev { 267 audio_dev_t *adev; 268 dev_info_t *dip; 269 ddi_acc_handle_t acch; 270 caddr_t regs; 271 272 int pintrs; 273 int rintrs; 274 ddi_intr_handle_t ihandle; 275 kstat_t *ksp; 276 277 int model; 278 #define MDL_CM8738 1 279 #define MDL_CM8338A 2 280 #define MDL_CM8338B 3 281 #define MDL_CM8768 4 282 char *chip_name; 283 int chiprev; 284 285 boolean_t suspended; 286 287 kmutex_t mutex; 288 cmpci_port_t port[PORT_MAX]; 289 cmpci_ctrl_t controls[CTL_NUM]; 290 }; 291 292 /* 293 * The hardware appears to be able to address up to 16-bits worth of samples, 294 * giving a total address space of 256K. Note, however, that we will restrict 295 * this further when we do fragment and memory allocation. 296 */ 297 #define CMPCI_BUF_LEN (65536) 298 #define DEFINTS 175 299 300 #define GET8(dev, offset) \ 301 ddi_get8(dev->acch, (uint8_t *)(dev->regs + (offset))) 302 #define GET16(dev, offset) \ 303 ddi_get16(dev->acch, (uint16_t *)(void *)(dev->regs + (offset))) 304 #define GET32(dev, offset) \ 305 ddi_get32(dev->acch, (uint32_t *)(void *)(dev->regs + (offset))) 306 #define PUT8(dev, offset, v) \ 307 ddi_put8(dev->acch, (uint8_t *)(dev->regs + (offset)), v) 308 #define PUT16(dev, offset, v) \ 309 ddi_put16(dev->acch, (uint16_t *)(void *)(dev->regs + (offset)), v) 310 #define PUT32(dev, offset, v) \ 311 ddi_put32(dev->acch, (uint32_t *)(void *)(dev->regs + (offset)), v) 312 313 #define CLR8(dev, offset, v) PUT8(dev, offset, GET8(dev, offset) & ~(v)) 314 #define SET8(dev, offset, v) PUT8(dev, offset, GET8(dev, offset) | (v)) 315 #define CLR16(dev, offset, v) PUT16(dev, offset, GET16(dev, offset) & ~(v)) 316 #define SET16(dev, offset, v) PUT16(dev, offset, GET16(dev, offset) | (v)) 317 #define CLR32(dev, offset, v) PUT32(dev, offset, GET32(dev, offset) & ~(v)) 318 #define SET32(dev, offset, v) PUT32(dev, offset, GET32(dev, offset) | (v)) 319 320 #define KSINTR(dev) ((kstat_intr_t *)((dev)->ksp->ks_data)) 321 322 #define BIT(n) (1U << (n)) 323 324 #endif /* _AUDIOCMI_H */ 325