188447a05SGarrett D'Amore /* 288447a05SGarrett D'Amore * CDDL HEADER START 388447a05SGarrett D'Amore * 488447a05SGarrett D'Amore * The contents of this file are subject to the terms of the 588447a05SGarrett D'Amore * Common Development and Distribution License (the "License"). 688447a05SGarrett D'Amore * You may not use this file except in compliance with the License. 788447a05SGarrett D'Amore * 888447a05SGarrett D'Amore * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 988447a05SGarrett D'Amore * or http://www.opensolaris.org/os/licensing. 1088447a05SGarrett D'Amore * See the License for the specific language governing permissions 1188447a05SGarrett D'Amore * and limitations under the License. 1288447a05SGarrett D'Amore * 1388447a05SGarrett D'Amore * When distributing Covered Code, include this CDDL HEADER in each 1488447a05SGarrett D'Amore * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 1588447a05SGarrett D'Amore * If applicable, add the following below this CDDL HEADER, with the 1688447a05SGarrett D'Amore * fields enclosed by brackets "[]" replaced with your own identifying 1788447a05SGarrett D'Amore * information: Portions Copyright [yyyy] [name of copyright owner] 1888447a05SGarrett D'Amore * 1988447a05SGarrett D'Amore * CDDL HEADER END 2088447a05SGarrett D'Amore */ 2188447a05SGarrett D'Amore /* 22*68c47f65SGarrett D'Amore * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 2388447a05SGarrett D'Amore * Use is subject to license terms. 2488447a05SGarrett D'Amore */ 2588447a05SGarrett D'Amore 2688447a05SGarrett D'Amore #ifndef _AUDIO810_H_ 2788447a05SGarrett D'Amore #define _AUDIO810_H_ 2888447a05SGarrett D'Amore 2988447a05SGarrett D'Amore /* 3088447a05SGarrett D'Amore * Header file for the audio810 device driver 3188447a05SGarrett D'Amore */ 3288447a05SGarrett D'Amore 3388447a05SGarrett D'Amore /* 3488447a05SGarrett D'Amore * Driver supported configuration information 3588447a05SGarrett D'Amore */ 3688447a05SGarrett D'Amore #define I810_NAME "audio810" 3788447a05SGarrett D'Amore #define I810_MOD_NAME "audio810 audio driver" 3888447a05SGarrett D'Amore 3988447a05SGarrett D'Amore /* 4088447a05SGarrett D'Amore * Misc. defines 4188447a05SGarrett D'Amore */ 4288447a05SGarrett D'Amore 4388447a05SGarrett D'Amore #define I810_BD_NUMS (32) 4488447a05SGarrett D'Amore #define I810_NUM_PORTS (2) 4588447a05SGarrett D'Amore #define I810_MOD_SIZE (16) 4688447a05SGarrett D'Amore 4788447a05SGarrett D'Amore #define I810_ROUNDUP(x, algn) (((x) + ((algn) - 1)) & ~((algn) - 1)) 4888447a05SGarrett D'Amore 4988447a05SGarrett D'Amore /* The size of each entry of "reg" property is 5 integers */ 5088447a05SGarrett D'Amore #define I810_INTS_PER_REG_PROP 5 5188447a05SGarrett D'Amore 5288447a05SGarrett D'Amore /* offset from the base of specified DMA engine */ 5388447a05SGarrett D'Amore #define I810_OFFSET_BD_BASE (0x00) 5488447a05SGarrett D'Amore #define I810_OFFSET_CIV (0x04) 5588447a05SGarrett D'Amore #define I810_OFFSET_LVI (0x05) 5688447a05SGarrett D'Amore #define I810_OFFSET_SR (0x06) 5788447a05SGarrett D'Amore #define I810_OFFSET_PICB (0x08) 5888447a05SGarrett D'Amore #define I810_OFFSET_PIV (0x0A) 5988447a05SGarrett D'Amore #define I810_OFFSET_CR (0x0B) 6088447a05SGarrett D'Amore 6188447a05SGarrett D'Amore /* DMA engine offset from base */ 6288447a05SGarrett D'Amore #define I810_BASE_PCM_IN (0x00) 6388447a05SGarrett D'Amore #define I810_BASE_PCM_OUT (0x10) 6488447a05SGarrett D'Amore #define I810_BASE_MIC (0x20) 6588447a05SGarrett D'Amore 6688447a05SGarrett D'Amore #define I810_REG_GCR 0x2C 6788447a05SGarrett D'Amore #define I810_REG_GSR 0x30 6888447a05SGarrett D'Amore #define I810_REG_CASR 0x34 6988447a05SGarrett D'Amore #define I810_REG_SISCTL 0x4C /* SiS 7012 control */ 7088447a05SGarrett D'Amore 7188447a05SGarrett D'Amore /* bits of bus master status register */ 7288447a05SGarrett D'Amore #define I810_BM_SR_DCH 0x01 7388447a05SGarrett D'Amore #define I810_BM_SR_CELV 0x02 7488447a05SGarrett D'Amore #define I810_BM_SR_LVBCI 0x04 7588447a05SGarrett D'Amore #define I810_BM_SR_BCIS 0x08 7688447a05SGarrett D'Amore #define I810_BM_SR_FIFOE 0x10 7788447a05SGarrett D'Amore 7888447a05SGarrett D'Amore /* bits of bus master control register */ 7988447a05SGarrett D'Amore #define I810_BM_CR_RUN 0x01 8088447a05SGarrett D'Amore #define I810_BM_CR_RST 0x02 8188447a05SGarrett D'Amore #define I810_BM_CR_LVBIE 0x04 8288447a05SGarrett D'Amore #define I810_BM_CR_FEIE 0x08 8388447a05SGarrett D'Amore #define I810_BM_CR_IOCE 0x10 8488447a05SGarrett D'Amore 8588447a05SGarrett D'Amore #define I810_BM_CR_PAUSE 0x00 8688447a05SGarrett D'Amore 8788447a05SGarrett D'Amore /* 8888447a05SGarrett D'Amore * Global Control Register 8988447a05SGarrett D'Amore */ 9088447a05SGarrett D'Amore #define I810_GCR_GPIE 0x00000001 9188447a05SGarrett D'Amore #define I810_GCR_COLD_RST 0x00000002 9288447a05SGarrett D'Amore #define I810_GCR_WARM_RST 0x00000004 9388447a05SGarrett D'Amore #define I810_GCR_ACLINK_OFF 0x00000008 9488447a05SGarrett D'Amore #define I810_GCR_PRI_INTR_ENABLE 0x00000010 9588447a05SGarrett D'Amore #define I810_GCR_SEC_INTR_ENABLE 0x00000020 9688447a05SGarrett D'Amore 9788447a05SGarrett D'Amore /* For ICH2 or more, bit21:20 is the PCM 4/6-channel enable bits */ 9888447a05SGarrett D'Amore #define I810_GCR_2_CHANNELS (0 << 20) 9988447a05SGarrett D'Amore #define I810_GCR_4_CHANNELS (1 << 20) 10088447a05SGarrett D'Amore #define I810_GCR_6_CHANNELS (2 << 20) 10188447a05SGarrett D'Amore #define I810_GCR_CHANNELS_MASK (3 << 20) 10288447a05SGarrett D'Amore /* SiS 7012 has its own flags here */ 10388447a05SGarrett D'Amore #define I810_GCR_SIS_2_CHANNELS (0 << 6) 10488447a05SGarrett D'Amore #define I810_GCR_SIS_4_CHANNELS (1 << 6) 10588447a05SGarrett D'Amore #define I810_GCR_SIS_6_CHANNELS (2 << 6) 10688447a05SGarrett D'Amore #define I810_GCR_SIS_CHANNELS_MASK (3 << 6) 10788447a05SGarrett D'Amore 10888447a05SGarrett D'Amore 10988447a05SGarrett D'Amore /* 11088447a05SGarrett D'Amore * Global Status Register 11188447a05SGarrett D'Amore */ 11288447a05SGarrett D'Amore #define I810_GSR_TRI_READY 0x10000000 /* for ICH4/5 */ 11388447a05SGarrett D'Amore #define I810_GSR_CAP8CH 0x00400000 11488447a05SGarrett D'Amore #define I810_GSR_CAP6CH 0x00200000 11588447a05SGarrett D'Amore #define I810_GSR_CAP4CH 0x00100000 11688447a05SGarrett D'Amore #define I810_GSR_READ_COMPL 0x00008000 11788447a05SGarrett D'Amore #define I810_GSR_INTR_SEC_RESUME 0x00000800 11888447a05SGarrett D'Amore #define I810_GSR_INTR_PRI_RESUME 0x00000400 11988447a05SGarrett D'Amore #define I810_GSR_SEC_READY 0x00000200 12088447a05SGarrett D'Amore #define I810_GSR_PRI_READY 0x00000100 12188447a05SGarrett D'Amore #define I810_GSR_INTR_MIC 0x00000080 12288447a05SGarrett D'Amore #define I810_GSR_INTR_POUT 0x00000040 12388447a05SGarrett D'Amore #define I810_GSR_INTR_PIN 0x00000020 12488447a05SGarrett D'Amore #define I810_GSR_INTR_MO 0x00000004 12588447a05SGarrett D'Amore #define I810_GSR_INTR_MI 0x00000002 12688447a05SGarrett D'Amore #define I810_GSR_INTR_GSI 0x00000001 12788447a05SGarrett D'Amore #define I810_GSR_USE_INTR 0x00000060 /* PCM-IN ,PCM-OUT */ 12888447a05SGarrett D'Amore 12988447a05SGarrett D'Amore /* 13088447a05SGarrett D'Amore * SiS Control Register 13188447a05SGarrett D'Amore */ 13288447a05SGarrett D'Amore #define I810_SISCTL_UNMUTE 0x01 13388447a05SGarrett D'Amore 13488447a05SGarrett D'Amore /* 13588447a05SGarrett D'Amore * Macro for AD1980 codec 13688447a05SGarrett D'Amore */ 13788447a05SGarrett D'Amore #define AD1980_VID1 0x4144 13888447a05SGarrett D'Amore #define AD1980_VID2 0x5370 13988447a05SGarrett D'Amore #define AD1985_VID2 0x5375 14088447a05SGarrett D'Amore #define CODEC_AD_REG_MISC 0x76 /* offset of ad1980 misc control reg */ 14188447a05SGarrett D'Amore #define AD1980_MISC_LOSEL 0x0020 /* Line-out amplifier output selector */ 14288447a05SGarrett D'Amore #define AD1980_MISC_HPSEL 0x0400 /* HP-out amplifier output selector */ 14388447a05SGarrett D'Amore #define AD1980_SURR_MUTE 0x8080 /* Mute for surround volume register */ 14488447a05SGarrett D'Amore 14588447a05SGarrett D'Amore #define I810_PCM_IN 0 14688447a05SGarrett D'Amore #define I810_PCM_OUT 1 14788447a05SGarrett D'Amore 14888447a05SGarrett D'Amore struct audio810_port { 14988447a05SGarrett D'Amore struct audio810_state *statep; 15088447a05SGarrett D'Amore int num; 15188447a05SGarrett D'Amore ddi_dma_handle_t samp_dmah; 15288447a05SGarrett D'Amore ddi_acc_handle_t samp_acch; 153*68c47f65SGarrett D'Amore uint32_t samp_frames; 15488447a05SGarrett D'Amore size_t samp_size; 15588447a05SGarrett D'Amore caddr_t samp_kaddr; 15688447a05SGarrett D'Amore uint32_t samp_paddr; 15788447a05SGarrett D'Amore 15888447a05SGarrett D'Amore ddi_dma_handle_t bdl_dmah; 15988447a05SGarrett D'Amore ddi_acc_handle_t bdl_acch; 16088447a05SGarrett D'Amore size_t bdl_size; 16188447a05SGarrett D'Amore caddr_t bdl_kaddr; 16288447a05SGarrett D'Amore uint32_t bdl_paddr; 16388447a05SGarrett D'Amore 164*68c47f65SGarrett D'Amore uint32_t offset; 16588447a05SGarrett D'Amore uint64_t count; 16688447a05SGarrett D'Amore uint8_t nchan; 16788447a05SGarrett D'Amore 16888447a05SGarrett D'Amore uint8_t regoff; 16988447a05SGarrett D'Amore uint8_t stsoff; /* status offset */ 17088447a05SGarrett D'Amore uint8_t picboff; /* picb offset */ 17188447a05SGarrett D'Amore unsigned sync_dir; 17288447a05SGarrett D'Amore 17388447a05SGarrett D'Amore audio_engine_t *engine; 17488447a05SGarrett D'Amore }; 17588447a05SGarrett D'Amore typedef struct audio810_port audio810_port_t; 17688447a05SGarrett D'Amore 17788447a05SGarrett D'Amore /* 17888447a05SGarrett D'Amore * buffer descripter list entry, sees datasheet 17988447a05SGarrett D'Amore */ 18088447a05SGarrett D'Amore struct i810_bd_entry { 18188447a05SGarrett D'Amore uint32_t buf_base; /* the address of the buffer */ 18288447a05SGarrett D'Amore uint16_t buf_len; /* the number of samples */ 18388447a05SGarrett D'Amore uint16_t buf_cmd; 18488447a05SGarrett D'Amore }; 18588447a05SGarrett D'Amore typedef struct i810_bd_entry i810_bd_entry_t; 18688447a05SGarrett D'Amore #define BUF_CMD_BUP 0x4000 18788447a05SGarrett D'Amore #define BUF_CMD_IOC 0x8000 18888447a05SGarrett D'Amore 18988447a05SGarrett D'Amore typedef enum i810_quirk { 19088447a05SGarrett D'Amore QUIRK_NONE = 0, 191*68c47f65SGarrett D'Amore QUIRK_OLDICH, /* likely emulated, needs deeper playahead */ 19288447a05SGarrett D'Amore QUIRK_SIS7012, /* weird registers and such */ 19388447a05SGarrett D'Amore } i810_quirk_t; 19488447a05SGarrett D'Amore 19588447a05SGarrett D'Amore /* 19688447a05SGarrett D'Amore * audio810_state_t -per instance state and operation data 19788447a05SGarrett D'Amore */ 19888447a05SGarrett D'Amore struct audio810_state { 19988447a05SGarrett D'Amore dev_info_t *dip; /* used by audio810_getinfo() */ 20088447a05SGarrett D'Amore audio_dev_t *adev; 20188447a05SGarrett D'Amore ac97_t *ac97; 20288447a05SGarrett D'Amore audio810_port_t *ports[2]; 20388447a05SGarrett D'Amore 20488447a05SGarrett D'Amore ddi_acc_handle_t am_regs_handle; /* for audio mixer register */ 20588447a05SGarrett D'Amore ddi_acc_handle_t bm_regs_handle; /* for bus master register */ 20688447a05SGarrett D'Amore caddr_t am_regs_base; /* base of audio mixer regs */ 20788447a05SGarrett D'Amore caddr_t bm_regs_base; /* base of bus master regs */ 20888447a05SGarrett D'Amore 20988447a05SGarrett D'Amore kstat_t *ksp; /* kernel statistics */ 21088447a05SGarrett D'Amore 21188447a05SGarrett D'Amore uint8_t maxch; 21288447a05SGarrett D'Amore i810_quirk_t quirk; 21388447a05SGarrett D'Amore }; 21488447a05SGarrett D'Amore typedef struct audio810_state audio810_state_t; 21588447a05SGarrett D'Amore 21688447a05SGarrett D'Amore /* 21788447a05SGarrett D'Amore * Useful bit twiddlers 21888447a05SGarrett D'Amore */ 21988447a05SGarrett D'Amore #define I810_BM_GET8(reg) \ 22088447a05SGarrett D'Amore ddi_get8(statep->bm_regs_handle, \ 22188447a05SGarrett D'Amore (void *)((char *)statep->bm_regs_base + (reg))) 22288447a05SGarrett D'Amore 22388447a05SGarrett D'Amore #define I810_BM_GET16(reg) \ 22488447a05SGarrett D'Amore ddi_get16(statep->bm_regs_handle, \ 22588447a05SGarrett D'Amore (void *)((char *)statep->bm_regs_base + (reg))) 22688447a05SGarrett D'Amore 22788447a05SGarrett D'Amore #define I810_BM_GET32(reg) \ 22888447a05SGarrett D'Amore ddi_get32(statep->bm_regs_handle, \ 22988447a05SGarrett D'Amore (void *)((char *)statep->bm_regs_base + (reg))) 23088447a05SGarrett D'Amore 23188447a05SGarrett D'Amore #define I810_BM_PUT8(reg, val) \ 23288447a05SGarrett D'Amore ddi_put8(statep->bm_regs_handle, \ 23388447a05SGarrett D'Amore (void *)((char *)statep->bm_regs_base + (reg)), (val)) 23488447a05SGarrett D'Amore 23588447a05SGarrett D'Amore #define I810_BM_PUT16(reg, val) \ 23688447a05SGarrett D'Amore ddi_put16(statep->bm_regs_handle, \ 23788447a05SGarrett D'Amore (void *)((char *)statep->bm_regs_base + (reg)), (val)) 23888447a05SGarrett D'Amore 23988447a05SGarrett D'Amore #define I810_BM_PUT32(reg, val) \ 24088447a05SGarrett D'Amore ddi_put32(statep->bm_regs_handle, \ 24188447a05SGarrett D'Amore (void *)((char *)statep->bm_regs_base + (reg)), (val)) 24288447a05SGarrett D'Amore 24388447a05SGarrett D'Amore #define I810_AM_GET16(reg) \ 24488447a05SGarrett D'Amore ddi_get16(statep->am_regs_handle, \ 24588447a05SGarrett D'Amore (void *)((char *)statep->am_regs_base + (reg))) 24688447a05SGarrett D'Amore 24788447a05SGarrett D'Amore #define I810_AM_PUT16(reg, val) \ 24888447a05SGarrett D'Amore ddi_put16(statep->am_regs_handle, \ 24988447a05SGarrett D'Amore (void *)((char *)statep->am_regs_base + (reg)), (val)) 25088447a05SGarrett D'Amore 25188447a05SGarrett D'Amore #endif /* _AUDIO810_H_ */ 252