1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef AUDIO1575_H 27 #define AUDIO1575_H 28 29 /* 30 * Header file for the audio1575 device driver 31 */ 32 33 /* 34 * Driver supported configuration information 35 */ 36 #define M1575_NAME "audio1575" 37 #define M1575_MOD_NAME "M1575 audio driver" 38 39 #define M1575_INTS (175) /* default interrupt rate */ 40 #define M1575_MIN_INTS (25) /* minimum interrupt rate */ 41 #define M1575_MAX_INTS (5000) /* maximum interrupt rate */ 42 43 /* 44 * Implementation specific header file for the audio1575 device driver. 45 */ 46 47 /* Misc. defines */ 48 #define M1575_AUDIO_IO_SPACE (1) 49 50 #define M1575_LOOP_CTR (100) 51 52 /* audio direction */ 53 #define M1575_PLAY (0) 54 #define M1575_REC (1) 55 56 /* Buffer Descriptor List defines */ 57 #define M1575_BD_NUMS (32) 58 #define M1575_NUM_PORTS (2) 59 #define M1575_MOD_SIZE (16) 60 61 /* kstat interrupt counter define */ 62 #define M1575_KIOP(X) ((kstat_intr_t *)(X->ksp->ks_data)) 63 #define M1575_ROUNDUP(x, algn) (((x) + ((algn) - 1)) & ~((algn) - 1)) 64 65 /* PCI CFG SPACE REGISTERS for Audio (Device 29, Function 0) */ 66 #define M1575_PCIPMR_REG 0x42 /* Power Capabilities 16 */ 67 #define M1575_PCIPMCSR_REG 0x44 /* Power Cmd & Status 16 */ 68 #define M1575_PCISCCR_REG 0x48 /* System Cfg Cntrl 16 */ 69 #define M1575_PCIAPMUCR1_REG 0x54 /* Add. PMU Cntrl Reg 8 */ 70 #define M1575_PCISCRR_REG 0x57 /* Scratch Reg 8 */ 71 #define M1575_PCIMISC_REG 0x58 /* Misc Reg 8 */ 72 #define M1575_PCIGCC_REG 0x59 /* Global Clk Control 16 */ 73 #define M1575_PCIACD_REG 0x5C /* AC97 Codec Detect 8 */ 74 #define M1575_PCIMISC_REG 0x58 /* Misc Reg 8 */ 75 #define M1575_PCIGCLK_REG 0x59 /* Misc Reg 8 */ 76 #define M1575_PCIMSICTRL_REG 0x62 /* MSI Control Reg 16 */ 77 #define M1575_PCIMSIADDR_REG 0x64 /* MSI Address Reg 32 */ 78 #define M1575_PCIMSIDATA_REG 0x68 /* MSI Data Reg 16 */ 79 #define M1575_PCIMSIMASK_REG 0x6C /* MSI Data Reg 32 */ 80 #define M1575_PCIMSIPEND_REG 0x70 /* MSI Pend Reg 32 */ 81 82 /* Bit definitions for PCI AC97 Clk detect Reg */ 83 #define M1575_PCIACD_CLKDET 0x01 84 #define M1575_PCIMISC_INTENB 0x40 85 #define M1575_PCIINT_LINE 0x05 86 87 /* Base Line Audio I/O Memory Registers */ 88 #define M1575_SCR_REG 0x00 /* System Control Reg 32 */ 89 #define M1575_SSR_REG 0x04 /* System System Reg 32 */ 90 #define M1575_DMACR_REG 0x08 /* DMA Control Reg 32 */ 91 #define M1575_FIFOCR1_REG 0x0C /* FIFO 1 Control Reg 32 */ 92 #define M1575_INTFCR_REG 0x10 /* Interface Ctrl Reg 32 */ 93 #define M1575_INTRCR_REG 0x14 /* Interrupt Ctrl Reg 32 */ 94 #define M1575_INTRSR_REG 0x18 /* Interrupt Status Reg 32 */ 95 #define M1575_FIFOCR2_REG 0x1C /* FIFO 2 Control Reg 32 */ 96 #define M1575_CPR_REG 0x20 /* Cmd Port Reg 32 */ 97 #define M1575_SPR_REG 0x24 /* Status Port Reg 32 */ 98 #define M1575_FIFOCR3_REG 0x2C /* FIFO 3 Control Reg 32 */ 99 #define M1575_TTSR_REG 0x30 /* Tx Tag Slot Reg 32 */ 100 #define M1575_RTSR_REG 0x34 /* Rx Tag Slot Reg 32 */ 101 #define M1575_CSPSR_REG 0x38 /* CSP Status Reg 32 */ 102 #define M1575_CASR_REG 0x3C /* Codec Access Sem Reg 32 */ 103 104 /* PCM IN Registers */ 105 #define M1575_PCMIBDBAR_REG 0x40 /* 32 */ 106 #define M1575_PCMICIV_REG 0x44 /* 8 */ 107 #define M1575_PCMILVIV_REG 0x45 /* 8 */ 108 #define M1575_PCMISR_REG 0x46 /* 16 */ 109 #define M1575_PCMIPICB_REG 0x48 /* 16 */ 110 #define M1575_PCMICR_REG 0x4B /* 8 */ 111 112 /* PCM OUT Registers */ 113 #define M1575_PCMOBDBAR_REG 0x50 /* 32 */ 114 #define M1575_PCMOCIV_REG 0x54 /* 8 */ 115 #define M1575_PCMOLVIV_REG 0x55 /* 8 */ 116 #define M1575_PCMOSR_REG 0x56 /* 16 */ 117 #define M1575_PCMOPICB_REG 0x58 /* 16 */ 118 #define M1575_PCMOCR_REG 0x5B /* 8 */ 119 120 /* MIC In Registers */ 121 #define M1575_MICIBDBAR_REG 0x60 /* 32 */ 122 #define M1575_MICICIV_REG 0x64 /* 8 */ 123 #define M1575_MICILVIV_REG 0x65 /* 8 */ 124 #define M1575_MICISR_REG 0x66 /* 16 */ 125 #define M1575_MICIPICB_REG 0x68 /* 16 */ 126 #define M1575_MICICR_REG 0x6B /* 8 */ 127 128 /* SPIDOF Registers */ 129 #define M1575_CSPOBDBAR_REG 0x70 /* 32 */ 130 #define M1575_CSPOCIV_REG 0x74 /* 8 */ 131 #define M1575_CSPOLVIV_REG 0x75 /* 8 */ 132 #define M1575_CSPOSR_REG 0x76 /* 16 */ 133 #define M1575_CSPOPICB_REG 0x78 /* 16 */ 134 #define M1575_CSPOCR_REG 0x7B /* 8 */ 135 136 /* PCM IN2 Registers */ 137 #define M1575_PCMI2BDBAR_REG 0xd0 /* 32 */ 138 #define M1575_PCMI2CIV_REG 0xd4 /* 8 */ 139 #define M1575_PCMI2LVIV_REG 0xd5 /* 8 */ 140 #define M1575_PCMI2SR_REG 0xd6 /* 16 */ 141 #define M1575_PCMI2PICB_REG 0xd8 /* 16 */ 142 #define M1575_PCMI2CR_REG 0xdB /* 8 */ 143 144 /* MIC2 IN2 Registers */ 145 #define M1575_MICI2BDBAR_REG 0xe0 /* 32 */ 146 #define M1575_MICI2CIV_REG 0xe4 /* 8 */ 147 #define M1575_MICI2LVIV_REG 0xe5 /* 8 */ 148 #define M1575_MICI2SR_REG 0xe6 /* 16 */ 149 #define M1575_MICI2PICB_REG 0xe8 /* 16 */ 150 #define M1575_MICI2CR_REG 0xeB /* 8 */ 151 152 /* Bits of FIFO Control Register1 */ 153 #define M1575_FIFOCR1_CSPORST 0x80000000 /* SPDIF Out Reset */ 154 #define M1575_FIFOCR1_MICIRST 0x00800000 /* MIC In Reset */ 155 #define M1575_FIFOCR1_PCMORST 0x00008000 /* PCM Out Reset */ 156 #define M1575_FIFOCR1_PCMIRST 0x00000080 /* PCM In Reset */ 157 158 /* Bits of FIFO Control Register2 */ 159 #define M1575_FIFOCR2_SPORST 0x80000000 /* SPDIF Out FIFO Reset */ 160 #define M1575_FIFOCR2_SPIRST 0x00800000 /* SPDIF In FIFO Reset */ 161 #define M1575_FIFOCR2_LFEORST 0x00008000 /* LFE Out FIFO Reset */ 162 #define M1575_FIFOCR2_CENORST 0x00000080 /* CENTER Out Reset */ 163 164 /* Bits of FIFO Control Register3 */ 165 #define M1575_FIFOCR3_PCMI2RST 0x00800000 /* PCM In2 FIFO Reset */ 166 #define M1575_FIFOCR3_MICI2RST 0x00008000 /* MIC In2 FIFO Reset */ 167 #define M1575_FIFOCR3_I2SIRST 0x00000080 /* I2S In FIFO Reset */ 168 169 /* Bits of DMA Control Register */ 170 #define M1575_DMACR_PCMISTART 0x00000001 171 #define M1575_DMACR_PCMOSTART 0x00000002 172 #define M1575_DMACR_MICISTART 0x00000004 173 #define M1575_DMACR_CSPOSTART 0x00000008 174 #define M1575_DMACR_CENOSTART 0x00000010 175 #define M1575_DMACR_LFEOSTART 0x00000020 176 #define M1575_DMACR_SPISTART 0x00000040 177 #define M1575_DMACR_SPOSTART 0x00000080 178 #define M1575_DMACR_I2SISTART 0x00000100 179 #define M1575_DMACR_PCMI2START 0x00000200 180 #define M1575_DMACR_MICI2START 0x00000400 181 #define M1575_DMACR_PCMIPAUSE 0x00010000 182 #define M1575_DMACR_PCMOPAUSE 0x00020000 183 #define M1575_DMACR_MICIPAUSE 0x00040000 184 #define M1575_DMACR_CSPOPAUSE 0x00080000 185 #define M1575_DMACR_CENOPAUSE 0x00100000 186 #define M1575_DMACR_LFEOPAUSE 0x00200000 187 #define M1575_DMACR_SPIPAUSE 0x00400000 188 #define M1575_DMACR_SPOPAUSE 0x00800000 189 #define M1575_DMACR_I2SIPAUSE 0x01000000 190 #define M1575_DMACR_PCMI2PAUSE 0x02000000 191 #define M1575_DMACR_MICI2PAUSE 0x04000000 192 193 #define M1575_DMACR_PAUSE_ALL 0x07ff0000 194 195 /* Bits of INTRSR Interrupt Status Register */ 196 #define M1575_INTRSR_GPIOINTR 0x0000002 197 #define M1575_INTRSR_SPRINTR 0x0000020 198 #define M1575_INTRSR_CPRINTR 0x0000080 199 #define M1575_INTRSR_PCMIINTR 0x0010000 200 #define M1575_INTRSR_PCMOINTR 0x0020000 201 #define M1575_INTRSR_MICIINTR 0x0040000 202 #define M1575_INTRSR_CSPOINTR 0x0080000 203 #define M1575_INTRSR_CENOINTR 0x0100000 204 #define M1575_INTRSR_LFEOINTR 0x0200000 205 #define M1575_INTRSR_SPIINTR 0x0400000 206 #define M1575_INTRSR_SPOINTR 0x0800000 207 #define M1575_INTRSR_I2SIINTR 0x1000000 208 #define M1575_INTRSR_PCMI2INTR 0x2000000 209 #define M1575_INTRSR_MICI2INTR 0x4000000 210 211 #define M1575_INTR_MASK (M1575_INTRSR_GPIOINTR |\ 212 M1575_INTRSR_SPRINTR |\ 213 M1575_INTRSR_CPRINTR |\ 214 M1575_INTRSR_PCMIINTR |\ 215 M1575_INTRSR_PCMOINTR |\ 216 M1575_INTRSR_MICIINTR |\ 217 M1575_INTRSR_CSPOINTR |\ 218 M1575_INTRSR_CENOINTR |\ 219 M1575_INTRSR_LFEOINTR |\ 220 M1575_INTRSR_SPIINTR |\ 221 M1575_INTRSR_SPOINTR |\ 222 M1575_INTRSR_I2SIINTR |\ 223 M1575_INTRSR_PCMI2INTR|\ 224 M1575_INTRSR_MICI2INTR) 225 226 #define M1575_UNUSED_INTR_MASK (M1575_INTRSR_GPIOINTR |\ 227 M1575_INTRSR_SPRINTR |\ 228 M1575_INTRSR_CPRINTR |\ 229 M1575_INTRSR_MICIINTR |\ 230 M1575_INTRSR_CSPOINTR |\ 231 M1575_INTRSR_CENOINTR |\ 232 M1575_INTRSR_LFEOINTR |\ 233 M1575_INTRSR_SPIINTR |\ 234 M1575_INTRSR_SPOINTR |\ 235 M1575_INTRSR_I2SIINTR |\ 236 M1575_INTRSR_PCMI2INTR|\ 237 M1575_INTRSR_MICI2INTR) 238 239 /* Defines a generic clear for all MIC and PCM Status Registers */ 240 #define M1575_SR_CLR 0x001e 241 #define M1575_SR_DMACS 0x0001 242 243 /* Defines a generic RESET for all MIC and PCM Control Registers */ 244 #define M1575_CR_IOCE 0x10 245 #define M1575_CR_RR 0x02 246 247 /* Bits of PCM In Status Register */ 248 #define M1575_PCMISR_DMACS 0x01 /* DMACS=0 if DMA Engine is IDLE */ 249 #define M1575_PCMISR_CELV 0x02 250 #define M1575_PCMISR_LVBCI 0x04 251 #define M1575_PCMISR_BCIS 0x08 252 #define M1575_PCMISR_FIFOE 0x10 253 254 /* Bits in PCM In Control Register */ 255 #define M1575_PCMICR_RR 0x02 /* Reset */ 256 #define M1575_PCMICR_LVBIE 0x04 /* Last valid Buffer Intr Enable */ 257 #define M1575_PCMICR_IOCE 0x10 /* Intr On Completion Enable */ 258 259 /* Bits of PCM Out Status Register */ 260 #define M1575_PCMOSR_DMACS 0x01 /* DMACS=0 if DMA Engine is IDLE */ 261 #define M1575_PCMOSR_CELV 0x02 262 #define M1575_PCMOSR_LVBCI 0x04 263 #define M1575_PCMOSR_BCIS 0x08 264 #define M1575_PCMOSR_FIFOE 0x10 265 266 /* Bits in PCM Out Control Register */ 267 #define M1575_PCMOCR_RR 0x02 /* Reset */ 268 #define M1575_PCMOCR_LVBIE 0x04 /* Last valid Buffer Intr Enable */ 269 #define M1575_PCMOCR_IOCE 0x10 /* Intr On Completion Enable */ 270 271 /* Bits of MIC In Status Register */ 272 #define M1575_MICISR_DMACS 0x01 /* DMACS=0 if DMA Engine is IDLE */ 273 #define M1575_MICISR_CELV 0x02 274 #define M1575_MICISR_LVBCI 0x04 275 #define M1575_MICISR_BCIS 0x08 276 #define M1575_MICISR_FIFOE 0x10 277 278 /* Bits in PCM In Control Register */ 279 #define M1575_MICICR_RR 0x02 /* Reset */ 280 #define M1575_MICICR_LVBIE 0x04 /* Last valid Buffer Intr Enable */ 281 #define M1575_MICICR_IOCE 0x10 /* Intr On Completion Enable */ 282 283 /* Bits in System Control Register */ 284 #define M1575_SCR_WARMRST 0x00000001 285 #define M1575_SCR_COLDRST 0x00000002 286 #define M1575_SCR_SPDIF_SLOT 0x00300000 /* 1=7/8, 2=6/9, 3=10/11 */ 287 #define M1575_SCR_RECMOD 0x000c0000 /* 0 = 16bit, 1=20 bit */ 288 #define M1575_SCR_PCMMOD 0x00030000 /* 0 = 16bit, 1=20 bit */ 289 #define M1575_SCR_6CHL_MASK 0x0000c000 /* FL, FR, C, BL, BR, LFE */ 290 #define M1575_SCR_6CHL_0 0x00000000 /* channel ordering */ 291 #define M1575_SCR_6CHL_1 0x00004000 /* FL, C, FR, BL, BR, LFE */ 292 #define M1575_SCR_6CHL_2 0x00008000 /* FL, FR, C, LFE, BL, BR */ 293 #define M1575_SCR_6CHL_3 0x0000c000 /* FL, C, FR, LFE, BL, BR */ 294 #define M1575_SCR_CHAMOD_MASK 0x00000300 /* 2, 4, or 6 channel */ 295 #define M1575_SCR_CHAMOD_2 0x00000000 /* 2 channel */ 296 #define M1575_SCR_CHAMOD_4 0x00000100 /* 4 channel surround */ 297 #define M1575_SCR_CHAMOD_6 0x00000200 /* 6 channel (5.1) surround */ 298 #define M1575_SCR_DRENT 0x40000000 299 #define M1575_SCR_MSTRST 0x80000000 300 301 /* Bits in System Status Register */ 302 #define M1575_SSR_RSTBLK 0x00000002 303 #define M1575_SSR_FACCS_MSK 0x00000018 304 #define M1575_SSR_SCID 0x00000040 305 306 /* Bits in Command Port Register */ 307 #define M1575_CPR_ACSCS 0x0100 /* Audio Codec for cmd 1=codec 2 */ 308 #define M1575_CPR_READ 0x0080 309 310 /* Bits in Cmd Status Port Register */ 311 #define M1575_CSPSR_SUCC 0x08 /* cmd successful */ 312 #define M1575_CSPSR_RDRDY 0x02 /* ready for read cmd */ 313 #define M1575_CSPSR_WRRDY 0x01 /* ready for write cmd */ 314 #define M1575_PCMI2CR_RR 0x02 /* Reset */ 315 #define M1575_MICI2CR_RR 0x02 /* Reset */ 316 #define M1575_CSPOCR_RR 0x02 /* Reset */ 317 318 /* Bits in Interface Control Register */ 319 #define M1575_INTFCR_RSTREL 0x02000000 320 #define M1575_INTFCR_RSTBLK 0x00200000 321 #define M1575_INTFCR_MICENB 0x00100000 322 #define M1575_INTFCR_PCMIENB 0x00080000 323 #define M1575_INTFCR_MICI2ENB 0x00040000 324 #define M1575_INTFCR_PCMI2ENB 0x00020000 325 #define M1575_INTFCR_MICI2SEL 0x00008000 326 #define M1575_INTFCR_MICISEL 0x00004000 327 #define M1575_INTFCR_PCMOENB 0x00000002 328 329 #define M1575_INTRCR_CPRINTR 0x00000080 330 #define M1575_INTRCR_SPRINTR 0x00000020 331 #define M1575_INTRCR_GPIOINTR 0x00000002 332 333 /* Bits of Recv Tag Slot Register */ 334 #define M1575_RTSR_SACRDY 0x20u /* 2nd Audio Codec Rdy */ 335 #define M1575_RTSR_FACRDY 0x80u /* 1st Audio Codec Rdy */ 336 337 /* Semaphore busy */ 338 #define M1575_CASR_SEMBSY 0x80000000 339 340 /* 341 * buffer descripter list entry, see M1575 datasheet 342 */ 343 #define IOC 0x8000 344 #define BUP 0x4000 345 346 struct m1575_bd_entry { 347 uint32_t buf_base; /* the address of the buffer */ 348 uint16_t buf_len; /* the number of samples */ 349 uint16_t buf_cmd; 350 }; 351 typedef struct m1575_bd_entry m1575_bd_entry_t; 352 353 struct audio1575_port { 354 struct audio1575_state *statep; 355 ddi_dma_handle_t samp_dmah; 356 ddi_acc_handle_t samp_acch; 357 size_t samp_size; 358 caddr_t samp_kaddr; 359 uint32_t samp_paddr; 360 361 ddi_dma_handle_t bdl_dmah; 362 ddi_acc_handle_t bdl_acch; 363 size_t bdl_size; 364 caddr_t bdl_kaddr; 365 uint32_t bdl_paddr; 366 367 int num; 368 unsigned intrs; 369 unsigned fragfr; 370 uint64_t count; 371 uint8_t nchan; 372 373 uint8_t civ; 374 uint16_t picb; 375 unsigned sync_dir; 376 377 boolean_t started; 378 379 audio_engine_t *engine; 380 }; 381 typedef struct audio1575_port audio1575_port_t; 382 383 384 /* 385 * audio1575_state_t per instance state and operation data 386 */ 387 struct audio1575_state { 388 kmutex_t lock; /* intr mutex */ 389 kmutex_t ac_lock; /* ac'97 mutex */ 390 dev_info_t *dip; /* dev instance ptr */ 391 audio_dev_t *adev; /* audio handle */ 392 ac97_t *ac97; /* ac'97 handle */ 393 audio1575_port_t *ports[2]; /* DMA engines */ 394 395 ddi_intr_handle_t ih; /* intr handle */ 396 397 ddi_acc_handle_t pcih; /* pci config space */ 398 399 ddi_acc_handle_t regsh; /* audio i/o regs */ 400 caddr_t regsp; /* base of i/o regs */ 401 402 kstat_t *ksp; /* kernel statistics */ 403 404 boolean_t suspended; /* if DDI_SUSPENDed */ 405 uint8_t maxch; /* maximum channels */ 406 }; 407 typedef struct audio1575_state audio1575_state_t; 408 409 /* audio i/o register macros */ 410 #define GET8(reg) \ 411 ddi_get8(statep->regsh, (void *)(statep->regsp + (reg))) 412 413 #define GET16(reg) \ 414 ddi_get16(statep->regsh, (void *)(statep->regsp + (reg))) 415 416 #define GET32(reg) \ 417 ddi_get32(statep->regsh, (void *)(statep->regsp + (reg))) 418 419 #define PUT8(reg, val) \ 420 ddi_put8(statep->regsh, (void *)(statep->regsp + (reg)), (val)) 421 422 #define PUT16(reg, val) \ 423 ddi_put16(statep->regsh, (void *)(statep->regsp + (reg)), (val)) 424 425 #define PUT32(reg, val) \ 426 ddi_put32(statep->regsh, (void *)(statep->regsp + (reg)), (val)) 427 428 #define SET8(reg, bit) PUT8(reg, GET8(reg) | (bit)) 429 #define SET16(reg, bit) PUT16(reg, GET16(reg) | (bit)) 430 #define SET32(reg, bit) PUT32(reg, GET32(reg) | (bit)) 431 #define CLR8(reg, bit) PUT8(reg, GET8(reg) & ~(bit)) 432 #define CLR16(reg, bit) PUT16(reg, GET16(reg) & ~(bit)) 433 #define CLR32(reg, bit) PUT32(reg, GET32(reg) & ~(bit)) 434 435 436 #endif /* AUDIO1575_H */ 437