1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 27 /* 28 * audio1575 Audio Driver 29 * 30 * The driver is primarily targeted at providing audio support for 31 * those systems which use the Uli M1575 audio core. 32 * 33 * The M1575 audio core, in AC'97 controller mode, has independent 34 * channels for PCM in, PCM out, mic in, modem in, and modem out. 35 * 36 * The AC'97 controller is a PCI bus master with scatter/gather 37 * support. Each channel has a DMA engine. Currently, we use only 38 * the PCM in and PCM out channels. Each DMA engine uses one buffer 39 * descriptor list. And the buffer descriptor list is an array of up 40 * to 32 entries, each of which describes a data buffer. Each entry 41 * contains a pointer to a data buffer, control bits, and the length 42 * of the buffer being pointed to, where the length is expressed as 43 * the number of samples. This, combined with the 16-bit sample size, 44 * gives the actual physical length of the buffer. 45 * 46 * TODO: System power management is not yet supported by the driver. 47 * 48 * NOTE: 49 * This driver depends on the drv/audio, misc/ac97 50 * modules being loaded first. 51 */ 52 53 #include <sys/types.h> 54 #include <sys/modctl.h> 55 #include <sys/kmem.h> 56 #include <sys/conf.h> 57 #include <sys/ddi.h> 58 #include <sys/sunddi.h> 59 #include <sys/pci.h> 60 #include <sys/note.h> 61 #include <sys/audio/audio_driver.h> 62 #include <sys/audio/ac97.h> 63 #include "audio1575.h" 64 65 /* 66 * Module linkage routines for the kernel 67 */ 68 static int audio1575_ddi_attach(dev_info_t *, ddi_attach_cmd_t); 69 static int audio1575_ddi_detach(dev_info_t *, ddi_detach_cmd_t); 70 71 /* 72 * Entry point routine prototypes 73 */ 74 static int audio1575_open(void *, int, unsigned *, unsigned *, caddr_t *); 75 static void audio1575_close(void *); 76 static int audio1575_start(void *); 77 static void audio1575_stop(void *); 78 static int audio1575_format(void *); 79 static int audio1575_channels(void *); 80 static int audio1575_rate(void *); 81 static uint64_t audio1575_count(void *); 82 static void audio1575_sync(void *, unsigned); 83 static size_t audio1575_qlen(void *); 84 85 static audio_engine_ops_t audio1575_engine_ops = { 86 AUDIO_ENGINE_VERSION, 87 audio1575_open, 88 audio1575_close, 89 audio1575_start, 90 audio1575_stop, 91 audio1575_count, 92 audio1575_format, 93 audio1575_channels, 94 audio1575_rate, 95 audio1575_sync, 96 audio1575_qlen 97 }; 98 99 /* 100 * interrupt handler 101 */ 102 static uint_t audio1575_intr(caddr_t, caddr_t); 103 104 /* 105 * Local Routine Prototypes 106 */ 107 static int audio1575_attach(dev_info_t *); 108 static int audio1575_resume(dev_info_t *); 109 static int audio1575_detach(dev_info_t *); 110 static int audio1575_suspend(dev_info_t *); 111 112 static int audio1575_alloc_port(audio1575_state_t *, int); 113 static void audio1575_free_port(audio1575_port_t *); 114 static void audio1575_start_port(audio1575_port_t *); 115 static void audio1575_stop_port(audio1575_port_t *); 116 static void audio1575_reset_port(audio1575_port_t *); 117 static void audio1575_update_port(audio1575_port_t *); 118 119 static int audio1575_setup_intr(audio1575_state_t *); 120 static int audio1575_codec_sync(audio1575_state_t *); 121 static void audio1575_write_ac97(void *, uint8_t, uint16_t); 122 static uint16_t audio1575_read_ac97(void *, uint8_t); 123 static int audio1575_chip_init(audio1575_state_t *); 124 static int audio1575_map_regs(audio1575_state_t *); 125 static void audio1575_unmap_regs(audio1575_state_t *); 126 static void audio1575_dma_stop(audio1575_state_t *); 127 static void audio1575_pci_enable(audio1575_state_t *); 128 static void audio1575_pci_disable(audio1575_state_t *); 129 130 static void audio1575_destroy(audio1575_state_t *); 131 132 /* 133 * Global variables, but used only by this file. 134 */ 135 136 /* 137 * DDI Structures 138 */ 139 140 141 /* Device operations structure */ 142 static struct dev_ops audio1575_dev_ops = { 143 DEVO_REV, /* devo_rev */ 144 0, /* devo_refcnt */ 145 NULL, /* devo_getinfo */ 146 nulldev, /* devo_identify - obsolete */ 147 nulldev, /* devo_probe */ 148 audio1575_ddi_attach, /* devo_attach */ 149 audio1575_ddi_detach, /* devo_detach */ 150 nodev, /* devo_reset */ 151 NULL, /* devi_cb_ops */ 152 NULL, /* devo_bus_ops */ 153 NULL, /* devo_power */ 154 ddi_quiesce_not_supported, /* devo_quiesce */ 155 }; 156 157 /* Linkage structure for loadable drivers */ 158 static struct modldrv audio1575_modldrv = { 159 &mod_driverops, /* drv_modops */ 160 M1575_MOD_NAME, /* drv_linkinfo */ 161 &audio1575_dev_ops, /* drv_dev_ops */ 162 }; 163 164 /* Module linkage structure */ 165 static struct modlinkage audio1575_modlinkage = { 166 MODREV_1, /* ml_rev */ 167 (void *)&audio1575_modldrv, /* ml_linkage */ 168 NULL /* NULL terminates the list */ 169 }; 170 171 172 /* 173 * device access attributes for register mapping 174 */ 175 static struct ddi_device_acc_attr dev_attr = { 176 DDI_DEVICE_ATTR_V0, 177 DDI_STRUCTURE_LE_ACC, 178 DDI_STRICTORDER_ACC 179 }; 180 181 static struct ddi_device_acc_attr buf_attr = { 182 DDI_DEVICE_ATTR_V0, 183 DDI_NEVERSWAP_ACC, 184 DDI_STRICTORDER_ACC 185 }; 186 187 /* 188 * DMA attributes of buffer descriptor list 189 */ 190 static ddi_dma_attr_t bdlist_dma_attr = { 191 DMA_ATTR_V0, /* version */ 192 0x0000000000000000LL, /* dlim_addr_lo */ 193 0x00000000ffffffffLL, /* dlim_addr_hi */ 194 0x000000000000ffffLL, /* DMA counter register - 64 bits */ 195 0x0000000000000008LL, /* DMA address align must be 8-bytes */ 196 0x0000003c, /* 1 through 64 byte burst sizes */ 197 0x00000008, /* min xfer DMA size BDList entry */ 198 0x00000000000ffffLL, /* max xfer size, 64K */ 199 0x000000000001fffLL, /* seg, set to PAGESIZE */ 200 0x00000001, /* s/g list length, no s/g */ 201 0x00000008, /* granularity of device minxfer */ 202 0 /* DMA flags use virtual address */ 203 }; 204 205 /* 206 * DMA attributes of buffers to be used to receive/send audio data 207 */ 208 static ddi_dma_attr_t sample_buf_dma_attr = { 209 DMA_ATTR_V0, 210 0x0000000000000000LL, /* dlim_addr_lo */ 211 0x00000000ffffffffLL, /* dlim_addr_hi */ 212 0x000000000001fffeLL, /* DMA counter register - 16 bits */ 213 0x0000000000000004LL, /* DMA address align 2-byte boundary */ 214 0x0000003c, /* 1 through 60 byte burst sizes */ 215 0x00000004, /* min xfer DMA size BDList entry */ 216 0x000000000001ffffLL, /* max xfer size, 64K */ 217 0x000000000001ffffLL, /* seg, set to 64K */ 218 0x00000001, /* s/g list length, no s/g */ 219 0x00000004, /* granularity of device minxfer */ 220 0 /* DMA flags use virtual address */ 221 }; 222 223 /* 224 * _init() 225 * 226 * Description: 227 * Driver initialization, called when driver is first loaded. 228 * This is how access is initially given to all the static structures. 229 * 230 * Arguments: 231 * None 232 * 233 * Returns: 234 * mod_install() status, see mod_install(9f) 235 */ 236 int 237 _init(void) 238 { 239 int error; 240 241 audio_init_ops(&audio1575_dev_ops, M1575_NAME); 242 243 if ((error = mod_install(&audio1575_modlinkage)) != 0) { 244 audio_fini_ops(&audio1575_dev_ops); 245 } 246 247 return (error); 248 } 249 250 /* 251 * _fini() 252 * 253 * Description: 254 * Module de-initialization, called when the driver is to be unloaded. 255 * 256 * Arguments: 257 * None 258 * 259 * Returns: 260 * mod_remove() status, see mod_remove(9f) 261 */ 262 int 263 _fini(void) 264 { 265 int error; 266 267 if ((error = mod_remove(&audio1575_modlinkage)) != 0) { 268 return (error); 269 } 270 271 /* clean up ops */ 272 audio_fini_ops(&audio1575_dev_ops); 273 274 return (0); 275 } 276 277 /* 278 * _info() 279 * 280 * Description: 281 * Module information, returns information about the driver. 282 * 283 * Arguments: 284 * modinfo *modinfop Pointer to the opaque modinfo structure 285 * 286 * Returns: 287 * mod_info() status, see mod_info(9f) 288 */ 289 int 290 _info(struct modinfo *modinfop) 291 { 292 return (mod_info(&audio1575_modlinkage, modinfop)); 293 } 294 295 296 /* ******************* Driver Entry Points ********************************* */ 297 298 /* 299 * audio1575_ddi_attach() 300 * 301 * Description: 302 * Implements the DDI attach(9e) entry point. 303 * 304 * Arguments: 305 * dev_info_t *dip Pointer to the device's dev_info struct 306 * ddi_attach_cmd_t cmd Attach command 307 * 308 * Returns: 309 * DDI_SUCCESS The driver was initialized properly 310 * DDI_FAILURE The driver couldn't be initialized properly 311 */ 312 static int 313 audio1575_ddi_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 314 { 315 switch (cmd) { 316 case DDI_ATTACH: 317 return (audio1575_attach(dip)); 318 319 case DDI_RESUME: 320 return (audio1575_resume(dip)); 321 } 322 return (DDI_FAILURE); 323 } 324 325 /* 326 * audio1575_ddi_detach() 327 * 328 * Description: 329 * Implements the detach(9e) entry point. 330 * 331 * Arguments: 332 * dev_info_t *dip Pointer to the device's dev_info struct 333 * ddi_detach_cmd_t cmd Detach command 334 * 335 * Returns: 336 * DDI_SUCCESS The driver was detached 337 * DDI_FAILURE The driver couldn't be detached 338 */ 339 static int 340 audio1575_ddi_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 341 { 342 switch (cmd) { 343 case DDI_DETACH: 344 return (audio1575_detach(dip)); 345 346 case DDI_SUSPEND: 347 return (audio1575_suspend(dip)); 348 } 349 return (DDI_FAILURE); 350 } 351 352 /* 353 * audio1575_intr() 354 * 355 * Description: 356 * Interrupt service routine for both play and record. For play we 357 * get the next buffers worth of audio. For record we send it on to 358 * the mixer. 359 * 360 * Each of buffer descriptor has a field IOC(interrupt on completion) 361 * When both this and the IOC bit of correspondent dma control register 362 * is set, it means that the controller should issue an interrupt upon 363 * completion of this buffer. Note that in the clearing of the interrupts 364 * below that the PCM IN and PCM out interrupts ar cleared by their 365 * respective control registers and not by writing a '1' to the INTRSR 366 * the interrupt status register. Only CPRINTR,SPINTR,and GPIOINTR 367 * require a '1' written to the INTRSR register to clear those 368 * interrupts. See comments below. 369 * 370 * Arguments: 371 * caddr_t arg Pointer to the interrupting device's state 372 * structure 373 * 374 * Returns: 375 * DDI_INTR_CLAIMED Interrupt claimed and processed 376 * DDI_INTR_UNCLAIMED Interrupt not claimed, and thus ignored 377 */ 378 static uint_t 379 audio1575_intr(caddr_t arg, caddr_t dontcare) 380 { 381 audio1575_state_t *statep = (void *)arg; 382 uint32_t intrsr; 383 uint8_t index; 384 audio1575_port_t *consume = NULL; 385 audio1575_port_t *produce = NULL; 386 387 _NOTE(ARGUNUSED(dontcare)); 388 389 mutex_enter(&statep->lock); 390 391 intrsr = GET32(M1575_INTRSR_REG); 392 393 /* check if device is interrupting */ 394 if (intrsr == 0) { 395 if (statep->ksp) { 396 /* increment the spurious ino5 interrupt cnt */ 397 M1575_KIOP(statep)->intrs[KSTAT_INTR_SPURIOUS]++; 398 } 399 400 mutex_exit(&statep->lock); 401 return (DDI_INTR_UNCLAIMED); 402 } 403 404 /* update the kernel interrupt statistics */ 405 if (statep->ksp) { 406 M1575_KIOP(statep)->intrs[KSTAT_INTR_HARD]++; 407 } 408 409 /* 410 * The Uli M1575 generates an interrupt for each interrupt 411 * type. therefore we only process one interrupt type 412 * per invocation of the audio1575_intr() routine. 413 * WARNING: DO NOT attempt to optimize this by looping 414 * until the INTRSR register is clear as this will 415 * generate spurious ino5 interrupts. 416 */ 417 if (GET16(M1575_PCMISR_REG) & M1575_PCMISR_BCIS) { 418 /* Clear PCM IN interrupt */ 419 PUT16(M1575_PCMISR_REG, M1575_SR_CLR); 420 /* 421 * Note: This interrupt is not cleared by writing a '1' 422 * to the M1575_INTRSR_REG according to the M1575 Super I/O 423 * data sheet on page 189. 424 */ 425 426 /* update the LVI -- we just set it to the current value - 1 */ 427 index = GET8(M1575_PCMICIV_REG); 428 index = (index - 1) % M1575_BD_NUMS; 429 PUT8(M1575_PCMILVIV_REG, index); 430 produce = statep->ports[M1575_REC]; 431 432 } else if (GET16(M1575_PCMOSR_REG) & M1575_PCMOSR_BCIS) { 433 /* Clear PCM OUT interrupt */ 434 PUT16(M1575_PCMOSR_REG, M1575_SR_CLR); 435 /* 436 * Note: This interrupt is not cleared by writing a '1' 437 * to the M1575_INTRSR_REG according to the M1575 Super I/O 438 * data sheet on page 189. 439 */ 440 441 /* update the LVI -- we just set it to the current value - 1 */ 442 index = GET8(M1575_PCMOCIV_REG); 443 index = (index - 1) % M1575_BD_NUMS; 444 PUT8(M1575_PCMOLVIV_REG, index); 445 consume = statep->ports[M1575_PLAY]; 446 447 } else { 448 /* Clear other interrupts (there should not be any) */ 449 PUT32(M1575_INTRSR_REG, (intrsr & M1575_INTR_MASK)); 450 } 451 452 mutex_exit(&statep->lock); 453 454 if (produce) { 455 audio_engine_produce(produce->engine); 456 } 457 if (consume) { 458 audio_engine_consume(consume->engine); 459 } 460 461 return (DDI_INTR_CLAIMED); 462 } 463 464 /* 465 * audio1575_open() 466 * 467 * Description: 468 * Opens a DMA engine for use. 469 * 470 * Arguments: 471 * void *arg The DMA engine to set up 472 * int flag Open flags 473 * unsigned *fragfrp Receives number of frames per fragment 474 * unsigned *nfragsp Receives number of fragments 475 * caddr_t *bufp Receives kernel data buffer 476 * 477 * Returns: 478 * 0 on success 479 * errno on failure 480 */ 481 static int 482 audio1575_open(void *arg, int flag, 483 unsigned *fragfrp, unsigned *nfragsp, caddr_t *bufp) 484 { 485 audio1575_port_t *port = arg; 486 487 _NOTE(ARGUNUSED(flag)); 488 489 port->started = B_FALSE; 490 port->count = 0; 491 *fragfrp = port->fragfr; 492 *nfragsp = M1575_BD_NUMS; 493 *bufp = port->samp_kaddr; 494 495 mutex_enter(&port->statep->lock); 496 audio1575_reset_port(port); 497 mutex_exit(&port->statep->lock); 498 499 return (0); 500 } 501 502 503 /* 504 * audio1575_close() 505 * 506 * Description: 507 * Closes an audio DMA engine that was previously opened. Since 508 * nobody is using it, we take this opportunity to possibly power 509 * down the entire device. 510 * 511 * Arguments: 512 * void *arg The DMA engine to shut down 513 */ 514 static void 515 audio1575_close(void *arg) 516 { 517 audio1575_port_t *port = arg; 518 audio1575_state_t *statep = port->statep; 519 520 mutex_enter(&statep->lock); 521 audio1575_stop_port(port); 522 port->started = B_FALSE; 523 mutex_exit(&statep->lock); 524 } 525 526 /* 527 * audio1575_stop() 528 * 529 * Description: 530 * This is called by the framework to stop a port that is 531 * transferring data. 532 * 533 * Arguments: 534 * void *arg The DMA engine to stop 535 */ 536 static void 537 audio1575_stop(void *arg) 538 { 539 audio1575_port_t *port = arg; 540 audio1575_state_t *statep = port->statep; 541 542 mutex_enter(&statep->lock); 543 if (port->started) { 544 audio1575_stop_port(port); 545 } 546 port->started = B_FALSE; 547 mutex_exit(&statep->lock); 548 } 549 550 /* 551 * audio1575_start() 552 * 553 * Description: 554 * This is called by the framework to start a port transferring data. 555 * 556 * Arguments: 557 * void *arg The DMA engine to start 558 * 559 * Returns: 560 * 0 on success (never fails, errno if it did) 561 */ 562 static int 563 audio1575_start(void *arg) 564 { 565 audio1575_port_t *port = arg; 566 audio1575_state_t *statep = port->statep; 567 568 mutex_enter(&statep->lock); 569 if (!port->started) { 570 audio1575_start_port(port); 571 port->started = B_TRUE; 572 } 573 mutex_exit(&statep->lock); 574 return (0); 575 } 576 577 /* 578 * audio1575_format() 579 * 580 * Description: 581 * Called by the framework to query the format for the device. 582 * 583 * Arguments: 584 * void *arg The DMA engine to query 585 * 586 * Returns: 587 * AUDIO_FORMAT_S16_LE 588 */ 589 static int 590 audio1575_format(void *arg) 591 { 592 _NOTE(ARGUNUSED(arg)); 593 594 return (AUDIO_FORMAT_S16_LE); 595 } 596 597 /* 598 * audio1575_channels() 599 * 600 * Description: 601 * Called by the framework to query the channels for the device. 602 * 603 * Arguments: 604 * void *arg The DMA engine to query 605 * 606 * Returns: 607 * Number of channels for the device 608 */ 609 static int 610 audio1575_channels(void *arg) 611 { 612 audio1575_port_t *port = arg; 613 614 return (port->nchan); 615 } 616 617 /* 618 * audio1575_rate() 619 * 620 * Description: 621 * Called by the framework to query the sample rate for the device. 622 * 623 * Arguments: 624 * void *arg The DMA engine to query 625 * 626 * Returns: 627 * 48000 628 */ 629 static int 630 audio1575_rate(void *arg) 631 { 632 _NOTE(ARGUNUSED(arg)); 633 634 return (48000); 635 } 636 637 /* 638 * audio1575_count() 639 * 640 * Description: 641 * This is called by the framework to get the engine's frame counter 642 * 643 * Arguments: 644 * void *arg The DMA engine to query 645 * 646 * Returns: 647 * frame count for current engine 648 */ 649 static uint64_t 650 audio1575_count(void *arg) 651 { 652 audio1575_port_t *port = arg; 653 audio1575_state_t *statep = port->statep; 654 uint64_t val; 655 656 mutex_enter(&statep->lock); 657 audio1575_update_port(port); 658 val = port->count + port->picb; 659 mutex_exit(&statep->lock); 660 661 return (val); 662 } 663 664 /* 665 * audio1575_sync() 666 * 667 * Description: 668 * This is called by the framework to synchronize DMA caches. 669 * 670 * Arguments: 671 * void *arg The DMA engine to sync 672 */ 673 static void 674 audio1575_sync(void *arg, unsigned nframes) 675 { 676 audio1575_port_t *port = arg; 677 _NOTE(ARGUNUSED(nframes)); 678 679 (void) ddi_dma_sync(port->samp_dmah, 0, 0, port->sync_dir); 680 } 681 682 /* 683 * audio1575_qlen() 684 * 685 * Description: 686 * This is called by the framework to determine on-device queue length. 687 * 688 * Arguments: 689 * void *arg The DMA engine to query 690 * 691 * Returns: 692 * hardware queue length not reported by count (0 for this device) 693 */ 694 static size_t 695 audio1575_qlen(void *arg) 696 { 697 _NOTE(ARGUNUSED(arg)); 698 return (0); 699 } 700 701 702 /* 703 * audio1575_start_port() 704 * 705 * Description: 706 * This routine starts the DMA engine. 707 * 708 * Arguments: 709 * audio1575_port_t *port Port of DMA engine to start. 710 */ 711 static void 712 audio1575_start_port(audio1575_port_t *port) 713 { 714 audio1575_state_t *statep = port->statep; 715 716 ASSERT(mutex_owned(&statep->lock)); 717 718 /* if suspended, then do nothing else */ 719 if (statep->suspended) { 720 return; 721 } 722 723 if (port->num == M1575_REC) { 724 /* ULi says do fifo resets here */ 725 SET32(M1575_FIFOCR1_REG, M1575_FIFOCR1_PCMIRST); 726 CLR32(M1575_DMACR_REG, M1575_DMACR_PCMIPAUSE); 727 PUT8(M1575_PCMICR_REG, M1575_PCMICR_IOCE); 728 SET32(M1575_DMACR_REG, M1575_DMACR_PCMISTART); 729 } else { 730 CLR32(M1575_DMACR_REG, M1575_DMACR_PCMOPAUSE); 731 PUT8(M1575_PCMOCR_REG, M1575_PCMOCR_IOCE); 732 SET32(M1575_DMACR_REG, M1575_DMACR_PCMOSTART); 733 } 734 } 735 736 /* 737 * audio1575_stop_port() 738 * 739 * Description: 740 * This routine stops the DMA engine. 741 * 742 * Arguments: 743 * audio1575_port_t *port Port of DMA engine to stop. 744 */ 745 static void 746 audio1575_stop_port(audio1575_port_t *port) 747 { 748 audio1575_state_t *statep = port->statep; 749 750 ASSERT(mutex_owned(&statep->lock)); 751 752 /* if suspended, then do nothing else */ 753 if (statep->suspended) { 754 return; 755 } 756 757 if (port->num == M1575_REC) { 758 SET32(M1575_DMACR_REG, M1575_DMACR_PCMIPAUSE); 759 } else { 760 SET32(M1575_DMACR_REG, M1575_DMACR_PCMOPAUSE); 761 } 762 } 763 764 /* 765 * audio1575_reset_port() 766 * 767 * Description: 768 * This routine resets the DMA engine pareparing it for work. 769 * 770 * Arguments: 771 * audio1575_port_t *port Port of DMA engine to reset. 772 */ 773 static void 774 audio1575_reset_port(audio1575_port_t *port) 775 { 776 audio1575_state_t *statep = port->statep; 777 778 ASSERT(mutex_owned(&statep->lock)); 779 780 port->civ = 0; 781 port->picb = 0; 782 783 if (statep->suspended) 784 return; 785 786 if (port->num == M1575_REC) { 787 /* Uli FIFO madness ... */ 788 SET32(M1575_FIFOCR1_REG, M1575_FIFOCR1_PCMIRST); 789 SET32(M1575_DMACR_REG, M1575_DMACR_PCMIPAUSE); 790 791 PUT8(M1575_PCMICR_REG, 0); 792 PUT8(M1575_PCMICR_REG, M1575_CR_RR | M1575_CR_IOCE); 793 794 PUT32(M1575_PCMIBDBAR_REG, port->bdl_paddr); 795 PUT8(M1575_PCMILVIV_REG, M1575_BD_NUMS - 1); 796 797 CLR32(M1575_DMACR_REG, M1575_DMACR_PCMIPAUSE); 798 799 } else { 800 801 /* Uli FIFO madness ... */ 802 SET32(M1575_FIFOCR1_REG, M1575_FIFOCR1_PCMORST); 803 SET32(M1575_DMACR_REG, M1575_DMACR_PCMOPAUSE); 804 805 PUT8(M1575_PCMOCR_REG, 0); 806 PUT8(M1575_PCMOCR_REG, M1575_CR_RR | M1575_CR_IOCE); 807 808 PUT32(M1575_PCMOBDBAR_REG, port->bdl_paddr); 809 PUT8(M1575_PCMOLVIV_REG, M1575_BD_NUMS - 1); 810 811 CLR32(M1575_DMACR_REG, M1575_DMACR_PCMOPAUSE); 812 } 813 } 814 815 /* 816 * audio1575_update_port() 817 * 818 * Description: 819 * This routine updates the ports frame counter from hardware, and 820 * gracefully handles wraps. 821 * 822 * Arguments: 823 * audio1575_port_t *port The port to update. 824 */ 825 static void 826 audio1575_update_port(audio1575_port_t *port) 827 { 828 audio1575_state_t *statep = port->statep; 829 uint8_t civ; 830 uint16_t picb; 831 unsigned n; 832 int civoff; 833 int picoff; 834 835 if (port->num == M1575_REC) { 836 civoff = M1575_PCMICIV_REG; 837 picoff = M1575_PCMIPICB_REG; 838 } else { 839 civoff = M1575_PCMOCIV_REG; 840 picoff = M1575_PCMOPICB_REG; 841 } 842 843 if (statep->suspended) { 844 civ = 0; 845 picb = 0; 846 } else { 847 /* 848 * We read the position counters, but we're careful to avoid 849 * the situation where the position counter resets at the end 850 * of a buffer. 851 */ 852 for (int i = 0; i < 2; i++) { 853 civ = GET8(civoff); 854 picb = GET16(picoff); 855 if (GET8(civoff) == civ) { 856 /* 857 * Chip did not start a new index, so 858 * the picb is valid. 859 */ 860 break; 861 } 862 } 863 if (civ >= port->civ) { 864 n = civ - port->civ; 865 } else { 866 n = civ + (M1575_BD_NUMS - port->civ); 867 } 868 port->count += (n * port->fragfr); 869 } 870 port->civ = civ; 871 port->picb = picb; 872 } 873 874 /* 875 * audio1575_attach() 876 * 877 * Description: 878 * Attach an instance of the audio1575 driver. This routine does the 879 * device dependent attach tasks. When it is completed, it registers 880 * with the audio framework. 881 * 882 * Arguments: 883 * dev_info_t *dip Pointer to the device's dev_info struct 884 * 885 * Returns: 886 * DDI_SUCCESS The driver was initialized properly 887 * DDI_FAILURE The driver couldn't be initialized properly 888 */ 889 static int 890 audio1575_attach(dev_info_t *dip) 891 { 892 audio1575_state_t *statep; 893 audio_dev_t *adev; 894 uint32_t devid; 895 const char *name; 896 const char *rev; 897 898 /* allocate the soft state structure */ 899 statep = kmem_zalloc(sizeof (*statep), KM_SLEEP); 900 ddi_set_driver_private(dip, statep); 901 statep->dip = dip; 902 903 /* 904 * We want the micboost enabled by default as well. 905 */ 906 ddi_prop_update_int(DDI_DEV_T_NONE, dip, AC97_PROP_MICBOOST, 1); 907 908 /* allocate common audio dev structure */ 909 adev = audio_dev_alloc(dip, 0); 910 if (adev == NULL) { 911 audio_dev_warn(NULL, "unable to allocate audio dev"); 912 goto error; 913 } 914 statep->adev = adev; 915 916 /* map in the audio registers */ 917 if (audio1575_map_regs(statep) != DDI_SUCCESS) { 918 audio_dev_warn(adev, "couldn't map registers"); 919 goto error; 920 } 921 922 if (audio1575_setup_intr(statep) != DDI_SUCCESS) { 923 /* message already noted */ 924 goto error; 925 } 926 927 /* Enable PCI I/O and Memory Spaces */ 928 audio1575_pci_enable(statep); 929 930 devid = (pci_config_get16(statep->pcih, PCI_CONF_VENID) << 16) | 931 pci_config_get16(statep->pcih, PCI_CONF_DEVID); 932 switch (devid) { 933 case 0x10b95455: 934 name = "Uli M1575 AC'97"; 935 rev = "M5455"; 936 break; 937 default: 938 name = "Uli AC'97"; 939 rev = "Unknown"; 940 break; 941 } 942 /* set device information -- this should check PCI config space */ 943 audio_dev_set_description(adev, name); 944 audio_dev_set_version(adev, rev); 945 946 947 /* allocate port structures */ 948 if ((audio1575_alloc_port(statep, M1575_PLAY) != DDI_SUCCESS) || 949 (audio1575_alloc_port(statep, M1575_REC) != DDI_SUCCESS)) { 950 goto error; 951 } 952 953 statep->ac97 = ac97_alloc(dip, audio1575_read_ac97, 954 audio1575_write_ac97, statep); 955 ASSERT(statep->ac97 != NULL); 956 957 if (audio1575_chip_init(statep) != DDI_SUCCESS) { 958 audio_dev_warn(adev, "failed to init chip"); 959 goto error; 960 } 961 962 if (ac97_init(statep->ac97, adev) != DDI_SUCCESS) { 963 audio_dev_warn(adev, "ac'97 initialization failed"); 964 goto error; 965 } 966 967 /* set up kernel statistics */ 968 if ((statep->ksp = kstat_create(M1575_NAME, 969 ddi_get_instance(dip), M1575_NAME, "controller", 970 KSTAT_TYPE_INTR, 1, KSTAT_FLAG_PERSISTENT)) != NULL) { 971 kstat_install(statep->ksp); 972 } 973 974 /* Enable PCI Interrupts */ 975 pci_config_put8(statep->pcih, M1575_PCIMISC_REG, M1575_PCIMISC_INTENB); 976 977 /* enable audio interrupts */ 978 if (ddi_intr_enable(statep->ih) != DDI_SUCCESS) { 979 audio_dev_warn(adev, "ddi_intr_enable() failure"); 980 goto error; 981 } 982 983 /* register with the framework */ 984 if (audio_dev_register(adev) != DDI_SUCCESS) { 985 audio_dev_warn(adev, "unable to register with framework"); 986 goto error; 987 } 988 989 /* everything worked out, so report the device */ 990 ddi_report_dev(dip); 991 992 return (DDI_SUCCESS); 993 994 error: 995 audio1575_destroy(statep); 996 return (DDI_FAILURE); 997 } 998 999 /* 1000 * audio1575_detach() 1001 * 1002 * Description: 1003 * Detach an instance of the audio1575 driver. 1004 * 1005 * Arguments: 1006 * dev_info_t *dip Pointer to the device's dev_info struct 1007 * 1008 * Returns: 1009 * DDI_SUCCESS The driver was detached 1010 * DDI_FAILURE The driver couldn't be detached 1011 */ 1012 static int 1013 audio1575_detach(dev_info_t *dip) 1014 { 1015 audio1575_state_t *statep; 1016 1017 statep = ddi_get_driver_private(dip); 1018 1019 if (audio_dev_unregister(statep->adev) != DDI_SUCCESS) { 1020 return (DDI_FAILURE); 1021 } 1022 1023 audio1575_destroy(statep); 1024 return (DDI_SUCCESS); 1025 } 1026 1027 /* *********************** Local Routines *************************** */ 1028 1029 /* 1030 * audio1575_setup_intr() 1031 * 1032 * Description: 1033 * This routine initializes the audio driver's interrupt handle and 1034 * mutex. 1035 * 1036 * Arguments: 1037 * audio1575_state_t *state The device's state structure 1038 * 1039 * Returns: 1040 * DDI_SUCCESS Interrupt handle & mutex initialized 1041 * DDI_FAILURE Interrupt handle & mutex not initialized 1042 */ 1043 int 1044 audio1575_setup_intr(audio1575_state_t *statep) 1045 { 1046 audio_dev_t *adev; 1047 dev_info_t *dip; 1048 uint_t ipri; 1049 int actual; 1050 int rv; 1051 int itype; 1052 int count; 1053 ddi_intr_handle_t ih = NULL; 1054 1055 dip = statep->dip; 1056 adev = statep->adev; 1057 1058 /* get supported interrupt types */ 1059 rv = ddi_intr_get_supported_types(dip, &itype); 1060 if ((rv != DDI_SUCCESS) || (!(itype & DDI_INTR_TYPE_FIXED))) { 1061 audio_dev_warn(adev, "Fixed type interrupts not supported"); 1062 return (DDI_FAILURE); 1063 } 1064 1065 /* make sure we only have one fixed type interrupt */ 1066 rv = ddi_intr_get_nintrs(dip, DDI_INTR_TYPE_FIXED, &count); 1067 if ((rv != DDI_SUCCESS) || (count != 1)) { 1068 audio_dev_warn(adev, "No fixed interrupts"); 1069 return (DDI_FAILURE); 1070 } 1071 1072 rv = ddi_intr_alloc(statep->dip, &ih, DDI_INTR_TYPE_FIXED, 1073 0, 1, &actual, DDI_INTR_ALLOC_STRICT); 1074 if ((rv != DDI_SUCCESS) || (actual != 1)) { 1075 audio_dev_warn(adev, "Can't alloc interrupt handle"); 1076 return (DDI_FAILURE); 1077 } 1078 1079 /* test for a high level interrupt */ 1080 if (ddi_intr_get_pri(ih, &ipri) != DDI_SUCCESS) { 1081 audio_dev_warn(adev, "Can't get interrupt priority"); 1082 (void) ddi_intr_free(ih); 1083 return (DDI_FAILURE); 1084 } 1085 if (ipri >= ddi_intr_get_hilevel_pri()) { 1086 audio_dev_warn(adev, "Unsupported high level interrupt"); 1087 (void) ddi_intr_free(ih); 1088 return (DDI_FAILURE); 1089 } 1090 1091 if (ddi_intr_add_handler(ih, audio1575_intr, statep, NULL) != 1092 DDI_SUCCESS) { 1093 audio_dev_warn(adev, "Can't add interrupt handler"); 1094 (void) ddi_intr_free(ih); 1095 return (DDI_FAILURE); 1096 } 1097 1098 statep->ih = ih; 1099 mutex_init(&statep->lock, NULL, MUTEX_DRIVER, DDI_INTR_PRI(ipri)); 1100 mutex_init(&statep->ac_lock, NULL, MUTEX_DRIVER, DDI_INTR_PRI(ipri)); 1101 1102 return (DDI_SUCCESS); 1103 } 1104 1105 /* 1106 * audio1575_alloc_port() 1107 * 1108 * Description: 1109 * This routine allocates the DMA handles and the memory for the 1110 * DMA engines to use. It also configures the BDL lists properly 1111 * for use. 1112 * 1113 * Arguments: 1114 * dev_info_t *dip Pointer to the device's devinfo 1115 * 1116 * Returns: 1117 * DDI_SUCCESS Registers successfully mapped 1118 * DDI_FAILURE Registers not successfully mapped 1119 */ 1120 static int 1121 audio1575_alloc_port(audio1575_state_t *statep, int num) 1122 { 1123 ddi_dma_cookie_t cookie; 1124 uint_t count; 1125 int dir; 1126 unsigned caps; 1127 char *prop; 1128 audio_dev_t *adev; 1129 audio1575_port_t *port; 1130 uint32_t *kaddr; 1131 uint32_t paddr; 1132 int rc; 1133 dev_info_t *dip; 1134 1135 adev = statep->adev; 1136 dip = statep->dip; 1137 1138 port = kmem_zalloc(sizeof (*port), KM_SLEEP); 1139 statep->ports[num] = port; 1140 port->num = num; 1141 port->statep = statep; 1142 port->started = B_FALSE; 1143 1144 if (num == M1575_REC) { 1145 prop = "record-interrupts"; 1146 dir = DDI_DMA_READ; 1147 caps = ENGINE_INPUT_CAP; 1148 port->sync_dir = DDI_DMA_SYNC_FORKERNEL; 1149 port->nchan = 2; 1150 } else { 1151 prop = "play-interrupts"; 1152 dir = DDI_DMA_WRITE; 1153 caps = ENGINE_OUTPUT_CAP; 1154 port->sync_dir = DDI_DMA_SYNC_FORDEV; 1155 /* XXX: possibly support multichannel! */ 1156 port->nchan = 2; 1157 } 1158 1159 port->intrs = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 1160 DDI_PROP_DONTPASS, prop, M1575_INTS); 1161 1162 /* make sure the values are good */ 1163 if (port->intrs < M1575_MIN_INTS) { 1164 audio_dev_warn(adev, "%s too low, %d, resetting to %d", 1165 prop, port->intrs, M1575_INTS); 1166 port->intrs = M1575_INTS; 1167 } else if (port->intrs > M1575_MAX_INTS) { 1168 audio_dev_warn(adev, "%s too high, %d, resetting to %d", 1169 prop, port->intrs, M1575_INTS); 1170 port->intrs = M1575_INTS; 1171 } 1172 1173 /* 1174 * Figure out how much space we need. Sample rate is 48kHz, and 1175 * we need to store 32 chunks. (Note that this means that low 1176 * interrupt frequencies will require more RAM. We could probably 1177 * do some cleverness to use a shorter BD list.) 1178 */ 1179 port->fragfr = 48000 / port->intrs; 1180 port->fragfr = M1575_ROUNDUP(port->fragfr, M1575_MOD_SIZE); 1181 port->samp_size = port->fragfr * port->nchan * 2; 1182 port->samp_size *= M1575_BD_NUMS; 1183 1184 /* allocate dma handle */ 1185 rc = ddi_dma_alloc_handle(dip, &sample_buf_dma_attr, DDI_DMA_SLEEP, 1186 NULL, &port->samp_dmah); 1187 if (rc != DDI_SUCCESS) { 1188 audio_dev_warn(adev, "ddi_dma_alloc_handle failed: %d", rc); 1189 return (DDI_FAILURE); 1190 } 1191 /* allocate DMA buffer */ 1192 rc = ddi_dma_mem_alloc(port->samp_dmah, port->samp_size, &buf_attr, 1193 DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, &port->samp_kaddr, 1194 &port->samp_size, &port->samp_acch); 1195 if (rc == DDI_FAILURE) { 1196 audio_dev_warn(adev, "dma_mem_alloc failed"); 1197 return (DDI_FAILURE); 1198 } 1199 1200 /* bind DMA buffer */ 1201 rc = ddi_dma_addr_bind_handle(port->samp_dmah, NULL, 1202 port->samp_kaddr, port->samp_size, dir|DDI_DMA_CONSISTENT, 1203 DDI_DMA_SLEEP, NULL, &cookie, &count); 1204 if ((rc != DDI_DMA_MAPPED) || (count != 1)) { 1205 audio_dev_warn(adev, 1206 "ddi_dma_addr_bind_handle failed: %d", rc); 1207 return (DDI_FAILURE); 1208 } 1209 port->samp_paddr = cookie.dmac_address; 1210 1211 /* 1212 * now, from here we allocate DMA memory for buffer descriptor list. 1213 * we allocate adjacent DMA memory for all DMA engines. 1214 */ 1215 rc = ddi_dma_alloc_handle(dip, &bdlist_dma_attr, DDI_DMA_SLEEP, 1216 NULL, &port->bdl_dmah); 1217 if (rc != DDI_SUCCESS) { 1218 audio_dev_warn(adev, "ddi_dma_alloc_handle(bdlist) failed"); 1219 return (DDI_FAILURE); 1220 } 1221 1222 /* 1223 * we allocate all buffer descriptors lists in continuous dma memory. 1224 */ 1225 port->bdl_size = sizeof (m1575_bd_entry_t) * M1575_BD_NUMS; 1226 rc = ddi_dma_mem_alloc(port->bdl_dmah, port->bdl_size, 1227 &dev_attr, DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, 1228 &port->bdl_kaddr, &port->bdl_size, &port->bdl_acch); 1229 if (rc != DDI_SUCCESS) { 1230 audio_dev_warn(adev, "ddi_dma_mem_alloc(bdlist) failed"); 1231 return (DDI_FAILURE); 1232 } 1233 1234 /* 1235 * Wire up the BD list. We do this *before* binding the BD list 1236 * so that we don't have to do an extra ddi_dma_sync. 1237 */ 1238 paddr = port->samp_paddr; 1239 kaddr = (void *)port->bdl_kaddr; 1240 for (int i = 0; i < M1575_BD_NUMS; i++) { 1241 1242 /* set base address of buffer */ 1243 ddi_put32(port->bdl_acch, kaddr, paddr); 1244 kaddr++; 1245 1246 /* set size in frames, and enable IOC interrupt */ 1247 ddi_put32(port->bdl_acch, kaddr, 1248 ((port->fragfr * port->nchan) | (1U << 31))); 1249 kaddr++; 1250 1251 paddr += (port->fragfr * port->nchan * 2); 1252 } 1253 1254 rc = ddi_dma_addr_bind_handle(port->bdl_dmah, NULL, port->bdl_kaddr, 1255 port->bdl_size, DDI_DMA_WRITE|DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, 1256 NULL, &cookie, &count); 1257 if ((rc != DDI_DMA_MAPPED) || (count != 1)) { 1258 audio_dev_warn(adev, "addr_bind_handle failed"); 1259 return (DDI_FAILURE); 1260 } 1261 port->bdl_paddr = cookie.dmac_address; 1262 1263 port->engine = audio_engine_alloc(&audio1575_engine_ops, caps); 1264 if (port->engine == NULL) { 1265 audio_dev_warn(adev, "audio_engine_alloc failed"); 1266 return (DDI_FAILURE); 1267 } 1268 1269 audio_engine_set_private(port->engine, port); 1270 audio_dev_add_engine(adev, port->engine); 1271 1272 return (DDI_SUCCESS); 1273 } 1274 1275 /* 1276 * audio1575_free_port() 1277 * 1278 * Description: 1279 * This routine unbinds the DMA cookies, frees the DMA buffers, 1280 * deallocates the DMA handles. 1281 * 1282 * Arguments: 1283 * audio810_port_t *port The port structure for a DMA engine. 1284 */ 1285 static void 1286 audio1575_free_port(audio1575_port_t *port) 1287 { 1288 if (port == NULL) 1289 return; 1290 1291 if (port->engine) { 1292 audio_dev_remove_engine(port->statep->adev, port->engine); 1293 audio_engine_free(port->engine); 1294 } 1295 if (port->bdl_paddr) { 1296 (void) ddi_dma_unbind_handle(port->bdl_dmah); 1297 } 1298 if (port->bdl_acch) { 1299 ddi_dma_mem_free(&port->bdl_acch); 1300 } 1301 if (port->bdl_dmah) { 1302 ddi_dma_free_handle(&port->bdl_dmah); 1303 } 1304 if (port->samp_paddr) { 1305 (void) ddi_dma_unbind_handle(port->samp_dmah); 1306 } 1307 if (port->samp_acch) { 1308 ddi_dma_mem_free(&port->samp_acch); 1309 } 1310 if (port->samp_dmah) { 1311 ddi_dma_free_handle(&port->samp_dmah); 1312 } 1313 kmem_free(port, sizeof (*port)); 1314 } 1315 1316 /* 1317 * audio1575_map_regs() 1318 * 1319 * Description: 1320 * The registers are mapped in. 1321 * 1322 * Arguments: 1323 * dev_info_t *dip Pointer to the device's devinfo 1324 * 1325 * Returns: 1326 * DDI_SUCCESS Registers successfully mapped 1327 * DDI_FAILURE Registers not successfully mapped 1328 */ 1329 static int 1330 audio1575_map_regs(audio1575_state_t *statep) 1331 { 1332 dev_info_t *dip = statep->dip; 1333 1334 /* Check for fault management capabilities */ 1335 if (DDI_FM_ACC_ERR_CAP(ddi_fm_capable(dip))) { 1336 dev_attr.devacc_attr_access = DDI_FLAGERR_ACC; 1337 } 1338 1339 /* map the M1575 Audio PCI Cfg Space */ 1340 if (pci_config_setup(dip, &statep->pcih) != DDI_SUCCESS) { 1341 audio_dev_warn(statep->adev, "PCI config map failure"); 1342 goto error; 1343 } 1344 1345 /* map the M1575 Audio registers in PCI IO Space */ 1346 if ((ddi_regs_map_setup(dip, M1575_AUDIO_IO_SPACE, &statep->regsp, 1347 0, 0, &dev_attr, &statep->regsh)) != DDI_SUCCESS) { 1348 audio_dev_warn(statep->adev, "Audio IO mapping failure"); 1349 goto error; 1350 } 1351 return (DDI_SUCCESS); 1352 1353 error: 1354 audio1575_unmap_regs(statep); 1355 1356 return (DDI_FAILURE); 1357 } 1358 1359 /* 1360 * audio1575_unmap_regs() 1361 * 1362 * Description: 1363 * This routine unmaps control registers. 1364 * 1365 * Arguments: 1366 * audio1575_state_t *state The device's state structure 1367 */ 1368 static void 1369 audio1575_unmap_regs(audio1575_state_t *statep) 1370 { 1371 if (statep->regsh) { 1372 ddi_regs_map_free(&statep->regsh); 1373 } 1374 1375 if (statep->pcih) { 1376 pci_config_teardown(&statep->pcih); 1377 } 1378 } 1379 1380 /* 1381 * audio1575_chip_init() 1382 * 1383 * Description: 1384 * This routine initializes the M1575 AC97 audio controller and the AC97 1385 * codec. The AC97 codec registers are programmed from codec_shadow[]. 1386 * If we are not doing a restore, we initialize codec_shadow[], otherwise 1387 * we use the current values of shadow. This routine expects that the 1388 * PCI IO and Memory spaces have been mapped and enabled already. 1389 * Arguments: 1390 * audio1575_state_t *state The device's state structure 1391 * restore from codec_shadow[] 1392 * Returns: 1393 * DDI_SUCCESS The hardware was initialized properly 1394 * DDI_FAILURE The hardware couldn't be initialized properly 1395 */ 1396 static int 1397 audio1575_chip_init(audio1575_state_t *statep) 1398 { 1399 uint32_t ssr; 1400 uint32_t rtsr; 1401 uint32_t intrsr; 1402 int i; 1403 int j; 1404 uint8_t clk_detect; 1405 clock_t ticks; 1406 ddi_acc_handle_t pcih; 1407 1408 /* 1409 * clear the interrupt control and status register 1410 * READ/WRITE/READ workaround required 1411 * for buggy hardware 1412 */ 1413 1414 PUT32(M1575_INTRCR_REG, 0); 1415 (void) GET32(M1575_INTRCR_REG); 1416 1417 intrsr = GET32(M1575_INTRSR_REG); 1418 PUT32(M1575_INTRSR_REG, (intrsr & M1575_INTR_MASK)); 1419 (void) GET32(M1575_INTRSR_REG); 1420 1421 ticks = drv_usectohz(M1575_LOOP_CTR); 1422 1423 /* 1424 * SADA only supports stereo, so we set the channel bits 1425 * to "00" to select 2 channels. 1426 * will also set the following: 1427 * 1428 * Disable double rate enable 1429 * no SPDIF output selected 1430 * 16 bit audio record mode 1431 * 16 bit pcm out mode 1432 * PCM Out 6 chan mode FL FR CEN BL BR LFE 1433 * PCM Out 2 channel mode (00) 1434 */ 1435 for (i = 0; i < M1575_LOOP_CTR; i++) { 1436 /* Reset the AC97 Codec and default to 2 channel 16 bit mode */ 1437 PUT32(M1575_SCR_REG, M1575_SCR_COLDRST); 1438 delay(ticks<<1); 1439 1440 /* Read the System Status Reg */ 1441 ssr = GET32(M1575_SSR_REG); 1442 1443 /* make sure and release the blocked reset bit */ 1444 if (ssr & M1575_SSR_RSTBLK) { 1445 SET32(M1575_INTFCR_REG, M1575_INTFCR_RSTREL); 1446 delay(ticks); 1447 1448 /* Read the System Status Reg */ 1449 ssr = GET32(M1575_SSR_REG); 1450 1451 /* make sure and release the blocked reset bit */ 1452 if (ssr & M1575_SSR_RSTBLK) { 1453 return (DDI_FAILURE); 1454 } 1455 1456 /* Reset the controller */ 1457 PUT32(M1575_SCR_REG, M1575_SCR_COLDRST); 1458 delay(ticks); 1459 } 1460 1461 /* according AC'97 spec, wait for codec reset */ 1462 for (j = 0; j < M1575_LOOP_CTR; j++) { 1463 if ((GET32(M1575_SCR_REG) & M1575_SCR_COLDRST) == 0) { 1464 break; 1465 } 1466 delay(ticks); 1467 } 1468 1469 /* codec reset failed */ 1470 if (j >= M1575_LOOP_CTR) { 1471 audio_dev_warn(statep->adev, 1472 "failure to reset codec"); 1473 return (DDI_FAILURE); 1474 } 1475 1476 /* 1477 * Wait for FACRDY First codec ready. The hardware can 1478 * provide the state of 1479 * codec ready bit on SDATA_IN[0] and as reflected in 1480 * the Recv Tag Slot Reg. 1481 */ 1482 rtsr = GET32(M1575_RTSR_REG); 1483 if (rtsr & M1575_RTSR_FACRDY) { 1484 break; 1485 } else { /* reset the status and wait for new status to set */ 1486 rtsr |= M1575_RTSR_FACRDY; 1487 PUT32(M1575_RTSR_REG, rtsr); 1488 drv_usecwait(10); 1489 } 1490 } 1491 1492 /* if we could not reset the AC97 codec then report failure */ 1493 if (i >= M1575_LOOP_CTR) { 1494 audio_dev_warn(statep->adev, 1495 "no codec ready signal received"); 1496 return (DDI_FAILURE); 1497 } 1498 1499 /* Magic code from ULi to Turn on the AC_LINK clock */ 1500 pcih = statep->pcih; 1501 pci_config_put8(pcih, M1575_PCIACD_REG, 0); 1502 pci_config_put8(pcih, M1575_PCIACD_REG, 4); 1503 pci_config_put8(pcih, M1575_PCIACD_REG, 0); 1504 (void) pci_config_get8(pcih, M1575_PCIACD_REG); 1505 pci_config_put8(pcih, M1575_PCIACD_REG, 2); 1506 pci_config_put8(pcih, M1575_PCIACD_REG, 0); 1507 clk_detect = pci_config_get8(pcih, M1575_PCIACD_REG); 1508 1509 if (clk_detect != 1) { 1510 audio_dev_warn(statep->adev, "No AC97 Clock Detected"); 1511 return (DDI_FAILURE); 1512 } 1513 1514 /* Magic code from Uli to Init FIFO1 and FIFO2 */ 1515 PUT32(M1575_FIFOCR1_REG, 0x81818181); 1516 PUT32(M1575_FIFOCR2_REG, 0x81818181); 1517 PUT32(M1575_FIFOCR3_REG, 0x81818181); 1518 1519 /* Make sure that PCM in and PCM out are enabled */ 1520 SET32(M1575_INTFCR_REG, (M1575_INTFCR_PCMIENB | M1575_INTFCR_PCMOENB)); 1521 1522 audio1575_dma_stop(statep); 1523 1524 return (DDI_SUCCESS); 1525 } 1526 1527 /* 1528 * audio1575_dma_stop() 1529 * 1530 * Description: 1531 * This routine is used to put each DMA engine into the quiet state. 1532 * 1533 * Arguments: 1534 * audio1575_state_t *statep The device's state structure 1535 */ 1536 static void 1537 audio1575_dma_stop(audio1575_state_t *statep) 1538 { 1539 uint32_t intrsr; 1540 int i; 1541 1542 if (statep->regsh == NULL) { 1543 return; 1544 } 1545 1546 /* pause bus master (needed for the following reset register) */ 1547 for (i = 0; i < M1575_LOOP_CTR; i++) { 1548 1549 SET32(M1575_DMACR_REG, M1575_DMACR_PAUSE_ALL); 1550 if (GET32(M1575_DMACR_REG) & M1575_DMACR_PAUSE_ALL) { 1551 break; 1552 } 1553 drv_usecwait(10); 1554 } 1555 1556 if (i >= M1575_LOOP_CTR) { 1557 audio_dev_warn(statep->adev, "failed to stop DMA"); 1558 return; 1559 } 1560 1561 /* Pause bus master (needed for the following reset register) */ 1562 PUT8(M1575_PCMICR_REG, 0); 1563 PUT8(M1575_PCMOCR_REG, 0); 1564 PUT8(M1575_MICICR_REG, 0); 1565 PUT8(M1575_CSPOCR_REG, 0); 1566 PUT8(M1575_PCMI2CR_RR, 0); 1567 PUT8(M1575_MICI2CR_RR, 0); 1568 1569 /* Reset the bus master registers for all DMA engines */ 1570 PUT8(M1575_PCMICR_REG, M1575_PCMICR_RR); 1571 PUT8(M1575_PCMOCR_REG, M1575_PCMOCR_RR); 1572 PUT8(M1575_MICICR_REG, M1575_MICICR_RR); 1573 PUT8(M1575_CSPOCR_REG, M1575_CSPOCR_RR); 1574 PUT8(M1575_PCMI2CR_REG, M1575_PCMI2CR_RR); 1575 PUT8(M1575_MICI2CR_REG, M1575_MICI2CR_RR); 1576 1577 /* Reset FIFOS */ 1578 PUT32(M1575_FIFOCR1_REG, 0x81818181); 1579 PUT32(M1575_FIFOCR2_REG, 0x81818181); 1580 PUT32(M1575_FIFOCR3_REG, 0x81818181); 1581 1582 /* Clear Interrupts */ 1583 SET16(M1575_PCMISR_REG, M1575_SR_CLR); 1584 SET16(M1575_PCMOSR_REG, M1575_SR_CLR); 1585 SET16(M1575_MICISR_REG, M1575_SR_CLR); 1586 SET16(M1575_CSPOSR_REG, M1575_SR_CLR); 1587 SET16(M1575_PCMI2SR_REG, M1575_SR_CLR); 1588 SET16(M1575_MICI2SR_REG, M1575_SR_CLR); 1589 1590 /* 1591 * clear the interrupt control and status register 1592 * READ/WRITE/READ workaround required 1593 * for buggy hardware 1594 */ 1595 1596 PUT32(M1575_INTRCR_REG, 0); 1597 (void) GET32(M1575_INTRCR_REG); 1598 1599 intrsr = GET32(M1575_INTRSR_REG); 1600 PUT32(M1575_INTRSR_REG, (intrsr & M1575_INTR_MASK)); 1601 (void) GET32(M1575_INTRSR_REG); 1602 } 1603 1604 /* 1605 * audio1575_codec_sync() 1606 * 1607 * Description: 1608 * Serialize access to the AC97 audio mixer registers. 1609 * 1610 * Arguments: 1611 * audio1575_state_t *state The device's state structure 1612 * 1613 * Returns: 1614 * DDI_SUCCESS Ready for an I/O access to the codec 1615 * DDI_FAILURE An I/O access is currently in progress, can't 1616 * perform another I/O access. 1617 */ 1618 static int 1619 audio1575_codec_sync(audio1575_state_t *statep) 1620 { 1621 /* do the Uli Shuffle ... */ 1622 for (int i = 0; i < M1575_LOOP_CTR; i++) { 1623 /* Read the semaphore, and loop till we own it */ 1624 if ((GET32(M1575_CASR_REG) & 1) == 0) { 1625 for (int j = 0; j < M1575_LOOP_CTR; j++) { 1626 /* Wait for CWRSUCC 0x8 */ 1627 if (GET32(M1575_CSPSR_REG) & 1628 M1575_CSPSR_SUCC) { 1629 return (DDI_SUCCESS); 1630 } 1631 drv_usecwait(1); 1632 } 1633 } 1634 drv_usecwait(10); 1635 } 1636 1637 return (DDI_FAILURE); 1638 } 1639 1640 /* 1641 * audio1575_write_ac97() 1642 * 1643 * Description: 1644 * Set the specific AC97 Codec register. 1645 * 1646 * Arguments: 1647 * void *arg The device's state structure 1648 * uint8_t reg AC97 register number 1649 * uint16_t data The data want to be set 1650 */ 1651 static void 1652 audio1575_write_ac97(void *arg, uint8_t reg, uint16_t data) 1653 { 1654 audio1575_state_t *statep = arg; 1655 int i; 1656 1657 mutex_enter(&statep->ac_lock); 1658 1659 if (audio1575_codec_sync(statep) != DDI_SUCCESS) { 1660 mutex_exit(&statep->ac_lock); 1661 return; 1662 } 1663 1664 /* write the data to WRITE to the lo word of the CPR register */ 1665 PUT16(M1575_CPR_REG, data); 1666 1667 /* write the address to WRITE to the hi word of the CPR register */ 1668 PUT16(M1575_CPR_REG+2, reg); 1669 1670 /* wait until command is completed sucessfully */ 1671 for (i = 0; i < M1575_LOOP_CTR; i++) { 1672 /* Wait for Write Ready 0x01 */ 1673 if (GET32(M1575_CSPSR_REG) & M1575_CSPSR_WRRDY) { 1674 break; 1675 } 1676 drv_usecwait(1); 1677 } 1678 1679 mutex_exit(&statep->ac_lock); 1680 1681 if (i < M1575_LOOP_CTR) { 1682 (void) audio1575_read_ac97(statep, reg); 1683 } 1684 } 1685 1686 /* 1687 * audio1575_read_ac97() 1688 * 1689 * Description: 1690 * Get the specific AC97 Codec register. It also updates codec_shadow[] 1691 * with the register value. 1692 * 1693 * Arguments: 1694 * void *arg The device's state structure 1695 * uint8_t reg AC97 register number 1696 * 1697 * Returns: 1698 * Value of AC97 register. (0xffff in failure situations). 1699 */ 1700 static uint16_t 1701 audio1575_read_ac97(void *arg, uint8_t reg) 1702 { 1703 audio1575_state_t *statep = arg; 1704 uint16_t addr = 0; 1705 uint16_t data = 0xffff; 1706 int i; 1707 1708 mutex_enter(&statep->ac_lock); 1709 if ((audio1575_codec_sync(statep)) != DDI_SUCCESS) { 1710 mutex_exit(&statep->ac_lock); 1711 return (data); 1712 } 1713 1714 /* 1715 * at this point we have the CASR semaphore 1716 * and the codec is r/w ready 1717 * OR in the READ opcode into the address field 1718 */ 1719 1720 addr = (reg | M1575_CPR_READ); 1721 1722 /* write the address to READ to the hi word of the CPR register */ 1723 PUT16(M1575_CPR_REG+2, addr); 1724 1725 /* wait until command is completed sucessfully */ 1726 for (i = 0; i < M1575_LOOP_CTR; i++) { 1727 /* Wait for Read Ready 0x02 */ 1728 if (GET32(M1575_CSPSR_REG) & M1575_CSPSR_RDRDY) { 1729 break; 1730 } 1731 drv_usecwait(1); 1732 } 1733 1734 if (i < M1575_LOOP_CTR) { 1735 /* read back the data and address */ 1736 data = GET16(M1575_SPR_REG); 1737 addr = GET16(M1575_SPR_REG+2); 1738 if (addr != reg) { 1739 data = 0xffff; 1740 } 1741 } 1742 1743 mutex_exit(&statep->ac_lock); 1744 return (data); 1745 } 1746 1747 /* 1748 * audio1575_pci_enable() 1749 * 1750 * Description: 1751 * This routine Enables all PCI IO and MEMORY accesses 1752 * 1753 * Arguments: 1754 * audio1575_state_t *statep The device's state structure 1755 */ 1756 static void 1757 audio1575_pci_enable(audio1575_state_t *statep) 1758 { 1759 uint16_t pcics_reg; 1760 1761 pcics_reg = pci_config_get16(statep->pcih, PCI_CONF_COMM); 1762 pcics_reg |= (PCI_COMM_IO | PCI_COMM_MAE | PCI_COMM_ME); 1763 pci_config_put16(statep->pcih, PCI_CONF_COMM, pcics_reg); 1764 } 1765 1766 /* 1767 * audio1575_pci_disable() 1768 * 1769 * Description: 1770 * This routine Disables all PCI IO and MEMORY accesses 1771 * 1772 * Arguments: 1773 * audio1575_state_t *statep The device's state structure 1774 */ 1775 static void 1776 audio1575_pci_disable(audio1575_state_t *statep) 1777 { 1778 uint16_t pcics_reg; 1779 1780 if (statep->pcih == NULL) 1781 return; 1782 pcics_reg = pci_config_get16(statep->pcih, PCI_CONF_COMM); 1783 pcics_reg &= ~(PCI_COMM_IO | PCI_COMM_MAE | PCI_COMM_ME); 1784 pci_config_put16(statep->pcih, PCI_CONF_COMM, pcics_reg); 1785 } 1786 1787 /* 1788 * audio1575_resume() 1789 * 1790 * Description: 1791 * Resume operation of the device after sleeping or hibernating. 1792 * Note that this should never fail, even if hardware goes wonky, 1793 * because the current PM framework will panic if it does. 1794 * 1795 * Arguments: 1796 * dev_info_t *dip Pointer to the device's dev_info struct 1797 * 1798 * Returns: 1799 * DDI_SUCCESS The driver was resumed 1800 */ 1801 static int 1802 audio1575_resume(dev_info_t *dip) 1803 { 1804 audio1575_state_t *statep; 1805 audio_dev_t *adev; 1806 1807 /* we've already allocated the state structure so get ptr */ 1808 statep = ddi_get_driver_private(dip); 1809 adev = statep->adev; 1810 ASSERT(!mutex_owned(&statep->lock)); 1811 1812 if (audio1575_chip_init(statep) != DDI_SUCCESS) { 1813 /* 1814 * Note that PM gurus say we should return 1815 * success here. Failure of audio shouldn't 1816 * be considered FATAL to the system. The 1817 * upshot is that audio will not progress. 1818 */ 1819 audio_dev_warn(adev, "DDI_RESUME failed to init chip"); 1820 return (DDI_SUCCESS); 1821 } 1822 1823 /* allow ac97 operations again */ 1824 ac97_resume(statep->ac97); 1825 1826 mutex_enter(&statep->lock); 1827 1828 ASSERT(statep->suspended); 1829 statep->suspended = B_FALSE; 1830 1831 for (int i = 0; i < M1575_NUM_PORTS; i++) { 1832 1833 audio1575_port_t *port = statep->ports[i]; 1834 1835 if (port != NULL) { 1836 /* reset framework DMA engine buffer */ 1837 if (port->engine != NULL) { 1838 audio_engine_reset(port->engine); 1839 } 1840 1841 /* reset and initialize hardware ports */ 1842 audio1575_reset_port(port); 1843 if (port->started) { 1844 audio1575_start_port(port); 1845 } else { 1846 audio1575_stop_port(port); 1847 } 1848 } 1849 } 1850 mutex_exit(&statep->lock); 1851 1852 return (DDI_SUCCESS); 1853 } 1854 1855 /* 1856 * audio1575_suspend() 1857 * 1858 * Description: 1859 * Suspend an instance of the audio1575 driver. 1860 * 1861 * Arguments: 1862 * dev_info_t *dip Pointer to the device's dev_info struct 1863 * 1864 * Returns: 1865 * DDI_SUCCESS The driver was suspended 1866 */ 1867 static int 1868 audio1575_suspend(dev_info_t *dip) 1869 { 1870 audio1575_state_t *statep; 1871 1872 statep = ddi_get_driver_private(dip); 1873 1874 ac97_suspend(statep->ac97); 1875 1876 mutex_enter(&statep->lock); 1877 1878 statep->suspended = B_TRUE; 1879 1880 /* 1881 * stop all DMA operations 1882 */ 1883 audio1575_dma_stop(statep); 1884 1885 mutex_exit(&statep->lock); 1886 1887 return (DDI_SUCCESS); 1888 } 1889 1890 /* 1891 * audio1575_destroy() 1892 * 1893 * Description: 1894 * This routine releases all resources held by the device instance, 1895 * as part of either detach or a failure in attach. 1896 * 1897 * Arguments: 1898 * audio1575_state_t *state The device soft state. 1899 * 1900 * Returns: 1901 * None 1902 */ 1903 void 1904 audio1575_destroy(audio1575_state_t *statep) 1905 { 1906 ddi_acc_handle_t pcih; 1907 1908 /* stop DMA engines */ 1909 audio1575_dma_stop(statep); 1910 1911 if (statep->regsh != NULL) { 1912 /* reset the codec */ 1913 PUT32(M1575_SCR_REG, M1575_SCR_COLDRST); 1914 } 1915 1916 if ((pcih = statep->pcih) != NULL) { 1917 /* turn off the AC_LINK clock */ 1918 pci_config_put8(pcih, M1575_PCIACD_REG, 0); 1919 pci_config_put8(pcih, M1575_PCIACD_REG, 4); 1920 pci_config_put8(pcih, M1575_PCIACD_REG, 0); 1921 } 1922 1923 /* Disable PCI I/O and Memory Spaces */ 1924 audio1575_pci_disable(statep); 1925 1926 if (statep->ih != NULL) { 1927 (void) ddi_intr_disable(statep->ih); 1928 (void) ddi_intr_remove_handler(statep->ih); 1929 (void) ddi_intr_free(statep->ih); 1930 mutex_destroy(&statep->lock); 1931 mutex_destroy(&statep->ac_lock); 1932 } 1933 1934 if (statep->ksp != NULL) { 1935 kstat_delete(statep->ksp); 1936 } 1937 1938 audio1575_free_port(statep->ports[M1575_PLAY]); 1939 audio1575_free_port(statep->ports[M1575_REC]); 1940 1941 audio1575_unmap_regs(statep); 1942 1943 if (statep->ac97 != NULL) { 1944 ac97_free(statep->ac97); 1945 } 1946 1947 if (statep->adev != NULL) { 1948 audio_dev_free(statep->adev); 1949 } 1950 1951 kmem_free(statep, sizeof (*statep)); 1952 } 1953