1*5e8715b9SGary Mills /* 2*5e8715b9SGary Mills * CDDL HEADER START 3*5e8715b9SGary Mills * 4*5e8715b9SGary Mills * The contents of this file are subject to the terms of the 5*5e8715b9SGary Mills * Common Development and Distribution License (the "License"). 6*5e8715b9SGary Mills * You may not use this file except in compliance with the License. 7*5e8715b9SGary Mills * 8*5e8715b9SGary Mills * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9*5e8715b9SGary Mills * or http://www.opensolaris.org/os/licensing. 10*5e8715b9SGary Mills * See the License for the specific language governing permissions 11*5e8715b9SGary Mills * and limitations under the License. 12*5e8715b9SGary Mills * 13*5e8715b9SGary Mills * When distributing Covered Code, include this CDDL HEADER in each 14*5e8715b9SGary Mills * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15*5e8715b9SGary Mills * If applicable, add the following below this CDDL HEADER, with the 16*5e8715b9SGary Mills * fields enclosed by brackets "[]" replaced with your own identifying 17*5e8715b9SGary Mills * information: Portions Copyright [yyyy] [name of copyright owner] 18*5e8715b9SGary Mills * 19*5e8715b9SGary Mills * CDDL HEADER END 20*5e8715b9SGary Mills */ 21*5e8715b9SGary Mills /* 22*5e8715b9SGary Mills * Copyright (c) 2012 Gary Mills 23*5e8715b9SGary Mills * 24*5e8715b9SGary Mills * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 25*5e8715b9SGary Mills * Use is subject to license terms. 26*5e8715b9SGary Mills */ 27*5e8715b9SGary Mills /* 28*5e8715b9SGary Mills * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 29*5e8715b9SGary Mills * All rights reserved. 30*5e8715b9SGary Mills * 31*5e8715b9SGary Mills * Redistribution and use in source and binary forms, with or without 32*5e8715b9SGary Mills * modification, are permitted provided that the following conditions 33*5e8715b9SGary Mills * are met: 34*5e8715b9SGary Mills * 1. Redistributions of source code must retain the above copyright 35*5e8715b9SGary Mills * notice unmodified, this list of conditions, and the following 36*5e8715b9SGary Mills * disclaimer. 37*5e8715b9SGary Mills * 2. Redistributions in binary form must reproduce the above copyright 38*5e8715b9SGary Mills * notice, this list of conditions and the following disclaimer in the 39*5e8715b9SGary Mills * documentation and/or other materials provided with the distribution. 40*5e8715b9SGary Mills * 41*5e8715b9SGary Mills * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 42*5e8715b9SGary Mills * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 43*5e8715b9SGary Mills * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 44*5e8715b9SGary Mills * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 45*5e8715b9SGary Mills * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 46*5e8715b9SGary Mills * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 47*5e8715b9SGary Mills * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 48*5e8715b9SGary Mills * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 49*5e8715b9SGary Mills * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 50*5e8715b9SGary Mills * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 51*5e8715b9SGary Mills * SUCH DAMAGE. 52*5e8715b9SGary Mills */ 53*5e8715b9SGary Mills 54*5e8715b9SGary Mills #ifndef _ATGE_L1C_REG_H 55*5e8715b9SGary Mills #define _ATGE_L1C_REG_H 56*5e8715b9SGary Mills 57*5e8715b9SGary Mills #ifdef __cplusplus 58*5e8715b9SGary Mills extern "C" { 59*5e8715b9SGary Mills #endif 60*5e8715b9SGary Mills 61*5e8715b9SGary Mills #pragma pack(1) 62*5e8715b9SGary Mills typedef struct l1c_cmb { 63*5e8715b9SGary Mills uint32_t intr_status; 64*5e8715b9SGary Mills uint32_t rx_prod_cons; 65*5e8715b9SGary Mills uint32_t tx_prod_cons; 66*5e8715b9SGary Mills } l1c_cmb_t; 67*5e8715b9SGary Mills 68*5e8715b9SGary Mills typedef struct l1c_rx_desc { 69*5e8715b9SGary Mills uint64_t addr; 70*5e8715b9SGary Mills /* No length field. */ 71*5e8715b9SGary Mills } l1c_rx_desc_t; 72*5e8715b9SGary Mills 73*5e8715b9SGary Mills typedef struct l1c_rx_rdesc { 74*5e8715b9SGary Mills uint32_t rdinfo; /* word 0 */ 75*5e8715b9SGary Mills uint32_t rss; /* word 1 */ 76*5e8715b9SGary Mills uint32_t vtag; /* word 2 */ 77*5e8715b9SGary Mills uint32_t status; /* word 3 */ 78*5e8715b9SGary Mills } l1c_rx_rdesc_t; 79*5e8715b9SGary Mills 80*5e8715b9SGary Mills /* 81*5e8715b9SGary Mills * Statistics counters collected by the MAC 82*5e8715b9SGary Mills */ 83*5e8715b9SGary Mills typedef struct l1c_smb { 84*5e8715b9SGary Mills /* Rx stats. */ 85*5e8715b9SGary Mills uint32_t rx_frames; 86*5e8715b9SGary Mills uint32_t rx_bcast_frames; 87*5e8715b9SGary Mills uint32_t rx_mcast_frames; 88*5e8715b9SGary Mills uint32_t rx_pause_frames; 89*5e8715b9SGary Mills uint32_t rx_control_frames; 90*5e8715b9SGary Mills uint32_t rx_crcerrs; 91*5e8715b9SGary Mills uint32_t rx_lenerrs; 92*5e8715b9SGary Mills uint32_t rx_bytes; 93*5e8715b9SGary Mills uint32_t rx_runts; 94*5e8715b9SGary Mills uint32_t rx_fragments; 95*5e8715b9SGary Mills uint32_t rx_pkts_64; 96*5e8715b9SGary Mills uint32_t rx_pkts_65_127; 97*5e8715b9SGary Mills uint32_t rx_pkts_128_255; 98*5e8715b9SGary Mills uint32_t rx_pkts_256_511; 99*5e8715b9SGary Mills uint32_t rx_pkts_512_1023; 100*5e8715b9SGary Mills uint32_t rx_pkts_1024_1518; 101*5e8715b9SGary Mills uint32_t rx_pkts_1519_max; 102*5e8715b9SGary Mills uint32_t rx_pkts_truncated; 103*5e8715b9SGary Mills uint32_t rx_fifo_oflows; 104*5e8715b9SGary Mills uint32_t rx_desc_oflows; 105*5e8715b9SGary Mills uint32_t rx_alignerrs; 106*5e8715b9SGary Mills uint32_t rx_bcast_bytes; 107*5e8715b9SGary Mills uint32_t rx_mcast_bytes; 108*5e8715b9SGary Mills uint32_t rx_pkts_filtered; 109*5e8715b9SGary Mills /* Tx stats. */ 110*5e8715b9SGary Mills uint32_t tx_frames; 111*5e8715b9SGary Mills uint32_t tx_bcast_frames; 112*5e8715b9SGary Mills uint32_t tx_mcast_frames; 113*5e8715b9SGary Mills uint32_t tx_pause_frames; 114*5e8715b9SGary Mills uint32_t tx_excess_defer; 115*5e8715b9SGary Mills uint32_t tx_control_frames; 116*5e8715b9SGary Mills uint32_t tx_deferred; 117*5e8715b9SGary Mills uint32_t tx_bytes; 118*5e8715b9SGary Mills uint32_t tx_pkts_64; 119*5e8715b9SGary Mills uint32_t tx_pkts_65_127; 120*5e8715b9SGary Mills uint32_t tx_pkts_128_255; 121*5e8715b9SGary Mills uint32_t tx_pkts_256_511; 122*5e8715b9SGary Mills uint32_t tx_pkts_512_1023; 123*5e8715b9SGary Mills uint32_t tx_pkts_1024_1518; 124*5e8715b9SGary Mills uint32_t tx_pkts_1519_max; 125*5e8715b9SGary Mills uint32_t tx_single_colls; 126*5e8715b9SGary Mills uint32_t tx_multi_colls; 127*5e8715b9SGary Mills uint32_t tx_late_colls; 128*5e8715b9SGary Mills uint32_t tx_excess_colls; 129*5e8715b9SGary Mills uint32_t tx_underrun; 130*5e8715b9SGary Mills uint32_t tx_desc_underrun; 131*5e8715b9SGary Mills uint32_t tx_lenerrs; 132*5e8715b9SGary Mills uint32_t tx_pkts_truncated; 133*5e8715b9SGary Mills uint32_t tx_bcast_bytes; 134*5e8715b9SGary Mills uint32_t tx_mcast_bytes; 135*5e8715b9SGary Mills uint32_t updated; 136*5e8715b9SGary Mills } atge_l1c_smb_t; 137*5e8715b9SGary Mills #pragma pack() 138*5e8715b9SGary Mills 139*5e8715b9SGary Mills #define L1C_RX_RING_CNT 256 140*5e8715b9SGary Mills #define L1C_RR_RING_CNT L1C_RX_RING_CNT 141*5e8715b9SGary Mills #define L1C_HEADROOM 6 /* Must be divisible by 2, but not 4. */ 142*5e8715b9SGary Mills 143*5e8715b9SGary Mills #define L1C_RING_ALIGN 16 144*5e8715b9SGary Mills #define L1C_TX_RING_ALIGN 16 145*5e8715b9SGary Mills #define L1C_RX_RING_ALIGN 16 146*5e8715b9SGary Mills #define L1C_RR_RING_ALIGN 16 147*5e8715b9SGary Mills #define L1C_CMB_ALIGN 16 148*5e8715b9SGary Mills #define L1C_SMB_ALIGN 16 149*5e8715b9SGary Mills 150*5e8715b9SGary Mills #define L1C_CMB_BLOCK_SZ sizeof (struct l1c_cmb) 151*5e8715b9SGary Mills #define L1C_SMB_BLOCK_SZ sizeof (struct l1c_smb) 152*5e8715b9SGary Mills 153*5e8715b9SGary Mills #define L1C_RX_RING_SZ \ 154*5e8715b9SGary Mills (sizeof (struct l1c_rx_desc) * L1C_RX_RING_CNT) 155*5e8715b9SGary Mills 156*5e8715b9SGary Mills #define L1C_RR_RING_SZ \ 157*5e8715b9SGary Mills (sizeof (struct l1c_rx_rdesc) * L1C_RR_RING_CNT) 158*5e8715b9SGary Mills 159*5e8715b9SGary Mills /* 160*5e8715b9SGary Mills * For RX 161*5e8715b9SGary Mills */ 162*5e8715b9SGary Mills /* word 0 */ 163*5e8715b9SGary Mills #define L1C_RRD_CSUM_MASK 0x0000FFFF 164*5e8715b9SGary Mills #define L1C_RRD_RD_CNT_MASK 0x000F0000 165*5e8715b9SGary Mills #define L1C_RRD_RD_IDX_MASK 0xFFF00000 166*5e8715b9SGary Mills #define L1C_RRD_CSUM_SHIFT 0 167*5e8715b9SGary Mills #define L1C_RRD_RD_CNT_SHIFT 16 168*5e8715b9SGary Mills #define L1C_RRD_RD_IDX_SHIFT 20 169*5e8715b9SGary Mills #define L1C_RRD_CSUM(x) \ 170*5e8715b9SGary Mills (((x) & L1C_RRD_CSUM_MASK) >> L1C_RRD_CSUM_SHIFT) 171*5e8715b9SGary Mills #define L1C_RRD_RD_CNT(x) \ 172*5e8715b9SGary Mills (((x) & L1C_RRD_RD_CNT_MASK) >> L1C_RRD_RD_CNT_SHIFT) 173*5e8715b9SGary Mills #define L1C_RRD_RD_IDX(x) \ 174*5e8715b9SGary Mills (((x) & L1C_RRD_RD_IDX_MASK) >> L1C_RRD_RD_IDX_SHIFT) 175*5e8715b9SGary Mills 176*5e8715b9SGary Mills /* word 2 */ 177*5e8715b9SGary Mills #define L1C_RRD_VLAN_MASK 0x0000FFFF 178*5e8715b9SGary Mills #define L1C_RRD_HEAD_LEN_MASK 0x00FF0000 179*5e8715b9SGary Mills #define L1C_RRD_HDS_MASK 0x03000000 180*5e8715b9SGary Mills #define L1C_RRD_HDS_NONE 0x00000000 181*5e8715b9SGary Mills #define L1C_RRD_HDS_HEAD 0x01000000 182*5e8715b9SGary Mills #define L1C_RRD_HDS_DATA 0x02000000 183*5e8715b9SGary Mills #define L1C_RRD_CPU_MASK 0x0C000000 184*5e8715b9SGary Mills #define L1C_RRD_HASH_FLAG_MASK 0xF0000000 185*5e8715b9SGary Mills #define L1C_RRD_VLAN_SHIFT 0 186*5e8715b9SGary Mills #define L1C_RRD_HEAD_LEN_SHIFT 16 187*5e8715b9SGary Mills #define L1C_RRD_HDS_SHIFT 24 188*5e8715b9SGary Mills #define L1C_RRD_CPU_SHIFT 26 189*5e8715b9SGary Mills #define L1C_RRD_HASH_FLAG_SHIFT 28 190*5e8715b9SGary Mills #define L1C_RRD_VLAN(x) \ 191*5e8715b9SGary Mills (((x) & L1C_RRD_VLAN_MASK) >> L1C_RRD_VLAN_SHIFT) 192*5e8715b9SGary Mills #define L1C_RRD_HEAD_LEN(x) \ 193*5e8715b9SGary Mills (((x) & L1C_RRD_HEAD_LEN_MASK) >> L1C_RRD_HEAD_LEN_SHIFT) 194*5e8715b9SGary Mills #define L1C_RRD_CPU(x) \ 195*5e8715b9SGary Mills (((x) & L1C_RRD_CPU_MASK) >> L1C_RRD_CPU_SHIFT) 196*5e8715b9SGary Mills 197*5e8715b9SGary Mills /* word3 */ 198*5e8715b9SGary Mills #define L1C_RRD_LEN_MASK 0x00003FFF 199*5e8715b9SGary Mills #define L1C_RRD_LEN_SHIFT 0 200*5e8715b9SGary Mills #define L1C_RRD_TCP_UDPCSUM_NOK 0x00004000 201*5e8715b9SGary Mills #define L1C_RRD_IPCSUM_NOK 0x00008000 202*5e8715b9SGary Mills #define L1C_RRD_VLAN_TAG 0x00010000 203*5e8715b9SGary Mills #define L1C_RRD_PROTO_MASK 0x000E0000 204*5e8715b9SGary Mills #define L1C_RRD_PROTO_IPV4 0x00020000 205*5e8715b9SGary Mills #define L1C_RRD_PROTO_IPV6 0x000C0000 206*5e8715b9SGary Mills #define L1C_RRD_ERR_SUM 0x00100000 207*5e8715b9SGary Mills #define L1C_RRD_ERR_CRC 0x00200000 208*5e8715b9SGary Mills #define L1C_RRD_ERR_ALIGN 0x00400000 209*5e8715b9SGary Mills #define L1C_RRD_ERR_TRUNC 0x00800000 210*5e8715b9SGary Mills #define L1C_RRD_ERR_RUNT 0x01000000 211*5e8715b9SGary Mills #define L1C_RRD_ERR_ICMP 0x02000000 212*5e8715b9SGary Mills #define L1C_RRD_BCAST 0x04000000 213*5e8715b9SGary Mills #define L1C_RRD_MCAST 0x08000000 214*5e8715b9SGary Mills #define L1C_RRD_SNAP_LLC 0x10000000 215*5e8715b9SGary Mills #define L1C_RRD_ETHER 0x00000000 216*5e8715b9SGary Mills #define L1C_RRD_FIFO_FULL 0x20000000 217*5e8715b9SGary Mills #define L1C_RRD_ERR_LENGTH 0x40000000 218*5e8715b9SGary Mills #define L1C_RRD_VALID 0x80000000 219*5e8715b9SGary Mills #define L1C_RRD_BYTES(x) \ 220*5e8715b9SGary Mills (((x) & L1C_RRD_LEN_MASK) >> L1C_RRD_LEN_SHIFT) 221*5e8715b9SGary Mills #define L1C_RRD_IPV4(x) \ 222*5e8715b9SGary Mills (((x) & L1C_RRD_PROTO_MASK) == L1C_RRD_PROTO_IPV4) 223*5e8715b9SGary Mills 224*5e8715b9SGary Mills #define RRD_PROD_MASK 0x0000FFFF 225*5e8715b9SGary Mills #define TPD_CONS_MASK 0xFFFF0000 226*5e8715b9SGary Mills #define TPD_CONS_SHIFT 16 227*5e8715b9SGary Mills #define CMB_UPDATED 0x00000001 228*5e8715b9SGary Mills #define RRD_PROD_SHIFT 0 229*5e8715b9SGary Mills 230*5e8715b9SGary Mills #pragma pack(1) 231*5e8715b9SGary Mills typedef struct l1c_tx_desc { 232*5e8715b9SGary Mills uint32_t len; 233*5e8715b9SGary Mills #define L1C_TD_BUFLEN_MASK 0x00003FFF 234*5e8715b9SGary Mills #define L1C_TD_VLAN_MASK 0xFFFF0000 235*5e8715b9SGary Mills #define L1C_TD_BUFLEN_SHIFT 0 236*5e8715b9SGary Mills #define L1C_TX_BYTES(x) \ 237*5e8715b9SGary Mills (((x) << L1C_TD_BUFLEN_SHIFT) & L1C_TD_BUFLEN_MASK) 238*5e8715b9SGary Mills #define L1C_TD_VLAN_SHIFT 16 239*5e8715b9SGary Mills 240*5e8715b9SGary Mills uint32_t flags; 241*5e8715b9SGary Mills #define L1C_TD_L4HDR_OFFSET_MASK 0x000000FF /* byte unit */ 242*5e8715b9SGary Mills #define L1C_TD_TCPHDR_OFFSET_MASK 0x000000FF /* byte unit */ 243*5e8715b9SGary Mills #define L1C_TD_PLOAD_OFFSET_MASK 0x000000FF /* 2 bytes unit */ 244*5e8715b9SGary Mills #define L1C_TD_CUSTOM_CSUM 0x00000100 245*5e8715b9SGary Mills #define L1C_TD_IPCSUM 0x00000200 246*5e8715b9SGary Mills #define L1C_TD_TCPCSUM 0x00000400 247*5e8715b9SGary Mills #define L1C_TD_UDPCSUM 0x00000800 248*5e8715b9SGary Mills #define L1C_TD_TSO 0x00001000 249*5e8715b9SGary Mills #define L1C_TD_TSO_DESCV1 0x00000000 250*5e8715b9SGary Mills #define L1C_TD_TSO_DESCV2 0x00002000 251*5e8715b9SGary Mills #define L1C_TD_CON_VLAN_TAG 0x00004000 252*5e8715b9SGary Mills #define L1C_TD_INS_VLAN_TAG 0x00008000 253*5e8715b9SGary Mills #define L1C_TD_IPV4_DESCV2 0x00010000 254*5e8715b9SGary Mills #define L1C_TD_LLC_SNAP 0x00020000 255*5e8715b9SGary Mills #define L1C_TD_ETHERNET 0x00000000 256*5e8715b9SGary Mills #define L1C_TD_CUSTOM_CSUM_OFFSET_MASK 0x03FC0000 /* 2 bytes unit */ 257*5e8715b9SGary Mills #define L1C_TD_CUSTOM_CSUM_EVEN_PAD 0x40000000 258*5e8715b9SGary Mills #define L1C_TD_MSS_MASK 0x7FFC0000 259*5e8715b9SGary Mills #define L1C_TD_EOP 0x80000000 260*5e8715b9SGary Mills #define L1C_TD_L4HDR_OFFSET_SHIFT 0 261*5e8715b9SGary Mills #define L1C_TD_TCPHDR_OFFSET_SHIFT 0 262*5e8715b9SGary Mills #define L1C_TD_PLOAD_OFFSET_SHIFT 0 263*5e8715b9SGary Mills #define L1C_TD_CUSTOM_CSUM_OFFSET_SHIFT 18 264*5e8715b9SGary Mills #define L1C_TD_MSS_SHIFT 18 265*5e8715b9SGary Mills 266*5e8715b9SGary Mills uint64_t addr; 267*5e8715b9SGary Mills } l1c_tx_desc_t; 268*5e8715b9SGary Mills #pragma pack() 269*5e8715b9SGary Mills 270*5e8715b9SGary Mills /* 271*5e8715b9SGary Mills * All descriptors and CMB/SMB share the same high address. 272*5e8715b9SGary Mills */ 273*5e8715b9SGary Mills 274*5e8715b9SGary Mills /* From Freebsd if_alcreg.h */ 275*5e8715b9SGary Mills #define L1C_RSS_IDT_TABLE0 0x14E0 276*5e8715b9SGary Mills 277*5e8715b9SGary Mills #define L1C_RX_BASE_ADDR_HI 0x1540 278*5e8715b9SGary Mills 279*5e8715b9SGary Mills #define L1C_TX_BASE_ADDR_HI 0x1544 280*5e8715b9SGary Mills 281*5e8715b9SGary Mills #define L1C_SMB_BASE_ADDR_HI 0x1548 282*5e8715b9SGary Mills 283*5e8715b9SGary Mills #define L1C_SMB_BASE_ADDR_LO 0x154C 284*5e8715b9SGary Mills 285*5e8715b9SGary Mills #define L1C_RD0_HEAD_ADDR_LO 0x1550 286*5e8715b9SGary Mills 287*5e8715b9SGary Mills #define L1C_RD1_HEAD_ADDR_LO 0x1554 288*5e8715b9SGary Mills 289*5e8715b9SGary Mills #define L1C_RD2_HEAD_ADDR_LO 0x1558 290*5e8715b9SGary Mills 291*5e8715b9SGary Mills #define L1C_RD3_HEAD_ADDR_LO 0x155C 292*5e8715b9SGary Mills 293*5e8715b9SGary Mills #define L1C_RD_RING_CNT 0x1560 294*5e8715b9SGary Mills #define RD_RING_CNT_MASK 0x00000FFF 295*5e8715b9SGary Mills #define RD_RING_CNT_SHIFT 0 296*5e8715b9SGary Mills 297*5e8715b9SGary Mills #define L1C_RX_BUF_SIZE 0x1564 298*5e8715b9SGary Mills #define RX_BUF_SIZE_MASK 0x0000FFFF 299*5e8715b9SGary Mills /* 300*5e8715b9SGary Mills * If larger buffer size than 1536 is specified the controller 301*5e8715b9SGary Mills * will be locked up. This is hardware limitation. 302*5e8715b9SGary Mills */ 303*5e8715b9SGary Mills #define RX_BUF_SIZE_MAX 1536 304*5e8715b9SGary Mills 305*5e8715b9SGary Mills #define L1C_RRD0_HEAD_ADDR_LO 0x1568 306*5e8715b9SGary Mills 307*5e8715b9SGary Mills #define L1C_RRD1_HEAD_ADDR_LO 0x156C 308*5e8715b9SGary Mills 309*5e8715b9SGary Mills #define L1C_RRD2_HEAD_ADDR_LO 0x1570 310*5e8715b9SGary Mills 311*5e8715b9SGary Mills #define L1C_RRD3_HEAD_ADDR_LO 0x1574 312*5e8715b9SGary Mills 313*5e8715b9SGary Mills #define L1C_RRD_RING_CNT 0x1578 314*5e8715b9SGary Mills #define RRD_RING_CNT_MASK 0x00000FFF 315*5e8715b9SGary Mills #define RRD_RING_CNT_SHIFT 0 316*5e8715b9SGary Mills 317*5e8715b9SGary Mills #define L1C_TDH_HEAD_ADDR_LO 0x157C 318*5e8715b9SGary Mills 319*5e8715b9SGary Mills #define L1C_TDL_HEAD_ADDR_LO 0x1580 320*5e8715b9SGary Mills 321*5e8715b9SGary Mills #define L1C_TD_RING_CNT 0x1584 322*5e8715b9SGary Mills #define TD_RING_CNT_MASK 0x0000FFFF 323*5e8715b9SGary Mills #define TD_RING_CNT_SHIFT 0 324*5e8715b9SGary Mills 325*5e8715b9SGary Mills #define L1C_CMB_BASE_ADDR_LO 0x1588 326*5e8715b9SGary Mills 327*5e8715b9SGary Mills #define L1C_RXQ_CFG 0x15A0 328*5e8715b9SGary Mills #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_MASK 0x00000003 329*5e8715b9SGary Mills #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_NONE 0x00000000 330*5e8715b9SGary Mills #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M 0x00000001 331*5e8715b9SGary Mills #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_10M 0x00000002 332*5e8715b9SGary Mills #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M 0x00000003 333*5e8715b9SGary Mills 334*5e8715b9SGary Mills #define L1C_RSS_CPU 0x15B8 335*5e8715b9SGary Mills 336*5e8715b9SGary Mills /* End of Freebsd if_alcreg.h */ 337*5e8715b9SGary Mills 338*5e8715b9SGary Mills /* 339*5e8715b9SGary Mills * PHY registers. 340*5e8715b9SGary Mills */ 341*5e8715b9SGary Mills #define PHY_CDTS_STAT_OK 0x0000 342*5e8715b9SGary Mills #define PHY_CDTS_STAT_SHORT 0x0100 343*5e8715b9SGary Mills #define PHY_CDTS_STAT_OPEN 0x0200 344*5e8715b9SGary Mills #define PHY_CDTS_STAT_INVAL 0x0300 345*5e8715b9SGary Mills #define PHY_CDTS_STAT_MASK 0x0300 346*5e8715b9SGary Mills 347*5e8715b9SGary Mills /* 348*5e8715b9SGary Mills * MAC CFG registers (L1C specific) 349*5e8715b9SGary Mills */ 350*5e8715b9SGary Mills #define L1C_CFG_SINGLE_PAUSE_ENB 0x10000000 351*5e8715b9SGary Mills 352*5e8715b9SGary Mills /* 353*5e8715b9SGary Mills * DMA CFG registers (L1C specific) 354*5e8715b9SGary Mills */ 355*5e8715b9SGary Mills #define DMA_CFG_RD_ENB 0x00000400 356*5e8715b9SGary Mills #define DMA_CFG_WR_ENB 0x00000800 357*5e8715b9SGary Mills #define DMA_CFG_RD_BURST_MASK 0x07 358*5e8715b9SGary Mills #define DMA_CFG_RD_BURST_SHIFT 4 359*5e8715b9SGary Mills #define DMA_CFG_WR_BURST_MASK 0x07 360*5e8715b9SGary Mills #define DMA_CFG_WR_BURST_SHIFT 7 361*5e8715b9SGary Mills #define DMA_CFG_SMB_DIS 0x01000000 362*5e8715b9SGary Mills 363*5e8715b9SGary Mills #define L1C_RD_LEN_MASK 0x0000FFFF 364*5e8715b9SGary Mills #define L1C_RD_LEN_SHIFT 0 365*5e8715b9SGary Mills 366*5e8715b9SGary Mills #define L1C_SRAM_RD_ADDR 0x1500 367*5e8715b9SGary Mills #define L1C_SRAM_RD_LEN 0x1504 368*5e8715b9SGary Mills #define L1C_SRAM_RRD_ADDR 0x1508 369*5e8715b9SGary Mills #define L1C_SRAM_RRD_LEN 0x150C 370*5e8715b9SGary Mills #define L1C_SRAM_TPD_ADDR 0x1510 371*5e8715b9SGary Mills #define L1C_SRAM_TPD_LEN 0x1514 372*5e8715b9SGary Mills #define L1C_SRAM_TRD_ADDR 0x1518 373*5e8715b9SGary Mills #define L1C_SRAM_TRD_LEN 0x151C 374*5e8715b9SGary Mills #define L1C_SRAM_RX_FIFO_ADDR 0x1520 375*5e8715b9SGary Mills #define L1C_SRAM_RX_FIFO_LEN 0x1524 376*5e8715b9SGary Mills #define L1C_SRAM_TX_FIFO_ADDR 0x1528 377*5e8715b9SGary Mills #define L1C_SRAM_TX_FIFO_LEN 0x152C 378*5e8715b9SGary Mills 379*5e8715b9SGary Mills #define L1C_RXQ_CFG_RD_BURST_MASK 0x03f00000 380*5e8715b9SGary Mills #define L1C_RXQ_CFG_RD_BURST_SHIFT 20 381*5e8715b9SGary Mills 382*5e8715b9SGary Mills #define L1C_TXQ_CFG 0x1590 383*5e8715b9SGary Mills #define TXQ_CFG_TPD_FETCH_THRESH_MASK 0x00003F00 384*5e8715b9SGary Mills #define L1C_TXQ_CFG_TPD_BURST_DEFAULT 5 385*5e8715b9SGary Mills #define TXQ_CFG_TPD_FETCH_THRESH_SHIFT 8 386*5e8715b9SGary Mills #define TXQ_CFG_TPD_FETCH_DEFAULT 16 387*5e8715b9SGary Mills 388*5e8715b9SGary Mills #define L1C_TXF_WATER_MARK 0x1598 /* 8 bytes unit */ 389*5e8715b9SGary Mills #define TXF_WATER_MARK_HI_MASK 0x00000FFF 390*5e8715b9SGary Mills #define TXF_WATER_MARK_LO_MASK 0x0FFF0000 391*5e8715b9SGary Mills #define TXF_WATER_MARK_BURST_ENB 0x80000000 392*5e8715b9SGary Mills #define TXF_WATER_MARK_LO_SHIFT 0 393*5e8715b9SGary Mills #define TXF_WATER_MARK_HI_SHIFT 16 394*5e8715b9SGary Mills 395*5e8715b9SGary Mills #define L1C_RD_DMA_CFG 0x15AC 396*5e8715b9SGary Mills #define RD_DMA_CFG_THRESH_MASK 0x00000FFF /* 8 bytes unit */ 397*5e8715b9SGary Mills #define RD_DMA_CFG_TIMER_MASK 0xFFFF0000 398*5e8715b9SGary Mills #define RD_DMA_CFG_THRESH_SHIFT 0 399*5e8715b9SGary Mills #define RD_DMA_CFG_TIMER_SHIFT 16 400*5e8715b9SGary Mills #define RD_DMA_CFG_THRESH_DEFAULT 0x100 401*5e8715b9SGary Mills #define RD_DMA_CFG_TIMER_DEFAULT 0 402*5e8715b9SGary Mills #define RD_DMA_CFG_TICK_USECS 8 403*5e8715b9SGary Mills #define L1C_RD_DMA_CFG_USECS(x) ((x) / RD_DMA_CFG_TICK_USECS) 404*5e8715b9SGary Mills 405*5e8715b9SGary Mills /* CMB DMA Write Threshold Register */ 406*5e8715b9SGary Mills #define L1C_CMB_WR_THRESH 0x15D4 407*5e8715b9SGary Mills #define CMB_WR_THRESH_RRD_MASK 0x000007FF 408*5e8715b9SGary Mills #define CMB_WR_THRESH_TPD_MASK 0x07FF0000 409*5e8715b9SGary Mills #define CMB_WR_THRESH_RRD_SHIFT 0 410*5e8715b9SGary Mills #define CMB_WR_THRESH_RRD_DEFAULT 4 411*5e8715b9SGary Mills #define CMB_WR_THRESH_TPD_SHIFT 16 412*5e8715b9SGary Mills #define CMB_WR_THRESH_TPD_DEFAULT 4 413*5e8715b9SGary Mills 414*5e8715b9SGary Mills /* SMB auto DMA timer register */ 415*5e8715b9SGary Mills #define L1C_SMB_TIMER 0x15E4 416*5e8715b9SGary Mills 417*5e8715b9SGary Mills #define L1C_CSMB_CTRL 0x15D0 418*5e8715b9SGary Mills #define CSMB_CTRL_CMB_KICK 0x00000001 419*5e8715b9SGary Mills #define CSMB_CTRL_SMB_KICK 0x00000002 420*5e8715b9SGary Mills #define CSMB_CTRL_CMB_ENB 0x00000004 421*5e8715b9SGary Mills #define CSMB_CTRL_SMB_ENB 0x00000008 422*5e8715b9SGary Mills 423*5e8715b9SGary Mills /* From Freebsd if_alcreg.h */ 424*5e8715b9SGary Mills #define L1C_INTR_SMB 0x00000001 425*5e8715b9SGary Mills #define L1C_INTR_TIMER 0x00000002 426*5e8715b9SGary Mills #define L1C_INTR_MANUAL_TIMER 0x00000004 427*5e8715b9SGary Mills #define L1C_INTR_RX_FIFO_OFLOW 0x00000008 428*5e8715b9SGary Mills #define L1C_INTR_RD0_UNDERRUN 0x00000010 429*5e8715b9SGary Mills #define L1C_INTR_RD1_UNDERRUN 0x00000020 430*5e8715b9SGary Mills #define L1C_INTR_RD2_UNDERRUN 0x00000040 431*5e8715b9SGary Mills #define L1C_INTR_RD3_UNDERRUN 0x00000080 432*5e8715b9SGary Mills #define L1C_INTR_TX_FIFO_UNDERRUN 0x00000100 433*5e8715b9SGary Mills #define L1C_INTR_DMA_RD_TO_RST 0x00000200 434*5e8715b9SGary Mills #define L1C_INTR_DMA_WR_TO_RST 0x00000400 435*5e8715b9SGary Mills #define L1C_INTR_TX_CREDIT 0x00000800 436*5e8715b9SGary Mills #define L1C_INTR_GPHY 0x00001000 437*5e8715b9SGary Mills #define L1C_INTR_GPHY_LOW_PW 0x00002000 438*5e8715b9SGary Mills #define L1C_INTR_TXQ_TO_RST 0x00004000 439*5e8715b9SGary Mills #define L1C_INTR_TX_PKT 0x00008000 440*5e8715b9SGary Mills #define L1C_INTR_RX_PKT0 0x00010000 441*5e8715b9SGary Mills #define L1C_INTR_RX_PKT1 0x00020000 442*5e8715b9SGary Mills #define L1C_INTR_RX_PKT2 0x00040000 443*5e8715b9SGary Mills #define L1C_INTR_RX_PKT3 0x00080000 444*5e8715b9SGary Mills #define L1C_INTR_MAC_RX 0x00100000 445*5e8715b9SGary Mills #define L1C_INTR_MAC_TX 0x00200000 446*5e8715b9SGary Mills #define L1C_INTR_UNDERRUN 0x00400000 447*5e8715b9SGary Mills #define L1C_INTR_FRAME_ERROR 0x00800000 448*5e8715b9SGary Mills #define L1C_INTR_FRAME_OK 0x01000000 449*5e8715b9SGary Mills #define L1C_INTR_CSUM_ERROR 0x02000000 450*5e8715b9SGary Mills #define L1C_INTR_PHY_LINK_DOWN 0x04000000 451*5e8715b9SGary Mills #define L1C_INTR_DIS_INT 0x80000000 452*5e8715b9SGary Mills 453*5e8715b9SGary Mills #define L1C_INTR_RX_PKT L1C_INTR_RX_PKT0 454*5e8715b9SGary Mills #define L1C_INTR_RD_UNDERRUN L1C_INTR_RD0_UNDERRUN 455*5e8715b9SGary Mills 456*5e8715b9SGary Mills #define L1C_INTRS \ 457*5e8715b9SGary Mills (L1C_INTR_DMA_RD_TO_RST | L1C_INTR_DMA_WR_TO_RST | \ 458*5e8715b9SGary Mills L1C_INTR_TXQ_TO_RST| L1C_INTR_RX_PKT | L1C_INTR_TX_PKT | \ 459*5e8715b9SGary Mills L1C_INTR_RX_FIFO_OFLOW | L1C_INTR_RD_UNDERRUN | \ 460*5e8715b9SGary Mills L1C_INTR_TX_FIFO_UNDERRUN) 461*5e8715b9SGary Mills 462*5e8715b9SGary Mills #define L1C_RXQ_RRD_PAUSE_THRESH 0x15AC 463*5e8715b9SGary Mills #define RXQ_RRD_PAUSE_THRESH_HI_MASK 0x00000FFF 464*5e8715b9SGary Mills #define RXQ_RRD_PAUSE_THRESH_LO_MASK 0x0FFF0000 465*5e8715b9SGary Mills #define RXQ_RRD_PAUSE_THRESH_HI_SHIFT 0 466*5e8715b9SGary Mills #define RXQ_RRD_PAUSE_THRESH_LO_SHIFT 16 467*5e8715b9SGary Mills 468*5e8715b9SGary Mills /* RX/TX count-down timer to trigger CMB-write. */ 469*5e8715b9SGary Mills #define L1C_CMB_WR_TIMER 0x15D8 470*5e8715b9SGary Mills #define CMB_WR_TIMER_RX_MASK 0x0000FFFF 471*5e8715b9SGary Mills #define CMB_WR_TIMER_TX_MASK 0xFFFF0000 472*5e8715b9SGary Mills #define CMB_WR_TIMER_RX_SHIFT 0 473*5e8715b9SGary Mills #define CMB_WR_TIMER_TX_SHIFT 16 474*5e8715b9SGary Mills 475*5e8715b9SGary Mills /* 476*5e8715b9SGary Mills * Useful macros. 477*5e8715b9SGary Mills */ 478*5e8715b9SGary Mills #define L1C_RX_NSEGS(x) \ 479*5e8715b9SGary Mills (((x) & L1C_RRD_NSEGS_MASK) >> L1C_RRD_NSEGS_SHIFT) 480*5e8715b9SGary Mills #define L1C_RX_CONS(x) \ 481*5e8715b9SGary Mills (((x) & L1C_RRD_CONS_MASK) >> L1C_RRD_CONS_SHIFT) 482*5e8715b9SGary Mills #define L1C_RX_CSUM(x) \ 483*5e8715b9SGary Mills (((x) & L1C_RRD_CSUM_MASK) >> L1C_RRD_CSUM_SHIFT) 484*5e8715b9SGary Mills #define L1C_RX_BYTES(x) \ 485*5e8715b9SGary Mills (((x) & L1C_RRD_LEN_MASK) >> L1C_RRD_LEN_SHIFT) 486*5e8715b9SGary Mills 487*5e8715b9SGary Mills 488*5e8715b9SGary Mills #ifdef __cplusplus 489*5e8715b9SGary Mills } 490*5e8715b9SGary Mills #endif 491*5e8715b9SGary Mills 492*5e8715b9SGary Mills #endif /* _ATGE_L1C_REG_H */ 493