1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _ATGE_CMN_REG_H 27 #define _ATGE_CMN_REG_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 #define ATGE_SPI_CTRL 0x200 34 #define SPI_VPD_ENB 0x00002000 35 36 #define PCIE_DEVCTRL 0x0060 /* L1 */ 37 38 /* 39 * Station Address 40 */ 41 #define ATGE_PAR0 0x1488 42 #define ATGE_PAR1 0x148C 43 44 #define ATGE_MASTER_CFG 0x1400 45 #define MASTER_RESET 0x00000001 46 #define MASTER_MTIMER_ENB 0x00000002 47 #define MASTER_ITIMER_ENB 0x00000004 /* L1 */ 48 #define MASTER_IM_TX_TIMER_ENB 0x00000004 /* L1E */ 49 #define MASTER_MANUAL_INT_ENB 0x00000008 50 #define MASTER_IM_RX_TIMER_ENB 0x00000020 51 #define MASTER_INT_RDCLR 0x00000040 52 #define MASTER_LED_MODE 0x00000200 53 #define MASTER_CHIP_REV_MASK 0x00FF0000 54 #define MASTER_CHIP_ID_MASK 0xFF000000 55 #define MASTER_CHIP_REV_SHIFT 16 56 #define MASTER_CHIP_ID_SHIFT 24 57 58 #define ATGE_RESET_TIMEOUT 100 59 60 #define ATGE_IDLE_STATUS 0x1410 61 #define IDLE_STATUS_RXMAC 0x00000001 62 #define IDLE_STATUS_TXMAC 0x00000002 63 #define IDLE_STATUS_RXQ 0x00000004 64 #define IDLE_STATUS_TXQ 0x00000008 65 #define IDLE_STATUS_DMARD 0x00000010 66 #define IDLE_STATUS_DMAWR 0x00000020 67 #define IDLE_STATUS_SMB 0x00000040 68 #define IDLE_STATUS_CMB 0x00000080 69 70 #define ATGE_MAC_CFG 0x1480 71 #define ATGE_CFG_TX_ENB 0x00000001 72 #define ATGE_CFG_RX_ENB 0x00000002 73 #define ATGE_CFG_TX_FC 0x00000004 74 #define ATGE_CFG_RX_FC 0x00000008 75 #define ATGE_CFG_LOOP 0x00000010 76 #define ATGE_CFG_FULL_DUPLEX 0x00000020 77 #define ATGE_CFG_TX_CRC_ENB 0x00000040 78 #define ATGE_CFG_TX_AUTO_PAD 0x00000080 79 #define ATGE_CFG_TX_LENCHK 0x00000100 80 #define ATGE_CFG_RX_JUMBO_ENB 0x00000200 81 #define ATGE_CFG_PREAMBLE_MASK 0x00003C00 82 #define ATGE_CFG_VLAN_TAG_STRIP 0x00004000 83 #define ATGE_CFG_PROMISC 0x00008000 84 #define ATGE_CFG_TX_PAUSE 0x00010000 85 #define ATGE_CFG_SCNT 0x00020000 86 #define ATGE_CFG_SYNC_RST_TX 0x00040000 87 #define ATGE_CFG_SPEED_MASK 0x00300000 88 #define ATGE_CFG_SPEED_10_100 0x00100000 89 #define ATGE_CFG_SPEED_1000 0x00200000 90 #define ATGE_CFG_DBG_TX_BACKOFF 0x00400000 91 #define ATGE_CFG_TX_JUMBO_ENB 0x00800000 92 #define ATGE_CFG_RXCSUM_ENB 0x01000000 93 #define ATGE_CFG_ALLMULTI 0x02000000 94 #define ATGE_CFG_BCAST 0x04000000 95 #define ATGE_CFG_DBG 0x08000000 96 #define ATGE_CFG_PREAMBLE_SHIFT 10 97 #define ATGE_CFG_PREAMBLE_DEFAULT 7 98 99 /* 100 * Interrupt related registers. 101 */ 102 #define ATGE_INTR_MASK 0x1604 103 #define ATGE_INTR_STATUS 0x1600 104 #define INTR_SMB 0x00000001 105 #define INTR_MOD_TIMER 0x00000002 106 #define INTR_MANUAL_TIMER 0x00000004 107 #define INTR_RX_FIFO_OFLOW 0x00000008 108 #define INTR_RD_UNDERRUN 0x00000010 109 #define INTR_RRD_OFLOW 0x00000020 110 #define INTR_TX_FIFO_UNDERRUN 0x00000040 111 #define INTR_LINK_CHG 0x00000080 112 #define INTR_HOST_RD_UNDERRUN 0x00000100 113 #define INTR_HOST_RRD_OFLOW 0x00000200 114 #define INTR_DMA_RD_TO_RST 0x00000400 115 #define INTR_DMA_WR_TO_RST 0x00000800 116 #define INTR_GPHY 0x00001000 117 #define INTR_RX_PKT 0x00010000 118 #define INTR_TX_PKT 0x00020000 119 #define INTR_TX_DMA 0x00040000 120 #define INTR_MAC_RX 0x00400000 121 #define INTR_MAC_TX 0x00800000 122 #define INTR_UNDERRUN 0x01000000 123 #define INTR_FRAME_ERROR 0x02000000 124 #define INTR_FRAME_OK 0x04000000 125 #define INTR_CSUM_ERROR 0x08000000 126 #define INTR_PHY_LINK_DOWN 0x10000000 127 #define INTR_DIS_SM 0x20000000 128 #define INTR_DIS_DMA 0x40000000 129 #define INTR_DIS_INT 0x80000000 130 131 /* L1E intr status */ 132 #define INTR_RX_PKT1 0x00080000 133 #define INTR_RX_PKT2 0x00100000 134 #define INTR_RX_PKT3 0x00200000 135 136 /* L1 intr status */ 137 #define INTR_TX_DMA 0x00040000 138 139 /* 140 * L1E specific errors. We keep it here since some errors are common for 141 * both L1 and L1E chip. 142 * 143 */ 144 #define L1E_INTR_ERRORS \ 145 (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST) 146 147 /* 148 * TXQ CFG registers. 149 */ 150 #define ATGE_TXQ_CFG 0x1580 151 #define TXQ_CFG_TPD_BURST_MASK 0x0000000F 152 #define TXQ_CFG_ENB 0x00000020 153 #define TXQ_CFG_ENHANCED_MODE 0x00000040 154 #define TXQ_CFG_TX_FIFO_BURST_MASK 0xFFFF0000 155 #define TXQ_CFG_TPD_BURST_SHIFT 0 156 #define TXQ_CFG_TPD_BURST_DEFAULT 4 157 #define TXQ_CFG_TX_FIFO_BURST_SHIFT 16 158 #define TXQ_CFG_TX_FIFO_BURST_DEFAULT 256 159 160 /* 161 * RXQ CFG register. 162 */ 163 #define ATGE_RXQ_CFG 0x15A0 164 165 /* 166 * Common registers for DMA CFG. 167 */ 168 #define ATGE_DMA_CFG 0x15C0 169 #define DMA_CFG_IN_ORDER 0x00000001 170 #define DMA_CFG_ENH_ORDER 0x00000002 171 #define DMA_CFG_OUT_ORDER 0x00000004 172 #define DMA_CFG_RCB_64 0x00000000 173 #define DMA_CFG_RCB_128 0x00000008 174 #define DMA_CFG_RD_BURST_128 0x00000000 175 #define DMA_CFG_RD_BURST_256 0x00000010 176 #define DMA_CFG_RD_BURST_512 0x00000020 177 #define DMA_CFG_RD_BURST_1024 0x00000030 178 #define DMA_CFG_RD_BURST_2048 0x00000040 179 #define DMA_CFG_RD_BURST_4096 0x00000050 180 #define DMA_CFG_WR_BURST_128 0x00000000 181 #define DMA_CFG_WR_BURST_256 0x00000080 182 #define DMA_CFG_WR_BURST_512 0x00000100 183 #define DMA_CFG_WR_BURST_1024 0x00000180 184 #define DMA_CFG_WR_BURST_2048 0x00000200 185 #define DMA_CFG_WR_BURST_4096 0x00000280 186 187 /* L1E specific but can go into common regs */ 188 #define DMA_CFG_RXCMB_ENB 0x00200000 189 #define DMA_CFG_RD_DELAY_CNT_DEFAULT 15 190 #define DMA_CFG_RD_DELAY_CNT_SHIFT 11 191 #define DMA_CFG_RD_DELAY_CNT_MASK 0x0000F800 192 #define DMA_CFG_WR_DELAY_CNT_DEFAULT 4 193 #define DMA_CFG_WR_DELAY_CNT_SHIFT 16 194 #define DMA_CFG_WR_DELAY_CNT_MASK 0x000F0000 195 196 /* 197 * Common PHY registers. 198 */ 199 #define ATGE_MDIO 0x1414 200 #define MDIO_DATA_MASK 0x0000FFFF 201 #define MDIO_REG_ADDR_MASK 0x001F0000 202 #define MDIO_OP_READ 0x00200000 203 #define MDIO_OP_WRITE 0x00000000 204 #define MDIO_SUP_PREAMBLE 0x00400000 205 #define MDIO_OP_EXECUTE 0x00800000 206 #define MDIO_CLK_25_4 0x00000000 207 #define MDIO_CLK_25_6 0x02000000 208 #define MDIO_CLK_25_8 0x03000000 209 #define MDIO_CLK_25_10 0x04000000 210 #define MDIO_CLK_25_14 0x05000000 211 #define MDIO_CLK_25_20 0x06000000 212 #define MDIO_CLK_25_28 0x07000000 213 #define MDIO_OP_BUSY 0x08000000 214 #define MDIO_DATA_SHIFT 0 215 #define MDIO_REG_ADDR_SHIFT 16 216 217 #define MDIO_REG_ADDR(x) \ 218 (((x) << MDIO_REG_ADDR_SHIFT) & MDIO_REG_ADDR_MASK) 219 220 #define ATGE_GPHY_CTRL 0x140C /* 16-bits */ 221 #define GPHY_CTRL_RST 0x0000 222 #define GPHY_CTRL_CLR 0x0001 223 #define ATPHY_CDTC 0x16 224 #define PHY_CDTC_ENB 0x0001 225 #define PHY_CDTC_POFF 0x8 226 #define ATPHY_CDTS 0x1C 227 228 229 #define ATGE_PHY_ADDR 0 230 #define ATGE_PHY_STATUS 0x1418 231 #define PHY_TIMEOUT 1000 232 233 #define ATGE_DESC_TPD_CNT 0x155C 234 #define DESC_TPD_CNT_MASK 0x00003FF 235 #define DESC_TPD_CNT_SHIFT 0 236 237 #define ATGE_DMA_BLOCK 0x1534 238 #define DMA_BLOCK_LOAD 0x00000001 239 240 #define ATGE_MBOX 0x15F0 241 #define MBOX_RD_PROD_IDX_MASK 0x000007FF 242 #define MBOX_RRD_CONS_IDX_MASK 0x003FF800 243 #define MBOX_TD_PROD_IDX_MASK 0xFFC00000 244 #define MBOX_RD_PROD_IDX_SHIFT 0 245 #define MBOX_RRD_CONS_IDX_SHIFT 11 246 #define MBOX_TD_PROD_IDX_SHIFT 22 247 248 249 #define ATGE_IPG_IFG_CFG 0x1484 250 #define IPG_IFG_IPGT_MASK 0x0000007F 251 #define IPG_IFG_MIFG_MASK 0x0000FF00 252 #define IPG_IFG_IPG1_MASK 0x007F0000 253 #define IPG_IFG_IPG2_MASK 0x7F000000 254 #define IPG_IFG_IPGT_SHIFT 0 255 #define IPG_IFG_IPGT_DEFAULT 0x60 256 #define IPG_IFG_MIFG_SHIFT 8 257 #define IPG_IFG_MIFG_DEFAULT 0x50 258 #define IPG_IFG_IPG1_SHIFT 16 259 #define IPG_IFG_IPG1_DEFAULT 0x40 260 #define IPG_IFG_IPG2_SHIFT 24 261 #define IPG_IFG_IPG2_DEFAULT 0x60 262 263 /* half-duplex parameter configuration. */ 264 #define ATGE_HDPX_CFG 0x1498 265 #define HDPX_CFG_LCOL_MASK 0x000003FF 266 #define HDPX_CFG_RETRY_MASK 0x0000F000 267 #define HDPX_CFG_EXC_DEF_EN 0x00010000 268 #define HDPX_CFG_NO_BACK_C 0x00020000 269 #define HDPX_CFG_NO_BACK_P 0x00040000 270 #define HDPX_CFG_ABEBE 0x00080000 271 #define HDPX_CFG_ABEBT_MASK 0x00F00000 272 #define HDPX_CFG_JAMIPG_MASK 0x0F000000 273 #define HDPX_CFG_LCOL_SHIFT 0 274 #define HDPX_CFG_LCOL_DEFAULT 0x37 275 #define HDPX_CFG_RETRY_SHIFT 12 276 #define HDPX_CFG_RETRY_DEFAULT 0x0F 277 #define HDPX_CFG_ABEBT_SHIFT 20 278 #define HDPX_CFG_ABEBT_DEFAULT 0x0A 279 #define HDPX_CFG_JAMIPG_SHIFT 24 280 #define HDPX_CFG_JAMIPG_DEFAULT 0x07 281 282 #define ATGE_FRAME_SIZE 0x149C 283 284 #define ATGE_WOL_CFG 0x14A0 285 #define WOL_CFG_PATTERN 0x00000001 286 #define WOL_CFG_PATTERN_ENB 0x00000002 287 #define WOL_CFG_MAGIC 0x00000004 288 #define WOL_CFG_MAGIC_ENB 0x00000008 289 #define WOL_CFG_LINK_CHG 0x00000010 290 #define WOL_CFG_LINK_CHG_ENB 0x00000020 291 #define WOL_CFG_PATTERN_DET 0x00000100 292 #define WOL_CFG_MAGIC_DET 0x00000200 293 #define WOL_CFG_LINK_CHG_DET 0x00000400 294 #define WOL_CFG_CLK_SWITCH_ENB 0x00008000 295 #define WOL_CFG_PATTERN0 0x00010000 296 #define WOL_CFG_PATTERN1 0x00020000 297 #define WOL_CFG_PATTERN2 0x00040000 298 #define WOL_CFG_PATTERN3 0x00080000 299 #define WOL_CFG_PATTERN4 0x00100000 300 #define WOL_CFG_PATTERN5 0x00200000 301 #define WOL_CFG_PATTERN6 0x00400000 302 303 /* WOL pattern length. */ 304 #define ATGE_PATTERN_CFG0 0x14A4 305 #define PATTERN_CFG_0_LEN_MASK 0x0000007F 306 #define PATTERN_CFG_1_LEN_MASK 0x00007F00 307 #define PATTERN_CFG_2_LEN_MASK 0x007F0000 308 #define PATTERN_CFG_3_LEN_MASK 0x7F000000 309 310 #define ATGE_PATTERN_CFG1 0x14A8 311 #define PATTERN_CFG_4_LEN_MASK 0x0000007F 312 #define PATTERN_CFG_5_LEN_MASK 0x00007F00 313 #define PATTERN_CFG_6_LEN_MASK 0x007F0000 314 315 #define ATGE_TICK_USECS 2 316 #define ATGE_USECS(x) ((x) / ATGE_TICK_USECS) 317 318 #define ATGE_INTR_CLR_TIMER 0x140E /* 16-bits */ 319 #define ATGE_IM_TIMER 0x1408 320 #define ATGE_IM_TIMER2 0x140A 321 #define ATGE_IM_TIMER_MIN 0 322 #define ATGE_IM_TIMER_MAX 130000 /* 130 ms */ 323 #define ATGE_IM_TIMER_DEFAULT 100 324 #define ATGE_IM_RX_TIMER_DEFAULT 1 325 #define ATGE_IM_TX_TIMER_DEFAULT 1 326 #define IM_TIMER_TX_SHIFT 0 327 #define IM_TIMER_RX_SHIFT 16 328 329 #define ATGE_DESC_ADDR_HI 0x1540 330 #define ATGE_DESC_RD_ADDR_LO 0x1544 331 #define ATGE_DESC_RRD_ADDR_LO 0x1548 332 #define ATGE_DESC_TPD_ADDR_LO 0x154C 333 #define ATGE_DESC_CMB_ADDR_LO 0x1550 334 #define ATGE_DESC_SMB_ADDR_LO 0x1554 335 #define ATGE_DESC_RRD_RD_CNT 0x1558 336 337 #define ATGE_RXQ_JUMBO_CFG 0x15A4 338 #define RXQ_JUMBO_CFG_SZ_THRESH_SHIFT 0 339 #define RXQ_JUMBO_CFG_SZ_THRESH_MASK 0x000007FF 340 #define RXQ_JUMBO_CFG_LKAH_DEFAULT 0x01 341 #define RXQ_JUMBO_CFG_LKAH_SHIFT 11 342 #define RXQ_JUMBO_CFG_LKAH_MASK 0x00007800 343 #define RXQ_JUMBO_CFG_RRD_TIMER_SHIFT 16 344 #define RXQ_JUMBO_CFG_RRD_TIMER_MASK 0xFFFF0000 345 346 #define ATGE_RXQ_FIFO_PAUSE_THRESH 0x15A8 347 #define RXQ_FIFO_PAUSE_THRESH_LO_MASK 0x00000FFF 348 #define RXQ_FIFO_PAUSE_THRESH_HI_MASK 0x0FFF000 349 #define RXQ_FIFO_PAUSE_THRESH_LO_SHIFT 0 350 #define RXQ_FIFO_PAUSE_THRESH_HI_SHIFT 16 351 352 #define ATGE_RXQ_CFG 0x15A0 353 #define ATGE_TXQ_CFG 0x1580 354 #define RXQ_CFG_ALIGN_32 0x00000000 355 #define RXQ_CFG_ALIGN_64 0x00000001 356 #define RXQ_CFG_ALIGN_128 0x00000002 357 #define RXQ_CFG_ALIGN_256 0x00000003 358 #define RXQ_CFG_QUEUE1_ENB 0x00000010 359 #define RXQ_CFG_QUEUE2_ENB 0x00000020 360 #define RXQ_CFG_QUEUE3_ENB 0x00000040 361 #define RXQ_CFG_IPV6_CSUM_VERIFY 0x00000080 362 #define RXQ_CFG_RSS_HASH_TBL_LEN_MASK 0x0000FF00 363 #define RXQ_CFG_RSS_HASH_IPV4 0x00010000 364 #define RXQ_CFG_RSS_HASH_IPV4_TCP 0x00020000 365 #define RXQ_CFG_RSS_HASH_IPV6 0x00040000 366 #define RXQ_CFG_RSS_HASH_IPV6_TCP 0x00080000 367 #define RXQ_CFG_RSS_MODE_DIS 0x00000000 368 #define RXQ_CFG_RSS_MODE_SQSINT 0x04000000 369 #define RXQ_CFG_RSS_MODE_MQUESINT 0x08000000 370 #define RXQ_CFG_RSS_MODE_MQUEMINT 0x0C000000 371 #define RXQ_CFG_NIP_QUEUE_SEL_TBL 0x10000000 372 #define RXQ_CFG_RSS_HASH_ENB 0x20000000 373 #define RXQ_CFG_CUT_THROUGH_ENB 0x40000000 374 #define RXQ_CFG_ENB 0x80000000 375 #define RXQ_CFG_RSS_HASH_TBL_LEN_SHIFT 8 376 377 /* 64bit multicast hash register. */ 378 #define ATGE_MAR0 0x1490 379 #define ATGE_MAR1 0x1494 380 381 #define ATPHY_DBG_ADDR 0x1D 382 #define ATPHY_DBG_DATA 0x1E 383 384 #define ATGE_TD_EOP 0x00000001 385 #define ATGE_TD_BUFLEN_MASK 0x00003FFF 386 #define ATGE_TD_BUFLEN_SHIFT 0 387 #define ATGE_TX_BYTES(x) \ 388 (((x) << ATGE_TD_BUFLEN_SHIFT) & ATGE_TD_BUFLEN_MASK) 389 390 #define ATGE_ISR_ACK_GPHY 19 391 392 #ifdef __cplusplus 393 } 394 #endif 395 396 #endif /* _ATGE_CMN_REG_H */ 397