11959748cSgd78059 /* 21959748cSgd78059 * Solaris DLPI driver for ethernet cards based on the ADMtek Centaur 31959748cSgd78059 * 41959748cSgd78059 * Copyright (c) 2007 by Garrett D'Amore <garrett@damore.org>. 51959748cSgd78059 * All rights reserved. 61959748cSgd78059 * 71959748cSgd78059 * Redistribution and use in source and binary forms, with or without 81959748cSgd78059 * modification, are permitted provided that the following conditions 91959748cSgd78059 * are met: 101959748cSgd78059 * 1. Redistributions of source code must retain the above copyright 111959748cSgd78059 * notice, this list of conditions and the following disclaimer. 121959748cSgd78059 * 2. Redistributions in binary form must reproduce the above copyright 131959748cSgd78059 * notice, this list of conditions and the following disclaimer in the 141959748cSgd78059 * documentation and/or other materials provided with the distribution. 151959748cSgd78059 * 3. Neither the name of the author nor the names of any co-contributors 161959748cSgd78059 * may be used to endorse or promote products derived from this software 171959748cSgd78059 * without specific prior written permission. 181959748cSgd78059 * 191959748cSgd78059 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS ``AS IS'' 201959748cSgd78059 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 211959748cSgd78059 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 221959748cSgd78059 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 231959748cSgd78059 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 241959748cSgd78059 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 251959748cSgd78059 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 261959748cSgd78059 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 271959748cSgd78059 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 281959748cSgd78059 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 291959748cSgd78059 * POSSIBILITY OF SUCH DAMAGE. 301959748cSgd78059 */ 31*bdb9230aSGarrett D'Amore /* 32*bdb9230aSGarrett D'Amore * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 33*bdb9230aSGarrett D'Amore * Use is subject to license terms. 34*bdb9230aSGarrett D'Amore */ 351959748cSgd78059 361959748cSgd78059 #ifndef _AFE_H 371959748cSgd78059 #define _AFE_H 381959748cSgd78059 391959748cSgd78059 #ifdef __cplusplus 401959748cSgd78059 extern "C" { 411959748cSgd78059 #endif 421959748cSgd78059 431959748cSgd78059 /* 441959748cSgd78059 * Registers and values are here, becuase they can be exported to userland 451959748cSgd78059 * via the AFEIOC_GETCSR and friends ioctls. These are private to this 461959748cSgd78059 * driver and the bundled diagnostic utility, and should not be used by 471959748cSgd78059 * end user application programs. 481959748cSgd78059 */ 491959748cSgd78059 501959748cSgd78059 /* 511959748cSgd78059 * AFE register definitions. 521959748cSgd78059 */ 531959748cSgd78059 /* PCI configuration registers */ 541959748cSgd78059 #define PCI_VID 0x00 /* Loaded vendor ID */ 551959748cSgd78059 #define PCI_DID 0x02 /* Loaded device ID */ 561959748cSgd78059 #define PCI_CMD 0x04 /* Configuration command register */ 571959748cSgd78059 #define PCI_STAT 0x06 /* Configuration status register */ 581959748cSgd78059 #define PCI_RID 0x08 /* Revision ID */ 591959748cSgd78059 #define PCI_CLS 0x0c /* Cache line size */ 601959748cSgd78059 #define PCI_SVID 0x2c /* Subsystem vendor ID */ 611959748cSgd78059 #define PCI_SSID 0x2e /* Subsystem ID */ 621959748cSgd78059 #define PCI_MINGNT 0x3e /* Minimum Grant */ 631959748cSgd78059 #define PCI_MAXLAT 0x3f /* Maximum latency */ 641959748cSgd78059 #define PCI_SIG 0x80 /* Signature of AN983 */ 651959748cSgd78059 #define PCI_PMR0 0xc0 /* Power Management Register 0 */ 661959748cSgd78059 #define PCI_PMR1 0xc4 /* Power Management Register 1 */ 671959748cSgd78059 681959748cSgd78059 /* 691959748cSgd78059 * Bits for PCI command register. 701959748cSgd78059 */ 711959748cSgd78059 #define PCI_CMD_MWIE 0x0010 /* memory write-invalidate enable */ 721959748cSgd78059 #define PCI_CMD_BME 0x0004 /* bus master enable */ 731959748cSgd78059 #define PCI_CMD_MAE 0x0002 /* memory access enable */ 741959748cSgd78059 #define PCI_CMD_IOE 0x0001 /* I/O access enable */ 751959748cSgd78059 761959748cSgd78059 /* 771959748cSgd78059 * Signature values for PCI_SIG 781959748cSgd78059 */ 791959748cSgd78059 #define SIG_AN983 0x09811317 801959748cSgd78059 #define SIG_AN985 0x09851317 811959748cSgd78059 #define SIG_ADM9511 0x69851317 821959748cSgd78059 831959748cSgd78059 /* Ordinary control/status registers */ 841959748cSgd78059 #define CSR_PAR 0x00 /* PCI access register */ 851959748cSgd78059 #define CSR_TDR 0x08 /* Transmit demand register */ 861959748cSgd78059 #define CSR_RDR 0x10 /* Receive demand register */ 871959748cSgd78059 #define CSR_RDB 0x18 /* Receive descriptor base address */ 881959748cSgd78059 #define CSR_TDB 0x20 /* Transmit descriptor base address */ 891959748cSgd78059 #define CSR_SR 0x28 /* Status register */ 901959748cSgd78059 #define CSR_NAR 0x30 /* Network access register */ 911959748cSgd78059 #define CSR_IER 0x38 /* Interrupt enable register */ 921959748cSgd78059 #define CSR_LPC 0x40 /* Lost packet counter */ 931959748cSgd78059 #define CSR_SPR 0x48 /* Serial port register */ 941959748cSgd78059 #define CSR_TIMER 0x58 /* Timer */ 951959748cSgd78059 #define CSR_SR2 0x80 /* Status register 2 */ 961959748cSgd78059 #define CSR_IER2 0x84 /* Interrupt enable register 2 */ 971959748cSgd78059 #define CSR_CR 0x88 /* Command register */ 981959748cSgd78059 #define CSR_PMCSR 0x90 /* Power Management Command and Status */ 991959748cSgd78059 #define CSR_PAR0 0xa4 /* Physical address register 0 */ 1001959748cSgd78059 #define CSR_PAR1 0xa8 /* Physical address register 1 */ 1011959748cSgd78059 #define CSR_MAR0 0xac /* Multicast address hash table register 0 */ 1021959748cSgd78059 #define CSR_MAR1 0xb0 /* Multicast address hash table register 1 */ 1031959748cSgd78059 #define CSR_BMCR 0xb4 /* PHY BMCR (comet only) */ 1041959748cSgd78059 #define CSR_BMSR 0xb8 /* PHY BMSR (comet only) */ 1051959748cSgd78059 #define CSR_PHYIDR1 0xbc /* PHY PHYIDR1 (comet only) */ 1061959748cSgd78059 #define CSR_PHYIDR2 0xc0 /* PHY PHYIDR2 (comet only) */ 1071959748cSgd78059 #define CSR_ANAR 0xc4 /* PHY ANAR (comet only) */ 1081959748cSgd78059 #define CSR_ANLPAR 0xc8 /* PHY ANLPAR (comet only) */ 1091959748cSgd78059 #define CSR_ANER 0xcc /* PHY ANER (comet only) */ 1101959748cSgd78059 #define CSR_XMC 0xd0 /* XCVR mode control (comet only) */ 1111959748cSgd78059 #define CSR_XCIIS 0xd4 /* XCVR config info/int status (comet only) */ 1121959748cSgd78059 #define CSR_XIE 0xd8 /* XCVR interupt enable (comet only) */ 1131959748cSgd78059 #define CSR_OPM 0xfc /* Opmode register (centaur only) */ 1141959748cSgd78059 1151959748cSgd78059 /* 1161959748cSgd78059 * Bits for PCI access register. 1171959748cSgd78059 */ 1181959748cSgd78059 #define PAR_RESET 0x00000001U /* Reset the entire chip */ 1191959748cSgd78059 #define PAR_MWIE 0x01000000U /* PCI memory-write-invalidate */ 1201959748cSgd78059 #define PAR_MRLE 0x00800000U /* PCI memory-read-line */ 1211959748cSgd78059 #define PAR_MRME 0x00200000U /* PCI memory-read-multiple */ 1221959748cSgd78059 #define PAR_TXHIPRI 0x00000002U /* Transmit higher priority */ 1231959748cSgd78059 #define PAR_DESCSKIP 0x0000007cU /* Descriptor skip length in DW */ 1241959748cSgd78059 #define PAR_BIGENDIAN 0x00000080U /* Use big endian data buffers */ 1251959748cSgd78059 #define PAR_TXAUTOPOLL 0x00060000U /* Programmable TX autopoll interval */ 1261959748cSgd78059 #define PAR_RXFIFO_100 0x00009000U /* RX FIFO control, Centaur only */ 1271959748cSgd78059 #define PAR_RXFIFO_10 0x00002800U /* RX FIFO control, Centaur only */ 1281959748cSgd78059 #define PAR_CALIGN_NONE 0x00000000U /* No cache alignment, Comet */ 1291959748cSgd78059 #define PAR_CALIGN_8 0x00004000U /* 8 DW cache alignment, Comet */ 1301959748cSgd78059 #define PAR_CALIGN_16 0x00008000U /* 16 DW cache alignment, Comet */ 1311959748cSgd78059 #define PAR_CALIGN_32 0x0000c000U /* 32 DW cache alignment, Comet */ 1321959748cSgd78059 #define PAR_BURSTLEN 0x00003F00U /* Programmable burst length, Comet */ 1331959748cSgd78059 #define PAR_BURSTUNL 0x00000000U /* Unlimited burst length, Comet */ 1341959748cSgd78059 #define PAR_BURST_1 0x00000100U /* 1 DW burst length, Comet */ 1351959748cSgd78059 #define PAR_BURST_2 0x00000200U /* 2 DW burst length, Comet */ 1361959748cSgd78059 #define PAR_BURST_4 0x00000400U /* 4 DW burst length, Comet */ 1371959748cSgd78059 #define PAR_BURST_8 0x00000800U /* 8 DW burst length, Comet */ 1381959748cSgd78059 #define PAR_BURST_16 0x00001000U /* 16 DW burst length, Comet */ 1391959748cSgd78059 #define PAR_BURST_32 0x00002000U /* 32 DW burst length, Comet */ 1401959748cSgd78059 1411959748cSgd78059 /* 1421959748cSgd78059 * Bits for status register. 1431959748cSgd78059 */ 1441959748cSgd78059 #define SR_BERR_TYPE 0x03800000U /* bus error type */ 1451959748cSgd78059 #define SR_BERR_PARITY 0x00000000U /* parity error */ 1461959748cSgd78059 #define SR_BERR_TARGET_ABORT 0x01000000U /* target abort */ 1471959748cSgd78059 #define SR_BERR_MASTER_ABORT 0x00800000U /* master abort */ 1481959748cSgd78059 #define SR_TX_STATE 0x00700000U /* transmit state */ 1491959748cSgd78059 #define SR_RX_STATE 0x000E0000U /* receive state */ 1501959748cSgd78059 1511959748cSgd78059 /* 1521959748cSgd78059 * Interrupts. These are in IER2 and SR2. Some of them also appear 1531959748cSgd78059 * in SR and IER, but we only use the ADMtek specific IER2 and SR2. 1541959748cSgd78059 */ 1551959748cSgd78059 #define INT_TXEARLY 0x80000000U /* transmit early interrupt */ 1561959748cSgd78059 #define INT_RXEARLY 0x40000000U /* receive early interrupt */ 1571959748cSgd78059 #define INT_LINKCHG 0x20000000U /* link status changed */ 1581959748cSgd78059 #define INT_TXDEFER 0x10000000U /* transmit defer interrupt */ 1591959748cSgd78059 #define INT_PAUSE 0x04000000U /* pause frame received */ 1601959748cSgd78059 #define INT_NORMAL 0x00010000U /* normal interrupt */ 1611959748cSgd78059 #define INT_ABNORMAL 0x00008000U /* abnormal interrupt */ 1621959748cSgd78059 #define INT_BUSERR 0x00002000U /* fatal bus error */ 1631959748cSgd78059 #define INT_TIMER 0x00000800U /* onboard timer */ 1641959748cSgd78059 #define INT_RXJABBER 0x00000200U /* receive watchdog */ 1651959748cSgd78059 #define INT_RXSTOPPED 0x00000100U /* receive stopped */ 1661959748cSgd78059 #define INT_RXNOBUF 0x00000080U /* no rcv descriptor */ 1671959748cSgd78059 #define INT_RXOK 0x00000040U /* receive complete */ 1681959748cSgd78059 #define INT_TXUNDERFLOW 0x00000020U /* transmit underflow */ 1691959748cSgd78059 #define INT_TXJABBER 0x00000008U /* transmit jabber timeout */ 1701959748cSgd78059 #define INT_TXNOBUF 0x00000004U /* no xmt descriptor */ 1711959748cSgd78059 #define INT_TXSTOPPED 0x00000002U /* transmit stopped */ 1721959748cSgd78059 #define INT_TXOK 0x00000001U /* transmit ok interrupt */ 1731959748cSgd78059 1741959748cSgd78059 #define INT_NONE 0x00000000U /* no interrupts */ 1751959748cSgd78059 #define INT_ALL 0xf401abefU /* all interrupts */ 1761959748cSgd78059 #define INT_WANTED (INT_NORMAL | INT_ABNORMAL | \ 1771959748cSgd78059 INT_BUSERR | INT_RXJABBER | \ 1781959748cSgd78059 INT_RXOK | INT_RXNOBUF | \ 1791959748cSgd78059 INT_TIMER | INT_LINKCHG | \ 1801959748cSgd78059 INT_RXSTOPPED | INT_TXSTOPPED | \ 1811959748cSgd78059 INT_TXUNDERFLOW | INT_TXJABBER) 1821959748cSgd78059 1831959748cSgd78059 /* 1841959748cSgd78059 * Bits for network access register. 1851959748cSgd78059 */ 1861959748cSgd78059 #define NAR_TX_ENABLE 0x00002000U /* Enable transmit */ 1871959748cSgd78059 #define NAR_RX_MULTI 0x00000080U /* Receive all multicast packets */ 1881959748cSgd78059 #define NAR_RX_PROMISC 0x00000040U /* Receive any good packet */ 1891959748cSgd78059 #define NAR_RX_BAD 0x00000008U /* Pass bad packets */ 1901959748cSgd78059 #define NAR_RX_ENABLE 0x00000002U /* Enable receive */ 1911959748cSgd78059 #define NAR_TR 0x0000c000U /* Transmit threshold mask */ 1921959748cSgd78059 #define NAR_TR_72 0x00000000U /* 72 B (128 @ 100Mbps) tx thresh */ 1931959748cSgd78059 #define NAR_TR_96 0x00004000U /* 96 B (256 @ 100Mbps) tx thresh */ 1941959748cSgd78059 #define NAR_TR_128 0x00008000U /* 128 B (512 @ 100Mbps) tx thresh */ 1951959748cSgd78059 #define NAR_TR_160 0x0000c000U /* 160 B (1K @ 100Mbsp) tx thresh */ 1961959748cSgd78059 #define NAR_SF 0x00200000U /* store and forward */ 1971959748cSgd78059 #define NAR_HBD 0x00080000U /* Disable SQE heartbeat */ 1981959748cSgd78059 #define NAR_FCOLL 0x00001000U /* force collision */ 1991959748cSgd78059 #define NAR_MODE 0x00000c00U /* mode (loopback, etc.) */ 2001959748cSgd78059 #define NAR_MACLOOP 0x00000400U /* mac loop back */ 2011959748cSgd78059 2021959748cSgd78059 /* 2031959748cSgd78059 * Bits for lost packet counter. 2041959748cSgd78059 */ 2051959748cSgd78059 #define LPC_COUNT 0x0000FFFFU /* Count of missed frames */ 2061959748cSgd78059 #define LPC_OFLOW 0x00010000U /* Counter overflow bit */ 2071959748cSgd78059 2081959748cSgd78059 /* 2091959748cSgd78059 * Bits for CSR_SPR (MII and SROM access) 2101959748cSgd78059 */ 2111959748cSgd78059 #define SPR_MII_DIN 0x00080000U /* MII data input */ 2121959748cSgd78059 #define SPR_MII_CTRL 0x00040000U /* MII management control, 1=read */ 2131959748cSgd78059 #define SPR_MII_DOUT 0x00020000U /* MII data output */ 2141959748cSgd78059 #define SPR_MII_CLOCK 0x00010000U /* MII data clock */ 2151959748cSgd78059 #define SPR_SROM_READ 0x00004000U /* Serial EEPROM read control */ 2161959748cSgd78059 #define SPR_SROM_WRITE 0x00002000U /* Serial EEPROM write control */ 2171959748cSgd78059 #define SPR_SROM_SEL 0x00000800U /* Serial EEPROM select */ 2181959748cSgd78059 #define SPR_SROM_DOUT 0x00000008U /* Serial EEPROM data out */ 2191959748cSgd78059 #define SPR_SROM_DIN 0x00000004U /* Serial EEPROM data in */ 2201959748cSgd78059 #define SPR_SROM_CLOCK 0x00000002U /* Serial EEPROM clock */ 2211959748cSgd78059 #define SPR_SROM_CHIP 0x00000001U /* Serial EEPROM chip select */ 2221959748cSgd78059 #define SROM_ENADDR 0x4 /* Offset of ethernet address */ 2231959748cSgd78059 #define SROM_READCMD 0x6 /* command to read SROM */ 2241959748cSgd78059 2251959748cSgd78059 /* 2261959748cSgd78059 * Bits for CSR_TIMER 2271959748cSgd78059 */ 2281959748cSgd78059 #define TIMER_LOOP 0x00010000U /* continuous operating mode */ 2291959748cSgd78059 #define TIMER_USEC 204 /* usecs per timer count */ 2301959748cSgd78059 2311959748cSgd78059 /* 2321959748cSgd78059 * Bits for CSR_CR 2331959748cSgd78059 */ 234*bdb9230aSGarrett D'Amore #define CR_PAUSE 0x00000020U /* enable pause flow control */ 2351959748cSgd78059 #define CR_TXURAUTOR 0x00000001U /* transmit underrun auto recovery */ 2361959748cSgd78059 2371959748cSgd78059 /* 2381959748cSgd78059 * Bits for XMC (Comet specific) 2391959748cSgd78059 */ 2401959748cSgd78059 #define XMC_LDIS 0x0800 /* long distance 10Base-T cable */ 2411959748cSgd78059 2421959748cSgd78059 /* 2431959748cSgd78059 * Bits for XCIIS (Comet specific) 2441959748cSgd78059 */ 2451959748cSgd78059 #define XCIIS_SPEED 0x0200 /* 100 Mbps mode */ 2461959748cSgd78059 #define XCIIS_DUPLEX 0x0100 /* full duplex mode */ 2471959748cSgd78059 #define XCIIS_FLOWCTL 0x0080 /* flow control support */ 2481959748cSgd78059 #define XCIIS_ANC 0x0040 /* autonegotiation complete */ 2491959748cSgd78059 #define XCIIS_RF 0x0020 /* remote fault detected */ 2501959748cSgd78059 #define XCIIS_LFAIL 0x0010 /* link fail */ 2511959748cSgd78059 #define XCIIS_ANLPAR 0x0008 /* anar received from link partner */ 2521959748cSgd78059 #define XCIIS_PDF 0x0004 /* parallel detection fault */ 2531959748cSgd78059 #define XCIIS_ANPR 0x0002 /* autoneg. page received */ 2541959748cSgd78059 #define XCIIS_REF 0x0001 /* receive error counter full */ 2551959748cSgd78059 2561959748cSgd78059 /* 2571959748cSgd78059 * Bits for XIE (Comet specific) 2581959748cSgd78059 */ 2591959748cSgd78059 #define XIE_ANCE 0x0040 /* aneg complete interrupt enable */ 2601959748cSgd78059 #define XIE_RFE 0x0020 /* remote fault interrupt enable */ 2611959748cSgd78059 #define XIE_LDE 0x0010 /* link fail interrupt enable */ 2621959748cSgd78059 #define XIE_ANAE 0x0008 /* aneg. ack. interrupt enable */ 2631959748cSgd78059 #define XIE_PDFE 0x0004 /* parallel det. fault int. enable */ 2641959748cSgd78059 #define XIE_ANPE 0x0002 /* autoneg. page rec'd int. enable */ 2651959748cSgd78059 #define XIE_REFE 0x0001 /* receive error full int. enable */ 2661959748cSgd78059 2671959748cSgd78059 /* 2681959748cSgd78059 * Centaur 1.1 extensions to MII. 2691959748cSgd78059 */ 2701959748cSgd78059 #define PHY_PILR 0x10 /* an983b 1.1 - polarity/int lvl */ 2711959748cSgd78059 #define PHY_MCR 0x15 /* an983b 1.1 - mode control */ 2721959748cSgd78059 2731959748cSgd78059 #define PILR_NOSQE 0x0800 /* disable 10BaseT SQE */ 2741959748cSgd78059 #define MCR_FIBER 0x0001 /* enable fiber */ 2751959748cSgd78059 2761959748cSgd78059 /* 2771959748cSgd78059 * Bits for Opmode (Centaur specific) 2781959748cSgd78059 */ 2791959748cSgd78059 #define OPM_SPEED 0x80000000U /* 100 Mbps */ 2801959748cSgd78059 #define OPM_DUPLEX 0x40000000U /* full duplex */ 2811959748cSgd78059 #define OPM_LINK 0x20000000U /* link up? */ 2821959748cSgd78059 #define OPM_MODE 0x00000007U /* mode mask */ 2831959748cSgd78059 #define OPM_INTPHY 0x00000007U /* single chip mode, internal PHY */ 2841959748cSgd78059 #define OPM_MACONLY 0x00000004U /* MAC ony mode, external PHY */ 2851959748cSgd78059 2861959748cSgd78059 #ifdef _KERNEL 2871959748cSgd78059 /* 2881959748cSgd78059 * Put exported kernel interfaces here. (There should be none.) 2891959748cSgd78059 */ 2901959748cSgd78059 #endif /* _KERNEL */ 2911959748cSgd78059 2921959748cSgd78059 #ifdef __cplusplus 2931959748cSgd78059 } 2941959748cSgd78059 #endif 2951959748cSgd78059 2961959748cSgd78059 #endif /* _AFE_H */ 297