1 /* 2 * Solaris driver for ethernet cards based on the ADMtek Centaur 3 * 4 * Copyright (c) 2007 by Garrett D'Amore <garrett@damore.org>. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of the author nor the names of any co-contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS ``AS IS'' 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 /* 32 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 33 * Use is subject to license terms. 34 */ 35 36 37 #include <sys/varargs.h> 38 #include <sys/types.h> 39 #include <sys/modctl.h> 40 #include <sys/conf.h> 41 #include <sys/devops.h> 42 #include <sys/stream.h> 43 #include <sys/strsun.h> 44 #include <sys/cmn_err.h> 45 #include <sys/ethernet.h> 46 #include <sys/kmem.h> 47 #include <sys/time.h> 48 #include <sys/crc32.h> 49 #include <sys/miiregs.h> 50 #include <sys/mac.h> 51 #include <sys/mac_ether.h> 52 #include <sys/ddi.h> 53 #include <sys/sunddi.h> 54 #include <sys/vlan.h> 55 56 #include "afe.h" 57 #include "afeimpl.h" 58 59 /* 60 * Driver globals. 61 */ 62 63 /* patchable debug flag ... must not be static! */ 64 #ifdef DEBUG 65 unsigned afe_debug = DWARN; 66 #endif 67 68 /* table of supported devices */ 69 static afe_card_t afe_cards[] = { 70 71 /* 72 * ADMtek Centaur and Comet 73 */ 74 { 0x1317, 0x0981, "ADMtek AL981", MODEL_COMET }, 75 { 0x1317, 0x0985, "ADMtek AN983", MODEL_CENTAUR }, 76 { 0x1317, 0x1985, "ADMtek AN985", MODEL_CENTAUR }, 77 { 0x1317, 0x9511, "ADMtek ADM9511", MODEL_CENTAUR }, 78 { 0x1317, 0x9513, "ADMtek ADM9513", MODEL_CENTAUR }, 79 /* 80 * Accton just relabels other companies' controllers 81 */ 82 { 0x1113, 0x1216, "Accton EN5251", MODEL_CENTAUR }, 83 /* 84 * Models listed here. 85 */ 86 { 0x10b7, 0x9300, "3Com 3CSOHO100B-TX", MODEL_CENTAUR }, 87 { 0x1113, 0xec02, "SMC SMC1244TX", MODEL_CENTAUR }, 88 { 0x10b8, 0x1255, "SMC SMC1255TX", MODEL_CENTAUR }, 89 { 0x111a, 0x1020, "Siemens SpeedStream PCI 10/100", MODEL_CENTAUR }, 90 { 0x1113, 0x1207, "Accton EN1207F", MODEL_CENTAUR }, 91 { 0x1113, 0x2242, "Accton EN2242", MODEL_CENTAUR }, 92 { 0x1113, 0x2220, "Accton EN2220", MODEL_CENTAUR }, 93 { 0x1113, 0x9216, "3M VOL-N100VF+TX", MODEL_CENTAUR }, 94 { 0x1317, 0x0574, "Linksys LNE100TX", MODEL_CENTAUR }, 95 { 0x1317, 0x0570, "Linksys NC100", MODEL_CENTAUR }, 96 { 0x1385, 0x511a, "Netgear FA511", MODEL_CENTAUR }, 97 { 0x13d1, 0xab02, "AboCom FE2500", MODEL_CENTAUR }, 98 { 0x13d1, 0xab03, "AboCom PCM200", MODEL_CENTAUR }, 99 { 0x13d1, 0xab08, "AboCom FE2500MX", MODEL_CENTAUR }, 100 { 0x1414, 0x0001, "Microsoft MN-120", MODEL_CENTAUR }, 101 { 0x16ec, 0x00ed, "U.S. Robotics USR997900", MODEL_CENTAUR }, 102 { 0x1734, 0x100c, "Fujitsu-Siemens D1961", MODEL_CENTAUR }, 103 { 0x1737, 0xab08, "Linksys PCMPC200", MODEL_CENTAUR }, 104 { 0x1737, 0xab09, "Linksys PCM200", MODEL_CENTAUR }, 105 { 0x17b3, 0xab08, "Hawking PN672TX", MODEL_CENTAUR }, 106 }; 107 108 #define ETHERVLANMTU (ETHERMAX + 4) 109 110 /* 111 * Function prototypes 112 */ 113 static int afe_attach(dev_info_t *, ddi_attach_cmd_t); 114 static int afe_detach(dev_info_t *, ddi_detach_cmd_t); 115 static int afe_resume(dev_info_t *); 116 static int afe_m_unicst(void *, const uint8_t *); 117 static int afe_m_multicst(void *, boolean_t, const uint8_t *); 118 static int afe_m_promisc(void *, boolean_t); 119 static mblk_t *afe_m_tx(void *, mblk_t *); 120 static int afe_m_stat(void *, uint_t, uint64_t *); 121 static int afe_m_start(void *); 122 static void afe_m_stop(void *); 123 static int afe_m_getprop(void *, const char *, mac_prop_id_t, uint_t, 124 uint_t, void *, uint_t *); 125 static int afe_m_setprop(void *, const char *, mac_prop_id_t, uint_t, 126 const void *); 127 static unsigned afe_intr(caddr_t); 128 static void afe_startmac(afe_t *); 129 static void afe_stopmac(afe_t *); 130 static void afe_resetrings(afe_t *); 131 static boolean_t afe_initialize(afe_t *); 132 static void afe_startall(afe_t *); 133 static void afe_stopall(afe_t *); 134 static void afe_resetall(afe_t *); 135 static afe_txbuf_t *afe_alloctxbuf(afe_t *); 136 static void afe_destroytxbuf(afe_txbuf_t *); 137 static afe_rxbuf_t *afe_allocrxbuf(afe_t *); 138 static void afe_destroyrxbuf(afe_rxbuf_t *); 139 static boolean_t afe_send(afe_t *, mblk_t *); 140 static int afe_allocrxring(afe_t *); 141 static void afe_freerxring(afe_t *); 142 static int afe_alloctxring(afe_t *); 143 static void afe_freetxring(afe_t *); 144 static void afe_error(dev_info_t *, char *, ...); 145 static void afe_setrxfilt(afe_t *); 146 static uint8_t afe_sromwidth(afe_t *); 147 static uint16_t afe_readsromword(afe_t *, unsigned); 148 static void afe_readsrom(afe_t *, unsigned, unsigned, char *); 149 static void afe_getfactaddr(afe_t *, uchar_t *); 150 static uint8_t afe_miireadbit(afe_t *); 151 static void afe_miiwritebit(afe_t *, uint8_t); 152 static void afe_miitristate(afe_t *); 153 static uint16_t afe_miiread(afe_t *, int, int); 154 static void afe_miiwrite(afe_t *, int, int, uint16_t); 155 static uint16_t afe_miireadgeneral(afe_t *, int, int); 156 static void afe_miiwritegeneral(afe_t *, int, int, uint16_t); 157 static uint16_t afe_miireadcomet(afe_t *, int, int); 158 static void afe_miiwritecomet(afe_t *, int, int, uint16_t); 159 static int afe_getmiibit(afe_t *, uint16_t, uint16_t); 160 static void afe_startphy(afe_t *); 161 static void afe_stopphy(afe_t *); 162 static void afe_reportlink(afe_t *); 163 static void afe_checklink(afe_t *); 164 static void afe_checklinkcomet(afe_t *); 165 static void afe_checklinkcentaur(afe_t *); 166 static void afe_checklinkmii(afe_t *); 167 static void afe_disableinterrupts(afe_t *); 168 static void afe_enableinterrupts(afe_t *); 169 static void afe_reclaim(afe_t *); 170 static mblk_t *afe_receive(afe_t *); 171 172 #ifdef DEBUG 173 static void afe_dprintf(afe_t *, const char *, int, char *, ...); 174 #endif 175 176 #define KIOIP KSTAT_INTR_PTR(afep->afe_intrstat) 177 178 static mac_callbacks_t afe_m_callbacks = { 179 MC_SETPROP | MC_GETPROP, 180 afe_m_stat, 181 afe_m_start, 182 afe_m_stop, 183 afe_m_promisc, 184 afe_m_multicst, 185 afe_m_unicst, 186 afe_m_tx, 187 NULL, /* mc_ioctl */ 188 NULL, /* mc_getcapab */ 189 NULL, /* mc_open */ 190 NULL, /* mc_close */ 191 afe_m_setprop, 192 afe_m_getprop, 193 }; 194 195 196 /* 197 * Stream information 198 */ 199 DDI_DEFINE_STREAM_OPS(afe_devops, nulldev, nulldev, afe_attach, afe_detach, 200 nodev, NULL, D_MP, NULL, ddi_quiesce_not_supported); 201 202 /* 203 * Module linkage information. 204 */ 205 206 static struct modldrv afe_modldrv = { 207 &mod_driverops, /* drv_modops */ 208 "ADMtek Fast Ethernet", /* drv_linkinfo */ 209 &afe_devops /* drv_dev_ops */ 210 }; 211 212 static struct modlinkage afe_modlinkage = { 213 MODREV_1, /* ml_rev */ 214 { &afe_modldrv, NULL } /* ml_linkage */ 215 }; 216 217 /* 218 * Device attributes. 219 */ 220 static ddi_device_acc_attr_t afe_devattr = { 221 DDI_DEVICE_ATTR_V0, 222 DDI_STRUCTURE_LE_ACC, 223 DDI_STRICTORDER_ACC 224 }; 225 226 static ddi_device_acc_attr_t afe_bufattr = { 227 DDI_DEVICE_ATTR_V0, 228 DDI_NEVERSWAP_ACC, 229 DDI_STRICTORDER_ACC 230 }; 231 232 static ddi_dma_attr_t afe_dma_attr = { 233 DMA_ATTR_V0, /* dma_attr_version */ 234 0, /* dma_attr_addr_lo */ 235 0xFFFFFFFFU, /* dma_attr_addr_hi */ 236 0x7FFFFFFFU, /* dma_attr_count_max */ 237 4, /* dma_attr_align */ 238 0x3F, /* dma_attr_burstsizes */ 239 1, /* dma_attr_minxfer */ 240 0xFFFFFFFFU, /* dma_attr_maxxfer */ 241 0xFFFFFFFFU, /* dma_attr_seg */ 242 1, /* dma_attr_sgllen */ 243 1, /* dma_attr_granular */ 244 0 /* dma_attr_flags */ 245 }; 246 247 /* 248 * Tx buffers can be arbitrarily aligned. Additionally, they can 249 * cross a page boundary, so we use the two buffer addresses of the 250 * chip to provide a two-entry scatter-gather list. 251 */ 252 static ddi_dma_attr_t afe_dma_txattr = { 253 DMA_ATTR_V0, /* dma_attr_version */ 254 0, /* dma_attr_addr_lo */ 255 0xFFFFFFFFU, /* dma_attr_addr_hi */ 256 0x7FFFFFFFU, /* dma_attr_count_max */ 257 1, /* dma_attr_align */ 258 0x3F, /* dma_attr_burstsizes */ 259 1, /* dma_attr_minxfer */ 260 0xFFFFFFFFU, /* dma_attr_maxxfer */ 261 0xFFFFFFFFU, /* dma_attr_seg */ 262 2, /* dma_attr_sgllen */ 263 1, /* dma_attr_granular */ 264 0 /* dma_attr_flags */ 265 }; 266 267 /* 268 * Ethernet addresses. 269 */ 270 static uchar_t afe_broadcast[ETHERADDRL] = { 271 0xff, 0xff, 0xff, 0xff, 0xff, 0xff 272 }; 273 274 /* 275 * DDI entry points. 276 */ 277 int 278 _init(void) 279 { 280 int rv; 281 mac_init_ops(&afe_devops, "afe"); 282 if ((rv = mod_install(&afe_modlinkage)) != DDI_SUCCESS) { 283 mac_fini_ops(&afe_devops); 284 } 285 return (rv); 286 } 287 288 int 289 _fini(void) 290 { 291 int rv; 292 if ((rv = mod_remove(&afe_modlinkage)) == DDI_SUCCESS) { 293 mac_fini_ops(&afe_devops); 294 } 295 return (rv); 296 } 297 298 int 299 _info(struct modinfo *modinfop) 300 { 301 return (mod_info(&afe_modlinkage, modinfop)); 302 } 303 304 int 305 afe_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 306 { 307 afe_t *afep; 308 mac_register_t *macp; 309 int inst = ddi_get_instance(dip); 310 ddi_acc_handle_t pci; 311 uint16_t venid; 312 uint16_t devid; 313 uint16_t svid; 314 uint16_t ssid; 315 uint16_t cachesize; 316 afe_card_t *cardp; 317 int i; 318 319 switch (cmd) { 320 case DDI_RESUME: 321 return (afe_resume(dip)); 322 323 case DDI_ATTACH: 324 break; 325 326 default: 327 return (DDI_FAILURE); 328 } 329 330 /* this card is a bus master, reject any slave-only slot */ 331 if (ddi_slaveonly(dip) == DDI_SUCCESS) { 332 afe_error(dip, "slot does not support PCI bus-master"); 333 return (DDI_FAILURE); 334 } 335 /* PCI devices shouldn't generate hilevel interrupts */ 336 if (ddi_intr_hilevel(dip, 0) != 0) { 337 afe_error(dip, "hilevel interrupts not supported"); 338 return (DDI_FAILURE); 339 } 340 if (pci_config_setup(dip, &pci) != DDI_SUCCESS) { 341 afe_error(dip, "unable to setup PCI config handle"); 342 return (DDI_FAILURE); 343 } 344 345 venid = pci_config_get16(pci, PCI_VID); 346 devid = pci_config_get16(pci, PCI_DID); 347 svid = pci_config_get16(pci, PCI_SVID); 348 ssid = pci_config_get16(pci, PCI_SSID); 349 350 /* 351 * Note: ADMtek boards seem to misprogram themselves with bogus 352 * timings, which do not seem to work properly on SPARC. We 353 * reprogram them zero (but only if they appear to be broken), 354 * which seems to at least work. Its unclear that this is a 355 * legal or wise practice to me, but it certainly works better 356 * than the original values. (I would love to hear 357 * suggestions for better values, or a better strategy.) 358 */ 359 if ((pci_config_get8(pci, PCI_MINGNT) == 0xff) && 360 (pci_config_get8(pci, PCI_MAXLAT) == 0xff)) { 361 pci_config_put8(pci, PCI_MINGNT, 0); 362 pci_config_put8(pci, PCI_MAXLAT, 0); 363 } 364 365 /* 366 * the last entry in the card table matches every possible 367 * card, so the for-loop always terminates properly. 368 */ 369 cardp = NULL; 370 for (i = 0; i < (sizeof (afe_cards) / sizeof (afe_card_t)); i++) { 371 if ((venid == afe_cards[i].card_venid) && 372 (devid == afe_cards[i].card_devid)) { 373 cardp = &afe_cards[i]; 374 } 375 if ((svid == afe_cards[i].card_venid) && 376 (ssid == afe_cards[i].card_devid)) { 377 cardp = &afe_cards[i]; 378 break; 379 } 380 } 381 382 if (cardp == NULL) { 383 pci_config_teardown(&pci); 384 afe_error(dip, "Unable to identify PCI card"); 385 return (DDI_FAILURE); 386 } 387 388 if (ddi_prop_update_string(DDI_DEV_T_NONE, dip, "model", 389 cardp->card_cardname) != DDI_PROP_SUCCESS) { 390 pci_config_teardown(&pci); 391 afe_error(dip, "Unable to create model property"); 392 return (DDI_FAILURE); 393 } 394 395 /* 396 * Grab the PCI cachesize -- we use this to program the 397 * cache-optimization bus access bits. 398 */ 399 cachesize = pci_config_get8(pci, PCI_CLS); 400 401 /* this cannot fail */ 402 afep = kmem_zalloc(sizeof (afe_t), KM_SLEEP); 403 ddi_set_driver_private(dip, afep); 404 405 /* get the interrupt block cookie */ 406 if (ddi_get_iblock_cookie(dip, 0, &afep->afe_icookie) != DDI_SUCCESS) { 407 afe_error(dip, "ddi_get_iblock_cookie failed"); 408 pci_config_teardown(&pci); 409 kmem_free(afep, sizeof (afe_t)); 410 return (DDI_FAILURE); 411 } 412 413 afep->afe_dip = dip; 414 afep->afe_cardp = cardp; 415 afep->afe_phyaddr = -1; 416 afep->afe_cachesize = cachesize; 417 418 /* default properties */ 419 afep->afe_adv_aneg = !!ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0, 420 "adv_autoneg_cap", 1); 421 afep->afe_adv_100T4 = !!ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0, 422 "adv_100T4_cap", 1); 423 afep->afe_adv_100fdx = !!ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0, 424 "adv_100fdx_cap", 1); 425 afep->afe_adv_100hdx = !!ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0, 426 "adv_100hdx_cap", 1); 427 afep->afe_adv_10fdx = !!ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0, 428 "adv_10fdx_cap", 1); 429 afep->afe_adv_10hdx = !!ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0, 430 "adv_10hdx_cap", 1); 431 432 afep->afe_forcefiber = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0, 433 "fiber", 0); 434 435 DBG(DPCI, "PCI vendor id = %x", venid); 436 DBG(DPCI, "PCI device id = %x", devid); 437 DBG(DPCI, "PCI cachesize = %d", cachesize); 438 DBG(DPCI, "PCI COMM = %x", pci_config_get8(pci, PCI_CMD)); 439 DBG(DPCI, "PCI STAT = %x", pci_config_get8(pci, PCI_STAT)); 440 441 mutex_init(&afep->afe_xmtlock, NULL, MUTEX_DRIVER, afep->afe_icookie); 442 mutex_init(&afep->afe_intrlock, NULL, MUTEX_DRIVER, afep->afe_icookie); 443 444 /* 445 * Enable bus master, IO space, and memory space accesses. 446 */ 447 pci_config_put16(pci, PCI_CMD, 448 pci_config_get16(pci, PCI_CMD) | PCI_CMD_BME | PCI_CMD_MAE); 449 450 /* we're done with this now, drop it */ 451 pci_config_teardown(&pci); 452 453 /* 454 * Initialize interrupt kstat. This should not normally fail, since 455 * we don't use a persistent stat. We do it this way to avoid having 456 * to test for it at run time on the hot path. 457 */ 458 afep->afe_intrstat = kstat_create("afe", inst, "intr", "controller", 459 KSTAT_TYPE_INTR, 1, 0); 460 if (afep->afe_intrstat == NULL) { 461 afe_error(dip, "kstat_create failed"); 462 goto failed; 463 } 464 kstat_install(afep->afe_intrstat); 465 466 /* 467 * Map in the device registers. 468 */ 469 if (ddi_regs_map_setup(dip, 1, (caddr_t *)&afep->afe_regs, 470 0, 0, &afe_devattr, &afep->afe_regshandle)) { 471 afe_error(dip, "ddi_regs_map_setup failed"); 472 goto failed; 473 } 474 475 /* 476 * Allocate DMA resources (descriptor rings and buffers). 477 */ 478 if ((afe_allocrxring(afep) != DDI_SUCCESS) || 479 (afe_alloctxring(afep) != DDI_SUCCESS)) { 480 afe_error(dip, "unable to allocate DMA resources"); 481 goto failed; 482 } 483 484 /* Initialize the chip. */ 485 mutex_enter(&afep->afe_intrlock); 486 mutex_enter(&afep->afe_xmtlock); 487 if (!afe_initialize(afep)) { 488 mutex_exit(&afep->afe_xmtlock); 489 mutex_exit(&afep->afe_intrlock); 490 goto failed; 491 } 492 mutex_exit(&afep->afe_xmtlock); 493 mutex_exit(&afep->afe_intrlock); 494 495 /* Determine the number of address bits to our EEPROM. */ 496 afep->afe_sromwidth = afe_sromwidth(afep); 497 498 /* 499 * Get the factory ethernet address. This becomes the current 500 * ethernet address (it can be overridden later via ifconfig). 501 */ 502 afe_getfactaddr(afep, afep->afe_curraddr); 503 afep->afe_promisc = B_FALSE; 504 505 /* make sure we add configure the initial filter */ 506 (void) afe_m_unicst(afep, afep->afe_curraddr); 507 (void) afe_m_multicst(afep, B_TRUE, afe_broadcast); 508 509 /* 510 * Establish interrupt handler. 511 */ 512 if (ddi_add_intr(dip, 0, NULL, NULL, afe_intr, (caddr_t)afep) != 513 DDI_SUCCESS) { 514 afe_error(dip, "unable to add interrupt"); 515 goto failed; 516 } 517 518 /* TODO: do the power management stuff */ 519 520 if ((macp = mac_alloc(MAC_VERSION)) == NULL) { 521 afe_error(dip, "mac_alloc failed"); 522 goto failed; 523 } 524 525 macp->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 526 macp->m_driver = afep; 527 macp->m_dip = dip; 528 macp->m_src_addr = afep->afe_curraddr; 529 macp->m_callbacks = &afe_m_callbacks; 530 macp->m_min_sdu = 0; 531 macp->m_max_sdu = ETHERMTU; 532 macp->m_margin = VLAN_TAGSZ; 533 534 if (mac_register(macp, &afep->afe_mh) == DDI_SUCCESS) { 535 mac_free(macp); 536 return (DDI_SUCCESS); 537 } 538 539 /* failed to register with MAC */ 540 mac_free(macp); 541 failed: 542 if (afep->afe_icookie != NULL) { 543 ddi_remove_intr(dip, 0, afep->afe_icookie); 544 } 545 if (afep->afe_intrstat) { 546 kstat_delete(afep->afe_intrstat); 547 } 548 mutex_destroy(&afep->afe_intrlock); 549 mutex_destroy(&afep->afe_xmtlock); 550 551 afe_freerxring(afep); 552 afe_freetxring(afep); 553 554 if (afep->afe_regshandle != NULL) { 555 ddi_regs_map_free(&afep->afe_regshandle); 556 } 557 kmem_free(afep, sizeof (afe_t)); 558 return (DDI_FAILURE); 559 } 560 561 int 562 afe_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 563 { 564 afe_t *afep; 565 566 afep = ddi_get_driver_private(dip); 567 if (afep == NULL) { 568 afe_error(dip, "no soft state in detach!"); 569 return (DDI_FAILURE); 570 } 571 572 switch (cmd) { 573 case DDI_DETACH: 574 575 if (mac_unregister(afep->afe_mh) != 0) { 576 return (DDI_FAILURE); 577 } 578 579 /* make sure hardware is quiesced */ 580 mutex_enter(&afep->afe_intrlock); 581 mutex_enter(&afep->afe_xmtlock); 582 afep->afe_flags &= ~AFE_RUNNING; 583 afe_stopall(afep); 584 mutex_exit(&afep->afe_xmtlock); 585 mutex_exit(&afep->afe_intrlock); 586 587 /* clean up and shut down device */ 588 ddi_remove_intr(dip, 0, afep->afe_icookie); 589 590 /* clean up kstats */ 591 kstat_delete(afep->afe_intrstat); 592 593 ddi_prop_remove_all(dip); 594 595 /* free up any left over buffers or DMA resources */ 596 afe_freerxring(afep); 597 afe_freetxring(afep); 598 599 ddi_regs_map_free(&afep->afe_regshandle); 600 mutex_destroy(&afep->afe_intrlock); 601 mutex_destroy(&afep->afe_xmtlock); 602 603 kmem_free(afep, sizeof (afe_t)); 604 return (DDI_SUCCESS); 605 606 case DDI_SUSPEND: 607 /* quiesce the hardware */ 608 mutex_enter(&afep->afe_intrlock); 609 mutex_enter(&afep->afe_xmtlock); 610 afep->afe_flags |= AFE_SUSPENDED; 611 afe_stopall(afep); 612 mutex_exit(&afep->afe_xmtlock); 613 mutex_exit(&afep->afe_intrlock); 614 return (DDI_SUCCESS); 615 default: 616 return (DDI_FAILURE); 617 } 618 } 619 620 int 621 afe_resume(dev_info_t *dip) 622 { 623 afe_t *afep; 624 625 if ((afep = ddi_get_driver_private(dip)) == NULL) { 626 return (DDI_FAILURE); 627 } 628 629 mutex_enter(&afep->afe_intrlock); 630 mutex_enter(&afep->afe_xmtlock); 631 632 afep->afe_flags &= ~AFE_SUSPENDED; 633 634 /* re-initialize chip */ 635 if (!afe_initialize(afep)) { 636 afe_error(afep->afe_dip, "unable to resume chip!"); 637 afep->afe_flags |= AFE_SUSPENDED; 638 mutex_exit(&afep->afe_intrlock); 639 mutex_exit(&afep->afe_xmtlock); 640 return (DDI_SUCCESS); 641 } 642 643 /* start the chip */ 644 if (afep->afe_flags & AFE_RUNNING) { 645 afe_startall(afep); 646 } 647 648 /* drop locks */ 649 mutex_exit(&afep->afe_xmtlock); 650 mutex_exit(&afep->afe_intrlock); 651 652 return (DDI_SUCCESS); 653 } 654 655 void 656 afe_setrxfilt(afe_t *afep) 657 { 658 unsigned rxen, pa0, pa1; 659 660 if (afep->afe_flags & AFE_SUSPENDED) { 661 /* don't touch a suspended interface */ 662 return; 663 } 664 665 rxen = GETCSR(afep, CSR_NAR) & NAR_RX_ENABLE; 666 667 /* stop receiver */ 668 if (rxen) { 669 afe_stopmac(afep); 670 } 671 672 /* program promiscuous mode */ 673 if (afep->afe_promisc) 674 SETBIT(afep, CSR_NAR, NAR_RX_PROMISC); 675 else 676 CLRBIT(afep, CSR_NAR, NAR_RX_PROMISC); 677 678 /* program mac address */ 679 pa0 = (afep->afe_curraddr[3] << 24) | (afep->afe_curraddr[2] << 16) | 680 (afep->afe_curraddr[1] << 8) | afep->afe_curraddr[0]; 681 pa1 = (afep->afe_curraddr[5] << 8) | afep->afe_curraddr[4]; 682 683 DBG(DMACID, "programming PAR0 with %x", pa0); 684 DBG(DMACID, "programming PAR1 with %x", pa1); 685 PUTCSR(afep, CSR_PAR0, pa0); 686 PUTCSR(afep, CSR_PAR1, pa1); 687 if (rxen) { 688 SETBIT(afep, CSR_NAR, rxen); 689 } 690 691 DBG(DMACID, "programming MAR0 = %x", afep->afe_mctab[0]); 692 DBG(DMACID, "programming MAR1 = %x", afep->afe_mctab[1]); 693 694 /* program multicast filter */ 695 if (AFE_MODEL(afep) == MODEL_COMET) { 696 if (afep->afe_mctab[0] || afep->afe_mctab[1]) { 697 SETBIT(afep, CSR_NAR, NAR_RX_MULTI); 698 } else { 699 CLRBIT(afep, CSR_NAR, NAR_RX_MULTI); 700 } 701 } else { 702 CLRBIT(afep, CSR_NAR, NAR_RX_MULTI); 703 PUTCSR(afep, CSR_MAR0, afep->afe_mctab[0]); 704 PUTCSR(afep, CSR_MAR1, afep->afe_mctab[1]); 705 } 706 707 /* restart receiver */ 708 if (rxen) { 709 afe_startmac(afep); 710 } 711 } 712 713 int 714 afe_m_multicst(void *arg, boolean_t add, const uint8_t *macaddr) 715 { 716 afe_t *afep = arg; 717 int index; 718 uint32_t crc; 719 uint32_t bit; 720 uint32_t newval, oldval; 721 722 CRC32(crc, macaddr, ETHERADDRL, -1U, crc32_table); 723 crc %= AFE_MCHASH; 724 725 /* bit within a 32-bit word */ 726 index = crc / 32; 727 bit = (1 << (crc % 32)); 728 729 mutex_enter(&afep->afe_intrlock); 730 mutex_enter(&afep->afe_xmtlock); 731 newval = oldval = afep->afe_mctab[index]; 732 733 if (add) { 734 afep->afe_mccount[crc]++; 735 if (afep->afe_mccount[crc] == 1) 736 newval |= bit; 737 } else { 738 afep->afe_mccount[crc]--; 739 if (afep->afe_mccount[crc] == 0) 740 newval &= ~bit; 741 } 742 if (newval != oldval) { 743 afep->afe_mctab[index] = newval; 744 afe_setrxfilt(afep); 745 } 746 747 mutex_exit(&afep->afe_xmtlock); 748 mutex_exit(&afep->afe_intrlock); 749 750 return (0); 751 } 752 753 int 754 afe_m_promisc(void *arg, boolean_t on) 755 { 756 afe_t *afep = arg; 757 758 /* exclusive access to the card while we reprogram it */ 759 mutex_enter(&afep->afe_intrlock); 760 mutex_enter(&afep->afe_xmtlock); 761 /* save current promiscuous mode state for replay in resume */ 762 afep->afe_promisc = on; 763 764 afe_setrxfilt(afep); 765 mutex_exit(&afep->afe_xmtlock); 766 mutex_exit(&afep->afe_intrlock); 767 768 return (0); 769 } 770 771 int 772 afe_m_unicst(void *arg, const uint8_t *macaddr) 773 { 774 afe_t *afep = arg; 775 776 /* exclusive access to the card while we reprogram it */ 777 mutex_enter(&afep->afe_intrlock); 778 mutex_enter(&afep->afe_xmtlock); 779 780 bcopy(macaddr, afep->afe_curraddr, ETHERADDRL); 781 afe_setrxfilt(afep); 782 783 mutex_exit(&afep->afe_xmtlock); 784 mutex_exit(&afep->afe_intrlock); 785 786 return (0); 787 } 788 789 mblk_t * 790 afe_m_tx(void *arg, mblk_t *mp) 791 { 792 afe_t *afep = arg; 793 mblk_t *nmp; 794 795 mutex_enter(&afep->afe_xmtlock); 796 797 if (afep->afe_flags & AFE_SUSPENDED) { 798 while ((nmp = mp) != NULL) { 799 afep->afe_carrier_errors++; 800 mp = mp->b_next; 801 freemsg(nmp); 802 } 803 mutex_exit(&afep->afe_xmtlock); 804 return (NULL); 805 } 806 807 while (mp != NULL) { 808 nmp = mp->b_next; 809 mp->b_next = NULL; 810 811 if (!afe_send(afep, mp)) { 812 mp->b_next = nmp; 813 break; 814 } 815 mp = nmp; 816 } 817 mutex_exit(&afep->afe_xmtlock); 818 819 return (mp); 820 } 821 822 /* 823 * Hardware management. 824 */ 825 static boolean_t 826 afe_initialize(afe_t *afep) 827 { 828 int i; 829 unsigned val; 830 uint32_t par, nar; 831 832 ASSERT(mutex_owned(&afep->afe_intrlock)); 833 ASSERT(mutex_owned(&afep->afe_xmtlock)); 834 835 DBG(DCHATTY, "resetting!"); 836 SETBIT(afep, CSR_PAR, PAR_RESET); 837 for (i = 1; i < 10; i++) { 838 drv_usecwait(5); 839 val = GETCSR(afep, CSR_PAR); 840 if (!(val & PAR_RESET)) { 841 break; 842 } 843 } 844 if (i == 10) { 845 afe_error(afep->afe_dip, "timed out waiting for reset!"); 846 return (B_FALSE); 847 } 848 849 /* 850 * Updated Centaur data sheets show that the Comet and Centaur are 851 * alike here (contrary to earlier versions of the data sheet). 852 */ 853 /* XXX:? chip problems */ 854 /* par = PAR_MRLE | PAR_MRME | PAR_MWIE; */ 855 par = 0; 856 switch (afep->afe_cachesize) { 857 case 8: 858 par |= PAR_CALIGN_8 | PAR_BURST_8; 859 break; 860 case 16: 861 par |= PAR_CALIGN_16 | PAR_BURST_16; 862 break; 863 case 32: 864 par |= PAR_CALIGN_32 | PAR_BURST_32; 865 break; 866 default: 867 par |= PAR_BURST_32; 868 par &= ~(PAR_MWIE | PAR_MRLE | PAR_MRME); 869 break; 870 871 } 872 873 PUTCSR(afep, CSR_PAR, par); 874 875 /* enable transmit underrun auto-recovery */ 876 SETBIT(afep, CSR_CR, CR_TXURAUTOR); 877 878 afe_resetrings(afep); 879 880 /* clear the lost packet counter (cleared on read) */ 881 (void) GETCSR(afep, CSR_LPC); 882 883 nar = GETCSR(afep, CSR_NAR); 884 nar &= ~NAR_TR; /* clear tx threshold */ 885 nar |= NAR_SF; /* store-and-forward */ 886 nar |= NAR_HBD; /* disable SQE test */ 887 PUTCSR(afep, CSR_NAR, nar); 888 889 afe_setrxfilt(afep); 890 891 return (B_TRUE); 892 } 893 894 /* 895 * Serial EEPROM access - inspired by the FreeBSD implementation. 896 */ 897 898 uint8_t 899 afe_sromwidth(afe_t *afep) 900 { 901 int i; 902 uint32_t eeread; 903 uint8_t addrlen = 8; 904 905 eeread = SPR_SROM_READ | SPR_SROM_SEL | SPR_SROM_CHIP; 906 907 PUTCSR(afep, CSR_SPR, eeread & ~SPR_SROM_CHIP); 908 drv_usecwait(1); 909 PUTCSR(afep, CSR_SPR, eeread); 910 911 /* command bits first */ 912 for (i = 4; i != 0; i >>= 1) { 913 unsigned val = (SROM_READCMD & i) ? SPR_SROM_DIN : 0; 914 915 PUTCSR(afep, CSR_SPR, eeread | val); 916 drv_usecwait(1); 917 PUTCSR(afep, CSR_SPR, eeread | val | SPR_SROM_CLOCK); 918 drv_usecwait(1); 919 } 920 921 PUTCSR(afep, CSR_SPR, eeread); 922 923 for (addrlen = 1; addrlen <= 12; addrlen++) { 924 PUTCSR(afep, CSR_SPR, eeread | SPR_SROM_CLOCK); 925 drv_usecwait(1); 926 if (!(GETCSR(afep, CSR_SPR) & SPR_SROM_DOUT)) { 927 PUTCSR(afep, CSR_SPR, eeread); 928 drv_usecwait(1); 929 break; 930 } 931 PUTCSR(afep, CSR_SPR, eeread); 932 drv_usecwait(1); 933 } 934 935 /* turn off accesses to the EEPROM */ 936 PUTCSR(afep, CSR_SPR, eeread &~ SPR_SROM_CHIP); 937 938 DBG(DSROM, "detected srom width = %d bits", addrlen); 939 940 return ((addrlen < 4 || addrlen > 12) ? 6 : addrlen); 941 } 942 943 /* 944 * The words in EEPROM are stored in little endian order. We 945 * shift bits out in big endian order, though. This requires 946 * a byte swap on some platforms. 947 */ 948 uint16_t 949 afe_readsromword(afe_t *afep, unsigned romaddr) 950 { 951 int i; 952 uint16_t word = 0; 953 uint16_t retval; 954 int eeread; 955 uint8_t addrlen; 956 int readcmd; 957 uchar_t *ptr; 958 959 eeread = SPR_SROM_READ | SPR_SROM_SEL | SPR_SROM_CHIP; 960 addrlen = afep->afe_sromwidth; 961 readcmd = (SROM_READCMD << addrlen) | romaddr; 962 963 if (romaddr >= (1 << addrlen)) { 964 /* too big to fit! */ 965 return (0); 966 } 967 968 PUTCSR(afep, CSR_SPR, eeread & ~SPR_SROM_CHIP); 969 PUTCSR(afep, CSR_SPR, eeread); 970 971 /* command and address bits */ 972 for (i = 4 + addrlen; i >= 0; i--) { 973 short val = (readcmd & (1 << i)) ? SPR_SROM_DIN : 0; 974 975 PUTCSR(afep, CSR_SPR, eeread | val); 976 drv_usecwait(1); 977 PUTCSR(afep, CSR_SPR, eeread | val | SPR_SROM_CLOCK); 978 drv_usecwait(1); 979 } 980 981 PUTCSR(afep, CSR_SPR, eeread); 982 983 for (i = 0; i < 16; i++) { 984 PUTCSR(afep, CSR_SPR, eeread | SPR_SROM_CLOCK); 985 drv_usecwait(1); 986 word <<= 1; 987 if (GETCSR(afep, CSR_SPR) & SPR_SROM_DOUT) { 988 word |= 1; 989 } 990 PUTCSR(afep, CSR_SPR, eeread); 991 drv_usecwait(1); 992 } 993 994 /* turn off accesses to the EEPROM */ 995 PUTCSR(afep, CSR_SPR, eeread &~ SPR_SROM_CHIP); 996 997 /* 998 * Fix up the endianness thing. Note that the values 999 * are stored in little endian format on the SROM. 1000 */ 1001 ptr = (uchar_t *)&word; 1002 retval = (ptr[1] << 8) | ptr[0]; 1003 return (retval); 1004 } 1005 1006 void 1007 afe_readsrom(afe_t *afep, unsigned romaddr, unsigned len, char *dest) 1008 { 1009 int i; 1010 uint16_t word; 1011 uint16_t *ptr = (uint16_t *)((void *)dest); 1012 for (i = 0; i < len; i++) { 1013 word = afe_readsromword(afep, romaddr + i); 1014 *ptr = word; 1015 ptr++; 1016 } 1017 } 1018 1019 void 1020 afe_getfactaddr(afe_t *afep, uchar_t *eaddr) 1021 { 1022 afe_readsrom(afep, SROM_ENADDR, ETHERADDRL / 2, (char *)eaddr); 1023 1024 DBG(DMACID, 1025 "factory ethernet address = %02x:%02x:%02x:%02x:%02x:%02x", 1026 eaddr[0], eaddr[1], eaddr[2], eaddr[3], eaddr[4], eaddr[5]); 1027 } 1028 1029 /* 1030 * MII management. 1031 */ 1032 void 1033 afe_startphy(afe_t *afep) 1034 { 1035 unsigned phyaddr; 1036 unsigned bmcr; 1037 unsigned bmsr; 1038 unsigned anar; 1039 unsigned phyidr1; 1040 unsigned phyidr2; 1041 unsigned nosqe = 0; 1042 int retries; 1043 int fiber; 1044 int cnt; 1045 1046 /* ADMtek devices just use the PHY at address 1 */ 1047 afep->afe_phyaddr = phyaddr = 1; 1048 1049 phyidr1 = afe_miiread(afep, phyaddr, MII_PHYIDH); 1050 phyidr2 = afe_miiread(afep, phyaddr, MII_PHYIDL); 1051 if ((phyidr1 == 0x0022) && 1052 ((phyidr2 & 0xfff0) == 0x5410)) { 1053 nosqe = 1; 1054 /* only 983B has fiber support */ 1055 afep->afe_flags |= AFE_HASFIBER; 1056 } 1057 afep->afe_phyid = (phyidr1 << 16) | phyidr2; 1058 1059 DBG(DPHY, "phy at %d: %x,%x", phyaddr, phyidr1, phyidr2); 1060 DBG(DPHY, "bmsr = %x", afe_miiread(afep, 1061 afep->afe_phyaddr, MII_STATUS)); 1062 DBG(DPHY, "anar = %x", afe_miiread(afep, 1063 afep->afe_phyaddr, MII_AN_ADVERT)); 1064 DBG(DPHY, "anlpar = %x", afe_miiread(afep, 1065 afep->afe_phyaddr, MII_AN_LPABLE)); 1066 DBG(DPHY, "aner = %x", afe_miiread(afep, 1067 afep->afe_phyaddr, MII_AN_EXPANSION)); 1068 1069 DBG(DPHY, "resetting phy"); 1070 1071 /* we reset the phy block */ 1072 afe_miiwrite(afep, phyaddr, MII_CONTROL, MII_CONTROL_RESET); 1073 /* 1074 * wait for it to complete -- 500usec is still to short to 1075 * bother getting the system clock involved. 1076 */ 1077 drv_usecwait(500); 1078 for (retries = 0; retries < 10; retries++) { 1079 if (afe_miiread(afep, phyaddr, MII_CONTROL) & 1080 MII_CONTROL_RESET) { 1081 drv_usecwait(500); 1082 continue; 1083 } 1084 break; 1085 } 1086 if (retries == 100) { 1087 afe_error(afep->afe_dip, "timeout waiting on phy to reset"); 1088 return; 1089 } 1090 1091 DBG(DPHY, "phy reset complete"); 1092 1093 bmsr = afe_miiread(afep, phyaddr, MII_STATUS); 1094 anar = afe_miiread(afep, phyaddr, MII_AN_ADVERT); 1095 1096 anar &= ~(MII_ABILITY_100BASE_T4 | 1097 MII_ABILITY_100BASE_TX_FD | MII_ABILITY_100BASE_TX | 1098 MII_ABILITY_10BASE_T_FD | MII_ABILITY_10BASE_T); 1099 1100 fiber = 0; 1101 1102 /* if fiber is being forced, and device supports fiber... */ 1103 if (afep->afe_flags & AFE_HASFIBER) { 1104 1105 uint16_t mcr; 1106 1107 DBG(DPHY, "device supports 100BaseFX"); 1108 mcr = afe_miiread(afep, phyaddr, PHY_MCR); 1109 switch (afep->afe_forcefiber) { 1110 case 0: 1111 /* UTP Port */ 1112 DBG(DPHY, "forcing twpair"); 1113 mcr &= ~MCR_FIBER; 1114 fiber = 0; 1115 break; 1116 case 1: 1117 /* Fiber Port */ 1118 DBG(DPHY, "forcing 100BaseFX"); 1119 mcr |= MCR_FIBER; 1120 bmcr = (MII_CONTROL_100MB | MII_CONTROL_FDUPLEX); 1121 fiber = 1; 1122 break; 1123 default: 1124 DBG(DPHY, "checking for 100BaseFX link"); 1125 /* fiber is 100 Mb FDX */ 1126 afe_miiwrite(afep, phyaddr, MII_CONTROL, 1127 MII_CONTROL_100MB | MII_CONTROL_FDUPLEX); 1128 drv_usecwait(50); 1129 1130 mcr = afe_miiread(afep, phyaddr, PHY_MCR); 1131 mcr |= MCR_FIBER; 1132 afe_miiwrite(afep, phyaddr, PHY_MCR, mcr); 1133 drv_usecwait(500); 1134 1135 /* if fiber is active, use it */ 1136 if ((afe_miiread(afep, phyaddr, MII_STATUS) & 1137 MII_STATUS_LINKUP)) { 1138 bmcr = MII_CONTROL_100MB | MII_CONTROL_FDUPLEX; 1139 fiber = 1; 1140 } else { 1141 mcr &= ~MCR_FIBER; 1142 fiber = 0; 1143 } 1144 break; 1145 } 1146 afe_miiwrite(afep, phyaddr, PHY_MCR, mcr); 1147 drv_usecwait(500); 1148 } 1149 1150 if (fiber) { 1151 /* fiber only supports 100FDX(?) */ 1152 bmsr &= ~(MII_STATUS_100_BASE_T4 | 1153 MII_STATUS_100_BASEX | MII_STATUS_10_FD | MII_STATUS_10); 1154 bmsr |= MII_STATUS_100_BASEX_FD; 1155 } 1156 1157 /* assume full support for everything to start */ 1158 afep->afe_cap_aneg = afep->afe_cap_100T4 = 1159 afep->afe_cap_100fdx = afep->afe_cap_100hdx = 1160 afep->afe_cap_10fdx = afep->afe_cap_10hdx = 1; 1161 1162 /* disable modes not supported in hardware */ 1163 if (!(bmsr & MII_STATUS_100_BASEX_FD)) { 1164 afep->afe_adv_100fdx = 0; 1165 afep->afe_cap_100fdx = 0; 1166 } 1167 if (!(bmsr & MII_STATUS_100_BASE_T4)) { 1168 afep->afe_adv_100T4 = 0; 1169 afep->afe_cap_100T4 = 0; 1170 } 1171 if (!(bmsr & MII_STATUS_100_BASEX)) { 1172 afep->afe_adv_100hdx = 0; 1173 afep->afe_cap_100hdx = 0; 1174 } 1175 if (!(bmsr & MII_STATUS_10_FD)) { 1176 afep->afe_adv_10fdx = 0; 1177 afep->afe_cap_10fdx = 0; 1178 } 1179 if (!(bmsr & MII_STATUS_10)) { 1180 afep->afe_adv_10hdx = 0; 1181 afep->afe_cap_10hdx = 0; 1182 } 1183 if (!(bmsr & MII_STATUS_CANAUTONEG)) { 1184 afep->afe_adv_aneg = 0; 1185 afep->afe_cap_aneg = 0; 1186 } 1187 1188 cnt = 0; 1189 if (afep->afe_adv_100fdx) { 1190 anar |= MII_ABILITY_100BASE_TX_FD; 1191 cnt++; 1192 } 1193 if (afep->afe_adv_100T4) { 1194 anar |= MII_ABILITY_100BASE_T4; 1195 cnt++; 1196 } 1197 if (afep->afe_adv_100hdx) { 1198 anar |= MII_ABILITY_100BASE_TX; 1199 cnt++; 1200 } 1201 if (afep->afe_adv_10fdx) { 1202 anar |= MII_ABILITY_10BASE_T_FD; 1203 cnt++; 1204 } 1205 if (afep->afe_adv_10hdx) { 1206 anar |= MII_ABILITY_10BASE_T; 1207 cnt++; 1208 } 1209 1210 /* 1211 * Make certain at least one valid link mode is selected. 1212 */ 1213 if (!cnt) { 1214 afe_error(afep->afe_dip, "No valid link mode selected."); 1215 afe_error(afep->afe_dip, "Powering down PHY."); 1216 afe_stopphy(afep); 1217 afep->afe_linkup = LINK_STATE_DOWN; 1218 if (afep->afe_flags & AFE_RUNNING) 1219 afe_reportlink(afep); 1220 return; 1221 } 1222 1223 if (fiber) { 1224 bmcr = MII_CONTROL_100MB | MII_CONTROL_FDUPLEX; 1225 } else if ((afep->afe_adv_aneg) && (bmsr & MII_STATUS_CANAUTONEG)) { 1226 DBG(DPHY, "using autoneg mode"); 1227 bmcr = (MII_CONTROL_ANE | MII_CONTROL_RSAN); 1228 } else { 1229 DBG(DPHY, "using forced mode"); 1230 if (afep->afe_adv_100fdx) { 1231 bmcr = (MII_CONTROL_100MB | MII_CONTROL_FDUPLEX); 1232 } else if (afep->afe_adv_100hdx) { 1233 bmcr = MII_CONTROL_100MB; 1234 } else if (afep->afe_adv_10fdx) { 1235 bmcr = MII_CONTROL_FDUPLEX; 1236 } else { 1237 /* 10HDX */ 1238 bmcr = 0; 1239 } 1240 } 1241 1242 DBG(DPHY, "programming anar to 0x%x", anar); 1243 afe_miiwrite(afep, phyaddr, MII_AN_ADVERT, anar); 1244 DBG(DPHY, "programming bmcr to 0x%x", bmcr); 1245 afe_miiwrite(afep, phyaddr, MII_CONTROL, bmcr); 1246 1247 if (nosqe) { 1248 uint16_t pilr; 1249 /* 1250 * work around for errata 983B_0416 -- duplex light flashes 1251 * in 10 HDX. we just disable SQE testing on the device. 1252 */ 1253 pilr = afe_miiread(afep, phyaddr, PHY_PILR); 1254 pilr |= PILR_NOSQE; 1255 afe_miiwrite(afep, phyaddr, PHY_PILR, pilr); 1256 } 1257 1258 /* 1259 * schedule a query of the link status 1260 */ 1261 PUTCSR(afep, CSR_TIMER, TIMER_LOOP | 1262 (AFE_LINKTIMER * 1000 / TIMER_USEC)); 1263 } 1264 1265 void 1266 afe_stopphy(afe_t *afep) 1267 { 1268 /* stop the phy timer */ 1269 PUTCSR(afep, CSR_TIMER, 0); 1270 1271 /* 1272 * phy in isolate & powerdown mode... 1273 */ 1274 afe_miiwrite(afep, afep->afe_phyaddr, MII_CONTROL, 1275 MII_CONTROL_PWRDN | MII_CONTROL_ISOLATE); 1276 1277 /* 1278 * mark the link state unknown 1279 */ 1280 if (!afep->afe_resetting) { 1281 afep->afe_linkup = LINK_STATE_UNKNOWN; 1282 afep->afe_ifspeed = 0; 1283 afep->afe_duplex = LINK_DUPLEX_UNKNOWN; 1284 if (afep->afe_flags & AFE_RUNNING) 1285 afe_reportlink(afep); 1286 } 1287 } 1288 1289 void 1290 afe_reportlink(afe_t *afep) 1291 { 1292 int changed = 0; 1293 1294 if (afep->afe_ifspeed != afep->afe_lastifspeed) { 1295 afep->afe_lastifspeed = afep->afe_ifspeed; 1296 changed++; 1297 } 1298 if (afep->afe_duplex != afep->afe_lastduplex) { 1299 afep->afe_lastduplex = afep->afe_duplex; 1300 changed++; 1301 } 1302 if (changed) 1303 mac_link_update(afep->afe_mh, afep->afe_linkup); 1304 } 1305 1306 void 1307 afe_checklink(afe_t *afep) 1308 { 1309 if ((afep->afe_flags & AFE_RUNNING) == 0) 1310 return; 1311 1312 if ((afep->afe_txstall_time != 0) && 1313 (gethrtime() > afep->afe_txstall_time) && 1314 (afep->afe_txavail != AFE_TXRING)) { 1315 afep->afe_txstall_time = 0; 1316 afe_error(afep->afe_dip, "TX stall detected!"); 1317 afe_resetall(afep); 1318 return; 1319 } 1320 1321 switch (AFE_MODEL(afep)) { 1322 case MODEL_COMET: 1323 afe_checklinkcomet(afep); 1324 break; 1325 case MODEL_CENTAUR: 1326 afe_checklinkcentaur(afep); 1327 break; 1328 } 1329 } 1330 1331 void 1332 afe_checklinkcomet(afe_t *afep) 1333 { 1334 uint16_t xciis; 1335 int reinit = 0; 1336 1337 xciis = GETCSR16(afep, CSR_XCIIS); 1338 if (xciis & XCIIS_PDF) { 1339 afe_error(afep->afe_dip, "Parallel detection fault detected!"); 1340 } 1341 if (xciis & XCIIS_RF) { 1342 afe_error(afep->afe_dip, "Remote fault detected."); 1343 } 1344 if (xciis & XCIIS_LFAIL) { 1345 if (afep->afe_linkup == LINK_STATE_UP) { 1346 reinit++; 1347 } 1348 afep->afe_ifspeed = 0; 1349 afep->afe_linkup = LINK_STATE_DOWN; 1350 afep->afe_duplex = LINK_DUPLEX_UNKNOWN; 1351 afe_reportlink(afep); 1352 if (reinit) { 1353 afe_startphy(afep); 1354 } 1355 return; 1356 } 1357 1358 afep->afe_linkup = LINK_STATE_UP; 1359 afep->afe_ifspeed = (xciis & XCIIS_SPEED) ? 100000000 : 10000000; 1360 if (xciis & XCIIS_DUPLEX) { 1361 afep->afe_duplex = LINK_DUPLEX_FULL; 1362 } else { 1363 afep->afe_duplex = LINK_DUPLEX_HALF; 1364 } 1365 1366 afe_reportlink(afep); 1367 } 1368 1369 void 1370 afe_checklinkcentaur(afe_t *afep) 1371 { 1372 unsigned opmode; 1373 int reinit = 0; 1374 1375 opmode = GETCSR(afep, CSR_OPM); 1376 if ((opmode & OPM_MODE) == OPM_MACONLY) { 1377 DBG(DPHY, "Centaur running in MAC-only mode"); 1378 afe_checklinkmii(afep); 1379 return; 1380 } 1381 DBG(DPHY, "Centaur running in single chip mode"); 1382 if ((opmode & OPM_LINK) == 0) { 1383 if (afep->afe_linkup == LINK_STATE_UP) { 1384 reinit++; 1385 } 1386 afep->afe_ifspeed = 0; 1387 afep->afe_duplex = LINK_DUPLEX_UNKNOWN; 1388 afep->afe_linkup = LINK_STATE_DOWN; 1389 afe_reportlink(afep); 1390 if (reinit) { 1391 afe_startphy(afep); 1392 } 1393 return; 1394 } 1395 1396 afep->afe_linkup = LINK_STATE_UP; 1397 afep->afe_ifspeed = (opmode & OPM_SPEED) ? 100000000 : 10000000; 1398 if (opmode & OPM_DUPLEX) { 1399 afep->afe_duplex = LINK_DUPLEX_FULL; 1400 } else { 1401 afep->afe_duplex = LINK_DUPLEX_HALF; 1402 } 1403 afe_reportlink(afep); 1404 } 1405 1406 void 1407 afe_checklinkmii(afe_t *afep) 1408 { 1409 /* read MII state registers */ 1410 uint16_t bmsr; 1411 uint16_t bmcr; 1412 uint16_t anar; 1413 uint16_t anlpar; 1414 int reinit = 0; 1415 1416 /* read this twice, to clear latched link state */ 1417 bmsr = afe_miiread(afep, afep->afe_phyaddr, MII_STATUS); 1418 bmsr = afe_miiread(afep, afep->afe_phyaddr, MII_STATUS); 1419 bmcr = afe_miiread(afep, afep->afe_phyaddr, MII_CONTROL); 1420 anar = afe_miiread(afep, afep->afe_phyaddr, MII_AN_ADVERT); 1421 anlpar = afe_miiread(afep, afep->afe_phyaddr, MII_AN_LPABLE); 1422 1423 if (bmsr & MII_STATUS_REMFAULT) { 1424 afe_error(afep->afe_dip, "Remote fault detected."); 1425 } 1426 if (bmsr & MII_STATUS_JABBERING) { 1427 afe_error(afep->afe_dip, "Jabber condition detected."); 1428 } 1429 if ((bmsr & MII_STATUS_LINKUP) == 0) { 1430 /* no link */ 1431 if (afep->afe_linkup == LINK_STATE_UP) { 1432 reinit = 1; 1433 } 1434 afep->afe_ifspeed = 0; 1435 afep->afe_duplex = LINK_DUPLEX_UNKNOWN; 1436 afep->afe_linkup = LINK_STATE_DOWN; 1437 afe_reportlink(afep); 1438 if (reinit) { 1439 afe_startphy(afep); 1440 } 1441 return; 1442 } 1443 1444 DBG(DCHATTY, "link up!"); 1445 afep->afe_linkup = LINK_STATE_UP; 1446 1447 if (!(bmcr & MII_CONTROL_ANE)) { 1448 /* forced mode */ 1449 if (bmcr & MII_CONTROL_100MB) { 1450 afep->afe_ifspeed = 100000000; 1451 } else { 1452 afep->afe_ifspeed = 10000000; 1453 } 1454 if (bmcr & MII_CONTROL_FDUPLEX) { 1455 afep->afe_duplex = LINK_DUPLEX_FULL; 1456 } else { 1457 afep->afe_duplex = LINK_DUPLEX_HALF; 1458 } 1459 } else if ((!(bmsr & MII_STATUS_CANAUTONEG)) || 1460 (!(bmsr & MII_STATUS_ANDONE))) { 1461 afep->afe_ifspeed = 0; 1462 afep->afe_duplex = LINK_DUPLEX_UNKNOWN; 1463 } else if (anar & anlpar & MII_ABILITY_100BASE_TX_FD) { 1464 afep->afe_ifspeed = 100000000; 1465 afep->afe_duplex = LINK_DUPLEX_FULL; 1466 } else if (anar & anlpar & MII_ABILITY_100BASE_T4) { 1467 afep->afe_ifspeed = 100000000; 1468 afep->afe_duplex = LINK_DUPLEX_HALF; 1469 } else if (anar & anlpar & MII_ABILITY_100BASE_TX) { 1470 afep->afe_ifspeed = 100000000; 1471 afep->afe_duplex = LINK_DUPLEX_HALF; 1472 } else if (anar & anlpar & MII_ABILITY_10BASE_T_FD) { 1473 afep->afe_ifspeed = 10000000; 1474 afep->afe_duplex = LINK_DUPLEX_FULL; 1475 } else if (anar & anlpar & MII_ABILITY_10BASE_T) { 1476 afep->afe_ifspeed = 10000000; 1477 afep->afe_duplex = LINK_DUPLEX_HALF; 1478 } else { 1479 afep->afe_ifspeed = 0; 1480 afep->afe_duplex = LINK_DUPLEX_UNKNOWN; 1481 } 1482 1483 afe_reportlink(afep); 1484 } 1485 1486 void 1487 afe_miitristate(afe_t *afep) 1488 { 1489 uint32_t val = SPR_SROM_WRITE | SPR_MII_CTRL; 1490 1491 PUTCSR(afep, CSR_SPR, val); 1492 drv_usecwait(1); 1493 PUTCSR(afep, CSR_SPR, val | SPR_MII_CLOCK); 1494 drv_usecwait(1); 1495 } 1496 1497 void 1498 afe_miiwritebit(afe_t *afep, uint8_t bit) 1499 { 1500 uint32_t val = bit ? SPR_MII_DOUT : 0; 1501 1502 PUTCSR(afep, CSR_SPR, val); 1503 drv_usecwait(1); 1504 PUTCSR(afep, CSR_SPR, val | SPR_MII_CLOCK); 1505 drv_usecwait(1); 1506 } 1507 1508 uint8_t 1509 afe_miireadbit(afe_t *afep) 1510 { 1511 uint32_t val = SPR_MII_CTRL | SPR_SROM_READ; 1512 uint8_t bit; 1513 1514 PUTCSR(afep, CSR_SPR, val); 1515 drv_usecwait(1); 1516 bit = (GETCSR(afep, CSR_SPR) & SPR_MII_DIN) ? 1 : 0; 1517 PUTCSR(afep, CSR_SPR, val | SPR_MII_CLOCK); 1518 drv_usecwait(1); 1519 return (bit); 1520 } 1521 1522 uint16_t 1523 afe_miiread(afe_t *afep, int phy, int reg) 1524 { 1525 /* 1526 * ADMtek bugs ignore address decode bits -- they only 1527 * support PHY at 1. 1528 */ 1529 if (phy != 1) { 1530 return (0xffff); 1531 } 1532 switch (AFE_MODEL(afep)) { 1533 case MODEL_COMET: 1534 return (afe_miireadcomet(afep, phy, reg)); 1535 case MODEL_CENTAUR: 1536 return (afe_miireadgeneral(afep, phy, reg)); 1537 } 1538 return (0xffff); 1539 } 1540 1541 uint16_t 1542 afe_miireadgeneral(afe_t *afep, int phy, int reg) 1543 { 1544 uint16_t value = 0; 1545 int i; 1546 1547 /* send the 32 bit preamble */ 1548 for (i = 0; i < 32; i++) { 1549 afe_miiwritebit(afep, 1); 1550 } 1551 1552 /* send the start code - 01b */ 1553 afe_miiwritebit(afep, 0); 1554 afe_miiwritebit(afep, 1); 1555 1556 /* send the opcode for read, - 10b */ 1557 afe_miiwritebit(afep, 1); 1558 afe_miiwritebit(afep, 0); 1559 1560 /* next we send the 5 bit phy address */ 1561 for (i = 0x10; i > 0; i >>= 1) { 1562 afe_miiwritebit(afep, (phy & i) ? 1 : 0); 1563 } 1564 1565 /* the 5 bit register address goes next */ 1566 for (i = 0x10; i > 0; i >>= 1) { 1567 afe_miiwritebit(afep, (reg & i) ? 1 : 0); 1568 } 1569 1570 /* turnaround - tristate followed by logic 0 */ 1571 afe_miitristate(afep); 1572 afe_miiwritebit(afep, 0); 1573 1574 /* read the 16 bit register value */ 1575 for (i = 0x8000; i > 0; i >>= 1) { 1576 value <<= 1; 1577 value |= afe_miireadbit(afep); 1578 } 1579 afe_miitristate(afep); 1580 return (value); 1581 } 1582 1583 uint16_t 1584 afe_miireadcomet(afe_t *afep, int phy, int reg) 1585 { 1586 if (phy != 1) { 1587 return (0xffff); 1588 } 1589 switch (reg) { 1590 case MII_CONTROL: 1591 reg = CSR_BMCR; 1592 break; 1593 case MII_STATUS: 1594 reg = CSR_BMSR; 1595 break; 1596 case MII_PHYIDH: 1597 reg = CSR_PHYIDR1; 1598 break; 1599 case MII_PHYIDL: 1600 reg = CSR_PHYIDR2; 1601 break; 1602 case MII_AN_ADVERT: 1603 reg = CSR_ANAR; 1604 break; 1605 case MII_AN_LPABLE: 1606 reg = CSR_ANLPAR; 1607 break; 1608 case MII_AN_EXPANSION: 1609 reg = CSR_ANER; 1610 break; 1611 default: 1612 return (0); 1613 } 1614 return (GETCSR16(afep, reg) & 0xFFFF); 1615 } 1616 1617 void 1618 afe_miiwrite(afe_t *afep, int phy, int reg, uint16_t val) 1619 { 1620 /* 1621 * ADMtek bugs ignore address decode bits -- they only 1622 * support PHY at 1. 1623 */ 1624 if (phy != 1) { 1625 return; 1626 } 1627 switch (AFE_MODEL(afep)) { 1628 case MODEL_COMET: 1629 afe_miiwritecomet(afep, phy, reg, val); 1630 break; 1631 case MODEL_CENTAUR: 1632 afe_miiwritegeneral(afep, phy, reg, val); 1633 break; 1634 } 1635 } 1636 1637 void 1638 afe_miiwritegeneral(afe_t *afep, int phy, int reg, uint16_t val) 1639 { 1640 int i; 1641 1642 /* send the 32 bit preamble */ 1643 for (i = 0; i < 32; i++) { 1644 afe_miiwritebit(afep, 1); 1645 } 1646 1647 /* send the start code - 01b */ 1648 afe_miiwritebit(afep, 0); 1649 afe_miiwritebit(afep, 1); 1650 1651 /* send the opcode for write, - 01b */ 1652 afe_miiwritebit(afep, 0); 1653 afe_miiwritebit(afep, 1); 1654 1655 /* next we send the 5 bit phy address */ 1656 for (i = 0x10; i > 0; i >>= 1) { 1657 afe_miiwritebit(afep, (phy & i) ? 1 : 0); 1658 } 1659 1660 /* the 5 bit register address goes next */ 1661 for (i = 0x10; i > 0; i >>= 1) { 1662 afe_miiwritebit(afep, (reg & i) ? 1 : 0); 1663 } 1664 1665 /* turnaround - tristate followed by logic 0 */ 1666 afe_miitristate(afep); 1667 afe_miiwritebit(afep, 0); 1668 1669 /* now write out our data (16 bits) */ 1670 for (i = 0x8000; i > 0; i >>= 1) { 1671 afe_miiwritebit(afep, (val & i) ? 1 : 0); 1672 } 1673 1674 /* idle mode */ 1675 afe_miitristate(afep); 1676 } 1677 1678 void 1679 afe_miiwritecomet(afe_t *afep, int phy, int reg, uint16_t val) 1680 { 1681 if (phy != 1) { 1682 return; 1683 } 1684 switch (reg) { 1685 case MII_CONTROL: 1686 reg = CSR_BMCR; 1687 break; 1688 case MII_STATUS: 1689 reg = CSR_BMSR; 1690 break; 1691 case MII_PHYIDH: 1692 reg = CSR_PHYIDR1; 1693 break; 1694 case MII_PHYIDL: 1695 reg = CSR_PHYIDR2; 1696 break; 1697 case MII_AN_ADVERT: 1698 reg = CSR_ANAR; 1699 break; 1700 case MII_AN_LPABLE: 1701 reg = CSR_ANLPAR; 1702 break; 1703 case MII_AN_EXPANSION: 1704 reg = CSR_ANER; 1705 break; 1706 default: 1707 return; 1708 } 1709 PUTCSR16(afep, reg, val); 1710 } 1711 1712 int 1713 afe_m_start(void *arg) 1714 { 1715 afe_t *afep = arg; 1716 1717 /* grab exclusive access to the card */ 1718 mutex_enter(&afep->afe_intrlock); 1719 mutex_enter(&afep->afe_xmtlock); 1720 1721 afe_startall(afep); 1722 afep->afe_flags |= AFE_RUNNING; 1723 1724 mutex_exit(&afep->afe_xmtlock); 1725 mutex_exit(&afep->afe_intrlock); 1726 return (0); 1727 } 1728 1729 void 1730 afe_m_stop(void *arg) 1731 { 1732 afe_t *afep = arg; 1733 1734 /* exclusive access to the hardware! */ 1735 mutex_enter(&afep->afe_intrlock); 1736 mutex_enter(&afep->afe_xmtlock); 1737 1738 afe_stopall(afep); 1739 afep->afe_flags &= ~AFE_RUNNING; 1740 1741 mutex_exit(&afep->afe_xmtlock); 1742 mutex_exit(&afep->afe_intrlock); 1743 } 1744 1745 void 1746 afe_startmac(afe_t *afep) 1747 { 1748 /* verify exclusive access to the card */ 1749 ASSERT(mutex_owned(&afep->afe_intrlock)); 1750 ASSERT(mutex_owned(&afep->afe_xmtlock)); 1751 1752 /* start the card */ 1753 SETBIT(afep, CSR_NAR, NAR_TX_ENABLE | NAR_RX_ENABLE); 1754 1755 if (afep->afe_txavail != AFE_TXRING) 1756 PUTCSR(afep, CSR_TDR, 0); 1757 1758 /* tell the mac that we are ready to go! */ 1759 if (afep->afe_flags & AFE_RUNNING) 1760 mac_tx_update(afep->afe_mh); 1761 } 1762 1763 void 1764 afe_stopmac(afe_t *afep) 1765 { 1766 int i; 1767 1768 /* exclusive access to the hardware! */ 1769 ASSERT(mutex_owned(&afep->afe_intrlock)); 1770 ASSERT(mutex_owned(&afep->afe_xmtlock)); 1771 1772 CLRBIT(afep, CSR_NAR, NAR_TX_ENABLE | NAR_RX_ENABLE); 1773 1774 /* 1775 * A 1518 byte frame at 10Mbps takes about 1.2 msec to drain. 1776 * We just add up to the nearest msec (2), which should be 1777 * plenty to complete. 1778 * 1779 * Note that some chips never seem to indicate the transition to 1780 * the stopped state properly. Experience shows that we can safely 1781 * proceed anyway, after waiting the requisite timeout. 1782 */ 1783 for (i = 2000; i != 0; i -= 10) { 1784 if ((GETCSR(afep, CSR_SR) & (SR_TX_STATE | SR_RX_STATE)) == 0) 1785 break; 1786 drv_usecwait(10); 1787 } 1788 1789 /* prevent an interrupt */ 1790 PUTCSR(afep, CSR_SR2, INT_RXSTOPPED | INT_TXSTOPPED); 1791 } 1792 1793 void 1794 afe_resetrings(afe_t *afep) 1795 { 1796 int i; 1797 1798 /* now we need to reset the pointers... */ 1799 PUTCSR(afep, CSR_RDB, 0); 1800 PUTCSR(afep, CSR_TDB, 0); 1801 1802 /* reset the descriptor ring pointers */ 1803 afep->afe_rxhead = 0; 1804 afep->afe_txreclaim = 0; 1805 afep->afe_txsend = 0; 1806 afep->afe_txavail = AFE_TXRING; 1807 1808 /* set up transmit descriptor ring */ 1809 for (i = 0; i < AFE_TXRING; i++) { 1810 afe_desc_t *tmdp = &afep->afe_txdescp[i]; 1811 unsigned control = 0; 1812 if (i == (AFE_TXRING - 1)) { 1813 control |= TXCTL_ENDRING; 1814 } 1815 PUTTXDESC(afep, tmdp->desc_status, 0); 1816 PUTTXDESC(afep, tmdp->desc_control, control); 1817 PUTTXDESC(afep, tmdp->desc_buffer1, 0); 1818 PUTTXDESC(afep, tmdp->desc_buffer2, 0); 1819 SYNCTXDESC(afep, i, DDI_DMA_SYNC_FORDEV); 1820 } 1821 PUTCSR(afep, CSR_TDB, afep->afe_txdesc_paddr); 1822 1823 /* make the receive buffers available */ 1824 for (i = 0; i < AFE_RXRING; i++) { 1825 afe_rxbuf_t *rxb = afep->afe_rxbufs[i]; 1826 afe_desc_t *rmdp = &afep->afe_rxdescp[i]; 1827 unsigned control; 1828 1829 control = AFE_BUFSZ & RXCTL_BUFLEN1; 1830 if (i == (AFE_RXRING - 1)) { 1831 control |= RXCTL_ENDRING; 1832 } 1833 PUTRXDESC(afep, rmdp->desc_buffer1, rxb->rxb_paddr); 1834 PUTRXDESC(afep, rmdp->desc_buffer2, 0); 1835 PUTRXDESC(afep, rmdp->desc_control, control); 1836 PUTRXDESC(afep, rmdp->desc_status, RXSTAT_OWN); 1837 SYNCRXDESC(afep, i, DDI_DMA_SYNC_FORDEV); 1838 } 1839 PUTCSR(afep, CSR_RDB, afep->afe_rxdesc_paddr); 1840 } 1841 1842 void 1843 afe_stopall(afe_t *afep) 1844 { 1845 afe_disableinterrupts(afep); 1846 1847 afe_stopmac(afep); 1848 1849 /* stop the phy */ 1850 afe_stopphy(afep); 1851 } 1852 1853 void 1854 afe_startall(afe_t *afep) 1855 { 1856 ASSERT(mutex_owned(&afep->afe_intrlock)); 1857 ASSERT(mutex_owned(&afep->afe_xmtlock)); 1858 1859 /* make sure interrupts are disabled to begin */ 1860 afe_disableinterrupts(afep); 1861 1862 /* initialize the chip */ 1863 (void) afe_initialize(afep); 1864 1865 /* now we can enable interrupts */ 1866 afe_enableinterrupts(afep); 1867 1868 /* start up the phy */ 1869 afe_startphy(afep); 1870 1871 /* start up the mac */ 1872 afe_startmac(afep); 1873 } 1874 1875 void 1876 afe_resetall(afe_t *afep) 1877 { 1878 afep->afe_resetting = B_TRUE; 1879 afe_stopall(afep); 1880 afep->afe_resetting = B_FALSE; 1881 afe_startall(afep); 1882 } 1883 1884 afe_txbuf_t * 1885 afe_alloctxbuf(afe_t *afep) 1886 { 1887 ddi_dma_cookie_t dmac; 1888 unsigned ncookies; 1889 afe_txbuf_t *txb; 1890 size_t len; 1891 1892 txb = kmem_zalloc(sizeof (*txb), KM_SLEEP); 1893 1894 if (ddi_dma_alloc_handle(afep->afe_dip, &afe_dma_txattr, 1895 DDI_DMA_SLEEP, NULL, &txb->txb_dmah) != DDI_SUCCESS) { 1896 return (NULL); 1897 } 1898 1899 if (ddi_dma_mem_alloc(txb->txb_dmah, AFE_BUFSZ, &afe_bufattr, 1900 DDI_DMA_STREAMING, DDI_DMA_SLEEP, NULL, &txb->txb_buf, &len, 1901 &txb->txb_acch) != DDI_SUCCESS) { 1902 return (NULL); 1903 } 1904 if (ddi_dma_addr_bind_handle(txb->txb_dmah, NULL, txb->txb_buf, 1905 len, DDI_DMA_WRITE | DDI_DMA_STREAMING, DDI_DMA_SLEEP, NULL, 1906 &dmac, &ncookies) != DDI_DMA_MAPPED) { 1907 return (NULL); 1908 } 1909 txb->txb_paddr = dmac.dmac_address; 1910 1911 return (txb); 1912 } 1913 1914 void 1915 afe_destroytxbuf(afe_txbuf_t *txb) 1916 { 1917 if (txb != NULL) { 1918 if (txb->txb_paddr) 1919 (void) ddi_dma_unbind_handle(txb->txb_dmah); 1920 if (txb->txb_acch) 1921 ddi_dma_mem_free(&txb->txb_acch); 1922 if (txb->txb_dmah) 1923 ddi_dma_free_handle(&txb->txb_dmah); 1924 kmem_free(txb, sizeof (*txb)); 1925 } 1926 } 1927 1928 afe_rxbuf_t * 1929 afe_allocrxbuf(afe_t *afep) 1930 { 1931 afe_rxbuf_t *rxb; 1932 size_t len; 1933 unsigned ccnt; 1934 ddi_dma_cookie_t dmac; 1935 1936 rxb = kmem_zalloc(sizeof (*rxb), KM_SLEEP); 1937 1938 if (ddi_dma_alloc_handle(afep->afe_dip, &afe_dma_attr, 1939 DDI_DMA_SLEEP, NULL, &rxb->rxb_dmah) != DDI_SUCCESS) { 1940 kmem_free(rxb, sizeof (*rxb)); 1941 return (NULL); 1942 } 1943 if (ddi_dma_mem_alloc(rxb->rxb_dmah, AFE_BUFSZ, &afe_bufattr, 1944 DDI_DMA_STREAMING, DDI_DMA_SLEEP, NULL, &rxb->rxb_buf, &len, 1945 &rxb->rxb_acch) != DDI_SUCCESS) { 1946 ddi_dma_free_handle(&rxb->rxb_dmah); 1947 kmem_free(rxb, sizeof (*rxb)); 1948 return (NULL); 1949 } 1950 if (ddi_dma_addr_bind_handle(rxb->rxb_dmah, NULL, rxb->rxb_buf, len, 1951 DDI_DMA_READ | DDI_DMA_STREAMING, DDI_DMA_SLEEP, NULL, &dmac, 1952 &ccnt) != DDI_DMA_MAPPED) { 1953 ddi_dma_mem_free(&rxb->rxb_acch); 1954 ddi_dma_free_handle(&rxb->rxb_dmah); 1955 kmem_free(rxb, sizeof (*rxb)); 1956 return (NULL); 1957 } 1958 rxb->rxb_paddr = dmac.dmac_address; 1959 1960 return (rxb); 1961 } 1962 1963 void 1964 afe_destroyrxbuf(afe_rxbuf_t *rxb) 1965 { 1966 if (rxb) { 1967 (void) ddi_dma_unbind_handle(rxb->rxb_dmah); 1968 ddi_dma_mem_free(&rxb->rxb_acch); 1969 ddi_dma_free_handle(&rxb->rxb_dmah); 1970 kmem_free(rxb, sizeof (*rxb)); 1971 } 1972 } 1973 1974 /* 1975 * Allocate receive resources. 1976 */ 1977 int 1978 afe_allocrxring(afe_t *afep) 1979 { 1980 int rval; 1981 int i; 1982 size_t size; 1983 size_t len; 1984 ddi_dma_cookie_t dmac; 1985 unsigned ncookies; 1986 caddr_t kaddr; 1987 1988 size = AFE_RXRING * sizeof (afe_desc_t); 1989 1990 rval = ddi_dma_alloc_handle(afep->afe_dip, &afe_dma_attr, 1991 DDI_DMA_SLEEP, NULL, &afep->afe_rxdesc_dmah); 1992 if (rval != DDI_SUCCESS) { 1993 afe_error(afep->afe_dip, 1994 "unable to allocate DMA handle for rx descriptors"); 1995 return (DDI_FAILURE); 1996 } 1997 1998 rval = ddi_dma_mem_alloc(afep->afe_rxdesc_dmah, size, &afe_devattr, 1999 DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, &kaddr, &len, 2000 &afep->afe_rxdesc_acch); 2001 if (rval != DDI_SUCCESS) { 2002 afe_error(afep->afe_dip, 2003 "unable to allocate DMA memory for rx descriptors"); 2004 return (DDI_FAILURE); 2005 } 2006 2007 rval = ddi_dma_addr_bind_handle(afep->afe_rxdesc_dmah, NULL, kaddr, 2008 size, DDI_DMA_RDWR | DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, 2009 &dmac, &ncookies); 2010 if (rval != DDI_DMA_MAPPED) { 2011 afe_error(afep->afe_dip, 2012 "unable to bind DMA for rx descriptors"); 2013 return (DDI_FAILURE); 2014 } 2015 2016 /* because of afe_dma_attr */ 2017 ASSERT(ncookies == 1); 2018 2019 /* we take the 32-bit physical address out of the cookie */ 2020 afep->afe_rxdesc_paddr = dmac.dmac_address; 2021 afep->afe_rxdescp = (void *)kaddr; 2022 2023 /* allocate buffer pointers (not the buffers themselves, yet) */ 2024 afep->afe_rxbufs = kmem_zalloc(AFE_RXRING * sizeof (afe_rxbuf_t *), 2025 KM_SLEEP); 2026 2027 /* now allocate rx buffers */ 2028 for (i = 0; i < AFE_RXRING; i++) { 2029 afe_rxbuf_t *rxb = afe_allocrxbuf(afep); 2030 if (rxb == NULL) 2031 return (DDI_FAILURE); 2032 afep->afe_rxbufs[i] = rxb; 2033 } 2034 2035 return (DDI_SUCCESS); 2036 } 2037 2038 /* 2039 * Allocate transmit resources. 2040 */ 2041 int 2042 afe_alloctxring(afe_t *afep) 2043 { 2044 int rval; 2045 int i; 2046 size_t size; 2047 size_t len; 2048 ddi_dma_cookie_t dmac; 2049 unsigned ncookies; 2050 caddr_t kaddr; 2051 2052 size = AFE_TXRING * sizeof (afe_desc_t); 2053 2054 rval = ddi_dma_alloc_handle(afep->afe_dip, &afe_dma_attr, 2055 DDI_DMA_SLEEP, NULL, &afep->afe_txdesc_dmah); 2056 if (rval != DDI_SUCCESS) { 2057 afe_error(afep->afe_dip, 2058 "unable to allocate DMA handle for tx descriptors"); 2059 return (DDI_FAILURE); 2060 } 2061 2062 rval = ddi_dma_mem_alloc(afep->afe_txdesc_dmah, size, &afe_devattr, 2063 DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, &kaddr, &len, 2064 &afep->afe_txdesc_acch); 2065 if (rval != DDI_SUCCESS) { 2066 afe_error(afep->afe_dip, 2067 "unable to allocate DMA memory for tx descriptors"); 2068 return (DDI_FAILURE); 2069 } 2070 2071 rval = ddi_dma_addr_bind_handle(afep->afe_txdesc_dmah, NULL, kaddr, 2072 size, DDI_DMA_RDWR | DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, 2073 &dmac, &ncookies); 2074 if (rval != DDI_DMA_MAPPED) { 2075 afe_error(afep->afe_dip, 2076 "unable to bind DMA for tx descriptors"); 2077 return (DDI_FAILURE); 2078 } 2079 2080 /* because of afe_dma_attr */ 2081 ASSERT(ncookies == 1); 2082 2083 /* we take the 32-bit physical address out of the cookie */ 2084 afep->afe_txdesc_paddr = dmac.dmac_address; 2085 afep->afe_txdescp = (void *)kaddr; 2086 2087 /* allocate buffer pointers (not the buffers themselves, yet) */ 2088 afep->afe_txbufs = kmem_zalloc(AFE_TXRING * sizeof (afe_txbuf_t *), 2089 KM_SLEEP); 2090 2091 /* now allocate tx buffers */ 2092 for (i = 0; i < AFE_TXRING; i++) { 2093 afe_txbuf_t *txb = afe_alloctxbuf(afep); 2094 if (txb == NULL) 2095 return (DDI_FAILURE); 2096 afep->afe_txbufs[i] = txb; 2097 } 2098 2099 return (DDI_SUCCESS); 2100 } 2101 2102 void 2103 afe_freerxring(afe_t *afep) 2104 { 2105 int i; 2106 2107 for (i = 0; i < AFE_RXRING; i++) { 2108 afe_destroyrxbuf(afep->afe_rxbufs[i]); 2109 } 2110 2111 if (afep->afe_rxbufs) { 2112 kmem_free(afep->afe_rxbufs, 2113 AFE_RXRING * sizeof (afe_rxbuf_t *)); 2114 } 2115 2116 if (afep->afe_rxdesc_paddr) 2117 (void) ddi_dma_unbind_handle(afep->afe_rxdesc_dmah); 2118 if (afep->afe_rxdesc_acch) 2119 ddi_dma_mem_free(&afep->afe_rxdesc_acch); 2120 if (afep->afe_rxdesc_dmah) 2121 ddi_dma_free_handle(&afep->afe_rxdesc_dmah); 2122 } 2123 2124 void 2125 afe_freetxring(afe_t *afep) 2126 { 2127 int i; 2128 2129 for (i = 0; i < AFE_TXRING; i++) { 2130 afe_destroytxbuf(afep->afe_txbufs[i]); 2131 } 2132 2133 if (afep->afe_txbufs) { 2134 kmem_free(afep->afe_txbufs, 2135 AFE_TXRING * sizeof (afe_txbuf_t *)); 2136 } 2137 if (afep->afe_txdesc_paddr) 2138 (void) ddi_dma_unbind_handle(afep->afe_txdesc_dmah); 2139 if (afep->afe_txdesc_acch) 2140 ddi_dma_mem_free(&afep->afe_txdesc_acch); 2141 if (afep->afe_txdesc_dmah) 2142 ddi_dma_free_handle(&afep->afe_txdesc_dmah); 2143 } 2144 2145 /* 2146 * Interrupt service routine. 2147 */ 2148 unsigned 2149 afe_intr(caddr_t arg) 2150 { 2151 afe_t *afep = (void *)arg; 2152 uint32_t status; 2153 mblk_t *mp = NULL; 2154 2155 mutex_enter(&afep->afe_intrlock); 2156 2157 if (afep->afe_flags & AFE_SUSPENDED) { 2158 /* we cannot receive interrupts! */ 2159 mutex_exit(&afep->afe_intrlock); 2160 return (DDI_INTR_UNCLAIMED); 2161 } 2162 2163 /* check interrupt status bits, did we interrupt? */ 2164 status = GETCSR(afep, CSR_SR2) & INT_ALL; 2165 2166 if (status == 0) { 2167 KIOIP->intrs[KSTAT_INTR_SPURIOUS]++; 2168 mutex_exit(&afep->afe_intrlock); 2169 return (DDI_INTR_UNCLAIMED); 2170 } 2171 /* ack the interrupt */ 2172 PUTCSR(afep, CSR_SR2, status); 2173 KIOIP->intrs[KSTAT_INTR_HARD]++; 2174 2175 if (!(afep->afe_flags & AFE_RUNNING)) { 2176 /* not running, don't touch anything */ 2177 mutex_exit(&afep->afe_intrlock); 2178 return (DDI_INTR_CLAIMED); 2179 } 2180 2181 if (status & (INT_RXOK|INT_RXNOBUF)) { 2182 /* receive packets */ 2183 mp = afe_receive(afep); 2184 if (status & INT_RXNOBUF) 2185 PUTCSR(afep, CSR_RDR, 0); /* wake up chip */ 2186 } 2187 2188 if (status & INT_TXOK) { 2189 /* transmit completed */ 2190 mutex_enter(&afep->afe_xmtlock); 2191 afe_reclaim(afep); 2192 mutex_exit(&afep->afe_xmtlock); 2193 } 2194 2195 if (status & (INT_LINKCHG|INT_TIMER)) { 2196 mutex_enter(&afep->afe_xmtlock); 2197 afe_checklink(afep); 2198 mutex_exit(&afep->afe_xmtlock); 2199 } 2200 2201 if (status & (INT_RXSTOPPED|INT_TXSTOPPED| 2202 INT_RXJABBER|INT_TXJABBER|INT_TXUNDERFLOW)) { 2203 2204 if (status & (INT_RXJABBER | INT_TXJABBER)) { 2205 afep->afe_jabber++; 2206 } 2207 DBG(DWARN, "resetting mac, status %x", status); 2208 mutex_enter(&afep->afe_xmtlock); 2209 afe_resetall(afep); 2210 mutex_exit(&afep->afe_xmtlock); 2211 } 2212 2213 if (status & INT_BUSERR) { 2214 switch (GETCSR(afep, CSR_SR) & SR_BERR_TYPE) { 2215 case SR_BERR_PARITY: 2216 afe_error(afep->afe_dip, "PCI parity error"); 2217 break; 2218 case SR_BERR_TARGET_ABORT: 2219 afe_error(afep->afe_dip, "PCI target abort"); 2220 break; 2221 case SR_BERR_MASTER_ABORT: 2222 afe_error(afep->afe_dip, "PCI master abort"); 2223 break; 2224 default: 2225 afe_error(afep->afe_dip, "Unknown PCI error"); 2226 break; 2227 } 2228 2229 /* reset the chip in an attempt to fix things */ 2230 mutex_enter(&afep->afe_xmtlock); 2231 afe_resetall(afep); 2232 mutex_exit(&afep->afe_xmtlock); 2233 } 2234 2235 mutex_exit(&afep->afe_intrlock); 2236 2237 /* 2238 * Send up packets. We do this outside of the intrlock. 2239 */ 2240 if (mp) { 2241 mac_rx(afep->afe_mh, NULL, mp); 2242 } 2243 2244 return (DDI_INTR_CLAIMED); 2245 } 2246 2247 void 2248 afe_enableinterrupts(afe_t *afep) 2249 { 2250 unsigned mask = INT_WANTED; 2251 2252 if (afep->afe_wantw) 2253 mask |= INT_TXOK; 2254 2255 PUTCSR(afep, CSR_IER2, mask); 2256 2257 if (AFE_MODEL(afep) == MODEL_COMET) { 2258 /* 2259 * On the Comet, this is the internal transceiver 2260 * interrupt. We program the Comet's built-in PHY to 2261 * enable certain interrupts. 2262 */ 2263 PUTCSR16(afep, CSR_XIE, XIE_LDE | XIE_ANCE); 2264 } 2265 } 2266 2267 void 2268 afe_disableinterrupts(afe_t *afep) 2269 { 2270 /* disable further interrupts */ 2271 PUTCSR(afep, CSR_IER2, INT_NONE); 2272 2273 /* clear any pending interrupts */ 2274 PUTCSR(afep, CSR_SR2, INT_ALL); 2275 } 2276 2277 boolean_t 2278 afe_send(afe_t *afep, mblk_t *mp) 2279 { 2280 size_t len; 2281 afe_txbuf_t *txb; 2282 afe_desc_t *tmd; 2283 uint32_t control; 2284 int txsend; 2285 2286 ASSERT(mutex_owned(&afep->afe_xmtlock)); 2287 ASSERT(mp != NULL); 2288 2289 len = msgsize(mp); 2290 if (len > ETHERVLANMTU) { 2291 DBG(DXMIT, "frame too long: %d", len); 2292 afep->afe_macxmt_errors++; 2293 freemsg(mp); 2294 return (B_TRUE); 2295 } 2296 2297 if (afep->afe_txavail < AFE_TXRECLAIM) 2298 afe_reclaim(afep); 2299 2300 if (afep->afe_txavail == 0) { 2301 /* no more tmds */ 2302 afep->afe_wantw = B_TRUE; 2303 /* enable TX interrupt */ 2304 afe_enableinterrupts(afep); 2305 return (B_FALSE); 2306 } 2307 2308 txsend = afep->afe_txsend; 2309 2310 /* 2311 * For simplicity, we just do a copy into a preallocated 2312 * DMA buffer. 2313 */ 2314 2315 txb = afep->afe_txbufs[txsend]; 2316 mcopymsg(mp, txb->txb_buf); /* frees mp! */ 2317 2318 /* 2319 * Statistics. 2320 */ 2321 afep->afe_opackets++; 2322 afep->afe_obytes += len; 2323 if (txb->txb_buf[0] & 0x1) { 2324 if (bcmp(txb->txb_buf, afe_broadcast, ETHERADDRL) != 0) 2325 afep->afe_multixmt++; 2326 else 2327 afep->afe_brdcstxmt++; 2328 } 2329 2330 /* note len is already known to be a small unsigned */ 2331 control = len | TXCTL_FIRST | TXCTL_LAST | TXCTL_INTCMPLTE; 2332 2333 if (txsend == (AFE_TXRING - 1)) 2334 control |= TXCTL_ENDRING; 2335 2336 tmd = &afep->afe_txdescp[txsend]; 2337 2338 SYNCTXBUF(txb, len, DDI_DMA_SYNC_FORDEV); 2339 PUTTXDESC(afep, tmd->desc_control, control); 2340 PUTTXDESC(afep, tmd->desc_buffer1, txb->txb_paddr); 2341 PUTTXDESC(afep, tmd->desc_buffer2, 0); 2342 PUTTXDESC(afep, tmd->desc_status, TXSTAT_OWN); 2343 /* sync the descriptor out to the device */ 2344 SYNCTXDESC(afep, txsend, DDI_DMA_SYNC_FORDEV); 2345 2346 /* 2347 * Note the new values of txavail and txsend. 2348 */ 2349 afep->afe_txavail--; 2350 afep->afe_txsend = (txsend + 1) % AFE_TXRING; 2351 2352 /* 2353 * It should never, ever take more than 5 seconds to drain 2354 * the ring. If it happens, then we are stuck! 2355 */ 2356 afep->afe_txstall_time = gethrtime() + (5 * 1000000000ULL); 2357 2358 /* 2359 * wake up the chip ... inside the lock to protect against DR suspend, 2360 * etc. 2361 */ 2362 PUTCSR(afep, CSR_TDR, 0); 2363 2364 return (B_TRUE); 2365 } 2366 2367 /* 2368 * Reclaim buffers that have completed transmission. 2369 */ 2370 void 2371 afe_reclaim(afe_t *afep) 2372 { 2373 afe_desc_t *tmdp; 2374 2375 while (afep->afe_txavail != AFE_TXRING) { 2376 uint32_t status; 2377 uint32_t control; 2378 int index = afep->afe_txreclaim; 2379 2380 tmdp = &afep->afe_txdescp[index]; 2381 2382 /* sync it before we read it */ 2383 SYNCTXDESC(afep, index, DDI_DMA_SYNC_FORKERNEL); 2384 2385 control = GETTXDESC(afep, tmdp->desc_control); 2386 status = GETTXDESC(afep, tmdp->desc_status); 2387 2388 if (status & TXSTAT_OWN) { 2389 /* chip is still working on it, we're done */ 2390 break; 2391 } 2392 2393 afep->afe_txavail++; 2394 afep->afe_txreclaim = (index + 1) % AFE_TXRING; 2395 2396 /* in the most common successful case, all bits are clear */ 2397 if (status == 0) 2398 continue; 2399 2400 if ((control & TXCTL_LAST) == 0) 2401 continue; 2402 2403 if (status & TXSTAT_TXERR) { 2404 afep->afe_errxmt++; 2405 2406 if (status & TXSTAT_JABBER) { 2407 /* transmit jabber timeout */ 2408 afep->afe_macxmt_errors++; 2409 } 2410 if (status & 2411 (TXSTAT_CARRLOST | TXSTAT_NOCARR)) { 2412 afep->afe_carrier_errors++; 2413 } 2414 if (status & TXSTAT_UFLOW) { 2415 afep->afe_underflow++; 2416 } 2417 if (status & TXSTAT_LATECOL) { 2418 afep->afe_tx_late_collisions++; 2419 } 2420 if (status & TXSTAT_EXCOLL) { 2421 afep->afe_ex_collisions++; 2422 afep->afe_collisions += 16; 2423 } 2424 } 2425 2426 if (status & TXSTAT_DEFER) { 2427 afep->afe_defer_xmts++; 2428 } 2429 2430 /* collision counting */ 2431 if (TXCOLLCNT(status) == 1) { 2432 afep->afe_collisions++; 2433 afep->afe_first_collisions++; 2434 } else if (TXCOLLCNT(status)) { 2435 afep->afe_collisions += TXCOLLCNT(status); 2436 afep->afe_multi_collisions += TXCOLLCNT(status); 2437 } 2438 } 2439 2440 if (afep->afe_txavail >= AFE_TXRESCHED) { 2441 if (afep->afe_wantw) { 2442 /* 2443 * we were able to reclaim some packets, so 2444 * disable tx interrupts 2445 */ 2446 afep->afe_wantw = B_FALSE; 2447 afe_enableinterrupts(afep); 2448 mac_tx_update(afep->afe_mh); 2449 } 2450 } 2451 } 2452 2453 mblk_t * 2454 afe_receive(afe_t *afep) 2455 { 2456 unsigned len; 2457 afe_rxbuf_t *rxb; 2458 afe_desc_t *rmd; 2459 uint32_t status; 2460 mblk_t *mpchain, **mpp, *mp; 2461 int head, cnt; 2462 2463 mpchain = NULL; 2464 mpp = &mpchain; 2465 head = afep->afe_rxhead; 2466 2467 /* limit the number of packets we process to a half ring size */ 2468 for (cnt = 0; cnt < AFE_RXRING / 2; cnt++) { 2469 2470 DBG(DRECV, "receive at index %d", head); 2471 2472 rmd = &afep->afe_rxdescp[head]; 2473 rxb = afep->afe_rxbufs[head]; 2474 2475 SYNCRXDESC(afep, head, DDI_DMA_SYNC_FORKERNEL); 2476 status = GETRXDESC(afep, rmd->desc_status); 2477 if (status & RXSTAT_OWN) { 2478 /* chip is still chewing on it */ 2479 break; 2480 } 2481 2482 /* discard the ethernet frame checksum */ 2483 len = RXLENGTH(status) - ETHERFCSL; 2484 2485 DBG(DRECV, "recv length %d, status %x", len, status); 2486 2487 if ((status & (RXSTAT_ERRS | RXSTAT_FIRST | RXSTAT_LAST)) != 2488 (RXSTAT_FIRST | RXSTAT_LAST)) { 2489 2490 afep->afe_errrcv++; 2491 2492 /* 2493 * Abnormal status bits detected, analyze further. 2494 */ 2495 if ((status & (RXSTAT_LAST|RXSTAT_FIRST)) != 2496 (RXSTAT_LAST|RXSTAT_FIRST)) { 2497 DBG(DRECV, "rx packet overspill"); 2498 if (status & RXSTAT_FIRST) { 2499 afep->afe_toolong_errors++; 2500 } 2501 } else if (status & RXSTAT_DESCERR) { 2502 afep->afe_macrcv_errors++; 2503 2504 } else if (status & RXSTAT_RUNT) { 2505 afep->afe_runt++; 2506 2507 } else if (status & RXSTAT_COLLSEEN) { 2508 /* this should really be rx_late_collisions */ 2509 afep->afe_macrcv_errors++; 2510 2511 } else if (status & RXSTAT_DRIBBLE) { 2512 afep->afe_align_errors++; 2513 2514 } else if (status & RXSTAT_CRCERR) { 2515 afep->afe_fcs_errors++; 2516 2517 } else if (status & RXSTAT_OFLOW) { 2518 afep->afe_overflow++; 2519 } 2520 } 2521 2522 else if (len > ETHERVLANMTU) { 2523 afep->afe_errrcv++; 2524 afep->afe_toolong_errors++; 2525 } 2526 2527 /* 2528 * At this point, the chip thinks the packet is OK. 2529 */ 2530 else { 2531 mp = allocb(len + AFE_HEADROOM, 0); 2532 if (mp == NULL) { 2533 afep->afe_errrcv++; 2534 afep->afe_norcvbuf++; 2535 goto skip; 2536 } 2537 2538 /* sync the buffer before we look at it */ 2539 SYNCRXBUF(rxb, len, DDI_DMA_SYNC_FORKERNEL); 2540 mp->b_rptr += AFE_HEADROOM; 2541 mp->b_wptr = mp->b_rptr + len; 2542 bcopy((char *)rxb->rxb_buf, mp->b_rptr, len); 2543 2544 afep->afe_ipackets++; 2545 afep->afe_rbytes += len; 2546 if (status & RXSTAT_GROUP) { 2547 if (bcmp(mp->b_rptr, afe_broadcast, 2548 ETHERADDRL) == 0) 2549 afep->afe_brdcstrcv++; 2550 else 2551 afep->afe_multircv++; 2552 } 2553 *mpp = mp; 2554 mpp = &mp->b_next; 2555 } 2556 2557 skip: 2558 /* return ring entry to the hardware */ 2559 PUTRXDESC(afep, rmd->desc_status, RXSTAT_OWN); 2560 SYNCRXDESC(afep, head, DDI_DMA_SYNC_FORDEV); 2561 2562 /* advance to next RMD */ 2563 head = (head + 1) % AFE_RXRING; 2564 } 2565 2566 afep->afe_rxhead = head; 2567 2568 return (mpchain); 2569 } 2570 2571 int 2572 afe_getmiibit(afe_t *afep, uint16_t reg, uint16_t bit) 2573 { 2574 unsigned val; 2575 2576 mutex_enter(&afep->afe_xmtlock); 2577 if (afep->afe_flags & AFE_SUSPENDED) { 2578 mutex_exit(&afep->afe_xmtlock); 2579 /* device is suspended */ 2580 return (0); 2581 } 2582 val = afe_miiread(afep, afep->afe_phyaddr, reg); 2583 mutex_exit(&afep->afe_xmtlock); 2584 2585 return (val & bit ? 1 : 0); 2586 } 2587 #define GETMIIBIT(reg, bit) afe_getmiibit(afep, reg, bit) 2588 2589 int 2590 afe_m_stat(void *arg, uint_t stat, uint64_t *val) 2591 { 2592 afe_t *afep = arg; 2593 2594 mutex_enter(&afep->afe_xmtlock); 2595 if ((afep->afe_flags & (AFE_RUNNING|AFE_SUSPENDED)) == AFE_RUNNING) 2596 afe_reclaim(afep); 2597 mutex_exit(&afep->afe_xmtlock); 2598 2599 switch (stat) { 2600 case MAC_STAT_IFSPEED: 2601 *val = afep->afe_ifspeed; 2602 break; 2603 2604 case MAC_STAT_MULTIRCV: 2605 *val = afep->afe_multircv; 2606 break; 2607 2608 case MAC_STAT_BRDCSTRCV: 2609 *val = afep->afe_brdcstrcv; 2610 break; 2611 2612 case MAC_STAT_MULTIXMT: 2613 *val = afep->afe_multixmt; 2614 break; 2615 2616 case MAC_STAT_BRDCSTXMT: 2617 *val = afep->afe_brdcstxmt; 2618 break; 2619 2620 case MAC_STAT_IPACKETS: 2621 *val = afep->afe_ipackets; 2622 break; 2623 2624 case MAC_STAT_RBYTES: 2625 *val = afep->afe_rbytes; 2626 break; 2627 2628 case MAC_STAT_OPACKETS: 2629 *val = afep->afe_opackets; 2630 break; 2631 2632 case MAC_STAT_OBYTES: 2633 *val = afep->afe_obytes; 2634 break; 2635 2636 case MAC_STAT_NORCVBUF: 2637 *val = afep->afe_norcvbuf; 2638 break; 2639 2640 case MAC_STAT_NOXMTBUF: 2641 *val = 0; 2642 break; 2643 2644 case MAC_STAT_COLLISIONS: 2645 *val = afep->afe_collisions; 2646 break; 2647 2648 case MAC_STAT_IERRORS: 2649 *val = afep->afe_errrcv; 2650 break; 2651 2652 case MAC_STAT_OERRORS: 2653 *val = afep->afe_errxmt; 2654 break; 2655 2656 case ETHER_STAT_LINK_DUPLEX: 2657 *val = afep->afe_duplex; 2658 break; 2659 2660 case ETHER_STAT_ALIGN_ERRORS: 2661 *val = afep->afe_align_errors; 2662 break; 2663 2664 case ETHER_STAT_FCS_ERRORS: 2665 *val = afep->afe_fcs_errors; 2666 break; 2667 2668 case ETHER_STAT_SQE_ERRORS: 2669 *val = afep->afe_sqe_errors; 2670 break; 2671 2672 case ETHER_STAT_DEFER_XMTS: 2673 *val = afep->afe_defer_xmts; 2674 break; 2675 2676 case ETHER_STAT_FIRST_COLLISIONS: 2677 *val = afep->afe_first_collisions; 2678 break; 2679 2680 case ETHER_STAT_MULTI_COLLISIONS: 2681 *val = afep->afe_multi_collisions; 2682 break; 2683 2684 case ETHER_STAT_TX_LATE_COLLISIONS: 2685 *val = afep->afe_tx_late_collisions; 2686 break; 2687 2688 case ETHER_STAT_EX_COLLISIONS: 2689 *val = afep->afe_ex_collisions; 2690 break; 2691 2692 case ETHER_STAT_MACXMT_ERRORS: 2693 *val = afep->afe_macxmt_errors; 2694 break; 2695 2696 case ETHER_STAT_CARRIER_ERRORS: 2697 *val = afep->afe_carrier_errors; 2698 break; 2699 2700 case ETHER_STAT_TOOLONG_ERRORS: 2701 *val = afep->afe_toolong_errors; 2702 break; 2703 2704 case ETHER_STAT_MACRCV_ERRORS: 2705 *val = afep->afe_macrcv_errors; 2706 break; 2707 2708 case MAC_STAT_OVERFLOWS: 2709 *val = afep->afe_overflow; 2710 break; 2711 2712 case MAC_STAT_UNDERFLOWS: 2713 *val = afep->afe_underflow; 2714 break; 2715 2716 case ETHER_STAT_TOOSHORT_ERRORS: 2717 *val = afep->afe_runt; 2718 break; 2719 2720 case ETHER_STAT_JABBER_ERRORS: 2721 *val = afep->afe_jabber; 2722 break; 2723 2724 case ETHER_STAT_CAP_100T4: 2725 *val = afep->afe_cap_100T4; 2726 break; 2727 2728 case ETHER_STAT_CAP_100FDX: 2729 *val = afep->afe_cap_100fdx; 2730 break; 2731 2732 case ETHER_STAT_CAP_100HDX: 2733 *val = afep->afe_cap_100hdx; 2734 break; 2735 2736 case ETHER_STAT_CAP_10FDX: 2737 *val = afep->afe_cap_10fdx; 2738 break; 2739 2740 case ETHER_STAT_CAP_10HDX: 2741 *val = afep->afe_cap_10hdx; 2742 break; 2743 2744 case ETHER_STAT_CAP_AUTONEG: 2745 *val = afep->afe_cap_aneg; 2746 break; 2747 2748 case ETHER_STAT_LINK_AUTONEG: 2749 *val = ((afep->afe_adv_aneg != 0) && 2750 (GETMIIBIT(MII_AN_LPABLE, MII_AN_EXP_LPCANAN) != 0)); 2751 break; 2752 2753 case ETHER_STAT_ADV_CAP_100T4: 2754 *val = afep->afe_adv_100T4; 2755 break; 2756 2757 case ETHER_STAT_ADV_CAP_100FDX: 2758 *val = afep->afe_adv_100fdx; 2759 break; 2760 2761 case ETHER_STAT_ADV_CAP_100HDX: 2762 *val = afep->afe_adv_100hdx; 2763 break; 2764 2765 case ETHER_STAT_ADV_CAP_10FDX: 2766 *val = afep->afe_adv_10fdx; 2767 break; 2768 2769 case ETHER_STAT_ADV_CAP_10HDX: 2770 *val = afep->afe_adv_10hdx; 2771 break; 2772 2773 case ETHER_STAT_ADV_CAP_AUTONEG: 2774 *val = afep->afe_adv_aneg; 2775 break; 2776 2777 case ETHER_STAT_LP_CAP_100T4: 2778 *val = GETMIIBIT(MII_AN_LPABLE, MII_ABILITY_100BASE_T4); 2779 break; 2780 2781 case ETHER_STAT_LP_CAP_100FDX: 2782 *val = GETMIIBIT(MII_AN_LPABLE, MII_ABILITY_100BASE_TX_FD); 2783 break; 2784 2785 case ETHER_STAT_LP_CAP_100HDX: 2786 *val = GETMIIBIT(MII_AN_LPABLE, MII_ABILITY_100BASE_TX); 2787 break; 2788 2789 case ETHER_STAT_LP_CAP_10FDX: 2790 *val = GETMIIBIT(MII_AN_LPABLE, MII_ABILITY_10BASE_T_FD); 2791 break; 2792 2793 case ETHER_STAT_LP_CAP_10HDX: 2794 *val = GETMIIBIT(MII_AN_LPABLE, MII_ABILITY_10BASE_T); 2795 break; 2796 2797 case ETHER_STAT_LP_CAP_AUTONEG: 2798 *val = GETMIIBIT(MII_AN_EXPANSION, MII_AN_EXP_LPCANAN); 2799 break; 2800 2801 case ETHER_STAT_XCVR_ADDR: 2802 *val = afep->afe_phyaddr; 2803 break; 2804 2805 case ETHER_STAT_XCVR_ID: 2806 *val = afep->afe_phyid; 2807 break; 2808 2809 default: 2810 return (ENOTSUP); 2811 } 2812 return (0); 2813 } 2814 2815 /*ARGSUSED*/ 2816 int 2817 afe_m_getprop(void *arg, const char *name, mac_prop_id_t num, uint_t flags, 2818 uint_t sz, void *val, uint_t *perm) 2819 { 2820 afe_t *afep = arg; 2821 int err = 0; 2822 boolean_t dfl = flags & MAC_PROP_DEFAULT; 2823 2824 if (sz == 0) 2825 return (EINVAL); 2826 2827 *perm = MAC_PROP_PERM_RW; 2828 switch (num) { 2829 case MAC_PROP_DUPLEX: 2830 *perm = MAC_PROP_PERM_READ; 2831 if (sz >= sizeof (link_duplex_t)) { 2832 bcopy(&afep->afe_duplex, val, sizeof (link_duplex_t)); 2833 } else { 2834 err = EINVAL; 2835 } 2836 break; 2837 2838 case MAC_PROP_SPEED: 2839 *perm = MAC_PROP_PERM_READ; 2840 if (sz >= sizeof (uint64_t)) { 2841 bcopy(&afep->afe_ifspeed, val, sizeof (uint64_t)); 2842 } else { 2843 err = EINVAL; 2844 } 2845 break; 2846 2847 case MAC_PROP_AUTONEG: 2848 *(uint8_t *)val = 2849 dfl ? afep->afe_cap_aneg : afep->afe_adv_aneg; 2850 break; 2851 2852 #if 0 2853 case MAC_PROP_ADV_1000FDX_CAP: 2854 case MAC_PROP_EN_1000FDX_CAP: 2855 case MAC_PROP_ADV_1000HDX_CAP: 2856 case MAC_PROP_EN_1000HDX_CAP: 2857 /* We don't support gigabit! */ 2858 *(uint8_t *)val = 0; 2859 break; 2860 #endif 2861 2862 case MAC_PROP_ADV_100FDX_CAP: 2863 *perm = MAC_PROP_PERM_READ; 2864 *(uint8_t *)val = 2865 dfl ? afep->afe_cap_100fdx : afep->afe_adv_100fdx; 2866 break; 2867 case MAC_PROP_EN_100FDX_CAP: 2868 *(uint8_t *)val = 2869 dfl ? afep->afe_cap_100fdx : afep->afe_adv_100fdx; 2870 break; 2871 2872 case MAC_PROP_ADV_100HDX_CAP: 2873 *perm = MAC_PROP_PERM_READ; 2874 *(uint8_t *)val = 2875 dfl ? afep->afe_cap_100hdx : afep->afe_adv_100hdx; 2876 break; 2877 case MAC_PROP_EN_100HDX_CAP: 2878 *(uint8_t *)val = 2879 dfl ? afep->afe_cap_100hdx : afep->afe_adv_100hdx; 2880 break; 2881 2882 case MAC_PROP_ADV_10FDX_CAP: 2883 *perm = MAC_PROP_PERM_READ; 2884 *(uint8_t *)val = 2885 dfl ? afep->afe_cap_10fdx : afep->afe_adv_10fdx; 2886 break; 2887 case MAC_PROP_EN_10FDX_CAP: 2888 *(uint8_t *)val = 2889 dfl ? afep->afe_cap_10fdx : afep->afe_adv_10fdx; 2890 break; 2891 2892 case MAC_PROP_ADV_10HDX_CAP: 2893 *perm = MAC_PROP_PERM_READ; 2894 *(uint8_t *)val = 2895 dfl ? afep->afe_cap_10hdx : afep->afe_adv_10hdx; 2896 break; 2897 case MAC_PROP_EN_10HDX_CAP: 2898 *(uint8_t *)val = 2899 dfl ? afep->afe_cap_10hdx : afep->afe_adv_10hdx; 2900 break; 2901 2902 case MAC_PROP_ADV_100T4_CAP: 2903 *perm = MAC_PROP_PERM_READ; 2904 *(uint8_t *)val = 2905 dfl ? afep->afe_cap_100T4 : afep->afe_adv_100T4; 2906 break; 2907 case MAC_PROP_EN_100T4_CAP: 2908 *(uint8_t *)val = 2909 dfl ? afep->afe_cap_100T4 : afep->afe_adv_100T4; 2910 break; 2911 2912 default: 2913 err = ENOTSUP; 2914 } 2915 2916 return (err); 2917 } 2918 2919 /*ARGSUSED*/ 2920 int 2921 afe_m_setprop(void *arg, const char *name, mac_prop_id_t num, uint_t sz, 2922 const void *val) 2923 { 2924 afe_t *afep = arg; 2925 uint8_t *advp; 2926 uint8_t *capp; 2927 2928 switch (num) { 2929 case MAC_PROP_EN_100FDX_CAP: 2930 advp = &afep->afe_adv_100fdx; 2931 capp = &afep->afe_cap_100fdx; 2932 break; 2933 2934 case MAC_PROP_EN_100HDX_CAP: 2935 advp = &afep->afe_adv_100hdx; 2936 capp = &afep->afe_cap_100hdx; 2937 break; 2938 2939 case MAC_PROP_EN_10FDX_CAP: 2940 advp = &afep->afe_adv_10fdx; 2941 capp = &afep->afe_cap_10fdx; 2942 break; 2943 2944 case MAC_PROP_EN_10HDX_CAP: 2945 advp = &afep->afe_adv_10hdx; 2946 capp = &afep->afe_cap_10hdx; 2947 break; 2948 2949 case MAC_PROP_EN_100T4_CAP: 2950 advp = &afep->afe_adv_100T4; 2951 capp = &afep->afe_cap_100T4; 2952 break; 2953 2954 case MAC_PROP_AUTONEG: 2955 advp = &afep->afe_adv_aneg; 2956 capp = &afep->afe_cap_aneg; 2957 break; 2958 2959 default: 2960 return (ENOTSUP); 2961 } 2962 2963 if (*capp == 0) /* ensure phy can support value */ 2964 return (ENOTSUP); 2965 2966 mutex_enter(&afep->afe_intrlock); 2967 mutex_enter(&afep->afe_xmtlock); 2968 2969 if (*advp != *(const uint8_t *)val) { 2970 *advp = *(const uint8_t *)val; 2971 2972 if ((afep->afe_flags & (AFE_RUNNING|AFE_SUSPENDED)) == 2973 AFE_RUNNING) { 2974 /* 2975 * This re-initializes the phy, but it also 2976 * restarts transmit and receive rings. 2977 * Needless to say, changing the link 2978 * parameters is destructive to traffic in 2979 * progress. 2980 */ 2981 afe_resetall(afep); 2982 } 2983 } 2984 mutex_exit(&afep->afe_xmtlock); 2985 mutex_exit(&afep->afe_intrlock); 2986 2987 return (0); 2988 } 2989 2990 /* 2991 * Debugging and error reporting. 2992 */ 2993 void 2994 afe_error(dev_info_t *dip, char *fmt, ...) 2995 { 2996 va_list ap; 2997 char buf[256]; 2998 2999 va_start(ap, fmt); 3000 (void) vsnprintf(buf, sizeof (buf), fmt, ap); 3001 va_end(ap); 3002 3003 if (dip) { 3004 cmn_err(CE_WARN, "%s%d: %s", 3005 ddi_driver_name(dip), ddi_get_instance(dip), buf); 3006 } else { 3007 cmn_err(CE_WARN, "afe: %s", buf); 3008 } 3009 } 3010 3011 #ifdef DEBUG 3012 3013 void 3014 afe_dprintf(afe_t *afep, const char *func, int level, char *fmt, ...) 3015 { 3016 va_list ap; 3017 3018 va_start(ap, fmt); 3019 if (afe_debug & level) { 3020 char tag[64]; 3021 char buf[256]; 3022 3023 if (afep && afep->afe_dip) { 3024 (void) snprintf(tag, sizeof (tag), "%s%d", 3025 ddi_driver_name(afep->afe_dip), 3026 ddi_get_instance(afep->afe_dip)); 3027 } else { 3028 (void) snprintf(tag, sizeof (tag), "afe"); 3029 } 3030 3031 (void) snprintf(buf, sizeof (buf), "%s: %s: %s\n", 3032 tag, func, fmt); 3033 3034 vcmn_err(CE_CONT, buf, ap); 3035 } 3036 va_end(ap); 3037 } 3038 3039 #endif 3040