1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2004 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 /* 28 * hci1394_s1394if.c 29 * The interface into the HAL from the services layer. 30 */ 31 32 #include <sys/conf.h> 33 #include <sys/ddi.h> 34 #include <sys/modctl.h> 35 #include <sys/stat.h> 36 #include <sys/sunddi.h> 37 #include <sys/cmn_err.h> 38 39 #include <sys/1394/h1394.h> 40 #include <sys/1394/ixl1394.h> 41 #include <sys/1394/adapters/hci1394.h> 42 43 44 static void hci1394_s1394if_shutdown(void *hal_private); 45 static int hci1394_s1394if_phy(void *hal_private, cmd1394_cmd_t *cmd_id, 46 h1394_cmd_priv_t *cmd_private, int *result); 47 static int hci1394_s1394if_write(void *hal_private, cmd1394_cmd_t *cmd_id, 48 h1394_cmd_priv_t *cmd_private, int *result); 49 static int hci1394_s1394if_read(void *hal_private, cmd1394_cmd_t *cmd_id, 50 h1394_cmd_priv_t *cmd_private, int *result); 51 static int hci1394_s1394if_lock(void *hal_private, cmd1394_cmd_t *cmd_id, 52 h1394_cmd_priv_t *cmd_private, int *result); 53 static int hci1394_s1394if_write_response(void *hal_private, 54 cmd1394_cmd_t *cmd_id, h1394_cmd_priv_t *cmd_private, int *result); 55 static int hci1394_s1394if_read_response(void *hal_private, 56 cmd1394_cmd_t *cmd_id, h1394_cmd_priv_t *cmd_private, int *result); 57 static int hci1394_s1394if_lock_response(void *hal_private, 58 cmd1394_cmd_t *cmd_id, h1394_cmd_priv_t *cmd_private, int *result); 59 static void hci1394_s1394if_response_complete(void *hal_private, 60 cmd1394_cmd_t *cmd_id, h1394_cmd_priv_t *cmd_private); 61 static int hci1394_s1394if_reset_bus(void *hal_private); 62 static int hci1394_s1394if_set_contender_bit(void *hal_private); 63 static int hci1394_s1394if_set_root_holdoff_bit(void *hal_private); 64 static int hci1394_s1394if_set_gap_count(void *hal_private, uint_t gap_count); 65 static int hci1394_s1394if_update_config_rom(void *hal_private, 66 void *local_buf, uint_t quadlet_count); 67 static int hci1394_s1394if_phy_filter_set(void *hal_private, 68 uint64_t mask, uint_t generation); 69 static int hci1394_s1394if_phy_filter_clr(void *hal_private, 70 uint64_t mask, uint_t generation); 71 static int hci1394_s1394if_short_bus_reset(void *hal_private); 72 static int hci1394_s1394if_csr_read(void *hal_private, 73 uint_t offset, uint32_t *data); 74 static int hci1394_s1394if_csr_write(void *hal_private, 75 uint_t offset, uint32_t data); 76 static int hci1394_s1394if_csr_cswap32(void *hal_private, uint_t generation, 77 uint_t offset, uint32_t compare, uint32_t swap, uint32_t *old); 78 static void hci1394_s1394if_power_state_change(void *hal_private, 79 h1394_node_pwr_flags_t nodeflags); 80 81 82 /* entry points into HAL from Services Layer */ 83 h1394_evts_t hci1394_evts = { 84 H1394_EVTS_V1, /* hal_version */ 85 0, /* reserved */ 86 hci1394_s1394if_shutdown, /* shutdown */ 87 hci1394_s1394if_phy, /* send_phy_config_pkt */ 88 hci1394_s1394if_read, /* read */ 89 hci1394_s1394if_read_response, /* read_response */ 90 hci1394_s1394if_write, /* write */ 91 hci1394_s1394if_write_response, /* write_response */ 92 hci1394_s1394if_response_complete, /* response_complete */ 93 hci1394_s1394if_lock, /* lock */ 94 hci1394_s1394if_lock_response, /* lock_response */ 95 hci1394_alloc_isoch_dma, /* allocate_isoch_dma */ 96 hci1394_free_isoch_dma, /* free_isoch_dma */ 97 hci1394_start_isoch_dma, /* start_isoch_dma */ 98 hci1394_stop_isoch_dma, /* stop_isoch_dma */ 99 hci1394_update_isoch_dma, /* update_isoch_dma */ 100 hci1394_s1394if_update_config_rom, /* update_config_rom */ 101 hci1394_s1394if_reset_bus, /* bus_reset */ 102 hci1394_s1394if_short_bus_reset, /* short_bus_reset */ 103 hci1394_s1394if_set_contender_bit, /* set_contender_bit */ 104 hci1394_s1394if_set_root_holdoff_bit, /* set_root_holdoff_bit */ 105 hci1394_s1394if_set_gap_count, /* set_gap_count */ 106 hci1394_s1394if_csr_read, /* csr_read */ 107 hci1394_s1394if_csr_write, /* csr_write */ 108 hci1394_s1394if_csr_cswap32, /* csr_cswap32 */ 109 hci1394_s1394if_phy_filter_set, /* phys_arreq_enable_set */ 110 hci1394_s1394if_phy_filter_clr, /* phys_arreq_enable_clr */ 111 hci1394_s1394if_power_state_change /* node_power_state_change */ 112 }; 113 114 115 /* 116 * hci1394_s1394if_shutdown() 117 * Shutdown the HAL. This is called when a critical error has been detected. 118 * This routine should shutdown the HAL so that it will no longer send or 119 * receive information to/from the 1394 bus. The purpose of this function is 120 * to try and keep the machine from crashing. 121 */ 122 static void 123 hci1394_s1394if_shutdown(void *hal_private) 124 { 125 hci1394_state_t *soft_state; 126 127 128 ASSERT(hal_private != NULL); 129 130 soft_state = (hci1394_state_t *)hal_private; 131 hci1394_shutdown(soft_state->drvinfo.di_dip); 132 } 133 134 135 /* 136 * hci1394_s1394if_phy() 137 * write a phy packet out to the 1394 bus. A phy packet consists of one 138 * quadlet of data. 139 */ 140 static int 141 hci1394_s1394if_phy(void *hal_private, cmd1394_cmd_t *cmd_id, 142 h1394_cmd_priv_t *cmd_private, int *result) 143 { 144 hci1394_state_t *soft_state; 145 int status; 146 147 148 ASSERT(hal_private != NULL); 149 150 soft_state = (hci1394_state_t *)hal_private; 151 152 /* make sure we are not in a bus reset or shutdown */ 153 if (hci1394_state(&soft_state->drvinfo) != HCI1394_NORMAL) { 154 if (hci1394_state(&soft_state->drvinfo) == HCI1394_BUS_RESET) { 155 *result = H1394_STATUS_INVALID_BUSGEN; 156 } else { 157 *result = H1394_STATUS_INTERNAL_ERROR; 158 } 159 return (DDI_FAILURE); 160 } 161 162 status = hci1394_async_phy(soft_state->async, cmd_id, cmd_private, 163 result); 164 if (status != DDI_SUCCESS) { 165 return (DDI_FAILURE); 166 } 167 168 return (DDI_SUCCESS); 169 } 170 171 172 /* 173 * hci1394_s1394if_write() 174 * Perform a 1394 write operation. This can be either a quadlet or block 175 * write. 176 */ 177 static int 178 hci1394_s1394if_write(void *hal_private, cmd1394_cmd_t *cmd_id, 179 h1394_cmd_priv_t *cmd_private, int *result) 180 { 181 hci1394_state_t *soft_state; 182 int status; 183 184 185 ASSERT(hal_private != NULL); 186 187 soft_state = (hci1394_state_t *)hal_private; 188 189 /* make sure we are not in a bus reset or shutdown */ 190 if (hci1394_state(&soft_state->drvinfo) != HCI1394_NORMAL) { 191 if (hci1394_state(&soft_state->drvinfo) == HCI1394_BUS_RESET) { 192 *result = H1394_STATUS_INVALID_BUSGEN; 193 } else { 194 *result = H1394_STATUS_INTERNAL_ERROR; 195 } 196 return (DDI_FAILURE); 197 } 198 199 status = hci1394_async_write(soft_state->async, cmd_id, cmd_private, 200 result); 201 if (status != DDI_SUCCESS) { 202 return (DDI_FAILURE); 203 } 204 205 return (DDI_SUCCESS); 206 } 207 208 209 /* 210 * hci1394_s1394if_read() 211 * Perform a 1394 read operation. This can be either a quadlet or block 212 * read. 213 */ 214 static int 215 hci1394_s1394if_read(void *hal_private, cmd1394_cmd_t *cmd_id, 216 h1394_cmd_priv_t *cmd_private, int *result) 217 { 218 hci1394_state_t *soft_state; 219 int status; 220 221 222 ASSERT(hal_private != NULL); 223 224 soft_state = (hci1394_state_t *)hal_private; 225 226 /* make sure we are not in a bus reset or shutdown */ 227 if (hci1394_state(&soft_state->drvinfo) != HCI1394_NORMAL) { 228 if (hci1394_state(&soft_state->drvinfo) == HCI1394_BUS_RESET) { 229 *result = H1394_STATUS_INVALID_BUSGEN; 230 } else { 231 *result = H1394_STATUS_INTERNAL_ERROR; 232 } 233 return (DDI_FAILURE); 234 } 235 236 status = hci1394_async_read(soft_state->async, cmd_id, cmd_private, 237 result); 238 if (status != DDI_SUCCESS) { 239 return (DDI_FAILURE); 240 } 241 242 return (DDI_SUCCESS); 243 } 244 245 246 /* 247 * hci1394_s1394if_lock() 248 * Perform a 1394/1212 lock operation. This can be one of the following lock 249 * operations: (CMD1394_LOCK_MASK_SWAP, CMD1394_LOCK_COMPARE_SWAP 250 * CMD1394_LOCK_FETCH_ADD, CMD1394_LOCK_LITTLE_ADD, CMD1394_LOCK_BOUNDED_ADD 251 * CMD1394_LOCK_WRAP_ADD) 252 */ 253 static int 254 hci1394_s1394if_lock(void *hal_private, cmd1394_cmd_t *cmd_id, 255 h1394_cmd_priv_t *cmd_private, int *result) 256 { 257 hci1394_state_t *soft_state; 258 int status; 259 260 261 ASSERT(hal_private != NULL); 262 263 soft_state = (hci1394_state_t *)hal_private; 264 265 /* make sure we are not in a bus reset or shutdown */ 266 if (hci1394_state(&soft_state->drvinfo) != HCI1394_NORMAL) { 267 if (hci1394_state(&soft_state->drvinfo) == HCI1394_BUS_RESET) { 268 *result = H1394_STATUS_INVALID_BUSGEN; 269 } else { 270 *result = H1394_STATUS_INTERNAL_ERROR; 271 } 272 return (DDI_FAILURE); 273 } 274 275 status = hci1394_async_lock(soft_state->async, cmd_id, cmd_private, 276 result); 277 if (status != DDI_SUCCESS) { 278 return (DDI_FAILURE); 279 } 280 281 return (DDI_SUCCESS); 282 } 283 284 285 /* 286 * hci1394_s1394if_write_response() 287 * Send a response to a write request received off of the 1394 bus. This 288 * could have been with a quadlet or block write request. 289 */ 290 static int 291 hci1394_s1394if_write_response(void *hal_private, cmd1394_cmd_t *cmd_id, 292 h1394_cmd_priv_t *cmd_private, int *result) 293 { 294 hci1394_state_t *soft_state; 295 int status; 296 297 298 ASSERT(hal_private != NULL); 299 300 soft_state = (hci1394_state_t *)hal_private; 301 302 /* make sure we are not in a bus reset or shutdown */ 303 if (hci1394_state(&soft_state->drvinfo) != HCI1394_NORMAL) { 304 if (hci1394_state(&soft_state->drvinfo) == HCI1394_BUS_RESET) { 305 *result = H1394_STATUS_INVALID_BUSGEN; 306 } else { 307 *result = H1394_STATUS_INTERNAL_ERROR; 308 } 309 return (DDI_FAILURE); 310 } 311 312 status = hci1394_async_write_response(soft_state->async, cmd_id, 313 cmd_private, result); 314 if (status != DDI_SUCCESS) { 315 return (DDI_FAILURE); 316 } 317 318 return (DDI_SUCCESS); 319 } 320 321 322 /* 323 * hci1394_s1394if_read_response() 324 * Send a response to a read request received off of the 1394 bus. This 325 * could have been with a quadlet or block read request. 326 */ 327 static int 328 hci1394_s1394if_read_response(void *hal_private, cmd1394_cmd_t *cmd_id, 329 h1394_cmd_priv_t *cmd_private, int *result) 330 { 331 hci1394_state_t *soft_state; 332 int status; 333 334 335 ASSERT(hal_private != NULL); 336 337 soft_state = (hci1394_state_t *)hal_private; 338 339 /* make sure we are not in a bus reset or shutdown */ 340 if (hci1394_state(&soft_state->drvinfo) != HCI1394_NORMAL) { 341 if (hci1394_state(&soft_state->drvinfo) == HCI1394_BUS_RESET) { 342 *result = H1394_STATUS_INVALID_BUSGEN; 343 } else { 344 *result = H1394_STATUS_INTERNAL_ERROR; 345 } 346 return (DDI_FAILURE); 347 } 348 349 status = hci1394_async_read_response(soft_state->async, cmd_id, 350 cmd_private, result); 351 if (status != DDI_SUCCESS) { 352 return (DDI_FAILURE); 353 } 354 355 return (DDI_SUCCESS); 356 } 357 358 359 /* 360 * hci1394_s1394if_lock_response() 361 * Send a response to a lock request received off of the 1394 bus. This 362 * could have been one of the following lock operations: 363 * (CMD1394_LOCK_MASK_SWAP, CMD1394_LOCK_COMPARE_SWAP CMD1394_LOCK_FETCH_ADD, 364 * CMD1394_LOCK_LITTLE_ADD, CMD1394_LOCK_BOUNDED_ADD, CMD1394_LOCK_WRAP_ADD) 365 */ 366 static int 367 hci1394_s1394if_lock_response(void *hal_private, cmd1394_cmd_t *cmd_id, 368 h1394_cmd_priv_t *cmd_private, int *result) 369 { 370 hci1394_state_t *soft_state; 371 int status; 372 373 374 ASSERT(hal_private != NULL); 375 376 soft_state = (hci1394_state_t *)hal_private; 377 378 /* make sure we are not in a bus reset or shutdown */ 379 if (hci1394_state(&soft_state->drvinfo) != HCI1394_NORMAL) { 380 if (hci1394_state(&soft_state->drvinfo) == HCI1394_BUS_RESET) { 381 *result = H1394_STATUS_INVALID_BUSGEN; 382 } else { 383 *result = H1394_STATUS_INTERNAL_ERROR; 384 } 385 return (DDI_FAILURE); 386 } 387 388 status = hci1394_async_lock_response(soft_state->async, cmd_id, 389 cmd_private, result); 390 if (status != DDI_SUCCESS) { 391 return (DDI_FAILURE); 392 } 393 394 return (DDI_SUCCESS); 395 } 396 397 398 /* 399 * hci1394_s1394if_response_complete() 400 * This notifies the HAL that the services layer and target driver are done 401 * with a command that was received off of the 1394 bus. This will usually 402 * be called after the response to the command has been command_complete'd. 403 * The HAL is free to re-use the command or free up the memory from this 404 * command after this call has returned. This should only be called for 405 * ARREQ's. 406 */ 407 static void 408 hci1394_s1394if_response_complete(void *hal_private, cmd1394_cmd_t *cmd_id, 409 h1394_cmd_priv_t *cmd_private) 410 { 411 hci1394_state_t *soft_state; 412 413 ASSERT(hal_private != NULL); 414 soft_state = (hci1394_state_t *)hal_private; 415 hci1394_async_response_complete(soft_state->async, cmd_id, cmd_private); 416 } 417 418 419 /* 420 * hci1394_s1394if_reset_bus() 421 * This routine resets the 1394 bus. It performs a "long" bus reset. It 422 * should work on all OpenHCI adapters. 423 */ 424 static int 425 hci1394_s1394if_reset_bus(void *hal_private) 426 { 427 hci1394_state_t *soft_state; 428 int status; 429 430 431 ASSERT(hal_private != NULL); 432 433 soft_state = (hci1394_state_t *)hal_private; 434 435 /* make sure we are not shutdown */ 436 if (hci1394_state(&soft_state->drvinfo) == HCI1394_SHUTDOWN) { 437 return (DDI_FAILURE); 438 } 439 440 status = hci1394_ohci_bus_reset(soft_state->ohci); 441 if (status != DDI_SUCCESS) { 442 return (DDI_FAILURE); 443 } 444 445 return (DDI_SUCCESS); 446 } 447 448 449 /* 450 * hci1394_s1394if_set_contender_bit() 451 * This routine sets up the PHY so that the selfid contender bit will be set 452 * on subsequent bus resets. This routine will fail when we have a 1394-1995 453 * PHY since this PHY does not have a SW controllable contender bit. 454 */ 455 static int 456 hci1394_s1394if_set_contender_bit(void *hal_private) 457 { 458 hci1394_state_t *soft_state; 459 int status; 460 461 462 ASSERT(hal_private != NULL); 463 464 soft_state = (hci1394_state_t *)hal_private; 465 466 /* make sure we are not shutdown */ 467 if (hci1394_state(&soft_state->drvinfo) == HCI1394_SHUTDOWN) { 468 return (DDI_FAILURE); 469 } 470 471 if (soft_state->halinfo.phy == H1394_PHY_1995) { 472 return (DDI_FAILURE); 473 } 474 475 status = hci1394_ohci_contender_enable(soft_state->ohci); 476 if (status != DDI_SUCCESS) { 477 return (DDI_FAILURE); 478 } 479 480 return (DDI_SUCCESS); 481 } 482 483 484 /* 485 * hci1394_s1394if_set_root_holdoff_bit() 486 * This routine will set the root holdoff bit in the PHY. The Services Layer 487 * should send out a PHY configuration packet first to tell everyone which 488 * node to set the root holdoff bit on. If it is our root holdoff bit we 489 * are setting, the PHY will automatically set it unless we have an old 490 * (1394-1995) PHY. If we have a 1394-1995 PHY, the SL needs to call this 491 * routine after sending the PHY configuration packet. The SL also needs to 492 * call this if they want to perform a long bus reset and have the root 493 * holdoff bit set. We do this so that we do not have to do a read before 494 * the write. A PHY register write has less of a chance of failing. 495 */ 496 static int 497 hci1394_s1394if_set_root_holdoff_bit(void *hal_private) 498 { 499 hci1394_state_t *soft_state; 500 int status; 501 502 503 ASSERT(hal_private != NULL); 504 505 soft_state = (hci1394_state_t *)hal_private; 506 507 /* make sure we are not shutdown */ 508 if (hci1394_state(&soft_state->drvinfo) == HCI1394_SHUTDOWN) { 509 return (DDI_FAILURE); 510 } 511 512 status = hci1394_ohci_root_holdoff_enable(soft_state->ohci); 513 if (status != DDI_SUCCESS) { 514 return (DDI_FAILURE); 515 } 516 517 return (DDI_SUCCESS); 518 } 519 520 521 /* 522 * hci1394_s1394if_set_gap_count() 523 * This routine will set the gap count bit in the PHY. The Services Layer 524 * should send out a PHY configuration packet first to tell everyone what 525 * gap count to use. Our PHY will automatically set the gap count unless we 526 * have an old (1394-1995) PHY. If we have a 1394-1995 PHY, the SL needs to 527 * call this routine after sending the PHY configuration packet and before 528 * generating a bus reset. The SL also needs to call before the they call to 529 * perform a long bus reset. We do this so that we do not have to do a PHY 530 * read before the write. A PHY register write has less of a chance of 531 * failing. 532 */ 533 static int 534 hci1394_s1394if_set_gap_count(void *hal_private, uint_t gap_count) 535 { 536 hci1394_state_t *soft_state; 537 int status; 538 539 540 ASSERT(hal_private != NULL); 541 542 soft_state = (hci1394_state_t *)hal_private; 543 544 /* make sure we are not shutdown */ 545 if (hci1394_state(&soft_state->drvinfo) == HCI1394_SHUTDOWN) { 546 return (DDI_FAILURE); 547 } 548 549 status = hci1394_ohci_gap_count_set(soft_state->ohci, gap_count); 550 if (status != DDI_SUCCESS) { 551 return (DDI_FAILURE); 552 } 553 554 return (DDI_SUCCESS); 555 } 556 557 558 /* 559 * hci1394_s1394if_phy_filter_set() 560 * reads/writes to physically mapped memory from devices on the bus are 561 * disabled by default. They can be enabled on a node by node basis. All 562 * physical accesses are disabled every bus reset so they must be re-enabled 563 * every bus reset (This is due to the fact the the node ids change every bus 564 * reset). A 64-bit mask is passed in to enable nodes to be able to rd/wr 565 * physically mapped memory over the 1394 bus. A bit = to 1 enables that 566 * node's physical accesses, a bit = to 0 does nothing (i.e. a bitwise or is 567 * performed). The LSB of the mask (bit 0), maps to node #0, bit #62, maps to 568 * node 62. The MSB (#63) is not used since the can only be 63 nodes 569 * (0 - 62) on the bus. 570 * 571 * hci1394_s1394if_phy_filter_clr() is used to disable access to physical 572 * memory. This is only required if the node had previously been enabled. 573 * 574 * generation is used to verify that we are have not gotten a bus reset since 575 * the mask was built. 576 */ 577 static int 578 hci1394_s1394if_phy_filter_set(void *hal_private, 579 uint64_t mask, uint_t generation) 580 { 581 hci1394_state_t *soft_state; 582 int status; 583 584 585 ASSERT(hal_private != NULL); 586 587 soft_state = (hci1394_state_t *)hal_private; 588 589 /* make sure we are not shutdown */ 590 if (hci1394_state(&soft_state->drvinfo) == HCI1394_SHUTDOWN) { 591 return (DDI_FAILURE); 592 } 593 594 status = hci1394_ohci_phy_filter_set(soft_state->ohci, mask, 595 generation); 596 if (status != DDI_SUCCESS) { 597 return (DDI_FAILURE); 598 } 599 600 return (DDI_SUCCESS); 601 } 602 603 604 /* 605 * hci1394_s1394if_phy_filter_clr() 606 * reads/writes to physically mapped memory from devices on the bus are 607 * disabled by default. They can be enabled/disabled on a node by node basis. 608 * All physical accesses are disabled every bus reset so they must be 609 * re-enabled every bus reset (This is due to the fact the the node ids 610 * change every bus reset). Only nodes which have been enabled and no longer 611 * need access to physical memory need to be disabled. 612 * 613 * A 64-bit mask is passed in to disable nodes from being able to rd/wr 614 * physically mapped memory over the 1394 bus. A bit = to 1 disables that 615 * node's physical accesses, a bit = to 0 does nothing (i.e. a bitwise or is 616 * performed). The LSB of the mask (bit 0), maps to node #0, bit #62, maps to 617 * node 62. The MSB (#63) is not used since there can only be 63 nodes 618 * (0 - 62) on the bus. 619 * 620 * hci1394_s1394if_phy_filter_set() is used to enable access to physical 621 * memory. 622 * 623 * generation is used to verify that we are have not gotten a bus reset since 624 * the mask was build. 625 */ 626 static int 627 hci1394_s1394if_phy_filter_clr(void *hal_private, 628 uint64_t mask, uint_t generation) 629 { 630 hci1394_state_t *soft_state; 631 int status; 632 633 634 ASSERT(hal_private != NULL); 635 636 soft_state = (hci1394_state_t *)hal_private; 637 638 /* make sure we are not shutdown */ 639 if (hci1394_state(&soft_state->drvinfo) == HCI1394_SHUTDOWN) { 640 return (DDI_FAILURE); 641 } 642 643 status = hci1394_ohci_phy_filter_clr(soft_state->ohci, mask, 644 generation); 645 if (status != DDI_SUCCESS) { 646 return (DDI_FAILURE); 647 } 648 649 return (DDI_SUCCESS); 650 } 651 652 653 /* 654 * hci1394_s1394if_short_bus_reset() 655 * This routine resets the 1394 bus. It performs a "short" bus reset. It 656 * will only work on adapters with a 1394A or later PHY. Calling this routine 657 * when we have a 1394-1995 PHY is an error. 658 */ 659 static int 660 hci1394_s1394if_short_bus_reset(void *hal_private) 661 { 662 hci1394_state_t *soft_state; 663 int status; 664 665 666 ASSERT(hal_private != NULL); 667 668 soft_state = (hci1394_state_t *)hal_private; 669 670 /* make sure we are not shutdown */ 671 if (hci1394_state(&soft_state->drvinfo) == HCI1394_SHUTDOWN) { 672 return (DDI_FAILURE); 673 } 674 675 if (soft_state->halinfo.phy == H1394_PHY_1995) { 676 return (DDI_FAILURE); 677 } 678 679 status = hci1394_ohci_bus_reset_short(soft_state->ohci); 680 if (status != DDI_SUCCESS) { 681 return (DDI_FAILURE); 682 } 683 684 return (DDI_SUCCESS); 685 } 686 687 688 /* 689 * hci1394_s1394if_update_config_rom() 690 * This routine updates the configuration ROM. It copies "quadlet_count" 691 * 32-bit words from "local_buf" to the config ROM starting at the first 692 * location in config ROM. This routine is meant to update the entire config 693 * ROM and not meant for a partial update. 694 */ 695 static int 696 hci1394_s1394if_update_config_rom(void *hal_private, 697 void *local_buf, uint_t quadlet_count) 698 { 699 hci1394_state_t *soft_state; 700 701 702 ASSERT(hal_private != NULL); 703 ASSERT(local_buf != NULL); 704 705 soft_state = (hci1394_state_t *)hal_private; 706 707 /* make sure we are not shutdown */ 708 if (hci1394_state(&soft_state->drvinfo) == HCI1394_SHUTDOWN) { 709 return (DDI_FAILURE); 710 } 711 712 hci1394_ohci_cfgrom_update(soft_state->ohci, local_buf, quadlet_count); 713 714 return (DDI_SUCCESS); 715 } 716 717 718 /* 719 * hci1394_s1394if_csr_read() 720 * CSR register read interface 721 * For more information on CSR registers, see 722 * IEEE 1212 723 * IEEE 1394-1995 724 * section 8.3.2 725 * IEEE P1394A Draft 3.0 726 * sections 10.32,10.33 727 */ 728 static int 729 hci1394_s1394if_csr_read(void *hal_private, uint_t offset, uint32_t *data) 730 { 731 hci1394_state_t *soft_state; 732 int status; 733 734 735 ASSERT(hal_private != NULL); 736 ASSERT(data != NULL); 737 738 soft_state = (hci1394_state_t *)hal_private; 739 740 /* make sure we are not shutdown */ 741 if (hci1394_state(&soft_state->drvinfo) == HCI1394_SHUTDOWN) { 742 return (DDI_FAILURE); 743 } 744 745 switch (offset) { 746 case CSR_STATE_CLEAR: 747 hci1394_csr_state_get(soft_state->csr, data); 748 status = DDI_SUCCESS; 749 break; 750 case CSR_STATE_SET: 751 /* Write Only Register */ 752 status = DDI_FAILURE; 753 break; 754 case CSR_NODE_IDS: 755 hci1394_ohci_nodeid_get(soft_state->ohci, data); 756 status = DDI_SUCCESS; 757 break; 758 case CSR_RESET_START: 759 /* Not supported */ 760 status = DDI_FAILURE; 761 break; 762 case CSR_SPLIT_TIMEOUT_HI: 763 hci1394_csr_split_timeout_hi_get(soft_state->csr, data); 764 status = DDI_SUCCESS; 765 break; 766 case CSR_SPLIT_TIMEOUT_LO: 767 hci1394_csr_split_timeout_lo_get(soft_state->csr, data); 768 status = DDI_SUCCESS; 769 break; 770 case CSR_CYCLE_TIME: 771 /* CYCLE_TIME is implemented in HW */ 772 hci1394_ohci_cycletime_get(soft_state->ohci, data); 773 status = DDI_SUCCESS; 774 break; 775 case CSR_BUS_TIME: 776 /* BUS_TIME is implemented in the hci1394_ohci_* SW */ 777 hci1394_ohci_bustime_get(soft_state->ohci, data); 778 status = DDI_SUCCESS; 779 break; 780 case CSR_BUSY_TIMEOUT: 781 hci1394_ohci_atreq_retries_get(soft_state->ohci, data); 782 status = DDI_SUCCESS; 783 break; 784 case CSR_BUS_MANAGER_ID: 785 /* BUS_MANAGER_ID is implemented in HW */ 786 status = hci1394_ohci_csr_read(soft_state->ohci, 0, data); 787 break; 788 case CSR_BANDWIDTH_AVAILABLE: 789 /* BANDWIDTH_AVAILABLE is implemented in HW */ 790 status = hci1394_ohci_csr_read(soft_state->ohci, 1, data); 791 break; 792 case CSR_CHANNELS_AVAILABLE_HI: 793 /* CHANNELS_AVAILABLE_HI is implemented in HW */ 794 status = hci1394_ohci_csr_read(soft_state->ohci, 2, data); 795 break; 796 case CSR_CHANNELS_AVAILABLE_LO: 797 /* CHANNELS_AVAILABLE_LO is implemented in HW */ 798 status = hci1394_ohci_csr_read(soft_state->ohci, 3, data); 799 break; 800 default: 801 status = DDI_FAILURE; 802 break; 803 } 804 805 return (status); 806 } 807 808 809 /* 810 * hci1394_s1394if_csr_write() 811 * CSR register write interface 812 * For more information on CSR registers, see 813 * IEEE 1212 814 * IEEE 1394-1995 815 * section 8.3.2 816 * IEEE P1394A Draft 3.0 817 * sections 10.32,10.33 818 */ 819 static int 820 hci1394_s1394if_csr_write(void *hal_private, uint_t offset, uint32_t data) 821 { 822 hci1394_state_t *soft_state; 823 int status; 824 825 826 ASSERT(hal_private != NULL); 827 828 soft_state = (hci1394_state_t *)hal_private; 829 830 /* make sure we are not shutdown */ 831 if (hci1394_state(&soft_state->drvinfo) == HCI1394_SHUTDOWN) { 832 return (DDI_FAILURE); 833 } 834 835 switch (offset) { 836 case CSR_STATE_CLEAR: 837 hci1394_csr_state_bclr(soft_state->csr, data); 838 status = DDI_SUCCESS; 839 break; 840 case CSR_STATE_SET: 841 hci1394_csr_state_bset(soft_state->csr, data); 842 status = DDI_SUCCESS; 843 break; 844 case CSR_NODE_IDS: 845 hci1394_ohci_nodeid_set(soft_state->ohci, data); 846 status = DDI_SUCCESS; 847 break; 848 case CSR_RESET_START: 849 /* Not supported */ 850 status = DDI_FAILURE; 851 break; 852 853 /* 854 * there is a race condition when updating the split timeout 855 * due to the nature of the interface. (i.e. having a separate 856 * hi an lo register) 857 */ 858 case CSR_SPLIT_TIMEOUT_HI: 859 hci1394_csr_split_timeout_hi_set(soft_state->csr, data); 860 /* 861 * update the pending list timeout value. The split timeout 862 * is stored in 1394 bus cycles and the timeout is specified in 863 * nS. Therefore, we need to convert the split timeout into nS. 864 */ 865 hci1394_async_pending_timeout_update(soft_state->async, 866 OHCI_BUS_CYCLE_TO_nS(hci1394_csr_split_timeout_get( 867 soft_state->csr))); 868 status = DDI_SUCCESS; 869 break; 870 case CSR_SPLIT_TIMEOUT_LO: 871 hci1394_csr_split_timeout_lo_set(soft_state->csr, data); 872 /* 873 * update the pending list timeout value. The split timeout 874 * is stored in 1394 bus cycles and the timeout is specified in 875 * nS. Therefore, we need to convert the split timeout into nS. 876 */ 877 hci1394_async_pending_timeout_update(soft_state->async, 878 OHCI_BUS_CYCLE_TO_nS(hci1394_csr_split_timeout_get( 879 soft_state->csr))); 880 status = DDI_SUCCESS; 881 break; 882 883 case CSR_CYCLE_TIME: 884 hci1394_ohci_cycletime_set(soft_state->ohci, data); 885 status = DDI_SUCCESS; 886 break; 887 case CSR_BUS_TIME: 888 hci1394_ohci_bustime_set(soft_state->ohci, data); 889 status = DDI_SUCCESS; 890 break; 891 case CSR_BUSY_TIMEOUT: 892 hci1394_ohci_atreq_retries_set(soft_state->ohci, data); 893 status = DDI_SUCCESS; 894 break; 895 case CSR_BUS_MANAGER_ID: 896 /* Invalid access, only read/cswap32 allowed */ 897 status = DDI_FAILURE; 898 break; 899 case CSR_BANDWIDTH_AVAILABLE: 900 /* Invalid access, only read/cswap32 allowed */ 901 status = DDI_FAILURE; 902 break; 903 case CSR_CHANNELS_AVAILABLE_HI: 904 /* Invalid access, only read/cswap32 allowed */ 905 status = DDI_FAILURE; 906 break; 907 case CSR_CHANNELS_AVAILABLE_LO: 908 /* Invalid access, only read/cswap32 allowed */ 909 status = DDI_FAILURE; 910 break; 911 default: 912 status = DDI_FAILURE; 913 break; 914 } 915 916 return (status); 917 } 918 919 920 /* 921 * hci1394_s1394if_csr_cswap32() 922 * CSR register cswap32 interface 923 * For more information on CSR registers, see 924 * IEEE 1212 925 * IEEE 1394-1995 926 * section 8.3.2 927 * IEEE P1394A Draft 3.0 928 * sections 10.32,10.33 929 */ 930 static int 931 hci1394_s1394if_csr_cswap32(void *hal_private, uint_t generation, uint_t offset, 932 uint32_t compare, uint32_t swap, uint32_t *old) 933 { 934 hci1394_state_t *soft_state; 935 int status; 936 937 938 ASSERT(hal_private != NULL); 939 ASSERT(old != NULL); 940 941 soft_state = (hci1394_state_t *)hal_private; 942 943 /* make sure we are not shutdown */ 944 if (hci1394_state(&soft_state->drvinfo) == HCI1394_SHUTDOWN) { 945 return (DDI_FAILURE); 946 } 947 948 switch (offset) { 949 case CSR_STATE_CLEAR: 950 /* Invalid access, only read/write allowed */ 951 status = DDI_FAILURE; 952 break; 953 case CSR_STATE_SET: 954 /* Invalid access, only write allowed */ 955 status = DDI_FAILURE; 956 break; 957 case CSR_NODE_IDS: 958 /* Invalid access, only read/write allowed */ 959 status = DDI_FAILURE; 960 break; 961 case CSR_RESET_START: 962 /* Invalid access, only read/write allowed */ 963 status = DDI_FAILURE; 964 break; 965 case CSR_SPLIT_TIMEOUT_HI: 966 /* Invalid access, only read/write allowed */ 967 status = DDI_FAILURE; 968 break; 969 case CSR_SPLIT_TIMEOUT_LO: 970 /* Invalid access, only read/write allowed */ 971 status = DDI_FAILURE; 972 break; 973 case CSR_CYCLE_TIME: 974 /* Invalid access, only read/write allowed */ 975 status = DDI_FAILURE; 976 break; 977 case CSR_BUS_TIME: 978 /* Invalid access, only read/write allowed */ 979 status = DDI_FAILURE; 980 break; 981 case CSR_BUSY_TIMEOUT: 982 /* Invalid access, only read/write allowed */ 983 status = DDI_FAILURE; 984 break; 985 case CSR_BUS_MANAGER_ID: 986 /* BUS_MANAGER_ID is implemented in HW */ 987 status = hci1394_ohci_csr_cswap(soft_state->ohci, generation, 988 OHCI_CSR_SEL_BUS_MGR_ID, compare, swap, old); 989 break; 990 case CSR_BANDWIDTH_AVAILABLE: 991 /* BANDWIDTH_AVAILABLE is implemented in HW */ 992 status = hci1394_ohci_csr_cswap(soft_state->ohci, generation, 993 OHCI_CSR_SEL_BANDWIDTH_AVAIL, compare, swap, old); 994 break; 995 case CSR_CHANNELS_AVAILABLE_HI: 996 /* CHANNELS_AVAILABLE_HI is implemented in HW */ 997 status = hci1394_ohci_csr_cswap(soft_state->ohci, generation, 998 OHCI_CSR_SEL_CHANS_AVAIL_HI, compare, swap, old); 999 break; 1000 case CSR_CHANNELS_AVAILABLE_LO: 1001 /* CHANNELS_AVAILABLE_LO is implemented in HW */ 1002 status = hci1394_ohci_csr_cswap(soft_state->ohci, generation, 1003 OHCI_CSR_SEL_CHANS_AVAIL_LO, compare, swap, old); 1004 break; 1005 default: 1006 status = DDI_FAILURE; 1007 break; 1008 } 1009 1010 return (status); 1011 } 1012 1013 1014 /* 1015 * hci1394_s1394if_power_state_change() 1016 * Signals that a change in the bus topology has taken place which may affect 1017 * power management. 1018 */ 1019 /*ARGSUSED*/ 1020 static void 1021 hci1394_s1394if_power_state_change(void *hal_private, 1022 h1394_node_pwr_flags_t nodeflags) 1023 { 1024 /* not implemented */ 1025 } 1026