1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 /* 30 * hci1394_ohci.c 31 * Provides access routines to the OpenHCI HW. 32 */ 33 34 #include <sys/conf.h> 35 #include <sys/ddi.h> 36 #include <sys/modctl.h> 37 #include <sys/sunddi.h> 38 #include <sys/types.h> 39 #include <sys/mkdev.h> 40 #include <sys/kmem.h> 41 #include <sys/pci.h> 42 43 #include <sys/1394/adapters/hci1394.h> 44 #include <sys/1394/adapters/hci1394_extern.h> 45 46 47 /* 48 * Data swap macros used to swap config rom data that is going to be placed 49 * in OpenHCI registers. The config rom is treated like a byte stream. When 50 * the services layer calls into us to update the config rom, they pass us a 51 * byte stream of data. This works well except for the the fact that the 52 * hardware uses its internal registers for the first 5 quadlets. We have to 53 * copy the cfgrom header and bus options into their corresponding OpenHCI 54 * registers. On an x86 machine, this means we have to byte swap them first. 55 */ 56 #ifdef _LITTLE_ENDIAN 57 #define OHCI_SWAP32(DATA) (ddi_swap32(DATA)) 58 #else 59 #define OHCI_SWAP32(DATA) (DATA) 60 #endif 61 62 63 static int hci1394_ohci_selfid_init(hci1394_ohci_handle_t ohci_hdl); 64 static int hci1394_ohci_cfgrom_init(hci1394_ohci_handle_t ohci_hdl); 65 static int hci1394_ohci_chip_init(hci1394_ohci_handle_t ohci_hdl); 66 static int hci1394_ohci_phy_resume(hci1394_ohci_handle_t ohci_hdl); 67 static int hci1394_ohci_1394a_init(hci1394_ohci_handle_t ohci_hdl); 68 static int hci1394_ohci_1394a_resume(hci1394_ohci_handle_t ohci_hdl); 69 static int hci1394_ohci_phy_read_no_lock(hci1394_ohci_handle_t ohci_hdl, 70 uint_t address, uint_t *data); 71 static int hci1394_ohci_phy_write_no_lock(hci1394_ohci_handle_t ohci_hdl, 72 uint_t address, uint_t data); 73 74 75 /* 76 * hci1394_ohci_init() 77 * Initialize the OpenHCI hardware. 78 */ 79 int 80 hci1394_ohci_init(hci1394_state_t *soft_state, hci1394_drvinfo_t *drvinfo, 81 hci1394_ohci_handle_t *ohci_hdl) 82 { 83 int status; 84 uint32_t version; 85 hci1394_ohci_t *ohci; 86 #if defined(__x86) 87 uint16_t cmdreg; 88 #endif 89 90 91 ASSERT(ohci_hdl != NULL); 92 TNF_PROBE_0_DEBUG(hci1394_ohci_init_enter, HCI1394_TNF_HAL_STACK, ""); 93 94 /* alloc the space for ohci */ 95 ohci = kmem_alloc(sizeof (hci1394_ohci_t), KM_SLEEP); 96 *ohci_hdl = ohci; 97 98 /* 99 * Start with the cycle timer rollover interrupt disabled. When it is 100 * enabled, we will get an interrupt every 64 seconds, even if we have 101 * nothing plugged into the bus. This interrupt is used to keep track 102 * of the bus time. We will enable the interrupt when the bus manager 103 * writes to the bus_time CSR register (Currently there are not known 104 * implementations that write to the bus_time register) 105 */ 106 ohci->ohci_bustime_enabled = B_FALSE; 107 ohci->ohci_bustime_count = 0; 108 109 ohci->ohci_set_root_holdoff = B_FALSE; 110 ohci->ohci_set_gap_count = B_FALSE; 111 ohci->ohci_gap_count = 0; 112 113 mutex_init(&ohci->ohci_mutex, NULL, MUTEX_DRIVER, 114 drvinfo->di_iblock_cookie); 115 116 /* Map OpenHCI Registers */ 117 status = ddi_regs_map_setup(drvinfo->di_dip, OHCI_REG_SET, 118 (caddr_t *)&ohci->ohci_regs, 0, 0, &drvinfo->di_reg_attr, 119 &ohci->ohci_reg_handle); 120 if (status != DDI_SUCCESS) { 121 mutex_destroy(&ohci->ohci_mutex); 122 kmem_free(ohci, sizeof (hci1394_ohci_t)); 123 *ohci_hdl = NULL; 124 TNF_PROBE_0(ddi_regs_map_setup_fail, HCI1394_TNF_HAL_ERROR, 125 ""); 126 TNF_PROBE_0_DEBUG(hci1394_ohci_init_exit, HCI1394_TNF_HAL_STACK, 127 ""); 128 return (DDI_FAILURE); 129 } 130 131 ohci->soft_state = soft_state; 132 ohci->ohci_drvinfo = drvinfo; 133 134 /* 135 * make sure PCI Master and PCI Memory Access are enabled on x86 136 * platforms. This may not be the case if plug and play OS is 137 * set in the BIOS 138 */ 139 #if defined(__x86) 140 cmdreg = pci_config_get16(soft_state->pci_config, PCI_CONF_COMM); 141 if ((cmdreg & (PCI_COMM_MAE | PCI_COMM_ME)) != (PCI_COMM_MAE | 142 PCI_COMM_ME)) { 143 cmdreg |= PCI_COMM_MAE | PCI_COMM_ME; 144 pci_config_put16(soft_state->pci_config, PCI_CONF_COMM, cmdreg); 145 } 146 #endif 147 148 /* 149 * Initialize the openHCI chip. This is broken out because we need to 150 * do this when resuming too. 151 */ 152 status = hci1394_ohci_chip_init(ohci); 153 if (status != DDI_SUCCESS) { 154 ddi_regs_map_free(&ohci->ohci_reg_handle); 155 mutex_destroy(&ohci->ohci_mutex); 156 kmem_free(ohci, sizeof (hci1394_ohci_t)); 157 *ohci_hdl = NULL; 158 TNF_PROBE_0(hci1394_ohci_chip_init_fail, HCI1394_TNF_HAL_ERROR, 159 ""); 160 TNF_PROBE_0_DEBUG(hci1394_ohci_init_exit, 161 HCI1394_TNF_HAL_STACK, ""); 162 return (DDI_FAILURE); 163 } 164 165 /* Init the 1394 PHY */ 166 status = hci1394_ohci_phy_init(ohci); 167 if (status != DDI_SUCCESS) { 168 (void) hci1394_ohci_soft_reset(ohci); 169 ddi_regs_map_free(&ohci->ohci_reg_handle); 170 mutex_destroy(&ohci->ohci_mutex); 171 kmem_free(ohci, sizeof (hci1394_ohci_t)); 172 *ohci_hdl = NULL; 173 TNF_PROBE_0(hci1394_ohci_phy_init_fail, 174 HCI1394_TNF_HAL_ERROR, ""); 175 TNF_PROBE_0_DEBUG(hci1394_ohci_init_exit, 176 HCI1394_TNF_HAL_STACK, ""); 177 return (DDI_FAILURE); 178 } 179 180 /* Init 1394a features if present */ 181 if (ohci->ohci_phy == H1394_PHY_1394A) { 182 status = hci1394_ohci_1394a_init(ohci); 183 if (status != DDI_SUCCESS) { 184 (void) hci1394_ohci_soft_reset(ohci); 185 ddi_regs_map_free(&ohci->ohci_reg_handle); 186 mutex_destroy(&ohci->ohci_mutex); 187 kmem_free(ohci, sizeof (hci1394_ohci_t)); 188 *ohci_hdl = NULL; 189 TNF_PROBE_0(hci1394_ohci_1394a_init_fail, 190 HCI1394_TNF_HAL_ERROR, ""); 191 TNF_PROBE_0_DEBUG(hci1394_ohci_init_exit, 192 HCI1394_TNF_HAL_STACK, ""); 193 return (DDI_FAILURE); 194 } 195 } 196 197 /* save away guid, phy type, and vendor info */ 198 soft_state->halinfo.guid = hci1394_ohci_guid(ohci); 199 soft_state->halinfo.phy = ohci->ohci_phy; 200 soft_state->vendor_info.ohci_vendor_id = 201 ddi_get32(ohci->ohci_reg_handle, &ohci->ohci_regs->vendor_id); 202 version = ddi_get32(ohci->ohci_reg_handle, &ohci->ohci_regs->version); 203 soft_state->vendor_info.ohci_version = version; 204 205 /* We do not support version < 1.0 */ 206 if (OHCI_VERSION(version) == 0) { 207 cmn_err(CE_NOTE, 208 "hci1394(%d): OpenHCI version %x.%x is not supported", 209 drvinfo->di_instance, OHCI_VERSION(version), 210 OHCI_REVISION(version)); 211 (void) hci1394_ohci_soft_reset(ohci); 212 ddi_regs_map_free(&ohci->ohci_reg_handle); 213 mutex_destroy(&ohci->ohci_mutex); 214 kmem_free(ohci, sizeof (hci1394_ohci_t)); 215 *ohci_hdl = NULL; 216 TNF_PROBE_0(hci1394_ohci_selfid_init_fail, 217 HCI1394_TNF_HAL_ERROR, ""); 218 TNF_PROBE_0_DEBUG(hci1394_ohci_init_exit, 219 HCI1394_TNF_HAL_STACK, ""); 220 return (DDI_FAILURE); 221 } 222 223 /* Initialize the selfid buffer */ 224 status = hci1394_ohci_selfid_init(ohci); 225 if (status != DDI_SUCCESS) { 226 (void) hci1394_ohci_soft_reset(ohci); 227 ddi_regs_map_free(&ohci->ohci_reg_handle); 228 mutex_destroy(&ohci->ohci_mutex); 229 kmem_free(ohci, sizeof (hci1394_ohci_t)); 230 *ohci_hdl = NULL; 231 TNF_PROBE_0(hci1394_ohci_selfid_init_fail, 232 HCI1394_TNF_HAL_ERROR, ""); 233 TNF_PROBE_0_DEBUG(hci1394_ohci_init_exit, 234 HCI1394_TNF_HAL_STACK, ""); 235 return (DDI_FAILURE); 236 } 237 238 /* Initialize the config rom buffer */ 239 status = hci1394_ohci_cfgrom_init(ohci); 240 if (status != DDI_SUCCESS) { 241 (void) hci1394_ohci_soft_reset(ohci); 242 hci1394_buf_free(&ohci->ohci_selfid_handle); 243 ddi_regs_map_free(&ohci->ohci_reg_handle); 244 mutex_destroy(&ohci->ohci_mutex); 245 kmem_free(ohci, sizeof (hci1394_ohci_t)); 246 *ohci_hdl = NULL; 247 TNF_PROBE_0(hci1394_ohci_cfgrom_init_fail, 248 HCI1394_TNF_HAL_ERROR, ""); 249 TNF_PROBE_0_DEBUG(hci1394_ohci_init_exit, 250 HCI1394_TNF_HAL_STACK, ""); 251 return (DDI_FAILURE); 252 } 253 254 TNF_PROBE_0_DEBUG(hci1394_ohci_init_exit, HCI1394_TNF_HAL_STACK, ""); 255 256 return (DDI_SUCCESS); 257 } 258 259 260 /* 261 * hci1394_ohci_fini() 262 * Cleanup after OpenHCI init. This should be called during detach. 263 */ 264 void 265 hci1394_ohci_fini(hci1394_ohci_handle_t *ohci_hdl) 266 { 267 hci1394_ohci_t *ohci; 268 269 270 ASSERT(ohci_hdl != NULL); 271 TNF_PROBE_0_DEBUG(hci1394_ohci_fini_enter, HCI1394_TNF_HAL_STACK, ""); 272 273 ohci = *ohci_hdl; 274 275 /* reset chip */ 276 (void) hci1394_ohci_soft_reset(ohci); 277 278 /* Free config rom space */ 279 hci1394_buf_free(&ohci->ohci_cfgrom_handle); 280 281 /* Free selfid buffer space */ 282 hci1394_buf_free(&ohci->ohci_selfid_handle); 283 284 /* Free up the OpenHCI registers */ 285 ddi_regs_map_free(&ohci->ohci_reg_handle); 286 287 mutex_destroy(&ohci->ohci_mutex); 288 289 /* Free the OpenHCI state space */ 290 kmem_free(ohci, sizeof (hci1394_ohci_t)); 291 *ohci_hdl = NULL; 292 293 TNF_PROBE_0_DEBUG(hci1394_ohci_fini_exit, HCI1394_TNF_HAL_STACK, ""); 294 } 295 296 297 /* 298 * hci1394_ohci_chip_init() 299 * Initialize the OpenHCI registers. This contains the bulk of the initial 300 * register setup. 301 */ 302 static int 303 hci1394_ohci_chip_init(hci1394_ohci_handle_t ohci_hdl) 304 { 305 int status; 306 307 308 ASSERT(ohci_hdl != NULL); 309 TNF_PROBE_0_DEBUG(hci1394_ohci_chip_init_enter, HCI1394_TNF_HAL_STACK, 310 ""); 311 312 /* Reset 1394 OHCI HW */ 313 status = hci1394_ohci_soft_reset(ohci_hdl); 314 if (status != DDI_SUCCESS) { 315 TNF_PROBE_0(hci1394_ohci_soft_reset_fail, 316 HCI1394_TNF_HAL_ERROR, ""); 317 TNF_PROBE_0_DEBUG(hci1394_ohci_init_exit, 318 HCI1394_TNF_HAL_STACK, ""); 319 return (DDI_FAILURE); 320 } 321 322 /* 323 * Setup Host Control Register. The software reset does not put all 324 * registers in a known state. The Host Control Register is one of these 325 * registers. First make sure noByteSwapData and postedWriteEnable and 326 * are cleared. 327 */ 328 ddi_put32(ohci_hdl->ohci_reg_handle, 329 &ohci_hdl->ohci_regs->hc_ctrl_clr, OHCI_HC_NO_BSWAP | 330 OHCI_HC_POSTWR_ENBL); 331 332 /* 333 * the determination if we should swap data is made during the PCI 334 * initialization. 335 */ 336 if (ohci_hdl->soft_state->swap_data == B_FALSE) { 337 /* 338 * most hba's don't swap data. It will be swapped in the 339 * global swap for SPARC. Enable Link Power(LPS). Enable 340 * Posted Writes 341 */ 342 ddi_put32(ohci_hdl->ohci_reg_handle, 343 &ohci_hdl->ohci_regs->hc_ctrl_set, OHCI_HC_NO_BSWAP | 344 OHCI_HC_LPS | OHCI_HC_POSTWR_ENBL); 345 } else { 346 /* 347 * Swap Data. Enable Link Power(LPS). Enable Posted Writes 348 */ 349 ddi_put32(ohci_hdl->ohci_reg_handle, 350 &ohci_hdl->ohci_regs->hc_ctrl_set, OHCI_HC_LPS | 351 OHCI_HC_POSTWR_ENBL); 352 } 353 354 /* 355 * Wait for PHY to come up. There does not seem to be standard time for 356 * how long wait for the PHY to come up. The problem is that the PHY 357 * provides a clock to the link layer and if that is not stable, we 358 * could get a PCI timeout error when reading/writing a phy register 359 * (and maybe an OpenHCI register?) This used to be set to 10mS which 360 * works for just about every adapter we tested on. We got a new TI 361 * adapter which would crash the system once in a while if nothing 362 * (1394 device) was pluged into the adapter. Changing this delay to 363 * 50mS made that problem go away. This value is set via a patchable 364 * variable located in hci1394_extern.c 365 */ 366 delay(drv_usectohz(hci1394_phy_stabilization_delay_uS)); 367 368 /* Clear Isochrounous receive multi-chan mode registers */ 369 ddi_put32(ohci_hdl->ohci_reg_handle, 370 &ohci_hdl->ohci_regs->ir_multi_maskhi_clr, 0xFFFFFFFF); 371 ddi_put32(ohci_hdl->ohci_reg_handle, 372 &ohci_hdl->ohci_regs->ir_multi_masklo_clr, 0xFFFFFFFF); 373 374 /* 375 * Setup async retry on busy or ack_data_error 376 * secondlimit = 0 <= bits 31-29 377 * cycleLimit = 0 <= bits 28-16 378 * maxPhysRespRetries = 0 <= bits 11-8 379 * maxARRespRetries = 0 <= bits 7-4 380 * maxATReqRetries = 2 <= bits 3-0 381 */ 382 ddi_put32(ohci_hdl->ohci_reg_handle, 383 &ohci_hdl->ohci_regs->at_retries, 0x00000002); 384 385 /* 386 * Setup Link Control 387 * Enable cycleMaster, cycleTimerEnable, and rcvPhyPkt. 388 */ 389 ddi_put32(ohci_hdl->ohci_reg_handle, 390 &ohci_hdl->ohci_regs->link_ctrl_clr, 0xFFFFFFFF); 391 ddi_put32(ohci_hdl->ohci_reg_handle, 392 &ohci_hdl->ohci_regs->link_ctrl_set, OHCI_LC_CYC_MAST | 393 OHCI_LC_CTIME_ENBL | OHCI_LC_RCV_PHY); 394 395 /* 396 * Set the Physical address map boundary to 0x0000FFFFFFFF. The 397 * phys_upper_bound is the upper 32-bits of the 48-bit 1394 address. The 398 * lower 16 bits are assumed to be 0xFFFF. 399 */ 400 ddi_put32(ohci_hdl->ohci_reg_handle, 401 &ohci_hdl->ohci_regs->phys_upper_bound, (uint32_t)0x0000FFFF); 402 403 /* 404 * Enable all async requests. 405 * The asyncReqResourceAll bit (0x80000000) does not get cleared during 406 * a bus reset. If this code is changed to selectively allow nodes to 407 * perform ARREQ's, the ARREQ filter bits will need to be updated after 408 * every bus reset. 409 */ 410 ddi_put32(ohci_hdl->ohci_reg_handle, 411 &ohci_hdl->ohci_regs->ar_req_filterhi_set, (uint32_t)0x80000000); 412 413 /* 414 * clear isochronous interrupt event and mask registers clearing the 415 * mask registers disable all isoc tx & rx ints 416 */ 417 ddi_put32(ohci_hdl->ohci_reg_handle, 418 &ohci_hdl->ohci_regs->it_intr_event_clr, (uint32_t)0xFFFFFFFF); 419 ddi_put32(ohci_hdl->ohci_reg_handle, 420 &ohci_hdl->ohci_regs->it_intr_mask_clr, (uint32_t)0xFFFFFFFF); 421 ddi_put32(ohci_hdl->ohci_reg_handle, 422 &ohci_hdl->ohci_regs->ir_intr_event_clr, (uint32_t)0xFFFFFFFF); 423 ddi_put32(ohci_hdl->ohci_reg_handle, 424 &ohci_hdl->ohci_regs->ir_intr_mask_clr, (uint32_t)0xFFFFFFFF); 425 426 /* Clear interrupt event/mask register */ 427 ddi_put32(ohci_hdl->ohci_reg_handle, 428 &ohci_hdl->ohci_regs->intr_event_clr, (uint32_t)0xFFFFFFFF); 429 ddi_put32(ohci_hdl->ohci_reg_handle, 430 &ohci_hdl->ohci_regs->intr_mask_clr, (uint32_t)0xFFFFFFFF); 431 432 TNF_PROBE_0_DEBUG(hci1394_ohci_chip_init_exit, HCI1394_TNF_HAL_STACK, 433 ""); 434 return (DDI_SUCCESS); 435 } 436 437 438 /* 439 * hci1394_ohci_soft_reset() 440 * Reset OpenHCI HW. 441 */ 442 int 443 hci1394_ohci_soft_reset(hci1394_ohci_handle_t ohci_hdl) 444 { 445 uint32_t resetStatus; 446 447 448 ASSERT(ohci_hdl != NULL); 449 TNF_PROBE_0_DEBUG(hci1394_ohci_soft_reset_enter, 450 HCI1394_TNF_HAL_STACK, ""); 451 452 /* Reset 1394 HW - Reset is bit 16 in HCControl */ 453 ddi_put32(ohci_hdl->ohci_reg_handle, 454 &ohci_hdl->ohci_regs->hc_ctrl_set, OHCI_HC_SOFT_RESET); 455 456 /* Wait for reset to complete */ 457 drv_usecwait(OHCI_CHIP_RESET_TIME_IN_uSEC); 458 459 /* Verify reset is complete */ 460 resetStatus = ddi_get32(ohci_hdl->ohci_reg_handle, 461 &ohci_hdl->ohci_regs->hc_ctrl_set); 462 resetStatus = resetStatus & OHCI_HC_SOFT_RESET; 463 if (resetStatus != 0) { 464 TNF_PROBE_0(hci1394_ohci_reset_not_complete_fail, 465 HCI1394_TNF_HAL_ERROR, ""); 466 TNF_PROBE_0_DEBUG(hci1394_ohci_soft_reset_exit, 467 HCI1394_TNF_HAL_STACK, ""); 468 return (DDI_FAILURE); 469 } 470 471 TNF_PROBE_0_DEBUG(hci1394_ohci_soft_reset_exit, 472 HCI1394_TNF_HAL_STACK, ""); 473 474 return (DDI_SUCCESS); 475 } 476 477 478 /* 479 * hci1394_ohci_reg_read() 480 * Read OpenHCI register. This is called from the test ioctl interface 481 * through devctl. 482 */ 483 void 484 hci1394_ohci_reg_read(hci1394_ohci_handle_t ohci_hdl, 485 uint_t offset, uint32_t *data) 486 { 487 uint32_t *addr; 488 489 490 ASSERT(ohci_hdl != NULL); 491 ASSERT(data != NULL); 492 TNF_PROBE_0_DEBUG(hci1394_ohci_reg_read_enter, 493 HCI1394_TNF_HAL_STACK, ""); 494 495 addr = (uint32_t *)((uintptr_t)ohci_hdl->ohci_regs + 496 (uintptr_t)(offset & OHCI_REG_ADDR_MASK)); 497 *data = ddi_get32(ohci_hdl->ohci_reg_handle, addr); 498 499 TNF_PROBE_0_DEBUG(hci1394_ohci_reg_read_exit, 500 HCI1394_TNF_HAL_STACK, ""); 501 } 502 503 504 /* 505 * hci1394_ohci_reg_write() 506 * Write OpenHCI register. This is called from the test ioctl interface 507 * through devctl. 508 */ 509 void 510 hci1394_ohci_reg_write(hci1394_ohci_handle_t ohci_hdl, 511 uint_t offset, uint32_t data) 512 { 513 uint32_t *addr; 514 515 516 ASSERT(ohci_hdl != NULL); 517 TNF_PROBE_0_DEBUG(hci1394_ohci_reg_read_enter, 518 HCI1394_TNF_HAL_STACK, ""); 519 520 addr = (uint32_t *)((uintptr_t)ohci_hdl->ohci_regs + 521 (uintptr_t)(offset & OHCI_REG_ADDR_MASK)); 522 ddi_put32(ohci_hdl->ohci_reg_handle, addr, data); 523 524 TNF_PROBE_0_DEBUG(hci1394_ohci_reg_read_exit, 525 HCI1394_TNF_HAL_STACK, ""); 526 } 527 528 529 /* 530 * hci1394_ohci_intr_master_enable() 531 * Enable interrupts to be passed on from OpenHCI. This is a global mask. 532 * Individual interrupts still need to be enabled for interrupts to be 533 * generated. 534 */ 535 void 536 hci1394_ohci_intr_master_enable(hci1394_ohci_handle_t ohci_hdl) 537 { 538 ASSERT(ohci_hdl != NULL); 539 TNF_PROBE_0_DEBUG(hci1394_ohci_intr_master_enable_enter, 540 HCI1394_TNF_HAL_STACK, ""); 541 542 ddi_put32(ohci_hdl->ohci_reg_handle, 543 &ohci_hdl->ohci_regs->intr_mask_set, OHCI_INTR_MASTER_INTR_ENBL); 544 545 TNF_PROBE_0_DEBUG(hci1394_ohci_intr_master_enable_exit, 546 HCI1394_TNF_HAL_STACK, ""); 547 } 548 549 550 /* 551 * hci1394_ohci_intr_master_disable() 552 * Disable all OpenHCI interrupts from being passed on. This does not affect 553 * the individual interrupt mask settings. When interrupts are enabled 554 * again, the same individual interrupts will still be enabled. 555 */ 556 void 557 hci1394_ohci_intr_master_disable(hci1394_ohci_handle_t ohci_hdl) 558 { 559 ASSERT(ohci_hdl != NULL); 560 TNF_PROBE_0_DEBUG(hci1394_ohci_intr_master_disable_enter, 561 HCI1394_TNF_HAL_STACK, ""); 562 563 ddi_put32(ohci_hdl->ohci_reg_handle, 564 &ohci_hdl->ohci_regs->intr_mask_clr, OHCI_INTR_MASTER_INTR_ENBL); 565 566 TNF_PROBE_0_DEBUG(hci1394_ohci_intr_master_disable_exit, 567 HCI1394_TNF_HAL_STACK, ""); 568 } 569 570 571 /* 572 * hci1394_ohci_intr_asserted() 573 * Return which ENABLED interrupts are asserted. If an interrupt is disabled 574 * via its mask bit, it will not be returned from here. 575 * 576 * NOTE: we may want to make this a macro at some point. 577 */ 578 uint32_t 579 hci1394_ohci_intr_asserted(hci1394_ohci_handle_t ohci_hdl) 580 { 581 uint32_t interrupts_asserted; 582 583 ASSERT(ohci_hdl != NULL); 584 TNF_PROBE_0_DEBUG(hci1394_ohci_intr_asserted_enter, 585 HCI1394_TNF_HAL_STACK, ""); 586 587 /* 588 * Only look at interrupts which are enabled by reading the 589 * intr_event_clr register. 590 */ 591 interrupts_asserted = ddi_get32(ohci_hdl->ohci_reg_handle, 592 &ohci_hdl->ohci_regs->intr_event_clr); 593 594 TNF_PROBE_0_DEBUG(hci1394_ohci_intr_asserted_exit, 595 HCI1394_TNF_HAL_STACK, ""); 596 return (interrupts_asserted); 597 } 598 599 600 /* 601 * hci1394_ohci_intr_enable() 602 * Enable an individual interrupt or set of interrupts. This does not affect 603 * the global interrupt mask. 604 */ 605 void 606 hci1394_ohci_intr_enable(hci1394_ohci_handle_t ohci_hdl, 607 uint32_t interrupt_mask) 608 { 609 ASSERT(ohci_hdl != NULL); 610 TNF_PROBE_0_DEBUG(hci1394_ohci_intr_enable_enter, 611 HCI1394_TNF_HAL_STACK, ""); 612 613 ddi_put32(ohci_hdl->ohci_reg_handle, 614 &ohci_hdl->ohci_regs->intr_mask_set, interrupt_mask); 615 616 TNF_PROBE_0_DEBUG(hci1394_ohci_intr_enable_exit, 617 HCI1394_TNF_HAL_STACK, ""); 618 } 619 620 621 /* 622 * hci1394_ohci_intr_disable() 623 * Disable an individual interrupt or set of interrupts. This does not affect 624 * the global interrupt mask. 625 */ 626 void 627 hci1394_ohci_intr_disable(hci1394_ohci_handle_t ohci_hdl, 628 uint32_t interrupt_mask) 629 { 630 ASSERT(ohci_hdl != NULL); 631 TNF_PROBE_0_DEBUG(hci1394_ohci_intr_disable_enter, 632 HCI1394_TNF_HAL_STACK, ""); 633 634 ddi_put32(ohci_hdl->ohci_reg_handle, 635 &ohci_hdl->ohci_regs->intr_mask_clr, interrupt_mask); 636 637 TNF_PROBE_0_DEBUG(hci1394_ohci_intr_disable_exit, 638 HCI1394_TNF_HAL_STACK, ""); 639 } 640 641 642 /* 643 * hci1394_ohci_intr_clear() 644 * Clear a set of interrupts so that they are not asserted anymore. 645 * 646 * NOTE: we may want to make this a macro at some point. 647 */ 648 void 649 hci1394_ohci_intr_clear(hci1394_ohci_handle_t ohci_hdl, 650 uint32_t interrupt_mask) 651 { 652 ASSERT(ohci_hdl != NULL); 653 TNF_PROBE_0_DEBUG(hci1394_ohci_intr_clear_enter, 654 HCI1394_TNF_HAL_STACK, ""); 655 656 ddi_put32(ohci_hdl->ohci_reg_handle, 657 &ohci_hdl->ohci_regs->intr_event_clr, interrupt_mask); 658 TNF_PROBE_1_DEBUG(hci1394_ohci_intr_clear, HCI1394_TNF_HAL, "", 659 tnf_uint, intr_mask, interrupt_mask); 660 661 TNF_PROBE_0_DEBUG(hci1394_ohci_intr_clear_exit, 662 HCI1394_TNF_HAL_STACK, ""); 663 } 664 665 666 /* 667 * hci1394_ohci_it_intr_asserted() 668 * Return which ENABLED isoch TX interrupts are asserted. If an interrupt is 669 * disabled via its mask bit, it will not be returned from here. 670 * 671 * NOTE: we may want to make this a macro at some point. 672 */ 673 uint32_t 674 hci1394_ohci_it_intr_asserted(hci1394_ohci_handle_t ohci_hdl) 675 { 676 uint32_t interrupts_asserted; 677 678 ASSERT(ohci_hdl != NULL); 679 TNF_PROBE_0_DEBUG(hci1394_ohci_it_intr_asserted_enter, 680 HCI1394_TNF_HAL_STACK, ""); 681 682 /* Only look at interrupts which are enabled */ 683 interrupts_asserted = ddi_get32(ohci_hdl->ohci_reg_handle, 684 &ohci_hdl->ohci_regs->it_intr_event_clr); 685 686 TNF_PROBE_0_DEBUG(hci1394_ohci_it_intr_asserted_exit, 687 HCI1394_TNF_HAL_STACK, ""); 688 return (interrupts_asserted); 689 } 690 691 692 /* 693 * hci1394_ohci_it_intr_enable() 694 * Enable an individual isoch TX interrupt. This does not affect the general 695 * isoch interrupt mask in the OpenHCI Mask register. That is enabled/ 696 * disabled via hci1394_ohci_intr_enable/hci1394_ohci_intr_disable. 697 */ 698 void 699 hci1394_ohci_it_intr_enable(hci1394_ohci_handle_t ohci_hdl, 700 uint32_t interrupt_mask) 701 { 702 ASSERT(ohci_hdl != NULL); 703 TNF_PROBE_0_DEBUG(hci1394_ohci_it_intr_enable_enter, 704 HCI1394_TNF_HAL_STACK, ""); 705 706 ddi_put32(ohci_hdl->ohci_reg_handle, 707 &ohci_hdl->ohci_regs->it_intr_mask_set, interrupt_mask); 708 709 TNF_PROBE_0_DEBUG(hci1394_ohci_it_intr_enable_exit, 710 HCI1394_TNF_HAL_STACK, ""); 711 } 712 713 714 /* 715 * hci1394_ohci_it_intr_disable() 716 * Disable an individual isoch TX interrupt. This does not affect the general 717 * isoch interrupt mask in the OpenHCI Mask register. That is enabled/ 718 * disabled via hci1394_ohci_intr_enable/hci1394_ohci_intr_disable. 719 */ 720 void 721 hci1394_ohci_it_intr_disable(hci1394_ohci_handle_t ohci_hdl, 722 uint32_t interrupt_mask) 723 { 724 ASSERT(ohci_hdl != NULL); 725 TNF_PROBE_0_DEBUG(hci1394_ohci_it_intr_disable_enter, 726 HCI1394_TNF_HAL_STACK, ""); 727 728 ddi_put32(ohci_hdl->ohci_reg_handle, 729 &ohci_hdl->ohci_regs->it_intr_mask_clr, interrupt_mask); 730 731 TNF_PROBE_0_DEBUG(hci1394_ohci_it_intr_disable_exit, 732 HCI1394_TNF_HAL_STACK, ""); 733 } 734 735 736 /* 737 * hci1394_ohci_it_intr_clear() 738 * Clear an individual isoch TX interrupt so that it is not asserted anymore. 739 * 740 * NOTE: we may want to make this a macro at some point. 741 */ 742 void 743 hci1394_ohci_it_intr_clear(hci1394_ohci_handle_t ohci_hdl, 744 uint32_t interrupt_mask) 745 { 746 ASSERT(ohci_hdl != NULL); 747 TNF_PROBE_0_DEBUG(hci1394_ohci_it_intr_clear_enter, 748 HCI1394_TNF_HAL_STACK, ""); 749 750 ddi_put32(ohci_hdl->ohci_reg_handle, 751 &ohci_hdl->ohci_regs->it_intr_event_clr, interrupt_mask); 752 753 TNF_PROBE_0_DEBUG(hci1394_ohci_it_intr_clear_exit, 754 HCI1394_TNF_HAL_STACK, ""); 755 } 756 757 758 /* 759 * hci1394_ohci_it_ctxt_count_get() 760 * Determine the number of supported isochronous transmit contexts. 761 */ 762 int 763 hci1394_ohci_it_ctxt_count_get(hci1394_ohci_handle_t ohci_hdl) 764 { 765 uint32_t channel_mask; 766 int count; 767 768 ASSERT(ohci_hdl != NULL); 769 TNF_PROBE_0_DEBUG(hci1394_ohci_it_ctxt_count_get_enter, 770 HCI1394_TNF_HAL_STACK, ""); 771 772 /* 773 * hw is required to support contexts 0 to N, where N <= 31 774 * the interrupt mask bits are wired to ground for unsupported 775 * contexts. Write 1's to all it mask bits, then read the mask. 776 * Implemented contexts will read (sequentially) as 1 777 */ 778 ddi_put32(ohci_hdl->ohci_reg_handle, 779 &ohci_hdl->ohci_regs->it_intr_mask_set, 0xFFFFFFFF); 780 channel_mask = ddi_get32(ohci_hdl->ohci_reg_handle, 781 &ohci_hdl->ohci_regs->it_intr_mask_set); 782 count = 0; 783 while (channel_mask != 0) { 784 channel_mask = channel_mask >> 1; 785 count++; 786 } 787 788 TNF_PROBE_0_DEBUG(hci1394_ohci_it_ctxt_count_get_exit, 789 HCI1394_TNF_HAL_STACK, ""); 790 return (count); 791 } 792 793 794 /* 795 * hci1394_ohci_it_cmd_ptr_set() 796 * Set the context pointer for a given isoch TX context. This is the IO 797 * address for the HW to fetch the first descriptor. The context should 798 * not be running when this routine is called. 799 */ 800 void 801 hci1394_ohci_it_cmd_ptr_set(hci1394_ohci_handle_t ohci_hdl, 802 uint_t context_number, uint32_t io_addr) 803 { 804 ASSERT(ohci_hdl != NULL); 805 TNF_PROBE_0_DEBUG(hci1394_ohci_it_cmd_ptr_set_enter, 806 HCI1394_TNF_HAL_STACK, ""); 807 808 ddi_put32(ohci_hdl->ohci_reg_handle, 809 &ohci_hdl->ohci_regs->it[context_number].cmd_ptrlo, 810 io_addr); 811 812 TNF_PROBE_0_DEBUG(hci1394_ohci_it_cmd_ptr_set_exit, 813 HCI1394_TNF_HAL_STACK, ""); 814 } 815 816 817 /* 818 * hci1394_ohci_ir_intr_asserted() 819 * Return which ENABLED isoch RX interrupts are asserted. If an interrupt is 820 * disabled via its mask bit, it will not be returned from here. 821 * 822 * NOTE: we may want to make this a macro at some point. 823 */ 824 uint32_t 825 hci1394_ohci_ir_intr_asserted(hci1394_ohci_handle_t ohci_hdl) 826 { 827 uint32_t interrupts_asserted; 828 829 ASSERT(ohci_hdl != NULL); 830 TNF_PROBE_0_DEBUG(hci1394_ohci_ir_intr_asserted_enter, 831 HCI1394_TNF_HAL_STACK, ""); 832 833 /* Only look at interrupts which are enabled */ 834 interrupts_asserted = ddi_get32(ohci_hdl->ohci_reg_handle, 835 &ohci_hdl->ohci_regs->ir_intr_event_clr); 836 837 TNF_PROBE_0_DEBUG(hci1394_ohci_ir_intr_asserted_exit, 838 HCI1394_TNF_HAL_STACK, ""); 839 return (interrupts_asserted); 840 } 841 842 843 /* 844 * hci1394_ohci_ir_intr_enable() 845 * Enable an individual isoch RX interrupt. This does not affect the isoch 846 * interrupt mask in the OpenHCI Mask register. That is enabled/disabled 847 * via hci1394_ohci_intr_enable/hci1394_ohci_intr_disable. 848 */ 849 void 850 hci1394_ohci_ir_intr_enable(hci1394_ohci_handle_t ohci_hdl, 851 uint32_t interrupt_mask) 852 { 853 ASSERT(ohci_hdl != NULL); 854 TNF_PROBE_0_DEBUG(hci1394_ohci_ir_intr_enable_enter, 855 HCI1394_TNF_HAL_STACK, ""); 856 857 ddi_put32(ohci_hdl->ohci_reg_handle, 858 &ohci_hdl->ohci_regs->ir_intr_mask_set, interrupt_mask); 859 860 TNF_PROBE_0_DEBUG(hci1394_ohci_ir_intr_enable_exit, 861 HCI1394_TNF_HAL_STACK, ""); 862 } 863 864 865 /* 866 * hci1394_ohci_ir_intr_disable() 867 * Disable an individual isoch RX interrupt. This does not affect the isoch 868 * interrupt mask in the OpenHCI Mask register. That is enabled/disabled 869 * via hci1394_ohci_intr_enable/hci1394_ohci_intr_disable. 870 */ 871 void 872 hci1394_ohci_ir_intr_disable(hci1394_ohci_handle_t ohci_hdl, 873 uint32_t interrupt_mask) 874 { 875 ASSERT(ohci_hdl != NULL); 876 TNF_PROBE_0_DEBUG(hci1394_ohci_ir_intr_disable_enter, 877 HCI1394_TNF_HAL_STACK, ""); 878 879 ddi_put32(ohci_hdl->ohci_reg_handle, 880 &ohci_hdl->ohci_regs->ir_intr_mask_clr, interrupt_mask); 881 882 TNF_PROBE_0_DEBUG(hci1394_ohci_ir_intr_disable_exit, 883 HCI1394_TNF_HAL_STACK, ""); 884 } 885 886 887 /* 888 * hci1394_ohci_ir_intr_clear() 889 * Clear an individual isoch RX interrupt so that it is not asserted anymore. 890 * 891 * NOTE: we may want to make this a macro at some point. 892 */ 893 void 894 hci1394_ohci_ir_intr_clear(hci1394_ohci_handle_t ohci_hdl, 895 uint32_t interrupt_mask) 896 { 897 ASSERT(ohci_hdl != NULL); 898 TNF_PROBE_0_DEBUG(hci1394_ohci_ir_intr_clear_enter, 899 HCI1394_TNF_HAL_STACK, ""); 900 901 ddi_put32(ohci_hdl->ohci_reg_handle, 902 &ohci_hdl->ohci_regs->ir_intr_event_clr, interrupt_mask); 903 904 TNF_PROBE_0_DEBUG(hci1394_ohci_ir_intr_clear_exit, 905 HCI1394_TNF_HAL_STACK, ""); 906 } 907 908 909 /* 910 * hci1394_ohci_ir_ctxt_count_get() 911 * Determine the number of supported isochronous receive contexts. 912 */ 913 int 914 hci1394_ohci_ir_ctxt_count_get(hci1394_ohci_handle_t ohci_hdl) 915 { 916 uint32_t channel_mask; 917 int count; 918 919 ASSERT(ohci_hdl != NULL); 920 TNF_PROBE_0_DEBUG(hci1394_ohci_ir_ctxt_count_get_enter, 921 HCI1394_TNF_HAL_STACK, ""); 922 923 /* 924 * hw is required to support contexts 0 to N, where N <= 31 925 * the interrupt mask bits are wired to ground for unsupported 926 * contexts. Write 1's to all ir mask bits, then read the mask. 927 * Implemented contexts will read (sequentially) as 1 928 */ 929 ddi_put32(ohci_hdl->ohci_reg_handle, 930 &ohci_hdl->ohci_regs->ir_intr_mask_set, 0xFFFFFFFF); 931 channel_mask = ddi_get32(ohci_hdl->ohci_reg_handle, 932 &ohci_hdl->ohci_regs->ir_intr_mask_set); 933 count = 0; 934 while (channel_mask != 0) { 935 channel_mask = channel_mask >> 1; 936 count++; 937 } 938 939 TNF_PROBE_0_DEBUG(hci1394_ohci_ir_ctxt_count_get_exit, 940 HCI1394_TNF_HAL_STACK, ""); 941 return (count); 942 } 943 944 945 /* 946 * hci1394_ohci_ir_cmd_ptr_set() 947 * Set the context pointer for a given isoch RX context. This is the IO 948 * address for the HW to fetch the first descriptor. The context should 949 * not be running when this routine is called. 950 */ 951 void 952 hci1394_ohci_ir_cmd_ptr_set(hci1394_ohci_handle_t ohci_hdl, 953 uint_t context_number, uint32_t io_addr) 954 { 955 ASSERT(ohci_hdl != NULL); 956 TNF_PROBE_0_DEBUG(hci1394_ohci_ir_cmd_ptr_set_enter, 957 HCI1394_TNF_HAL_STACK, ""); 958 959 ddi_put32(ohci_hdl->ohci_reg_handle, 960 &ohci_hdl->ohci_regs->ir[context_number].cmd_ptrlo, 961 io_addr); 962 963 TNF_PROBE_0_DEBUG(hci1394_ohci_ir_cmd_ptr_set_exit, 964 HCI1394_TNF_HAL_STACK, ""); 965 } 966 967 968 /* 969 * hci1394_ohci_link_enable() 970 * Enable the 1394 link layer. When the link is enabled, the PHY will pass 971 * up any 1394 bus transactions which would normally come up to the link. 972 */ 973 void 974 hci1394_ohci_link_enable(hci1394_ohci_handle_t ohci_hdl) 975 { 976 ASSERT(ohci_hdl != NULL); 977 TNF_PROBE_0_DEBUG(hci1394_ohci_link_enable_enter, 978 HCI1394_TNF_HAL_STACK, ""); 979 980 ddi_put32(ohci_hdl->ohci_reg_handle, 981 &ohci_hdl->ohci_regs->hc_ctrl_set, OHCI_HC_LINK_ENBL); 982 983 TNF_PROBE_0_DEBUG(hci1394_ohci_link_enable_exit, 984 HCI1394_TNF_HAL_STACK, ""); 985 } 986 987 988 /* 989 * hci1394_ohci_link_disable() 990 * Disable the 1394 link layer. When the link is disabled, the PHY will NOT 991 * pass up any 1394 bus transactions which would normally come up to the 992 * link. This "logically" disconnects us from the 1394 bus. 993 */ 994 void 995 hci1394_ohci_link_disable(hci1394_ohci_handle_t ohci_hdl) 996 { 997 ASSERT(ohci_hdl != NULL); 998 TNF_PROBE_0_DEBUG(hci1394_ohci_link_disable_enter, 999 HCI1394_TNF_HAL_STACK, ""); 1000 1001 ddi_put32(ohci_hdl->ohci_reg_handle, 1002 &ohci_hdl->ohci_regs->hc_ctrl_clr, OHCI_HC_LINK_ENBL); 1003 1004 TNF_PROBE_0_DEBUG(hci1394_ohci_link_disable_exit, 1005 HCI1394_TNF_HAL_STACK, ""); 1006 } 1007 1008 1009 /* 1010 * hci1394_ohci_bus_reset() 1011 * Reset the 1394 bus. This performs a "long" bus reset and can be called 1012 * when the adapter has either a 1394-1995 or 1394A PHY. 1013 */ 1014 int 1015 hci1394_ohci_bus_reset(hci1394_ohci_handle_t ohci_hdl) 1016 { 1017 int status; 1018 uint_t reg; 1019 1020 1021 ASSERT(ohci_hdl != NULL); 1022 TNF_PROBE_0_DEBUG(hci1394_ohci_bus_reset_enter, 1023 HCI1394_TNF_HAL_STACK, ""); 1024 1025 /* 1026 * We want to reset the bus. We also handle the root_holdoff and gap 1027 * count cacheing explained at the top of this file. 1028 */ 1029 reg = OHCI_PHY_IBR; 1030 if (ohci_hdl->ohci_set_root_holdoff == B_TRUE) { 1031 reg = reg | OHCI_PHY_RHB; 1032 } 1033 if (ohci_hdl->ohci_set_gap_count == B_TRUE) { 1034 reg = reg | ohci_hdl->ohci_gap_count; 1035 } else { 1036 reg = reg | OHCI_PHY_MAX_GAP; 1037 } 1038 1039 /* 1040 * Reset the bus. We intentionally do NOT do a PHY read here. A PHY 1041 * read could introduce race conditions and would be more likely to fail 1042 * due to a timeout. 1043 */ 1044 status = hci1394_ohci_phy_write(ohci_hdl, 0x1, reg); 1045 if (status != DDI_SUCCESS) { 1046 TNF_PROBE_0(hci1394_ohci_phy_write_fail, 1047 HCI1394_TNF_HAL_ERROR, ""); 1048 TNF_PROBE_0_DEBUG(hci1394_ohci_bus_reset_exit, 1049 HCI1394_TNF_HAL_STACK, ""); 1050 return (DDI_FAILURE); 1051 } 1052 1053 /* clear the root holdoff and gap count state bits */ 1054 ohci_hdl->ohci_set_root_holdoff = B_FALSE; 1055 ohci_hdl->ohci_set_gap_count = B_FALSE; 1056 1057 TNF_PROBE_0_DEBUG(hci1394_ohci_bus_reset_exit, 1058 HCI1394_TNF_HAL_STACK, ""); 1059 1060 return (DDI_SUCCESS); 1061 } 1062 1063 1064 /* 1065 * hci1394_ohci_phy_init() 1066 * Setup the PHY. This should be called during attach and performs any PHY 1067 * initialization required including figuring out what kind of PHY we have. 1068 */ 1069 int 1070 hci1394_ohci_phy_init(hci1394_ohci_handle_t ohci_hdl) 1071 { 1072 int status; 1073 uint_t phy_reg; 1074 1075 1076 ASSERT(ohci_hdl != NULL); 1077 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_init_enter, 1078 HCI1394_TNF_HAL_STACK, ""); 1079 1080 /* 1081 * if the phy has extended set to 7, the phy is a not a 1394-1995 PHY. 1082 * It could be a 1394a phy or beyond. The PHY type can be found in PHY 1083 * register page 1 in the compliance_level register. 1084 * 1085 * Since there are not any current standards beyond 1394A, we are going 1086 * to consider the PHY to be a 1394A phy if the extended bit is set. 1087 * 1088 * phy registers are byte wide registers and are addressed as 0, 1, 2, 1089 * 3, ... Phy register 0 may not be read or written. 1090 * 1091 * Phy register 0x2 (bit 0 MSB, 7 LSB) 1092 * Extended - bits 0 - 2 1093 * Total Ports - bits 4 - 7 1094 */ 1095 status = hci1394_ohci_phy_read(ohci_hdl, 2, &phy_reg); 1096 if (status != DDI_SUCCESS) { 1097 TNF_PROBE_0(hci1394_ohci_phy_read_failed, 1098 HCI1394_TNF_HAL_ERROR, ""); 1099 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_init_exit, 1100 HCI1394_TNF_HAL_STACK, ""); 1101 return (DDI_FAILURE); 1102 } 1103 1104 if ((phy_reg & OHCI_PHY_EXTND_MASK) != OHCI_PHY_EXTND) { 1105 /* 1106 * if the extended bit is not set, we have to be a 1394-1995 1107 * PHY 1108 */ 1109 ohci_hdl->ohci_phy = H1394_PHY_1995; 1110 } else { 1111 /* Treat all other PHY's as a 1394A PHY */ 1112 ohci_hdl->ohci_phy = H1394_PHY_1394A; 1113 } 1114 1115 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_init_exit, 1116 HCI1394_TNF_HAL_STACK, ""); 1117 1118 return (DDI_SUCCESS); 1119 } 1120 1121 1122 /* 1123 * hci1394_ohci_phy_resume() 1124 * re-initialize the PHY. This routine should be called during a resume after 1125 * a successful suspend has been done. 1126 */ 1127 /* ARGSUSED */ 1128 static int 1129 hci1394_ohci_phy_resume(hci1394_ohci_handle_t ohci_hdl) 1130 { 1131 ASSERT(ohci_hdl != NULL); 1132 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_resume_enter, 1133 HCI1394_TNF_HAL_STACK, ""); 1134 1135 /* There is currently nothing to re-initialize here */ 1136 1137 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_resume_exit, 1138 HCI1394_TNF_HAL_STACK, ""); 1139 1140 return (DDI_SUCCESS); 1141 } 1142 1143 1144 /* 1145 * hci1394_ohci_phy_set() 1146 * Perform bitset operation on PHY register. 1147 */ 1148 int 1149 hci1394_ohci_phy_set(hci1394_ohci_handle_t ohci_hdl, uint_t address, 1150 uint_t bits) 1151 { 1152 int status; 1153 uint_t reg; 1154 1155 1156 ASSERT(ohci_hdl != NULL); 1157 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_set_enter, 1158 HCI1394_TNF_HAL_STACK, ""); 1159 1160 mutex_enter(&ohci_hdl->ohci_mutex); 1161 1162 /* read the PHY register */ 1163 status = hci1394_ohci_phy_read_no_lock(ohci_hdl, address, ®); 1164 if (status != DDI_SUCCESS) { 1165 mutex_exit(&ohci_hdl->ohci_mutex); 1166 TNF_PROBE_0(hci1394_ohci_phy_read_fail, 1167 HCI1394_TNF_HAL_ERROR, ""); 1168 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_set_exit, 1169 HCI1394_TNF_HAL_STACK, ""); 1170 return (DDI_FAILURE); 1171 } 1172 1173 /* Set the bits and write the result back */ 1174 reg = reg | bits; 1175 status = hci1394_ohci_phy_write_no_lock(ohci_hdl, address, reg); 1176 if (status != DDI_SUCCESS) { 1177 mutex_exit(&ohci_hdl->ohci_mutex); 1178 TNF_PROBE_0(hci1394_ohci_phy_write_fail, 1179 HCI1394_TNF_HAL_ERROR, ""); 1180 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_set_exit, 1181 HCI1394_TNF_HAL_STACK, ""); 1182 return (DDI_FAILURE); 1183 } 1184 1185 mutex_exit(&ohci_hdl->ohci_mutex); 1186 1187 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_set_exit, HCI1394_TNF_HAL_STACK, 1188 ""); 1189 1190 return (DDI_SUCCESS); 1191 } 1192 1193 1194 /* 1195 * hci1394_ohci_phy_clr() 1196 * Perform bitclr operation on PHY register. 1197 */ 1198 int 1199 hci1394_ohci_phy_clr(hci1394_ohci_handle_t ohci_hdl, uint_t address, 1200 uint_t bits) 1201 { 1202 int status; 1203 uint_t reg; 1204 1205 1206 ASSERT(ohci_hdl != NULL); 1207 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_clr_enter, 1208 HCI1394_TNF_HAL_STACK, ""); 1209 1210 mutex_enter(&ohci_hdl->ohci_mutex); 1211 1212 /* read the PHY register */ 1213 status = hci1394_ohci_phy_read_no_lock(ohci_hdl, address, ®); 1214 if (status != DDI_SUCCESS) { 1215 mutex_exit(&ohci_hdl->ohci_mutex); 1216 TNF_PROBE_0(hci1394_ohci_phy_read_fail, 1217 HCI1394_TNF_HAL_ERROR, ""); 1218 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_clr_exit, 1219 HCI1394_TNF_HAL_STACK, ""); 1220 return (DDI_FAILURE); 1221 } 1222 1223 /* Set the bits and write the result back */ 1224 reg = reg & ~bits; 1225 status = hci1394_ohci_phy_write_no_lock(ohci_hdl, address, reg); 1226 if (status != DDI_SUCCESS) { 1227 mutex_exit(&ohci_hdl->ohci_mutex); 1228 TNF_PROBE_0(hci1394_ohci_phy_write_fail, 1229 HCI1394_TNF_HAL_ERROR, ""); 1230 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_clr_exit, 1231 HCI1394_TNF_HAL_STACK, ""); 1232 return (DDI_FAILURE); 1233 } 1234 1235 mutex_exit(&ohci_hdl->ohci_mutex); 1236 1237 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_clr_exit, HCI1394_TNF_HAL_STACK, 1238 ""); 1239 1240 return (DDI_SUCCESS); 1241 } 1242 1243 1244 /* 1245 * hci1394_ohci_phy_read() 1246 * Atomic PHY register read 1247 */ 1248 int 1249 hci1394_ohci_phy_read(hci1394_ohci_handle_t ohci_hdl, uint_t address, 1250 uint_t *data) 1251 { 1252 int status; 1253 1254 ASSERT(ohci_hdl != NULL); 1255 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_read_enter, HCI1394_TNF_HAL_STACK, 1256 ""); 1257 mutex_enter(&ohci_hdl->ohci_mutex); 1258 status = hci1394_ohci_phy_read_no_lock(ohci_hdl, address, data); 1259 mutex_exit(&ohci_hdl->ohci_mutex); 1260 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_read_exit, HCI1394_TNF_HAL_STACK, 1261 ""); 1262 1263 return (status); 1264 } 1265 1266 1267 /* 1268 * hci1394_ohci_phy_write() 1269 * Atomic PHY register write 1270 */ 1271 int 1272 hci1394_ohci_phy_write(hci1394_ohci_handle_t ohci_hdl, uint_t address, 1273 uint_t data) 1274 { 1275 int status; 1276 1277 ASSERT(ohci_hdl != NULL); 1278 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_write_enter, HCI1394_TNF_HAL_STACK, 1279 ""); 1280 mutex_enter(&ohci_hdl->ohci_mutex); 1281 status = hci1394_ohci_phy_write_no_lock(ohci_hdl, address, data); 1282 mutex_exit(&ohci_hdl->ohci_mutex); 1283 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_write_exit, HCI1394_TNF_HAL_STACK, 1284 ""); 1285 1286 return (status); 1287 } 1288 1289 1290 /* 1291 * hci1394_ohci_phy_read_no_lock() 1292 * This routine actually performs the PHY register read. It is seperated 1293 * out from phy_read so set & clr lock can perform an atomic PHY register 1294 * operation. It assumes the OpenHCI mutex is held. 1295 */ 1296 static int 1297 hci1394_ohci_phy_read_no_lock(hci1394_ohci_handle_t ohci_hdl, uint_t address, 1298 uint_t *data) 1299 { 1300 uint32_t ohci_reg; 1301 int count; 1302 1303 1304 ASSERT(ohci_hdl != NULL); 1305 ASSERT(data != NULL); 1306 ASSERT(MUTEX_HELD(&ohci_hdl->ohci_mutex)); 1307 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_read_no_lock_enter, 1308 HCI1394_TNF_HAL_STACK, ""); 1309 1310 /* You can't read or write PHY register #0 */ 1311 if (address == 0) { 1312 TNF_PROBE_1(hci1394_ohci_phy_addr_fail, HCI1394_TNF_HAL_ERROR, 1313 "", tnf_string, errmsg, "can't rd/wr PHY reg #0"); 1314 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_read_no_lock_exit, 1315 HCI1394_TNF_HAL_STACK, ""); 1316 return (DDI_FAILURE); 1317 } 1318 1319 /* Verify phy access not in progress */ 1320 ohci_reg = ddi_get32(ohci_hdl->ohci_reg_handle, 1321 &ohci_hdl->ohci_regs->phy_ctrl); 1322 if ((ohci_reg & (OHCI_PHYC_RDREG | OHCI_PHYC_WRREG)) != 0) { 1323 TNF_PROBE_1(hci1394_ohci_phy_xfer_fail, HCI1394_TNF_HAL_ERROR, 1324 "", tnf_string, errmsg, "transfer already in progress?"); 1325 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_read_no_lock_exit, 1326 HCI1394_TNF_HAL_STACK, ""); 1327 return (DDI_FAILURE); 1328 } 1329 1330 /* Start the PHY register read */ 1331 ohci_reg = OHCI_PHYC_RDREG | ((address & 0xF) << 1332 OHCI_PHYC_REGADDR_SHIFT); 1333 ddi_put32(ohci_hdl->ohci_reg_handle, &ohci_hdl->ohci_regs->phy_ctrl, 1334 ohci_reg); 1335 1336 /* 1337 * The PHY read usually takes less than 1uS. It is not worth having 1338 * this be interrupt driven. Having this be interrupt driven would also 1339 * make the bus reset and self id processing much more complex for 1340 * 1995 PHY's. We will wait up to hci1394_phy_delay_uS for the read 1341 * to complete (this was initially set to 10). I have yet to see 1342 * count > 1. The delay is a patchable variable. 1343 */ 1344 count = 0; 1345 while (count < hci1394_phy_delay_uS) { 1346 /* See if the read is done yet */ 1347 ohci_reg = ddi_get32(ohci_hdl->ohci_reg_handle, 1348 &ohci_hdl->ohci_regs->phy_ctrl); 1349 if ((ohci_reg & OHCI_PHYC_RDDONE) != 0) { 1350 /* 1351 * The read is done. clear the phyRegRecv interrupt. We 1352 * do not have this interrupt enabled but this keeps 1353 * things clean in case someone in the future does. 1354 * Break out of the loop, we are done. 1355 */ 1356 ddi_put32(ohci_hdl->ohci_reg_handle, 1357 &ohci_hdl->ohci_regs->intr_event_clr, 1358 OHCI_INTR_PHY_REG_RCVD); 1359 break; 1360 } 1361 1362 /* 1363 * the phy read did not yet complete, wait 1uS, increment the 1364 * count and try again. 1365 */ 1366 drv_usecwait(1); 1367 count++; 1368 } 1369 1370 /* Check to see if we timed out */ 1371 if (count >= hci1394_phy_delay_uS) { 1372 /* we timed out, return failure */ 1373 *data = 0; 1374 TNF_PROBE_0(hci1394_ohci_phy_rd_timeout_fail, 1375 HCI1394_TNF_HAL_ERROR, ""); 1376 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_read_no_lock_exit, 1377 HCI1394_TNF_HAL_STACK, ""); 1378 return (DDI_FAILURE); 1379 } 1380 1381 /* setup the PHY read data to be returned */ 1382 *data = (ddi_get32(ohci_hdl->ohci_reg_handle, 1383 &ohci_hdl->ohci_regs->phy_ctrl) & OHCI_PHYC_RDDATA_MASK) >> 1384 OHCI_PHYC_RDDATA_SHIFT; 1385 1386 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_read_no_lock_exit, 1387 HCI1394_TNF_HAL_STACK, ""); 1388 1389 return (DDI_SUCCESS); 1390 } 1391 1392 1393 /* 1394 * hci1394_ohci_phy_write_no_lock() 1395 * This routine actually performs the PHY register write. It is separated 1396 * out from phy_write so set & clr lock can perform an atomic PHY register 1397 * operation. It assumes the OpenHCI mutex is held. 1398 */ 1399 static int 1400 hci1394_ohci_phy_write_no_lock(hci1394_ohci_handle_t ohci_hdl, uint_t address, 1401 uint_t data) 1402 { 1403 uint32_t ohci_reg; 1404 int count; 1405 1406 1407 ASSERT(ohci_hdl != NULL); 1408 ASSERT(MUTEX_HELD(&ohci_hdl->ohci_mutex)); 1409 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_write_enter, 1410 HCI1394_TNF_HAL_STACK, ""); 1411 1412 /* You can't read or write PHY register #0 */ 1413 if (address == 0) { 1414 TNF_PROBE_1(hci1394_ohci_phy_addr_fail, HCI1394_TNF_HAL_ERROR, 1415 "", tnf_string, errmsg, "can't rd/wr PHY reg #0"); 1416 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_write_exit, 1417 HCI1394_TNF_HAL_STACK, ""); 1418 return (DDI_FAILURE); 1419 } 1420 1421 /* Verify phy access not in progress */ 1422 ohci_reg = ddi_get32(ohci_hdl->ohci_reg_handle, 1423 &ohci_hdl->ohci_regs->phy_ctrl); 1424 if ((ohci_reg & (OHCI_PHYC_RDREG | OHCI_PHYC_WRREG)) != 0) { 1425 TNF_PROBE_1(hci1394_ohci_phy_xfer_fail, HCI1394_TNF_HAL_ERROR, 1426 "", tnf_string, errmsg, "transfer already in progress?"); 1427 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_write_exit, 1428 HCI1394_TNF_HAL_STACK, ""); 1429 return (DDI_FAILURE); 1430 } 1431 1432 /* Start the PHY register write */ 1433 ohci_reg = OHCI_PHYC_WRREG | ((address & 0xF) << 1434 OHCI_PHYC_REGADDR_SHIFT) | (data & OHCI_PHYC_WRDATA_MASK); 1435 ddi_put32(ohci_hdl->ohci_reg_handle, 1436 &ohci_hdl->ohci_regs->phy_ctrl, ohci_reg); 1437 1438 /* 1439 * The PHY write usually takes less than 1uS. It is not worth having 1440 * this be interrupt driven. Having this be interrupt driven would also 1441 * make the bus reset and self id processing much more complex. We will 1442 * wait up to hci1394_phy_delay_uS for the write to complete (this was 1443 * initially set to 10). I have yet to see count > 0. The delay is a 1444 * patchable variable. 1445 */ 1446 count = 0; 1447 while (count < hci1394_phy_delay_uS) { 1448 /* See if the write is done yet */ 1449 ohci_reg = ddi_get32(ohci_hdl->ohci_reg_handle, 1450 &ohci_hdl->ohci_regs->phy_ctrl); 1451 if ((ohci_reg & OHCI_PHYC_WRREG) == 0) { 1452 /* 1453 * The write completed. Break out of the loop, we are 1454 * done. 1455 */ 1456 break; 1457 } 1458 1459 /* 1460 * the phy write did not yet complete, wait 1uS, increment the 1461 * count and try again. 1462 */ 1463 drv_usecwait(1); 1464 count++; 1465 } 1466 1467 /* Check to see if we timed out */ 1468 if (count >= hci1394_phy_delay_uS) { 1469 /* we timed out, return failure */ 1470 TNF_PROBE_0(hci1394_ohci_phy_wr_timeout_fail, 1471 HCI1394_TNF_HAL_ERROR, ""); 1472 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_write_exit, 1473 HCI1394_TNF_HAL_STACK, ""); 1474 return (DDI_FAILURE); 1475 } 1476 1477 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_write_exit, 1478 HCI1394_TNF_HAL_STACK, ""); 1479 1480 return (DDI_SUCCESS); 1481 } 1482 1483 1484 /* 1485 * hci1394_ohci_phy_info() 1486 * Return selfid word for our PHY. This routine should ONLY be called for 1487 * adapters with a 1394-1995 PHY. These PHY's do not embed their own selfid 1488 * information in the selfid buffer so we need to do it for them in the 1489 * selfid complete interrupt handler. This routine only supports building 1490 * selfid info for a 3 port PHY. Since we will probably not ever see a 1491 * 1394-1995 PHY in any production system, and if we do it will have 3 ports 1492 * or less, this is a pretty safe assumption. 1493 */ 1494 int 1495 hci1394_ohci_phy_info(hci1394_ohci_handle_t ohci_hdl, uint32_t *info) 1496 { 1497 int status; 1498 uint32_t phy_info; 1499 uint32_t reg; 1500 int index; 1501 int num_ports; 1502 int count; 1503 uint32_t port_status; 1504 1505 1506 ASSERT(ohci_hdl != NULL); 1507 ASSERT(info != NULL); 1508 ASSERT(ohci_hdl->ohci_phy == H1394_PHY_1995); 1509 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_info_enter, 1510 HCI1394_TNF_HAL_STACK, ""); 1511 1512 /* 1513 * Set Link on. We are using power class 0 since we have no idea what 1514 * our real power class is. 1515 */ 1516 phy_info = 0x80400000; 1517 1518 /* Add in Physical ID */ 1519 reg = ddi_get32(ohci_hdl->ohci_reg_handle, 1520 &ohci_hdl->ohci_regs->node_id); 1521 phy_info = phy_info | ((reg << IEEE1394_SELFID_PHYID_SHIFT) & 1522 IEEE1394_SELFID_PHYID_MASK); 1523 1524 /* Add in Gap Count */ 1525 status = hci1394_ohci_phy_read(ohci_hdl, 1, ®); 1526 if (status != DDI_SUCCESS) { 1527 TNF_PROBE_0(hci1394_ohci_phy_read_fail, 1528 HCI1394_TNF_HAL_ERROR, ""); 1529 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_info_exit, 1530 HCI1394_TNF_HAL_STACK, ""); 1531 return (DDI_FAILURE); 1532 } 1533 phy_info = phy_info | ((reg << IEEE1394_SELFID_GAP_CNT_SHIFT) & 1534 IEEE1394_SELFID_GAP_CNT_MASK); 1535 1536 /* Add in speed & ports */ 1537 status = hci1394_ohci_phy_read(ohci_hdl, 2, ®); 1538 if (status != DDI_SUCCESS) { 1539 TNF_PROBE_0(hci1394_ohci_phy_read_fail, 1540 HCI1394_TNF_HAL_ERROR, ""); 1541 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_info_exit, 1542 HCI1394_TNF_HAL_STACK, ""); 1543 return (DDI_FAILURE); 1544 } 1545 phy_info = phy_info | ((reg & 0xC0) << 8); 1546 num_ports = reg & 0x1F; 1547 1548 /* PHY reports that it has 0 ports?? */ 1549 if (num_ports == 0) { 1550 TNF_PROBE_1(hci1394_ohci_phy_zero_ports_fail, 1551 HCI1394_TNF_HAL_ERROR, "", tnf_string, errmsg, 1552 "1995 phy has zero ports?"); 1553 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_info_exit, 1554 HCI1394_TNF_HAL_STACK, ""); 1555 return (DDI_FAILURE); 1556 } 1557 1558 /* Build up the port information for each port in the PHY */ 1559 count = 0; 1560 for (index = 0; index < 3; index++) { 1561 if (num_ports > 0) { 1562 status = hci1394_ohci_phy_read(ohci_hdl, 1563 count + 3, ®); 1564 if (status != DDI_SUCCESS) { 1565 TNF_PROBE_0(hci1394_ohci_phy_read_fail, 1566 HCI1394_TNF_HAL_ERROR, ""); 1567 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_info_exit, 1568 HCI1394_TNF_HAL_STACK, ""); 1569 return (DDI_FAILURE); 1570 } 1571 /* if port is not connected */ 1572 if ((reg & 0x04) == 0) { 1573 port_status = 1574 IEEE1394_SELFID_PORT_NOT_CONNECTED; 1575 1576 /* else if port is connected to parent */ 1577 } else if ((reg & 0x08) == 0) { 1578 port_status = IEEE1394_SELFID_PORT_TO_PARENT; 1579 1580 /* else port is connected to child */ 1581 } else { 1582 port_status = IEEE1394_SELFID_PORT_TO_CHILD; 1583 } 1584 1585 num_ports--; 1586 } else { 1587 port_status = IEEE1394_SELFID_PORT_NO_PORT; 1588 } 1589 1590 /* add in the port information */ 1591 phy_info = phy_info | (port_status << (6 - (index * 2))); 1592 count++; 1593 } 1594 1595 /* Copy the PHY selfid info to the return parameter */ 1596 *info = phy_info; 1597 1598 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_info_exit, 1599 HCI1394_TNF_HAL_STACK, ""); 1600 1601 return (DDI_SUCCESS); 1602 } 1603 1604 1605 /* 1606 * hci1394_ohci_current_busgen() 1607 * return the current bus generation. 1608 */ 1609 uint_t 1610 hci1394_ohci_current_busgen(hci1394_ohci_handle_t ohci_hdl) 1611 { 1612 uint32_t reg; 1613 uint_t generation_count; 1614 1615 1616 ASSERT(ohci_hdl != NULL); 1617 TNF_PROBE_0_DEBUG(hci1394_ohci_current_busgen_enter, 1618 HCI1394_TNF_HAL_STACK, ""); 1619 1620 reg = ddi_get32(ohci_hdl->ohci_reg_handle, 1621 &ohci_hdl->ohci_regs->self_id_count); 1622 generation_count = (reg & OHCI_SLFC_GEN_MASK) >> OHCI_SLFC_GEN_SHIFT; 1623 1624 TNF_PROBE_0_DEBUG(hci1394_ohci_current_busgen_exit, 1625 HCI1394_TNF_HAL_STACK, ""); 1626 1627 return (generation_count); 1628 } 1629 1630 1631 /* 1632 * hci1394_ohci_startup() 1633 * Startup the 1394 nexus driver. This is called after all of the HW has 1634 * been initialized (in both attach and resume) and we are ready to 1635 * participate on the bus. 1636 */ 1637 int 1638 hci1394_ohci_startup(hci1394_ohci_handle_t ohci_hdl) 1639 { 1640 int status; 1641 1642 1643 ASSERT(ohci_hdl != NULL); 1644 TNF_PROBE_0_DEBUG(hci1394_ohci_startup_enter, 1645 HCI1394_TNF_HAL_STACK, ""); 1646 1647 /* 1648 * Turn on 1394 link. This allows us to receive 1394 traffic off the 1649 * bus 1650 */ 1651 hci1394_ohci_link_enable(ohci_hdl); 1652 1653 /* 1654 * Reset the 1394 Bus. 1655 * Need to do this so that the link layer can collect all of the self-id 1656 * packets. The Interrupt routine will cause further initialization 1657 * after the bus reset has completed 1658 */ 1659 status = hci1394_ohci_bus_reset(ohci_hdl); 1660 if (status != DDI_SUCCESS) { 1661 TNF_PROBE_1_DEBUG(hci1394_ohci_startup_exit, 1662 HCI1394_TNF_HAL_ERROR, "", tnf_string, errmsg, 1663 "failed to reset bus"); 1664 TNF_PROBE_0_DEBUG(hci1394_ohci_startup_exit, 1665 HCI1394_TNF_HAL_STACK, ""); 1666 return (DDI_FAILURE); 1667 } 1668 1669 /* setup out initial interrupt mask and enable interrupts */ 1670 hci1394_isr_mask_setup(ohci_hdl->soft_state); 1671 hci1394_ohci_intr_master_enable(ohci_hdl); 1672 1673 TNF_PROBE_0_DEBUG(hci1394_ohci_startup_exit, HCI1394_TNF_HAL_STACK, 1674 ""); 1675 1676 return (DDI_SUCCESS); 1677 } 1678 1679 1680 /* 1681 * hci1394_ohci_postwr_addr() 1682 * Read the Posted Write Address registers. This should be read when a 1683 * posted write error is detected to find out what transaction had an error. 1684 */ 1685 void 1686 hci1394_ohci_postwr_addr(hci1394_ohci_handle_t ohci_hdl, uint64_t *addr) 1687 { 1688 uint32_t reg; 1689 1690 1691 ASSERT(ohci_hdl != NULL); 1692 ASSERT(addr != NULL); 1693 TNF_PROBE_0_DEBUG(hci1394_ohci_postwr_addr_enter, 1694 HCI1394_TNF_HAL_STACK, ""); 1695 1696 /* read in the errored address */ 1697 reg = ddi_get32(ohci_hdl->ohci_reg_handle, 1698 &ohci_hdl->ohci_regs->posted_write_addrhi); 1699 *addr = ((uint64_t)reg) << 32; 1700 reg = ddi_get32(ohci_hdl->ohci_reg_handle, 1701 &ohci_hdl->ohci_regs->posted_write_addrlo); 1702 *addr = *addr | (uint64_t)reg; 1703 1704 /* 1705 * Interrupt should be cleared after reading the posted write address. 1706 * See 13.2.8.1 in OpenHCI spec v1.0. 1707 */ 1708 hci1394_ohci_intr_clear(ohci_hdl, OHCI_INTR_POST_WR_ERR); 1709 1710 TNF_PROBE_0_DEBUG(hci1394_ohci_postwr_addr_exit, 1711 HCI1394_TNF_HAL_STACK, ""); 1712 } 1713 1714 1715 /* 1716 * hci1394_ohci_guid() 1717 * Return the adapter's GUID 1718 */ 1719 uint64_t 1720 hci1394_ohci_guid(hci1394_ohci_handle_t ohci_hdl) 1721 { 1722 uint32_t reg; 1723 uint64_t guid; 1724 1725 1726 ASSERT(ohci_hdl != NULL); 1727 TNF_PROBE_0_DEBUG(hci1394_ohci_guid_enter, HCI1394_TNF_HAL_STACK, ""); 1728 1729 reg = ddi_get32(ohci_hdl->ohci_reg_handle, 1730 &ohci_hdl->ohci_regs->guid_hi); 1731 guid = ((uint64_t)reg) << 32; 1732 reg = ddi_get32(ohci_hdl->ohci_reg_handle, 1733 &ohci_hdl->ohci_regs->guid_lo); 1734 guid = guid | (uint64_t)reg; 1735 1736 TNF_PROBE_0_DEBUG(hci1394_ohci_guid_exit, HCI1394_TNF_HAL_STACK, ""); 1737 1738 return (guid); 1739 } 1740 1741 1742 /* 1743 * hci1394_ohci_csr_read() 1744 * Read one of the HW implemented CSR registers. These include 1745 * bus_manager_id, bandwidth_available, channels_available_hi, and 1746 * channels_available_lo. Offset should be set to 1747 * OHCI_CSR_SEL_BUS_MGR_ID, OHCI_CSR_SEL_BANDWIDTH_AVAIL 1748 * OHCI_CSR_SEL_CHANS_AVAIL_HI, or OHCI_CSR_SEL_CHANS_AVAIL_LO. 1749 */ 1750 int 1751 hci1394_ohci_csr_read(hci1394_ohci_handle_t ohci_hdl, uint_t offset, 1752 uint32_t *data) 1753 { 1754 uint_t generation; 1755 int status; 1756 1757 1758 ASSERT(ohci_hdl != NULL); 1759 ASSERT(data != NULL); 1760 TNF_PROBE_0_DEBUG(hci1394_ohci_csr_read_enter, HCI1394_TNF_HAL_STACK, 1761 ""); 1762 1763 /* 1764 * read the CSR register by doing a cswap with the same compare and 1765 * swap value. 1766 */ 1767 generation = hci1394_ohci_current_busgen(ohci_hdl); 1768 status = hci1394_ohci_csr_cswap(ohci_hdl, generation, offset, 0, 0, 1769 data); 1770 if (status != DDI_SUCCESS) { 1771 TNF_PROBE_0(hci1394_ohci_csr_read_csw_fail, 1772 HCI1394_TNF_HAL_ERROR, ""); 1773 TNF_PROBE_0_DEBUG(hci1394_ohci_csr_read_exit, 1774 HCI1394_TNF_HAL_STACK, ""); 1775 return (DDI_FAILURE); 1776 } 1777 1778 TNF_PROBE_0_DEBUG(hci1394_ohci_csr_read_exit, HCI1394_TNF_HAL_STACK, 1779 ""); 1780 1781 return (DDI_SUCCESS); 1782 } 1783 1784 1785 /* 1786 * hci1394_ohci_csr_cswap() 1787 * Perform a compare/swap on one of the HW implemented CSR registers. These 1788 * include bus_manager_id, bandwidth_available, channels_available_hi, and 1789 * channels_available_lo. Offset should be set to 1790 * OHCI_CSR_SEL_BUS_MGR_ID, OHCI_CSR_SEL_BANDWIDTH_AVAIL 1791 * OHCI_CSR_SEL_CHANS_AVAIL_HI, or OHCI_CSR_SEL_CHANS_AVAIL_LO. 1792 */ 1793 int 1794 hci1394_ohci_csr_cswap(hci1394_ohci_handle_t ohci_hdl, uint_t generation, 1795 uint_t offset, uint32_t compare, uint32_t swap, uint32_t *old) 1796 { 1797 int count; 1798 uint32_t ohci_reg; 1799 1800 1801 ASSERT(ohci_hdl != NULL); 1802 ASSERT(old != NULL); 1803 TNF_PROBE_0_DEBUG(hci1394_ohci_csr_cswap_enter, 1804 HCI1394_TNF_HAL_STACK, ""); 1805 1806 /* 1807 * Make sure we have not gotten a bus reset since this action was 1808 * started. 1809 */ 1810 if (generation != hci1394_ohci_current_busgen(ohci_hdl)) { 1811 TNF_PROBE_1(hci1394_ohci_invbusgen_fail, HCI1394_TNF_HAL_ERROR, 1812 "", tnf_string, errmsg, "Invalid Bus Generation"); 1813 TNF_PROBE_0_DEBUG(hci1394_ohci_csr_cswap_exit, 1814 HCI1394_TNF_HAL_STACK, ""); 1815 return (DDI_FAILURE); 1816 } 1817 1818 mutex_enter(&ohci_hdl->ohci_mutex); 1819 1820 /* init csrData and csrCompare */ 1821 ddi_put32(ohci_hdl->ohci_reg_handle, 1822 &ohci_hdl->ohci_regs->csr_data, swap); 1823 ddi_put32(ohci_hdl->ohci_reg_handle, 1824 &ohci_hdl->ohci_regs->csr_compare_data, compare); 1825 1826 /* start the compare swap */ 1827 ddi_put32(ohci_hdl->ohci_reg_handle, 1828 &ohci_hdl->ohci_regs->csr_ctrl, offset & OHCI_CSR_SELECT); 1829 1830 /* 1831 * The CSR access should be immediate. There in nothing that officially 1832 * states this so we will wait up to 2uS just in case before we timeout. 1833 * We actually perform a compare swap with both compare and swap set 1834 * to the same value. This will return the old value which is in 1835 * essence, a read. 1836 */ 1837 count = 0; 1838 while (count < 2) { 1839 /* See if the compare swap is done */ 1840 ohci_reg = ddi_get32(ohci_hdl->ohci_reg_handle, 1841 &ohci_hdl->ohci_regs->csr_ctrl); 1842 if ((ohci_reg & OHCI_CSR_DONE) != 0) { 1843 /* The compare swap is done, break out of the loop */ 1844 break; 1845 } 1846 /* 1847 * The compare swap has not completed yet, wait 1uS, increment 1848 * the count and try again 1849 */ 1850 drv_usecwait(1); 1851 count++; 1852 } 1853 1854 /* If we timed out, return an error */ 1855 if (count >= 2) { 1856 *old = 0; 1857 mutex_exit(&ohci_hdl->ohci_mutex); 1858 TNF_PROBE_0(hci1394_ohci_phy_csr_timeout_fail, 1859 HCI1394_TNF_HAL_ERROR, ""); 1860 TNF_PROBE_0_DEBUG(hci1394_ohci_csr_cswap_exit, 1861 HCI1394_TNF_HAL_STACK, ""); 1862 return (DDI_FAILURE); 1863 } 1864 1865 /* Copy the old data into the return parameter */ 1866 *old = ddi_get32(ohci_hdl->ohci_reg_handle, 1867 &ohci_hdl->ohci_regs->csr_data); 1868 1869 mutex_exit(&ohci_hdl->ohci_mutex); 1870 1871 /* 1872 * There is a race condition in the OpenHCI design here. After checking 1873 * the generation and before performing the cswap, we could get a bus 1874 * reset and incorrectly set something like the bus manager. This would 1875 * put us into a condition where we would not have a bus manager and 1876 * we would think there was one. If it is possible that this race 1877 * condition occured, we will reset the bus to clean things up. We only 1878 * care about this if the compare swap was successful. 1879 */ 1880 if (generation != hci1394_ohci_current_busgen(ohci_hdl)) { 1881 if (*old == compare) { 1882 (void) hci1394_ohci_bus_reset(ohci_hdl); 1883 TNF_PROBE_1(hci1394_ohci_invbusgen_fail, 1884 HCI1394_TNF_HAL_ERROR, "", tnf_string, errmsg, 1885 "Invalid Bus Generation"); 1886 TNF_PROBE_0_DEBUG(hci1394_ohci_csr_cswap_exit, 1887 HCI1394_TNF_HAL_STACK, ""); 1888 return (DDI_FAILURE); 1889 } 1890 } 1891 1892 TNF_PROBE_0_DEBUG(hci1394_ohci_csr_cswap_exit, HCI1394_TNF_HAL_STACK, 1893 ""); 1894 1895 return (DDI_SUCCESS); 1896 } 1897 1898 1899 /* 1900 * hci1394_ohci_contender_enable() 1901 * Set the contender bit in the PHY. This routine should only be called 1902 * if our PHY is 1394A compliant. (i.e. this routine should not be called 1903 * for a 1394-1995 PHY). 1904 */ 1905 int 1906 hci1394_ohci_contender_enable(hci1394_ohci_handle_t ohci_hdl) 1907 { 1908 int status; 1909 1910 1911 ASSERT(ohci_hdl != NULL); 1912 TNF_PROBE_0_DEBUG(hci1394_ohci_contender_enable_enter, 1913 HCI1394_TNF_HAL_STACK, ""); 1914 1915 /* 1916 * Make sure that phy is not a 1394-1995 phy. Those phy's do not have a 1917 * contender bit to set. 1918 */ 1919 if (ohci_hdl->ohci_phy == H1394_PHY_1995) { 1920 TNF_PROBE_0(hci1394_ohci_phy_type_fail, 1921 HCI1394_TNF_HAL_ERROR, ""); 1922 TNF_PROBE_0_DEBUG(hci1394_ohci_contender_enable_exit, 1923 HCI1394_TNF_HAL_STACK, ""); 1924 return (DDI_FAILURE); 1925 } 1926 1927 /* Set the Contender Bit */ 1928 status = hci1394_ohci_phy_set(ohci_hdl, 0x4, OHCI_PHY_CNTDR); 1929 if (status != DDI_SUCCESS) { 1930 TNF_PROBE_0(hci1394_ohci_phy_set_fail, 1931 HCI1394_TNF_HAL_ERROR, ""); 1932 TNF_PROBE_0_DEBUG(hci1394_ohci_contender_enable_exit, 1933 HCI1394_TNF_HAL_STACK, ""); 1934 return (DDI_FAILURE); 1935 } 1936 1937 TNF_PROBE_0_DEBUG(hci1394_ohci_contender_enable_exit, 1938 HCI1394_TNF_HAL_STACK, ""); 1939 1940 return (DDI_SUCCESS); 1941 } 1942 1943 1944 /* 1945 * hci1394_ohci_root_holdoff_enable() 1946 * Set the root holdoff bit in the PHY. Since there are race conditions when 1947 * writing to PHY register 1 (which can get updated from a PHY packet off the 1948 * bus), we cache this state until a "long" bus reset is issued. 1949 */ 1950 int 1951 hci1394_ohci_root_holdoff_enable(hci1394_ohci_handle_t ohci_hdl) 1952 { 1953 ASSERT(ohci_hdl != NULL); 1954 TNF_PROBE_0_DEBUG(hci1394_ohci_root_holdoff_enable_enter, 1955 HCI1394_TNF_HAL_STACK, ""); 1956 1957 ohci_hdl->ohci_set_root_holdoff = B_TRUE; 1958 1959 TNF_PROBE_0_DEBUG(hci1394_ohci_root_holdoff_enable_exit, 1960 HCI1394_TNF_HAL_STACK, ""); 1961 1962 return (DDI_SUCCESS); 1963 } 1964 1965 1966 /* 1967 * hci1394_ohci_gap_count_set() 1968 * Set the gap count in the PHY. Since there are race conditions when writing 1969 * to PHY register 1 (which can get updated from a PHY packet off the bus), 1970 * we cache this gap count until a "long" bus reset is issued. 1971 */ 1972 int 1973 hci1394_ohci_gap_count_set(hci1394_ohci_handle_t ohci_hdl, uint_t gap_count) 1974 { 1975 ASSERT(ohci_hdl != NULL); 1976 TNF_PROBE_0_DEBUG(hci1394_ohci_gap_count_set_enter, 1977 HCI1394_TNF_HAL_STACK, ""); 1978 1979 ohci_hdl->ohci_set_gap_count = B_TRUE; 1980 ohci_hdl->ohci_gap_count = gap_count & OHCI_PHY_MAX_GAP; 1981 1982 TNF_PROBE_0_DEBUG(hci1394_ohci_gap_count_set_exit, 1983 HCI1394_TNF_HAL_STACK, ""); 1984 1985 return (DDI_SUCCESS); 1986 } 1987 1988 1989 /* 1990 * hci1394_ohci_phy_filter_set() 1991 * Enable a node (or nodes) to perform transactions to our physical 1992 * memory. OpenHCI allows you to disable/enable physical requests on a node 1993 * per node basis. A physical request is basically a read/write to 1394 1994 * address space 0x0 - 0xFFFFFFFF. This address goes out to the IO MMU (in 1995 * the case of a SPARC machine). The HAL starts with all nodes unable to 1996 * read/write physical memory. The Services Layer will call down and enable 1997 * nodes via setting a physical filter bit for that given node. Since node 1998 * numbers change every bus reset, the services layer has to call down after 1999 * every bus reset to re-enable physical accesses. (NOTE: the hardware 2000 * automatically clears these bits. 2001 */ 2002 int 2003 hci1394_ohci_phy_filter_set(hci1394_ohci_handle_t ohci_hdl, uint64_t mask, 2004 uint_t generation) 2005 { 2006 uint32_t data; 2007 2008 2009 ASSERT(ohci_hdl != NULL); 2010 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_filter_set_enter, 2011 HCI1394_TNF_HAL_STACK, ""); 2012 2013 /* 2014 * Make sure we have not gotten a bus reset since this action was 2015 * started. 2016 */ 2017 if (generation != hci1394_ohci_current_busgen(ohci_hdl)) { 2018 TNF_PROBE_1(hci1394_ohci_invbusgen_fail, HCI1394_TNF_HAL_ERROR, 2019 "", tnf_string, errmsg, "Invalid Bus Generation"); 2020 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_filter_set_exit, 2021 HCI1394_TNF_HAL_STACK, ""); 2022 return (DDI_FAILURE); 2023 } 2024 2025 data = (uint32_t)((mask >> 32) & 0xFFFFFFFF); 2026 ddi_put32(ohci_hdl->ohci_reg_handle, 2027 &ohci_hdl->ohci_regs->phys_req_filterhi_set, data); 2028 data = (uint32_t)(mask & 0xFFFFFFFF); 2029 ddi_put32(ohci_hdl->ohci_reg_handle, 2030 &ohci_hdl->ohci_regs->phys_req_filterlo_set, data); 2031 2032 /* 2033 * There is a race condition in the OpenHCI design here. After checking 2034 * the generation and before setting the physical filter bits, we could 2035 * get a bus reset and incorrectly set the physical filter bits. If it 2036 * is possible that this race condition occured, we will reset the bus 2037 * to clean things up. 2038 */ 2039 if (generation != hci1394_ohci_current_busgen(ohci_hdl)) { 2040 (void) hci1394_ohci_bus_reset(ohci_hdl); 2041 TNF_PROBE_1(hci1394_ohci_filterrace_fail, HCI1394_TNF_HAL_ERROR, 2042 "", tnf_string, errmsg, "Invalid Bus Generation"); 2043 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_filter_set_exit, 2044 HCI1394_TNF_HAL_STACK, ""); 2045 return (DDI_SUCCESS); 2046 } 2047 2048 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_filter_set_exit, 2049 HCI1394_TNF_HAL_STACK, ""); 2050 2051 return (DDI_SUCCESS); 2052 } 2053 2054 2055 /* 2056 * hci1394_ohci_phy_filter_clr() 2057 * Disable a node (or nodes) from performing transactions to our physical 2058 * memory. See hci1394_ohci_phy_filter_set() above for more info. 2059 */ 2060 int 2061 hci1394_ohci_phy_filter_clr(hci1394_ohci_handle_t ohci_hdl, 2062 uint64_t mask, uint_t generation) 2063 { 2064 uint32_t data; 2065 2066 2067 ASSERT(ohci_hdl != NULL); 2068 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_filter_clr_enter, 2069 HCI1394_TNF_HAL_STACK, ""); 2070 2071 /* 2072 * Make sure we have not gotten a bus reset since this action was 2073 * started. 2074 */ 2075 if (generation != hci1394_ohci_current_busgen(ohci_hdl)) { 2076 TNF_PROBE_1(hci1394_ohci_invbusgen_fail, HCI1394_TNF_HAL_ERROR, 2077 "", tnf_string, errmsg, "Invalid Bus Generation"); 2078 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_filter_clr_exit, 2079 HCI1394_TNF_HAL_STACK, ""); 2080 return (DDI_FAILURE); 2081 } 2082 2083 data = (uint32_t)((mask >> 32) & 0xFFFFFFFF); 2084 ddi_put32(ohci_hdl->ohci_reg_handle, 2085 &ohci_hdl->ohci_regs->phys_req_filterhi_clr, data); 2086 data = (uint32_t)(mask & 0xFFFFFFFF); 2087 ddi_put32(ohci_hdl->ohci_reg_handle, 2088 &ohci_hdl->ohci_regs->phys_req_filterlo_clr, data); 2089 2090 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_filter_clr_exit, 2091 HCI1394_TNF_HAL_STACK, ""); 2092 2093 return (DDI_SUCCESS); 2094 } 2095 2096 2097 /* 2098 * hci1394_ohci_bus_reset_short() 2099 * Perform a 1394A short bus reset. This function should only be called 2100 * on an adapter with a 1394A PHY (or later). 2101 */ 2102 int 2103 hci1394_ohci_bus_reset_short(hci1394_ohci_handle_t ohci_hdl) 2104 { 2105 int status; 2106 2107 ASSERT(ohci_hdl != NULL); 2108 TNF_PROBE_0_DEBUG(hci1394_ohci_bus_reset_short_enter, 2109 HCI1394_TNF_HAL_STACK, ""); 2110 2111 /* 2112 * Make sure that phy is not a 1394-1995 phy. Those phy's do not have a 2113 * contender bit to set. 2114 */ 2115 if (ohci_hdl->ohci_phy == H1394_PHY_1995) { 2116 TNF_PROBE_0(hci1394_ohci_brs_phy_fail, 2117 HCI1394_TNF_HAL_ERROR, ""); 2118 TNF_PROBE_0_DEBUG(hci1394_ohci_bus_reset_short_exit, 2119 HCI1394_TNF_HAL_STACK, ""); 2120 return (DDI_FAILURE); 2121 } 2122 2123 /* Initiate the short bus reset */ 2124 status = hci1394_ohci_phy_set(ohci_hdl, 0x5, OHCI_PHY_ISBR); 2125 if (status != DDI_SUCCESS) { 2126 TNF_PROBE_0(hci1394_ohci_phy_set_fail, 2127 HCI1394_TNF_HAL_ERROR, ""); 2128 TNF_PROBE_0_DEBUG(hci1394_ohci_bus_reset_short_exit, 2129 HCI1394_TNF_HAL_STACK, ""); 2130 return (DDI_FAILURE); 2131 } 2132 2133 TNF_PROBE_0_DEBUG(hci1394_ohci_bus_reset_short_exit, 2134 HCI1394_TNF_HAL_STACK, ""); 2135 2136 return (status); 2137 } 2138 2139 2140 /* 2141 * hci1394_ohci_cfgrom_update() 2142 * Update the config rom with the provided contents. The config rom is 2143 * provided as a byte stream which is multiple of 4 bytes large. The 2144 * size is passed as a quadlet (4 bytes) count. The entire contents 2145 * of the config rom is updated at once. We do not provide a partial 2146 * update interface. 2147 */ 2148 void 2149 hci1394_ohci_cfgrom_update(hci1394_ohci_handle_t ohci_hdl, void *local_buf, 2150 uint_t quadlet_count) 2151 { 2152 uint32_t *data; 2153 2154 2155 ASSERT(ohci_hdl != NULL); 2156 ASSERT(local_buf != NULL); 2157 TNF_PROBE_0_DEBUG(hci1394_ohci_cfgrom_update_enter, 2158 HCI1394_TNF_HAL_STACK, ""); 2159 2160 data = (uint32_t *)local_buf; 2161 2162 /* zero out the config ROM header to start */ 2163 ddi_put32(ohci_hdl->ohci_reg_handle, 2164 &ohci_hdl->ohci_regs->config_rom_hdr, 0); 2165 2166 /* copy Services Layer buffer into config rom buffer */ 2167 ddi_rep_put8(ohci_hdl->ohci_cfgrom.bi_handle, local_buf, 2168 (uint8_t *)ohci_hdl->ohci_cfgrom.bi_kaddr, quadlet_count << 2, 2169 DDI_DEV_AUTOINCR); 2170 2171 (void) ddi_dma_sync(ohci_hdl->ohci_cfgrom.bi_dma_handle, 0, 2172 quadlet_count << 2, DDI_DMA_SYNC_FORDEV); 2173 2174 /* 2175 * setup OHCI bus options and config rom hdr registers. We need to swap 2176 * the config rom header and bus options on an X86 machine since the 2177 * data is provided to us as a byte stream and the OHCI registers expect 2178 * a big endian 32-bit number. 2179 */ 2180 ddi_put32(ohci_hdl->ohci_reg_handle, 2181 &ohci_hdl->ohci_regs->bus_options, OHCI_SWAP32(data[2])); 2182 ddi_put32(ohci_hdl->ohci_reg_handle, 2183 &ohci_hdl->ohci_regs->config_rom_hdr, OHCI_SWAP32(data[0])); 2184 2185 TNF_PROBE_0_DEBUG(hci1394_ohci_cfgrom_update_exit, 2186 HCI1394_TNF_HAL_STACK, ""); 2187 } 2188 2189 2190 /* 2191 * hci1394_ohci_nodeid_get() 2192 * Return our current nodeid (bus #/Node #) 2193 */ 2194 void 2195 hci1394_ohci_nodeid_get(hci1394_ohci_handle_t ohci_hdl, uint_t *nodeid) 2196 { 2197 uint32_t reg; 2198 2199 ASSERT(ohci_hdl != NULL); 2200 ASSERT(nodeid != NULL); 2201 TNF_PROBE_0_DEBUG(hci1394_ohci_nodeid_get_enter, HCI1394_TNF_HAL_STACK, 2202 ""); 2203 reg = ddi_get32(ohci_hdl->ohci_reg_handle, 2204 &ohci_hdl->ohci_regs->node_id); 2205 *nodeid = (reg & 0xFFFF) << 16; 2206 TNF_PROBE_0_DEBUG(hci1394_ohci_nodeid_get_exit, HCI1394_TNF_HAL_STACK, 2207 ""); 2208 } 2209 2210 2211 /* 2212 * hci1394_ohci_nodeid_set() 2213 * Set our current nodeid (bus #/Node #). This actually sets our bus number. 2214 * Our node number cannot be set by software. This is usually trigered via 2215 * a write to the CSR NODEIDS register. 2216 */ 2217 void 2218 hci1394_ohci_nodeid_set(hci1394_ohci_handle_t ohci_hdl, uint_t nodeid) 2219 { 2220 uint32_t reg; 2221 2222 ASSERT(ohci_hdl != NULL); 2223 TNF_PROBE_0_DEBUG(hci1394_ohci_nodeid_set_enter, 2224 HCI1394_TNF_HAL_STACK, ""); 2225 2226 reg = ((nodeid & 0xFFC00000) >> 16); 2227 ddi_put32(ohci_hdl->ohci_reg_handle, 2228 &ohci_hdl->ohci_regs->node_id, reg); 2229 2230 TNF_PROBE_0_DEBUG(hci1394_ohci_nodeid_set_exit, 2231 HCI1394_TNF_HAL_STACK, ""); 2232 } 2233 2234 2235 /* 2236 * hci1394_ohci_nodeid_info() 2237 * Return our current nodeid (bus #/Node #). This also returns whether or 2238 * not our nodeid error bit is set. This is useful in determining if the 2239 * bus reset completed without errors in the selfid complete interrupt 2240 * processing. 2241 */ 2242 void 2243 hci1394_ohci_nodeid_info(hci1394_ohci_handle_t ohci_hdl, uint_t *nodeid, 2244 boolean_t *error) 2245 { 2246 uint32_t reg; 2247 2248 ASSERT(ohci_hdl != NULL); 2249 ASSERT(nodeid != NULL); 2250 TNF_PROBE_0_DEBUG(hci1394_ohci_nodeid_info_enter, 2251 HCI1394_TNF_HAL_STACK, ""); 2252 2253 reg = ddi_get32(ohci_hdl->ohci_reg_handle, 2254 &ohci_hdl->ohci_regs->node_id); 2255 *nodeid = reg & 0xFFFF; 2256 if ((reg & OHCI_NDID_IDVALID) == 0) { 2257 *error = B_TRUE; 2258 } else { 2259 *error = B_FALSE; 2260 } 2261 2262 TNF_PROBE_0_DEBUG(hci1394_ohci_nodeid_info_exit, 2263 HCI1394_TNF_HAL_STACK, ""); 2264 } 2265 2266 2267 /* 2268 * hci1394_ohci_cycletime_get() 2269 * Return the current cycle time 2270 */ 2271 void 2272 hci1394_ohci_cycletime_get(hci1394_ohci_handle_t ohci_hdl, 2273 uint32_t *cycle_time) 2274 { 2275 ASSERT(ohci_hdl != NULL); 2276 ASSERT(cycle_time != NULL); 2277 TNF_PROBE_0_DEBUG(hci1394_ohci_cycletime_get_enter, 2278 HCI1394_TNF_HAL_STACK, ""); 2279 *cycle_time = ddi_get32(ohci_hdl->ohci_reg_handle, 2280 &ohci_hdl->ohci_regs->isoch_cycle_timer); 2281 TNF_PROBE_0_DEBUG(hci1394_ohci_cycletime_get_exit, 2282 HCI1394_TNF_HAL_STACK, ""); 2283 } 2284 2285 2286 /* 2287 * hci1394_ohci_cycletime_get() 2288 * Set the cycle time 2289 */ 2290 void 2291 hci1394_ohci_cycletime_set(hci1394_ohci_handle_t ohci_hdl, 2292 uint32_t cycle_time) 2293 { 2294 ASSERT(ohci_hdl != NULL); 2295 TNF_PROBE_0_DEBUG(hci1394_ohci_cycletime_set_enter, 2296 HCI1394_TNF_HAL_STACK, ""); 2297 ddi_put32(ohci_hdl->ohci_reg_handle, 2298 &ohci_hdl->ohci_regs->isoch_cycle_timer, cycle_time); 2299 TNF_PROBE_0_DEBUG(hci1394_ohci_cycletime_set_exit, 2300 HCI1394_TNF_HAL_STACK, ""); 2301 } 2302 2303 2304 /* 2305 * hci1394_ohci_bustime_get() 2306 * Return the current bus time. 2307 */ 2308 void 2309 hci1394_ohci_bustime_get(hci1394_ohci_handle_t ohci_hdl, uint32_t *bus_time) 2310 { 2311 uint32_t bus_time1; 2312 uint32_t bus_time2; 2313 uint32_t cycle_time; 2314 2315 2316 ASSERT(ohci_hdl != NULL); 2317 ASSERT(bus_time != NULL); 2318 TNF_PROBE_0_DEBUG(hci1394_ohci_bustime_get_enter, 2319 HCI1394_TNF_HAL_STACK, ""); 2320 2321 /* 2322 * The bus time is composed of a portion of the cycle time and the 2323 * cycle time rollover count (ohci_bustime_count). There is a race 2324 * condition where we read the rollover count and then the cycle 2325 * timer rolls over. This is the reason for the double read of the 2326 * rollover count. 2327 */ 2328 do { 2329 bus_time1 = ohci_hdl->ohci_bustime_count; 2330 cycle_time = ddi_get32(ohci_hdl->ohci_reg_handle, 2331 &ohci_hdl->ohci_regs->isoch_cycle_timer); 2332 bus_time2 = ohci_hdl->ohci_bustime_count; 2333 } while (bus_time1 != bus_time2); 2334 2335 *bus_time = (bus_time2 << 7) | (cycle_time >> 25); 2336 2337 TNF_PROBE_0_DEBUG(hci1394_ohci_bustime_get_exit, 2338 HCI1394_TNF_HAL_STACK, ""); 2339 } 2340 2341 2342 /* 2343 * hci1394_ohci_bustime_set() 2344 * Set the cycle timer rollover portion of the bus time. 2345 */ 2346 void 2347 hci1394_ohci_bustime_set(hci1394_ohci_handle_t ohci_hdl, uint32_t bus_time) 2348 { 2349 ASSERT(ohci_hdl != NULL); 2350 TNF_PROBE_0_DEBUG(hci1394_ohci_bustime_set_enter, 2351 HCI1394_TNF_HAL_STACK, ""); 2352 2353 /* 2354 * we will start with the cycle 64 seconds interrupt disabled. If this 2355 * is the first write to bus time, enable the interrupt. 2356 */ 2357 if (ohci_hdl->ohci_bustime_enabled == B_FALSE) { 2358 ohci_hdl->ohci_bustime_enabled = B_TRUE; 2359 /* Clear the cycle64Seconds interrupt then enable it */ 2360 hci1394_ohci_intr_clear(ohci_hdl, OHCI_INTR_CYC_64_SECS); 2361 hci1394_ohci_intr_enable(ohci_hdl, OHCI_INTR_CYC_64_SECS); 2362 } 2363 ohci_hdl->ohci_bustime_count = (bus_time >> 7); 2364 2365 TNF_PROBE_0_DEBUG(hci1394_ohci_bustime_set_exit, 2366 HCI1394_TNF_HAL_STACK, ""); 2367 } 2368 2369 2370 /* 2371 * hci1394_ohci_atreq_retries_get() 2372 * Get the number of atreq retries we will perform. 2373 */ 2374 void 2375 hci1394_ohci_atreq_retries_get(hci1394_ohci_handle_t ohci_hdl, 2376 uint_t *atreq_retries) 2377 { 2378 uint32_t reg; 2379 2380 ASSERT(ohci_hdl != NULL); 2381 ASSERT(atreq_retries != NULL); 2382 TNF_PROBE_0_DEBUG(hci1394_ohci_atreq_retries_get_enter, 2383 HCI1394_TNF_HAL_STACK, ""); 2384 reg = ddi_get32(ohci_hdl->ohci_reg_handle, 2385 &ohci_hdl->ohci_regs->at_retries); 2386 *atreq_retries = reg & OHCI_RET_MAX_ATREQ_MASK; 2387 TNF_PROBE_0_DEBUG(hci1394_ohci_atreq_retries_get_exit, 2388 HCI1394_TNF_HAL_STACK, ""); 2389 } 2390 2391 2392 /* 2393 * hci1394_ohci_atreq_retries_get() 2394 * Set the number of atreq retries we will perform. 2395 */ 2396 void 2397 hci1394_ohci_atreq_retries_set(hci1394_ohci_handle_t ohci_hdl, 2398 uint_t atreq_retries) 2399 { 2400 uint32_t reg; 2401 2402 2403 ASSERT(ohci_hdl != NULL); 2404 TNF_PROBE_0_DEBUG(hci1394_ohci_atreq_retries_set_enter, 2405 HCI1394_TNF_HAL_STACK, ""); 2406 2407 mutex_enter(&ohci_hdl->ohci_mutex); 2408 reg = ddi_get32(ohci_hdl->ohci_reg_handle, 2409 &ohci_hdl->ohci_regs->at_retries); 2410 reg = reg & ~OHCI_RET_MAX_ATREQ_MASK; 2411 reg = reg | (atreq_retries & OHCI_RET_MAX_ATREQ_MASK); 2412 ddi_put32(ohci_hdl->ohci_reg_handle, 2413 &ohci_hdl->ohci_regs->at_retries, reg); 2414 mutex_exit(&ohci_hdl->ohci_mutex); 2415 2416 TNF_PROBE_0_DEBUG(hci1394_ohci_atreq_retries_set_exit, 2417 HCI1394_TNF_HAL_STACK, ""); 2418 } 2419 2420 2421 /* 2422 * hci1394_ohci_isr_cycle64seconds() 2423 * Interrupt handler for the cycle64seconds interrupt. 2424 */ 2425 void 2426 hci1394_ohci_isr_cycle64seconds(hci1394_ohci_handle_t ohci_hdl) 2427 { 2428 uint32_t cycle_time; 2429 2430 ASSERT(ohci_hdl != NULL); 2431 TNF_PROBE_0_DEBUG(hci1394_ohci_isr_cycle64seconds_enter, 2432 HCI1394_TNF_HAL_STACK, ""); 2433 2434 hci1394_ohci_intr_clear(ohci_hdl, OHCI_INTR_CYC_64_SECS); 2435 cycle_time = ddi_get32(ohci_hdl->ohci_reg_handle, 2436 &ohci_hdl->ohci_regs->isoch_cycle_timer); 2437 2438 /* 2439 * cycle64second interrupts when the MSBit in the cycle timer changes 2440 * state. We only care about rollover so we will increment only when 2441 * the MSBit is set to 0. 2442 */ 2443 if ((cycle_time & 0x80000000) == 0) { 2444 ohci_hdl->ohci_bustime_count++; 2445 } 2446 2447 TNF_PROBE_0_DEBUG(hci1394_ohci_isr_cycle64seconds_exit, 2448 HCI1394_TNF_HAL_STACK, ""); 2449 } 2450 2451 2452 /* 2453 * hci1394_ohci_isr_phy() 2454 * Interrupt handler for a PHY event 2455 */ 2456 void 2457 hci1394_ohci_isr_phy(hci1394_ohci_handle_t ohci_hdl) 2458 { 2459 uint_t phy_status; 2460 int status; 2461 2462 2463 ASSERT(ohci_hdl != NULL); 2464 TNF_PROBE_0_DEBUG(hci1394_ohci_isr_phy_enter, 2465 HCI1394_TNF_HAL_STACK, ""); 2466 2467 /* clear the interrupt */ 2468 hci1394_ohci_intr_clear(ohci_hdl, OHCI_INTR_PHY); 2469 2470 /* increment the statistics count */ 2471 ohci_hdl->ohci_drvinfo->di_stats.st_phy_isr++; 2472 2473 /* 2474 * If the PHY is a 1995 phy, just return since there are no status bits 2475 * to read. 2476 */ 2477 if (ohci_hdl->ohci_phy == H1394_PHY_1995) { 2478 TNF_PROBE_0(hci1394_ohci_phy_isr_1995, 2479 HCI1394_TNF_HAL_ERROR, ""); 2480 TNF_PROBE_0_DEBUG(hci1394_ohci_isr_phy_exit, 2481 HCI1394_TNF_HAL_STACK, ""); 2482 return; 2483 } 2484 2485 /* See why we got this interrupt */ 2486 status = hci1394_ohci_phy_read(ohci_hdl, 5, &phy_status); 2487 if (status != DDI_SUCCESS) { 2488 TNF_PROBE_0(hci1394_ohci_phy_read_failed, 2489 HCI1394_TNF_HAL_ERROR, ""); 2490 TNF_PROBE_0_DEBUG(hci1394_ohci_isr_phy_exit, 2491 HCI1394_TNF_HAL_STACK, ""); 2492 return; 2493 } 2494 2495 if (phy_status & OHCI_PHY_LOOP_ERR) { 2496 ohci_hdl->ohci_drvinfo->di_stats.st_phy_loop_err++; 2497 cmn_err(CE_NOTE, "hci1394(%d): ERROR - bus loop detected", 2498 ohci_hdl->ohci_drvinfo->di_instance); 2499 TNF_PROBE_0(hci1394_ohci_phy_isr_loop, HCI1394_TNF_HAL, ""); 2500 } 2501 if (phy_status & OHCI_PHY_PWRFAIL_ERR) { 2502 ohci_hdl->ohci_drvinfo->di_stats.st_phy_pwrfail_err++; 2503 TNF_PROBE_0(hci1394_ohci_phy_isr_pwr, HCI1394_TNF_HAL, ""); 2504 } 2505 if (phy_status & OHCI_PHY_TIMEOUT_ERR) { 2506 ohci_hdl->ohci_drvinfo->di_stats.st_phy_timeout_err++; 2507 TNF_PROBE_0(hci1394_ohci_phy_isr_tmout, HCI1394_TNF_HAL, ""); 2508 } 2509 if (phy_status & OHCI_PHY_PORTEVT_ERR) { 2510 ohci_hdl->ohci_drvinfo->di_stats.st_phy_portevt_err++; 2511 TNF_PROBE_0(hci1394_ohci_phy_isr_pevt, HCI1394_TNF_HAL, ""); 2512 } 2513 2514 /* clear any set status bits */ 2515 status = hci1394_ohci_phy_write(ohci_hdl, 5, phy_status); 2516 if (status != DDI_SUCCESS) { 2517 TNF_PROBE_0(hci1394_ohci_phy_write_failed, 2518 HCI1394_TNF_HAL_ERROR, ""); 2519 TNF_PROBE_0_DEBUG(hci1394_ohci_isr_phy_exit, 2520 HCI1394_TNF_HAL_STACK, ""); 2521 return; 2522 } 2523 2524 /* 2525 * Disable the PHY interrupt. We are getting stuck in this ISR in 2526 * certain PHY implementations so we will disable the interrupt until 2527 * we see a selfid complete. 2528 */ 2529 hci1394_ohci_intr_disable(ohci_hdl, OHCI_INTR_PHY); 2530 2531 TNF_PROBE_0_DEBUG(hci1394_ohci_isr_phy_exit, 2532 HCI1394_TNF_HAL_STACK, ""); 2533 } 2534 2535 2536 /* 2537 * hci1394_ohci_root_check 2538 * Returns status about if we are currently the root node on the 1394 bus. 2539 * returns B_TRUE if we are the root, B_FALSE if we are not the root. 2540 */ 2541 boolean_t 2542 hci1394_ohci_root_check(hci1394_ohci_handle_t ohci_hdl) 2543 { 2544 uint32_t reg; 2545 int status; 2546 2547 ASSERT(ohci_hdl != NULL); 2548 TNF_PROBE_0_DEBUG(hci1394_ohci_root_check_enter, HCI1394_TNF_HAL_STACK, 2549 ""); 2550 reg = ddi_get32(ohci_hdl->ohci_reg_handle, 2551 &ohci_hdl->ohci_regs->node_id); 2552 if ((reg & OHCI_REG_NODEID_ROOT) && (reg & OHCI_NDID_IDVALID)) { 2553 status = B_TRUE; 2554 } else { 2555 status = B_FALSE; 2556 } 2557 TNF_PROBE_0_DEBUG(hci1394_ohci_root_check_exit, HCI1394_TNF_HAL_STACK, 2558 ""); 2559 2560 return (status); 2561 } 2562 2563 2564 /* 2565 * hci1394_ohci_cmc_check() 2566 * Returns status about if we are cycle master capable. Returns 2567 * B_TRUE if we are the cycle master capable, B_FALSE if we are not the cycle 2568 * master capable. 2569 */ 2570 boolean_t 2571 hci1394_ohci_cmc_check(hci1394_ohci_handle_t ohci_hdl) 2572 { 2573 uint32_t reg; 2574 int status; 2575 2576 ASSERT(ohci_hdl != NULL); 2577 TNF_PROBE_0_DEBUG(hci1394_ohci_cmc_check_enter, HCI1394_TNF_HAL_STACK, 2578 ""); 2579 reg = ddi_get32(ohci_hdl->ohci_reg_handle, 2580 &ohci_hdl->ohci_regs->bus_options); 2581 if (reg & OHCI_REG_BUSOPTIONS_CMC) { 2582 status = B_TRUE; 2583 } else { 2584 status = B_FALSE; 2585 } 2586 TNF_PROBE_0_DEBUG(hci1394_ohci_cmc_check_exit, HCI1394_TNF_HAL_STACK, 2587 ""); 2588 2589 return (status); 2590 } 2591 2592 2593 /* 2594 * hci1394_ohci_cycle_master_enable() 2595 * Enables us to be cycle master. If we are root, we will start generating 2596 * cycle start packets. 2597 */ 2598 void 2599 hci1394_ohci_cycle_master_enable(hci1394_ohci_handle_t ohci_hdl) 2600 { 2601 ASSERT(ohci_hdl != NULL); 2602 TNF_PROBE_0_DEBUG(hci1394_ohci_cycle_master_enable_enter, 2603 HCI1394_TNF_HAL_STACK, ""); 2604 2605 /* First make sure that cycleTooLong is clear */ 2606 ddi_put32(ohci_hdl->ohci_reg_handle, 2607 &ohci_hdl->ohci_regs->intr_event_clr, OHCI_INTR_CYC_TOO_LONG); 2608 2609 /* Enable Cycle Master */ 2610 ddi_put32(ohci_hdl->ohci_reg_handle, 2611 &ohci_hdl->ohci_regs->link_ctrl_set, OHCI_LC_CYC_MAST); 2612 2613 TNF_PROBE_0_DEBUG(hci1394_ohci_cycle_master_enable_exit, 2614 HCI1394_TNF_HAL_STACK, ""); 2615 } 2616 2617 2618 /* 2619 * hci1394_ohci_cycle_master_disable() 2620 * Disabled us from being cycle master. If we are root, we will stop 2621 * generating cycle start packets. 2622 */ 2623 void 2624 hci1394_ohci_cycle_master_disable(hci1394_ohci_handle_t ohci_hdl) 2625 { 2626 ASSERT(ohci_hdl != NULL); 2627 TNF_PROBE_0_DEBUG(hci1394_ohci_cycle_master_disable_enter, 2628 HCI1394_TNF_HAL_STACK, ""); 2629 2630 /* disable cycle master */ 2631 ddi_put32(ohci_hdl->ohci_reg_handle, 2632 &ohci_hdl->ohci_regs->link_ctrl_clr, OHCI_LC_CYC_MAST); 2633 2634 TNF_PROBE_0_DEBUG(hci1394_ohci_cycle_master_disable_exit, 2635 HCI1394_TNF_HAL_STACK, ""); 2636 } 2637 2638 2639 /* 2640 * hci1394_ohci_resume() 2641 * Re-initialize the openHCI HW during a resume. (after a power suspend) 2642 */ 2643 int 2644 hci1394_ohci_resume(hci1394_ohci_handle_t ohci_hdl) 2645 { 2646 uint32_t quadlet; 2647 int status; 2648 2649 2650 ASSERT(ohci_hdl != NULL); 2651 TNF_PROBE_0_DEBUG(hci1394_ohci_resume_enter, 2652 HCI1394_TNF_HAL_STACK, ""); 2653 2654 /* Re-initialize the OpenHCI chip */ 2655 status = hci1394_ohci_chip_init(ohci_hdl); 2656 if (status != DDI_SUCCESS) { 2657 TNF_PROBE_0(hci1394_ohci_chip_init_fail, HCI1394_TNF_HAL_ERROR, 2658 ""); 2659 TNF_PROBE_0_DEBUG(hci1394_ohci_resume_exit, 2660 HCI1394_TNF_HAL_STACK, ""); 2661 return (DDI_FAILURE); 2662 } 2663 2664 /* Re-initialize the PHY */ 2665 status = hci1394_ohci_phy_resume(ohci_hdl); 2666 if (status != DDI_SUCCESS) { 2667 TNF_PROBE_0(hci1394_ohci_phy_resume_fail, 2668 HCI1394_TNF_HAL_ERROR, ""); 2669 TNF_PROBE_0_DEBUG(hci1394_ohci_resume_exit, 2670 HCI1394_TNF_HAL_STACK, ""); 2671 return (DDI_FAILURE); 2672 } 2673 2674 /* Re-initialize any 1394A features we are using */ 2675 status = hci1394_ohci_1394a_resume(ohci_hdl); 2676 if (status != DDI_SUCCESS) { 2677 TNF_PROBE_0(hci1394_ohci_1394a_resume_fail, 2678 HCI1394_TNF_HAL_ERROR, ""); 2679 TNF_PROBE_0_DEBUG(hci1394_ohci_resume_exit, 2680 HCI1394_TNF_HAL_STACK, ""); 2681 return (DDI_FAILURE); 2682 } 2683 2684 /* Tell OpenHCI where the Config ROM buffer is */ 2685 ddi_put32(ohci_hdl->ohci_reg_handle, 2686 &ohci_hdl->ohci_regs->config_rom_maplo, 2687 (uint32_t)ohci_hdl->ohci_cfgrom.bi_cookie.dmac_address); 2688 2689 /* Tell OpenHCI where the SelfId buffer is */ 2690 ddi_put32(ohci_hdl->ohci_reg_handle, 2691 &ohci_hdl->ohci_regs->self_id_buflo, 2692 (uint32_t)ohci_hdl->ohci_selfid.bi_cookie.dmac_address); 2693 2694 /* Enable selfid DMA engine */ 2695 hci1394_ohci_selfid_enable(ohci_hdl); 2696 2697 /* 2698 * re-setup OHCI bus options and config rom hdr registers. We need to 2699 * read from the config rom using ddi_rep_get8 since it is stored as 2700 * a byte stream. We need to swap he config rom header and bus options 2701 * on an X86 machine since the data is a byte stream and the OHCI 2702 * registers expect a big endian 32-bit number. 2703 */ 2704 ddi_rep_get8(ohci_hdl->ohci_cfgrom.bi_handle, (uint8_t *)&quadlet, 2705 &((uint8_t *)ohci_hdl->ohci_cfgrom.bi_kaddr)[8], 4, 2706 DDI_DEV_AUTOINCR); 2707 ddi_put32(ohci_hdl->ohci_reg_handle, 2708 &ohci_hdl->ohci_regs->bus_options, OHCI_SWAP32(quadlet)); 2709 ddi_rep_get8(ohci_hdl->ohci_cfgrom.bi_handle, (uint8_t *)&quadlet, 2710 &((uint8_t *)ohci_hdl->ohci_cfgrom.bi_kaddr)[0], 4, 2711 DDI_DEV_AUTOINCR); 2712 ddi_put32(ohci_hdl->ohci_reg_handle, 2713 &ohci_hdl->ohci_regs->config_rom_hdr, OHCI_SWAP32(quadlet)); 2714 2715 TNF_PROBE_0_DEBUG(hci1394_ohci_resume_exit, 2716 HCI1394_TNF_HAL_STACK, ""); 2717 return (DDI_SUCCESS); 2718 } 2719 2720 2721 /* 2722 * hci1394_ohci_selfid_init() 2723 * Initialize the selfid buffer 2724 */ 2725 static int 2726 hci1394_ohci_selfid_init(hci1394_ohci_handle_t ohci_hdl) 2727 { 2728 hci1394_buf_parms_t parms; 2729 int status; 2730 2731 2732 ASSERT(ohci_hdl != NULL); 2733 TNF_PROBE_0_DEBUG(hci1394_init_selfid_enter, HCI1394_TNF_HAL_STACK, ""); 2734 2735 /* 2736 * Setup for 2K buffer, aligned on a 2Kbyte address boundary. Make sure 2737 * that the buffer is not broken up into multiple cookies. OpenHCI can 2738 * only handle one address for the selfid buffer location. 2739 */ 2740 parms.bp_length = 2048; 2741 parms.bp_max_cookies = 1; 2742 parms.bp_alignment = 2048; 2743 status = hci1394_buf_alloc(ohci_hdl->ohci_drvinfo, &parms, 2744 &ohci_hdl->ohci_selfid, &ohci_hdl->ohci_selfid_handle); 2745 if (status != DDI_SUCCESS) { 2746 TNF_PROBE_0(hci1394_buf_alloc_fail, HCI1394_TNF_HAL_ERROR, ""); 2747 TNF_PROBE_0_DEBUG(hci1394_init_selfid_exit, 2748 HCI1394_TNF_HAL_STACK, ""); 2749 return (DDI_FAILURE); 2750 } 2751 2752 /* Tell OpenHCI where the buffer is */ 2753 ddi_put32(ohci_hdl->ohci_reg_handle, 2754 &ohci_hdl->ohci_regs->self_id_buflo, 2755 (uint32_t)ohci_hdl->ohci_selfid.bi_cookie.dmac_address); 2756 2757 /* Enable selfid DMA engine */ 2758 hci1394_ohci_selfid_enable(ohci_hdl); 2759 2760 TNF_PROBE_0_DEBUG(hci1394_init_selfid_exit, HCI1394_TNF_HAL_STACK, ""); 2761 2762 return (DDI_SUCCESS); 2763 } 2764 2765 2766 /* 2767 * hci1394_ohci_selfid_enable() 2768 * Allow selfid packets to be placed into the selfid buffer. This should be 2769 * called after the selfid buffer address has been setup in the HW. 2770 */ 2771 void 2772 hci1394_ohci_selfid_enable(hci1394_ohci_handle_t ohci_hdl) 2773 { 2774 ASSERT(ohci_hdl != NULL); 2775 TNF_PROBE_0_DEBUG(hci1394_ohci_selfid_enable_enter, 2776 HCI1394_TNF_HAL_STACK, ""); 2777 2778 /* 2779 * Allow selfid packets to be received. This should be called during 2780 * driver attach after the selfid buffer address has been initialized. 2781 * 2782 * Link Control Register 2783 * rscSelfId = 1 <= bit 9 2784 */ 2785 ddi_put32(ohci_hdl->ohci_reg_handle, 2786 &ohci_hdl->ohci_regs->link_ctrl_set, OHCI_LC_RCV_SELF); 2787 2788 TNF_PROBE_0_DEBUG(hci1394_ohci_selfid_enable_exit, 2789 HCI1394_TNF_HAL_STACK, ""); 2790 } 2791 2792 2793 /* 2794 * hci1394_ohci_selfid_read() 2795 * Read a word out of the selfid buffer. 2796 */ 2797 void 2798 hci1394_ohci_selfid_read(hci1394_ohci_handle_t ohci_hdl, uint_t offset, 2799 uint32_t *data) 2800 { 2801 ASSERT(ohci_hdl != NULL); 2802 ASSERT(data != NULL); 2803 TNF_PROBE_0_DEBUG(hci1394_ohci_selfid_read_enter, 2804 HCI1394_TNF_HAL_STACK, ""); 2805 *data = ddi_get32(ohci_hdl->ohci_selfid.bi_handle, 2806 &((uint32_t *)ohci_hdl->ohci_selfid.bi_kaddr)[offset]); 2807 TNF_PROBE_0_DEBUG(hci1394_ohci_selfid_read_exit, 2808 HCI1394_TNF_HAL_STACK, ""); 2809 } 2810 2811 2812 /* 2813 * hci1394_ohci_selfid_info() 2814 * Return the current bus generation, the number of bytes currently in the 2815 * selfid buffer, and if we have seen any selfid errors. 2816 */ 2817 void 2818 hci1394_ohci_selfid_info(hci1394_ohci_handle_t ohci_hdl, uint_t *busgen, 2819 uint_t *size, boolean_t *error) 2820 { 2821 uint32_t reg; 2822 2823 2824 ASSERT(ohci_hdl != NULL); 2825 ASSERT(busgen != NULL); 2826 ASSERT(size != NULL); 2827 ASSERT(error != NULL); 2828 TNF_PROBE_0_DEBUG(hci1394_ohci_selfid_info_enter, 2829 HCI1394_TNF_HAL_STACK, ""); 2830 2831 reg = ddi_get32(ohci_hdl->ohci_reg_handle, 2832 &ohci_hdl->ohci_regs->self_id_count); 2833 *busgen = (reg & OHCI_SLFC_GEN_MASK) >> OHCI_SLFC_GEN_SHIFT; 2834 *size = reg & OHCI_SLFC_NUM_QUADS_MASK; 2835 if ((reg & OHCI_SLFC_ERROR) == 0) { 2836 *error = B_FALSE; 2837 } else { 2838 *error = B_TRUE; 2839 } 2840 2841 TNF_PROBE_0_DEBUG(hci1394_ohci_selfid_info_exit, 2842 HCI1394_TNF_HAL_STACK, ""); 2843 } 2844 2845 2846 /* 2847 * hci1394_ohci_selfid_buf_current() 2848 * Test if the selfid buffer is current. Return B_TRUE if it is current and 2849 * B_FALSE if it is not current. 2850 */ 2851 boolean_t 2852 hci1394_ohci_selfid_buf_current(hci1394_ohci_handle_t ohci_hdl) 2853 { 2854 uint32_t reg; 2855 int status; 2856 2857 ASSERT(ohci_hdl != NULL); 2858 TNF_PROBE_0_DEBUG(hci1394_ohci_selfid_buf_current_enter, 2859 HCI1394_TNF_HAL_STACK, ""); 2860 2861 /* 2862 * if the generation stored in the selfid buffer is not equal to the 2863 * generation we have previously stored, the selfid buffer is not 2864 * current. (It maybe older or it maybe newer) 2865 */ 2866 reg = ddi_get32(ohci_hdl->ohci_selfid.bi_handle, 2867 &((uint32_t *)ohci_hdl->ohci_selfid.bi_kaddr)[0]); 2868 if (ohci_hdl->ohci_drvinfo->di_gencnt != ((reg & OHCI_SLFC_GEN_MASK) >> 2869 OHCI_SLFC_GEN_SHIFT)) { 2870 status = B_FALSE; 2871 } else { 2872 status = B_TRUE; 2873 } 2874 2875 TNF_PROBE_0_DEBUG(hci1394_ohci_selfid_buf_current_exit, 2876 HCI1394_TNF_HAL_STACK, ""); 2877 2878 return (status); 2879 } 2880 2881 2882 /* 2883 * hci1394_ohci_selfid_sync() 2884 * Perform a ddi_dma_sync on the selfid buffer 2885 */ 2886 void 2887 hci1394_ohci_selfid_sync(hci1394_ohci_handle_t ohci_hdl) 2888 { 2889 ASSERT(ohci_hdl != NULL); 2890 TNF_PROBE_0_DEBUG(hci1394_ohci_selfid_sync_enter, 2891 HCI1394_TNF_HAL_STACK, ""); 2892 (void) ddi_dma_sync(ohci_hdl->ohci_selfid.bi_dma_handle, 0, 2893 ohci_hdl->ohci_selfid.bi_length, DDI_DMA_SYNC_FORKERNEL); 2894 TNF_PROBE_0_DEBUG(hci1394_ohci_selfid_sync_exit, HCI1394_TNF_HAL_STACK, 2895 ""); 2896 } 2897 2898 2899 /* 2900 * hci1394_ohci_cfgrom_init() 2901 * Initialize the configuration ROM buffer 2902 */ 2903 static int 2904 hci1394_ohci_cfgrom_init(hci1394_ohci_handle_t ohci_hdl) 2905 { 2906 hci1394_buf_parms_t parms; 2907 int status; 2908 2909 2910 ASSERT(ohci_hdl != NULL); 2911 TNF_PROBE_0_DEBUG(hci1394_ohci_cfgrom_init_enter, 2912 HCI1394_TNF_HAL_STACK, ""); 2913 2914 /* 2915 * Setup for 1K buffer, aligned at 1K address boundary, and allow no 2916 * less than 4 byte data transfers. Create the Buffer. Make sure that 2917 * the buffer is not broken up into multiple cookies. OpenHCI can only 2918 * handle one address for the config ROM buffer location. 2919 */ 2920 parms.bp_length = 1024; 2921 parms.bp_max_cookies = 1; 2922 parms.bp_alignment = 1024; 2923 status = hci1394_buf_alloc(ohci_hdl->ohci_drvinfo, &parms, 2924 &ohci_hdl->ohci_cfgrom, &ohci_hdl->ohci_cfgrom_handle); 2925 if (status != DDI_SUCCESS) { 2926 TNF_PROBE_0(hci1394_buf_alloc_fail, HCI1394_TNF_HAL_ERROR, ""); 2927 TNF_PROBE_0_DEBUG(hci1394_ohci_cfgrom_init_exit, 2928 HCI1394_TNF_HAL_STACK, ""); 2929 return (DDI_FAILURE); 2930 } 2931 2932 /* Tell OpenHCI where the buffer is */ 2933 ddi_put32(ohci_hdl->ohci_reg_handle, 2934 &ohci_hdl->ohci_regs->config_rom_maplo, 2935 (uint32_t)ohci_hdl->ohci_cfgrom.bi_cookie.dmac_address); 2936 2937 TNF_PROBE_0_DEBUG(hci1394_ohci_cfgrom_init_exit, HCI1394_TNF_HAL_STACK, 2938 ""); 2939 2940 return (DDI_SUCCESS); 2941 } 2942 2943 2944 /* 2945 * hci1394_ohci_bus_capabilities() 2946 * Return our current bus capabilities 2947 */ 2948 void 2949 hci1394_ohci_bus_capabilities(hci1394_ohci_handle_t ohci_hdl, 2950 uint32_t *bus_capabilities) 2951 { 2952 ASSERT(ohci_hdl != NULL); 2953 TNF_PROBE_0_DEBUG(hci1394_ohci_bus_capabilities_enter, 2954 HCI1394_TNF_HAL_STACK, ""); 2955 /* 2956 * read in the bus options register. Set bits saying that we are isoch 2957 * resource manager capable, Cycle master capable, and Isoch capable 2958 */ 2959 *bus_capabilities = ddi_get32(ohci_hdl->ohci_reg_handle, 2960 &ohci_hdl->ohci_regs->bus_options) | (OHCI_BOPT_IRMC | 2961 OHCI_BOPT_CMC | OHCI_BOPT_ISC); 2962 TNF_PROBE_0_DEBUG(hci1394_ohci_bus_capabilities_exit, 2963 HCI1394_TNF_HAL_STACK, ""); 2964 } 2965 2966 2967 /* 2968 * hci1394_ohci_at_active() 2969 * Returns status one if either of the AT engines are active. If either AT 2970 * engine is active, we return B_TRUE. If both AT engines are not active, we 2971 * return B_FALSE. 2972 */ 2973 boolean_t 2974 hci1394_ohci_at_active(hci1394_ohci_handle_t ohci_hdl) 2975 { 2976 uint32_t reg; 2977 2978 2979 ASSERT(ohci_hdl != NULL); 2980 TNF_PROBE_0_DEBUG(hci1394_ohci_at_active_enter, 2981 HCI1394_TNF_HAL_STACK, ""); 2982 2983 /* see if atreq active bit set */ 2984 reg = ddi_get32(ohci_hdl->ohci_reg_handle, 2985 &ohci_hdl->ohci_regs->at_req.ctxt_ctrl_set); 2986 if (reg & OHCI_CC_ACTIVE_MASK) { 2987 /* atreq engine is still active */ 2988 TNF_PROBE_0(hci1394_ohci_atreq_active_fail, 2989 HCI1394_TNF_HAL_ERROR, ""); 2990 TNF_PROBE_0_DEBUG(hci1394_ohci_at_active_exit, 2991 HCI1394_TNF_HAL_STACK, ""); 2992 return (B_TRUE); 2993 } 2994 2995 /* see if atresp active bit set */ 2996 reg = ddi_get32(ohci_hdl->ohci_reg_handle, 2997 &ohci_hdl->ohci_regs->at_resp.ctxt_ctrl_set); 2998 if (reg & OHCI_CC_ACTIVE_MASK) { 2999 /* atresp engine is still active */ 3000 TNF_PROBE_0(hci1394_ohci_atresp_active_fail, 3001 HCI1394_TNF_HAL_ERROR, ""); 3002 TNF_PROBE_0_DEBUG(hci1394_ohci_at_active_exit, 3003 HCI1394_TNF_HAL_STACK, ""); 3004 return (B_TRUE); 3005 } 3006 3007 TNF_PROBE_0_DEBUG(hci1394_ohci_at_active_exit, 3008 HCI1394_TNF_HAL_STACK, ""); 3009 3010 /* both atreq and atresp active bits are cleared */ 3011 return (B_FALSE); 3012 } 3013 3014 3015 /* 3016 * hci1394_ohci_atreq_start() 3017 * Start the atreq dma engine. Set the address of the first descriptor 3018 * to read in equal to cmdptr. 3019 */ 3020 void 3021 hci1394_ohci_atreq_start(hci1394_ohci_handle_t ohci_hdl, uint32_t cmdptr) 3022 { 3023 ASSERT(ohci_hdl != NULL); 3024 TNF_PROBE_0_DEBUG(hci1394_ohci_atreq_start_enter, 3025 HCI1394_TNF_HAL_STACK, ""); 3026 3027 ddi_put32(ohci_hdl->ohci_reg_handle, 3028 &ohci_hdl->ohci_regs->at_req.cmd_ptrlo, cmdptr); 3029 ddi_put32(ohci_hdl->ohci_reg_handle, 3030 &ohci_hdl->ohci_regs->at_req.ctxt_ctrl_set, OHCI_CC_RUN_MASK); 3031 3032 TNF_PROBE_0_DEBUG(hci1394_ohci_atreq_start_exit, 3033 HCI1394_TNF_HAL_STACK, ""); 3034 } 3035 3036 3037 /* 3038 * hci1394_ohci_atreq_wake() 3039 * Wake up the atreq dma engine. This should be called when a new descriptor 3040 * is added to the Q and the dma engine has already be started. It it OK to 3041 * call this when the DMA engine is active. 3042 */ 3043 void 3044 hci1394_ohci_atreq_wake(hci1394_ohci_handle_t ohci_hdl) 3045 { 3046 ASSERT(ohci_hdl != NULL); 3047 TNF_PROBE_0_DEBUG(hci1394_ohci_atreq_wake_enter, 3048 HCI1394_TNF_HAL_STACK, ""); 3049 3050 ddi_put32(ohci_hdl->ohci_reg_handle, 3051 &ohci_hdl->ohci_regs->at_req.ctxt_ctrl_set, OHCI_CC_WAKE_MASK); 3052 3053 TNF_PROBE_0_DEBUG(hci1394_ohci_atreq_wake_exit, 3054 HCI1394_TNF_HAL_STACK, ""); 3055 } 3056 3057 3058 /* 3059 * hci1394_ohci_atreq_stop() 3060 * Stop the atreq dma engine. No further descriptors will be read until 3061 * it dma engine is started again. 3062 */ 3063 void 3064 hci1394_ohci_atreq_stop(hci1394_ohci_handle_t ohci_hdl) 3065 { 3066 ASSERT(ohci_hdl != NULL); 3067 TNF_PROBE_0_DEBUG(hci1394_ohci_atreq_stop_enter, 3068 HCI1394_TNF_HAL_STACK, ""); 3069 3070 ddi_put32(ohci_hdl->ohci_reg_handle, 3071 &ohci_hdl->ohci_regs->at_req.ctxt_ctrl_clr, OHCI_CC_RUN_MASK); 3072 3073 TNF_PROBE_0_DEBUG(hci1394_ohci_atreq_stop_exit, 3074 HCI1394_TNF_HAL_STACK, ""); 3075 } 3076 3077 3078 /* 3079 * hci1394_ohci_arresp_start() 3080 * Start the arresp dma engine. Set the address of the first descriptor 3081 * to read in equal to cmdptr. 3082 */ 3083 void 3084 hci1394_ohci_arresp_start(hci1394_ohci_handle_t ohci_hdl, uint32_t cmdptr) 3085 { 3086 ASSERT(ohci_hdl != NULL); 3087 TNF_PROBE_0_DEBUG(hci1394_ohci_arresp_start_enter, 3088 HCI1394_TNF_HAL_STACK, ""); 3089 3090 ddi_put32(ohci_hdl->ohci_reg_handle, 3091 &ohci_hdl->ohci_regs->ar_resp.cmd_ptrlo, cmdptr); 3092 ddi_put32(ohci_hdl->ohci_reg_handle, 3093 &ohci_hdl->ohci_regs->ar_resp.ctxt_ctrl_set, OHCI_CC_RUN_MASK); 3094 3095 TNF_PROBE_0_DEBUG(hci1394_ohci_arresp_start_exit, 3096 HCI1394_TNF_HAL_STACK, ""); 3097 } 3098 3099 3100 /* 3101 * hci1394_ohci_arresp_wake() 3102 * Wake up the arresp dma engine. This should be called when a new 3103 * descriptor is added to the Q and the dma engine has already be started. 3104 * It is OK to call this when the DMA engine is active. 3105 */ 3106 void 3107 hci1394_ohci_arresp_wake(hci1394_ohci_handle_t ohci_hdl) 3108 { 3109 ASSERT(ohci_hdl != NULL); 3110 TNF_PROBE_0_DEBUG(hci1394_ohci_arresp_wake_enter, 3111 HCI1394_TNF_HAL_STACK, ""); 3112 3113 ddi_put32(ohci_hdl->ohci_reg_handle, 3114 &ohci_hdl->ohci_regs->ar_resp.ctxt_ctrl_set, OHCI_CC_WAKE_MASK); 3115 3116 TNF_PROBE_0_DEBUG(hci1394_ohci_arresp_wake_exit, 3117 HCI1394_TNF_HAL_STACK, ""); 3118 } 3119 3120 3121 /* 3122 * hci1394_ohci_atreq_stop() 3123 * Stop the arresp dma engine. No further data will be received after any 3124 * current packets being received have finished. 3125 */ 3126 void 3127 hci1394_ohci_arresp_stop(hci1394_ohci_handle_t ohci_hdl) 3128 { 3129 ASSERT(ohci_hdl != NULL); 3130 TNF_PROBE_0_DEBUG(hci1394_ohci_arresp_stop_enter, 3131 HCI1394_TNF_HAL_STACK, ""); 3132 3133 ddi_put32(ohci_hdl->ohci_reg_handle, 3134 &ohci_hdl->ohci_regs->ar_resp.ctxt_ctrl_clr, OHCI_CC_RUN_MASK); 3135 3136 TNF_PROBE_0_DEBUG(hci1394_ohci_arresp_stop_exit, 3137 HCI1394_TNF_HAL_STACK, ""); 3138 } 3139 3140 3141 /* 3142 * hci1394_ohci_arreq_start() 3143 * Start the arreq dma engine. Set the address of the first descriptor 3144 * to read in equal to cmdptr. 3145 */ 3146 void 3147 hci1394_ohci_arreq_start(hci1394_ohci_handle_t ohci_hdl, uint32_t cmdptr) 3148 { 3149 ASSERT(ohci_hdl != NULL); 3150 TNF_PROBE_0_DEBUG(hci1394_ohci_arreq_start_enter, 3151 HCI1394_TNF_HAL_STACK, ""); 3152 3153 ddi_put32(ohci_hdl->ohci_reg_handle, 3154 &ohci_hdl->ohci_regs->ar_req.cmd_ptrlo, cmdptr); 3155 ddi_put32(ohci_hdl->ohci_reg_handle, 3156 &ohci_hdl->ohci_regs->ar_req.ctxt_ctrl_set, OHCI_CC_RUN_MASK); 3157 3158 TNF_PROBE_0_DEBUG(hci1394_ohci_arreq_start_exit, 3159 HCI1394_TNF_HAL_STACK, ""); 3160 } 3161 3162 3163 /* 3164 * hci1394_ohci_arreq_wake() 3165 * Wake up the arreq dma engine. This should be called when a new descriptor 3166 * is added to the Q and the dma engine has already be started. It is OK to 3167 * call this when the DMA engine is active. 3168 */ 3169 void 3170 hci1394_ohci_arreq_wake(hci1394_ohci_handle_t ohci_hdl) 3171 { 3172 ASSERT(ohci_hdl != NULL); 3173 TNF_PROBE_0_DEBUG(hci1394_ohci_arreq_wake_enter, 3174 HCI1394_TNF_HAL_STACK, ""); 3175 3176 ddi_put32(ohci_hdl->ohci_reg_handle, 3177 &ohci_hdl->ohci_regs->ar_req.ctxt_ctrl_set, OHCI_CC_WAKE_MASK); 3178 3179 TNF_PROBE_0_DEBUG(hci1394_ohci_arreq_wake_exit, 3180 HCI1394_TNF_HAL_STACK, ""); 3181 } 3182 3183 3184 /* 3185 * hci1394_ohci_arreq_stop() 3186 * Stop the arreq dma engine. No further data will be received after any 3187 * current packets being received have finished. 3188 */ 3189 void 3190 hci1394_ohci_arreq_stop(hci1394_ohci_handle_t ohci_hdl) 3191 { 3192 ASSERT(ohci_hdl != NULL); 3193 TNF_PROBE_0_DEBUG(hci1394_ohci_arreq_stop_enter, 3194 HCI1394_TNF_HAL_STACK, ""); 3195 3196 ddi_put32(ohci_hdl->ohci_reg_handle, 3197 &ohci_hdl->ohci_regs->ar_req.ctxt_ctrl_clr, OHCI_CC_RUN_MASK); 3198 3199 TNF_PROBE_0_DEBUG(hci1394_ohci_arreq_stop_exit, 3200 HCI1394_TNF_HAL_STACK, ""); 3201 } 3202 3203 3204 /* 3205 * hci1394_ohci_atresp_start() 3206 * Start the atresp dma engine. Set the address of the first descriptor 3207 * to read in equal to cmdptr. 3208 */ 3209 void 3210 hci1394_ohci_atresp_start(hci1394_ohci_handle_t ohci_hdl, uint32_t cmdptr) 3211 { 3212 ASSERT(ohci_hdl != NULL); 3213 TNF_PROBE_0_DEBUG(hci1394_ohci_atresp_start_enter, 3214 HCI1394_TNF_HAL_STACK, ""); 3215 3216 ddi_put32(ohci_hdl->ohci_reg_handle, 3217 &ohci_hdl->ohci_regs->at_resp.cmd_ptrlo, cmdptr); 3218 ddi_put32(ohci_hdl->ohci_reg_handle, 3219 &ohci_hdl->ohci_regs->at_resp.ctxt_ctrl_set, OHCI_CC_RUN_MASK); 3220 3221 TNF_PROBE_0_DEBUG(hci1394_ohci_atresp_start_exit, 3222 HCI1394_TNF_HAL_STACK, ""); 3223 } 3224 3225 3226 /* 3227 * hci1394_ohci_atresp_wake() 3228 * Wake up the atresp dma engine. This should be called when a new 3229 * descriptor is added to the Q and the dma engine has already be started. 3230 * It is OK to call this when the DMA engine is active. 3231 */ 3232 void 3233 hci1394_ohci_atresp_wake(hci1394_ohci_handle_t ohci_hdl) 3234 { 3235 ASSERT(ohci_hdl != NULL); 3236 TNF_PROBE_0_DEBUG(hci1394_ohci_atresp_wake_enter, 3237 HCI1394_TNF_HAL_STACK, ""); 3238 3239 ddi_put32(ohci_hdl->ohci_reg_handle, 3240 &ohci_hdl->ohci_regs->at_resp.ctxt_ctrl_set, OHCI_CC_WAKE_MASK); 3241 3242 TNF_PROBE_0_DEBUG(hci1394_ohci_atresp_wake_exit, 3243 HCI1394_TNF_HAL_STACK, ""); 3244 } 3245 3246 3247 /* 3248 * hci1394_ohci_atresp_stop() 3249 * Stop the atresp dma engine. No further descriptors will be read until 3250 * it dma engine is started again. 3251 */ 3252 void 3253 hci1394_ohci_atresp_stop(hci1394_ohci_handle_t ohci_hdl) 3254 { 3255 ASSERT(ohci_hdl != NULL); 3256 TNF_PROBE_0_DEBUG(hci1394_ohci_atresp_stop_enter, 3257 HCI1394_TNF_HAL_STACK, ""); 3258 3259 ddi_put32(ohci_hdl->ohci_reg_handle, 3260 &ohci_hdl->ohci_regs->at_resp.ctxt_ctrl_clr, OHCI_CC_RUN_MASK); 3261 3262 TNF_PROBE_0_DEBUG(hci1394_ohci_atresp_stop_exit, 3263 HCI1394_TNF_HAL_STACK, ""); 3264 } 3265 3266 3267 /* 3268 * hci1394_ohci_1394a_init() 3269 * Initialize any 1394a features that we are using. 3270 */ 3271 /* ARGSUSED */ 3272 int 3273 hci1394_ohci_1394a_init(hci1394_ohci_handle_t ohci_hdl) 3274 { 3275 uint32_t reg; 3276 int status; 3277 3278 ASSERT(ohci_hdl != NULL); 3279 TNF_PROBE_0_DEBUG(hci1394_ohci_1394a_init_enter, HCI1394_TNF_HAL_STACK, 3280 ""); 3281 3282 reg = ddi_get32(ohci_hdl->ohci_reg_handle, 3283 &ohci_hdl->ohci_regs->hc_ctrl_set); 3284 if (reg & OHCI_HC_PROG_PHY_ENBL) { 3285 ddi_put32(ohci_hdl->ohci_reg_handle, 3286 &ohci_hdl->ohci_regs->hc_ctrl_set, OHCI_HC_APHY_ENBL); 3287 status = hci1394_ohci_phy_set(ohci_hdl, 5, 3288 (OHCI_PHY_ENBL_ACCEL | OHCI_PHY_ENBL_MULTI)); 3289 if (status != DDI_SUCCESS) { 3290 TNF_PROBE_0(hci1394_ohci_1394a_init_phy_fail, 3291 HCI1394_TNF_HAL_STACK, ""); 3292 TNF_PROBE_0_DEBUG(hci1394_ohci_1394a_init_exit, 3293 HCI1394_TNF_HAL_STACK, ""); 3294 return (DDI_FAILURE); 3295 } 3296 } 3297 3298 TNF_PROBE_0_DEBUG(hci1394_ohci_1394a_init_exit, HCI1394_TNF_HAL_STACK, 3299 ""); 3300 return (DDI_SUCCESS); 3301 } 3302 3303 3304 /* 3305 * hci1394_ohci_1394a_init() 3306 * Re-initialize any 1394a features that we are using. 3307 */ 3308 /* ARGSUSED */ 3309 int 3310 hci1394_ohci_1394a_resume(hci1394_ohci_handle_t ohci_hdl) 3311 { 3312 uint32_t reg; 3313 int status; 3314 3315 ASSERT(ohci_hdl != NULL); 3316 TNF_PROBE_0_DEBUG(hci1394_ohci_1394a_resume_enter, 3317 HCI1394_TNF_HAL_STACK, ""); 3318 3319 reg = ddi_get32(ohci_hdl->ohci_reg_handle, 3320 &ohci_hdl->ohci_regs->hc_ctrl_set); 3321 if (reg & OHCI_HC_PROG_PHY_ENBL) { 3322 ddi_put32(ohci_hdl->ohci_reg_handle, 3323 &ohci_hdl->ohci_regs->hc_ctrl_set, OHCI_HC_APHY_ENBL); 3324 status = hci1394_ohci_phy_set(ohci_hdl, 5, 3325 (OHCI_PHY_ENBL_ACCEL | OHCI_PHY_ENBL_MULTI)); 3326 if (status != DDI_SUCCESS) { 3327 TNF_PROBE_0(hci1394_ohci_1394a_resume_phy_fail, 3328 HCI1394_TNF_HAL_STACK, ""); 3329 TNF_PROBE_0_DEBUG(hci1394_ohci_1394a_resume_exit, 3330 HCI1394_TNF_HAL_STACK, ""); 3331 return (DDI_FAILURE); 3332 } 3333 } 3334 3335 TNF_PROBE_0_DEBUG(hci1394_ohci_1394a_resume_exit, 3336 HCI1394_TNF_HAL_STACK, ""); 3337 return (DDI_SUCCESS); 3338 } 3339