1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 * Copyright (c) 2016 by Delphix. All rights reserved. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 /* 30 * hci1394_ohci.c 31 * Provides access routines to the OpenHCI HW. 32 */ 33 34 #include <sys/conf.h> 35 #include <sys/ddi.h> 36 #include <sys/modctl.h> 37 #include <sys/sunddi.h> 38 #include <sys/types.h> 39 #include <sys/mkdev.h> 40 #include <sys/kmem.h> 41 #include <sys/pci.h> 42 43 #include <sys/1394/adapters/hci1394.h> 44 #include <sys/1394/adapters/hci1394_extern.h> 45 46 47 /* 48 * Data swap macros used to swap config rom data that is going to be placed 49 * in OpenHCI registers. The config rom is treated like a byte stream. When 50 * the services layer calls into us to update the config rom, they pass us a 51 * byte stream of data. This works well except for the the fact that the 52 * hardware uses its internal registers for the first 5 quadlets. We have to 53 * copy the cfgrom header and bus options into their corresponding OpenHCI 54 * registers. On an x86 machine, this means we have to byte swap them first. 55 */ 56 #ifdef _LITTLE_ENDIAN 57 #define OHCI_SWAP32(DATA) (ddi_swap32(DATA)) 58 #else 59 #define OHCI_SWAP32(DATA) (DATA) 60 #endif 61 62 63 static int hci1394_ohci_selfid_init(hci1394_ohci_handle_t ohci_hdl); 64 static int hci1394_ohci_cfgrom_init(hci1394_ohci_handle_t ohci_hdl); 65 static int hci1394_ohci_chip_init(hci1394_ohci_handle_t ohci_hdl); 66 static int hci1394_ohci_phy_resume(hci1394_ohci_handle_t ohci_hdl); 67 static int hci1394_ohci_1394a_init(hci1394_ohci_handle_t ohci_hdl); 68 static int hci1394_ohci_1394a_resume(hci1394_ohci_handle_t ohci_hdl); 69 static int hci1394_ohci_phy_read_no_lock(hci1394_ohci_handle_t ohci_hdl, 70 uint_t address, uint_t *data); 71 static int hci1394_ohci_phy_write_no_lock(hci1394_ohci_handle_t ohci_hdl, 72 uint_t address, uint_t data); 73 74 75 /* 76 * hci1394_ohci_init() 77 * Initialize the OpenHCI hardware. 78 */ 79 int 80 hci1394_ohci_init(hci1394_state_t *soft_state, hci1394_drvinfo_t *drvinfo, 81 hci1394_ohci_handle_t *ohci_hdl) 82 { 83 int status; 84 uint32_t version; 85 hci1394_ohci_t *ohci; 86 #if defined(__x86) 87 uint16_t cmdreg; 88 #endif 89 90 91 ASSERT(ohci_hdl != NULL); 92 TNF_PROBE_0_DEBUG(hci1394_ohci_init_enter, HCI1394_TNF_HAL_STACK, ""); 93 94 /* alloc the space for ohci */ 95 ohci = kmem_alloc(sizeof (hci1394_ohci_t), KM_SLEEP); 96 *ohci_hdl = ohci; 97 98 /* 99 * Start with the cycle timer rollover interrupt disabled. When it is 100 * enabled, we will get an interrupt every 64 seconds, even if we have 101 * nothing plugged into the bus. This interrupt is used to keep track 102 * of the bus time. We will enable the interrupt when the bus manager 103 * writes to the bus_time CSR register (Currently there are not known 104 * implementations that write to the bus_time register) 105 */ 106 ohci->ohci_bustime_enabled = B_FALSE; 107 ohci->ohci_bustime_count = 0; 108 109 ohci->ohci_set_root_holdoff = B_FALSE; 110 ohci->ohci_set_gap_count = B_FALSE; 111 ohci->ohci_gap_count = 0; 112 113 mutex_init(&ohci->ohci_mutex, NULL, MUTEX_DRIVER, 114 drvinfo->di_iblock_cookie); 115 116 /* Map OpenHCI Registers */ 117 status = ddi_regs_map_setup(drvinfo->di_dip, OHCI_REG_SET, 118 (caddr_t *)&ohci->ohci_regs, 0, 0, &drvinfo->di_reg_attr, 119 &ohci->ohci_reg_handle); 120 if (status != DDI_SUCCESS) { 121 mutex_destroy(&ohci->ohci_mutex); 122 kmem_free(ohci, sizeof (hci1394_ohci_t)); 123 *ohci_hdl = NULL; 124 TNF_PROBE_0(ddi_regs_map_setup_fail, HCI1394_TNF_HAL_ERROR, 125 ""); 126 TNF_PROBE_0_DEBUG(hci1394_ohci_init_exit, HCI1394_TNF_HAL_STACK, 127 ""); 128 return (DDI_FAILURE); 129 } 130 131 ohci->soft_state = soft_state; 132 ohci->ohci_drvinfo = drvinfo; 133 134 /* 135 * make sure PCI Master and PCI Memory Access are enabled on x86 136 * platforms. This may not be the case if plug and play OS is 137 * set in the BIOS 138 */ 139 #if defined(__x86) 140 cmdreg = pci_config_get16(soft_state->pci_config, PCI_CONF_COMM); 141 if ((cmdreg & (PCI_COMM_MAE | PCI_COMM_ME)) != (PCI_COMM_MAE | 142 PCI_COMM_ME)) { 143 cmdreg |= PCI_COMM_MAE | PCI_COMM_ME; 144 pci_config_put16(soft_state->pci_config, PCI_CONF_COMM, cmdreg); 145 } 146 #endif 147 148 /* 149 * Initialize the openHCI chip. This is broken out because we need to 150 * do this when resuming too. 151 */ 152 status = hci1394_ohci_chip_init(ohci); 153 if (status != DDI_SUCCESS) { 154 ddi_regs_map_free(&ohci->ohci_reg_handle); 155 mutex_destroy(&ohci->ohci_mutex); 156 kmem_free(ohci, sizeof (hci1394_ohci_t)); 157 *ohci_hdl = NULL; 158 TNF_PROBE_0(hci1394_ohci_chip_init_fail, HCI1394_TNF_HAL_ERROR, 159 ""); 160 TNF_PROBE_0_DEBUG(hci1394_ohci_init_exit, 161 HCI1394_TNF_HAL_STACK, ""); 162 return (DDI_FAILURE); 163 } 164 165 /* Init the 1394 PHY */ 166 status = hci1394_ohci_phy_init(ohci); 167 if (status != DDI_SUCCESS) { 168 (void) hci1394_ohci_soft_reset(ohci); 169 ddi_regs_map_free(&ohci->ohci_reg_handle); 170 mutex_destroy(&ohci->ohci_mutex); 171 kmem_free(ohci, sizeof (hci1394_ohci_t)); 172 *ohci_hdl = NULL; 173 TNF_PROBE_0(hci1394_ohci_phy_init_fail, 174 HCI1394_TNF_HAL_ERROR, ""); 175 TNF_PROBE_0_DEBUG(hci1394_ohci_init_exit, 176 HCI1394_TNF_HAL_STACK, ""); 177 return (DDI_FAILURE); 178 } 179 180 /* Init 1394a features if present */ 181 if (ohci->ohci_phy == H1394_PHY_1394A) { 182 status = hci1394_ohci_1394a_init(ohci); 183 if (status != DDI_SUCCESS) { 184 (void) hci1394_ohci_soft_reset(ohci); 185 ddi_regs_map_free(&ohci->ohci_reg_handle); 186 mutex_destroy(&ohci->ohci_mutex); 187 kmem_free(ohci, sizeof (hci1394_ohci_t)); 188 *ohci_hdl = NULL; 189 TNF_PROBE_0(hci1394_ohci_1394a_init_fail, 190 HCI1394_TNF_HAL_ERROR, ""); 191 TNF_PROBE_0_DEBUG(hci1394_ohci_init_exit, 192 HCI1394_TNF_HAL_STACK, ""); 193 return (DDI_FAILURE); 194 } 195 } 196 197 /* save away guid, phy type, and vendor info */ 198 soft_state->halinfo.guid = hci1394_ohci_guid(ohci); 199 soft_state->halinfo.phy = ohci->ohci_phy; 200 soft_state->vendor_info.ohci_vendor_id = 201 ddi_get32(ohci->ohci_reg_handle, &ohci->ohci_regs->vendor_id); 202 version = ddi_get32(ohci->ohci_reg_handle, &ohci->ohci_regs->version); 203 soft_state->vendor_info.ohci_version = version; 204 205 /* We do not support version < 1.0 */ 206 if (OHCI_VERSION(version) == 0) { 207 cmn_err(CE_NOTE, 208 "hci1394(%d): OpenHCI version %x.%x is not supported", 209 drvinfo->di_instance, OHCI_VERSION(version), 210 OHCI_REVISION(version)); 211 (void) hci1394_ohci_soft_reset(ohci); 212 ddi_regs_map_free(&ohci->ohci_reg_handle); 213 mutex_destroy(&ohci->ohci_mutex); 214 kmem_free(ohci, sizeof (hci1394_ohci_t)); 215 *ohci_hdl = NULL; 216 TNF_PROBE_0(hci1394_ohci_selfid_init_fail, 217 HCI1394_TNF_HAL_ERROR, ""); 218 TNF_PROBE_0_DEBUG(hci1394_ohci_init_exit, 219 HCI1394_TNF_HAL_STACK, ""); 220 return (DDI_FAILURE); 221 } 222 223 /* Initialize the selfid buffer */ 224 status = hci1394_ohci_selfid_init(ohci); 225 if (status != DDI_SUCCESS) { 226 (void) hci1394_ohci_soft_reset(ohci); 227 ddi_regs_map_free(&ohci->ohci_reg_handle); 228 mutex_destroy(&ohci->ohci_mutex); 229 kmem_free(ohci, sizeof (hci1394_ohci_t)); 230 *ohci_hdl = NULL; 231 TNF_PROBE_0(hci1394_ohci_selfid_init_fail, 232 HCI1394_TNF_HAL_ERROR, ""); 233 TNF_PROBE_0_DEBUG(hci1394_ohci_init_exit, 234 HCI1394_TNF_HAL_STACK, ""); 235 return (DDI_FAILURE); 236 } 237 238 /* Initialize the config rom buffer */ 239 status = hci1394_ohci_cfgrom_init(ohci); 240 if (status != DDI_SUCCESS) { 241 (void) hci1394_ohci_soft_reset(ohci); 242 hci1394_buf_free(&ohci->ohci_selfid_handle); 243 ddi_regs_map_free(&ohci->ohci_reg_handle); 244 mutex_destroy(&ohci->ohci_mutex); 245 kmem_free(ohci, sizeof (hci1394_ohci_t)); 246 *ohci_hdl = NULL; 247 TNF_PROBE_0(hci1394_ohci_cfgrom_init_fail, 248 HCI1394_TNF_HAL_ERROR, ""); 249 TNF_PROBE_0_DEBUG(hci1394_ohci_init_exit, 250 HCI1394_TNF_HAL_STACK, ""); 251 return (DDI_FAILURE); 252 } 253 254 TNF_PROBE_0_DEBUG(hci1394_ohci_init_exit, HCI1394_TNF_HAL_STACK, ""); 255 256 return (DDI_SUCCESS); 257 } 258 259 260 /* 261 * hci1394_ohci_fini() 262 * Cleanup after OpenHCI init. This should be called during detach. 263 */ 264 void 265 hci1394_ohci_fini(hci1394_ohci_handle_t *ohci_hdl) 266 { 267 hci1394_ohci_t *ohci; 268 269 270 ASSERT(ohci_hdl != NULL); 271 TNF_PROBE_0_DEBUG(hci1394_ohci_fini_enter, HCI1394_TNF_HAL_STACK, ""); 272 273 ohci = *ohci_hdl; 274 275 /* reset chip */ 276 (void) hci1394_ohci_soft_reset(ohci); 277 278 /* Free config rom space */ 279 hci1394_buf_free(&ohci->ohci_cfgrom_handle); 280 281 /* Free selfid buffer space */ 282 hci1394_buf_free(&ohci->ohci_selfid_handle); 283 284 /* Free up the OpenHCI registers */ 285 ddi_regs_map_free(&ohci->ohci_reg_handle); 286 287 mutex_destroy(&ohci->ohci_mutex); 288 289 /* Free the OpenHCI state space */ 290 kmem_free(ohci, sizeof (hci1394_ohci_t)); 291 *ohci_hdl = NULL; 292 293 TNF_PROBE_0_DEBUG(hci1394_ohci_fini_exit, HCI1394_TNF_HAL_STACK, ""); 294 } 295 296 297 /* 298 * hci1394_ohci_chip_init() 299 * Initialize the OpenHCI registers. This contains the bulk of the initial 300 * register setup. 301 */ 302 static int 303 hci1394_ohci_chip_init(hci1394_ohci_handle_t ohci_hdl) 304 { 305 int status; 306 307 308 ASSERT(ohci_hdl != NULL); 309 TNF_PROBE_0_DEBUG(hci1394_ohci_chip_init_enter, HCI1394_TNF_HAL_STACK, 310 ""); 311 312 /* Reset 1394 OHCI HW */ 313 status = hci1394_ohci_soft_reset(ohci_hdl); 314 if (status != DDI_SUCCESS) { 315 TNF_PROBE_0(hci1394_ohci_soft_reset_fail, 316 HCI1394_TNF_HAL_ERROR, ""); 317 TNF_PROBE_0_DEBUG(hci1394_ohci_init_exit, 318 HCI1394_TNF_HAL_STACK, ""); 319 return (DDI_FAILURE); 320 } 321 322 /* 323 * Setup Host Control Register. The software reset does not put all 324 * registers in a known state. The Host Control Register is one of these 325 * registers. First make sure noByteSwapData and postedWriteEnable and 326 * are cleared. 327 */ 328 ddi_put32(ohci_hdl->ohci_reg_handle, 329 &ohci_hdl->ohci_regs->hc_ctrl_clr, OHCI_HC_NO_BSWAP | 330 OHCI_HC_POSTWR_ENBL); 331 332 /* 333 * the determination if we should swap data is made during the PCI 334 * initialization. 335 */ 336 if (ohci_hdl->soft_state->swap_data == B_FALSE) { 337 /* 338 * most hba's don't swap data. It will be swapped in the 339 * global swap for SPARC. Enable Link Power(LPS). Enable 340 * Posted Writes 341 */ 342 ddi_put32(ohci_hdl->ohci_reg_handle, 343 &ohci_hdl->ohci_regs->hc_ctrl_set, OHCI_HC_NO_BSWAP | 344 OHCI_HC_LPS | OHCI_HC_POSTWR_ENBL); 345 } else { 346 /* 347 * Swap Data. Enable Link Power(LPS). Enable Posted Writes 348 */ 349 ddi_put32(ohci_hdl->ohci_reg_handle, 350 &ohci_hdl->ohci_regs->hc_ctrl_set, OHCI_HC_LPS | 351 OHCI_HC_POSTWR_ENBL); 352 } 353 354 /* 355 * Wait for PHY to come up. There does not seem to be standard time for 356 * how long wait for the PHY to come up. The problem is that the PHY 357 * provides a clock to the link layer and if that is not stable, we 358 * could get a PCI timeout error when reading/writing a phy register 359 * (and maybe an OpenHCI register?) This used to be set to 10mS which 360 * works for just about every adapter we tested on. We got a new TI 361 * adapter which would crash the system once in a while if nothing 362 * (1394 device) was pluged into the adapter. Changing this delay to 363 * 50mS made that problem go away. This value is set via a patchable 364 * variable located in hci1394_extern.c 365 */ 366 delay(drv_usectohz(hci1394_phy_stabilization_delay_uS)); 367 368 /* Clear Isochrounous receive multi-chan mode registers */ 369 ddi_put32(ohci_hdl->ohci_reg_handle, 370 &ohci_hdl->ohci_regs->ir_multi_maskhi_clr, 0xFFFFFFFF); 371 ddi_put32(ohci_hdl->ohci_reg_handle, 372 &ohci_hdl->ohci_regs->ir_multi_masklo_clr, 0xFFFFFFFF); 373 374 /* 375 * Setup async retry on busy or ack_data_error 376 * secondlimit = 0 <= bits 31-29 377 * cycleLimit = 0 <= bits 28-16 378 * maxPhysRespRetries = 0 <= bits 11-8 379 * maxARRespRetries = 0 <= bits 7-4 380 * maxATReqRetries = 2 <= bits 3-0 381 */ 382 ddi_put32(ohci_hdl->ohci_reg_handle, 383 &ohci_hdl->ohci_regs->at_retries, 0x00000002); 384 385 /* 386 * Setup Link Control 387 * Enable cycleMaster, cycleTimerEnable, and rcvPhyPkt. 388 */ 389 ddi_put32(ohci_hdl->ohci_reg_handle, 390 &ohci_hdl->ohci_regs->link_ctrl_clr, 0xFFFFFFFF); 391 ddi_put32(ohci_hdl->ohci_reg_handle, 392 &ohci_hdl->ohci_regs->link_ctrl_set, OHCI_LC_CYC_MAST | 393 OHCI_LC_CTIME_ENBL | OHCI_LC_RCV_PHY); 394 395 /* 396 * Set the Physical address map boundary to 0x0000FFFFFFFF. The 397 * phys_upper_bound is the upper 32-bits of the 48-bit 1394 address. The 398 * lower 16 bits are assumed to be 0xFFFF. 399 */ 400 ddi_put32(ohci_hdl->ohci_reg_handle, 401 &ohci_hdl->ohci_regs->phys_upper_bound, (uint32_t)0x0000FFFF); 402 403 /* 404 * Enable all async requests. 405 * The asyncReqResourceAll bit (0x80000000) does not get cleared during 406 * a bus reset. If this code is changed to selectively allow nodes to 407 * perform ARREQ's, the ARREQ filter bits will need to be updated after 408 * every bus reset. 409 */ 410 ddi_put32(ohci_hdl->ohci_reg_handle, 411 &ohci_hdl->ohci_regs->ar_req_filterhi_set, (uint32_t)0x80000000); 412 413 /* 414 * clear isochronous interrupt event and mask registers clearing the 415 * mask registers disable all isoc tx & rx ints 416 */ 417 ddi_put32(ohci_hdl->ohci_reg_handle, 418 &ohci_hdl->ohci_regs->it_intr_event_clr, (uint32_t)0xFFFFFFFF); 419 ddi_put32(ohci_hdl->ohci_reg_handle, 420 &ohci_hdl->ohci_regs->it_intr_mask_clr, (uint32_t)0xFFFFFFFF); 421 ddi_put32(ohci_hdl->ohci_reg_handle, 422 &ohci_hdl->ohci_regs->ir_intr_event_clr, (uint32_t)0xFFFFFFFF); 423 ddi_put32(ohci_hdl->ohci_reg_handle, 424 &ohci_hdl->ohci_regs->ir_intr_mask_clr, (uint32_t)0xFFFFFFFF); 425 426 /* Clear interrupt event/mask register */ 427 ddi_put32(ohci_hdl->ohci_reg_handle, 428 &ohci_hdl->ohci_regs->intr_event_clr, (uint32_t)0xFFFFFFFF); 429 ddi_put32(ohci_hdl->ohci_reg_handle, 430 &ohci_hdl->ohci_regs->intr_mask_clr, (uint32_t)0xFFFFFFFF); 431 432 TNF_PROBE_0_DEBUG(hci1394_ohci_chip_init_exit, HCI1394_TNF_HAL_STACK, 433 ""); 434 return (DDI_SUCCESS); 435 } 436 437 438 /* 439 * hci1394_ohci_soft_reset() 440 * Reset OpenHCI HW. 441 */ 442 int 443 hci1394_ohci_soft_reset(hci1394_ohci_handle_t ohci_hdl) 444 { 445 uint32_t resetStatus; 446 447 448 ASSERT(ohci_hdl != NULL); 449 TNF_PROBE_0_DEBUG(hci1394_ohci_soft_reset_enter, 450 HCI1394_TNF_HAL_STACK, ""); 451 452 /* Reset 1394 HW - Reset is bit 16 in HCControl */ 453 ddi_put32(ohci_hdl->ohci_reg_handle, 454 &ohci_hdl->ohci_regs->hc_ctrl_set, OHCI_HC_SOFT_RESET); 455 456 /* Wait for reset to complete */ 457 drv_usecwait(OHCI_CHIP_RESET_TIME_IN_uSEC); 458 459 /* Verify reset is complete */ 460 resetStatus = ddi_get32(ohci_hdl->ohci_reg_handle, 461 &ohci_hdl->ohci_regs->hc_ctrl_set); 462 resetStatus = resetStatus & OHCI_HC_SOFT_RESET; 463 if (resetStatus != 0) { 464 TNF_PROBE_0(hci1394_ohci_reset_not_complete_fail, 465 HCI1394_TNF_HAL_ERROR, ""); 466 TNF_PROBE_0_DEBUG(hci1394_ohci_soft_reset_exit, 467 HCI1394_TNF_HAL_STACK, ""); 468 return (DDI_FAILURE); 469 } 470 471 TNF_PROBE_0_DEBUG(hci1394_ohci_soft_reset_exit, 472 HCI1394_TNF_HAL_STACK, ""); 473 474 return (DDI_SUCCESS); 475 } 476 477 478 /* 479 * hci1394_ohci_reg_read() 480 * Read OpenHCI register. This is called from the test ioctl interface 481 * through devctl. 482 */ 483 void 484 hci1394_ohci_reg_read(hci1394_ohci_handle_t ohci_hdl, 485 uint_t offset, uint32_t *data) 486 { 487 uint32_t *addr; 488 489 490 ASSERT(ohci_hdl != NULL); 491 ASSERT(data != NULL); 492 TNF_PROBE_0_DEBUG(hci1394_ohci_reg_read_enter, 493 HCI1394_TNF_HAL_STACK, ""); 494 495 addr = (uint32_t *)((uintptr_t)ohci_hdl->ohci_regs + 496 (uintptr_t)(offset & OHCI_REG_ADDR_MASK)); 497 *data = ddi_get32(ohci_hdl->ohci_reg_handle, addr); 498 499 TNF_PROBE_0_DEBUG(hci1394_ohci_reg_read_exit, 500 HCI1394_TNF_HAL_STACK, ""); 501 } 502 503 504 /* 505 * hci1394_ohci_reg_write() 506 * Write OpenHCI register. This is called from the test ioctl interface 507 * through devctl. 508 */ 509 void 510 hci1394_ohci_reg_write(hci1394_ohci_handle_t ohci_hdl, 511 uint_t offset, uint32_t data) 512 { 513 uint32_t *addr; 514 515 516 ASSERT(ohci_hdl != NULL); 517 TNF_PROBE_0_DEBUG(hci1394_ohci_reg_read_enter, 518 HCI1394_TNF_HAL_STACK, ""); 519 520 addr = (uint32_t *)((uintptr_t)ohci_hdl->ohci_regs + 521 (uintptr_t)(offset & OHCI_REG_ADDR_MASK)); 522 ddi_put32(ohci_hdl->ohci_reg_handle, addr, data); 523 524 TNF_PROBE_0_DEBUG(hci1394_ohci_reg_read_exit, 525 HCI1394_TNF_HAL_STACK, ""); 526 } 527 528 529 /* 530 * hci1394_ohci_intr_master_enable() 531 * Enable interrupts to be passed on from OpenHCI. This is a global mask. 532 * Individual interrupts still need to be enabled for interrupts to be 533 * generated. 534 */ 535 void 536 hci1394_ohci_intr_master_enable(hci1394_ohci_handle_t ohci_hdl) 537 { 538 ASSERT(ohci_hdl != NULL); 539 TNF_PROBE_0_DEBUG(hci1394_ohci_intr_master_enable_enter, 540 HCI1394_TNF_HAL_STACK, ""); 541 542 ddi_put32(ohci_hdl->ohci_reg_handle, 543 &ohci_hdl->ohci_regs->intr_mask_set, OHCI_INTR_MASTER_INTR_ENBL); 544 545 TNF_PROBE_0_DEBUG(hci1394_ohci_intr_master_enable_exit, 546 HCI1394_TNF_HAL_STACK, ""); 547 } 548 549 550 /* 551 * hci1394_ohci_intr_master_disable() 552 * Disable all OpenHCI interrupts from being passed on. This does not affect 553 * the individual interrupt mask settings. When interrupts are enabled 554 * again, the same individual interrupts will still be enabled. 555 */ 556 void 557 hci1394_ohci_intr_master_disable(hci1394_ohci_handle_t ohci_hdl) 558 { 559 ASSERT(ohci_hdl != NULL); 560 TNF_PROBE_0_DEBUG(hci1394_ohci_intr_master_disable_enter, 561 HCI1394_TNF_HAL_STACK, ""); 562 563 ddi_put32(ohci_hdl->ohci_reg_handle, 564 &ohci_hdl->ohci_regs->intr_mask_clr, OHCI_INTR_MASTER_INTR_ENBL); 565 566 TNF_PROBE_0_DEBUG(hci1394_ohci_intr_master_disable_exit, 567 HCI1394_TNF_HAL_STACK, ""); 568 } 569 570 571 /* 572 * hci1394_ohci_intr_asserted() 573 * Return which ENABLED interrupts are asserted. If an interrupt is disabled 574 * via its mask bit, it will not be returned from here. 575 * 576 * NOTE: we may want to make this a macro at some point. 577 */ 578 uint32_t 579 hci1394_ohci_intr_asserted(hci1394_ohci_handle_t ohci_hdl) 580 { 581 uint32_t interrupts_asserted; 582 583 ASSERT(ohci_hdl != NULL); 584 TNF_PROBE_0_DEBUG(hci1394_ohci_intr_asserted_enter, 585 HCI1394_TNF_HAL_STACK, ""); 586 587 /* 588 * Only look at interrupts which are enabled by reading the 589 * intr_event_clr register. 590 */ 591 interrupts_asserted = ddi_get32(ohci_hdl->ohci_reg_handle, 592 &ohci_hdl->ohci_regs->intr_event_clr); 593 594 TNF_PROBE_0_DEBUG(hci1394_ohci_intr_asserted_exit, 595 HCI1394_TNF_HAL_STACK, ""); 596 return (interrupts_asserted); 597 } 598 599 600 /* 601 * hci1394_ohci_intr_enable() 602 * Enable an individual interrupt or set of interrupts. This does not affect 603 * the global interrupt mask. 604 */ 605 void 606 hci1394_ohci_intr_enable(hci1394_ohci_handle_t ohci_hdl, 607 uint32_t interrupt_mask) 608 { 609 ASSERT(ohci_hdl != NULL); 610 TNF_PROBE_0_DEBUG(hci1394_ohci_intr_enable_enter, 611 HCI1394_TNF_HAL_STACK, ""); 612 613 ddi_put32(ohci_hdl->ohci_reg_handle, 614 &ohci_hdl->ohci_regs->intr_mask_set, interrupt_mask); 615 616 TNF_PROBE_0_DEBUG(hci1394_ohci_intr_enable_exit, 617 HCI1394_TNF_HAL_STACK, ""); 618 } 619 620 621 /* 622 * hci1394_ohci_intr_disable() 623 * Disable an individual interrupt or set of interrupts. This does not affect 624 * the global interrupt mask. 625 */ 626 void 627 hci1394_ohci_intr_disable(hci1394_ohci_handle_t ohci_hdl, 628 uint32_t interrupt_mask) 629 { 630 ASSERT(ohci_hdl != NULL); 631 TNF_PROBE_0_DEBUG(hci1394_ohci_intr_disable_enter, 632 HCI1394_TNF_HAL_STACK, ""); 633 634 ddi_put32(ohci_hdl->ohci_reg_handle, 635 &ohci_hdl->ohci_regs->intr_mask_clr, interrupt_mask); 636 637 TNF_PROBE_0_DEBUG(hci1394_ohci_intr_disable_exit, 638 HCI1394_TNF_HAL_STACK, ""); 639 } 640 641 642 /* 643 * hci1394_ohci_intr_clear() 644 * Clear a set of interrupts so that they are not asserted anymore. 645 * 646 * NOTE: we may want to make this a macro at some point. 647 */ 648 void 649 hci1394_ohci_intr_clear(hci1394_ohci_handle_t ohci_hdl, 650 uint32_t interrupt_mask) 651 { 652 ASSERT(ohci_hdl != NULL); 653 TNF_PROBE_0_DEBUG(hci1394_ohci_intr_clear_enter, 654 HCI1394_TNF_HAL_STACK, ""); 655 656 ddi_put32(ohci_hdl->ohci_reg_handle, 657 &ohci_hdl->ohci_regs->intr_event_clr, interrupt_mask); 658 TNF_PROBE_1_DEBUG(hci1394_ohci_intr_clear, HCI1394_TNF_HAL, "", 659 tnf_uint, intr_mask, interrupt_mask); 660 661 TNF_PROBE_0_DEBUG(hci1394_ohci_intr_clear_exit, 662 HCI1394_TNF_HAL_STACK, ""); 663 } 664 665 666 /* 667 * hci1394_ohci_it_intr_asserted() 668 * Return which ENABLED isoch TX interrupts are asserted. If an interrupt is 669 * disabled via its mask bit, it will not be returned from here. 670 * 671 * NOTE: we may want to make this a macro at some point. 672 */ 673 uint32_t 674 hci1394_ohci_it_intr_asserted(hci1394_ohci_handle_t ohci_hdl) 675 { 676 uint32_t interrupts_asserted; 677 678 ASSERT(ohci_hdl != NULL); 679 TNF_PROBE_0_DEBUG(hci1394_ohci_it_intr_asserted_enter, 680 HCI1394_TNF_HAL_STACK, ""); 681 682 /* Only look at interrupts which are enabled */ 683 interrupts_asserted = ddi_get32(ohci_hdl->ohci_reg_handle, 684 &ohci_hdl->ohci_regs->it_intr_event_clr); 685 686 TNF_PROBE_0_DEBUG(hci1394_ohci_it_intr_asserted_exit, 687 HCI1394_TNF_HAL_STACK, ""); 688 return (interrupts_asserted); 689 } 690 691 692 /* 693 * hci1394_ohci_it_intr_enable() 694 * Enable an individual isoch TX interrupt. This does not affect the general 695 * isoch interrupt mask in the OpenHCI Mask register. That is enabled/ 696 * disabled via hci1394_ohci_intr_enable/hci1394_ohci_intr_disable. 697 */ 698 void 699 hci1394_ohci_it_intr_enable(hci1394_ohci_handle_t ohci_hdl, 700 uint32_t interrupt_mask) 701 { 702 ASSERT(ohci_hdl != NULL); 703 TNF_PROBE_0_DEBUG(hci1394_ohci_it_intr_enable_enter, 704 HCI1394_TNF_HAL_STACK, ""); 705 706 ddi_put32(ohci_hdl->ohci_reg_handle, 707 &ohci_hdl->ohci_regs->it_intr_mask_set, interrupt_mask); 708 709 TNF_PROBE_0_DEBUG(hci1394_ohci_it_intr_enable_exit, 710 HCI1394_TNF_HAL_STACK, ""); 711 } 712 713 714 /* 715 * hci1394_ohci_it_intr_disable() 716 * Disable an individual isoch TX interrupt. This does not affect the general 717 * isoch interrupt mask in the OpenHCI Mask register. That is enabled/ 718 * disabled via hci1394_ohci_intr_enable/hci1394_ohci_intr_disable. 719 */ 720 void 721 hci1394_ohci_it_intr_disable(hci1394_ohci_handle_t ohci_hdl, 722 uint32_t interrupt_mask) 723 { 724 ASSERT(ohci_hdl != NULL); 725 TNF_PROBE_0_DEBUG(hci1394_ohci_it_intr_disable_enter, 726 HCI1394_TNF_HAL_STACK, ""); 727 728 ddi_put32(ohci_hdl->ohci_reg_handle, 729 &ohci_hdl->ohci_regs->it_intr_mask_clr, interrupt_mask); 730 731 TNF_PROBE_0_DEBUG(hci1394_ohci_it_intr_disable_exit, 732 HCI1394_TNF_HAL_STACK, ""); 733 } 734 735 736 /* 737 * hci1394_ohci_it_intr_clear() 738 * Clear an individual isoch TX interrupt so that it is not asserted anymore. 739 * 740 * NOTE: we may want to make this a macro at some point. 741 */ 742 void 743 hci1394_ohci_it_intr_clear(hci1394_ohci_handle_t ohci_hdl, 744 uint32_t interrupt_mask) 745 { 746 ASSERT(ohci_hdl != NULL); 747 TNF_PROBE_0_DEBUG(hci1394_ohci_it_intr_clear_enter, 748 HCI1394_TNF_HAL_STACK, ""); 749 750 ddi_put32(ohci_hdl->ohci_reg_handle, 751 &ohci_hdl->ohci_regs->it_intr_event_clr, interrupt_mask); 752 753 TNF_PROBE_0_DEBUG(hci1394_ohci_it_intr_clear_exit, 754 HCI1394_TNF_HAL_STACK, ""); 755 } 756 757 758 /* 759 * hci1394_ohci_it_ctxt_count_get() 760 * Determine the number of supported isochronous transmit contexts. 761 */ 762 int 763 hci1394_ohci_it_ctxt_count_get(hci1394_ohci_handle_t ohci_hdl) 764 { 765 uint32_t channel_mask; 766 int count; 767 768 ASSERT(ohci_hdl != NULL); 769 TNF_PROBE_0_DEBUG(hci1394_ohci_it_ctxt_count_get_enter, 770 HCI1394_TNF_HAL_STACK, ""); 771 772 /* 773 * hw is required to support contexts 0 to N, where N <= 31 774 * the interrupt mask bits are wired to ground for unsupported 775 * contexts. Write 1's to all it mask bits, then read the mask. 776 * Implemented contexts will read (sequentially) as 1 777 */ 778 ddi_put32(ohci_hdl->ohci_reg_handle, 779 &ohci_hdl->ohci_regs->it_intr_mask_set, 0xFFFFFFFF); 780 channel_mask = ddi_get32(ohci_hdl->ohci_reg_handle, 781 &ohci_hdl->ohci_regs->it_intr_mask_set); 782 count = 0; 783 while (channel_mask != 0) { 784 channel_mask = channel_mask >> 1; 785 count++; 786 } 787 788 TNF_PROBE_0_DEBUG(hci1394_ohci_it_ctxt_count_get_exit, 789 HCI1394_TNF_HAL_STACK, ""); 790 return (count); 791 } 792 793 794 /* 795 * hci1394_ohci_it_cmd_ptr_set() 796 * Set the context pointer for a given isoch TX context. This is the IO 797 * address for the HW to fetch the first descriptor. The context should 798 * not be running when this routine is called. 799 */ 800 void 801 hci1394_ohci_it_cmd_ptr_set(hci1394_ohci_handle_t ohci_hdl, 802 uint_t context_number, uint32_t io_addr) 803 { 804 ASSERT(ohci_hdl != NULL); 805 TNF_PROBE_0_DEBUG(hci1394_ohci_it_cmd_ptr_set_enter, 806 HCI1394_TNF_HAL_STACK, ""); 807 808 ddi_put32(ohci_hdl->ohci_reg_handle, 809 &ohci_hdl->ohci_regs->it[context_number].cmd_ptrlo, 810 io_addr); 811 812 TNF_PROBE_0_DEBUG(hci1394_ohci_it_cmd_ptr_set_exit, 813 HCI1394_TNF_HAL_STACK, ""); 814 } 815 816 817 /* 818 * hci1394_ohci_ir_intr_asserted() 819 * Return which ENABLED isoch RX interrupts are asserted. If an interrupt is 820 * disabled via its mask bit, it will not be returned from here. 821 * 822 * NOTE: we may want to make this a macro at some point. 823 */ 824 uint32_t 825 hci1394_ohci_ir_intr_asserted(hci1394_ohci_handle_t ohci_hdl) 826 { 827 uint32_t interrupts_asserted; 828 829 ASSERT(ohci_hdl != NULL); 830 TNF_PROBE_0_DEBUG(hci1394_ohci_ir_intr_asserted_enter, 831 HCI1394_TNF_HAL_STACK, ""); 832 833 /* Only look at interrupts which are enabled */ 834 interrupts_asserted = ddi_get32(ohci_hdl->ohci_reg_handle, 835 &ohci_hdl->ohci_regs->ir_intr_event_clr); 836 837 TNF_PROBE_0_DEBUG(hci1394_ohci_ir_intr_asserted_exit, 838 HCI1394_TNF_HAL_STACK, ""); 839 return (interrupts_asserted); 840 } 841 842 843 /* 844 * hci1394_ohci_ir_intr_enable() 845 * Enable an individual isoch RX interrupt. This does not affect the isoch 846 * interrupt mask in the OpenHCI Mask register. That is enabled/disabled 847 * via hci1394_ohci_intr_enable/hci1394_ohci_intr_disable. 848 */ 849 void 850 hci1394_ohci_ir_intr_enable(hci1394_ohci_handle_t ohci_hdl, 851 uint32_t interrupt_mask) 852 { 853 ASSERT(ohci_hdl != NULL); 854 TNF_PROBE_0_DEBUG(hci1394_ohci_ir_intr_enable_enter, 855 HCI1394_TNF_HAL_STACK, ""); 856 857 ddi_put32(ohci_hdl->ohci_reg_handle, 858 &ohci_hdl->ohci_regs->ir_intr_mask_set, interrupt_mask); 859 860 TNF_PROBE_0_DEBUG(hci1394_ohci_ir_intr_enable_exit, 861 HCI1394_TNF_HAL_STACK, ""); 862 } 863 864 865 /* 866 * hci1394_ohci_ir_intr_disable() 867 * Disable an individual isoch RX interrupt. This does not affect the isoch 868 * interrupt mask in the OpenHCI Mask register. That is enabled/disabled 869 * via hci1394_ohci_intr_enable/hci1394_ohci_intr_disable. 870 */ 871 void 872 hci1394_ohci_ir_intr_disable(hci1394_ohci_handle_t ohci_hdl, 873 uint32_t interrupt_mask) 874 { 875 ASSERT(ohci_hdl != NULL); 876 TNF_PROBE_0_DEBUG(hci1394_ohci_ir_intr_disable_enter, 877 HCI1394_TNF_HAL_STACK, ""); 878 879 ddi_put32(ohci_hdl->ohci_reg_handle, 880 &ohci_hdl->ohci_regs->ir_intr_mask_clr, interrupt_mask); 881 882 TNF_PROBE_0_DEBUG(hci1394_ohci_ir_intr_disable_exit, 883 HCI1394_TNF_HAL_STACK, ""); 884 } 885 886 887 /* 888 * hci1394_ohci_ir_intr_clear() 889 * Clear an individual isoch RX interrupt so that it is not asserted anymore. 890 * 891 * NOTE: we may want to make this a macro at some point. 892 */ 893 void 894 hci1394_ohci_ir_intr_clear(hci1394_ohci_handle_t ohci_hdl, 895 uint32_t interrupt_mask) 896 { 897 ASSERT(ohci_hdl != NULL); 898 TNF_PROBE_0_DEBUG(hci1394_ohci_ir_intr_clear_enter, 899 HCI1394_TNF_HAL_STACK, ""); 900 901 ddi_put32(ohci_hdl->ohci_reg_handle, 902 &ohci_hdl->ohci_regs->ir_intr_event_clr, interrupt_mask); 903 904 TNF_PROBE_0_DEBUG(hci1394_ohci_ir_intr_clear_exit, 905 HCI1394_TNF_HAL_STACK, ""); 906 } 907 908 909 /* 910 * hci1394_ohci_ir_ctxt_count_get() 911 * Determine the number of supported isochronous receive contexts. 912 */ 913 int 914 hci1394_ohci_ir_ctxt_count_get(hci1394_ohci_handle_t ohci_hdl) 915 { 916 uint32_t channel_mask; 917 int count; 918 919 ASSERT(ohci_hdl != NULL); 920 TNF_PROBE_0_DEBUG(hci1394_ohci_ir_ctxt_count_get_enter, 921 HCI1394_TNF_HAL_STACK, ""); 922 923 /* 924 * hw is required to support contexts 0 to N, where N <= 31 925 * the interrupt mask bits are wired to ground for unsupported 926 * contexts. Write 1's to all ir mask bits, then read the mask. 927 * Implemented contexts will read (sequentially) as 1 928 */ 929 ddi_put32(ohci_hdl->ohci_reg_handle, 930 &ohci_hdl->ohci_regs->ir_intr_mask_set, 0xFFFFFFFF); 931 channel_mask = ddi_get32(ohci_hdl->ohci_reg_handle, 932 &ohci_hdl->ohci_regs->ir_intr_mask_set); 933 count = 0; 934 while (channel_mask != 0) { 935 channel_mask = channel_mask >> 1; 936 count++; 937 } 938 939 TNF_PROBE_0_DEBUG(hci1394_ohci_ir_ctxt_count_get_exit, 940 HCI1394_TNF_HAL_STACK, ""); 941 return (count); 942 } 943 944 945 /* 946 * hci1394_ohci_ir_cmd_ptr_set() 947 * Set the context pointer for a given isoch RX context. This is the IO 948 * address for the HW to fetch the first descriptor. The context should 949 * not be running when this routine is called. 950 */ 951 void 952 hci1394_ohci_ir_cmd_ptr_set(hci1394_ohci_handle_t ohci_hdl, 953 uint_t context_number, uint32_t io_addr) 954 { 955 ASSERT(ohci_hdl != NULL); 956 TNF_PROBE_0_DEBUG(hci1394_ohci_ir_cmd_ptr_set_enter, 957 HCI1394_TNF_HAL_STACK, ""); 958 959 ddi_put32(ohci_hdl->ohci_reg_handle, 960 &ohci_hdl->ohci_regs->ir[context_number].cmd_ptrlo, 961 io_addr); 962 963 TNF_PROBE_0_DEBUG(hci1394_ohci_ir_cmd_ptr_set_exit, 964 HCI1394_TNF_HAL_STACK, ""); 965 } 966 967 968 /* 969 * hci1394_ohci_link_enable() 970 * Enable the 1394 link layer. When the link is enabled, the PHY will pass 971 * up any 1394 bus transactions which would normally come up to the link. 972 */ 973 void 974 hci1394_ohci_link_enable(hci1394_ohci_handle_t ohci_hdl) 975 { 976 ASSERT(ohci_hdl != NULL); 977 TNF_PROBE_0_DEBUG(hci1394_ohci_link_enable_enter, 978 HCI1394_TNF_HAL_STACK, ""); 979 980 ddi_put32(ohci_hdl->ohci_reg_handle, 981 &ohci_hdl->ohci_regs->hc_ctrl_set, OHCI_HC_LINK_ENBL); 982 983 TNF_PROBE_0_DEBUG(hci1394_ohci_link_enable_exit, 984 HCI1394_TNF_HAL_STACK, ""); 985 } 986 987 988 /* 989 * hci1394_ohci_link_disable() 990 * Disable the 1394 link layer. When the link is disabled, the PHY will NOT 991 * pass up any 1394 bus transactions which would normally come up to the 992 * link. This "logically" disconnects us from the 1394 bus. 993 */ 994 void 995 hci1394_ohci_link_disable(hci1394_ohci_handle_t ohci_hdl) 996 { 997 ASSERT(ohci_hdl != NULL); 998 TNF_PROBE_0_DEBUG(hci1394_ohci_link_disable_enter, 999 HCI1394_TNF_HAL_STACK, ""); 1000 1001 ddi_put32(ohci_hdl->ohci_reg_handle, 1002 &ohci_hdl->ohci_regs->hc_ctrl_clr, OHCI_HC_LINK_ENBL); 1003 1004 TNF_PROBE_0_DEBUG(hci1394_ohci_link_disable_exit, 1005 HCI1394_TNF_HAL_STACK, ""); 1006 } 1007 1008 1009 /* 1010 * hci1394_ohci_bus_reset() 1011 * Reset the 1394 bus. This performs a "long" bus reset and can be called 1012 * when the adapter has either a 1394-1995 or 1394A PHY. 1013 */ 1014 int 1015 hci1394_ohci_bus_reset(hci1394_ohci_handle_t ohci_hdl) 1016 { 1017 int status; 1018 uint_t reg; 1019 1020 1021 ASSERT(ohci_hdl != NULL); 1022 TNF_PROBE_0_DEBUG(hci1394_ohci_bus_reset_enter, 1023 HCI1394_TNF_HAL_STACK, ""); 1024 1025 /* 1026 * We want to reset the bus. We also handle the root_holdoff and gap 1027 * count cacheing explained at the top of this file. 1028 */ 1029 reg = OHCI_PHY_IBR; 1030 if (ohci_hdl->ohci_set_root_holdoff == B_TRUE) { 1031 reg = reg | OHCI_PHY_RHB; 1032 } 1033 if (ohci_hdl->ohci_set_gap_count == B_TRUE) { 1034 reg = reg | ohci_hdl->ohci_gap_count; 1035 } else { 1036 reg = reg | OHCI_PHY_MAX_GAP; 1037 } 1038 1039 /* 1040 * Reset the bus. We intentionally do NOT do a PHY read here. A PHY 1041 * read could introduce race conditions and would be more likely to fail 1042 * due to a timeout. 1043 */ 1044 status = hci1394_ohci_phy_write(ohci_hdl, 0x1, reg); 1045 if (status != DDI_SUCCESS) { 1046 TNF_PROBE_0(hci1394_ohci_phy_write_fail, 1047 HCI1394_TNF_HAL_ERROR, ""); 1048 TNF_PROBE_0_DEBUG(hci1394_ohci_bus_reset_exit, 1049 HCI1394_TNF_HAL_STACK, ""); 1050 return (DDI_FAILURE); 1051 } 1052 1053 /* clear the root holdoff and gap count state bits */ 1054 ohci_hdl->ohci_set_root_holdoff = B_FALSE; 1055 ohci_hdl->ohci_set_gap_count = B_FALSE; 1056 1057 TNF_PROBE_0_DEBUG(hci1394_ohci_bus_reset_exit, 1058 HCI1394_TNF_HAL_STACK, ""); 1059 1060 return (DDI_SUCCESS); 1061 } 1062 1063 /* 1064 * 1065 * hci1394_ohci_bus_reset_nroot() 1066 * Reset the 1394 bus. This performs a "long" bus reset with out a root. 1067 */ 1068 int 1069 hci1394_ohci_bus_reset_nroot(hci1394_ohci_handle_t ohci_hdl) 1070 { 1071 int status; 1072 uint_t reg; 1073 1074 ASSERT(ohci_hdl != NULL); 1075 1076 /* 1077 * We want to reset the bus. We don't care about any holdoff 1078 * we are suspending need no root... 1079 */ 1080 (void) hci1394_ohci_phy_read(ohci_hdl, 0x1, ®); 1081 reg = reg | OHCI_PHY_IBR; 1082 reg = reg & ~OHCI_PHY_RHB; 1083 1084 /* 1085 * Reset the bus. We intentionally do NOT do a PHY read here. A PHY 1086 * read could introduce race conditions and would be more likely to fail 1087 * due to a timeout. 1088 */ 1089 status = hci1394_ohci_phy_write(ohci_hdl, 0x1, reg); 1090 if (status != DDI_SUCCESS) { 1091 TNF_PROBE_0(hci1394_ohci_phy_write_fail, 1092 HCI1394_TNF_HAL_ERROR, ""); 1093 TNF_PROBE_0_DEBUG(hci1394_ohci_bus_reset_nroot_exit, 1094 HCI1394_TNF_HAL_STACK, ""); 1095 return (DDI_FAILURE); 1096 } 1097 1098 return (DDI_SUCCESS); 1099 } 1100 1101 /* 1102 * hci1394_ohci_phy_init() 1103 * Setup the PHY. This should be called during attach and performs any PHY 1104 * initialization required including figuring out what kind of PHY we have. 1105 */ 1106 int 1107 hci1394_ohci_phy_init(hci1394_ohci_handle_t ohci_hdl) 1108 { 1109 int status; 1110 uint_t phy_reg; 1111 1112 1113 ASSERT(ohci_hdl != NULL); 1114 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_init_enter, 1115 HCI1394_TNF_HAL_STACK, ""); 1116 1117 /* 1118 * if the phy has extended set to 7, the phy is a not a 1394-1995 PHY. 1119 * It could be a 1394a phy or beyond. The PHY type can be found in PHY 1120 * register page 1 in the compliance_level register. 1121 * 1122 * Since there are not any current standards beyond 1394A, we are going 1123 * to consider the PHY to be a 1394A phy if the extended bit is set. 1124 * 1125 * phy registers are byte wide registers and are addressed as 0, 1, 2, 1126 * 3, ... Phy register 0 may not be read or written. 1127 * 1128 * Phy register 0x2 (bit 0 MSB, 7 LSB) 1129 * Extended - bits 0 - 2 1130 * Total Ports - bits 4 - 7 1131 */ 1132 status = hci1394_ohci_phy_read(ohci_hdl, 2, &phy_reg); 1133 if (status != DDI_SUCCESS) { 1134 TNF_PROBE_0(hci1394_ohci_phy_read_failed, 1135 HCI1394_TNF_HAL_ERROR, ""); 1136 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_init_exit, 1137 HCI1394_TNF_HAL_STACK, ""); 1138 return (DDI_FAILURE); 1139 } 1140 1141 if ((phy_reg & OHCI_PHY_EXTND_MASK) != OHCI_PHY_EXTND) { 1142 /* 1143 * if the extended bit is not set, we have to be a 1394-1995 1144 * PHY 1145 */ 1146 ohci_hdl->ohci_phy = H1394_PHY_1995; 1147 } else { 1148 /* Treat all other PHY's as a 1394A PHY */ 1149 ohci_hdl->ohci_phy = H1394_PHY_1394A; 1150 } 1151 1152 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_init_exit, 1153 HCI1394_TNF_HAL_STACK, ""); 1154 1155 return (DDI_SUCCESS); 1156 } 1157 1158 1159 /* 1160 * hci1394_ohci_phy_resume() 1161 * re-initialize the PHY. This routine should be called during a resume after 1162 * a successful suspend has been done. 1163 */ 1164 /* ARGSUSED */ 1165 static int 1166 hci1394_ohci_phy_resume(hci1394_ohci_handle_t ohci_hdl) 1167 { 1168 ASSERT(ohci_hdl != NULL); 1169 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_resume_enter, 1170 HCI1394_TNF_HAL_STACK, ""); 1171 1172 /* There is currently nothing to re-initialize here */ 1173 1174 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_resume_exit, 1175 HCI1394_TNF_HAL_STACK, ""); 1176 1177 return (DDI_SUCCESS); 1178 } 1179 1180 1181 /* 1182 * hci1394_ohci_phy_set() 1183 * Perform bitset operation on PHY register. 1184 */ 1185 int 1186 hci1394_ohci_phy_set(hci1394_ohci_handle_t ohci_hdl, uint_t address, 1187 uint_t bits) 1188 { 1189 int status; 1190 uint_t reg; 1191 1192 1193 ASSERT(ohci_hdl != NULL); 1194 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_set_enter, 1195 HCI1394_TNF_HAL_STACK, ""); 1196 1197 mutex_enter(&ohci_hdl->ohci_mutex); 1198 1199 /* read the PHY register */ 1200 status = hci1394_ohci_phy_read_no_lock(ohci_hdl, address, ®); 1201 if (status != DDI_SUCCESS) { 1202 mutex_exit(&ohci_hdl->ohci_mutex); 1203 TNF_PROBE_0(hci1394_ohci_phy_read_fail, 1204 HCI1394_TNF_HAL_ERROR, ""); 1205 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_set_exit, 1206 HCI1394_TNF_HAL_STACK, ""); 1207 return (DDI_FAILURE); 1208 } 1209 1210 /* Set the bits and write the result back */ 1211 reg = reg | bits; 1212 status = hci1394_ohci_phy_write_no_lock(ohci_hdl, address, reg); 1213 if (status != DDI_SUCCESS) { 1214 mutex_exit(&ohci_hdl->ohci_mutex); 1215 TNF_PROBE_0(hci1394_ohci_phy_write_fail, 1216 HCI1394_TNF_HAL_ERROR, ""); 1217 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_set_exit, 1218 HCI1394_TNF_HAL_STACK, ""); 1219 return (DDI_FAILURE); 1220 } 1221 1222 mutex_exit(&ohci_hdl->ohci_mutex); 1223 1224 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_set_exit, HCI1394_TNF_HAL_STACK, 1225 ""); 1226 1227 return (DDI_SUCCESS); 1228 } 1229 1230 1231 /* 1232 * hci1394_ohci_phy_clr() 1233 * Perform bitclr operation on PHY register. 1234 */ 1235 int 1236 hci1394_ohci_phy_clr(hci1394_ohci_handle_t ohci_hdl, uint_t address, 1237 uint_t bits) 1238 { 1239 int status; 1240 uint_t reg; 1241 1242 1243 ASSERT(ohci_hdl != NULL); 1244 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_clr_enter, 1245 HCI1394_TNF_HAL_STACK, ""); 1246 1247 mutex_enter(&ohci_hdl->ohci_mutex); 1248 1249 /* read the PHY register */ 1250 status = hci1394_ohci_phy_read_no_lock(ohci_hdl, address, ®); 1251 if (status != DDI_SUCCESS) { 1252 mutex_exit(&ohci_hdl->ohci_mutex); 1253 TNF_PROBE_0(hci1394_ohci_phy_read_fail, 1254 HCI1394_TNF_HAL_ERROR, ""); 1255 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_clr_exit, 1256 HCI1394_TNF_HAL_STACK, ""); 1257 return (DDI_FAILURE); 1258 } 1259 1260 /* Set the bits and write the result back */ 1261 reg = reg & ~bits; 1262 status = hci1394_ohci_phy_write_no_lock(ohci_hdl, address, reg); 1263 if (status != DDI_SUCCESS) { 1264 mutex_exit(&ohci_hdl->ohci_mutex); 1265 TNF_PROBE_0(hci1394_ohci_phy_write_fail, 1266 HCI1394_TNF_HAL_ERROR, ""); 1267 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_clr_exit, 1268 HCI1394_TNF_HAL_STACK, ""); 1269 return (DDI_FAILURE); 1270 } 1271 1272 mutex_exit(&ohci_hdl->ohci_mutex); 1273 1274 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_clr_exit, HCI1394_TNF_HAL_STACK, 1275 ""); 1276 1277 return (DDI_SUCCESS); 1278 } 1279 1280 1281 /* 1282 * hci1394_ohci_phy_read() 1283 * Atomic PHY register read 1284 */ 1285 int 1286 hci1394_ohci_phy_read(hci1394_ohci_handle_t ohci_hdl, uint_t address, 1287 uint_t *data) 1288 { 1289 int status; 1290 1291 ASSERT(ohci_hdl != NULL); 1292 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_read_enter, HCI1394_TNF_HAL_STACK, 1293 ""); 1294 mutex_enter(&ohci_hdl->ohci_mutex); 1295 status = hci1394_ohci_phy_read_no_lock(ohci_hdl, address, data); 1296 mutex_exit(&ohci_hdl->ohci_mutex); 1297 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_read_exit, HCI1394_TNF_HAL_STACK, 1298 ""); 1299 1300 return (status); 1301 } 1302 1303 1304 /* 1305 * hci1394_ohci_phy_write() 1306 * Atomic PHY register write 1307 */ 1308 int 1309 hci1394_ohci_phy_write(hci1394_ohci_handle_t ohci_hdl, uint_t address, 1310 uint_t data) 1311 { 1312 int status; 1313 1314 ASSERT(ohci_hdl != NULL); 1315 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_write_enter, HCI1394_TNF_HAL_STACK, 1316 ""); 1317 mutex_enter(&ohci_hdl->ohci_mutex); 1318 status = hci1394_ohci_phy_write_no_lock(ohci_hdl, address, data); 1319 mutex_exit(&ohci_hdl->ohci_mutex); 1320 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_write_exit, HCI1394_TNF_HAL_STACK, 1321 ""); 1322 1323 return (status); 1324 } 1325 1326 1327 /* 1328 * hci1394_ohci_phy_read_no_lock() 1329 * This routine actually performs the PHY register read. It is seperated 1330 * out from phy_read so set & clr lock can perform an atomic PHY register 1331 * operation. It assumes the OpenHCI mutex is held. 1332 */ 1333 static int 1334 hci1394_ohci_phy_read_no_lock(hci1394_ohci_handle_t ohci_hdl, uint_t address, 1335 uint_t *data) 1336 { 1337 uint32_t ohci_reg; 1338 int count; 1339 1340 1341 ASSERT(ohci_hdl != NULL); 1342 ASSERT(data != NULL); 1343 ASSERT(MUTEX_HELD(&ohci_hdl->ohci_mutex)); 1344 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_read_no_lock_enter, 1345 HCI1394_TNF_HAL_STACK, ""); 1346 1347 /* You can't read or write PHY register #0 */ 1348 if (address == 0) { 1349 TNF_PROBE_1(hci1394_ohci_phy_addr_fail, HCI1394_TNF_HAL_ERROR, 1350 "", tnf_string, errmsg, "can't rd/wr PHY reg #0"); 1351 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_read_no_lock_exit, 1352 HCI1394_TNF_HAL_STACK, ""); 1353 return (DDI_FAILURE); 1354 } 1355 1356 /* Verify phy access not in progress */ 1357 ohci_reg = ddi_get32(ohci_hdl->ohci_reg_handle, 1358 &ohci_hdl->ohci_regs->phy_ctrl); 1359 if ((ohci_reg & (OHCI_PHYC_RDREG | OHCI_PHYC_WRREG)) != 0) { 1360 TNF_PROBE_1(hci1394_ohci_phy_xfer_fail, HCI1394_TNF_HAL_ERROR, 1361 "", tnf_string, errmsg, "transfer already in progress?"); 1362 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_read_no_lock_exit, 1363 HCI1394_TNF_HAL_STACK, ""); 1364 return (DDI_FAILURE); 1365 } 1366 1367 /* Start the PHY register read */ 1368 ohci_reg = OHCI_PHYC_RDREG | ((address & 0xF) << 1369 OHCI_PHYC_REGADDR_SHIFT); 1370 ddi_put32(ohci_hdl->ohci_reg_handle, &ohci_hdl->ohci_regs->phy_ctrl, 1371 ohci_reg); 1372 1373 /* 1374 * The PHY read usually takes less than 1uS. It is not worth having 1375 * this be interrupt driven. Having this be interrupt driven would also 1376 * make the bus reset and self id processing much more complex for 1377 * 1995 PHY's. We will wait up to hci1394_phy_delay_uS for the read 1378 * to complete (this was initially set to 10). I have yet to see 1379 * count > 1. The delay is a patchable variable. 1380 */ 1381 count = 0; 1382 while (count < hci1394_phy_delay_uS) { 1383 /* See if the read is done yet */ 1384 ohci_reg = ddi_get32(ohci_hdl->ohci_reg_handle, 1385 &ohci_hdl->ohci_regs->phy_ctrl); 1386 if ((ohci_reg & OHCI_PHYC_RDDONE) != 0) { 1387 /* 1388 * The read is done. clear the phyRegRecv interrupt. We 1389 * do not have this interrupt enabled but this keeps 1390 * things clean in case someone in the future does. 1391 * Break out of the loop, we are done. 1392 */ 1393 ddi_put32(ohci_hdl->ohci_reg_handle, 1394 &ohci_hdl->ohci_regs->intr_event_clr, 1395 OHCI_INTR_PHY_REG_RCVD); 1396 break; 1397 } 1398 1399 /* 1400 * the phy read did not yet complete, wait 1uS, increment the 1401 * count and try again. 1402 */ 1403 drv_usecwait(1); 1404 count++; 1405 } 1406 1407 /* Check to see if we timed out */ 1408 if (count >= hci1394_phy_delay_uS) { 1409 /* we timed out, return failure */ 1410 *data = 0; 1411 TNF_PROBE_0(hci1394_ohci_phy_rd_timeout_fail, 1412 HCI1394_TNF_HAL_ERROR, ""); 1413 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_read_no_lock_exit, 1414 HCI1394_TNF_HAL_STACK, ""); 1415 return (DDI_FAILURE); 1416 } 1417 1418 /* setup the PHY read data to be returned */ 1419 *data = (ddi_get32(ohci_hdl->ohci_reg_handle, 1420 &ohci_hdl->ohci_regs->phy_ctrl) & OHCI_PHYC_RDDATA_MASK) >> 1421 OHCI_PHYC_RDDATA_SHIFT; 1422 1423 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_read_no_lock_exit, 1424 HCI1394_TNF_HAL_STACK, ""); 1425 1426 return (DDI_SUCCESS); 1427 } 1428 1429 1430 /* 1431 * hci1394_ohci_phy_write_no_lock() 1432 * This routine actually performs the PHY register write. It is separated 1433 * out from phy_write so set & clr lock can perform an atomic PHY register 1434 * operation. It assumes the OpenHCI mutex is held. 1435 */ 1436 static int 1437 hci1394_ohci_phy_write_no_lock(hci1394_ohci_handle_t ohci_hdl, uint_t address, 1438 uint_t data) 1439 { 1440 uint32_t ohci_reg; 1441 int count; 1442 1443 1444 ASSERT(ohci_hdl != NULL); 1445 ASSERT(MUTEX_HELD(&ohci_hdl->ohci_mutex)); 1446 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_write_enter, 1447 HCI1394_TNF_HAL_STACK, ""); 1448 1449 /* You can't read or write PHY register #0 */ 1450 if (address == 0) { 1451 TNF_PROBE_1(hci1394_ohci_phy_addr_fail, HCI1394_TNF_HAL_ERROR, 1452 "", tnf_string, errmsg, "can't rd/wr PHY reg #0"); 1453 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_write_exit, 1454 HCI1394_TNF_HAL_STACK, ""); 1455 return (DDI_FAILURE); 1456 } 1457 1458 /* Verify phy access not in progress */ 1459 ohci_reg = ddi_get32(ohci_hdl->ohci_reg_handle, 1460 &ohci_hdl->ohci_regs->phy_ctrl); 1461 if ((ohci_reg & (OHCI_PHYC_RDREG | OHCI_PHYC_WRREG)) != 0) { 1462 TNF_PROBE_1(hci1394_ohci_phy_xfer_fail, HCI1394_TNF_HAL_ERROR, 1463 "", tnf_string, errmsg, "transfer already in progress?"); 1464 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_write_exit, 1465 HCI1394_TNF_HAL_STACK, ""); 1466 return (DDI_FAILURE); 1467 } 1468 1469 /* Start the PHY register write */ 1470 ohci_reg = OHCI_PHYC_WRREG | ((address & 0xF) << 1471 OHCI_PHYC_REGADDR_SHIFT) | (data & OHCI_PHYC_WRDATA_MASK); 1472 ddi_put32(ohci_hdl->ohci_reg_handle, 1473 &ohci_hdl->ohci_regs->phy_ctrl, ohci_reg); 1474 1475 /* 1476 * The PHY write usually takes less than 1uS. It is not worth having 1477 * this be interrupt driven. Having this be interrupt driven would also 1478 * make the bus reset and self id processing much more complex. We will 1479 * wait up to hci1394_phy_delay_uS for the write to complete (this was 1480 * initially set to 10). I have yet to see count > 0. The delay is a 1481 * patchable variable. 1482 */ 1483 count = 0; 1484 while (count < hci1394_phy_delay_uS) { 1485 /* See if the write is done yet */ 1486 ohci_reg = ddi_get32(ohci_hdl->ohci_reg_handle, 1487 &ohci_hdl->ohci_regs->phy_ctrl); 1488 if ((ohci_reg & OHCI_PHYC_WRREG) == 0) { 1489 /* 1490 * The write completed. Break out of the loop, we are 1491 * done. 1492 */ 1493 break; 1494 } 1495 1496 /* 1497 * the phy write did not yet complete, wait 1uS, increment the 1498 * count and try again. 1499 */ 1500 drv_usecwait(1); 1501 count++; 1502 } 1503 1504 /* Check to see if we timed out */ 1505 if (count >= hci1394_phy_delay_uS) { 1506 /* we timed out, return failure */ 1507 TNF_PROBE_0(hci1394_ohci_phy_wr_timeout_fail, 1508 HCI1394_TNF_HAL_ERROR, ""); 1509 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_write_exit, 1510 HCI1394_TNF_HAL_STACK, ""); 1511 return (DDI_FAILURE); 1512 } 1513 1514 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_write_exit, 1515 HCI1394_TNF_HAL_STACK, ""); 1516 1517 return (DDI_SUCCESS); 1518 } 1519 1520 1521 /* 1522 * hci1394_ohci_phy_info() 1523 * Return selfid word for our PHY. This routine should ONLY be called for 1524 * adapters with a 1394-1995 PHY. These PHY's do not embed their own selfid 1525 * information in the selfid buffer so we need to do it for them in the 1526 * selfid complete interrupt handler. This routine only supports building 1527 * selfid info for a 3 port PHY. Since we will probably not ever see a 1528 * 1394-1995 PHY in any production system, and if we do it will have 3 ports 1529 * or less, this is a pretty safe assumption. 1530 */ 1531 int 1532 hci1394_ohci_phy_info(hci1394_ohci_handle_t ohci_hdl, uint32_t *info) 1533 { 1534 int status; 1535 uint32_t phy_info; 1536 uint32_t reg; 1537 int index; 1538 int num_ports; 1539 int count; 1540 uint32_t port_status; 1541 1542 1543 ASSERT(ohci_hdl != NULL); 1544 ASSERT(info != NULL); 1545 ASSERT(ohci_hdl->ohci_phy == H1394_PHY_1995); 1546 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_info_enter, 1547 HCI1394_TNF_HAL_STACK, ""); 1548 1549 /* 1550 * Set Link on. We are using power class 0 since we have no idea what 1551 * our real power class is. 1552 */ 1553 phy_info = 0x80400000; 1554 1555 /* Add in Physical ID */ 1556 reg = ddi_get32(ohci_hdl->ohci_reg_handle, 1557 &ohci_hdl->ohci_regs->node_id); 1558 phy_info = phy_info | ((reg << IEEE1394_SELFID_PHYID_SHIFT) & 1559 IEEE1394_SELFID_PHYID_MASK); 1560 1561 /* Add in Gap Count */ 1562 status = hci1394_ohci_phy_read(ohci_hdl, 1, ®); 1563 if (status != DDI_SUCCESS) { 1564 TNF_PROBE_0(hci1394_ohci_phy_read_fail, 1565 HCI1394_TNF_HAL_ERROR, ""); 1566 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_info_exit, 1567 HCI1394_TNF_HAL_STACK, ""); 1568 return (DDI_FAILURE); 1569 } 1570 phy_info = phy_info | ((reg << IEEE1394_SELFID_GAP_CNT_SHIFT) & 1571 IEEE1394_SELFID_GAP_CNT_MASK); 1572 1573 /* Add in speed & ports */ 1574 status = hci1394_ohci_phy_read(ohci_hdl, 2, ®); 1575 if (status != DDI_SUCCESS) { 1576 TNF_PROBE_0(hci1394_ohci_phy_read_fail, 1577 HCI1394_TNF_HAL_ERROR, ""); 1578 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_info_exit, 1579 HCI1394_TNF_HAL_STACK, ""); 1580 return (DDI_FAILURE); 1581 } 1582 phy_info = phy_info | ((reg & 0xC0) << 8); 1583 num_ports = reg & 0x1F; 1584 1585 /* PHY reports that it has 0 ports?? */ 1586 if (num_ports == 0) { 1587 TNF_PROBE_1(hci1394_ohci_phy_zero_ports_fail, 1588 HCI1394_TNF_HAL_ERROR, "", tnf_string, errmsg, 1589 "1995 phy has zero ports?"); 1590 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_info_exit, 1591 HCI1394_TNF_HAL_STACK, ""); 1592 return (DDI_FAILURE); 1593 } 1594 1595 /* Build up the port information for each port in the PHY */ 1596 count = 0; 1597 for (index = 0; index < 3; index++) { 1598 if (num_ports > 0) { 1599 status = hci1394_ohci_phy_read(ohci_hdl, 1600 count + 3, ®); 1601 if (status != DDI_SUCCESS) { 1602 TNF_PROBE_0(hci1394_ohci_phy_read_fail, 1603 HCI1394_TNF_HAL_ERROR, ""); 1604 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_info_exit, 1605 HCI1394_TNF_HAL_STACK, ""); 1606 return (DDI_FAILURE); 1607 } 1608 /* if port is not connected */ 1609 if ((reg & 0x04) == 0) { 1610 port_status = 1611 IEEE1394_SELFID_PORT_NOT_CONNECTED; 1612 1613 /* else if port is connected to parent */ 1614 } else if ((reg & 0x08) == 0) { 1615 port_status = IEEE1394_SELFID_PORT_TO_PARENT; 1616 1617 /* else port is connected to child */ 1618 } else { 1619 port_status = IEEE1394_SELFID_PORT_TO_CHILD; 1620 } 1621 1622 num_ports--; 1623 } else { 1624 port_status = IEEE1394_SELFID_PORT_NO_PORT; 1625 } 1626 1627 /* add in the port information */ 1628 phy_info = phy_info | (port_status << (6 - (index * 2))); 1629 count++; 1630 } 1631 1632 /* Copy the PHY selfid info to the return parameter */ 1633 *info = phy_info; 1634 1635 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_info_exit, 1636 HCI1394_TNF_HAL_STACK, ""); 1637 1638 return (DDI_SUCCESS); 1639 } 1640 1641 1642 /* 1643 * hci1394_ohci_current_busgen() 1644 * return the current bus generation. 1645 */ 1646 uint_t 1647 hci1394_ohci_current_busgen(hci1394_ohci_handle_t ohci_hdl) 1648 { 1649 uint32_t reg; 1650 uint_t generation_count; 1651 1652 1653 ASSERT(ohci_hdl != NULL); 1654 TNF_PROBE_0_DEBUG(hci1394_ohci_current_busgen_enter, 1655 HCI1394_TNF_HAL_STACK, ""); 1656 1657 reg = ddi_get32(ohci_hdl->ohci_reg_handle, 1658 &ohci_hdl->ohci_regs->self_id_count); 1659 generation_count = (reg & OHCI_SLFC_GEN_MASK) >> OHCI_SLFC_GEN_SHIFT; 1660 1661 TNF_PROBE_0_DEBUG(hci1394_ohci_current_busgen_exit, 1662 HCI1394_TNF_HAL_STACK, ""); 1663 1664 return (generation_count); 1665 } 1666 1667 1668 /* 1669 * hci1394_ohci_startup() 1670 * Startup the 1394 nexus driver. This is called after all of the HW has 1671 * been initialized (in both attach and resume) and we are ready to 1672 * participate on the bus. 1673 */ 1674 int 1675 hci1394_ohci_startup(hci1394_ohci_handle_t ohci_hdl) 1676 { 1677 int status; 1678 1679 1680 ASSERT(ohci_hdl != NULL); 1681 TNF_PROBE_0_DEBUG(hci1394_ohci_startup_enter, 1682 HCI1394_TNF_HAL_STACK, ""); 1683 1684 /* 1685 * Turn on 1394 link. This allows us to receive 1394 traffic off the 1686 * bus 1687 */ 1688 hci1394_ohci_link_enable(ohci_hdl); 1689 1690 /* 1691 * Reset the 1394 Bus. 1692 * Need to do this so that the link layer can collect all of the self-id 1693 * packets. The Interrupt routine will cause further initialization 1694 * after the bus reset has completed 1695 */ 1696 status = hci1394_ohci_bus_reset(ohci_hdl); 1697 if (status != DDI_SUCCESS) { 1698 TNF_PROBE_1_DEBUG(hci1394_ohci_startup_exit, 1699 HCI1394_TNF_HAL_ERROR, "", tnf_string, errmsg, 1700 "failed to reset bus"); 1701 TNF_PROBE_0_DEBUG(hci1394_ohci_startup_exit, 1702 HCI1394_TNF_HAL_STACK, ""); 1703 return (DDI_FAILURE); 1704 } 1705 1706 /* setup out initial interrupt mask and enable interrupts */ 1707 hci1394_isr_mask_setup(ohci_hdl->soft_state); 1708 hci1394_ohci_intr_master_enable(ohci_hdl); 1709 1710 TNF_PROBE_0_DEBUG(hci1394_ohci_startup_exit, HCI1394_TNF_HAL_STACK, 1711 ""); 1712 1713 return (DDI_SUCCESS); 1714 } 1715 1716 1717 /* 1718 * hci1394_ohci_postwr_addr() 1719 * Read the Posted Write Address registers. This should be read when a 1720 * posted write error is detected to find out what transaction had an error. 1721 */ 1722 void 1723 hci1394_ohci_postwr_addr(hci1394_ohci_handle_t ohci_hdl, uint64_t *addr) 1724 { 1725 uint32_t reg; 1726 1727 1728 ASSERT(ohci_hdl != NULL); 1729 ASSERT(addr != NULL); 1730 TNF_PROBE_0_DEBUG(hci1394_ohci_postwr_addr_enter, 1731 HCI1394_TNF_HAL_STACK, ""); 1732 1733 /* read in the errored address */ 1734 reg = ddi_get32(ohci_hdl->ohci_reg_handle, 1735 &ohci_hdl->ohci_regs->posted_write_addrhi); 1736 *addr = ((uint64_t)reg) << 32; 1737 reg = ddi_get32(ohci_hdl->ohci_reg_handle, 1738 &ohci_hdl->ohci_regs->posted_write_addrlo); 1739 *addr = *addr | (uint64_t)reg; 1740 1741 /* 1742 * Interrupt should be cleared after reading the posted write address. 1743 * See 13.2.8.1 in OpenHCI spec v1.0. 1744 */ 1745 hci1394_ohci_intr_clear(ohci_hdl, OHCI_INTR_POST_WR_ERR); 1746 1747 TNF_PROBE_0_DEBUG(hci1394_ohci_postwr_addr_exit, 1748 HCI1394_TNF_HAL_STACK, ""); 1749 } 1750 1751 1752 /* 1753 * hci1394_ohci_guid() 1754 * Return the adapter's GUID 1755 */ 1756 uint64_t 1757 hci1394_ohci_guid(hci1394_ohci_handle_t ohci_hdl) 1758 { 1759 uint32_t reg; 1760 uint64_t guid; 1761 1762 1763 ASSERT(ohci_hdl != NULL); 1764 TNF_PROBE_0_DEBUG(hci1394_ohci_guid_enter, HCI1394_TNF_HAL_STACK, ""); 1765 1766 reg = ddi_get32(ohci_hdl->ohci_reg_handle, 1767 &ohci_hdl->ohci_regs->guid_hi); 1768 guid = ((uint64_t)reg) << 32; 1769 reg = ddi_get32(ohci_hdl->ohci_reg_handle, 1770 &ohci_hdl->ohci_regs->guid_lo); 1771 guid = guid | (uint64_t)reg; 1772 1773 TNF_PROBE_0_DEBUG(hci1394_ohci_guid_exit, HCI1394_TNF_HAL_STACK, ""); 1774 1775 return (guid); 1776 } 1777 1778 1779 /* 1780 * hci1394_ohci_csr_read() 1781 * Read one of the HW implemented CSR registers. These include 1782 * bus_manager_id, bandwidth_available, channels_available_hi, and 1783 * channels_available_lo. Offset should be set to 1784 * OHCI_CSR_SEL_BUS_MGR_ID, OHCI_CSR_SEL_BANDWIDTH_AVAIL 1785 * OHCI_CSR_SEL_CHANS_AVAIL_HI, or OHCI_CSR_SEL_CHANS_AVAIL_LO. 1786 */ 1787 int 1788 hci1394_ohci_csr_read(hci1394_ohci_handle_t ohci_hdl, uint_t offset, 1789 uint32_t *data) 1790 { 1791 uint_t generation; 1792 int status; 1793 1794 1795 ASSERT(ohci_hdl != NULL); 1796 ASSERT(data != NULL); 1797 TNF_PROBE_0_DEBUG(hci1394_ohci_csr_read_enter, HCI1394_TNF_HAL_STACK, 1798 ""); 1799 1800 /* 1801 * read the CSR register by doing a cswap with the same compare and 1802 * swap value. 1803 */ 1804 generation = hci1394_ohci_current_busgen(ohci_hdl); 1805 status = hci1394_ohci_csr_cswap(ohci_hdl, generation, offset, 0, 0, 1806 data); 1807 if (status != DDI_SUCCESS) { 1808 TNF_PROBE_0(hci1394_ohci_csr_read_csw_fail, 1809 HCI1394_TNF_HAL_ERROR, ""); 1810 TNF_PROBE_0_DEBUG(hci1394_ohci_csr_read_exit, 1811 HCI1394_TNF_HAL_STACK, ""); 1812 return (DDI_FAILURE); 1813 } 1814 1815 TNF_PROBE_0_DEBUG(hci1394_ohci_csr_read_exit, HCI1394_TNF_HAL_STACK, 1816 ""); 1817 1818 return (DDI_SUCCESS); 1819 } 1820 1821 1822 /* 1823 * hci1394_ohci_csr_cswap() 1824 * Perform a compare/swap on one of the HW implemented CSR registers. These 1825 * include bus_manager_id, bandwidth_available, channels_available_hi, and 1826 * channels_available_lo. Offset should be set to 1827 * OHCI_CSR_SEL_BUS_MGR_ID, OHCI_CSR_SEL_BANDWIDTH_AVAIL 1828 * OHCI_CSR_SEL_CHANS_AVAIL_HI, or OHCI_CSR_SEL_CHANS_AVAIL_LO. 1829 */ 1830 int 1831 hci1394_ohci_csr_cswap(hci1394_ohci_handle_t ohci_hdl, uint_t generation, 1832 uint_t offset, uint32_t compare, uint32_t swap, uint32_t *old) 1833 { 1834 int count; 1835 uint32_t ohci_reg; 1836 1837 1838 ASSERT(ohci_hdl != NULL); 1839 ASSERT(old != NULL); 1840 TNF_PROBE_0_DEBUG(hci1394_ohci_csr_cswap_enter, 1841 HCI1394_TNF_HAL_STACK, ""); 1842 1843 /* 1844 * Make sure we have not gotten a bus reset since this action was 1845 * started. 1846 */ 1847 if (generation != hci1394_ohci_current_busgen(ohci_hdl)) { 1848 TNF_PROBE_1(hci1394_ohci_invbusgen_fail, HCI1394_TNF_HAL_ERROR, 1849 "", tnf_string, errmsg, "Invalid Bus Generation"); 1850 TNF_PROBE_0_DEBUG(hci1394_ohci_csr_cswap_exit, 1851 HCI1394_TNF_HAL_STACK, ""); 1852 return (DDI_FAILURE); 1853 } 1854 1855 mutex_enter(&ohci_hdl->ohci_mutex); 1856 1857 /* init csrData and csrCompare */ 1858 ddi_put32(ohci_hdl->ohci_reg_handle, 1859 &ohci_hdl->ohci_regs->csr_data, swap); 1860 ddi_put32(ohci_hdl->ohci_reg_handle, 1861 &ohci_hdl->ohci_regs->csr_compare_data, compare); 1862 1863 /* start the compare swap */ 1864 ddi_put32(ohci_hdl->ohci_reg_handle, 1865 &ohci_hdl->ohci_regs->csr_ctrl, offset & OHCI_CSR_SELECT); 1866 1867 /* 1868 * The CSR access should be immediate. There in nothing that officially 1869 * states this so we will wait up to 2uS just in case before we timeout. 1870 * We actually perform a compare swap with both compare and swap set 1871 * to the same value. This will return the old value which is in 1872 * essence, a read. 1873 */ 1874 count = 0; 1875 while (count < 2) { 1876 /* See if the compare swap is done */ 1877 ohci_reg = ddi_get32(ohci_hdl->ohci_reg_handle, 1878 &ohci_hdl->ohci_regs->csr_ctrl); 1879 if ((ohci_reg & OHCI_CSR_DONE) != 0) { 1880 /* The compare swap is done, break out of the loop */ 1881 break; 1882 } 1883 /* 1884 * The compare swap has not completed yet, wait 1uS, increment 1885 * the count and try again 1886 */ 1887 drv_usecwait(1); 1888 count++; 1889 } 1890 1891 /* If we timed out, return an error */ 1892 if (count >= 2) { 1893 *old = 0; 1894 mutex_exit(&ohci_hdl->ohci_mutex); 1895 TNF_PROBE_0(hci1394_ohci_phy_csr_timeout_fail, 1896 HCI1394_TNF_HAL_ERROR, ""); 1897 TNF_PROBE_0_DEBUG(hci1394_ohci_csr_cswap_exit, 1898 HCI1394_TNF_HAL_STACK, ""); 1899 return (DDI_FAILURE); 1900 } 1901 1902 /* Copy the old data into the return parameter */ 1903 *old = ddi_get32(ohci_hdl->ohci_reg_handle, 1904 &ohci_hdl->ohci_regs->csr_data); 1905 1906 mutex_exit(&ohci_hdl->ohci_mutex); 1907 1908 /* 1909 * There is a race condition in the OpenHCI design here. After checking 1910 * the generation and before performing the cswap, we could get a bus 1911 * reset and incorrectly set something like the bus manager. This would 1912 * put us into a condition where we would not have a bus manager and 1913 * we would think there was one. If it is possible that this race 1914 * condition occured, we will reset the bus to clean things up. We only 1915 * care about this if the compare swap was successful. 1916 */ 1917 if (generation != hci1394_ohci_current_busgen(ohci_hdl)) { 1918 if (*old == compare) { 1919 (void) hci1394_ohci_bus_reset(ohci_hdl); 1920 TNF_PROBE_1(hci1394_ohci_invbusgen_fail, 1921 HCI1394_TNF_HAL_ERROR, "", tnf_string, errmsg, 1922 "Invalid Bus Generation"); 1923 TNF_PROBE_0_DEBUG(hci1394_ohci_csr_cswap_exit, 1924 HCI1394_TNF_HAL_STACK, ""); 1925 return (DDI_FAILURE); 1926 } 1927 } 1928 1929 TNF_PROBE_0_DEBUG(hci1394_ohci_csr_cswap_exit, HCI1394_TNF_HAL_STACK, 1930 ""); 1931 1932 return (DDI_SUCCESS); 1933 } 1934 1935 1936 /* 1937 * hci1394_ohci_contender_enable() 1938 * Set the contender bit in the PHY. This routine should only be called 1939 * if our PHY is 1394A compliant. (i.e. this routine should not be called 1940 * for a 1394-1995 PHY). 1941 */ 1942 int 1943 hci1394_ohci_contender_enable(hci1394_ohci_handle_t ohci_hdl) 1944 { 1945 int status; 1946 1947 1948 ASSERT(ohci_hdl != NULL); 1949 TNF_PROBE_0_DEBUG(hci1394_ohci_contender_enable_enter, 1950 HCI1394_TNF_HAL_STACK, ""); 1951 1952 /* 1953 * Make sure that phy is not a 1394-1995 phy. Those phy's do not have a 1954 * contender bit to set. 1955 */ 1956 if (ohci_hdl->ohci_phy == H1394_PHY_1995) { 1957 TNF_PROBE_0(hci1394_ohci_phy_type_fail, 1958 HCI1394_TNF_HAL_ERROR, ""); 1959 TNF_PROBE_0_DEBUG(hci1394_ohci_contender_enable_exit, 1960 HCI1394_TNF_HAL_STACK, ""); 1961 return (DDI_FAILURE); 1962 } 1963 1964 /* Set the Contender Bit */ 1965 status = hci1394_ohci_phy_set(ohci_hdl, 0x4, OHCI_PHY_CNTDR); 1966 if (status != DDI_SUCCESS) { 1967 TNF_PROBE_0(hci1394_ohci_phy_set_fail, 1968 HCI1394_TNF_HAL_ERROR, ""); 1969 TNF_PROBE_0_DEBUG(hci1394_ohci_contender_enable_exit, 1970 HCI1394_TNF_HAL_STACK, ""); 1971 return (DDI_FAILURE); 1972 } 1973 1974 TNF_PROBE_0_DEBUG(hci1394_ohci_contender_enable_exit, 1975 HCI1394_TNF_HAL_STACK, ""); 1976 1977 return (DDI_SUCCESS); 1978 } 1979 1980 1981 /* 1982 * hci1394_ohci_root_holdoff_enable() 1983 * Set the root holdoff bit in the PHY. Since there are race conditions when 1984 * writing to PHY register 1 (which can get updated from a PHY packet off the 1985 * bus), we cache this state until a "long" bus reset is issued. 1986 */ 1987 int 1988 hci1394_ohci_root_holdoff_enable(hci1394_ohci_handle_t ohci_hdl) 1989 { 1990 ASSERT(ohci_hdl != NULL); 1991 TNF_PROBE_0_DEBUG(hci1394_ohci_root_holdoff_enable_enter, 1992 HCI1394_TNF_HAL_STACK, ""); 1993 1994 ohci_hdl->ohci_set_root_holdoff = B_TRUE; 1995 1996 TNF_PROBE_0_DEBUG(hci1394_ohci_root_holdoff_enable_exit, 1997 HCI1394_TNF_HAL_STACK, ""); 1998 1999 return (DDI_SUCCESS); 2000 } 2001 2002 2003 /* 2004 * hci1394_ohci_gap_count_set() 2005 * Set the gap count in the PHY. Since there are race conditions when writing 2006 * to PHY register 1 (which can get updated from a PHY packet off the bus), 2007 * we cache this gap count until a "long" bus reset is issued. 2008 */ 2009 int 2010 hci1394_ohci_gap_count_set(hci1394_ohci_handle_t ohci_hdl, uint_t gap_count) 2011 { 2012 ASSERT(ohci_hdl != NULL); 2013 TNF_PROBE_0_DEBUG(hci1394_ohci_gap_count_set_enter, 2014 HCI1394_TNF_HAL_STACK, ""); 2015 2016 ohci_hdl->ohci_set_gap_count = B_TRUE; 2017 ohci_hdl->ohci_gap_count = gap_count & OHCI_PHY_MAX_GAP; 2018 2019 TNF_PROBE_0_DEBUG(hci1394_ohci_gap_count_set_exit, 2020 HCI1394_TNF_HAL_STACK, ""); 2021 2022 return (DDI_SUCCESS); 2023 } 2024 2025 2026 /* 2027 * hci1394_ohci_phy_filter_set() 2028 * Enable a node (or nodes) to perform transactions to our physical 2029 * memory. OpenHCI allows you to disable/enable physical requests on a node 2030 * per node basis. A physical request is basically a read/write to 1394 2031 * address space 0x0 - 0xFFFFFFFF. This address goes out to the IO MMU (in 2032 * the case of a SPARC machine). The HAL starts with all nodes unable to 2033 * read/write physical memory. The Services Layer will call down and enable 2034 * nodes via setting a physical filter bit for that given node. Since node 2035 * numbers change every bus reset, the services layer has to call down after 2036 * every bus reset to re-enable physical accesses. (NOTE: the hardware 2037 * automatically clears these bits. 2038 */ 2039 int 2040 hci1394_ohci_phy_filter_set(hci1394_ohci_handle_t ohci_hdl, uint64_t mask, 2041 uint_t generation) 2042 { 2043 uint32_t data; 2044 2045 2046 ASSERT(ohci_hdl != NULL); 2047 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_filter_set_enter, 2048 HCI1394_TNF_HAL_STACK, ""); 2049 2050 /* 2051 * Make sure we have not gotten a bus reset since this action was 2052 * started. 2053 */ 2054 if (generation != hci1394_ohci_current_busgen(ohci_hdl)) { 2055 TNF_PROBE_1(hci1394_ohci_invbusgen_fail, HCI1394_TNF_HAL_ERROR, 2056 "", tnf_string, errmsg, "Invalid Bus Generation"); 2057 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_filter_set_exit, 2058 HCI1394_TNF_HAL_STACK, ""); 2059 return (DDI_FAILURE); 2060 } 2061 2062 data = (uint32_t)((mask >> 32) & 0xFFFFFFFF); 2063 ddi_put32(ohci_hdl->ohci_reg_handle, 2064 &ohci_hdl->ohci_regs->phys_req_filterhi_set, data); 2065 data = (uint32_t)(mask & 0xFFFFFFFF); 2066 ddi_put32(ohci_hdl->ohci_reg_handle, 2067 &ohci_hdl->ohci_regs->phys_req_filterlo_set, data); 2068 2069 /* 2070 * There is a race condition in the OpenHCI design here. After checking 2071 * the generation and before setting the physical filter bits, we could 2072 * get a bus reset and incorrectly set the physical filter bits. If it 2073 * is possible that this race condition occured, we will reset the bus 2074 * to clean things up. 2075 */ 2076 if (generation != hci1394_ohci_current_busgen(ohci_hdl)) { 2077 (void) hci1394_ohci_bus_reset(ohci_hdl); 2078 TNF_PROBE_1(hci1394_ohci_filterrace_fail, HCI1394_TNF_HAL_ERROR, 2079 "", tnf_string, errmsg, "Invalid Bus Generation"); 2080 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_filter_set_exit, 2081 HCI1394_TNF_HAL_STACK, ""); 2082 return (DDI_SUCCESS); 2083 } 2084 2085 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_filter_set_exit, 2086 HCI1394_TNF_HAL_STACK, ""); 2087 2088 return (DDI_SUCCESS); 2089 } 2090 2091 2092 /* 2093 * hci1394_ohci_phy_filter_clr() 2094 * Disable a node (or nodes) from performing transactions to our physical 2095 * memory. See hci1394_ohci_phy_filter_set() above for more info. 2096 */ 2097 int 2098 hci1394_ohci_phy_filter_clr(hci1394_ohci_handle_t ohci_hdl, 2099 uint64_t mask, uint_t generation) 2100 { 2101 uint32_t data; 2102 2103 2104 ASSERT(ohci_hdl != NULL); 2105 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_filter_clr_enter, 2106 HCI1394_TNF_HAL_STACK, ""); 2107 2108 /* 2109 * Make sure we have not gotten a bus reset since this action was 2110 * started. 2111 */ 2112 if (generation != hci1394_ohci_current_busgen(ohci_hdl)) { 2113 TNF_PROBE_1(hci1394_ohci_invbusgen_fail, HCI1394_TNF_HAL_ERROR, 2114 "", tnf_string, errmsg, "Invalid Bus Generation"); 2115 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_filter_clr_exit, 2116 HCI1394_TNF_HAL_STACK, ""); 2117 return (DDI_FAILURE); 2118 } 2119 2120 data = (uint32_t)((mask >> 32) & 0xFFFFFFFF); 2121 ddi_put32(ohci_hdl->ohci_reg_handle, 2122 &ohci_hdl->ohci_regs->phys_req_filterhi_clr, data); 2123 data = (uint32_t)(mask & 0xFFFFFFFF); 2124 ddi_put32(ohci_hdl->ohci_reg_handle, 2125 &ohci_hdl->ohci_regs->phys_req_filterlo_clr, data); 2126 2127 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_filter_clr_exit, 2128 HCI1394_TNF_HAL_STACK, ""); 2129 2130 return (DDI_SUCCESS); 2131 } 2132 2133 2134 /* 2135 * hci1394_ohci_bus_reset_short() 2136 * Perform a 1394A short bus reset. This function should only be called 2137 * on an adapter with a 1394A PHY (or later). 2138 */ 2139 int 2140 hci1394_ohci_bus_reset_short(hci1394_ohci_handle_t ohci_hdl) 2141 { 2142 int status; 2143 2144 ASSERT(ohci_hdl != NULL); 2145 TNF_PROBE_0_DEBUG(hci1394_ohci_bus_reset_short_enter, 2146 HCI1394_TNF_HAL_STACK, ""); 2147 2148 /* 2149 * Make sure that phy is not a 1394-1995 phy. Those phy's do not have a 2150 * contender bit to set. 2151 */ 2152 if (ohci_hdl->ohci_phy == H1394_PHY_1995) { 2153 TNF_PROBE_0(hci1394_ohci_brs_phy_fail, 2154 HCI1394_TNF_HAL_ERROR, ""); 2155 TNF_PROBE_0_DEBUG(hci1394_ohci_bus_reset_short_exit, 2156 HCI1394_TNF_HAL_STACK, ""); 2157 return (DDI_FAILURE); 2158 } 2159 2160 /* Initiate the short bus reset */ 2161 status = hci1394_ohci_phy_set(ohci_hdl, 0x5, OHCI_PHY_ISBR); 2162 if (status != DDI_SUCCESS) { 2163 TNF_PROBE_0(hci1394_ohci_phy_set_fail, 2164 HCI1394_TNF_HAL_ERROR, ""); 2165 TNF_PROBE_0_DEBUG(hci1394_ohci_bus_reset_short_exit, 2166 HCI1394_TNF_HAL_STACK, ""); 2167 return (DDI_FAILURE); 2168 } 2169 2170 TNF_PROBE_0_DEBUG(hci1394_ohci_bus_reset_short_exit, 2171 HCI1394_TNF_HAL_STACK, ""); 2172 2173 return (status); 2174 } 2175 2176 2177 /* 2178 * hci1394_ohci_cfgrom_update() 2179 * Update the config rom with the provided contents. The config rom is 2180 * provided as a byte stream which is multiple of 4 bytes large. The 2181 * size is passed as a quadlet (4 bytes) count. The entire contents 2182 * of the config rom is updated at once. We do not provide a partial 2183 * update interface. 2184 */ 2185 void 2186 hci1394_ohci_cfgrom_update(hci1394_ohci_handle_t ohci_hdl, void *local_buf, 2187 uint_t quadlet_count) 2188 { 2189 uint32_t *data; 2190 2191 2192 ASSERT(ohci_hdl != NULL); 2193 ASSERT(local_buf != NULL); 2194 TNF_PROBE_0_DEBUG(hci1394_ohci_cfgrom_update_enter, 2195 HCI1394_TNF_HAL_STACK, ""); 2196 2197 data = (uint32_t *)local_buf; 2198 2199 /* zero out the config ROM header to start */ 2200 ddi_put32(ohci_hdl->ohci_reg_handle, 2201 &ohci_hdl->ohci_regs->config_rom_hdr, 0); 2202 2203 /* copy Services Layer buffer into config rom buffer */ 2204 ddi_rep_put8(ohci_hdl->ohci_cfgrom.bi_handle, local_buf, 2205 (uint8_t *)ohci_hdl->ohci_cfgrom.bi_kaddr, quadlet_count << 2, 2206 DDI_DEV_AUTOINCR); 2207 2208 (void) ddi_dma_sync(ohci_hdl->ohci_cfgrom.bi_dma_handle, 0, 2209 quadlet_count << 2, DDI_DMA_SYNC_FORDEV); 2210 2211 /* 2212 * setup OHCI bus options and config rom hdr registers. We need to swap 2213 * the config rom header and bus options on an X86 machine since the 2214 * data is provided to us as a byte stream and the OHCI registers expect 2215 * a big endian 32-bit number. 2216 */ 2217 ddi_put32(ohci_hdl->ohci_reg_handle, 2218 &ohci_hdl->ohci_regs->bus_options, OHCI_SWAP32(data[2])); 2219 ddi_put32(ohci_hdl->ohci_reg_handle, 2220 &ohci_hdl->ohci_regs->config_rom_hdr, OHCI_SWAP32(data[0])); 2221 2222 TNF_PROBE_0_DEBUG(hci1394_ohci_cfgrom_update_exit, 2223 HCI1394_TNF_HAL_STACK, ""); 2224 } 2225 2226 2227 /* 2228 * hci1394_ohci_nodeid_get() 2229 * Return our current nodeid (bus #/Node #) 2230 */ 2231 void 2232 hci1394_ohci_nodeid_get(hci1394_ohci_handle_t ohci_hdl, uint_t *nodeid) 2233 { 2234 uint32_t reg; 2235 2236 ASSERT(ohci_hdl != NULL); 2237 ASSERT(nodeid != NULL); 2238 TNF_PROBE_0_DEBUG(hci1394_ohci_nodeid_get_enter, HCI1394_TNF_HAL_STACK, 2239 ""); 2240 reg = ddi_get32(ohci_hdl->ohci_reg_handle, 2241 &ohci_hdl->ohci_regs->node_id); 2242 *nodeid = (reg & 0xFFFF) << 16; 2243 TNF_PROBE_0_DEBUG(hci1394_ohci_nodeid_get_exit, HCI1394_TNF_HAL_STACK, 2244 ""); 2245 } 2246 2247 2248 /* 2249 * hci1394_ohci_nodeid_set() 2250 * Set our current nodeid (bus #/Node #). This actually sets our bus number. 2251 * Our node number cannot be set by software. This is usually trigered via 2252 * a write to the CSR NODEIDS register. 2253 */ 2254 void 2255 hci1394_ohci_nodeid_set(hci1394_ohci_handle_t ohci_hdl, uint_t nodeid) 2256 { 2257 uint32_t reg; 2258 2259 ASSERT(ohci_hdl != NULL); 2260 TNF_PROBE_0_DEBUG(hci1394_ohci_nodeid_set_enter, 2261 HCI1394_TNF_HAL_STACK, ""); 2262 2263 reg = ((nodeid & 0xFFC00000) >> 16); 2264 ddi_put32(ohci_hdl->ohci_reg_handle, 2265 &ohci_hdl->ohci_regs->node_id, reg); 2266 2267 TNF_PROBE_0_DEBUG(hci1394_ohci_nodeid_set_exit, 2268 HCI1394_TNF_HAL_STACK, ""); 2269 } 2270 2271 2272 /* 2273 * hci1394_ohci_nodeid_info() 2274 * Return our current nodeid (bus #/Node #). This also returns whether or 2275 * not our nodeid error bit is set. This is useful in determining if the 2276 * bus reset completed without errors in the selfid complete interrupt 2277 * processing. 2278 */ 2279 void 2280 hci1394_ohci_nodeid_info(hci1394_ohci_handle_t ohci_hdl, uint_t *nodeid, 2281 boolean_t *error) 2282 { 2283 uint32_t reg; 2284 2285 ASSERT(ohci_hdl != NULL); 2286 ASSERT(nodeid != NULL); 2287 TNF_PROBE_0_DEBUG(hci1394_ohci_nodeid_info_enter, 2288 HCI1394_TNF_HAL_STACK, ""); 2289 2290 reg = ddi_get32(ohci_hdl->ohci_reg_handle, 2291 &ohci_hdl->ohci_regs->node_id); 2292 *nodeid = reg & 0xFFFF; 2293 if ((reg & OHCI_NDID_IDVALID) == 0) { 2294 *error = B_TRUE; 2295 } else { 2296 *error = B_FALSE; 2297 } 2298 2299 TNF_PROBE_0_DEBUG(hci1394_ohci_nodeid_info_exit, 2300 HCI1394_TNF_HAL_STACK, ""); 2301 } 2302 2303 2304 /* 2305 * hci1394_ohci_cycletime_get() 2306 * Return the current cycle time 2307 */ 2308 void 2309 hci1394_ohci_cycletime_get(hci1394_ohci_handle_t ohci_hdl, 2310 uint32_t *cycle_time) 2311 { 2312 ASSERT(ohci_hdl != NULL); 2313 ASSERT(cycle_time != NULL); 2314 TNF_PROBE_0_DEBUG(hci1394_ohci_cycletime_get_enter, 2315 HCI1394_TNF_HAL_STACK, ""); 2316 *cycle_time = ddi_get32(ohci_hdl->ohci_reg_handle, 2317 &ohci_hdl->ohci_regs->isoch_cycle_timer); 2318 TNF_PROBE_0_DEBUG(hci1394_ohci_cycletime_get_exit, 2319 HCI1394_TNF_HAL_STACK, ""); 2320 } 2321 2322 2323 /* 2324 * hci1394_ohci_cycletime_get() 2325 * Set the cycle time 2326 */ 2327 void 2328 hci1394_ohci_cycletime_set(hci1394_ohci_handle_t ohci_hdl, 2329 uint32_t cycle_time) 2330 { 2331 ASSERT(ohci_hdl != NULL); 2332 TNF_PROBE_0_DEBUG(hci1394_ohci_cycletime_set_enter, 2333 HCI1394_TNF_HAL_STACK, ""); 2334 ddi_put32(ohci_hdl->ohci_reg_handle, 2335 &ohci_hdl->ohci_regs->isoch_cycle_timer, cycle_time); 2336 TNF_PROBE_0_DEBUG(hci1394_ohci_cycletime_set_exit, 2337 HCI1394_TNF_HAL_STACK, ""); 2338 } 2339 2340 2341 /* 2342 * hci1394_ohci_bustime_get() 2343 * Return the current bus time. 2344 */ 2345 void 2346 hci1394_ohci_bustime_get(hci1394_ohci_handle_t ohci_hdl, uint32_t *bus_time) 2347 { 2348 uint32_t bus_time1; 2349 uint32_t bus_time2; 2350 uint32_t cycle_time; 2351 2352 2353 ASSERT(ohci_hdl != NULL); 2354 ASSERT(bus_time != NULL); 2355 TNF_PROBE_0_DEBUG(hci1394_ohci_bustime_get_enter, 2356 HCI1394_TNF_HAL_STACK, ""); 2357 2358 /* 2359 * The bus time is composed of a portion of the cycle time and the 2360 * cycle time rollover count (ohci_bustime_count). There is a race 2361 * condition where we read the rollover count and then the cycle 2362 * timer rolls over. This is the reason for the double read of the 2363 * rollover count. 2364 */ 2365 do { 2366 bus_time1 = ohci_hdl->ohci_bustime_count; 2367 cycle_time = ddi_get32(ohci_hdl->ohci_reg_handle, 2368 &ohci_hdl->ohci_regs->isoch_cycle_timer); 2369 bus_time2 = ohci_hdl->ohci_bustime_count; 2370 } while (bus_time1 != bus_time2); 2371 2372 *bus_time = (bus_time2 << 7) | (cycle_time >> 25); 2373 2374 TNF_PROBE_0_DEBUG(hci1394_ohci_bustime_get_exit, 2375 HCI1394_TNF_HAL_STACK, ""); 2376 } 2377 2378 2379 /* 2380 * hci1394_ohci_bustime_set() 2381 * Set the cycle timer rollover portion of the bus time. 2382 */ 2383 void 2384 hci1394_ohci_bustime_set(hci1394_ohci_handle_t ohci_hdl, uint32_t bus_time) 2385 { 2386 ASSERT(ohci_hdl != NULL); 2387 TNF_PROBE_0_DEBUG(hci1394_ohci_bustime_set_enter, 2388 HCI1394_TNF_HAL_STACK, ""); 2389 2390 /* 2391 * we will start with the cycle 64 seconds interrupt disabled. If this 2392 * is the first write to bus time, enable the interrupt. 2393 */ 2394 if (ohci_hdl->ohci_bustime_enabled == B_FALSE) { 2395 ohci_hdl->ohci_bustime_enabled = B_TRUE; 2396 /* Clear the cycle64Seconds interrupt then enable it */ 2397 hci1394_ohci_intr_clear(ohci_hdl, OHCI_INTR_CYC_64_SECS); 2398 hci1394_ohci_intr_enable(ohci_hdl, OHCI_INTR_CYC_64_SECS); 2399 } 2400 ohci_hdl->ohci_bustime_count = (bus_time >> 7); 2401 2402 TNF_PROBE_0_DEBUG(hci1394_ohci_bustime_set_exit, 2403 HCI1394_TNF_HAL_STACK, ""); 2404 } 2405 2406 2407 /* 2408 * hci1394_ohci_atreq_retries_get() 2409 * Get the number of atreq retries we will perform. 2410 */ 2411 void 2412 hci1394_ohci_atreq_retries_get(hci1394_ohci_handle_t ohci_hdl, 2413 uint_t *atreq_retries) 2414 { 2415 uint32_t reg; 2416 2417 ASSERT(ohci_hdl != NULL); 2418 ASSERT(atreq_retries != NULL); 2419 TNF_PROBE_0_DEBUG(hci1394_ohci_atreq_retries_get_enter, 2420 HCI1394_TNF_HAL_STACK, ""); 2421 reg = ddi_get32(ohci_hdl->ohci_reg_handle, 2422 &ohci_hdl->ohci_regs->at_retries); 2423 *atreq_retries = reg & OHCI_RET_MAX_ATREQ_MASK; 2424 TNF_PROBE_0_DEBUG(hci1394_ohci_atreq_retries_get_exit, 2425 HCI1394_TNF_HAL_STACK, ""); 2426 } 2427 2428 2429 /* 2430 * hci1394_ohci_atreq_retries_get() 2431 * Set the number of atreq retries we will perform. 2432 */ 2433 void 2434 hci1394_ohci_atreq_retries_set(hci1394_ohci_handle_t ohci_hdl, 2435 uint_t atreq_retries) 2436 { 2437 uint32_t reg; 2438 2439 2440 ASSERT(ohci_hdl != NULL); 2441 TNF_PROBE_0_DEBUG(hci1394_ohci_atreq_retries_set_enter, 2442 HCI1394_TNF_HAL_STACK, ""); 2443 2444 mutex_enter(&ohci_hdl->ohci_mutex); 2445 reg = ddi_get32(ohci_hdl->ohci_reg_handle, 2446 &ohci_hdl->ohci_regs->at_retries); 2447 reg = reg & ~OHCI_RET_MAX_ATREQ_MASK; 2448 reg = reg | (atreq_retries & OHCI_RET_MAX_ATREQ_MASK); 2449 ddi_put32(ohci_hdl->ohci_reg_handle, 2450 &ohci_hdl->ohci_regs->at_retries, reg); 2451 mutex_exit(&ohci_hdl->ohci_mutex); 2452 2453 TNF_PROBE_0_DEBUG(hci1394_ohci_atreq_retries_set_exit, 2454 HCI1394_TNF_HAL_STACK, ""); 2455 } 2456 2457 2458 /* 2459 * hci1394_ohci_isr_cycle64seconds() 2460 * Interrupt handler for the cycle64seconds interrupt. 2461 */ 2462 void 2463 hci1394_ohci_isr_cycle64seconds(hci1394_ohci_handle_t ohci_hdl) 2464 { 2465 uint32_t cycle_time; 2466 2467 ASSERT(ohci_hdl != NULL); 2468 TNF_PROBE_0_DEBUG(hci1394_ohci_isr_cycle64seconds_enter, 2469 HCI1394_TNF_HAL_STACK, ""); 2470 2471 hci1394_ohci_intr_clear(ohci_hdl, OHCI_INTR_CYC_64_SECS); 2472 cycle_time = ddi_get32(ohci_hdl->ohci_reg_handle, 2473 &ohci_hdl->ohci_regs->isoch_cycle_timer); 2474 2475 /* 2476 * cycle64second interrupts when the MSBit in the cycle timer changes 2477 * state. We only care about rollover so we will increment only when 2478 * the MSBit is set to 0. 2479 */ 2480 if ((cycle_time & 0x80000000) == 0) { 2481 ohci_hdl->ohci_bustime_count++; 2482 } 2483 2484 TNF_PROBE_0_DEBUG(hci1394_ohci_isr_cycle64seconds_exit, 2485 HCI1394_TNF_HAL_STACK, ""); 2486 } 2487 2488 2489 /* 2490 * hci1394_ohci_isr_phy() 2491 * Interrupt handler for a PHY event 2492 */ 2493 void 2494 hci1394_ohci_isr_phy(hci1394_ohci_handle_t ohci_hdl) 2495 { 2496 uint_t phy_status; 2497 int status; 2498 2499 2500 ASSERT(ohci_hdl != NULL); 2501 TNF_PROBE_0_DEBUG(hci1394_ohci_isr_phy_enter, 2502 HCI1394_TNF_HAL_STACK, ""); 2503 2504 /* clear the interrupt */ 2505 hci1394_ohci_intr_clear(ohci_hdl, OHCI_INTR_PHY); 2506 2507 /* increment the statistics count */ 2508 ohci_hdl->ohci_drvinfo->di_stats.st_phy_isr++; 2509 2510 /* 2511 * If the PHY is a 1995 phy, just return since there are no status bits 2512 * to read. 2513 */ 2514 if (ohci_hdl->ohci_phy == H1394_PHY_1995) { 2515 TNF_PROBE_0(hci1394_ohci_phy_isr_1995, 2516 HCI1394_TNF_HAL_ERROR, ""); 2517 TNF_PROBE_0_DEBUG(hci1394_ohci_isr_phy_exit, 2518 HCI1394_TNF_HAL_STACK, ""); 2519 return; 2520 } 2521 2522 /* See why we got this interrupt */ 2523 status = hci1394_ohci_phy_read(ohci_hdl, 5, &phy_status); 2524 if (status != DDI_SUCCESS) { 2525 TNF_PROBE_0(hci1394_ohci_phy_read_failed, 2526 HCI1394_TNF_HAL_ERROR, ""); 2527 TNF_PROBE_0_DEBUG(hci1394_ohci_isr_phy_exit, 2528 HCI1394_TNF_HAL_STACK, ""); 2529 return; 2530 } 2531 2532 if (phy_status & OHCI_PHY_LOOP_ERR) { 2533 ohci_hdl->ohci_drvinfo->di_stats.st_phy_loop_err++; 2534 cmn_err(CE_NOTE, "hci1394(%d): ERROR - bus loop detected", 2535 ohci_hdl->ohci_drvinfo->di_instance); 2536 TNF_PROBE_0(hci1394_ohci_phy_isr_loop, HCI1394_TNF_HAL, ""); 2537 } 2538 if (phy_status & OHCI_PHY_PWRFAIL_ERR) { 2539 ohci_hdl->ohci_drvinfo->di_stats.st_phy_pwrfail_err++; 2540 TNF_PROBE_0(hci1394_ohci_phy_isr_pwr, HCI1394_TNF_HAL, ""); 2541 } 2542 if (phy_status & OHCI_PHY_TIMEOUT_ERR) { 2543 ohci_hdl->ohci_drvinfo->di_stats.st_phy_timeout_err++; 2544 TNF_PROBE_0(hci1394_ohci_phy_isr_tmout, HCI1394_TNF_HAL, ""); 2545 } 2546 if (phy_status & OHCI_PHY_PORTEVT_ERR) { 2547 ohci_hdl->ohci_drvinfo->di_stats.st_phy_portevt_err++; 2548 TNF_PROBE_0(hci1394_ohci_phy_isr_pevt, HCI1394_TNF_HAL, ""); 2549 } 2550 2551 /* clear any set status bits */ 2552 status = hci1394_ohci_phy_write(ohci_hdl, 5, phy_status); 2553 if (status != DDI_SUCCESS) { 2554 TNF_PROBE_0(hci1394_ohci_phy_write_failed, 2555 HCI1394_TNF_HAL_ERROR, ""); 2556 TNF_PROBE_0_DEBUG(hci1394_ohci_isr_phy_exit, 2557 HCI1394_TNF_HAL_STACK, ""); 2558 return; 2559 } 2560 2561 /* 2562 * Disable the PHY interrupt. We are getting stuck in this ISR in 2563 * certain PHY implementations so we will disable the interrupt until 2564 * we see a selfid complete. 2565 */ 2566 hci1394_ohci_intr_disable(ohci_hdl, OHCI_INTR_PHY); 2567 2568 TNF_PROBE_0_DEBUG(hci1394_ohci_isr_phy_exit, 2569 HCI1394_TNF_HAL_STACK, ""); 2570 } 2571 2572 2573 /* 2574 * hci1394_ohci_root_check 2575 * Returns status about if we are currently the root node on the 1394 bus. 2576 * returns B_TRUE if we are the root, B_FALSE if we are not the root. 2577 */ 2578 boolean_t 2579 hci1394_ohci_root_check(hci1394_ohci_handle_t ohci_hdl) 2580 { 2581 uint32_t reg; 2582 int status; 2583 2584 ASSERT(ohci_hdl != NULL); 2585 TNF_PROBE_0_DEBUG(hci1394_ohci_root_check_enter, HCI1394_TNF_HAL_STACK, 2586 ""); 2587 reg = ddi_get32(ohci_hdl->ohci_reg_handle, 2588 &ohci_hdl->ohci_regs->node_id); 2589 if ((reg & OHCI_REG_NODEID_ROOT) && (reg & OHCI_NDID_IDVALID)) { 2590 status = B_TRUE; 2591 } else { 2592 status = B_FALSE; 2593 } 2594 TNF_PROBE_0_DEBUG(hci1394_ohci_root_check_exit, HCI1394_TNF_HAL_STACK, 2595 ""); 2596 2597 return (status); 2598 } 2599 2600 2601 /* 2602 * hci1394_ohci_cmc_check() 2603 * Returns status about if we are cycle master capable. Returns 2604 * B_TRUE if we are the cycle master capable, B_FALSE if we are not the cycle 2605 * master capable. 2606 */ 2607 boolean_t 2608 hci1394_ohci_cmc_check(hci1394_ohci_handle_t ohci_hdl) 2609 { 2610 uint32_t reg; 2611 int status; 2612 2613 ASSERT(ohci_hdl != NULL); 2614 TNF_PROBE_0_DEBUG(hci1394_ohci_cmc_check_enter, HCI1394_TNF_HAL_STACK, 2615 ""); 2616 reg = ddi_get32(ohci_hdl->ohci_reg_handle, 2617 &ohci_hdl->ohci_regs->bus_options); 2618 if (reg & OHCI_REG_BUSOPTIONS_CMC) { 2619 status = B_TRUE; 2620 } else { 2621 status = B_FALSE; 2622 } 2623 TNF_PROBE_0_DEBUG(hci1394_ohci_cmc_check_exit, HCI1394_TNF_HAL_STACK, 2624 ""); 2625 2626 return (status); 2627 } 2628 2629 2630 /* 2631 * hci1394_ohci_cycle_master_enable() 2632 * Enables us to be cycle master. If we are root, we will start generating 2633 * cycle start packets. 2634 */ 2635 void 2636 hci1394_ohci_cycle_master_enable(hci1394_ohci_handle_t ohci_hdl) 2637 { 2638 ASSERT(ohci_hdl != NULL); 2639 TNF_PROBE_0_DEBUG(hci1394_ohci_cycle_master_enable_enter, 2640 HCI1394_TNF_HAL_STACK, ""); 2641 2642 /* First make sure that cycleTooLong is clear */ 2643 ddi_put32(ohci_hdl->ohci_reg_handle, 2644 &ohci_hdl->ohci_regs->intr_event_clr, OHCI_INTR_CYC_TOO_LONG); 2645 2646 /* Enable Cycle Master */ 2647 ddi_put32(ohci_hdl->ohci_reg_handle, 2648 &ohci_hdl->ohci_regs->link_ctrl_set, OHCI_LC_CYC_MAST); 2649 2650 TNF_PROBE_0_DEBUG(hci1394_ohci_cycle_master_enable_exit, 2651 HCI1394_TNF_HAL_STACK, ""); 2652 } 2653 2654 2655 /* 2656 * hci1394_ohci_cycle_master_disable() 2657 * Disabled us from being cycle master. If we are root, we will stop 2658 * generating cycle start packets. 2659 */ 2660 void 2661 hci1394_ohci_cycle_master_disable(hci1394_ohci_handle_t ohci_hdl) 2662 { 2663 ASSERT(ohci_hdl != NULL); 2664 TNF_PROBE_0_DEBUG(hci1394_ohci_cycle_master_disable_enter, 2665 HCI1394_TNF_HAL_STACK, ""); 2666 2667 /* disable cycle master */ 2668 ddi_put32(ohci_hdl->ohci_reg_handle, 2669 &ohci_hdl->ohci_regs->link_ctrl_clr, OHCI_LC_CYC_MAST); 2670 2671 TNF_PROBE_0_DEBUG(hci1394_ohci_cycle_master_disable_exit, 2672 HCI1394_TNF_HAL_STACK, ""); 2673 } 2674 2675 2676 /* 2677 * hci1394_ohci_resume() 2678 * Re-initialize the openHCI HW during a resume. (after a power suspend) 2679 */ 2680 int 2681 hci1394_ohci_resume(hci1394_ohci_handle_t ohci_hdl) 2682 { 2683 uint32_t quadlet; 2684 int status; 2685 2686 2687 ASSERT(ohci_hdl != NULL); 2688 TNF_PROBE_0_DEBUG(hci1394_ohci_resume_enter, 2689 HCI1394_TNF_HAL_STACK, ""); 2690 2691 /* Re-initialize the OpenHCI chip */ 2692 status = hci1394_ohci_chip_init(ohci_hdl); 2693 if (status != DDI_SUCCESS) { 2694 TNF_PROBE_0(hci1394_ohci_chip_init_fail, HCI1394_TNF_HAL_ERROR, 2695 ""); 2696 TNF_PROBE_0_DEBUG(hci1394_ohci_resume_exit, 2697 HCI1394_TNF_HAL_STACK, ""); 2698 return (DDI_FAILURE); 2699 } 2700 2701 /* Re-initialize the PHY */ 2702 status = hci1394_ohci_phy_resume(ohci_hdl); 2703 if (status != DDI_SUCCESS) { 2704 TNF_PROBE_0(hci1394_ohci_phy_resume_fail, 2705 HCI1394_TNF_HAL_ERROR, ""); 2706 TNF_PROBE_0_DEBUG(hci1394_ohci_resume_exit, 2707 HCI1394_TNF_HAL_STACK, ""); 2708 return (DDI_FAILURE); 2709 } 2710 2711 /* Re-initialize any 1394A features we are using */ 2712 status = hci1394_ohci_1394a_resume(ohci_hdl); 2713 if (status != DDI_SUCCESS) { 2714 TNF_PROBE_0(hci1394_ohci_1394a_resume_fail, 2715 HCI1394_TNF_HAL_ERROR, ""); 2716 TNF_PROBE_0_DEBUG(hci1394_ohci_resume_exit, 2717 HCI1394_TNF_HAL_STACK, ""); 2718 return (DDI_FAILURE); 2719 } 2720 2721 /* Tell OpenHCI where the Config ROM buffer is */ 2722 ddi_put32(ohci_hdl->ohci_reg_handle, 2723 &ohci_hdl->ohci_regs->config_rom_maplo, 2724 (uint32_t)ohci_hdl->ohci_cfgrom.bi_cookie.dmac_address); 2725 2726 /* Tell OpenHCI where the SelfId buffer is */ 2727 ddi_put32(ohci_hdl->ohci_reg_handle, 2728 &ohci_hdl->ohci_regs->self_id_buflo, 2729 (uint32_t)ohci_hdl->ohci_selfid.bi_cookie.dmac_address); 2730 2731 /* Enable selfid DMA engine */ 2732 hci1394_ohci_selfid_enable(ohci_hdl); 2733 2734 /* 2735 * re-setup OHCI bus options and config rom hdr registers. We need to 2736 * read from the config rom using ddi_rep_get8 since it is stored as 2737 * a byte stream. We need to swap the config rom header and bus options 2738 * on an X86 machine since the data is a byte stream and the OHCI 2739 * registers expect a big endian 32-bit number. 2740 */ 2741 ddi_rep_get8(ohci_hdl->ohci_cfgrom.bi_handle, (uint8_t *)&quadlet, 2742 &((uint8_t *)ohci_hdl->ohci_cfgrom.bi_kaddr)[8], 4, 2743 DDI_DEV_AUTOINCR); 2744 ddi_put32(ohci_hdl->ohci_reg_handle, 2745 &ohci_hdl->ohci_regs->bus_options, OHCI_SWAP32(quadlet)); 2746 ddi_rep_get8(ohci_hdl->ohci_cfgrom.bi_handle, (uint8_t *)&quadlet, 2747 &((uint8_t *)ohci_hdl->ohci_cfgrom.bi_kaddr)[0], 4, 2748 DDI_DEV_AUTOINCR); 2749 ddi_put32(ohci_hdl->ohci_reg_handle, 2750 &ohci_hdl->ohci_regs->config_rom_hdr, OHCI_SWAP32(quadlet)); 2751 2752 TNF_PROBE_0_DEBUG(hci1394_ohci_resume_exit, 2753 HCI1394_TNF_HAL_STACK, ""); 2754 return (DDI_SUCCESS); 2755 } 2756 2757 2758 /* 2759 * hci1394_ohci_selfid_init() 2760 * Initialize the selfid buffer 2761 */ 2762 static int 2763 hci1394_ohci_selfid_init(hci1394_ohci_handle_t ohci_hdl) 2764 { 2765 hci1394_buf_parms_t parms; 2766 int status; 2767 2768 2769 ASSERT(ohci_hdl != NULL); 2770 TNF_PROBE_0_DEBUG(hci1394_init_selfid_enter, HCI1394_TNF_HAL_STACK, ""); 2771 2772 /* 2773 * Setup for 2K buffer, aligned on a 2Kbyte address boundary. Make sure 2774 * that the buffer is not broken up into multiple cookies. OpenHCI can 2775 * only handle one address for the selfid buffer location. 2776 */ 2777 parms.bp_length = 2048; 2778 parms.bp_max_cookies = 1; 2779 parms.bp_alignment = 2048; 2780 status = hci1394_buf_alloc(ohci_hdl->ohci_drvinfo, &parms, 2781 &ohci_hdl->ohci_selfid, &ohci_hdl->ohci_selfid_handle); 2782 if (status != DDI_SUCCESS) { 2783 TNF_PROBE_0(hci1394_buf_alloc_fail, HCI1394_TNF_HAL_ERROR, ""); 2784 TNF_PROBE_0_DEBUG(hci1394_init_selfid_exit, 2785 HCI1394_TNF_HAL_STACK, ""); 2786 return (DDI_FAILURE); 2787 } 2788 2789 /* Tell OpenHCI where the buffer is */ 2790 ddi_put32(ohci_hdl->ohci_reg_handle, 2791 &ohci_hdl->ohci_regs->self_id_buflo, 2792 (uint32_t)ohci_hdl->ohci_selfid.bi_cookie.dmac_address); 2793 2794 /* Enable selfid DMA engine */ 2795 hci1394_ohci_selfid_enable(ohci_hdl); 2796 2797 TNF_PROBE_0_DEBUG(hci1394_init_selfid_exit, HCI1394_TNF_HAL_STACK, ""); 2798 2799 return (DDI_SUCCESS); 2800 } 2801 2802 2803 /* 2804 * hci1394_ohci_selfid_enable() 2805 * Allow selfid packets to be placed into the selfid buffer. This should be 2806 * called after the selfid buffer address has been setup in the HW. 2807 */ 2808 void 2809 hci1394_ohci_selfid_enable(hci1394_ohci_handle_t ohci_hdl) 2810 { 2811 ASSERT(ohci_hdl != NULL); 2812 TNF_PROBE_0_DEBUG(hci1394_ohci_selfid_enable_enter, 2813 HCI1394_TNF_HAL_STACK, ""); 2814 2815 /* 2816 * Allow selfid packets to be received. This should be called during 2817 * driver attach after the selfid buffer address has been initialized. 2818 * 2819 * Link Control Register 2820 * rscSelfId = 1 <= bit 9 2821 */ 2822 ddi_put32(ohci_hdl->ohci_reg_handle, 2823 &ohci_hdl->ohci_regs->link_ctrl_set, OHCI_LC_RCV_SELF); 2824 2825 TNF_PROBE_0_DEBUG(hci1394_ohci_selfid_enable_exit, 2826 HCI1394_TNF_HAL_STACK, ""); 2827 } 2828 2829 2830 /* 2831 * hci1394_ohci_selfid_read() 2832 * Read a word out of the selfid buffer. 2833 */ 2834 void 2835 hci1394_ohci_selfid_read(hci1394_ohci_handle_t ohci_hdl, uint_t offset, 2836 uint32_t *data) 2837 { 2838 ASSERT(ohci_hdl != NULL); 2839 ASSERT(data != NULL); 2840 TNF_PROBE_0_DEBUG(hci1394_ohci_selfid_read_enter, 2841 HCI1394_TNF_HAL_STACK, ""); 2842 *data = ddi_get32(ohci_hdl->ohci_selfid.bi_handle, 2843 &((uint32_t *)ohci_hdl->ohci_selfid.bi_kaddr)[offset]); 2844 TNF_PROBE_0_DEBUG(hci1394_ohci_selfid_read_exit, 2845 HCI1394_TNF_HAL_STACK, ""); 2846 } 2847 2848 2849 /* 2850 * hci1394_ohci_selfid_info() 2851 * Return the current bus generation, the number of bytes currently in the 2852 * selfid buffer, and if we have seen any selfid errors. 2853 */ 2854 void 2855 hci1394_ohci_selfid_info(hci1394_ohci_handle_t ohci_hdl, uint_t *busgen, 2856 uint_t *size, boolean_t *error) 2857 { 2858 uint32_t reg; 2859 2860 2861 ASSERT(ohci_hdl != NULL); 2862 ASSERT(busgen != NULL); 2863 ASSERT(size != NULL); 2864 ASSERT(error != NULL); 2865 TNF_PROBE_0_DEBUG(hci1394_ohci_selfid_info_enter, 2866 HCI1394_TNF_HAL_STACK, ""); 2867 2868 reg = ddi_get32(ohci_hdl->ohci_reg_handle, 2869 &ohci_hdl->ohci_regs->self_id_count); 2870 *busgen = (reg & OHCI_SLFC_GEN_MASK) >> OHCI_SLFC_GEN_SHIFT; 2871 *size = reg & OHCI_SLFC_NUM_QUADS_MASK; 2872 if ((reg & OHCI_SLFC_ERROR) == 0) { 2873 *error = B_FALSE; 2874 } else { 2875 *error = B_TRUE; 2876 } 2877 2878 TNF_PROBE_0_DEBUG(hci1394_ohci_selfid_info_exit, 2879 HCI1394_TNF_HAL_STACK, ""); 2880 } 2881 2882 2883 /* 2884 * hci1394_ohci_selfid_buf_current() 2885 * Test if the selfid buffer is current. Return B_TRUE if it is current and 2886 * B_FALSE if it is not current. 2887 */ 2888 boolean_t 2889 hci1394_ohci_selfid_buf_current(hci1394_ohci_handle_t ohci_hdl) 2890 { 2891 uint32_t reg; 2892 int status; 2893 2894 ASSERT(ohci_hdl != NULL); 2895 TNF_PROBE_0_DEBUG(hci1394_ohci_selfid_buf_current_enter, 2896 HCI1394_TNF_HAL_STACK, ""); 2897 2898 /* 2899 * if the generation stored in the selfid buffer is not equal to the 2900 * generation we have previously stored, the selfid buffer is not 2901 * current. (It maybe older or it maybe newer) 2902 */ 2903 reg = ddi_get32(ohci_hdl->ohci_selfid.bi_handle, 2904 &((uint32_t *)ohci_hdl->ohci_selfid.bi_kaddr)[0]); 2905 if (ohci_hdl->ohci_drvinfo->di_gencnt != ((reg & OHCI_SLFC_GEN_MASK) >> 2906 OHCI_SLFC_GEN_SHIFT)) { 2907 status = B_FALSE; 2908 } else { 2909 status = B_TRUE; 2910 } 2911 2912 TNF_PROBE_0_DEBUG(hci1394_ohci_selfid_buf_current_exit, 2913 HCI1394_TNF_HAL_STACK, ""); 2914 2915 return (status); 2916 } 2917 2918 2919 /* 2920 * hci1394_ohci_selfid_sync() 2921 * Perform a ddi_dma_sync on the selfid buffer 2922 */ 2923 void 2924 hci1394_ohci_selfid_sync(hci1394_ohci_handle_t ohci_hdl) 2925 { 2926 ASSERT(ohci_hdl != NULL); 2927 TNF_PROBE_0_DEBUG(hci1394_ohci_selfid_sync_enter, 2928 HCI1394_TNF_HAL_STACK, ""); 2929 (void) ddi_dma_sync(ohci_hdl->ohci_selfid.bi_dma_handle, 0, 2930 ohci_hdl->ohci_selfid.bi_length, DDI_DMA_SYNC_FORKERNEL); 2931 TNF_PROBE_0_DEBUG(hci1394_ohci_selfid_sync_exit, HCI1394_TNF_HAL_STACK, 2932 ""); 2933 } 2934 2935 2936 /* 2937 * hci1394_ohci_cfgrom_init() 2938 * Initialize the configuration ROM buffer 2939 */ 2940 static int 2941 hci1394_ohci_cfgrom_init(hci1394_ohci_handle_t ohci_hdl) 2942 { 2943 hci1394_buf_parms_t parms; 2944 int status; 2945 2946 2947 ASSERT(ohci_hdl != NULL); 2948 TNF_PROBE_0_DEBUG(hci1394_ohci_cfgrom_init_enter, 2949 HCI1394_TNF_HAL_STACK, ""); 2950 2951 /* 2952 * Setup for 1K buffer, aligned at 1K address boundary, and allow no 2953 * less than 4 byte data transfers. Create the Buffer. Make sure that 2954 * the buffer is not broken up into multiple cookies. OpenHCI can only 2955 * handle one address for the config ROM buffer location. 2956 */ 2957 parms.bp_length = 1024; 2958 parms.bp_max_cookies = 1; 2959 parms.bp_alignment = 1024; 2960 status = hci1394_buf_alloc(ohci_hdl->ohci_drvinfo, &parms, 2961 &ohci_hdl->ohci_cfgrom, &ohci_hdl->ohci_cfgrom_handle); 2962 if (status != DDI_SUCCESS) { 2963 TNF_PROBE_0(hci1394_buf_alloc_fail, HCI1394_TNF_HAL_ERROR, ""); 2964 TNF_PROBE_0_DEBUG(hci1394_ohci_cfgrom_init_exit, 2965 HCI1394_TNF_HAL_STACK, ""); 2966 return (DDI_FAILURE); 2967 } 2968 2969 /* Tell OpenHCI where the buffer is */ 2970 ddi_put32(ohci_hdl->ohci_reg_handle, 2971 &ohci_hdl->ohci_regs->config_rom_maplo, 2972 (uint32_t)ohci_hdl->ohci_cfgrom.bi_cookie.dmac_address); 2973 2974 TNF_PROBE_0_DEBUG(hci1394_ohci_cfgrom_init_exit, HCI1394_TNF_HAL_STACK, 2975 ""); 2976 2977 return (DDI_SUCCESS); 2978 } 2979 2980 2981 /* 2982 * hci1394_ohci_bus_capabilities() 2983 * Return our current bus capabilities 2984 */ 2985 void 2986 hci1394_ohci_bus_capabilities(hci1394_ohci_handle_t ohci_hdl, 2987 uint32_t *bus_capabilities) 2988 { 2989 ASSERT(ohci_hdl != NULL); 2990 TNF_PROBE_0_DEBUG(hci1394_ohci_bus_capabilities_enter, 2991 HCI1394_TNF_HAL_STACK, ""); 2992 /* 2993 * read in the bus options register. Set bits saying that we are isoch 2994 * resource manager capable, Cycle master capable, and Isoch capable 2995 */ 2996 *bus_capabilities = ddi_get32(ohci_hdl->ohci_reg_handle, 2997 &ohci_hdl->ohci_regs->bus_options) | (OHCI_BOPT_IRMC | 2998 OHCI_BOPT_CMC | OHCI_BOPT_ISC); 2999 TNF_PROBE_0_DEBUG(hci1394_ohci_bus_capabilities_exit, 3000 HCI1394_TNF_HAL_STACK, ""); 3001 } 3002 3003 3004 /* 3005 * hci1394_ohci_at_active() 3006 * Returns status one if either of the AT engines are active. If either AT 3007 * engine is active, we return B_TRUE. If both AT engines are not active, we 3008 * return B_FALSE. 3009 */ 3010 boolean_t 3011 hci1394_ohci_at_active(hci1394_ohci_handle_t ohci_hdl) 3012 { 3013 uint32_t reg; 3014 3015 3016 ASSERT(ohci_hdl != NULL); 3017 TNF_PROBE_0_DEBUG(hci1394_ohci_at_active_enter, 3018 HCI1394_TNF_HAL_STACK, ""); 3019 3020 /* see if atreq active bit set */ 3021 reg = ddi_get32(ohci_hdl->ohci_reg_handle, 3022 &ohci_hdl->ohci_regs->at_req.ctxt_ctrl_set); 3023 if (reg & OHCI_CC_ACTIVE_MASK) { 3024 /* atreq engine is still active */ 3025 TNF_PROBE_0(hci1394_ohci_atreq_active_fail, 3026 HCI1394_TNF_HAL_ERROR, ""); 3027 TNF_PROBE_0_DEBUG(hci1394_ohci_at_active_exit, 3028 HCI1394_TNF_HAL_STACK, ""); 3029 return (B_TRUE); 3030 } 3031 3032 /* see if atresp active bit set */ 3033 reg = ddi_get32(ohci_hdl->ohci_reg_handle, 3034 &ohci_hdl->ohci_regs->at_resp.ctxt_ctrl_set); 3035 if (reg & OHCI_CC_ACTIVE_MASK) { 3036 /* atresp engine is still active */ 3037 TNF_PROBE_0(hci1394_ohci_atresp_active_fail, 3038 HCI1394_TNF_HAL_ERROR, ""); 3039 TNF_PROBE_0_DEBUG(hci1394_ohci_at_active_exit, 3040 HCI1394_TNF_HAL_STACK, ""); 3041 return (B_TRUE); 3042 } 3043 3044 TNF_PROBE_0_DEBUG(hci1394_ohci_at_active_exit, 3045 HCI1394_TNF_HAL_STACK, ""); 3046 3047 /* both atreq and atresp active bits are cleared */ 3048 return (B_FALSE); 3049 } 3050 3051 3052 /* 3053 * hci1394_ohci_atreq_start() 3054 * Start the atreq dma engine. Set the address of the first descriptor 3055 * to read in equal to cmdptr. 3056 */ 3057 void 3058 hci1394_ohci_atreq_start(hci1394_ohci_handle_t ohci_hdl, uint32_t cmdptr) 3059 { 3060 ASSERT(ohci_hdl != NULL); 3061 TNF_PROBE_0_DEBUG(hci1394_ohci_atreq_start_enter, 3062 HCI1394_TNF_HAL_STACK, ""); 3063 3064 ddi_put32(ohci_hdl->ohci_reg_handle, 3065 &ohci_hdl->ohci_regs->at_req.cmd_ptrlo, cmdptr); 3066 ddi_put32(ohci_hdl->ohci_reg_handle, 3067 &ohci_hdl->ohci_regs->at_req.ctxt_ctrl_set, OHCI_CC_RUN_MASK); 3068 3069 TNF_PROBE_0_DEBUG(hci1394_ohci_atreq_start_exit, 3070 HCI1394_TNF_HAL_STACK, ""); 3071 } 3072 3073 3074 /* 3075 * hci1394_ohci_atreq_wake() 3076 * Wake up the atreq dma engine. This should be called when a new descriptor 3077 * is added to the Q and the dma engine has already be started. It it OK to 3078 * call this when the DMA engine is active. 3079 */ 3080 void 3081 hci1394_ohci_atreq_wake(hci1394_ohci_handle_t ohci_hdl) 3082 { 3083 ASSERT(ohci_hdl != NULL); 3084 TNF_PROBE_0_DEBUG(hci1394_ohci_atreq_wake_enter, 3085 HCI1394_TNF_HAL_STACK, ""); 3086 3087 ddi_put32(ohci_hdl->ohci_reg_handle, 3088 &ohci_hdl->ohci_regs->at_req.ctxt_ctrl_set, OHCI_CC_WAKE_MASK); 3089 3090 TNF_PROBE_0_DEBUG(hci1394_ohci_atreq_wake_exit, 3091 HCI1394_TNF_HAL_STACK, ""); 3092 } 3093 3094 3095 /* 3096 * hci1394_ohci_atreq_stop() 3097 * Stop the atreq dma engine. No further descriptors will be read until 3098 * it dma engine is started again. 3099 */ 3100 void 3101 hci1394_ohci_atreq_stop(hci1394_ohci_handle_t ohci_hdl) 3102 { 3103 ASSERT(ohci_hdl != NULL); 3104 TNF_PROBE_0_DEBUG(hci1394_ohci_atreq_stop_enter, 3105 HCI1394_TNF_HAL_STACK, ""); 3106 3107 ddi_put32(ohci_hdl->ohci_reg_handle, 3108 &ohci_hdl->ohci_regs->at_req.ctxt_ctrl_clr, OHCI_CC_RUN_MASK); 3109 3110 TNF_PROBE_0_DEBUG(hci1394_ohci_atreq_stop_exit, 3111 HCI1394_TNF_HAL_STACK, ""); 3112 } 3113 3114 3115 /* 3116 * hci1394_ohci_arresp_start() 3117 * Start the arresp dma engine. Set the address of the first descriptor 3118 * to read in equal to cmdptr. 3119 */ 3120 void 3121 hci1394_ohci_arresp_start(hci1394_ohci_handle_t ohci_hdl, uint32_t cmdptr) 3122 { 3123 ASSERT(ohci_hdl != NULL); 3124 TNF_PROBE_0_DEBUG(hci1394_ohci_arresp_start_enter, 3125 HCI1394_TNF_HAL_STACK, ""); 3126 3127 ddi_put32(ohci_hdl->ohci_reg_handle, 3128 &ohci_hdl->ohci_regs->ar_resp.cmd_ptrlo, cmdptr); 3129 ddi_put32(ohci_hdl->ohci_reg_handle, 3130 &ohci_hdl->ohci_regs->ar_resp.ctxt_ctrl_set, OHCI_CC_RUN_MASK); 3131 3132 TNF_PROBE_0_DEBUG(hci1394_ohci_arresp_start_exit, 3133 HCI1394_TNF_HAL_STACK, ""); 3134 } 3135 3136 3137 /* 3138 * hci1394_ohci_arresp_wake() 3139 * Wake up the arresp dma engine. This should be called when a new 3140 * descriptor is added to the Q and the dma engine has already be started. 3141 * It is OK to call this when the DMA engine is active. 3142 */ 3143 void 3144 hci1394_ohci_arresp_wake(hci1394_ohci_handle_t ohci_hdl) 3145 { 3146 ASSERT(ohci_hdl != NULL); 3147 TNF_PROBE_0_DEBUG(hci1394_ohci_arresp_wake_enter, 3148 HCI1394_TNF_HAL_STACK, ""); 3149 3150 ddi_put32(ohci_hdl->ohci_reg_handle, 3151 &ohci_hdl->ohci_regs->ar_resp.ctxt_ctrl_set, OHCI_CC_WAKE_MASK); 3152 3153 TNF_PROBE_0_DEBUG(hci1394_ohci_arresp_wake_exit, 3154 HCI1394_TNF_HAL_STACK, ""); 3155 } 3156 3157 3158 /* 3159 * hci1394_ohci_atreq_stop() 3160 * Stop the arresp dma engine. No further data will be received after any 3161 * current packets being received have finished. 3162 */ 3163 void 3164 hci1394_ohci_arresp_stop(hci1394_ohci_handle_t ohci_hdl) 3165 { 3166 ASSERT(ohci_hdl != NULL); 3167 TNF_PROBE_0_DEBUG(hci1394_ohci_arresp_stop_enter, 3168 HCI1394_TNF_HAL_STACK, ""); 3169 3170 ddi_put32(ohci_hdl->ohci_reg_handle, 3171 &ohci_hdl->ohci_regs->ar_resp.ctxt_ctrl_clr, OHCI_CC_RUN_MASK); 3172 3173 TNF_PROBE_0_DEBUG(hci1394_ohci_arresp_stop_exit, 3174 HCI1394_TNF_HAL_STACK, ""); 3175 } 3176 3177 3178 /* 3179 * hci1394_ohci_arreq_start() 3180 * Start the arreq dma engine. Set the address of the first descriptor 3181 * to read in equal to cmdptr. 3182 */ 3183 void 3184 hci1394_ohci_arreq_start(hci1394_ohci_handle_t ohci_hdl, uint32_t cmdptr) 3185 { 3186 ASSERT(ohci_hdl != NULL); 3187 TNF_PROBE_0_DEBUG(hci1394_ohci_arreq_start_enter, 3188 HCI1394_TNF_HAL_STACK, ""); 3189 3190 ddi_put32(ohci_hdl->ohci_reg_handle, 3191 &ohci_hdl->ohci_regs->ar_req.cmd_ptrlo, cmdptr); 3192 ddi_put32(ohci_hdl->ohci_reg_handle, 3193 &ohci_hdl->ohci_regs->ar_req.ctxt_ctrl_set, OHCI_CC_RUN_MASK); 3194 3195 TNF_PROBE_0_DEBUG(hci1394_ohci_arreq_start_exit, 3196 HCI1394_TNF_HAL_STACK, ""); 3197 } 3198 3199 3200 /* 3201 * hci1394_ohci_arreq_wake() 3202 * Wake up the arreq dma engine. This should be called when a new descriptor 3203 * is added to the Q and the dma engine has already be started. It is OK to 3204 * call this when the DMA engine is active. 3205 */ 3206 void 3207 hci1394_ohci_arreq_wake(hci1394_ohci_handle_t ohci_hdl) 3208 { 3209 ASSERT(ohci_hdl != NULL); 3210 TNF_PROBE_0_DEBUG(hci1394_ohci_arreq_wake_enter, 3211 HCI1394_TNF_HAL_STACK, ""); 3212 3213 ddi_put32(ohci_hdl->ohci_reg_handle, 3214 &ohci_hdl->ohci_regs->ar_req.ctxt_ctrl_set, OHCI_CC_WAKE_MASK); 3215 3216 TNF_PROBE_0_DEBUG(hci1394_ohci_arreq_wake_exit, 3217 HCI1394_TNF_HAL_STACK, ""); 3218 } 3219 3220 3221 /* 3222 * hci1394_ohci_arreq_stop() 3223 * Stop the arreq dma engine. No further data will be received after any 3224 * current packets being received have finished. 3225 */ 3226 void 3227 hci1394_ohci_arreq_stop(hci1394_ohci_handle_t ohci_hdl) 3228 { 3229 ASSERT(ohci_hdl != NULL); 3230 TNF_PROBE_0_DEBUG(hci1394_ohci_arreq_stop_enter, 3231 HCI1394_TNF_HAL_STACK, ""); 3232 3233 ddi_put32(ohci_hdl->ohci_reg_handle, 3234 &ohci_hdl->ohci_regs->ar_req.ctxt_ctrl_clr, OHCI_CC_RUN_MASK); 3235 3236 TNF_PROBE_0_DEBUG(hci1394_ohci_arreq_stop_exit, 3237 HCI1394_TNF_HAL_STACK, ""); 3238 } 3239 3240 3241 /* 3242 * hci1394_ohci_atresp_start() 3243 * Start the atresp dma engine. Set the address of the first descriptor 3244 * to read in equal to cmdptr. 3245 */ 3246 void 3247 hci1394_ohci_atresp_start(hci1394_ohci_handle_t ohci_hdl, uint32_t cmdptr) 3248 { 3249 ASSERT(ohci_hdl != NULL); 3250 TNF_PROBE_0_DEBUG(hci1394_ohci_atresp_start_enter, 3251 HCI1394_TNF_HAL_STACK, ""); 3252 3253 ddi_put32(ohci_hdl->ohci_reg_handle, 3254 &ohci_hdl->ohci_regs->at_resp.cmd_ptrlo, cmdptr); 3255 ddi_put32(ohci_hdl->ohci_reg_handle, 3256 &ohci_hdl->ohci_regs->at_resp.ctxt_ctrl_set, OHCI_CC_RUN_MASK); 3257 3258 TNF_PROBE_0_DEBUG(hci1394_ohci_atresp_start_exit, 3259 HCI1394_TNF_HAL_STACK, ""); 3260 } 3261 3262 3263 /* 3264 * hci1394_ohci_atresp_wake() 3265 * Wake up the atresp dma engine. This should be called when a new 3266 * descriptor is added to the Q and the dma engine has already be started. 3267 * It is OK to call this when the DMA engine is active. 3268 */ 3269 void 3270 hci1394_ohci_atresp_wake(hci1394_ohci_handle_t ohci_hdl) 3271 { 3272 ASSERT(ohci_hdl != NULL); 3273 TNF_PROBE_0_DEBUG(hci1394_ohci_atresp_wake_enter, 3274 HCI1394_TNF_HAL_STACK, ""); 3275 3276 ddi_put32(ohci_hdl->ohci_reg_handle, 3277 &ohci_hdl->ohci_regs->at_resp.ctxt_ctrl_set, OHCI_CC_WAKE_MASK); 3278 3279 TNF_PROBE_0_DEBUG(hci1394_ohci_atresp_wake_exit, 3280 HCI1394_TNF_HAL_STACK, ""); 3281 } 3282 3283 3284 /* 3285 * hci1394_ohci_atresp_stop() 3286 * Stop the atresp dma engine. No further descriptors will be read until 3287 * it dma engine is started again. 3288 */ 3289 void 3290 hci1394_ohci_atresp_stop(hci1394_ohci_handle_t ohci_hdl) 3291 { 3292 ASSERT(ohci_hdl != NULL); 3293 TNF_PROBE_0_DEBUG(hci1394_ohci_atresp_stop_enter, 3294 HCI1394_TNF_HAL_STACK, ""); 3295 3296 ddi_put32(ohci_hdl->ohci_reg_handle, 3297 &ohci_hdl->ohci_regs->at_resp.ctxt_ctrl_clr, OHCI_CC_RUN_MASK); 3298 3299 TNF_PROBE_0_DEBUG(hci1394_ohci_atresp_stop_exit, 3300 HCI1394_TNF_HAL_STACK, ""); 3301 } 3302 3303 3304 /* 3305 * hci1394_ohci_1394a_init() 3306 * Initialize any 1394a features that we are using. 3307 */ 3308 /* ARGSUSED */ 3309 int 3310 hci1394_ohci_1394a_init(hci1394_ohci_handle_t ohci_hdl) 3311 { 3312 uint32_t reg; 3313 int status; 3314 3315 ASSERT(ohci_hdl != NULL); 3316 TNF_PROBE_0_DEBUG(hci1394_ohci_1394a_init_enter, HCI1394_TNF_HAL_STACK, 3317 ""); 3318 3319 reg = ddi_get32(ohci_hdl->ohci_reg_handle, 3320 &ohci_hdl->ohci_regs->hc_ctrl_set); 3321 if (reg & OHCI_HC_PROG_PHY_ENBL) { 3322 ddi_put32(ohci_hdl->ohci_reg_handle, 3323 &ohci_hdl->ohci_regs->hc_ctrl_set, OHCI_HC_APHY_ENBL); 3324 status = hci1394_ohci_phy_set(ohci_hdl, 5, 3325 (OHCI_PHY_ENBL_ACCEL | OHCI_PHY_ENBL_MULTI)); 3326 if (status != DDI_SUCCESS) { 3327 TNF_PROBE_0(hci1394_ohci_1394a_init_phy_fail, 3328 HCI1394_TNF_HAL_STACK, ""); 3329 TNF_PROBE_0_DEBUG(hci1394_ohci_1394a_init_exit, 3330 HCI1394_TNF_HAL_STACK, ""); 3331 return (DDI_FAILURE); 3332 } 3333 } 3334 3335 TNF_PROBE_0_DEBUG(hci1394_ohci_1394a_init_exit, HCI1394_TNF_HAL_STACK, 3336 ""); 3337 return (DDI_SUCCESS); 3338 } 3339 3340 3341 /* 3342 * hci1394_ohci_1394a_init() 3343 * Re-initialize any 1394a features that we are using. 3344 */ 3345 /* ARGSUSED */ 3346 int 3347 hci1394_ohci_1394a_resume(hci1394_ohci_handle_t ohci_hdl) 3348 { 3349 uint32_t reg; 3350 int status; 3351 3352 ASSERT(ohci_hdl != NULL); 3353 TNF_PROBE_0_DEBUG(hci1394_ohci_1394a_resume_enter, 3354 HCI1394_TNF_HAL_STACK, ""); 3355 3356 reg = ddi_get32(ohci_hdl->ohci_reg_handle, 3357 &ohci_hdl->ohci_regs->hc_ctrl_set); 3358 if (reg & OHCI_HC_PROG_PHY_ENBL) { 3359 ddi_put32(ohci_hdl->ohci_reg_handle, 3360 &ohci_hdl->ohci_regs->hc_ctrl_set, OHCI_HC_APHY_ENBL); 3361 status = hci1394_ohci_phy_set(ohci_hdl, 5, 3362 (OHCI_PHY_ENBL_ACCEL | OHCI_PHY_ENBL_MULTI)); 3363 if (status != DDI_SUCCESS) { 3364 TNF_PROBE_0(hci1394_ohci_1394a_resume_phy_fail, 3365 HCI1394_TNF_HAL_STACK, ""); 3366 TNF_PROBE_0_DEBUG(hci1394_ohci_1394a_resume_exit, 3367 HCI1394_TNF_HAL_STACK, ""); 3368 return (DDI_FAILURE); 3369 } 3370 } 3371 3372 TNF_PROBE_0_DEBUG(hci1394_ohci_1394a_resume_exit, 3373 HCI1394_TNF_HAL_STACK, ""); 3374 return (DDI_SUCCESS); 3375 } 3376