1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright (c) 1999-2000 by Sun Microsystems, Inc. 24 * All rights reserved. 25 */ 26 27 /* 28 * hci1394_csr.c 29 * This code contains the code for the CSR registers handled by the HAL in 30 * SW. The HW implemented CSR registers are in hci1394_ohci.c 31 * 32 * For more information on CSR registers, see 33 * IEEE 1212 34 * IEEE 1394-1995 35 * section 8.3.2 36 * IEEE P1394A Draft 3.0 37 * sections 10.32,10.33 38 * 39 * NOTE: A read/write to a CSR SW based register will first go to the Services 40 * Layer which will do some filtering and then come through the s1394if. Look 41 * in hci1394_s1394if.c to see which registers are implemented in HW and 42 * which are implemented in SW. 43 */ 44 45 #include <sys/conf.h> 46 #include <sys/ddi.h> 47 #include <sys/modctl.h> 48 #include <sys/stat.h> 49 #include <sys/sunddi.h> 50 #include <sys/cmn_err.h> 51 #include <sys/kmem.h> 52 #include <sys/types.h> 53 54 #include <sys/1394/adapters/hci1394.h> 55 #include <sys/1394/adapters/hci1394_extern.h> 56 57 58 /* 59 * The split_timeout_lo register cannot be set below 800 and above 7999. The 60 * split_timeout_hi register cannot be set above 7. 61 */ 62 #define CSR_MIN_SPLIT_TIMEOUT_LO 800 63 #define CSR_MAX_SPLIT_TIMEOUT_LO 7999 64 #define CSR_MAX_SPLIT_TIMEOUT_HI 7 65 66 /* 67 * We will convert the split_timeout_lo to return the data in most significant 68 * 13 bits on the fly. 69 */ 70 #define CSR_SPLIT_TIMEOUT_LO_SHIFT 19 71 72 /* 73 * This is what we report to the services layer as our node capabilities. 74 * See IEEE 1212_1994, section 8.4.11 75 * 76 * Split Timeout Registers are implemented (bit 15) 77 * This node uses 64-bit addressing (bit 9) 78 * This node uses fixed addressing scheme (bit 8) 79 * STATE_BITS.lost is implemented 80 * STATE_BITS.dreq is implemented 81 */ 82 #define CSR_INITIAL_NODE_CAPABILITIES 0x000083C0 83 84 /* 85 * macro to calculate split_timeout based on split_timeout_lo and 86 * split_timeout_hi 87 */ 88 #define CSR_SPLIT_TIMEOUT(split_hi, split_lo) \ 89 ((split_hi * IEEE1394_BUS_CYCLES_PER_SEC) + split_lo) 90 91 92 static void hci1394_csr_state_init(hci1394_csr_t *csr); 93 94 95 /* 96 * hci1394_csr_init() 97 * Initialize CSR state and CSR SW based registers. 98 */ 99 void 100 hci1394_csr_init(hci1394_drvinfo_t *drvinfo, hci1394_ohci_handle_t ohci, 101 hci1394_csr_handle_t *csr_handle) 102 { 103 hci1394_csr_t *csr; 104 105 106 ASSERT(drvinfo != NULL); 107 ASSERT(ohci != NULL); 108 ASSERT(csr_handle != NULL); 109 110 /* alloc the space to keep track of the csr registers */ 111 csr = kmem_alloc(sizeof (hci1394_csr_t), KM_SLEEP); 112 113 /* setup the return parameter */ 114 *csr_handle = csr; 115 116 /* Initialize the csr structure */ 117 csr->csr_drvinfo = drvinfo; 118 csr->csr_ohci = ohci; 119 mutex_init(&csr->csr_mutex, NULL, MUTEX_DRIVER, 120 drvinfo->di_iblock_cookie); 121 hci1394_csr_state_init(csr); 122 } 123 124 125 /* 126 * hci1394_csr_fini() 127 * Free up any space allocated and any mutexes used. 128 */ 129 void 130 hci1394_csr_fini(hci1394_csr_handle_t *csr_handle) 131 { 132 hci1394_csr_t *csr; 133 134 135 ASSERT(csr_handle != NULL); 136 137 csr = (hci1394_csr_t *)*csr_handle; 138 mutex_destroy(&csr->csr_mutex); 139 kmem_free(csr, sizeof (hci1394_csr_t)); 140 *csr_handle = NULL; 141 } 142 143 144 /* 145 * hci1394_csr_resume() 146 * When resuming power on a workstation, re-setup our CSR registers. 147 */ 148 void 149 hci1394_csr_resume(hci1394_csr_handle_t csr_handle) 150 { 151 ASSERT(csr_handle != NULL); 152 hci1394_csr_state_init(csr_handle); 153 } 154 155 156 /* 157 * hci1394_csr_node_capabilities() 158 * Return the CSR node capabilities. 159 */ 160 void 161 hci1394_csr_node_capabilities(hci1394_csr_handle_t csr_handle, 162 uint32_t *capabilities) 163 { 164 ASSERT(csr_handle != NULL); 165 ASSERT(capabilities != NULL); 166 167 mutex_enter(&csr_handle->csr_mutex); 168 *capabilities = csr_handle->csr_capabilities; 169 mutex_exit(&csr_handle->csr_mutex); 170 } 171 172 173 /* 174 * hci1394_csr_state_get() 175 * Read the CSR state register. Currently we only support the dreq, cmstr, 176 * and abdicate bits in the CSR state register. See the specs mentioned 177 * above for the behavior of these bits. 178 */ 179 void 180 hci1394_csr_state_get(hci1394_csr_handle_t csr_handle, uint32_t *state) 181 { 182 ASSERT(csr_handle != NULL); 183 ASSERT(state != NULL); 184 185 mutex_enter(&csr_handle->csr_mutex); 186 *state = csr_handle->csr_state; 187 mutex_exit(&csr_handle->csr_mutex); 188 } 189 190 191 /* 192 * hci1394_csr_state_bset() 193 * Perform a bit set on the CSR state register. The value of state will be 194 * or'd with the CSR state register. Currently we only support the dreq, 195 * cmstr, and abdicate bits in the CSR state register. See the specs 196 * mentioned above for the behavior of these bits. 197 */ 198 void 199 hci1394_csr_state_bset(hci1394_csr_handle_t csr_handle, uint32_t state) 200 { 201 uint32_t supported_state; 202 203 204 ASSERT(csr_handle != NULL); 205 206 mutex_enter(&csr_handle->csr_mutex); 207 208 /* only support dreq, cmstr, and abdicate bits */ 209 supported_state = state & (IEEE1394_CSR_STATE_ABDICATE | 210 IEEE1394_CSR_STATE_CMSTR | IEEE1394_CSR_STATE_DREQ); 211 212 /* 213 * If we are setting the Cycle Master bit and we are the root node, 214 * enable Cycle Start Packets. 215 */ 216 if ((supported_state & IEEE1394_CSR_STATE_CMSTR) && 217 (hci1394_ohci_root_check(csr_handle->csr_ohci))) { 218 hci1394_ohci_cycle_master_enable(csr_handle->csr_ohci); 219 } 220 221 /* set the supported bits in csr_state */ 222 csr_handle->csr_state |= supported_state; 223 224 mutex_exit(&csr_handle->csr_mutex); 225 } 226 227 228 /* 229 * hci1394_csr_state_bclr() 230 * Perform a bit clear on the CSR state register. The inverted value of 231 * state will be and'd with CSR state register. Currently we only support 232 * the dreq, cmstr, and abdicate bits in the CSR state register. See the 233 * specs mentioned above for the behavior of these bits. 234 */ 235 void 236 hci1394_csr_state_bclr(hci1394_csr_handle_t csr_handle, uint32_t state) 237 { 238 uint32_t supported_state; 239 240 241 ASSERT(csr_handle != NULL); 242 243 mutex_enter(&csr_handle->csr_mutex); 244 245 /* only support dreq, cmstr, and abdicate bits */ 246 supported_state = state & (IEEE1394_CSR_STATE_ABDICATE | 247 IEEE1394_CSR_STATE_CMSTR | IEEE1394_CSR_STATE_DREQ); 248 249 /* 250 * If we are clearing the Cycle Master bit and we are the root node, 251 * disable Cycle Start Packets. 252 */ 253 if ((supported_state & IEEE1394_CSR_STATE_CMSTR) && 254 (hci1394_ohci_root_check(csr_handle->csr_ohci))) { 255 hci1394_ohci_cycle_master_disable(csr_handle->csr_ohci); 256 } 257 258 /* Clear the supported bits in csr_state */ 259 csr_handle->csr_state &= ~state; 260 261 mutex_exit(&csr_handle->csr_mutex); 262 } 263 264 265 /* 266 * hci1394_csr_split_timeout_hi_get() 267 * Read the CSR split_timeout_hi register. 268 */ 269 void 270 hci1394_csr_split_timeout_hi_get(hci1394_csr_handle_t csr_handle, 271 uint32_t *split_timeout_hi) 272 { 273 ASSERT(csr_handle != NULL); 274 ASSERT(split_timeout_hi != NULL); 275 276 mutex_enter(&csr_handle->csr_mutex); 277 *split_timeout_hi = csr_handle->csr_split_timeout_hi; 278 mutex_exit(&csr_handle->csr_mutex); 279 } 280 281 282 /* 283 * hci1394_csr_split_timeout_lo_get() 284 * Read the CSR split_timeout_lo register. 285 */ 286 void 287 hci1394_csr_split_timeout_lo_get(hci1394_csr_handle_t csr_handle, 288 uint32_t *split_timeout_lo) 289 { 290 ASSERT(csr_handle != NULL); 291 ASSERT(split_timeout_lo != NULL); 292 293 mutex_enter(&csr_handle->csr_mutex); 294 295 /* 296 * Read the split_timeout_lo CSR register. Convert split_timeout_lo to 297 * use the data in most significant 13 bits on the fly. 298 */ 299 *split_timeout_lo = csr_handle->csr_split_timeout_lo << 300 CSR_SPLIT_TIMEOUT_LO_SHIFT; 301 302 mutex_exit(&csr_handle->csr_mutex); 303 } 304 305 306 /* 307 * hci1394_csr_split_timeout_hi_set() 308 * Write the CSR split_timeout_hi register. This routine will also 309 * re-calculate the "split_timeout" which is used internally in the HAL 310 * driver. The only accesses to split_timeout_hi and split_timeout_lo 311 * should be over the 1394 bus. Only the least significant 3 bits are 312 * relevant in the split_timeout_hi register. 313 */ 314 void 315 hci1394_csr_split_timeout_hi_set(hci1394_csr_handle_t csr_handle, 316 uint32_t split_timeout_hi) 317 { 318 ASSERT(csr_handle != NULL); 319 320 mutex_enter(&csr_handle->csr_mutex); 321 322 /* 323 * update the split_timeout_hi CSR register. Only look at the 3 LSBits. 324 * Update our internal split_timeout value. 325 */ 326 csr_handle->csr_split_timeout_hi = split_timeout_hi & 327 CSR_MAX_SPLIT_TIMEOUT_HI; 328 csr_handle->csr_split_timeout = CSR_SPLIT_TIMEOUT( 329 csr_handle->csr_split_timeout_hi, csr_handle->csr_split_timeout_lo); 330 331 mutex_exit(&csr_handle->csr_mutex); 332 } 333 334 335 /* 336 * hci1394_csr_split_timeout_lo_set() 337 * Write the CSR split_timeout_lo register. This routine will also 338 * re-calculate the "split_timeout" which is used internally in the HAL 339 * driver. The only accesses to split_timeout_hi and split_timeout_lo 340 * should be over the 1394 bus. Only the most significant 13 bits are 341 * relevant in the split_timeout_lo register. 342 */ 343 void 344 hci1394_csr_split_timeout_lo_set(hci1394_csr_handle_t csr_handle, 345 uint32_t split_timeout_lo) 346 { 347 ASSERT(csr_handle != NULL); 348 349 mutex_enter(&csr_handle->csr_mutex); 350 351 /* 352 * Update the split_timeout_lo CSR register. Only look at the 3 LSBits. 353 * Convert the split_timeout_lo to use the data in most significant 13 354 * bits on the fly. 355 */ 356 csr_handle->csr_split_timeout_lo = split_timeout_lo >> 357 CSR_SPLIT_TIMEOUT_LO_SHIFT; 358 359 /* threshold the split_timeout_lo value */ 360 if (csr_handle->csr_split_timeout_lo < CSR_MIN_SPLIT_TIMEOUT_LO) { 361 csr_handle->csr_split_timeout_lo = CSR_MIN_SPLIT_TIMEOUT_LO; 362 } else if (csr_handle->csr_split_timeout_lo > 363 CSR_MAX_SPLIT_TIMEOUT_LO) { 364 csr_handle->csr_split_timeout_lo = CSR_MAX_SPLIT_TIMEOUT_LO; 365 } 366 367 /* Update our internal split_timeout value */ 368 csr_handle->csr_split_timeout = CSR_SPLIT_TIMEOUT( 369 csr_handle->csr_split_timeout_hi, csr_handle->csr_split_timeout_lo); 370 371 mutex_exit(&csr_handle->csr_mutex); 372 } 373 374 375 /* 376 * hci1394_csr_split_timeout_get() 377 * Return the current value of split_timeout. This is the only routine 378 * which should be used to get the split timeout for use in a calculation 379 * (e.g. for calculating ACK pending timeout). 380 */ 381 uint_t 382 hci1394_csr_split_timeout_get(hci1394_csr_handle_t csr_handle) 383 { 384 uint_t split_timeout; 385 386 387 ASSERT(csr_handle != NULL); 388 389 mutex_enter(&csr_handle->csr_mutex); 390 391 /* read our internal split_timeout value */ 392 split_timeout = csr_handle->csr_split_timeout; 393 394 mutex_exit(&csr_handle->csr_mutex); 395 396 return (split_timeout); 397 } 398 399 400 /* 401 * hci1394_csr_bus_reset() 402 * Perform required bus reset processing on CSR registers. This includes 403 * clearing the abdicate bit, and setting/clearing the Cycle Master bit. 404 * See sections 10.32 and 10.33 in the IEEE P1394A Draft 3.0 spec. See 405 * section 8.3.2.2.1 in the IEEE 1394-1995 spec. This routine should be 406 * called every bus reset. 407 */ 408 void 409 hci1394_csr_bus_reset(hci1394_csr_handle_t csr_handle) 410 { 411 ASSERT(csr_handle != NULL); 412 413 mutex_enter(&csr_handle->csr_mutex); 414 415 /* Clear the abdicate bit. Always do this. */ 416 csr_handle->csr_state &= ~IEEE1394_CSR_STATE_ABDICATE; 417 418 /* if we are NOT currently the root node on the bus */ 419 if (hci1394_ohci_root_check(csr_handle->csr_ohci) == B_FALSE) { 420 /* 421 * Set the was_root state. This is needed for the Cycle Master 422 * state machine below. 423 */ 424 csr_handle->csr_was_root = B_FALSE; 425 426 /* 427 * Clear the Cycle Master bit. We do not have to shut off cycle 428 * master in OpenHCI. The HW will automatically stop generating 429 * Cycle Start packets when it is not the root node. 430 */ 431 csr_handle->csr_state &= ~IEEE1394_CSR_STATE_CMSTR; 432 433 /* 434 * if we are currently the root node on the bus and we were NOT 435 * the root before the reset. 436 */ 437 } else if (csr_handle->csr_was_root == B_FALSE) { 438 439 /* set the was_root state to TRUE */ 440 csr_handle->csr_was_root = B_TRUE; 441 442 /* 443 * if we are cycle master capable, set the Cycle Master bit and 444 * start Cycle Start packets. We should always be Cycle Master 445 * capable. 446 */ 447 if (hci1394_ohci_cmc_check(csr_handle->csr_ohci)) { 448 csr_handle->csr_state |= IEEE1394_CSR_STATE_CMSTR; 449 hci1394_ohci_cycle_master_enable(csr_handle->csr_ohci); 450 451 /* 452 * if we are NOT cycle master capable, clear the Cycle Master 453 * bit and stop Cycle Start packets. We should never see this 454 * in OpenHCI. I think? :-) 455 */ 456 } else { 457 csr_handle->csr_state &= ~IEEE1394_CSR_STATE_CMSTR; 458 hci1394_ohci_cycle_master_disable(csr_handle->csr_ohci); 459 } 460 } 461 /* 462 * else {} 463 * else we are root now. We were root before, keep cmstr the same. 464 * Nothing to do. 465 */ 466 467 mutex_exit(&csr_handle->csr_mutex); 468 } 469 470 471 /* 472 * hci1394_csr_state_init() 473 * set the CSR SW registers and state variables to their initial settings. 474 */ 475 static void hci1394_csr_state_init(hci1394_csr_t *csr) 476 { 477 ASSERT(csr != NULL); 478 479 mutex_enter(&csr->csr_mutex); 480 481 /* 482 * Initialize the split timeout to be 0 seconds (split_timeout_hi) and 483 * use a patchable variable for the initial split_timeout_lo. This 484 * variable must be patched before the driver attaches. It is never 485 * looked at again after this code is run. 486 * 487 * Calculate the split_timeout which we will use in the driver based on 488 * split_timeout_lo and split_timeout_hi. 489 */ 490 csr->csr_split_timeout_hi = 0; 491 csr->csr_split_timeout_lo = hci1394_split_timeout; 492 csr->csr_split_timeout = CSR_SPLIT_TIMEOUT( 493 csr->csr_split_timeout_hi, csr->csr_split_timeout_lo); 494 495 /* Set the initial CSR State register to 0 */ 496 csr->csr_state = 0; 497 498 /* 499 * was_root is an internal state variable which tracks if we were root 500 * last bus reset. This is needed for the required state register bus 501 * reset processing. 502 */ 503 csr->csr_was_root = B_FALSE; 504 505 /* setup our initial capabilities setting */ 506 csr->csr_capabilities = CSR_INITIAL_NODE_CAPABILITIES; 507 508 mutex_exit(&csr->csr_mutex); 509 } 510