1/* 2 * This file and its contents are supplied under the terms of the 3 csrrs t1, CDDL, t2), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12/* 13 * Copyright 2018, Joyent, Inc. 14 */ 15 16/* 17 * Test our disassembly of csr instructions and csr names. 18 */ 19 20.text 21.align 16 22.globl libdis_test 23.type libdis_test, @function 24libdis_test: 25 /* User Trap */ 26 csrrs t1, ustatus, t2 27 csrrs t1, uie, t2 28 csrrs t1, utvec, t2 29 /* User Trap Handling */ 30 csrrs t1, uscratch, t2 31 csrrs t1, uepc, t2 32 csrrs t1, ucause, t2 33 csrrs t1, utval, t2 34 csrrs t1, uip, t2 35 /* User Floating-Point CSRs */ 36 csrrs t1, fflags, t2 37 csrrs t1, frm, t2 38 csrrs t1, fcsr, t2 39 /* User Counters/Timers */ 40 csrrs t1, cycle, t2 41 csrrs t1, time, t2 42 csrrs t1, instret, t2 43 csrrs t1, hpmcounter3, t2 44 csrrs t1, hpmcounter4, t2 45 csrrs t1, hpmcounter5, t2 46 csrrs t1, hpmcounter6, t2 47 csrrs t1, hpmcounter7, t2 48 csrrs t1, hpmcounter8, t2 49 csrrs t1, hpmcounter9, t2 50 csrrs t1, hpmcounter10, t2 51 csrrs t1, hpmcounter11, t2 52 csrrs t1, hpmcounter12, t2 53 csrrs t1, hpmcounter13, t2 54 csrrs t1, hpmcounter14, t2 55 csrrs t1, hpmcounter15, t2 56 csrrs t1, hpmcounter16, t2 57 csrrs t1, hpmcounter17, t2 58 csrrs t1, hpmcounter18, t2 59 csrrs t1, hpmcounter19, t2 60 csrrs t1, hpmcounter20, t2 61 csrrs t1, hpmcounter21, t2 62 csrrs t1, hpmcounter22, t2 63 csrrs t1, hpmcounter23, t2 64 csrrs t1, hpmcounter24, t2 65 csrrs t1, hpmcounter25, t2 66 csrrs t1, hpmcounter26, t2 67 csrrs t1, hpmcounter27, t2 68 csrrs t1, hpmcounter28, t2 69 csrrs t1, hpmcounter29, t2 70 csrrs t1, hpmcounter30, t2 71 csrrs t1, hpmcounter31, t2 72 csrrs t1, cycleh, t2 73 csrrs t1, timeh, t2 74 csrrs t1, instreth, t2 75 csrrs t1, hpmcounter3h, t2 76 csrrs t1, hpmcounter4h, t2 77 csrrs t1, hpmcounter5h, t2 78 csrrs t1, hpmcounter6h, t2 79 csrrs t1, hpmcounter7h, t2 80 csrrs t1, hpmcounter8h, t2 81 csrrs t1, hpmcounter9h, t2 82 csrrs t1, hpmcounter10h, t2 83 csrrs t1, hpmcounter11h, t2 84 csrrs t1, hpmcounter12h, t2 85 csrrs t1, hpmcounter13h, t2 86 csrrs t1, hpmcounter14h, t2 87 csrrs t1, hpmcounter15h, t2 88 csrrs t1, hpmcounter16h, t2 89 csrrs t1, hpmcounter17h, t2 90 csrrs t1, hpmcounter18h, t2 91 csrrs t1, hpmcounter19h, t2 92 csrrs t1, hpmcounter20h, t2 93 csrrs t1, hpmcounter21h, t2 94 csrrs t1, hpmcounter22h, t2 95 csrrs t1, hpmcounter23h, t2 96 csrrs t1, hpmcounter24h, t2 97 csrrs t1, hpmcounter25h, t2 98 csrrs t1, hpmcounter26h, t2 99 csrrs t1, hpmcounter27h, t2 100 csrrs t1, hpmcounter28h, t2 101 csrrs t1, hpmcounter29h, t2 102 csrrs t1, hpmcounter30h, t2 103 csrrs t1, hpmcounter31h, t2 104 /* Supervisor Trap Status */ 105 csrrs t1, sstatus, t2 106 csrrs t1, sedeleg, t2 107 csrrs t1, sideleg, t2 108 csrrs t1, sie, t2 109 csrrs t1, stvec, t2 110 csrrs t1, scounteren, t2 111 /* Supervisor Trap Handling */ 112 csrrs t1, sscratch, t2 113 csrrs t1, sepc, t2 114 csrrs t1, scause, t2 115 csrrs t1, stval, t2 116 csrrs t1, sip, t2 117 /* Supervisor Protection and Translation */ 118 csrrs t1, satp, t2 119 /* Machine Information Registers */ 120 csrrs t1, mvendorid, t2 121 csrrs t1, marchid, t2 122 csrrs t1, mimpid, t2 123 csrrs t1, mhartid, t2 124 /* Machine Trap Setup */ 125 csrrs t1, mstatus, t2 126 csrrs t1, misa, t2 127 csrrs t1, medeleg, t2 128 csrrs t1, mideleg, t2 129 csrrs t1, mie, t2 130 csrrs t1, mtvec, t2 131 csrrs t1, mcounteren, t2 132 /* Machine Trap Handling */ 133 csrrs t1, mscratch, t2 134 csrrs t1, mepc, t2 135 csrrs t1, mcause, t2 136 csrrs t1, mtval, t2 137 csrrs t1, mip, t2 138 /* Machine Protection and Translation */ 139 csrrs t1, pmpcfg0, t2 140 csrrs t1, pmpcfg1, t2 141 csrrs t1, pmpcfg2, t2 142 csrrs t1, pmpcfg3, t2 143 csrrs t1, pmpaddr0, t2 144 csrrs t1, pmpaddr1, t2 145 csrrs t1, pmpaddr2, t2 146 csrrs t1, pmpaddr3, t2 147 csrrs t1, pmpaddr4, t2 148 csrrs t1, pmpaddr5, t2 149 csrrs t1, pmpaddr6, t2 150 csrrs t1, pmpaddr7, t2 151 csrrs t1, pmpaddr8, t2 152 csrrs t1, pmpaddr9, t2 153 csrrs t1, pmpaddr10, t2 154 csrrs t1, pmpaddr11, t2 155 csrrs t1, pmpaddr12, t2 156 csrrs t1, pmpaddr13, t2 157 csrrs t1, pmpaddr14, t2 158 csrrs t1, pmpaddr15, t2 159 /* 160 * Various instr variants 161 */ 162 csrrs t1, ustatus, t2 163 csrrw t1, uie, t2 164 csrrc t1, utvec, t2 165 csrrwi t1, uscratch, 0x17 166 csrrsi t1, uepc, 0x16 167 csrrci t1, ucause, 0x15 168.size libdis_test, [.-libdis_test] 169