1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2022 Oxide Computer Company 14 */ 15 16 /* 17 * This provides a few different examples of how we take into account the DRAM 18 * hole. There are three primary cases to consider: 19 * 20 * o Taking it into account when determine if DRAM is valid or not. 21 * o Taking it into account when we do address interleaving (DFv4) 22 * o Taking it into account when performing normalization. 23 */ 24 25 #include "zen_umc_test.h" 26 27 /* 28 * This is a standard application of the DRAM hole starting at 2 GiB in the 29 * space. This follows the DFv3 rules. 30 */ 31 static const zen_umc_t zen_umc_hole_dfv3 = { 32 .umc_tom = 2ULL * 1024ULL * 1024ULL * 1024ULL, 33 .umc_tom2 = 68ULL * 1024ULL * 1024ULL * 1024ULL, 34 .umc_df_rev = DF_REV_3, 35 .umc_decomp = { 36 .dfd_sock_mask = 0x01, 37 .dfd_die_mask = 0x00, 38 .dfd_node_mask = 0x20, 39 .dfd_comp_mask = 0x1f, 40 .dfd_sock_shift = 0, 41 .dfd_die_shift = 0, 42 .dfd_node_shift = 5, 43 .dfd_comp_shift = 0 44 }, 45 .umc_ndfs = 1, 46 .umc_dfs = { { 47 .zud_flags = ZEN_UMC_DF_F_HOLE_VALID, 48 .zud_dfno = 0, 49 .zud_dram_nrules = 1, 50 .zud_nchan = 4, 51 .zud_cs_nremap = 0, 52 .zud_hole_base = 0x80000000, 53 .zud_rules = { { 54 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_HOLE, 55 .ddr_base = 0, 56 .ddr_limit = 68ULL * 1024ULL * 1024ULL * 1024ULL, 57 .ddr_dest_fabid = 0, 58 .ddr_sock_ileave_bits = 0, 59 .ddr_die_ileave_bits = 0, 60 .ddr_addr_start = 9, 61 .ddr_chan_ileave = DF_CHAN_ILEAVE_4CH 62 } }, 63 .zud_chan = { { 64 .chan_flags = UMC_CHAN_F_ECC_EN, 65 .chan_fabid = 0, 66 .chan_instid = 0, 67 .chan_logid = 0, 68 .chan_nrules = 1, 69 .chan_rules = { { 70 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_HOLE, 71 .ddr_base = 0, 72 .ddr_limit = 68ULL * 1024ULL * 1024ULL * 73 1024ULL, 74 .ddr_dest_fabid = 0, 75 .ddr_sock_ileave_bits = 0, 76 .ddr_die_ileave_bits = 0, 77 .ddr_addr_start = 9, 78 .ddr_chan_ileave = DF_CHAN_ILEAVE_4CH 79 } }, 80 .chan_dimms = { { 81 .ud_flags = UMC_DIMM_F_VALID, 82 .ud_width = UMC_DIMM_W_X4, 83 .ud_type = UMC_DIMM_T_DDR4, 84 .ud_kind = UMC_DIMM_K_RDIMM, 85 .ud_dimmno = 0, 86 .ud_cs = { { 87 .ucs_base = { 88 .udb_base = 0, 89 .udb_valid = B_TRUE 90 }, 91 .ucs_base_mask = 0x3ffffffff, 92 .ucs_nbanks = 0x4, 93 .ucs_ncol = 0xa, 94 .ucs_nrow_lo = 0x11, 95 .ucs_nbank_groups = 0x2, 96 .ucs_row_hi_bit = 0x18, 97 .ucs_row_low_bit = 0x11, 98 .ucs_bank_bits = { 0xf, 0x10, 0xd, 99 0xe }, 100 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 101 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 102 } } 103 } }, 104 }, { 105 .chan_flags = UMC_CHAN_F_ECC_EN, 106 .chan_fabid = 1, 107 .chan_instid = 1, 108 .chan_logid = 1, 109 .chan_nrules = 1, 110 .chan_rules = { { 111 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_HOLE, 112 .ddr_base = 0, 113 .ddr_limit = 68ULL * 1024ULL * 1024ULL * 114 1024ULL, 115 .ddr_dest_fabid = 0, 116 .ddr_sock_ileave_bits = 0, 117 .ddr_die_ileave_bits = 0, 118 .ddr_addr_start = 9, 119 .ddr_chan_ileave = DF_CHAN_ILEAVE_4CH 120 } }, 121 .chan_dimms = { { 122 .ud_flags = UMC_DIMM_F_VALID, 123 .ud_width = UMC_DIMM_W_X4, 124 .ud_type = UMC_DIMM_T_DDR4, 125 .ud_kind = UMC_DIMM_K_RDIMM, 126 .ud_dimmno = 0, 127 .ud_cs = { { 128 .ucs_base = { 129 .udb_base = 0, 130 .udb_valid = B_TRUE 131 }, 132 .ucs_base_mask = 0x3ffffffff, 133 .ucs_nbanks = 0x4, 134 .ucs_ncol = 0xa, 135 .ucs_nrow_lo = 0x11, 136 .ucs_nbank_groups = 0x2, 137 .ucs_row_hi_bit = 0x18, 138 .ucs_row_low_bit = 0x11, 139 .ucs_bank_bits = { 0xf, 0x10, 0xd, 140 0xe }, 141 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 142 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 143 } } 144 } }, 145 }, { 146 .chan_flags = UMC_CHAN_F_ECC_EN, 147 .chan_fabid = 2, 148 .chan_instid = 2, 149 .chan_logid = 2, 150 .chan_nrules = 1, 151 .chan_rules = { { 152 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_HOLE, 153 .ddr_base = 0, 154 .ddr_limit = 68ULL * 1024ULL * 1024ULL * 155 1024ULL, 156 .ddr_dest_fabid = 0, 157 .ddr_sock_ileave_bits = 0, 158 .ddr_die_ileave_bits = 0, 159 .ddr_addr_start = 9, 160 .ddr_chan_ileave = DF_CHAN_ILEAVE_4CH 161 } }, 162 .chan_dimms = { { 163 .ud_flags = UMC_DIMM_F_VALID, 164 .ud_width = UMC_DIMM_W_X4, 165 .ud_type = UMC_DIMM_T_DDR4, 166 .ud_kind = UMC_DIMM_K_RDIMM, 167 .ud_dimmno = 0, 168 .ud_cs = { { 169 .ucs_base = { 170 .udb_base = 0, 171 .udb_valid = B_TRUE 172 }, 173 .ucs_base_mask = 0x3ffffffff, 174 .ucs_nbanks = 0x4, 175 .ucs_ncol = 0xa, 176 .ucs_nrow_lo = 0x11, 177 .ucs_nbank_groups = 0x2, 178 .ucs_row_hi_bit = 0x18, 179 .ucs_row_low_bit = 0x11, 180 .ucs_bank_bits = { 0xf, 0x10, 0xd, 181 0xe }, 182 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 183 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 184 } } 185 } }, 186 }, { 187 .chan_flags = UMC_CHAN_F_ECC_EN, 188 .chan_fabid = 3, 189 .chan_instid = 3, 190 .chan_logid = 3, 191 .chan_nrules = 1, 192 .chan_rules = { { 193 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_HOLE, 194 .ddr_base = 0, 195 .ddr_limit = 68ULL * 1024ULL * 1024ULL * 196 1024ULL, 197 .ddr_dest_fabid = 0, 198 .ddr_sock_ileave_bits = 0, 199 .ddr_die_ileave_bits = 0, 200 .ddr_addr_start = 9, 201 .ddr_chan_ileave = DF_CHAN_ILEAVE_4CH 202 } }, 203 .chan_dimms = { { 204 .ud_flags = UMC_DIMM_F_VALID, 205 .ud_width = UMC_DIMM_W_X4, 206 .ud_type = UMC_DIMM_T_DDR4, 207 .ud_kind = UMC_DIMM_K_RDIMM, 208 .ud_dimmno = 0, 209 .ud_cs = { { 210 .ucs_base = { 211 .udb_base = 0, 212 .udb_valid = B_TRUE 213 }, 214 .ucs_base_mask = 0x3ffffffff, 215 .ucs_nbanks = 0x4, 216 .ucs_ncol = 0xa, 217 .ucs_nrow_lo = 0x11, 218 .ucs_nbank_groups = 0x2, 219 .ucs_row_hi_bit = 0x18, 220 .ucs_row_low_bit = 0x11, 221 .ucs_bank_bits = { 0xf, 0x10, 0xd, 222 0xe }, 223 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 224 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 225 } } 226 } }, 227 } } 228 } } 229 }; 230 231 /* 232 * This case is a little insidious to be honest. Here we're using a DFv4 style 233 * DRAM hole. Technically the hole needs to be taken into account before 234 * interleaving here (unlike DFv3). So we shrink the hole's size to 4 KiB and 235 * set up interleaving at address 12. This ensures that stuff around the hole 236 * will catch this and adjust for interleve. Yes, this is smaller than the hole 237 * is allowed to be in hardware, but here we're all just integers. Basically the 238 * whole covers the last 4 KiB of low memory. We use hex here to make these 239 * easier to deal with. 240 */ 241 static const zen_umc_t zen_umc_hole_dfv4 = { 242 .umc_tom = 0xfffff000, 243 .umc_tom2 = 0x1000001000, 244 .umc_df_rev = DF_REV_4, 245 .umc_decomp = { 246 .dfd_sock_mask = 0x01, 247 .dfd_die_mask = 0x00, 248 .dfd_node_mask = 0x20, 249 .dfd_comp_mask = 0x1f, 250 .dfd_sock_shift = 0, 251 .dfd_die_shift = 0, 252 .dfd_node_shift = 5, 253 .dfd_comp_shift = 0 254 }, 255 .umc_ndfs = 1, 256 .umc_dfs = { { 257 .zud_flags = ZEN_UMC_DF_F_HOLE_VALID, 258 .zud_dfno = 0, 259 .zud_dram_nrules = 1, 260 .zud_nchan = 4, 261 .zud_cs_nremap = 0, 262 .zud_hole_base = 0xfffff000, 263 .zud_rules = { { 264 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_HOLE, 265 .ddr_base = 0, 266 .ddr_limit = 0x1000001000, 267 .ddr_dest_fabid = 0, 268 .ddr_sock_ileave_bits = 0, 269 .ddr_die_ileave_bits = 0, 270 .ddr_addr_start = 12, 271 .ddr_chan_ileave = DF_CHAN_ILEAVE_4CH 272 } }, 273 .zud_chan = { { 274 .chan_flags = UMC_CHAN_F_ECC_EN, 275 .chan_fabid = 0, 276 .chan_instid = 0, 277 .chan_logid = 0, 278 .chan_nrules = 1, 279 .chan_rules = { { 280 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_HOLE, 281 .ddr_base = 0, 282 .ddr_limit = 0x1000001000, 283 .ddr_dest_fabid = 0, 284 .ddr_sock_ileave_bits = 0, 285 .ddr_die_ileave_bits = 0, 286 .ddr_addr_start = 12, 287 .ddr_chan_ileave = DF_CHAN_ILEAVE_4CH 288 } }, 289 .chan_dimms = { { 290 .ud_flags = UMC_DIMM_F_VALID, 291 .ud_width = UMC_DIMM_W_X4, 292 .ud_type = UMC_DIMM_T_DDR4, 293 .ud_kind = UMC_DIMM_K_RDIMM, 294 .ud_dimmno = 0, 295 .ud_cs = { { 296 .ucs_base = { 297 .udb_base = 0, 298 .udb_valid = B_TRUE 299 }, 300 .ucs_base_mask = 0x3ffffffff, 301 .ucs_nbanks = 0x4, 302 .ucs_ncol = 0xa, 303 .ucs_nrow_lo = 0x11, 304 .ucs_nbank_groups = 0x2, 305 .ucs_row_hi_bit = 0x18, 306 .ucs_row_low_bit = 0x11, 307 .ucs_bank_bits = { 0xf, 0x10, 0xd, 308 0xe }, 309 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 310 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 311 } } 312 } }, 313 }, { 314 .chan_flags = UMC_CHAN_F_ECC_EN, 315 .chan_fabid = 1, 316 .chan_instid = 1, 317 .chan_logid = 1, 318 .chan_nrules = 1, 319 .chan_rules = { { 320 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_HOLE, 321 .ddr_base = 0, 322 .ddr_limit = 0x1000001000, 323 .ddr_dest_fabid = 0, 324 .ddr_sock_ileave_bits = 0, 325 .ddr_die_ileave_bits = 0, 326 .ddr_addr_start = 12, 327 .ddr_chan_ileave = DF_CHAN_ILEAVE_4CH 328 } }, 329 .chan_dimms = { { 330 .ud_flags = UMC_DIMM_F_VALID, 331 .ud_width = UMC_DIMM_W_X4, 332 .ud_type = UMC_DIMM_T_DDR4, 333 .ud_kind = UMC_DIMM_K_RDIMM, 334 .ud_dimmno = 0, 335 .ud_cs = { { 336 .ucs_base = { 337 .udb_base = 0, 338 .udb_valid = B_TRUE 339 }, 340 .ucs_base_mask = 0x3ffffffff, 341 .ucs_nbanks = 0x4, 342 .ucs_ncol = 0xa, 343 .ucs_nrow_lo = 0x11, 344 .ucs_nbank_groups = 0x2, 345 .ucs_row_hi_bit = 0x18, 346 .ucs_row_low_bit = 0x11, 347 .ucs_bank_bits = { 0xf, 0x10, 0xd, 348 0xe }, 349 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 350 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 351 } } 352 } }, 353 }, { 354 .chan_flags = UMC_CHAN_F_ECC_EN, 355 .chan_fabid = 2, 356 .chan_instid = 2, 357 .chan_logid = 2, 358 .chan_nrules = 1, 359 .chan_rules = { { 360 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_HOLE, 361 .ddr_base = 0, 362 .ddr_limit = 0x1000001000, 363 .ddr_dest_fabid = 0, 364 .ddr_sock_ileave_bits = 0, 365 .ddr_die_ileave_bits = 0, 366 .ddr_addr_start = 12, 367 .ddr_chan_ileave = DF_CHAN_ILEAVE_4CH 368 } }, 369 .chan_dimms = { { 370 .ud_flags = UMC_DIMM_F_VALID, 371 .ud_width = UMC_DIMM_W_X4, 372 .ud_type = UMC_DIMM_T_DDR4, 373 .ud_kind = UMC_DIMM_K_RDIMM, 374 .ud_dimmno = 0, 375 .ud_cs = { { 376 .ucs_base = { 377 .udb_base = 0, 378 .udb_valid = B_TRUE 379 }, 380 .ucs_base_mask = 0x3ffffffff, 381 .ucs_nbanks = 0x4, 382 .ucs_ncol = 0xa, 383 .ucs_nrow_lo = 0x11, 384 .ucs_nbank_groups = 0x2, 385 .ucs_row_hi_bit = 0x18, 386 .ucs_row_low_bit = 0x11, 387 .ucs_bank_bits = { 0xf, 0x10, 0xd, 388 0xe }, 389 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 390 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 391 } } 392 } }, 393 }, { 394 .chan_flags = UMC_CHAN_F_ECC_EN, 395 .chan_fabid = 3, 396 .chan_instid = 3, 397 .chan_logid = 3, 398 .chan_nrules = 1, 399 .chan_rules = { { 400 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_HOLE, 401 .ddr_base = 0, 402 .ddr_limit = 0x1000001000, 403 .ddr_dest_fabid = 0, 404 .ddr_sock_ileave_bits = 0, 405 .ddr_die_ileave_bits = 0, 406 .ddr_addr_start = 12, 407 .ddr_chan_ileave = DF_CHAN_ILEAVE_4CH 408 } }, 409 .chan_dimms = { { 410 .ud_flags = UMC_DIMM_F_VALID, 411 .ud_width = UMC_DIMM_W_X4, 412 .ud_type = UMC_DIMM_T_DDR4, 413 .ud_kind = UMC_DIMM_K_RDIMM, 414 .ud_dimmno = 0, 415 .ud_cs = { { 416 .ucs_base = { 417 .udb_base = 0, 418 .udb_valid = B_TRUE 419 }, 420 .ucs_base_mask = 0x3ffffffff, 421 .ucs_nbanks = 0x4, 422 .ucs_ncol = 0xa, 423 .ucs_nrow_lo = 0x11, 424 .ucs_nbank_groups = 0x2, 425 .ucs_row_hi_bit = 0x18, 426 .ucs_row_low_bit = 0x11, 427 .ucs_bank_bits = { 0xf, 0x10, 0xd, 428 0xe }, 429 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 430 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 431 } } 432 } }, 433 } } 434 } } 435 }; 436 437 438 const umc_decode_test_t zen_umc_test_hole[] = { { 439 .udt_desc = "Memory in hole doesn't decode (0)", 440 .udt_umc = &zen_umc_hole_dfv3, 441 .udt_pa = 0xb0000000, 442 .udt_pass = B_FALSE, 443 .udt_fail = ZEN_UMC_DECODE_F_OUTSIDE_DRAM 444 }, { 445 .udt_desc = "Memory in hole doesn't decode (1)", 446 .udt_umc = &zen_umc_hole_dfv3, 447 .udt_pa = 0x80000000, 448 .udt_pass = B_FALSE, 449 .udt_fail = ZEN_UMC_DECODE_F_OUTSIDE_DRAM 450 }, { 451 .udt_desc = "Memory in hole doesn't decode (2)", 452 .udt_umc = &zen_umc_hole_dfv3, 453 .udt_pa = 0xffffffff, 454 .udt_pass = B_FALSE, 455 .udt_fail = ZEN_UMC_DECODE_F_OUTSIDE_DRAM 456 }, { 457 .udt_desc = "Memory in hole doesn't decode (3)", 458 .udt_umc = &zen_umc_hole_dfv3, 459 .udt_pa = 0xcba89754, 460 .udt_pass = B_FALSE, 461 .udt_fail = ZEN_UMC_DECODE_F_OUTSIDE_DRAM 462 }, { 463 .udt_desc = "DRAM Hole DFv3 4ch (0)", 464 .udt_umc = &zen_umc_hole_dfv3, 465 .udt_pa = 0x7fffffff, 466 .udt_pass = B_TRUE, 467 .udt_norm_addr = 0x1fffffff, 468 .udt_sock = 0, 469 .udt_die = 0, 470 .udt_comp = 3, 471 .udt_dimm_no = 0, 472 .udt_dimm_col = 0x3ff, 473 .udt_dimm_row = 0xfff, 474 .udt_dimm_bank = 3, 475 .udt_dimm_bank_group = 3, 476 .udt_dimm_subchan = 0, 477 .udt_dimm_rm = 0, 478 .udt_dimm_cs = 0 479 }, { 480 .udt_desc = "DRAM Hole DFv3 4ch (1)", 481 .udt_umc = &zen_umc_hole_dfv3, 482 .udt_pa = 0x7ffffdff, 483 .udt_pass = B_TRUE, 484 .udt_norm_addr = 0x1fffffff, 485 .udt_sock = 0, 486 .udt_die = 0, 487 .udt_comp = 2, 488 .udt_dimm_no = 0, 489 .udt_dimm_col = 0x3ff, 490 .udt_dimm_row = 0xfff, 491 .udt_dimm_bank = 3, 492 .udt_dimm_bank_group = 3, 493 .udt_dimm_subchan = 0, 494 .udt_dimm_rm = 0, 495 .udt_dimm_cs = 0 496 }, { 497 .udt_desc = "DRAM Hole DFv3 4ch (2)", 498 .udt_umc = &zen_umc_hole_dfv3, 499 .udt_pa = 0x7ffffbff, 500 .udt_pass = B_TRUE, 501 .udt_norm_addr = 0x1fffffff, 502 .udt_sock = 0, 503 .udt_die = 0, 504 .udt_comp = 1, 505 .udt_dimm_no = 0, 506 .udt_dimm_col = 0x3ff, 507 .udt_dimm_row = 0xfff, 508 .udt_dimm_bank = 3, 509 .udt_dimm_bank_group = 3, 510 .udt_dimm_subchan = 0, 511 .udt_dimm_rm = 0, 512 .udt_dimm_cs = 0 513 }, { 514 .udt_desc = "DRAM Hole DFv3 4ch (3)", 515 .udt_umc = &zen_umc_hole_dfv3, 516 .udt_pa = 0x7ffff9ff, 517 .udt_pass = B_TRUE, 518 .udt_norm_addr = 0x1fffffff, 519 .udt_sock = 0, 520 .udt_die = 0, 521 .udt_comp = 0, 522 .udt_dimm_no = 0, 523 .udt_dimm_col = 0x3ff, 524 .udt_dimm_row = 0xfff, 525 .udt_dimm_bank = 3, 526 .udt_dimm_bank_group = 3, 527 .udt_dimm_subchan = 0, 528 .udt_dimm_rm = 0, 529 .udt_dimm_cs = 0 530 }, { 531 .udt_desc = "DRAM Hole DFv3 4ch (4)", 532 .udt_umc = &zen_umc_hole_dfv3, 533 .udt_pa = 0x100000000, 534 .udt_pass = B_TRUE, 535 .udt_norm_addr = 0x20000000, 536 .udt_sock = 0, 537 .udt_die = 0, 538 .udt_comp = 0, 539 .udt_dimm_no = 0, 540 .udt_dimm_col = 0x0, 541 .udt_dimm_row = 0x1000, 542 .udt_dimm_bank = 0, 543 .udt_dimm_bank_group = 0, 544 .udt_dimm_subchan = 0, 545 .udt_dimm_rm = 0, 546 .udt_dimm_cs = 0 547 }, { 548 .udt_desc = "DRAM Hole DFv3 4ch (5)", 549 .udt_umc = &zen_umc_hole_dfv3, 550 .udt_pa = 0x100000200, 551 .udt_pass = B_TRUE, 552 .udt_norm_addr = 0x20000000, 553 .udt_sock = 0, 554 .udt_die = 0, 555 .udt_comp = 1, 556 .udt_dimm_no = 0, 557 .udt_dimm_col = 0x0, 558 .udt_dimm_row = 0x1000, 559 .udt_dimm_bank = 0, 560 .udt_dimm_bank_group = 0, 561 .udt_dimm_subchan = 0, 562 .udt_dimm_rm = 0, 563 .udt_dimm_cs = 0 564 }, { 565 .udt_desc = "DRAM Hole DFv3 4ch (6)", 566 .udt_umc = &zen_umc_hole_dfv3, 567 .udt_pa = 0x100000400, 568 .udt_pass = B_TRUE, 569 .udt_norm_addr = 0x20000000, 570 .udt_sock = 0, 571 .udt_die = 0, 572 .udt_comp = 2, 573 .udt_dimm_no = 0, 574 .udt_dimm_col = 0x0, 575 .udt_dimm_row = 0x1000, 576 .udt_dimm_bank = 0, 577 .udt_dimm_bank_group = 0, 578 .udt_dimm_subchan = 0, 579 .udt_dimm_rm = 0, 580 .udt_dimm_cs = 0 581 }, { 582 .udt_desc = "DRAM Hole DFv3 4ch (7)", 583 .udt_umc = &zen_umc_hole_dfv3, 584 .udt_pa = 0x100000600, 585 .udt_pass = B_TRUE, 586 .udt_norm_addr = 0x20000000, 587 .udt_sock = 0, 588 .udt_die = 0, 589 .udt_comp = 3, 590 .udt_dimm_no = 0, 591 .udt_dimm_col = 0x0, 592 .udt_dimm_row = 0x1000, 593 .udt_dimm_bank = 0, 594 .udt_dimm_bank_group = 0, 595 .udt_dimm_subchan = 0, 596 .udt_dimm_rm = 0, 597 .udt_dimm_cs = 0 598 }, { 599 .udt_desc = "DRAM Hole DFv4 4ch Shenanigans (0)", 600 .udt_umc = &zen_umc_hole_dfv4, 601 .udt_pa = 0x100000000, 602 .udt_pass = B_TRUE, 603 .udt_norm_addr = 0x3ffff000, 604 .udt_sock = 0, 605 .udt_die = 0, 606 .udt_comp = 3, 607 .udt_dimm_no = 0, 608 .udt_dimm_col = 0x200, 609 .udt_dimm_row = 0x1fff, 610 .udt_dimm_bank = 3, 611 .udt_dimm_bank_group = 3, 612 .udt_dimm_subchan = 0, 613 .udt_dimm_rm = 0, 614 .udt_dimm_cs = 0 615 }, { 616 .udt_desc = "DRAM Hole DFv4 4ch Shenanigans (1)", 617 .udt_umc = &zen_umc_hole_dfv4, 618 .udt_pa = 0x100001000, 619 .udt_pass = B_TRUE, 620 .udt_norm_addr = 0x40000000, 621 .udt_sock = 0, 622 .udt_die = 0, 623 .udt_comp = 0, 624 .udt_dimm_no = 0, 625 .udt_dimm_col = 0x0, 626 .udt_dimm_row = 0x2000, 627 .udt_dimm_bank = 0, 628 .udt_dimm_bank_group = 0, 629 .udt_dimm_subchan = 0, 630 .udt_dimm_rm = 0, 631 .udt_dimm_cs = 0 632 }, { 633 .udt_desc = "DRAM Hole DFv4 4ch Shenanigans (2)", 634 .udt_umc = &zen_umc_hole_dfv4, 635 .udt_pa = 0x100002000, 636 .udt_pass = B_TRUE, 637 .udt_norm_addr = 0x40000000, 638 .udt_sock = 0, 639 .udt_die = 0, 640 .udt_comp = 1, 641 .udt_dimm_no = 0, 642 .udt_dimm_col = 0x0, 643 .udt_dimm_row = 0x2000, 644 .udt_dimm_bank = 0, 645 .udt_dimm_bank_group = 0, 646 .udt_dimm_subchan = 0, 647 .udt_dimm_rm = 0, 648 .udt_dimm_cs = 0 649 }, { 650 .udt_desc = "DRAM Hole DFv4 4ch Shenanigans (3)", 651 .udt_umc = &zen_umc_hole_dfv4, 652 .udt_pa = 0x100003000, 653 .udt_pass = B_TRUE, 654 .udt_norm_addr = 0x40000000, 655 .udt_sock = 0, 656 .udt_die = 0, 657 .udt_comp = 2, 658 .udt_dimm_no = 0, 659 .udt_dimm_col = 0x0, 660 .udt_dimm_row = 0x2000, 661 .udt_dimm_bank = 0, 662 .udt_dimm_bank_group = 0, 663 .udt_dimm_subchan = 0, 664 .udt_dimm_rm = 0, 665 .udt_dimm_cs = 0 666 }, { 667 .udt_desc = NULL 668 } }; 669