1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2022 Oxide Computer Company 14 */ 15 16 /* 17 * Here we try to test a few variants of the Zen 3 COD based hashing, including 18 * our favorite 6 channel. These all use DFv3 and 1 DPC 16 GiB channels without 19 * any internal hashing (that is tested elsewhere). 20 */ 21 22 #include "zen_umc_test.h" 23 24 /* 25 * This is a basic 4-channel hash, sending us out to one of four locations. This 26 * enables hashing in all three regions because 6 channel variant does not seem 27 * to use them. 28 */ 29 static const zen_umc_t zen_umc_cod_4ch = { 30 .umc_tom = 4ULL * 1024ULL * 1024ULL * 1024ULL, 31 .umc_tom2 = 64ULL * 1024ULL * 1024ULL * 1024ULL, 32 .umc_df_rev = DF_REV_3, 33 .umc_decomp = { 34 .dfd_sock_mask = 0x01, 35 .dfd_die_mask = 0x00, 36 .dfd_node_mask = 0x20, 37 .dfd_comp_mask = 0x1f, 38 .dfd_sock_shift = 0, 39 .dfd_die_shift = 0, 40 .dfd_node_shift = 5, 41 .dfd_comp_shift = 0 42 }, 43 .umc_ndfs = 1, 44 .umc_dfs = { { 45 .zud_dfno = 0, 46 .zud_dram_nrules = 1, 47 .zud_nchan = 4, 48 .zud_cs_nremap = 0, 49 .zud_hole_base = 0, 50 .zud_rules = { { 51 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_HASH_16_18 | 52 DF_DRAM_F_HASH_21_23 | DF_DRAM_F_HASH_30_32, 53 .ddr_base = 0, 54 .ddr_limit = 64ULL * 1024ULL * 1024ULL * 1024ULL, 55 .ddr_dest_fabid = 0, 56 .ddr_sock_ileave_bits = 0, 57 .ddr_die_ileave_bits = 0, 58 .ddr_addr_start = 9, 59 .ddr_chan_ileave = DF_CHAN_ILEAVE_COD2_4CH 60 } }, 61 .zud_chan = { { 62 .chan_flags = UMC_CHAN_F_ECC_EN, 63 .chan_fabid = 0, 64 .chan_instid = 0, 65 .chan_logid = 0, 66 .chan_nrules = 1, 67 .chan_rules = { { 68 .ddr_flags = DF_DRAM_F_VALID | 69 DF_DRAM_F_HASH_16_18 | 70 DF_DRAM_F_HASH_21_23 | 71 DF_DRAM_F_HASH_30_32, 72 .ddr_base = 0, 73 .ddr_limit = 64ULL * 1024ULL * 1024ULL * 74 1024ULL, 75 .ddr_dest_fabid = 0, 76 .ddr_sock_ileave_bits = 0, 77 .ddr_die_ileave_bits = 0, 78 .ddr_addr_start = 9, 79 .ddr_chan_ileave = DF_CHAN_ILEAVE_COD2_4CH 80 } }, 81 .chan_dimms = { { 82 .ud_flags = UMC_DIMM_F_VALID, 83 .ud_width = UMC_DIMM_W_X4, 84 .ud_type = UMC_DIMM_T_DDR4, 85 .ud_kind = UMC_DIMM_K_RDIMM, 86 .ud_dimmno = 0, 87 .ud_cs = { { 88 .ucs_base = { 89 .udb_base = 0, 90 .udb_valid = B_TRUE 91 }, 92 .ucs_base_mask = 0x3ffffffff, 93 .ucs_nbanks = 0x4, 94 .ucs_ncol = 0xa, 95 .ucs_nrow_lo = 0x11, 96 .ucs_nbank_groups = 0x2, 97 .ucs_row_hi_bit = 0x18, 98 .ucs_row_low_bit = 0x11, 99 .ucs_bank_bits = { 0xf, 0x10, 0xd, 100 0xe }, 101 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 102 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 103 } } 104 } }, 105 }, { 106 .chan_flags = UMC_CHAN_F_ECC_EN, 107 .chan_fabid = 1, 108 .chan_instid = 1, 109 .chan_logid = 1, 110 .chan_nrules = 1, 111 .chan_rules = { { 112 .ddr_flags = DF_DRAM_F_VALID | 113 DF_DRAM_F_HASH_16_18 | 114 DF_DRAM_F_HASH_21_23 | 115 DF_DRAM_F_HASH_30_32, 116 .ddr_base = 0, 117 .ddr_limit = 64ULL * 1024ULL * 1024ULL * 118 1024ULL, 119 .ddr_dest_fabid = 0, 120 .ddr_sock_ileave_bits = 0, 121 .ddr_die_ileave_bits = 0, 122 .ddr_addr_start = 9, 123 .ddr_chan_ileave = DF_CHAN_ILEAVE_COD2_4CH 124 } }, 125 .chan_dimms = { { 126 .ud_flags = UMC_DIMM_F_VALID, 127 .ud_width = UMC_DIMM_W_X4, 128 .ud_type = UMC_DIMM_T_DDR4, 129 .ud_kind = UMC_DIMM_K_RDIMM, 130 .ud_dimmno = 0, 131 .ud_cs = { { 132 .ucs_base = { 133 .udb_base = 0, 134 .udb_valid = B_TRUE 135 }, 136 .ucs_base_mask = 0x3ffffffff, 137 .ucs_nbanks = 0x4, 138 .ucs_ncol = 0xa, 139 .ucs_nrow_lo = 0x11, 140 .ucs_nbank_groups = 0x2, 141 .ucs_row_hi_bit = 0x18, 142 .ucs_row_low_bit = 0x11, 143 .ucs_bank_bits = { 0xf, 0x10, 0xd, 144 0xe }, 145 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 146 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 147 } } 148 } }, 149 }, { 150 .chan_flags = UMC_CHAN_F_ECC_EN, 151 .chan_fabid = 2, 152 .chan_instid = 2, 153 .chan_logid = 2, 154 .chan_nrules = 1, 155 .chan_rules = { { 156 .ddr_flags = DF_DRAM_F_VALID | 157 DF_DRAM_F_HASH_16_18 | 158 DF_DRAM_F_HASH_21_23 | 159 DF_DRAM_F_HASH_30_32, 160 .ddr_base = 0, 161 .ddr_limit = 64ULL * 1024ULL * 1024ULL * 162 1024ULL, 163 .ddr_dest_fabid = 0, 164 .ddr_sock_ileave_bits = 0, 165 .ddr_die_ileave_bits = 0, 166 .ddr_addr_start = 9, 167 .ddr_chan_ileave = DF_CHAN_ILEAVE_COD2_4CH 168 } }, 169 .chan_dimms = { { 170 .ud_flags = UMC_DIMM_F_VALID, 171 .ud_width = UMC_DIMM_W_X4, 172 .ud_type = UMC_DIMM_T_DDR4, 173 .ud_kind = UMC_DIMM_K_RDIMM, 174 .ud_dimmno = 0, 175 .ud_cs = { { 176 .ucs_base = { 177 .udb_base = 0, 178 .udb_valid = B_TRUE 179 }, 180 .ucs_base_mask = 0x3ffffffff, 181 .ucs_nbanks = 0x4, 182 .ucs_ncol = 0xa, 183 .ucs_nrow_lo = 0x11, 184 .ucs_nbank_groups = 0x2, 185 .ucs_row_hi_bit = 0x18, 186 .ucs_row_low_bit = 0x11, 187 .ucs_bank_bits = { 0xf, 0x10, 0xd, 188 0xe }, 189 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 190 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 191 } } 192 } }, 193 }, { 194 .chan_flags = UMC_CHAN_F_ECC_EN, 195 .chan_fabid = 3, 196 .chan_instid = 3, 197 .chan_logid = 3, 198 .chan_nrules = 1, 199 .chan_rules = { { 200 .ddr_flags = DF_DRAM_F_VALID | 201 DF_DRAM_F_HASH_16_18 | 202 DF_DRAM_F_HASH_21_23 | 203 DF_DRAM_F_HASH_30_32, 204 .ddr_base = 0, 205 .ddr_limit = 64ULL * 1024ULL * 1024ULL * 206 1024ULL, 207 .ddr_dest_fabid = 0, 208 .ddr_sock_ileave_bits = 0, 209 .ddr_die_ileave_bits = 0, 210 .ddr_addr_start = 9, 211 .ddr_chan_ileave = DF_CHAN_ILEAVE_COD2_4CH 212 } }, 213 .chan_dimms = { { 214 .ud_flags = UMC_DIMM_F_VALID, 215 .ud_width = UMC_DIMM_W_X4, 216 .ud_type = UMC_DIMM_T_DDR4, 217 .ud_kind = UMC_DIMM_K_RDIMM, 218 .ud_dimmno = 0, 219 .ud_cs = { { 220 .ucs_base = { 221 .udb_base = 0, 222 .udb_valid = B_TRUE 223 }, 224 .ucs_base_mask = 0x3ffffffff, 225 .ucs_nbanks = 0x4, 226 .ucs_ncol = 0xa, 227 .ucs_nrow_lo = 0x11, 228 .ucs_nbank_groups = 0x2, 229 .ucs_row_hi_bit = 0x18, 230 .ucs_row_low_bit = 0x11, 231 .ucs_bank_bits = { 0xf, 0x10, 0xd, 232 0xe }, 233 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 234 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 235 } } 236 } }, 237 } } 238 } } 239 }; 240 241 static const zen_umc_t zen_umc_cod_6ch = { 242 .umc_tom = 4ULL * 1024ULL * 1024ULL * 1024ULL, 243 .umc_tom2 = 96ULL * 1024ULL * 1024ULL * 1024ULL, 244 .umc_df_rev = DF_REV_3, 245 .umc_decomp = { 246 .dfd_sock_mask = 0x01, 247 .dfd_die_mask = 0x00, 248 .dfd_node_mask = 0x20, 249 .dfd_comp_mask = 0x1f, 250 .dfd_sock_shift = 0, 251 .dfd_die_shift = 0, 252 .dfd_node_shift = 5, 253 .dfd_comp_shift = 0 254 }, 255 .umc_ndfs = 1, 256 .umc_dfs = { { 257 .zud_dfno = 0, 258 .zud_dram_nrules = 1, 259 .zud_nchan = 6, 260 .zud_cs_nremap = 0, 261 .zud_hole_base = 0, 262 .zud_rules = { { 263 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_HASH_21_23 | 264 DF_DRAM_F_HASH_30_32, 265 .ddr_base = 0, 266 .ddr_limit = 96ULL * 1024ULL * 1024ULL * 1024ULL, 267 .ddr_dest_fabid = 0, 268 .ddr_sock_ileave_bits = 0, 269 .ddr_die_ileave_bits = 0, 270 .ddr_addr_start = 12, 271 .ddr_chan_ileave = DF_CHAN_ILEAVE_6CH 272 } }, 273 .zud_chan = { { 274 .chan_flags = UMC_CHAN_F_ECC_EN, 275 .chan_fabid = 0, 276 .chan_instid = 0, 277 .chan_logid = 0, 278 .chan_nrules = 1, 279 .chan_np2_space0 = 21, 280 .chan_rules = { { 281 .ddr_flags = DF_DRAM_F_VALID | 282 DF_DRAM_F_HASH_21_23 | 283 DF_DRAM_F_HASH_30_32, 284 .ddr_base = 0, 285 .ddr_limit = 96ULL * 1024ULL * 1024ULL * 286 1024ULL, 287 .ddr_dest_fabid = 0, 288 .ddr_sock_ileave_bits = 0, 289 .ddr_die_ileave_bits = 0, 290 .ddr_addr_start = 12, 291 .ddr_chan_ileave = DF_CHAN_ILEAVE_6CH 292 } }, 293 .chan_dimms = { { 294 .ud_flags = UMC_DIMM_F_VALID, 295 .ud_width = UMC_DIMM_W_X4, 296 .ud_type = UMC_DIMM_T_DDR4, 297 .ud_kind = UMC_DIMM_K_RDIMM, 298 .ud_dimmno = 0, 299 .ud_cs = { { 300 .ucs_base = { 301 .udb_base = 0, 302 .udb_valid = B_TRUE 303 }, 304 .ucs_base_mask = 0x3ffffffff, 305 .ucs_nbanks = 0x4, 306 .ucs_ncol = 0xa, 307 .ucs_nrow_lo = 0x11, 308 .ucs_nbank_groups = 0x2, 309 .ucs_row_hi_bit = 0x18, 310 .ucs_row_low_bit = 0x11, 311 .ucs_bank_bits = { 0xf, 0x10, 0xd, 312 0xe }, 313 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 314 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 315 } } 316 } }, 317 }, { 318 .chan_flags = UMC_CHAN_F_ECC_EN, 319 .chan_fabid = 1, 320 .chan_instid = 1, 321 .chan_logid = 1, 322 .chan_nrules = 1, 323 .chan_np2_space0 = 21, 324 .chan_rules = { { 325 .ddr_flags = DF_DRAM_F_VALID | 326 DF_DRAM_F_HASH_21_23 | 327 DF_DRAM_F_HASH_30_32, 328 .ddr_base = 0, 329 .ddr_limit = 96ULL * 1024ULL * 1024ULL * 330 1024ULL, 331 .ddr_dest_fabid = 0, 332 .ddr_sock_ileave_bits = 0, 333 .ddr_die_ileave_bits = 0, 334 .ddr_addr_start = 12, 335 .ddr_chan_ileave = DF_CHAN_ILEAVE_6CH 336 } }, 337 .chan_dimms = { { 338 .ud_flags = UMC_DIMM_F_VALID, 339 .ud_width = UMC_DIMM_W_X4, 340 .ud_type = UMC_DIMM_T_DDR4, 341 .ud_kind = UMC_DIMM_K_RDIMM, 342 .ud_dimmno = 0, 343 .ud_cs = { { 344 .ucs_base = { 345 .udb_base = 0, 346 .udb_valid = B_TRUE 347 }, 348 .ucs_base_mask = 0x3ffffffff, 349 .ucs_nbanks = 0x4, 350 .ucs_ncol = 0xa, 351 .ucs_nrow_lo = 0x11, 352 .ucs_nbank_groups = 0x2, 353 .ucs_row_hi_bit = 0x18, 354 .ucs_row_low_bit = 0x11, 355 .ucs_bank_bits = { 0xf, 0x10, 0xd, 356 0xe }, 357 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 358 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 359 } } 360 } }, 361 }, { 362 .chan_flags = UMC_CHAN_F_ECC_EN, 363 .chan_fabid = 2, 364 .chan_instid = 2, 365 .chan_logid = 2, 366 .chan_nrules = 1, 367 .chan_np2_space0 = 21, 368 .chan_rules = { { 369 .ddr_flags = DF_DRAM_F_VALID | 370 DF_DRAM_F_HASH_21_23 | 371 DF_DRAM_F_HASH_30_32, 372 .ddr_base = 0, 373 .ddr_limit = 96ULL * 1024ULL * 1024ULL * 374 1024ULL, 375 .ddr_dest_fabid = 0, 376 .ddr_sock_ileave_bits = 0, 377 .ddr_die_ileave_bits = 0, 378 .ddr_addr_start = 12, 379 .ddr_chan_ileave = DF_CHAN_ILEAVE_6CH 380 } }, 381 .chan_dimms = { { 382 .ud_flags = UMC_DIMM_F_VALID, 383 .ud_width = UMC_DIMM_W_X4, 384 .ud_type = UMC_DIMM_T_DDR4, 385 .ud_kind = UMC_DIMM_K_RDIMM, 386 .ud_dimmno = 0, 387 .ud_cs = { { 388 .ucs_base = { 389 .udb_base = 0, 390 .udb_valid = B_TRUE 391 }, 392 .ucs_base_mask = 0x3ffffffff, 393 .ucs_nbanks = 0x4, 394 .ucs_ncol = 0xa, 395 .ucs_nrow_lo = 0x11, 396 .ucs_nbank_groups = 0x2, 397 .ucs_row_hi_bit = 0x18, 398 .ucs_row_low_bit = 0x11, 399 .ucs_bank_bits = { 0xf, 0x10, 0xd, 400 0xe }, 401 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 402 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 403 } } 404 } }, 405 }, { 406 .chan_flags = UMC_CHAN_F_ECC_EN, 407 .chan_fabid = 3, 408 .chan_instid = 3, 409 .chan_logid = 3, 410 .chan_nrules = 1, 411 .chan_np2_space0 = 21, 412 .chan_rules = { { 413 .ddr_flags = DF_DRAM_F_VALID | 414 DF_DRAM_F_HASH_21_23 | 415 DF_DRAM_F_HASH_30_32, 416 .ddr_base = 0, 417 .ddr_limit = 96ULL * 1024ULL * 1024ULL * 418 1024ULL, 419 .ddr_dest_fabid = 0, 420 .ddr_sock_ileave_bits = 0, 421 .ddr_die_ileave_bits = 0, 422 .ddr_addr_start = 12, 423 .ddr_chan_ileave = DF_CHAN_ILEAVE_6CH 424 } }, 425 .chan_dimms = { { 426 .ud_flags = UMC_DIMM_F_VALID, 427 .ud_width = UMC_DIMM_W_X4, 428 .ud_type = UMC_DIMM_T_DDR4, 429 .ud_kind = UMC_DIMM_K_RDIMM, 430 .ud_dimmno = 0, 431 .ud_cs = { { 432 .ucs_base = { 433 .udb_base = 0, 434 .udb_valid = B_TRUE 435 }, 436 .ucs_base_mask = 0x3ffffffff, 437 .ucs_nbanks = 0x4, 438 .ucs_ncol = 0xa, 439 .ucs_nrow_lo = 0x11, 440 .ucs_nbank_groups = 0x2, 441 .ucs_row_hi_bit = 0x18, 442 .ucs_row_low_bit = 0x11, 443 .ucs_bank_bits = { 0xf, 0x10, 0xd, 444 0xe }, 445 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 446 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 447 } } 448 } }, 449 }, { 450 .chan_flags = UMC_CHAN_F_ECC_EN, 451 .chan_fabid = 4, 452 .chan_instid = 4, 453 .chan_logid = 4, 454 .chan_nrules = 1, 455 .chan_np2_space0 = 21, 456 .chan_rules = { { 457 .ddr_flags = DF_DRAM_F_VALID | 458 DF_DRAM_F_HASH_21_23 | 459 DF_DRAM_F_HASH_30_32, 460 .ddr_base = 0, 461 .ddr_limit = 96ULL * 1024ULL * 1024ULL * 462 1024ULL, 463 .ddr_dest_fabid = 0, 464 .ddr_sock_ileave_bits = 0, 465 .ddr_die_ileave_bits = 0, 466 .ddr_addr_start = 12, 467 .ddr_chan_ileave = DF_CHAN_ILEAVE_6CH 468 } }, 469 .chan_dimms = { { 470 .ud_flags = UMC_DIMM_F_VALID, 471 .ud_width = UMC_DIMM_W_X4, 472 .ud_type = UMC_DIMM_T_DDR4, 473 .ud_kind = UMC_DIMM_K_RDIMM, 474 .ud_dimmno = 0, 475 .ud_cs = { { 476 .ucs_base = { 477 .udb_base = 0, 478 .udb_valid = B_TRUE 479 }, 480 .ucs_base_mask = 0x3ffffffff, 481 .ucs_nbanks = 0x4, 482 .ucs_ncol = 0xa, 483 .ucs_nrow_lo = 0x11, 484 .ucs_nbank_groups = 0x2, 485 .ucs_row_hi_bit = 0x18, 486 .ucs_row_low_bit = 0x11, 487 .ucs_bank_bits = { 0xf, 0x10, 0xd, 488 0xe }, 489 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 490 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 491 } } 492 } }, 493 }, { 494 .chan_flags = UMC_CHAN_F_ECC_EN, 495 .chan_fabid = 5, 496 .chan_instid = 5, 497 .chan_logid = 5, 498 .chan_nrules = 1, 499 .chan_np2_space0 = 21, 500 .chan_rules = { { 501 .ddr_flags = DF_DRAM_F_VALID | 502 DF_DRAM_F_HASH_21_23 | 503 DF_DRAM_F_HASH_30_32, 504 .ddr_base = 0, 505 .ddr_limit = 96ULL * 1024ULL * 1024ULL * 506 1024ULL, 507 .ddr_dest_fabid = 0, 508 .ddr_sock_ileave_bits = 0, 509 .ddr_die_ileave_bits = 0, 510 .ddr_addr_start = 12, 511 .ddr_chan_ileave = DF_CHAN_ILEAVE_6CH 512 } }, 513 .chan_dimms = { { 514 .ud_flags = UMC_DIMM_F_VALID, 515 .ud_width = UMC_DIMM_W_X4, 516 .ud_type = UMC_DIMM_T_DDR4, 517 .ud_kind = UMC_DIMM_K_RDIMM, 518 .ud_dimmno = 0, 519 .ud_cs = { { 520 .ucs_base = { 521 .udb_base = 0, 522 .udb_valid = B_TRUE 523 }, 524 .ucs_base_mask = 0x3ffffffff, 525 .ucs_nbanks = 0x4, 526 .ucs_ncol = 0xa, 527 .ucs_nrow_lo = 0x11, 528 .ucs_nbank_groups = 0x2, 529 .ucs_row_hi_bit = 0x18, 530 .ucs_row_low_bit = 0x11, 531 .ucs_bank_bits = { 0xf, 0x10, 0xd, 532 0xe }, 533 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 534 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 535 } } 536 } }, 537 } } 538 } } 539 }; 540 541 const umc_decode_test_t zen_umc_test_cod[] = { { 542 .udt_desc = "COD 4ch (0)", 543 .udt_umc = &zen_umc_cod_4ch, 544 .udt_pa = 0x1ff, 545 .udt_pass = B_TRUE, 546 .udt_norm_addr = 0x1ff, 547 .udt_sock = 0, 548 .udt_die = 0, 549 .udt_comp = 0, 550 .udt_dimm_no = 0, 551 .udt_dimm_col = 0x3f, 552 .udt_dimm_row = 0, 553 .udt_dimm_bank = 0, 554 .udt_dimm_bank_group = 0, 555 .udt_dimm_subchan = UINT8_MAX, 556 .udt_dimm_rm = 0, 557 .udt_dimm_cs = 0 558 }, { 559 .udt_desc = "COD 4ch (1)", 560 .udt_umc = &zen_umc_cod_4ch, 561 .udt_pa = 0x3ff, 562 .udt_pass = B_TRUE, 563 .udt_norm_addr = 0x1ff, 564 .udt_sock = 0, 565 .udt_die = 0, 566 .udt_comp = 1, 567 .udt_dimm_no = 0, 568 .udt_dimm_col = 0x3f, 569 .udt_dimm_row = 0, 570 .udt_dimm_bank = 0, 571 .udt_dimm_bank_group = 0, 572 .udt_dimm_subchan = UINT8_MAX, 573 .udt_dimm_rm = 0, 574 .udt_dimm_cs = 0 575 }, { 576 .udt_desc = "COD 4ch (2)", 577 .udt_umc = &zen_umc_cod_4ch, 578 .udt_pa = 0x11ff, 579 .udt_pass = B_TRUE, 580 .udt_norm_addr = 0x1ff, 581 .udt_sock = 0, 582 .udt_die = 0, 583 .udt_comp = 2, 584 .udt_dimm_no = 0, 585 .udt_dimm_col = 0x3f, 586 .udt_dimm_row = 0, 587 .udt_dimm_bank = 0, 588 .udt_dimm_bank_group = 0, 589 .udt_dimm_subchan = UINT8_MAX, 590 .udt_dimm_rm = 0, 591 .udt_dimm_cs = 0 592 }, { 593 .udt_desc = "COD 4ch (3)", 594 .udt_umc = &zen_umc_cod_4ch, 595 .udt_pa = 0x13ff, 596 .udt_pass = B_TRUE, 597 .udt_norm_addr = 0x1ff, 598 .udt_sock = 0, 599 .udt_die = 0, 600 .udt_comp = 3, 601 .udt_dimm_no = 0, 602 .udt_dimm_col = 0x3f, 603 .udt_dimm_row = 0, 604 .udt_dimm_bank = 0, 605 .udt_dimm_bank_group = 0, 606 .udt_dimm_subchan = UINT8_MAX, 607 .udt_dimm_rm = 0, 608 .udt_dimm_cs = 0 609 }, { 610 .udt_desc = "COD 4ch (4)", 611 .udt_umc = &zen_umc_cod_4ch, 612 .udt_pa = 0x101ff, 613 .udt_pass = B_TRUE, 614 .udt_norm_addr = 0x41ff, 615 .udt_sock = 0, 616 .udt_die = 0, 617 .udt_comp = 1, 618 .udt_dimm_no = 0, 619 .udt_dimm_col = 0x3f, 620 .udt_dimm_row = 0, 621 .udt_dimm_bank = 2, 622 .udt_dimm_bank_group = 0, 623 .udt_dimm_subchan = UINT8_MAX, 624 .udt_dimm_rm = 0, 625 .udt_dimm_cs = 0 626 }, { 627 .udt_desc = "COD 4ch (5)", 628 .udt_umc = &zen_umc_cod_4ch, 629 .udt_pa = 0x103ff, 630 .udt_pass = B_TRUE, 631 .udt_norm_addr = 0x41ff, 632 .udt_sock = 0, 633 .udt_die = 0, 634 .udt_comp = 0, 635 .udt_dimm_no = 0, 636 .udt_dimm_col = 0x3f, 637 .udt_dimm_row = 0, 638 .udt_dimm_bank = 2, 639 .udt_dimm_bank_group = 0, 640 .udt_dimm_subchan = UINT8_MAX, 641 .udt_dimm_rm = 0, 642 .udt_dimm_cs = 0 643 }, { 644 .udt_desc = "COD 4ch (6)", 645 .udt_umc = &zen_umc_cod_4ch, 646 .udt_pa = 0x303ff, 647 .udt_pass = B_TRUE, 648 .udt_norm_addr = 0xc1ff, 649 .udt_sock = 0, 650 .udt_die = 0, 651 .udt_comp = 2, 652 .udt_dimm_no = 0, 653 .udt_dimm_col = 0x3f, 654 .udt_dimm_row = 0, 655 .udt_dimm_bank = 2, 656 .udt_dimm_bank_group = 1, 657 .udt_dimm_subchan = UINT8_MAX, 658 .udt_dimm_rm = 0, 659 .udt_dimm_cs = 0 660 }, { 661 .udt_desc = "COD 4ch (7)", 662 .udt_umc = &zen_umc_cod_4ch, 663 .udt_pa = 0x313ff, 664 .udt_pass = B_TRUE, 665 .udt_norm_addr = 0xc1ff, 666 .udt_sock = 0, 667 .udt_die = 0, 668 .udt_comp = 0, 669 .udt_dimm_no = 0, 670 .udt_dimm_col = 0x3f, 671 .udt_dimm_row = 0, 672 .udt_dimm_bank = 2, 673 .udt_dimm_bank_group = 1, 674 .udt_dimm_subchan = UINT8_MAX, 675 .udt_dimm_rm = 0, 676 .udt_dimm_cs = 0 677 }, { 678 .udt_desc = "COD 4ch (8)", 679 .udt_umc = &zen_umc_cod_4ch, 680 .udt_pa = 0x311ff, 681 .udt_pass = B_TRUE, 682 .udt_norm_addr = 0xc1ff, 683 .udt_sock = 0, 684 .udt_die = 0, 685 .udt_comp = 1, 686 .udt_dimm_no = 0, 687 .udt_dimm_col = 0x3f, 688 .udt_dimm_row = 0, 689 .udt_dimm_bank = 2, 690 .udt_dimm_bank_group = 1, 691 .udt_dimm_subchan = UINT8_MAX, 692 .udt_dimm_rm = 0, 693 .udt_dimm_cs = 0 694 }, { 695 .udt_desc = "COD 4ch (9)", 696 .udt_umc = &zen_umc_cod_4ch, 697 .udt_pa = 0x2311ff, 698 .udt_pass = B_TRUE, 699 .udt_norm_addr = 0x8c1ff, 700 .udt_sock = 0, 701 .udt_die = 0, 702 .udt_comp = 0, 703 .udt_dimm_no = 0, 704 .udt_dimm_col = 0x3f, 705 .udt_dimm_row = 0x4, 706 .udt_dimm_bank = 2, 707 .udt_dimm_bank_group = 1, 708 .udt_dimm_subchan = UINT8_MAX, 709 .udt_dimm_rm = 0, 710 .udt_dimm_cs = 0 711 }, { 712 .udt_desc = "COD 4ch (10)", 713 .udt_umc = &zen_umc_cod_4ch, 714 .udt_pa = 0x6311ff, 715 .udt_pass = B_TRUE, 716 .udt_norm_addr = 0x18c1ff, 717 .udt_sock = 0, 718 .udt_die = 0, 719 .udt_comp = 2, 720 .udt_dimm_no = 0, 721 .udt_dimm_col = 0x3f, 722 .udt_dimm_row = 0xc, 723 .udt_dimm_bank = 2, 724 .udt_dimm_bank_group = 1, 725 .udt_dimm_subchan = UINT8_MAX, 726 .udt_dimm_rm = 0, 727 .udt_dimm_cs = 0 728 }, { 729 .udt_desc = "COD 4ch (11)", 730 .udt_umc = &zen_umc_cod_4ch, 731 .udt_pa = 0x6313ff, 732 .udt_pass = B_TRUE, 733 .udt_norm_addr = 0x18c1ff, 734 .udt_sock = 0, 735 .udt_die = 0, 736 .udt_comp = 3, 737 .udt_dimm_no = 0, 738 .udt_dimm_col = 0x3f, 739 .udt_dimm_row = 0xc, 740 .udt_dimm_bank = 2, 741 .udt_dimm_bank_group = 1, 742 .udt_dimm_subchan = UINT8_MAX, 743 .udt_dimm_rm = 0, 744 .udt_dimm_cs = 0 745 }, { 746 .udt_desc = "COD 4ch (12)", 747 .udt_umc = &zen_umc_cod_4ch, 748 .udt_pa = 0x6303ff, 749 .udt_pass = B_TRUE, 750 .udt_norm_addr = 0x18c1ff, 751 .udt_sock = 0, 752 .udt_die = 0, 753 .udt_comp = 1, 754 .udt_dimm_no = 0, 755 .udt_dimm_col = 0x3f, 756 .udt_dimm_row = 0xc, 757 .udt_dimm_bank = 2, 758 .udt_dimm_bank_group = 1, 759 .udt_dimm_subchan = UINT8_MAX, 760 .udt_dimm_rm = 0, 761 .udt_dimm_cs = 0 762 }, { 763 .udt_desc = "COD 4ch (13)", 764 .udt_umc = &zen_umc_cod_4ch, 765 .udt_pa = 0x6301ff, 766 .udt_pass = B_TRUE, 767 .udt_norm_addr = 0x18c1ff, 768 .udt_sock = 0, 769 .udt_die = 0, 770 .udt_comp = 0, 771 .udt_dimm_no = 0, 772 .udt_dimm_col = 0x3f, 773 .udt_dimm_row = 0xc, 774 .udt_dimm_bank = 2, 775 .udt_dimm_bank_group = 1, 776 .udt_dimm_subchan = UINT8_MAX, 777 .udt_dimm_rm = 0, 778 .udt_dimm_cs = 0 779 }, { 780 .udt_desc = "COD 4ch (14)", 781 .udt_umc = &zen_umc_cod_4ch, 782 .udt_pa = 0x406301ff, 783 .udt_pass = B_TRUE, 784 .udt_norm_addr = 0x1018c1ff, 785 .udt_sock = 0, 786 .udt_die = 0, 787 .udt_comp = 1, 788 .udt_dimm_no = 0, 789 .udt_dimm_col = 0x3f, 790 .udt_dimm_row = 0x80c, 791 .udt_dimm_bank = 2, 792 .udt_dimm_bank_group = 1, 793 .udt_dimm_subchan = UINT8_MAX, 794 .udt_dimm_rm = 0, 795 .udt_dimm_cs = 0 796 }, { 797 .udt_desc = "COD 4ch (15)", 798 .udt_umc = &zen_umc_cod_4ch, 799 .udt_pa = 0x406303ff, 800 .udt_pass = B_TRUE, 801 .udt_norm_addr = 0x1018c1ff, 802 .udt_sock = 0, 803 .udt_die = 0, 804 .udt_comp = 0, 805 .udt_dimm_no = 0, 806 .udt_dimm_col = 0x3f, 807 .udt_dimm_row = 0x80c, 808 .udt_dimm_bank = 2, 809 .udt_dimm_bank_group = 1, 810 .udt_dimm_subchan = UINT8_MAX, 811 .udt_dimm_rm = 0, 812 .udt_dimm_cs = 0 813 }, { 814 .udt_desc = "COD 4ch (16)", 815 .udt_umc = &zen_umc_cod_4ch, 816 .udt_pa = 0x406311ff, 817 .udt_pass = B_TRUE, 818 .udt_norm_addr = 0x1018c1ff, 819 .udt_sock = 0, 820 .udt_die = 0, 821 .udt_comp = 3, 822 .udt_dimm_no = 0, 823 .udt_dimm_col = 0x3f, 824 .udt_dimm_row = 0x80c, 825 .udt_dimm_bank = 2, 826 .udt_dimm_bank_group = 1, 827 .udt_dimm_subchan = UINT8_MAX, 828 .udt_dimm_rm = 0, 829 .udt_dimm_cs = 0 830 }, { 831 .udt_desc = "COD 4ch (17)", 832 .udt_umc = &zen_umc_cod_4ch, 833 .udt_pa = 0x406313ff, 834 .udt_pass = B_TRUE, 835 .udt_norm_addr = 0x1018c1ff, 836 .udt_sock = 0, 837 .udt_die = 0, 838 .udt_comp = 2, 839 .udt_dimm_no = 0, 840 .udt_dimm_col = 0x3f, 841 .udt_dimm_row = 0x80c, 842 .udt_dimm_bank = 2, 843 .udt_dimm_bank_group = 1, 844 .udt_dimm_subchan = UINT8_MAX, 845 .udt_dimm_rm = 0, 846 .udt_dimm_cs = 0 847 }, { 848 .udt_desc = "COD 4ch (18)", 849 .udt_umc = &zen_umc_cod_4ch, 850 .udt_pa = 0xc06313ff, 851 .udt_pass = B_TRUE, 852 .udt_norm_addr = 0x3018c1ff, 853 .udt_sock = 0, 854 .udt_die = 0, 855 .udt_comp = 0, 856 .udt_dimm_no = 0, 857 .udt_dimm_col = 0x3f, 858 .udt_dimm_row = 0x180c, 859 .udt_dimm_bank = 2, 860 .udt_dimm_bank_group = 1, 861 .udt_dimm_subchan = UINT8_MAX, 862 .udt_dimm_rm = 0, 863 .udt_dimm_cs = 0 864 }, { 865 .udt_desc = "COD 4ch (19)", 866 .udt_umc = &zen_umc_cod_4ch, 867 .udt_pa = 0xc06311ff, 868 .udt_pass = B_TRUE, 869 .udt_norm_addr = 0x3018c1ff, 870 .udt_sock = 0, 871 .udt_die = 0, 872 .udt_comp = 1, 873 .udt_dimm_no = 0, 874 .udt_dimm_col = 0x3f, 875 .udt_dimm_row = 0x180c, 876 .udt_dimm_bank = 2, 877 .udt_dimm_bank_group = 1, 878 .udt_dimm_subchan = UINT8_MAX, 879 .udt_dimm_rm = 0, 880 .udt_dimm_cs = 0 881 }, { 882 .udt_desc = "COD 4ch (20)", 883 .udt_umc = &zen_umc_cod_4ch, 884 .udt_pa = 0xc06301ff, 885 .udt_pass = B_TRUE, 886 .udt_norm_addr = 0x3018c1ff, 887 .udt_sock = 0, 888 .udt_die = 0, 889 .udt_comp = 3, 890 .udt_dimm_no = 0, 891 .udt_dimm_col = 0x3f, 892 .udt_dimm_row = 0x180c, 893 .udt_dimm_bank = 2, 894 .udt_dimm_bank_group = 1, 895 .udt_dimm_subchan = UINT8_MAX, 896 .udt_dimm_rm = 0, 897 .udt_dimm_cs = 0 898 }, { 899 .udt_desc = "COD 4ch (21)", 900 .udt_umc = &zen_umc_cod_4ch, 901 .udt_pa = 0xc06303ff, 902 .udt_pass = B_TRUE, 903 .udt_norm_addr = 0x3018c1ff, 904 .udt_sock = 0, 905 .udt_die = 0, 906 .udt_comp = 2, 907 .udt_dimm_no = 0, 908 .udt_dimm_col = 0x3f, 909 .udt_dimm_row = 0x180c, 910 .udt_dimm_bank = 2, 911 .udt_dimm_bank_group = 1, 912 .udt_dimm_subchan = UINT8_MAX, 913 .udt_dimm_rm = 0, 914 .udt_dimm_cs = 0 915 }, { 916 .udt_desc = "COD 6ch (0)", 917 .udt_umc = &zen_umc_cod_6ch, 918 .udt_pa = 0x1ff, 919 .udt_pass = B_TRUE, 920 .udt_norm_addr = 0x1ff, 921 .udt_sock = 0, 922 .udt_die = 0, 923 .udt_comp = 0, 924 .udt_dimm_no = 0, 925 .udt_dimm_col = 0x3f, 926 .udt_dimm_row = 0, 927 .udt_dimm_bank = 0, 928 .udt_dimm_bank_group = 0, 929 .udt_dimm_subchan = UINT8_MAX, 930 .udt_dimm_rm = 0, 931 .udt_dimm_cs = 0 932 }, { 933 .udt_desc = "COD 6ch (1)", 934 .udt_umc = &zen_umc_cod_6ch, 935 .udt_pa = 0x11ff, 936 .udt_pass = B_TRUE, 937 .udt_norm_addr = 0x1ff, 938 .udt_sock = 0, 939 .udt_die = 0, 940 .udt_comp = 1, 941 .udt_dimm_no = 0, 942 .udt_dimm_col = 0x3f, 943 .udt_dimm_row = 0, 944 .udt_dimm_bank = 0, 945 .udt_dimm_bank_group = 0, 946 .udt_dimm_subchan = UINT8_MAX, 947 .udt_dimm_rm = 0, 948 .udt_dimm_cs = 0 949 }, { 950 .udt_desc = "COD 6ch (2)", 951 .udt_umc = &zen_umc_cod_6ch, 952 .udt_pa = 0x21ff, 953 .udt_pass = B_TRUE, 954 .udt_norm_addr = 0x1ff, 955 .udt_sock = 0, 956 .udt_die = 0, 957 .udt_comp = 2, 958 .udt_dimm_no = 0, 959 .udt_dimm_col = 0x3f, 960 .udt_dimm_row = 0, 961 .udt_dimm_bank = 0, 962 .udt_dimm_bank_group = 0, 963 .udt_dimm_subchan = UINT8_MAX, 964 .udt_dimm_rm = 0, 965 .udt_dimm_cs = 0 966 }, { 967 .udt_desc = "COD 6ch (3)", 968 .udt_umc = &zen_umc_cod_6ch, 969 .udt_pa = 0x31ff, 970 .udt_pass = B_TRUE, 971 .udt_norm_addr = 0x1ff, 972 .udt_sock = 0, 973 .udt_die = 0, 974 .udt_comp = 3, 975 .udt_dimm_no = 0, 976 .udt_dimm_col = 0x3f, 977 .udt_dimm_row = 0, 978 .udt_dimm_bank = 0, 979 .udt_dimm_bank_group = 0, 980 .udt_dimm_subchan = UINT8_MAX, 981 .udt_dimm_rm = 0, 982 .udt_dimm_cs = 0 983 }, { 984 .udt_desc = "COD 6ch (4)", 985 .udt_umc = &zen_umc_cod_6ch, 986 .udt_pa = 0x41ff, 987 .udt_pass = B_TRUE, 988 .udt_norm_addr = 0x1ff, 989 .udt_sock = 0, 990 .udt_die = 0, 991 .udt_comp = 4, 992 .udt_dimm_no = 0, 993 .udt_dimm_col = 0x3f, 994 .udt_dimm_row = 0, 995 .udt_dimm_bank = 0, 996 .udt_dimm_bank_group = 0, 997 .udt_dimm_subchan = UINT8_MAX, 998 .udt_dimm_rm = 0, 999 .udt_dimm_cs = 0 1000 }, { 1001 .udt_desc = "COD 6ch (5)", 1002 .udt_umc = &zen_umc_cod_6ch, 1003 .udt_pa = 0x51ff, 1004 .udt_pass = B_TRUE, 1005 .udt_norm_addr = 0x1ff, 1006 .udt_sock = 0, 1007 .udt_die = 0, 1008 .udt_comp = 5, 1009 .udt_dimm_no = 0, 1010 .udt_dimm_col = 0x3f, 1011 .udt_dimm_row = 0, 1012 .udt_dimm_bank = 0, 1013 .udt_dimm_bank_group = 0, 1014 .udt_dimm_subchan = UINT8_MAX, 1015 .udt_dimm_rm = 0, 1016 .udt_dimm_cs = 0 1017 }, { 1018 .udt_desc = "COD 6ch (6)", 1019 .udt_umc = &zen_umc_cod_6ch, 1020 .udt_pa = 0x61ff, 1021 .udt_pass = B_TRUE, 1022 .udt_norm_addr = 0x3000001ff, 1023 .udt_sock = 0, 1024 .udt_die = 0, 1025 .udt_comp = 0, 1026 .udt_dimm_no = 0, 1027 .udt_dimm_col = 0x3f, 1028 .udt_dimm_row = 0x18000, 1029 .udt_dimm_bank = 0, 1030 .udt_dimm_bank_group = 0, 1031 .udt_dimm_subchan = UINT8_MAX, 1032 .udt_dimm_rm = 0, 1033 .udt_dimm_cs = 0 1034 }, { 1035 .udt_desc = "COD 6ch (7)", 1036 .udt_umc = &zen_umc_cod_6ch, 1037 .udt_pa = 0x71ff, 1038 .udt_pass = B_TRUE, 1039 .udt_norm_addr = 0x3000001ff, 1040 .udt_sock = 0, 1041 .udt_die = 0, 1042 .udt_comp = 1, 1043 .udt_dimm_no = 0, 1044 .udt_dimm_col = 0x3f, 1045 .udt_dimm_row = 0x18000, 1046 .udt_dimm_bank = 0, 1047 .udt_dimm_bank_group = 0, 1048 .udt_dimm_subchan = UINT8_MAX, 1049 .udt_dimm_rm = 0, 1050 .udt_dimm_cs = 0 1051 }, { 1052 .udt_desc = "COD 6ch (8)", 1053 .udt_umc = &zen_umc_cod_6ch, 1054 .udt_pa = 0x81ff, 1055 .udt_pass = B_TRUE, 1056 .udt_norm_addr = 0x11ff, 1057 .udt_sock = 0, 1058 .udt_die = 0, 1059 .udt_comp = 1, 1060 .udt_dimm_no = 0, 1061 .udt_dimm_col = 0x23f, 1062 .udt_dimm_row = 0, 1063 .udt_dimm_bank = 0, 1064 .udt_dimm_bank_group = 0, 1065 .udt_dimm_subchan = UINT8_MAX, 1066 .udt_dimm_rm = 0, 1067 .udt_dimm_cs = 0 1068 }, { 1069 .udt_desc = "COD 6ch (9)", 1070 .udt_umc = &zen_umc_cod_6ch, 1071 .udt_pa = 0x91ff, 1072 .udt_pass = B_TRUE, 1073 .udt_norm_addr = 0x11ff, 1074 .udt_sock = 0, 1075 .udt_die = 0, 1076 .udt_comp = 0, 1077 .udt_dimm_no = 0, 1078 .udt_dimm_col = 0x23f, 1079 .udt_dimm_row = 0, 1080 .udt_dimm_bank = 0, 1081 .udt_dimm_bank_group = 0, 1082 .udt_dimm_subchan = UINT8_MAX, 1083 .udt_dimm_rm = 0, 1084 .udt_dimm_cs = 0 1085 }, { 1086 .udt_desc = "COD 6ch (10)", 1087 .udt_umc = &zen_umc_cod_6ch, 1088 .udt_pa = 0xa1ff, 1089 .udt_pass = B_TRUE, 1090 .udt_norm_addr = 0x11ff, 1091 .udt_sock = 0, 1092 .udt_die = 0, 1093 .udt_comp = 3, 1094 .udt_dimm_no = 0, 1095 .udt_dimm_col = 0x23f, 1096 .udt_dimm_row = 0, 1097 .udt_dimm_bank = 0, 1098 .udt_dimm_bank_group = 0, 1099 .udt_dimm_subchan = UINT8_MAX, 1100 .udt_dimm_rm = 0, 1101 .udt_dimm_cs = 0 1102 }, { 1103 .udt_desc = "COD 6ch (11)", 1104 .udt_umc = &zen_umc_cod_6ch, 1105 .udt_pa = 0xb1ff, 1106 .udt_pass = B_TRUE, 1107 .udt_norm_addr = 0x11ff, 1108 .udt_sock = 0, 1109 .udt_die = 0, 1110 .udt_comp = 2, 1111 .udt_dimm_no = 0, 1112 .udt_dimm_col = 0x23f, 1113 .udt_dimm_row = 0, 1114 .udt_dimm_bank = 0, 1115 .udt_dimm_bank_group = 0, 1116 .udt_dimm_subchan = UINT8_MAX, 1117 .udt_dimm_rm = 0, 1118 .udt_dimm_cs = 0 1119 }, { 1120 .udt_desc = "COD 6ch (12)", 1121 .udt_umc = &zen_umc_cod_6ch, 1122 .udt_pa = 0xc1ff, 1123 .udt_pass = B_TRUE, 1124 .udt_norm_addr = 0x11ff, 1125 .udt_sock = 0, 1126 .udt_die = 0, 1127 .udt_comp = 5, 1128 .udt_dimm_no = 0, 1129 .udt_dimm_col = 0x23f, 1130 .udt_dimm_row = 0, 1131 .udt_dimm_bank = 0, 1132 .udt_dimm_bank_group = 0, 1133 .udt_dimm_subchan = UINT8_MAX, 1134 .udt_dimm_rm = 0, 1135 .udt_dimm_cs = 0 1136 }, { 1137 .udt_desc = "COD 6ch (13)", 1138 .udt_umc = &zen_umc_cod_6ch, 1139 .udt_pa = 0xd1ff, 1140 .udt_pass = B_TRUE, 1141 .udt_norm_addr = 0x11ff, 1142 .udt_sock = 0, 1143 .udt_die = 0, 1144 .udt_comp = 4, 1145 .udt_dimm_no = 0, 1146 .udt_dimm_col = 0x23f, 1147 .udt_dimm_row = 0, 1148 .udt_dimm_bank = 0, 1149 .udt_dimm_bank_group = 0, 1150 .udt_dimm_subchan = UINT8_MAX, 1151 .udt_dimm_rm = 0, 1152 .udt_dimm_cs = 0 1153 }, { 1154 .udt_desc = "COD 6ch (14)", 1155 .udt_umc = &zen_umc_cod_6ch, 1156 .udt_pa = 0xe1ff, 1157 .udt_pass = B_TRUE, 1158 .udt_norm_addr = 0x3000011ff, 1159 .udt_sock = 0, 1160 .udt_die = 0, 1161 .udt_comp = 3, 1162 .udt_dimm_no = 0, 1163 .udt_dimm_col = 0x23f, 1164 .udt_dimm_row = 0x18000, 1165 .udt_dimm_bank = 0, 1166 .udt_dimm_bank_group = 0, 1167 .udt_dimm_subchan = UINT8_MAX, 1168 .udt_dimm_rm = 0, 1169 .udt_dimm_cs = 0 1170 }, { 1171 .udt_desc = "COD 6ch (15)", 1172 .udt_umc = &zen_umc_cod_6ch, 1173 .udt_pa = 0xf1ff, 1174 .udt_pass = B_TRUE, 1175 .udt_norm_addr = 0x3000011ff, 1176 .udt_sock = 0, 1177 .udt_die = 0, 1178 .udt_comp = 2, 1179 .udt_dimm_no = 0, 1180 .udt_dimm_col = 0x23f, 1181 .udt_dimm_row = 0x18000, 1182 .udt_dimm_bank = 0, 1183 .udt_dimm_bank_group = 0, 1184 .udt_dimm_subchan = UINT8_MAX, 1185 .udt_dimm_rm = 0, 1186 .udt_dimm_cs = 0 1187 }, 1188 /* 1189 * The above went through and showed that we can probably hash things correctly 1190 * and account for our mod-3 case. The ones below try to find the higher level 1191 * addresses that would result in the same normalized address that we have, but 1192 * on different dies to try and complete the set. 1193 */ 1194 { 1195 .udt_desc = "COD 6ch (16)", 1196 .udt_umc = &zen_umc_cod_6ch, 1197 .udt_pa = 0x8000061ff, 1198 .udt_pass = B_TRUE, 1199 .udt_norm_addr = 0x3000001ff, 1200 .udt_sock = 0, 1201 .udt_die = 0, 1202 .udt_comp = 2, 1203 .udt_dimm_no = 0, 1204 .udt_dimm_col = 0x3f, 1205 .udt_dimm_row = 0x18000, 1206 .udt_dimm_bank = 0, 1207 .udt_dimm_bank_group = 0, 1208 .udt_dimm_subchan = UINT8_MAX, 1209 .udt_dimm_rm = 0, 1210 .udt_dimm_cs = 0 1211 }, { 1212 .udt_desc = "COD 6ch (17)", 1213 .udt_umc = &zen_umc_cod_6ch, 1214 .udt_pa = 0x8000071ff, 1215 .udt_pass = B_TRUE, 1216 .udt_norm_addr = 0x3000001ff, 1217 .udt_sock = 0, 1218 .udt_die = 0, 1219 .udt_comp = 3, 1220 .udt_dimm_no = 0, 1221 .udt_dimm_col = 0x3f, 1222 .udt_dimm_row = 0x18000, 1223 .udt_dimm_bank = 0, 1224 .udt_dimm_bank_group = 0, 1225 .udt_dimm_subchan = UINT8_MAX, 1226 .udt_dimm_rm = 0, 1227 .udt_dimm_cs = 0 1228 }, { 1229 .udt_desc = "COD 6ch (18)", 1230 .udt_umc = &zen_umc_cod_6ch, 1231 .udt_pa = 0x10000061ff, 1232 .udt_pass = B_TRUE, 1233 .udt_norm_addr = 0x3000001ff, 1234 .udt_sock = 0, 1235 .udt_die = 0, 1236 .udt_comp = 4, 1237 .udt_dimm_no = 0, 1238 .udt_dimm_col = 0x3f, 1239 .udt_dimm_row = 0x18000, 1240 .udt_dimm_bank = 0, 1241 .udt_dimm_bank_group = 0, 1242 .udt_dimm_subchan = UINT8_MAX, 1243 .udt_dimm_rm = 0, 1244 .udt_dimm_cs = 0 1245 }, { 1246 .udt_desc = "COD 6ch (19)", 1247 .udt_umc = &zen_umc_cod_6ch, 1248 .udt_pa = 0x10000071ff, 1249 .udt_pass = B_TRUE, 1250 .udt_norm_addr = 0x3000001ff, 1251 .udt_sock = 0, 1252 .udt_die = 0, 1253 .udt_comp = 5, 1254 .udt_dimm_no = 0, 1255 .udt_dimm_col = 0x3f, 1256 .udt_dimm_row = 0x18000, 1257 .udt_dimm_bank = 0, 1258 .udt_dimm_bank_group = 0, 1259 .udt_dimm_subchan = UINT8_MAX, 1260 .udt_dimm_rm = 0, 1261 .udt_dimm_cs = 0 1262 }, 1263 /* 1264 * Now with that there, we go back and show that hashing actually impacts things 1265 * as we expect. Note, the bit 0 hash was already taken into account. 1266 */ 1267 { 1268 .udt_desc = "COD 6ch (20)", 1269 .udt_umc = &zen_umc_cod_6ch, 1270 .udt_pa = 0x8001ff, 1271 .udt_pass = B_TRUE, 1272 .udt_norm_addr = 0x1001ff, 1273 .udt_sock = 0, 1274 .udt_die = 0, 1275 .udt_comp = 1, 1276 .udt_dimm_no = 0, 1277 .udt_dimm_col = 0x3f, 1278 .udt_dimm_row = 0x8, 1279 .udt_dimm_bank = 0, 1280 .udt_dimm_bank_group = 0, 1281 .udt_dimm_subchan = UINT8_MAX, 1282 .udt_dimm_rm = 0, 1283 .udt_dimm_cs = 0 1284 }, { 1285 .udt_desc = "COD 6ch (21)", 1286 .udt_umc = &zen_umc_cod_6ch, 1287 .udt_pa = 0xa001ff, 1288 .udt_pass = B_TRUE, 1289 .udt_norm_addr = 0x1401ff, 1290 .udt_sock = 0, 1291 .udt_die = 0, 1292 .udt_comp = 3, 1293 .udt_dimm_no = 0, 1294 .udt_dimm_col = 0x3f, 1295 .udt_dimm_row = 0xa, 1296 .udt_dimm_bank = 0, 1297 .udt_dimm_bank_group = 0, 1298 .udt_dimm_subchan = UINT8_MAX, 1299 .udt_dimm_rm = 0, 1300 .udt_dimm_cs = 0 1301 }, { 1302 .udt_desc = "COD 6ch (22)", 1303 .udt_umc = &zen_umc_cod_6ch, 1304 .udt_pa = 0xe001ff, 1305 .udt_pass = B_TRUE, 1306 .udt_norm_addr = 0x3001c01ff, 1307 .udt_sock = 0, 1308 .udt_die = 0, 1309 .udt_comp = 3, 1310 .udt_dimm_no = 0, 1311 .udt_dimm_col = 0x3f, 1312 .udt_dimm_row = 0x1800e, 1313 .udt_dimm_bank = 0, 1314 .udt_dimm_bank_group = 0, 1315 .udt_dimm_subchan = UINT8_MAX, 1316 .udt_dimm_rm = 0, 1317 .udt_dimm_cs = 0 1318 }, { 1319 .udt_desc = "COD 6ch (23)", 1320 .udt_umc = &zen_umc_cod_6ch, 1321 .udt_pa = 0x180e001ff, 1322 .udt_pass = B_TRUE, 1323 .udt_norm_addr = 0x301c01ff, 1324 .udt_sock = 0, 1325 .udt_die = 0, 1326 .udt_comp = 2, 1327 .udt_dimm_no = 0, 1328 .udt_dimm_col = 0x3f, 1329 .udt_dimm_row = 0x180e, 1330 .udt_dimm_bank = 0, 1331 .udt_dimm_bank_group = 0, 1332 .udt_dimm_subchan = UINT8_MAX, 1333 .udt_dimm_rm = 0, 1334 .udt_dimm_cs = 0 1335 }, { 1336 .udt_desc = "COD 6ch (24)", 1337 .udt_umc = &zen_umc_cod_6ch, 1338 .udt_pa = 0x1c0e041ff, 1339 .udt_pass = B_TRUE, 1340 .udt_norm_addr = 0x381c01ff, 1341 .udt_sock = 0, 1342 .udt_die = 0, 1343 .udt_comp = 4, 1344 .udt_dimm_no = 0, 1345 .udt_dimm_col = 0x3f, 1346 .udt_dimm_row = 0x1c0e, 1347 .udt_dimm_bank = 0, 1348 .udt_dimm_bank_group = 0, 1349 .udt_dimm_subchan = UINT8_MAX, 1350 .udt_dimm_rm = 0, 1351 .udt_dimm_cs = 0 1352 }, { 1353 .udt_desc = NULL 1354 } }; 1355