1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2022 Oxide Computer Company 14 */ 15 16 /* 17 * Here we test several different channel related test cases. In particular, we 18 * want to exercise the following situations: 19 * 20 * o Multiple DIMMs per channel (no hashing) 21 * o Multiple DIMMs per channel (chip-select interleaving) 22 * o CS Hashing 23 * o Bank Hashing 24 * o Bank Swaps 25 * o Basic sub-channel 26 * 27 * For all of these, we don't do anything special from the Data Fabric to 28 * strictly allow us to reason about the channel logic here. 29 * 30 * Currently, we do not have tests for the following because we don't have a 31 * great sense of how the AMD SoC will set this up for the decoder: 32 * 33 * o Cases where rank-multiplication and hashing are taking place 34 * o Cases where sub-channel hashing is being used 35 */ 36 37 #include "zen_umc_test.h" 38 39 /* 40 * This has two of our favorite 64 GiB DIMMs. Everything is done out linearly. 41 * Because of this, we don't apply any channel offsets. 42 */ 43 static const zen_umc_t zen_umc_chan_no_hash = { 44 .umc_tom = 4ULL * 1024ULL * 1024ULL * 1024ULL, 45 .umc_tom2 = 128ULL * 1024ULL * 1024ULL * 1024ULL, 46 .umc_df_rev = DF_REV_3, 47 /* Per milan_decomp */ 48 .umc_decomp = { 49 .dfd_sock_mask = 0x01, 50 .dfd_die_mask = 0x00, 51 .dfd_node_mask = 0x20, 52 .dfd_comp_mask = 0x1f, 53 .dfd_sock_shift = 0, 54 .dfd_die_shift = 0, 55 .dfd_node_shift = 5, 56 .dfd_comp_shift = 0 57 }, 58 .umc_ndfs = 1, 59 .umc_dfs = { { 60 .zud_dfno = 0, 61 .zud_ccm_inst = 0, 62 .zud_dram_nrules = 1, 63 .zud_nchan = 1, 64 .zud_cs_nremap = 0, 65 .zud_hole_base = 0, 66 .zud_rules = { { 67 .ddr_flags = DF_DRAM_F_VALID, 68 .ddr_base = 0, 69 .ddr_limit = 128ULL * 1024ULL * 1024ULL * 1024ULL, 70 .ddr_dest_fabid = 1, 71 .ddr_sock_ileave_bits = 0, 72 .ddr_die_ileave_bits = 0, 73 .ddr_addr_start = 9, 74 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 75 } }, 76 .zud_chan = { { 77 .chan_flags = UMC_CHAN_F_ECC_EN, 78 .chan_fabid = 1, 79 .chan_instid = 1, 80 .chan_logid = 0, 81 .chan_nrules = 1, 82 .chan_rules = { { 83 .ddr_flags = DF_DRAM_F_VALID, 84 .ddr_base = 0, 85 .ddr_limit = 128ULL * 1024ULL * 1024ULL * 86 1024ULL, 87 .ddr_dest_fabid = 1, 88 .ddr_sock_ileave_bits = 0, 89 .ddr_die_ileave_bits = 0, 90 .ddr_addr_start = 9, 91 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 92 } }, 93 .chan_dimms = { { 94 .ud_flags = UMC_DIMM_F_VALID, 95 .ud_width = UMC_DIMM_W_X4, 96 .ud_type = UMC_DIMM_T_DDR4, 97 .ud_kind = UMC_DIMM_K_RDIMM, 98 .ud_dimmno = 0, 99 .ud_cs = { { 100 .ucs_base = { 101 .udb_base = 0, 102 .udb_valid = B_TRUE 103 }, 104 .ucs_base_mask = 0x7ffffffff, 105 .ucs_nbanks = 0x4, 106 .ucs_ncol = 0xa, 107 .ucs_nrow_lo = 0x12, 108 .ucs_nbank_groups = 0x2, 109 .ucs_row_hi_bit = 0x18, 110 .ucs_row_low_bit = 0x11, 111 .ucs_bank_bits = { 0xf, 0x10, 0xd, 112 0xe }, 113 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 114 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 115 }, { 116 .ucs_base = { 117 .udb_base = 0x800000000, 118 .udb_valid = B_TRUE 119 }, 120 .ucs_base_mask = 0x7ffffffff, 121 .ucs_nbanks = 0x4, 122 .ucs_ncol = 0xa, 123 .ucs_nrow_lo = 0x12, 124 .ucs_nbank_groups = 0x2, 125 .ucs_row_hi_bit = 0x18, 126 .ucs_row_low_bit = 0x11, 127 .ucs_bank_bits = { 0xf, 0x10, 0xd, 128 0xe }, 129 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 130 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 131 } } 132 }, { 133 .ud_flags = UMC_DIMM_F_VALID, 134 .ud_width = UMC_DIMM_W_X4, 135 .ud_type = UMC_DIMM_T_DDR4, 136 .ud_kind = UMC_DIMM_K_RDIMM, 137 .ud_dimmno = 1, 138 .ud_cs = { { 139 .ucs_base = { 140 .udb_base = 0x1000000000, 141 .udb_valid = B_TRUE 142 }, 143 .ucs_base_mask = 0x7ffffffff, 144 .ucs_nbanks = 0x4, 145 .ucs_ncol = 0xa, 146 .ucs_nrow_lo = 0x12, 147 .ucs_nbank_groups = 0x2, 148 .ucs_row_hi_bit = 0x18, 149 .ucs_row_low_bit = 0x11, 150 .ucs_bank_bits = { 0xf, 0x10, 0xd, 151 0xe }, 152 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 153 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 154 }, { 155 .ucs_base = { 156 .udb_base = 0x1800000000, 157 .udb_valid = B_TRUE 158 }, 159 .ucs_base_mask = 0x7ffffffff, 160 .ucs_nbanks = 0x4, 161 .ucs_ncol = 0xa, 162 .ucs_nrow_lo = 0x12, 163 .ucs_nbank_groups = 0x2, 164 .ucs_row_hi_bit = 0x18, 165 .ucs_row_low_bit = 0x11, 166 .ucs_bank_bits = { 0xf, 0x10, 0xd, 167 0xe }, 168 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 169 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 170 } } 171 } } 172 } } 173 } } 174 }; 175 176 /* 177 * This is a variant on the prior where we begin to interleave across all 4 178 * ranks in a channel, which AMD calls chip-select interleaving. This basically 179 * uses bits in the middle of the address to select the rank and therefore 180 * shifts all the other bits that get used for rank and bank selection. This 181 * works by shifting which address bits are used to actually determine the row 182 * up, allowing us to interleave in the middle of this. 183 */ 184 static const zen_umc_t zen_umc_chan_ilv = { 185 .umc_tom = 4ULL * 1024ULL * 1024ULL * 1024ULL, 186 .umc_tom2 = 128ULL * 1024ULL * 1024ULL * 1024ULL, 187 .umc_df_rev = DF_REV_3, 188 /* Per milan_decomp */ 189 .umc_decomp = { 190 .dfd_sock_mask = 0x01, 191 .dfd_die_mask = 0x00, 192 .dfd_node_mask = 0x20, 193 .dfd_comp_mask = 0x1f, 194 .dfd_sock_shift = 0, 195 .dfd_die_shift = 0, 196 .dfd_node_shift = 5, 197 .dfd_comp_shift = 0 198 }, 199 .umc_ndfs = 1, 200 .umc_dfs = { { 201 .zud_dfno = 0, 202 .zud_ccm_inst = 0, 203 .zud_dram_nrules = 1, 204 .zud_nchan = 1, 205 .zud_cs_nremap = 0, 206 .zud_hole_base = 0, 207 .zud_rules = { { 208 .ddr_flags = DF_DRAM_F_VALID, 209 .ddr_base = 0, 210 .ddr_limit = 128ULL * 1024ULL * 1024ULL * 1024ULL, 211 .ddr_dest_fabid = 1, 212 .ddr_sock_ileave_bits = 0, 213 .ddr_die_ileave_bits = 0, 214 .ddr_addr_start = 9, 215 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 216 } }, 217 .zud_chan = { { 218 .chan_flags = UMC_CHAN_F_ECC_EN, 219 .chan_fabid = 1, 220 .chan_instid = 1, 221 .chan_logid = 0, 222 .chan_nrules = 1, 223 .chan_rules = { { 224 .ddr_flags = DF_DRAM_F_VALID, 225 .ddr_base = 0, 226 .ddr_limit = 128ULL * 1024ULL * 1024ULL * 227 1024ULL, 228 .ddr_dest_fabid = 1, 229 .ddr_sock_ileave_bits = 0, 230 .ddr_die_ileave_bits = 0, 231 .ddr_addr_start = 9, 232 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 233 } }, 234 .chan_dimms = { { 235 .ud_flags = UMC_DIMM_F_VALID, 236 .ud_width = UMC_DIMM_W_X4, 237 .ud_type = UMC_DIMM_T_DDR4, 238 .ud_kind = UMC_DIMM_K_RDIMM, 239 .ud_dimmno = 0, 240 .ud_cs = { { 241 .ucs_base = { 242 .udb_base = 0, 243 .udb_valid = B_TRUE 244 }, 245 .ucs_base_mask = 0x1ffff9ffff, 246 .ucs_nbanks = 0x4, 247 .ucs_ncol = 0xa, 248 .ucs_nrow_lo = 0x12, 249 .ucs_nbank_groups = 0x2, 250 .ucs_row_hi_bit = 0x18, 251 .ucs_row_low_bit = 0x13, 252 .ucs_bank_bits = { 0xd, 0xe, 0xf, 253 0x10 }, 254 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 255 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 256 }, { 257 .ucs_base = { 258 .udb_base = 0x20000, 259 .udb_valid = B_TRUE 260 }, 261 .ucs_base_mask = 0x1ffff9ffff, 262 .ucs_nbanks = 0x4, 263 .ucs_ncol = 0xa, 264 .ucs_nrow_lo = 0x12, 265 .ucs_nbank_groups = 0x2, 266 .ucs_row_hi_bit = 0x18, 267 .ucs_row_low_bit = 0x13, 268 .ucs_bank_bits = { 0xd, 0xe, 0xf, 269 0x10 }, 270 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 271 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 272 } } 273 }, { 274 .ud_flags = UMC_DIMM_F_VALID, 275 .ud_width = UMC_DIMM_W_X4, 276 .ud_type = UMC_DIMM_T_DDR4, 277 .ud_kind = UMC_DIMM_K_RDIMM, 278 .ud_dimmno = 1, 279 .ud_cs = { { 280 .ucs_base = { 281 .udb_base = 0x40000, 282 .udb_valid = B_TRUE 283 }, 284 .ucs_base_mask = 0x1ffff9ffff, 285 .ucs_nbanks = 0x4, 286 .ucs_ncol = 0xa, 287 .ucs_nrow_lo = 0x12, 288 .ucs_nbank_groups = 0x2, 289 .ucs_row_hi_bit = 0x18, 290 .ucs_row_low_bit = 0x13, 291 .ucs_bank_bits = { 0xd, 0xe, 0xf, 292 0x10 }, 293 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 294 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 295 }, { 296 .ucs_base = { 297 .udb_base = 0x60000, 298 .udb_valid = B_TRUE 299 }, 300 .ucs_base_mask = 0x1ffff9ffff, 301 .ucs_nbanks = 0x4, 302 .ucs_ncol = 0xa, 303 .ucs_nrow_lo = 0x12, 304 .ucs_nbank_groups = 0x2, 305 .ucs_row_hi_bit = 0x18, 306 .ucs_row_low_bit = 0x13, 307 .ucs_bank_bits = { 0xd, 0xe, 0xf, 308 0x10 }, 309 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 310 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 311 } } 312 } } 313 } } 314 } } 315 }; 316 317 /* 318 * This sets up a CS hash across all 4 ranks. The actual values here are 319 * representative of a set up we've seen on the CPU. 320 */ 321 static const zen_umc_t zen_umc_chan_ilv_cs_hash = { 322 .umc_tom = 4ULL * 1024ULL * 1024ULL * 1024ULL, 323 .umc_tom2 = 128ULL * 1024ULL * 1024ULL * 1024ULL, 324 .umc_df_rev = DF_REV_3, 325 /* Per milan_decomp */ 326 .umc_decomp = { 327 .dfd_sock_mask = 0x01, 328 .dfd_die_mask = 0x00, 329 .dfd_node_mask = 0x20, 330 .dfd_comp_mask = 0x1f, 331 .dfd_sock_shift = 0, 332 .dfd_die_shift = 0, 333 .dfd_node_shift = 5, 334 .dfd_comp_shift = 0 335 }, 336 .umc_ndfs = 1, 337 .umc_dfs = { { 338 .zud_dfno = 0, 339 .zud_ccm_inst = 0, 340 .zud_dram_nrules = 1, 341 .zud_nchan = 1, 342 .zud_cs_nremap = 0, 343 .zud_hole_base = 0, 344 .zud_rules = { { 345 .ddr_flags = DF_DRAM_F_VALID, 346 .ddr_base = 0, 347 .ddr_limit = 128ULL * 1024ULL * 1024ULL * 1024ULL, 348 .ddr_dest_fabid = 1, 349 .ddr_sock_ileave_bits = 0, 350 .ddr_die_ileave_bits = 0, 351 .ddr_addr_start = 9, 352 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 353 } }, 354 .zud_chan = { { 355 .chan_flags = UMC_CHAN_F_ECC_EN, 356 .chan_fabid = 1, 357 .chan_instid = 1, 358 .chan_logid = 0, 359 .chan_nrules = 1, 360 .chan_rules = { { 361 .ddr_flags = DF_DRAM_F_VALID, 362 .ddr_base = 0, 363 .ddr_limit = 128ULL * 1024ULL * 1024ULL * 364 1024ULL, 365 .ddr_dest_fabid = 1, 366 .ddr_sock_ileave_bits = 0, 367 .ddr_die_ileave_bits = 0, 368 .ddr_addr_start = 9, 369 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 370 } }, 371 .chan_dimms = { { 372 .ud_flags = UMC_DIMM_F_VALID, 373 .ud_width = UMC_DIMM_W_X4, 374 .ud_type = UMC_DIMM_T_DDR4, 375 .ud_kind = UMC_DIMM_K_RDIMM, 376 .ud_dimmno = 0, 377 .ud_cs = { { 378 .ucs_base = { 379 .udb_base = 0, 380 .udb_valid = B_TRUE 381 }, 382 .ucs_base_mask = 0x1ffff9ffff, 383 .ucs_nbanks = 0x4, 384 .ucs_ncol = 0xa, 385 .ucs_nrow_lo = 0x12, 386 .ucs_nbank_groups = 0x2, 387 .ucs_row_hi_bit = 0x18, 388 .ucs_row_low_bit = 0x13, 389 .ucs_bank_bits = { 0xd, 0xe, 0xf, 390 0x10 }, 391 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 392 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 393 }, { 394 .ucs_base = { 395 .udb_base = 0x20000, 396 .udb_valid = B_TRUE 397 }, 398 .ucs_base_mask = 0x1ffff9ffff, 399 .ucs_nbanks = 0x4, 400 .ucs_ncol = 0xa, 401 .ucs_nrow_lo = 0x12, 402 .ucs_nbank_groups = 0x2, 403 .ucs_row_hi_bit = 0x18, 404 .ucs_row_low_bit = 0x13, 405 .ucs_bank_bits = { 0xd, 0xe, 0xf, 406 0x10 }, 407 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 408 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 409 } } 410 }, { 411 .ud_flags = UMC_DIMM_F_VALID, 412 .ud_width = UMC_DIMM_W_X4, 413 .ud_type = UMC_DIMM_T_DDR4, 414 .ud_kind = UMC_DIMM_K_RDIMM, 415 .ud_dimmno = 1, 416 .ud_cs = { { 417 .ucs_base = { 418 .udb_base = 0x40000, 419 .udb_valid = B_TRUE 420 }, 421 .ucs_base_mask = 0x1ffff9ffff, 422 .ucs_nbanks = 0x4, 423 .ucs_ncol = 0xa, 424 .ucs_nrow_lo = 0x12, 425 .ucs_nbank_groups = 0x2, 426 .ucs_row_hi_bit = 0x18, 427 .ucs_row_low_bit = 0x13, 428 .ucs_bank_bits = { 0xd, 0xe, 0xf, 429 0x10 }, 430 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 431 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 432 }, { 433 .ucs_base = { 434 .udb_base = 0x60000, 435 .udb_valid = B_TRUE 436 }, 437 .ucs_base_mask = 0x1ffff9ffff, 438 .ucs_nbanks = 0x4, 439 .ucs_ncol = 0xa, 440 .ucs_nrow_lo = 0x12, 441 .ucs_nbank_groups = 0x2, 442 .ucs_row_hi_bit = 0x18, 443 .ucs_row_low_bit = 0x13, 444 .ucs_bank_bits = { 0xd, 0xe, 0xf, 445 0x10 }, 446 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 447 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 448 } } 449 } }, 450 .chan_hash = { 451 .uch_flags = UMC_CHAN_HASH_F_CS, 452 .uch_cs_hashes = { { 453 .uah_addr_xor = 0xaaaa80000, 454 .uah_en = B_TRUE 455 }, { 456 .uah_addr_xor = 0x1555500000, 457 .uah_en = B_TRUE 458 } } 459 } 460 } } 461 } } 462 }; 463 464 /* 465 * This enables bank hashing across both of the DIMMs in this configuration. The 466 * use of the row and not the column to select the bank is based on a CPU config 467 * seen in the wild. 468 */ 469 static const zen_umc_t zen_umc_chan_ilv_bank_hash = { 470 .umc_tom = 4ULL * 1024ULL * 1024ULL * 1024ULL, 471 .umc_tom2 = 128ULL * 1024ULL * 1024ULL * 1024ULL, 472 .umc_df_rev = DF_REV_3, 473 /* Per milan_decomp */ 474 .umc_decomp = { 475 .dfd_sock_mask = 0x01, 476 .dfd_die_mask = 0x00, 477 .dfd_node_mask = 0x20, 478 .dfd_comp_mask = 0x1f, 479 .dfd_sock_shift = 0, 480 .dfd_die_shift = 0, 481 .dfd_node_shift = 5, 482 .dfd_comp_shift = 0 483 }, 484 .umc_ndfs = 1, 485 .umc_dfs = { { 486 .zud_dfno = 0, 487 .zud_ccm_inst = 0, 488 .zud_dram_nrules = 1, 489 .zud_nchan = 1, 490 .zud_cs_nremap = 0, 491 .zud_hole_base = 0, 492 .zud_rules = { { 493 .ddr_flags = DF_DRAM_F_VALID, 494 .ddr_base = 0, 495 .ddr_limit = 128ULL * 1024ULL * 1024ULL * 1024ULL, 496 .ddr_dest_fabid = 1, 497 .ddr_sock_ileave_bits = 0, 498 .ddr_die_ileave_bits = 0, 499 .ddr_addr_start = 9, 500 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 501 } }, 502 .zud_chan = { { 503 .chan_flags = UMC_CHAN_F_ECC_EN, 504 .chan_fabid = 1, 505 .chan_instid = 1, 506 .chan_logid = 0, 507 .chan_nrules = 1, 508 .chan_rules = { { 509 .ddr_flags = DF_DRAM_F_VALID, 510 .ddr_base = 0, 511 .ddr_limit = 128ULL * 1024ULL * 1024ULL * 512 1024ULL, 513 .ddr_dest_fabid = 1, 514 .ddr_sock_ileave_bits = 0, 515 .ddr_die_ileave_bits = 0, 516 .ddr_addr_start = 9, 517 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 518 } }, 519 .chan_dimms = { { 520 .ud_flags = UMC_DIMM_F_VALID, 521 .ud_width = UMC_DIMM_W_X4, 522 .ud_type = UMC_DIMM_T_DDR4, 523 .ud_kind = UMC_DIMM_K_RDIMM, 524 .ud_dimmno = 0, 525 .ud_cs = { { 526 .ucs_base = { 527 .udb_base = 0, 528 .udb_valid = B_TRUE 529 }, 530 .ucs_base_mask = 0x1ffff9ffff, 531 .ucs_nbanks = 0x4, 532 .ucs_ncol = 0xa, 533 .ucs_nrow_lo = 0x12, 534 .ucs_nbank_groups = 0x2, 535 .ucs_row_hi_bit = 0x18, 536 .ucs_row_low_bit = 0x13, 537 .ucs_bank_bits = { 0xd, 0xe, 0xf, 538 0x10 }, 539 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 540 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 541 }, { 542 .ucs_base = { 543 .udb_base = 0x20000, 544 .udb_valid = B_TRUE 545 }, 546 .ucs_base_mask = 0x1ffff9ffff, 547 .ucs_nbanks = 0x4, 548 .ucs_ncol = 0xa, 549 .ucs_nrow_lo = 0x12, 550 .ucs_nbank_groups = 0x2, 551 .ucs_row_hi_bit = 0x18, 552 .ucs_row_low_bit = 0x13, 553 .ucs_bank_bits = { 0xd, 0xe, 0xf, 554 0x10 }, 555 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 556 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 557 } } 558 }, { 559 .ud_flags = UMC_DIMM_F_VALID, 560 .ud_width = UMC_DIMM_W_X4, 561 .ud_type = UMC_DIMM_T_DDR4, 562 .ud_kind = UMC_DIMM_K_RDIMM, 563 .ud_dimmno = 1, 564 .ud_cs = { { 565 .ucs_base = { 566 .udb_base = 0x40000, 567 .udb_valid = B_TRUE 568 }, 569 .ucs_base_mask = 0x1ffff9ffff, 570 .ucs_nbanks = 0x4, 571 .ucs_ncol = 0xa, 572 .ucs_nrow_lo = 0x12, 573 .ucs_nbank_groups = 0x2, 574 .ucs_row_hi_bit = 0x18, 575 .ucs_row_low_bit = 0x13, 576 .ucs_bank_bits = { 0xd, 0xe, 0xf, 577 0x10 }, 578 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 579 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 580 }, { 581 .ucs_base = { 582 .udb_base = 0x60000, 583 .udb_valid = B_TRUE 584 }, 585 .ucs_base_mask = 0x1ffff9ffff, 586 .ucs_nbanks = 0x4, 587 .ucs_ncol = 0xa, 588 .ucs_nrow_lo = 0x12, 589 .ucs_nbank_groups = 0x2, 590 .ucs_row_hi_bit = 0x18, 591 .ucs_row_low_bit = 0x13, 592 .ucs_bank_bits = { 0xd, 0xe, 0xf, 593 0x10 }, 594 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 595 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 596 } } 597 } }, 598 .chan_hash = { 599 .uch_flags = UMC_CHAN_HASH_F_BANK, 600 .uch_bank_hashes = { { 601 .ubh_row_xor = 0x11111, 602 .ubh_col_xor = 0, 603 .ubh_en = B_TRUE 604 }, { 605 .ubh_row_xor = 0x22222, 606 .ubh_col_xor = 0, 607 .ubh_en = B_TRUE 608 }, { 609 .ubh_row_xor = 0x4444, 610 .ubh_col_xor = 0, 611 .ubh_en = B_TRUE 612 }, { 613 .ubh_row_xor = 0x8888, 614 .ubh_col_xor = 0, 615 .ubh_en = B_TRUE 616 } } 617 } 618 } } 619 } } 620 }; 621 622 /* 623 * Some configurations allow optional bank swaps where by the bits we use for 624 * the column and the bank are swapped around. Do one of these just to make sure 625 * we haven't built in any surprise dependencies. 626 */ 627 static const zen_umc_t zen_umc_chan_ilv_bank_swap = { 628 .umc_tom = 4ULL * 1024ULL * 1024ULL * 1024ULL, 629 .umc_tom2 = 128ULL * 1024ULL * 1024ULL * 1024ULL, 630 .umc_df_rev = DF_REV_3, 631 .umc_decomp = { 632 .dfd_sock_mask = 0x01, 633 .dfd_die_mask = 0x00, 634 .dfd_node_mask = 0x20, 635 .dfd_comp_mask = 0x1f, 636 .dfd_sock_shift = 0, 637 .dfd_die_shift = 0, 638 .dfd_node_shift = 5, 639 .dfd_comp_shift = 0 640 }, 641 .umc_ndfs = 1, 642 .umc_dfs = { { 643 .zud_dfno = 0, 644 .zud_ccm_inst = 0, 645 .zud_dram_nrules = 1, 646 .zud_nchan = 1, 647 .zud_cs_nremap = 0, 648 .zud_hole_base = 0, 649 .zud_rules = { { 650 .ddr_flags = DF_DRAM_F_VALID, 651 .ddr_base = 0, 652 .ddr_limit = 128ULL * 1024ULL * 1024ULL * 1024ULL, 653 .ddr_dest_fabid = 1, 654 .ddr_sock_ileave_bits = 0, 655 .ddr_die_ileave_bits = 0, 656 .ddr_addr_start = 9, 657 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 658 } }, 659 .zud_chan = { { 660 .chan_flags = UMC_CHAN_F_ECC_EN, 661 .chan_fabid = 1, 662 .chan_instid = 1, 663 .chan_logid = 0, 664 .chan_nrules = 1, 665 .chan_rules = { { 666 .ddr_flags = DF_DRAM_F_VALID, 667 .ddr_base = 0, 668 .ddr_limit = 128ULL * 1024ULL * 1024ULL * 669 1024ULL, 670 .ddr_dest_fabid = 1, 671 .ddr_sock_ileave_bits = 0, 672 .ddr_die_ileave_bits = 0, 673 .ddr_addr_start = 9, 674 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 675 } }, 676 .chan_dimms = { { 677 .ud_flags = UMC_DIMM_F_VALID, 678 .ud_width = UMC_DIMM_W_X4, 679 .ud_type = UMC_DIMM_T_DDR4, 680 .ud_kind = UMC_DIMM_K_RDIMM, 681 .ud_dimmno = 0, 682 .ud_cs = { { 683 .ucs_base = { 684 .udb_base = 0, 685 .udb_valid = B_TRUE 686 }, 687 .ucs_base_mask = 0x1ffff9ffff, 688 .ucs_nbanks = 0x4, 689 .ucs_ncol = 0xa, 690 .ucs_nrow_lo = 0x12, 691 .ucs_nbank_groups = 0x2, 692 .ucs_row_hi_bit = 0x18, 693 .ucs_row_low_bit = 0x13, 694 .ucs_bank_bits = { 0x9, 0xa, 0x6, 695 0xb }, 696 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x7, 697 0x8, 0xc, 0xd, 0xe, 0xf, 0x10 } 698 }, { 699 .ucs_base = { 700 .udb_base = 0x20000, 701 .udb_valid = B_TRUE 702 }, 703 .ucs_base_mask = 0x1ffff9ffff, 704 .ucs_nbanks = 0x4, 705 .ucs_ncol = 0xa, 706 .ucs_nrow_lo = 0x12, 707 .ucs_nbank_groups = 0x2, 708 .ucs_row_hi_bit = 0x18, 709 .ucs_row_low_bit = 0x13, 710 .ucs_bank_bits = { 0x9, 0xa, 0x6, 711 0xb }, 712 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x7, 713 0x8, 0xc, 0xd, 0xe, 0xf, 0x10 } 714 } } 715 }, { 716 .ud_flags = UMC_DIMM_F_VALID, 717 .ud_width = UMC_DIMM_W_X4, 718 .ud_type = UMC_DIMM_T_DDR4, 719 .ud_kind = UMC_DIMM_K_RDIMM, 720 .ud_dimmno = 1, 721 .ud_cs = { { 722 .ucs_base = { 723 .udb_base = 0x40000, 724 .udb_valid = B_TRUE 725 }, 726 .ucs_base_mask = 0x1ffff9ffff, 727 .ucs_nbanks = 0x4, 728 .ucs_ncol = 0xa, 729 .ucs_nrow_lo = 0x12, 730 .ucs_nbank_groups = 0x2, 731 .ucs_row_hi_bit = 0x18, 732 .ucs_row_low_bit = 0x13, 733 .ucs_bank_bits = { 0x9, 0xa, 0x6, 734 0xb }, 735 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x7, 736 0x8, 0xc, 0xd, 0xe, 0xf, 0x10 } 737 }, { 738 .ucs_base = { 739 .udb_base = 0x60000, 740 .udb_valid = B_TRUE 741 }, 742 .ucs_base_mask = 0x1ffff9ffff, 743 .ucs_nbanks = 0x4, 744 .ucs_ncol = 0xa, 745 .ucs_nrow_lo = 0x12, 746 .ucs_nbank_groups = 0x2, 747 .ucs_row_hi_bit = 0x18, 748 .ucs_row_low_bit = 0x13, 749 .ucs_bank_bits = { 0x9, 0xa, 0x6, 750 0xb }, 751 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x7, 752 0x8, 0xc, 0xd, 0xe, 0xf, 0x10 } 753 } } 754 } } 755 } } 756 } } 757 }; 758 759 /* 760 * This is a basic DDR5 channel. We only use a single DIMM and set up a 761 * sub-channel on it. 762 */ 763 static const zen_umc_t zen_umc_chan_subchan_no_hash = { 764 .umc_tom = 4ULL * 1024ULL * 1024ULL * 1024ULL, 765 .umc_tom2 = 16ULL * 1024ULL * 1024ULL * 1024ULL, 766 .umc_df_rev = DF_REV_3, 767 .umc_decomp = { 768 .dfd_sock_mask = 0x01, 769 .dfd_die_mask = 0x00, 770 .dfd_node_mask = 0x20, 771 .dfd_comp_mask = 0x1f, 772 .dfd_sock_shift = 0, 773 .dfd_die_shift = 0, 774 .dfd_node_shift = 5, 775 .dfd_comp_shift = 0 776 }, 777 .umc_ndfs = 1, 778 .umc_dfs = { { 779 .zud_dfno = 0, 780 .zud_ccm_inst = 0, 781 .zud_dram_nrules = 1, 782 .zud_nchan = 1, 783 .zud_cs_nremap = 0, 784 .zud_hole_base = 0, 785 .zud_rules = { { 786 .ddr_flags = DF_DRAM_F_VALID, 787 .ddr_base = 0, 788 .ddr_limit = 16ULL * 1024ULL * 1024ULL * 1024ULL, 789 .ddr_dest_fabid = 1, 790 .ddr_sock_ileave_bits = 0, 791 .ddr_die_ileave_bits = 0, 792 .ddr_addr_start = 9, 793 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 794 } }, 795 .zud_chan = { { 796 .chan_flags = UMC_CHAN_F_ECC_EN, 797 .chan_fabid = 1, 798 .chan_instid = 1, 799 .chan_logid = 0, 800 .chan_nrules = 1, 801 .chan_rules = { { 802 .ddr_flags = DF_DRAM_F_VALID, 803 .ddr_base = 0, 804 .ddr_limit = 16ULL * 1024ULL * 1024ULL * 805 1024ULL, 806 .ddr_dest_fabid = 1, 807 .ddr_sock_ileave_bits = 0, 808 .ddr_die_ileave_bits = 0, 809 .ddr_addr_start = 9, 810 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 811 } }, 812 .chan_dimms = { { 813 .ud_flags = UMC_DIMM_F_VALID, 814 .ud_width = UMC_DIMM_W_X4, 815 .ud_type = UMC_DIMM_T_DDR5, 816 .ud_kind = UMC_DIMM_K_RDIMM, 817 .ud_dimmno = 0, 818 .ud_cs = { { 819 .ucs_base = { 820 .udb_base = 0, 821 .udb_valid = B_TRUE 822 }, 823 .ucs_base_mask = 0x3ffffffff, 824 .ucs_nbanks = 0x5, 825 .ucs_ncol = 0xa, 826 .ucs_nrow_lo = 0x10, 827 .ucs_nbank_groups = 0x3, 828 .ucs_row_low_bit = 0x12, 829 .ucs_bank_bits = { 0xf, 0x10, 0x11, 830 0xd, 0xe }, 831 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 832 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 833 .ucs_subchan = 0x6 834 } } 835 } } 836 } } 837 } } 838 }; 839 840 const umc_decode_test_t zen_umc_test_chans[] = { { 841 .udt_desc = "2 DPC 2R no ilv/hash (0)", 842 .udt_umc = &zen_umc_chan_no_hash, 843 .udt_pa = 0x0, 844 .udt_pass = B_TRUE, 845 .udt_norm_addr = 0x0, 846 .udt_sock = 0, 847 .udt_die = 0, 848 .udt_comp = 1, 849 .udt_dimm_no = 0, 850 .udt_dimm_col = 0, 851 .udt_dimm_row = 0, 852 .udt_dimm_bank = 0, 853 .udt_dimm_bank_group = 0, 854 .udt_dimm_subchan = UINT8_MAX, 855 .udt_dimm_rm = 0, 856 .udt_dimm_cs = 0 857 }, { 858 .udt_desc = "2 DPC 2R no ilv/hash (1)", 859 .udt_umc = &zen_umc_chan_no_hash, 860 .udt_pa = 0x800000000, 861 .udt_pass = B_TRUE, 862 .udt_norm_addr = 0x800000000, 863 .udt_sock = 0, 864 .udt_die = 0, 865 .udt_comp = 1, 866 .udt_dimm_no = 0, 867 .udt_dimm_col = 0, 868 .udt_dimm_row = 0, 869 .udt_dimm_bank = 0, 870 .udt_dimm_bank_group = 0, 871 .udt_dimm_subchan = UINT8_MAX, 872 .udt_dimm_rm = 0, 873 .udt_dimm_cs = 1 874 }, { 875 .udt_desc = "2 DPC 2R no ilv/hash (2)", 876 .udt_umc = &zen_umc_chan_no_hash, 877 .udt_pa = 0x1000000000, 878 .udt_pass = B_TRUE, 879 .udt_norm_addr = 0x1000000000, 880 .udt_sock = 0, 881 .udt_die = 0, 882 .udt_comp = 1, 883 .udt_dimm_no = 1, 884 .udt_dimm_col = 0, 885 .udt_dimm_row = 0, 886 .udt_dimm_bank = 0, 887 .udt_dimm_bank_group = 0, 888 .udt_dimm_subchan = UINT8_MAX, 889 .udt_dimm_rm = 0, 890 .udt_dimm_cs = 0 891 }, { 892 .udt_desc = "2 DPC 2R no ilv/hash (3)", 893 .udt_umc = &zen_umc_chan_no_hash, 894 .udt_pa = 0x1800000000, 895 .udt_pass = B_TRUE, 896 .udt_norm_addr = 0x1800000000, 897 .udt_sock = 0, 898 .udt_die = 0, 899 .udt_comp = 1, 900 .udt_dimm_no = 1, 901 .udt_dimm_col = 0, 902 .udt_dimm_row = 0, 903 .udt_dimm_bank = 0, 904 .udt_dimm_bank_group = 0, 905 .udt_dimm_subchan = UINT8_MAX, 906 .udt_dimm_rm = 0, 907 .udt_dimm_cs = 1 908 }, { 909 .udt_desc = "2 DPC 2R no ilv/hash (4)", 910 .udt_umc = &zen_umc_chan_no_hash, 911 .udt_pa = 0x0ff1ff120, 912 .udt_pass = B_TRUE, 913 .udt_norm_addr = 0x0ff1ff120, 914 .udt_sock = 0, 915 .udt_die = 0, 916 .udt_comp = 1, 917 .udt_dimm_no = 0, 918 .udt_dimm_col = 0x224, 919 .udt_dimm_row = 0x7f8f, 920 .udt_dimm_bank = 3, 921 .udt_dimm_bank_group = 3, 922 .udt_dimm_subchan = UINT8_MAX, 923 .udt_dimm_rm = 0, 924 .udt_dimm_cs = 0 925 }, { 926 .udt_desc = "2 DPC 2R no ilv/hash (5)", 927 .udt_umc = &zen_umc_chan_no_hash, 928 .udt_pa = 0x8ff4ff500, 929 .udt_pass = B_TRUE, 930 .udt_norm_addr = 0x8ff4ff500, 931 .udt_sock = 0, 932 .udt_die = 0, 933 .udt_comp = 1, 934 .udt_dimm_no = 0, 935 .udt_dimm_col = 0x2a0, 936 .udt_dimm_row = 0x7fa7, 937 .udt_dimm_bank = 3, 938 .udt_dimm_bank_group = 3, 939 .udt_dimm_subchan = UINT8_MAX, 940 .udt_dimm_rm = 0, 941 .udt_dimm_cs = 1 942 }, { 943 .udt_desc = "2 DPC 2R no ilv/hash (6)", 944 .udt_umc = &zen_umc_chan_no_hash, 945 .udt_pa = 0x10ff6ff700, 946 .udt_pass = B_TRUE, 947 .udt_norm_addr = 0x10ff6ff700, 948 .udt_sock = 0, 949 .udt_die = 0, 950 .udt_comp = 1, 951 .udt_dimm_no = 1, 952 .udt_dimm_col = 0x2e0, 953 .udt_dimm_row = 0x7fb7, 954 .udt_dimm_bank = 3, 955 .udt_dimm_bank_group = 3, 956 .udt_dimm_subchan = UINT8_MAX, 957 .udt_dimm_rm = 0, 958 .udt_dimm_cs = 0 959 }, { 960 .udt_desc = "2 DPC 2R no ilv/hash (7)", 961 .udt_umc = &zen_umc_chan_no_hash, 962 .udt_pa = 0x18ff8ff102, 963 .udt_pass = B_TRUE, 964 .udt_norm_addr = 0x18ff8ff102, 965 .udt_sock = 0, 966 .udt_die = 0, 967 .udt_comp = 1, 968 .udt_dimm_no = 1, 969 .udt_dimm_col = 0x220, 970 .udt_dimm_row = 0x7fc7, 971 .udt_dimm_bank = 3, 972 .udt_dimm_bank_group = 3, 973 .udt_dimm_subchan = UINT8_MAX, 974 .udt_dimm_rm = 0, 975 .udt_dimm_cs = 1 976 }, { 977 .udt_desc = "2 DPC 2R no hash, rank ilv (0)", 978 .udt_umc = &zen_umc_chan_ilv, 979 .udt_pa = 0x0, 980 .udt_pass = B_TRUE, 981 .udt_norm_addr = 0x0, 982 .udt_sock = 0, 983 .udt_die = 0, 984 .udt_comp = 1, 985 .udt_dimm_no = 0, 986 .udt_dimm_col = 0, 987 .udt_dimm_row = 0, 988 .udt_dimm_bank = 0, 989 .udt_dimm_bank_group = 0, 990 .udt_dimm_subchan = UINT8_MAX, 991 .udt_dimm_rm = 0, 992 .udt_dimm_cs = 0 993 }, { 994 .udt_desc = "2 DPC 2R no hash, rank ilv (1)", 995 .udt_umc = &zen_umc_chan_ilv, 996 .udt_pa = 0x20000, 997 .udt_pass = B_TRUE, 998 .udt_norm_addr = 0x20000, 999 .udt_sock = 0, 1000 .udt_die = 0, 1001 .udt_comp = 1, 1002 .udt_dimm_no = 0, 1003 .udt_dimm_col = 0, 1004 .udt_dimm_row = 0, 1005 .udt_dimm_bank = 0, 1006 .udt_dimm_bank_group = 0, 1007 .udt_dimm_subchan = UINT8_MAX, 1008 .udt_dimm_rm = 0, 1009 .udt_dimm_cs = 1 1010 }, { 1011 .udt_desc = "2 DPC 2R no hash, rank ilv (2)", 1012 .udt_umc = &zen_umc_chan_ilv, 1013 .udt_pa = 0x40000, 1014 .udt_pass = B_TRUE, 1015 .udt_norm_addr = 0x40000, 1016 .udt_sock = 0, 1017 .udt_die = 0, 1018 .udt_comp = 1, 1019 .udt_dimm_no = 1, 1020 .udt_dimm_col = 0, 1021 .udt_dimm_row = 0, 1022 .udt_dimm_bank = 0, 1023 .udt_dimm_bank_group = 0, 1024 .udt_dimm_subchan = UINT8_MAX, 1025 .udt_dimm_rm = 0, 1026 .udt_dimm_cs = 0 1027 }, { 1028 .udt_desc = "2 DPC 2R no hash, rank ilv (3)", 1029 .udt_umc = &zen_umc_chan_ilv, 1030 .udt_pa = 0x60000, 1031 .udt_pass = B_TRUE, 1032 .udt_norm_addr = 0x60000, 1033 .udt_sock = 0, 1034 .udt_die = 0, 1035 .udt_comp = 1, 1036 .udt_dimm_no = 1, 1037 .udt_dimm_col = 0, 1038 .udt_dimm_row = 0, 1039 .udt_dimm_bank = 0, 1040 .udt_dimm_bank_group = 0, 1041 .udt_dimm_subchan = UINT8_MAX, 1042 .udt_dimm_rm = 0, 1043 .udt_dimm_cs = 1 1044 }, { 1045 .udt_desc = "2 DPC 2R no hash, rank ilv (4)", 1046 .udt_umc = &zen_umc_chan_ilv, 1047 .udt_pa = 0xe1be12e00, 1048 .udt_pass = B_TRUE, 1049 .udt_norm_addr = 0xe1be12e00, 1050 .udt_sock = 0, 1051 .udt_die = 0, 1052 .udt_comp = 1, 1053 .udt_dimm_no = 0, 1054 .udt_dimm_col = 0x1c0, 1055 .udt_dimm_row = 0x1c37c, 1056 .udt_dimm_bank = 2, 1057 .udt_dimm_bank_group = 1, 1058 .udt_dimm_subchan = UINT8_MAX, 1059 .udt_dimm_rm = 0, 1060 .udt_dimm_cs = 0 1061 }, { 1062 .udt_desc = "2 DPC 2R no hash, rank ilv (5)", 1063 .udt_umc = &zen_umc_chan_ilv, 1064 .udt_pa = 0x1fffffffff, 1065 .udt_pass = B_TRUE, 1066 .udt_norm_addr = 0x1fffffffff, 1067 .udt_sock = 0, 1068 .udt_die = 0, 1069 .udt_comp = 1, 1070 .udt_dimm_no = 1, 1071 .udt_dimm_col = 0x3ff, 1072 .udt_dimm_row = 0x3ffff, 1073 .udt_dimm_bank = 3, 1074 .udt_dimm_bank_group = 3, 1075 .udt_dimm_subchan = UINT8_MAX, 1076 .udt_dimm_rm = 0, 1077 .udt_dimm_cs = 1 1078 }, 1079 /* 1080 * Test the CS hashing by first going back and using bits that aren't part of 1081 * the CS hash modification, e.g. the same 4 interleaving case that we hit 1082 * earlier. Next, we go through and tweak things that would normally go to a 1083 * given CS originally by tweaking the bits that would be used in a hash and 1084 * prove that they go elsewhere. 1085 */ 1086 { 1087 .udt_desc = "2 DPC 2R cs hash, rank ilv (0)", 1088 .udt_umc = &zen_umc_chan_ilv_cs_hash, 1089 .udt_pa = 0x0, 1090 .udt_pass = B_TRUE, 1091 .udt_norm_addr = 0x0, 1092 .udt_sock = 0, 1093 .udt_die = 0, 1094 .udt_comp = 1, 1095 .udt_dimm_no = 0, 1096 .udt_dimm_col = 0, 1097 .udt_dimm_row = 0, 1098 .udt_dimm_bank = 0, 1099 .udt_dimm_bank_group = 0, 1100 .udt_dimm_subchan = UINT8_MAX, 1101 .udt_dimm_rm = 0, 1102 .udt_dimm_cs = 0 1103 }, { 1104 .udt_desc = "2 DPC 2R cs hash, rank ilv (1)", 1105 .udt_umc = &zen_umc_chan_ilv_cs_hash, 1106 .udt_pa = 0x20000, 1107 .udt_pass = B_TRUE, 1108 .udt_norm_addr = 0x20000, 1109 .udt_sock = 0, 1110 .udt_die = 0, 1111 .udt_comp = 1, 1112 .udt_dimm_no = 0, 1113 .udt_dimm_col = 0, 1114 .udt_dimm_row = 0, 1115 .udt_dimm_bank = 0, 1116 .udt_dimm_bank_group = 0, 1117 .udt_dimm_subchan = UINT8_MAX, 1118 .udt_dimm_rm = 0, 1119 .udt_dimm_cs = 1 1120 }, { 1121 .udt_desc = "2 DPC 2R cs hash, rank ilv (2)", 1122 .udt_umc = &zen_umc_chan_ilv_cs_hash, 1123 .udt_pa = 0x40000, 1124 .udt_pass = B_TRUE, 1125 .udt_norm_addr = 0x40000, 1126 .udt_sock = 0, 1127 .udt_die = 0, 1128 .udt_comp = 1, 1129 .udt_dimm_no = 1, 1130 .udt_dimm_col = 0, 1131 .udt_dimm_row = 0, 1132 .udt_dimm_bank = 0, 1133 .udt_dimm_bank_group = 0, 1134 .udt_dimm_subchan = UINT8_MAX, 1135 .udt_dimm_rm = 0, 1136 .udt_dimm_cs = 0 1137 }, { 1138 .udt_desc = "2 DPC 2R cs hash, rank ilv (3)", 1139 .udt_umc = &zen_umc_chan_ilv_cs_hash, 1140 .udt_pa = 0x60000, 1141 .udt_pass = B_TRUE, 1142 .udt_norm_addr = 0x60000, 1143 .udt_sock = 0, 1144 .udt_die = 0, 1145 .udt_comp = 1, 1146 .udt_dimm_no = 1, 1147 .udt_dimm_col = 0, 1148 .udt_dimm_row = 0, 1149 .udt_dimm_bank = 0, 1150 .udt_dimm_bank_group = 0, 1151 .udt_dimm_subchan = UINT8_MAX, 1152 .udt_dimm_rm = 0, 1153 .udt_dimm_cs = 1 1154 }, { 1155 .udt_desc = "2 DPC 2R cs hash, rank ilv (4)", 1156 .udt_umc = &zen_umc_chan_ilv_cs_hash, 1157 .udt_pa = 0x80000, 1158 .udt_pass = B_TRUE, 1159 .udt_norm_addr = 0x80000, 1160 .udt_sock = 0, 1161 .udt_die = 0, 1162 .udt_comp = 1, 1163 .udt_dimm_no = 0, 1164 .udt_dimm_col = 0, 1165 .udt_dimm_row = 1, 1166 .udt_dimm_bank = 0, 1167 .udt_dimm_bank_group = 0, 1168 .udt_dimm_subchan = UINT8_MAX, 1169 .udt_dimm_rm = 0, 1170 .udt_dimm_cs = 1 1171 }, { 1172 .udt_desc = "2 DPC 2R cs hash, rank ilv (5)", 1173 .udt_umc = &zen_umc_chan_ilv_cs_hash, 1174 .udt_pa = 0x180000, 1175 .udt_pass = B_TRUE, 1176 .udt_norm_addr = 0x180000, 1177 .udt_sock = 0, 1178 .udt_die = 0, 1179 .udt_comp = 1, 1180 .udt_dimm_no = 1, 1181 .udt_dimm_col = 0, 1182 .udt_dimm_row = 3, 1183 .udt_dimm_bank = 0, 1184 .udt_dimm_bank_group = 0, 1185 .udt_dimm_subchan = UINT8_MAX, 1186 .udt_dimm_rm = 0, 1187 .udt_dimm_cs = 1 1188 }, { 1189 .udt_desc = "2 DPC 2R cs hash, rank ilv (6)", 1190 .udt_umc = &zen_umc_chan_ilv_cs_hash, 1191 .udt_pa = 0x100000, 1192 .udt_pass = B_TRUE, 1193 .udt_norm_addr = 0x100000, 1194 .udt_sock = 0, 1195 .udt_die = 0, 1196 .udt_comp = 1, 1197 .udt_dimm_no = 1, 1198 .udt_dimm_col = 0, 1199 .udt_dimm_row = 2, 1200 .udt_dimm_bank = 0, 1201 .udt_dimm_bank_group = 0, 1202 .udt_dimm_subchan = UINT8_MAX, 1203 .udt_dimm_rm = 0, 1204 .udt_dimm_cs = 0 1205 }, { 1206 .udt_desc = "2 DPC 2R cs hash, rank ilv (7)", 1207 .udt_umc = &zen_umc_chan_ilv_cs_hash, 1208 .udt_pa = 0x18180000, 1209 .udt_pass = B_TRUE, 1210 .udt_norm_addr = 0x18180000, 1211 .udt_sock = 0, 1212 .udt_die = 0, 1213 .udt_comp = 1, 1214 .udt_dimm_no = 0, 1215 .udt_dimm_col = 0, 1216 .udt_dimm_row = 0x303, 1217 .udt_dimm_bank = 0, 1218 .udt_dimm_bank_group = 0, 1219 .udt_dimm_subchan = UINT8_MAX, 1220 .udt_dimm_rm = 0, 1221 .udt_dimm_cs = 0 1222 }, { 1223 .udt_desc = "2 DPC 2R cs hash, rank ilv (8)", 1224 .udt_umc = &zen_umc_chan_ilv_cs_hash, 1225 .udt_pa = 0x181a0000, 1226 .udt_pass = B_TRUE, 1227 .udt_norm_addr = 0x181a0000, 1228 .udt_sock = 0, 1229 .udt_die = 0, 1230 .udt_comp = 1, 1231 .udt_dimm_no = 0, 1232 .udt_dimm_col = 0, 1233 .udt_dimm_row = 0x303, 1234 .udt_dimm_bank = 0, 1235 .udt_dimm_bank_group = 0, 1236 .udt_dimm_subchan = UINT8_MAX, 1237 .udt_dimm_rm = 0, 1238 .udt_dimm_cs = 1 1239 }, { 1240 .udt_desc = "2 DPC 2R cs hash, rank ilv (9)", 1241 .udt_umc = &zen_umc_chan_ilv_cs_hash, 1242 .udt_pa = 0x181c0000, 1243 .udt_pass = B_TRUE, 1244 .udt_norm_addr = 0x181c0000, 1245 .udt_sock = 0, 1246 .udt_die = 0, 1247 .udt_comp = 1, 1248 .udt_dimm_no = 1, 1249 .udt_dimm_col = 0, 1250 .udt_dimm_row = 0x303, 1251 .udt_dimm_bank = 0, 1252 .udt_dimm_bank_group = 0, 1253 .udt_dimm_subchan = UINT8_MAX, 1254 .udt_dimm_rm = 0, 1255 .udt_dimm_cs = 0 1256 }, { 1257 .udt_desc = "2 DPC 2R cs hash, rank ilv (10)", 1258 .udt_umc = &zen_umc_chan_ilv_cs_hash, 1259 .udt_pa = 0x181e0000, 1260 .udt_pass = B_TRUE, 1261 .udt_norm_addr = 0x181e0000, 1262 .udt_sock = 0, 1263 .udt_die = 0, 1264 .udt_comp = 1, 1265 .udt_dimm_no = 1, 1266 .udt_dimm_col = 0, 1267 .udt_dimm_row = 0x303, 1268 .udt_dimm_bank = 0, 1269 .udt_dimm_bank_group = 0, 1270 .udt_dimm_subchan = UINT8_MAX, 1271 .udt_dimm_rm = 0, 1272 .udt_dimm_cs = 1 1273 }, 1274 /* 1275 * For the bank hash we first prove that we can target a given row/column in 1276 * each bank and bank group without hashing (this leads to a total of 16 1277 * combinations). We then later go back and start tweaking the row/column to 1278 * change which bank and group we end up in. 1279 */ 1280 { 1281 .udt_desc = "2 DPC 2R bank hash, rank ilv (0)", 1282 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1283 .udt_pa = 0x0, 1284 .udt_pass = B_TRUE, 1285 .udt_norm_addr = 0x0, 1286 .udt_sock = 0, 1287 .udt_die = 0, 1288 .udt_comp = 1, 1289 .udt_dimm_no = 0, 1290 .udt_dimm_col = 0, 1291 .udt_dimm_row = 0, 1292 .udt_dimm_bank = 0, 1293 .udt_dimm_bank_group = 0, 1294 .udt_dimm_subchan = UINT8_MAX, 1295 .udt_dimm_rm = 0, 1296 .udt_dimm_cs = 0 1297 }, { 1298 .udt_desc = "2 DPC 2R bank hash, rank ilv (1)", 1299 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1300 .udt_pa = 0x8000, 1301 .udt_pass = B_TRUE, 1302 .udt_norm_addr = 0x8000, 1303 .udt_sock = 0, 1304 .udt_die = 0, 1305 .udt_comp = 1, 1306 .udt_dimm_no = 0, 1307 .udt_dimm_col = 0, 1308 .udt_dimm_row = 0, 1309 .udt_dimm_bank = 1, 1310 .udt_dimm_bank_group = 0, 1311 .udt_dimm_subchan = UINT8_MAX, 1312 .udt_dimm_rm = 0, 1313 .udt_dimm_cs = 0 1314 }, { 1315 .udt_desc = "2 DPC 2R bank hash, rank ilv (2)", 1316 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1317 .udt_pa = 0x10000, 1318 .udt_pass = B_TRUE, 1319 .udt_norm_addr = 0x10000, 1320 .udt_sock = 0, 1321 .udt_die = 0, 1322 .udt_comp = 1, 1323 .udt_dimm_no = 0, 1324 .udt_dimm_col = 0, 1325 .udt_dimm_row = 0, 1326 .udt_dimm_bank = 2, 1327 .udt_dimm_bank_group = 0, 1328 .udt_dimm_subchan = UINT8_MAX, 1329 .udt_dimm_rm = 0, 1330 .udt_dimm_cs = 0 1331 }, { 1332 .udt_desc = "2 DPC 2R bank hash, rank ilv (3)", 1333 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1334 .udt_pa = 0x18000, 1335 .udt_pass = B_TRUE, 1336 .udt_norm_addr = 0x18000, 1337 .udt_sock = 0, 1338 .udt_die = 0, 1339 .udt_comp = 1, 1340 .udt_dimm_no = 0, 1341 .udt_dimm_col = 0, 1342 .udt_dimm_row = 0, 1343 .udt_dimm_bank = 3, 1344 .udt_dimm_bank_group = 0, 1345 .udt_dimm_subchan = UINT8_MAX, 1346 .udt_dimm_rm = 0, 1347 .udt_dimm_cs = 0 1348 }, { 1349 .udt_desc = "2 DPC 2R bank hash, rank ilv (4)", 1350 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1351 .udt_pa = 0x2000, 1352 .udt_pass = B_TRUE, 1353 .udt_norm_addr = 0x2000, 1354 .udt_sock = 0, 1355 .udt_die = 0, 1356 .udt_comp = 1, 1357 .udt_dimm_no = 0, 1358 .udt_dimm_col = 0, 1359 .udt_dimm_row = 0, 1360 .udt_dimm_bank = 0, 1361 .udt_dimm_bank_group = 1, 1362 .udt_dimm_subchan = UINT8_MAX, 1363 .udt_dimm_rm = 0, 1364 .udt_dimm_cs = 0 1365 }, { 1366 .udt_desc = "2 DPC 2R bank hash, rank ilv (5)", 1367 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1368 .udt_pa = 0xa000, 1369 .udt_pass = B_TRUE, 1370 .udt_norm_addr = 0xa000, 1371 .udt_sock = 0, 1372 .udt_die = 0, 1373 .udt_comp = 1, 1374 .udt_dimm_no = 0, 1375 .udt_dimm_col = 0, 1376 .udt_dimm_row = 0, 1377 .udt_dimm_bank = 1, 1378 .udt_dimm_bank_group = 1, 1379 .udt_dimm_subchan = UINT8_MAX, 1380 .udt_dimm_rm = 0, 1381 .udt_dimm_cs = 0 1382 }, { 1383 .udt_desc = "2 DPC 2R bank hash, rank ilv (6)", 1384 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1385 .udt_pa = 0x12000, 1386 .udt_pass = B_TRUE, 1387 .udt_norm_addr = 0x12000, 1388 .udt_sock = 0, 1389 .udt_die = 0, 1390 .udt_comp = 1, 1391 .udt_dimm_no = 0, 1392 .udt_dimm_col = 0, 1393 .udt_dimm_row = 0, 1394 .udt_dimm_bank = 2, 1395 .udt_dimm_bank_group = 1, 1396 .udt_dimm_subchan = UINT8_MAX, 1397 .udt_dimm_rm = 0, 1398 .udt_dimm_cs = 0 1399 }, { 1400 .udt_desc = "2 DPC 2R bank hash, rank ilv (7)", 1401 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1402 .udt_pa = 0x1a000, 1403 .udt_pass = B_TRUE, 1404 .udt_norm_addr = 0x1a000, 1405 .udt_sock = 0, 1406 .udt_die = 0, 1407 .udt_comp = 1, 1408 .udt_dimm_no = 0, 1409 .udt_dimm_col = 0, 1410 .udt_dimm_row = 0, 1411 .udt_dimm_bank = 3, 1412 .udt_dimm_bank_group = 1, 1413 .udt_dimm_subchan = UINT8_MAX, 1414 .udt_dimm_rm = 0, 1415 .udt_dimm_cs = 0 1416 }, { 1417 .udt_desc = "2 DPC 2R bank hash, rank ilv (8)", 1418 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1419 .udt_pa = 0x4000, 1420 .udt_pass = B_TRUE, 1421 .udt_norm_addr = 0x4000, 1422 .udt_sock = 0, 1423 .udt_die = 0, 1424 .udt_comp = 1, 1425 .udt_dimm_no = 0, 1426 .udt_dimm_col = 0, 1427 .udt_dimm_row = 0, 1428 .udt_dimm_bank = 0, 1429 .udt_dimm_bank_group = 2, 1430 .udt_dimm_subchan = UINT8_MAX, 1431 .udt_dimm_rm = 0, 1432 .udt_dimm_cs = 0 1433 }, { 1434 .udt_desc = "2 DPC 2R bank hash, rank ilv (9)", 1435 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1436 .udt_pa = 0xc000, 1437 .udt_pass = B_TRUE, 1438 .udt_norm_addr = 0xc000, 1439 .udt_sock = 0, 1440 .udt_die = 0, 1441 .udt_comp = 1, 1442 .udt_dimm_no = 0, 1443 .udt_dimm_col = 0, 1444 .udt_dimm_row = 0, 1445 .udt_dimm_bank = 1, 1446 .udt_dimm_bank_group = 2, 1447 .udt_dimm_subchan = UINT8_MAX, 1448 .udt_dimm_rm = 0, 1449 .udt_dimm_cs = 0 1450 }, { 1451 .udt_desc = "2 DPC 2R bank hash, rank ilv (10)", 1452 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1453 .udt_pa = 0x14000, 1454 .udt_pass = B_TRUE, 1455 .udt_norm_addr = 0x14000, 1456 .udt_sock = 0, 1457 .udt_die = 0, 1458 .udt_comp = 1, 1459 .udt_dimm_no = 0, 1460 .udt_dimm_col = 0, 1461 .udt_dimm_row = 0, 1462 .udt_dimm_bank = 2, 1463 .udt_dimm_bank_group = 2, 1464 .udt_dimm_subchan = UINT8_MAX, 1465 .udt_dimm_rm = 0, 1466 .udt_dimm_cs = 0 1467 }, { 1468 .udt_desc = "2 DPC 2R bank hash, rank ilv (11)", 1469 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1470 .udt_pa = 0x1c000, 1471 .udt_pass = B_TRUE, 1472 .udt_norm_addr = 0x1c000, 1473 .udt_sock = 0, 1474 .udt_die = 0, 1475 .udt_comp = 1, 1476 .udt_dimm_no = 0, 1477 .udt_dimm_col = 0, 1478 .udt_dimm_row = 0, 1479 .udt_dimm_bank = 3, 1480 .udt_dimm_bank_group = 2, 1481 .udt_dimm_subchan = UINT8_MAX, 1482 .udt_dimm_rm = 0, 1483 .udt_dimm_cs = 0 1484 }, { 1485 .udt_desc = "2 DPC 2R bank hash, rank ilv (12)", 1486 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1487 .udt_pa = 0x6000, 1488 .udt_pass = B_TRUE, 1489 .udt_norm_addr = 0x6000, 1490 .udt_sock = 0, 1491 .udt_die = 0, 1492 .udt_comp = 1, 1493 .udt_dimm_no = 0, 1494 .udt_dimm_col = 0, 1495 .udt_dimm_row = 0, 1496 .udt_dimm_bank = 0, 1497 .udt_dimm_bank_group = 3, 1498 .udt_dimm_subchan = UINT8_MAX, 1499 .udt_dimm_rm = 0, 1500 .udt_dimm_cs = 0 1501 }, { 1502 .udt_desc = "2 DPC 2R bank hash, rank ilv (13)", 1503 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1504 .udt_pa = 0xe000, 1505 .udt_pass = B_TRUE, 1506 .udt_norm_addr = 0xe000, 1507 .udt_sock = 0, 1508 .udt_die = 0, 1509 .udt_comp = 1, 1510 .udt_dimm_no = 0, 1511 .udt_dimm_col = 0, 1512 .udt_dimm_row = 0, 1513 .udt_dimm_bank = 1, 1514 .udt_dimm_bank_group = 3, 1515 .udt_dimm_subchan = UINT8_MAX, 1516 .udt_dimm_rm = 0, 1517 .udt_dimm_cs = 0 1518 }, { 1519 .udt_desc = "2 DPC 2R bank hash, rank ilv (14)", 1520 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1521 .udt_pa = 0x16000, 1522 .udt_pass = B_TRUE, 1523 .udt_norm_addr = 0x16000, 1524 .udt_sock = 0, 1525 .udt_die = 0, 1526 .udt_comp = 1, 1527 .udt_dimm_no = 0, 1528 .udt_dimm_col = 0, 1529 .udt_dimm_row = 0, 1530 .udt_dimm_bank = 2, 1531 .udt_dimm_bank_group = 3, 1532 .udt_dimm_subchan = UINT8_MAX, 1533 .udt_dimm_rm = 0, 1534 .udt_dimm_cs = 0 1535 }, { 1536 .udt_desc = "2 DPC 2R bank hash, rank ilv (15)", 1537 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1538 .udt_pa = 0x1e000, 1539 .udt_pass = B_TRUE, 1540 .udt_norm_addr = 0x1e000, 1541 .udt_sock = 0, 1542 .udt_die = 0, 1543 .udt_comp = 1, 1544 .udt_dimm_no = 0, 1545 .udt_dimm_col = 0, 1546 .udt_dimm_row = 0, 1547 .udt_dimm_bank = 3, 1548 .udt_dimm_bank_group = 3, 1549 .udt_dimm_subchan = UINT8_MAX, 1550 .udt_dimm_rm = 0, 1551 .udt_dimm_cs = 0 1552 }, { 1553 .udt_desc = "2 DPC 2R bank hash, rank ilv (16)", 1554 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1555 .udt_pa = 0x79c000, 1556 .udt_pass = B_TRUE, 1557 .udt_norm_addr = 0x79c000, 1558 .udt_sock = 0, 1559 .udt_die = 0, 1560 .udt_comp = 1, 1561 .udt_dimm_no = 0, 1562 .udt_dimm_col = 0, 1563 .udt_dimm_row = 0xf, 1564 .udt_dimm_bank = 0, 1565 .udt_dimm_bank_group = 1, 1566 .udt_dimm_subchan = UINT8_MAX, 1567 .udt_dimm_rm = 0, 1568 .udt_dimm_cs = 0 1569 }, { 1570 .udt_desc = "2 DPC 2R bank hash, rank ilv (17)", 1571 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1572 .udt_pa = 0x7f9c000, 1573 .udt_pass = B_TRUE, 1574 .udt_norm_addr = 0x7f9c000, 1575 .udt_sock = 0, 1576 .udt_die = 0, 1577 .udt_comp = 1, 1578 .udt_dimm_no = 0, 1579 .udt_dimm_col = 0, 1580 .udt_dimm_row = 0xff, 1581 .udt_dimm_bank = 3, 1582 .udt_dimm_bank_group = 2, 1583 .udt_dimm_subchan = UINT8_MAX, 1584 .udt_dimm_rm = 0, 1585 .udt_dimm_cs = 0 1586 }, { 1587 .udt_desc = "2 DPC 2R bank hash, rank ilv (18)", 1588 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1589 .udt_pa = 0x7ff9c000, 1590 .udt_pass = B_TRUE, 1591 .udt_norm_addr = 0x7ff9c000, 1592 .udt_sock = 0, 1593 .udt_die = 0, 1594 .udt_comp = 1, 1595 .udt_dimm_no = 0, 1596 .udt_dimm_col = 0, 1597 .udt_dimm_row = 0xfff, 1598 .udt_dimm_bank = 0, 1599 .udt_dimm_bank_group = 1, 1600 .udt_dimm_subchan = UINT8_MAX, 1601 .udt_dimm_rm = 0, 1602 .udt_dimm_cs = 0 1603 }, { 1604 .udt_desc = "2 DPC 2R bank hash, rank ilv (19)", 1605 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1606 .udt_pa = 0x71c000, 1607 .udt_pass = B_TRUE, 1608 .udt_norm_addr = 0x71c000, 1609 .udt_sock = 0, 1610 .udt_die = 0, 1611 .udt_comp = 1, 1612 .udt_dimm_no = 0, 1613 .udt_dimm_col = 0, 1614 .udt_dimm_row = 0xe, 1615 .udt_dimm_bank = 0, 1616 .udt_dimm_bank_group = 0, 1617 .udt_dimm_subchan = UINT8_MAX, 1618 .udt_dimm_rm = 0, 1619 .udt_dimm_cs = 0 1620 }, { 1621 .udt_desc = "2 DPC 2R bank hash, rank ilv (20)", 1622 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1623 .udt_pa = 0x71c118, 1624 .udt_pass = B_TRUE, 1625 .udt_norm_addr = 0x71c118, 1626 .udt_sock = 0, 1627 .udt_die = 0, 1628 .udt_comp = 1, 1629 .udt_dimm_no = 0, 1630 .udt_dimm_col = 0x23, 1631 .udt_dimm_row = 0xe, 1632 .udt_dimm_bank = 0, 1633 .udt_dimm_bank_group = 0, 1634 .udt_dimm_subchan = UINT8_MAX, 1635 .udt_dimm_rm = 0, 1636 .udt_dimm_cs = 0 1637 }, 1638 /* 1639 * Bank swapping. We basically do a few sanity tests on this just to make sure 1640 * the right bits are triggering things here in the first DIMM/rank. 1641 */ 1642 { 1643 .udt_desc = "2 DPC 2R bank swap, rank ilv (0)", 1644 .udt_umc = &zen_umc_chan_ilv_bank_swap, 1645 .udt_pa = 0x4247, 1646 .udt_pass = B_TRUE, 1647 .udt_norm_addr = 0x4247, 1648 .udt_sock = 0, 1649 .udt_die = 0, 1650 .udt_comp = 1, 1651 .udt_dimm_no = 0, 1652 .udt_dimm_col = 0x80, 1653 .udt_dimm_row = 0, 1654 .udt_dimm_bank = 1, 1655 .udt_dimm_bank_group = 1, 1656 .udt_dimm_subchan = UINT8_MAX, 1657 .udt_dimm_rm = 0, 1658 .udt_dimm_cs = 0 1659 }, { 1660 .udt_desc = "2 DPC 2R bank swap, rank ilv (1)", 1661 .udt_umc = &zen_umc_chan_ilv_bank_swap, 1662 .udt_pa = 0xff6214247, 1663 .udt_pass = B_TRUE, 1664 .udt_norm_addr = 0xff6214247, 1665 .udt_sock = 0, 1666 .udt_die = 0, 1667 .udt_comp = 1, 1668 .udt_dimm_no = 0, 1669 .udt_dimm_col = 0x280, 1670 .udt_dimm_row = 0x1fec4, 1671 .udt_dimm_bank = 1, 1672 .udt_dimm_bank_group = 1, 1673 .udt_dimm_subchan = UINT8_MAX, 1674 .udt_dimm_rm = 0, 1675 .udt_dimm_cs = 0 1676 }, { 1677 .udt_desc = "Basic DDR5 Sub-channel (0)", 1678 .udt_umc = &zen_umc_chan_subchan_no_hash, 1679 .udt_pa = 0x0, 1680 .udt_pass = B_TRUE, 1681 .udt_norm_addr = 0x0, 1682 .udt_sock = 0, 1683 .udt_die = 0, 1684 .udt_comp = 1, 1685 .udt_dimm_no = 0, 1686 .udt_dimm_col = 0x0, 1687 .udt_dimm_row = 0x0, 1688 .udt_dimm_bank = 0, 1689 .udt_dimm_bank_group = 0, 1690 .udt_dimm_subchan = 0, 1691 .udt_dimm_rm = 0, 1692 .udt_dimm_cs = 0 1693 }, { 1694 .udt_desc = "Basic DDR5 Sub-channel (1)", 1695 .udt_umc = &zen_umc_chan_subchan_no_hash, 1696 .udt_pa = 0x9999, 1697 .udt_pass = B_TRUE, 1698 .udt_norm_addr = 0x9999, 1699 .udt_sock = 0, 1700 .udt_die = 0, 1701 .udt_comp = 1, 1702 .udt_dimm_no = 0, 1703 .udt_dimm_col = 0x336, 1704 .udt_dimm_row = 0x0, 1705 .udt_dimm_bank = 0, 1706 .udt_dimm_bank_group = 1, 1707 .udt_dimm_subchan = 0, 1708 .udt_dimm_rm = 0, 1709 .udt_dimm_cs = 0 1710 }, { 1711 .udt_desc = "Basic DDR5 Sub-channel (2)", 1712 .udt_umc = &zen_umc_chan_subchan_no_hash, 1713 .udt_pa = 0x99d9, 1714 .udt_pass = B_TRUE, 1715 .udt_norm_addr = 0x99d9, 1716 .udt_sock = 0, 1717 .udt_die = 0, 1718 .udt_comp = 1, 1719 .udt_dimm_no = 0, 1720 .udt_dimm_col = 0x336, 1721 .udt_dimm_row = 0x0, 1722 .udt_dimm_bank = 0, 1723 .udt_dimm_bank_group = 1, 1724 .udt_dimm_subchan = 1, 1725 .udt_dimm_rm = 0, 1726 .udt_dimm_cs = 0 1727 }, { 1728 .udt_desc = NULL 1729 } }; 1730