1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2023 Oxide Computer Company 14 */ 15 16 /* 17 * Here we test several different channel related test cases. In particular, we 18 * want to exercise the following situations: 19 * 20 * o Multiple DIMMs per channel (no hashing) 21 * o Multiple DIMMs per channel (chip-select interleaving) 22 * o CS Hashing 23 * o Bank Hashing 24 * o Bank Swaps 25 * o Basic sub-channel 26 * 27 * For all of these, we don't do anything special from the Data Fabric to 28 * strictly allow us to reason about the channel logic here. 29 * 30 * Currently, we do not have tests for the following because we don't have a 31 * great sense of how the AMD SoC will set this up for the decoder: 32 * 33 * o Cases where rank-multiplication and hashing are taking place 34 * o Cases where sub-channel hashing is being used 35 */ 36 37 #include "zen_umc_test.h" 38 39 /* 40 * This has two of our favorite 64 GiB DIMMs. Everything is done out linearly. 41 * Because of this, we don't apply any channel offsets. 42 */ 43 static const zen_umc_t zen_umc_chan_no_hash = { 44 .umc_tom = 4ULL * 1024ULL * 1024ULL * 1024ULL, 45 .umc_tom2 = 128ULL * 1024ULL * 1024ULL * 1024ULL, 46 .umc_df_rev = DF_REV_3, 47 /* Per milan_decomp */ 48 .umc_decomp = { 49 .dfd_sock_mask = 0x01, 50 .dfd_die_mask = 0x00, 51 .dfd_node_mask = 0x20, 52 .dfd_comp_mask = 0x1f, 53 .dfd_sock_shift = 0, 54 .dfd_die_shift = 0, 55 .dfd_node_shift = 5, 56 .dfd_comp_shift = 0 57 }, 58 .umc_ndfs = 1, 59 .umc_dfs = { { 60 .zud_dfno = 0, 61 .zud_ccm_inst = 0, 62 .zud_dram_nrules = 1, 63 .zud_nchan = 1, 64 .zud_cs_nremap = 0, 65 .zud_hole_base = 0, 66 .zud_rules = { { 67 .ddr_flags = DF_DRAM_F_VALID, 68 .ddr_base = 0, 69 .ddr_limit = 128ULL * 1024ULL * 1024ULL * 1024ULL, 70 .ddr_dest_fabid = 1, 71 .ddr_sock_ileave_bits = 0, 72 .ddr_die_ileave_bits = 0, 73 .ddr_addr_start = 9, 74 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 75 } }, 76 .zud_chan = { { 77 .chan_flags = UMC_CHAN_F_ECC_EN, 78 .chan_fabid = 1, 79 .chan_instid = 1, 80 .chan_logid = 0, 81 .chan_nrules = 1, 82 .chan_type = UMC_DIMM_T_DDR4, 83 .chan_rules = { { 84 .ddr_flags = DF_DRAM_F_VALID, 85 .ddr_base = 0, 86 .ddr_limit = 128ULL * 1024ULL * 1024ULL * 87 1024ULL, 88 .ddr_dest_fabid = 1, 89 .ddr_sock_ileave_bits = 0, 90 .ddr_die_ileave_bits = 0, 91 .ddr_addr_start = 9, 92 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 93 } }, 94 .chan_dimms = { { 95 .ud_flags = UMC_DIMM_F_VALID, 96 .ud_width = UMC_DIMM_W_X4, 97 .ud_kind = UMC_DIMM_K_RDIMM, 98 .ud_dimmno = 0, 99 .ud_cs = { { 100 .ucs_base = { 101 .udb_base = 0, 102 .udb_valid = B_TRUE 103 }, 104 .ucs_base_mask = 0x7ffffffff, 105 .ucs_nbanks = 0x4, 106 .ucs_ncol = 0xa, 107 .ucs_nrow_lo = 0x12, 108 .ucs_nbank_groups = 0x2, 109 .ucs_row_hi_bit = 0x18, 110 .ucs_row_low_bit = 0x11, 111 .ucs_bank_bits = { 0xf, 0x10, 0xd, 112 0xe }, 113 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 114 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 115 }, { 116 .ucs_base = { 117 .udb_base = 0x800000000, 118 .udb_valid = B_TRUE 119 }, 120 .ucs_base_mask = 0x7ffffffff, 121 .ucs_nbanks = 0x4, 122 .ucs_ncol = 0xa, 123 .ucs_nrow_lo = 0x12, 124 .ucs_nbank_groups = 0x2, 125 .ucs_row_hi_bit = 0x18, 126 .ucs_row_low_bit = 0x11, 127 .ucs_bank_bits = { 0xf, 0x10, 0xd, 128 0xe }, 129 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 130 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 131 } } 132 }, { 133 .ud_flags = UMC_DIMM_F_VALID, 134 .ud_width = UMC_DIMM_W_X4, 135 .ud_kind = UMC_DIMM_K_RDIMM, 136 .ud_dimmno = 1, 137 .ud_cs = { { 138 .ucs_base = { 139 .udb_base = 0x1000000000, 140 .udb_valid = B_TRUE 141 }, 142 .ucs_base_mask = 0x7ffffffff, 143 .ucs_nbanks = 0x4, 144 .ucs_ncol = 0xa, 145 .ucs_nrow_lo = 0x12, 146 .ucs_nbank_groups = 0x2, 147 .ucs_row_hi_bit = 0x18, 148 .ucs_row_low_bit = 0x11, 149 .ucs_bank_bits = { 0xf, 0x10, 0xd, 150 0xe }, 151 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 152 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 153 }, { 154 .ucs_base = { 155 .udb_base = 0x1800000000, 156 .udb_valid = B_TRUE 157 }, 158 .ucs_base_mask = 0x7ffffffff, 159 .ucs_nbanks = 0x4, 160 .ucs_ncol = 0xa, 161 .ucs_nrow_lo = 0x12, 162 .ucs_nbank_groups = 0x2, 163 .ucs_row_hi_bit = 0x18, 164 .ucs_row_low_bit = 0x11, 165 .ucs_bank_bits = { 0xf, 0x10, 0xd, 166 0xe }, 167 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 168 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 169 } } 170 } } 171 } } 172 } } 173 }; 174 175 /* 176 * This is a variant on the prior where we begin to interleave across all 4 177 * ranks in a channel, which AMD calls chip-select interleaving. This basically 178 * uses bits in the middle of the address to select the rank and therefore 179 * shifts all the other bits that get used for rank and bank selection. This 180 * works by shifting which address bits are used to actually determine the row 181 * up, allowing us to interleave in the middle of this. 182 */ 183 static const zen_umc_t zen_umc_chan_ilv = { 184 .umc_tom = 4ULL * 1024ULL * 1024ULL * 1024ULL, 185 .umc_tom2 = 128ULL * 1024ULL * 1024ULL * 1024ULL, 186 .umc_df_rev = DF_REV_3, 187 /* Per milan_decomp */ 188 .umc_decomp = { 189 .dfd_sock_mask = 0x01, 190 .dfd_die_mask = 0x00, 191 .dfd_node_mask = 0x20, 192 .dfd_comp_mask = 0x1f, 193 .dfd_sock_shift = 0, 194 .dfd_die_shift = 0, 195 .dfd_node_shift = 5, 196 .dfd_comp_shift = 0 197 }, 198 .umc_ndfs = 1, 199 .umc_dfs = { { 200 .zud_dfno = 0, 201 .zud_ccm_inst = 0, 202 .zud_dram_nrules = 1, 203 .zud_nchan = 1, 204 .zud_cs_nremap = 0, 205 .zud_hole_base = 0, 206 .zud_rules = { { 207 .ddr_flags = DF_DRAM_F_VALID, 208 .ddr_base = 0, 209 .ddr_limit = 128ULL * 1024ULL * 1024ULL * 1024ULL, 210 .ddr_dest_fabid = 1, 211 .ddr_sock_ileave_bits = 0, 212 .ddr_die_ileave_bits = 0, 213 .ddr_addr_start = 9, 214 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 215 } }, 216 .zud_chan = { { 217 .chan_flags = UMC_CHAN_F_ECC_EN, 218 .chan_fabid = 1, 219 .chan_instid = 1, 220 .chan_logid = 0, 221 .chan_nrules = 1, 222 .chan_type = UMC_DIMM_T_DDR4, 223 .chan_rules = { { 224 .ddr_flags = DF_DRAM_F_VALID, 225 .ddr_base = 0, 226 .ddr_limit = 128ULL * 1024ULL * 1024ULL * 227 1024ULL, 228 .ddr_dest_fabid = 1, 229 .ddr_sock_ileave_bits = 0, 230 .ddr_die_ileave_bits = 0, 231 .ddr_addr_start = 9, 232 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 233 } }, 234 .chan_dimms = { { 235 .ud_flags = UMC_DIMM_F_VALID, 236 .ud_width = UMC_DIMM_W_X4, 237 .ud_kind = UMC_DIMM_K_RDIMM, 238 .ud_dimmno = 0, 239 .ud_cs = { { 240 .ucs_base = { 241 .udb_base = 0, 242 .udb_valid = B_TRUE 243 }, 244 .ucs_base_mask = 0x1ffff9ffff, 245 .ucs_nbanks = 0x4, 246 .ucs_ncol = 0xa, 247 .ucs_nrow_lo = 0x12, 248 .ucs_nbank_groups = 0x2, 249 .ucs_row_hi_bit = 0x18, 250 .ucs_row_low_bit = 0x13, 251 .ucs_bank_bits = { 0xd, 0xe, 0xf, 252 0x10 }, 253 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 254 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 255 }, { 256 .ucs_base = { 257 .udb_base = 0x20000, 258 .udb_valid = B_TRUE 259 }, 260 .ucs_base_mask = 0x1ffff9ffff, 261 .ucs_nbanks = 0x4, 262 .ucs_ncol = 0xa, 263 .ucs_nrow_lo = 0x12, 264 .ucs_nbank_groups = 0x2, 265 .ucs_row_hi_bit = 0x18, 266 .ucs_row_low_bit = 0x13, 267 .ucs_bank_bits = { 0xd, 0xe, 0xf, 268 0x10 }, 269 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 270 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 271 } } 272 }, { 273 .ud_flags = UMC_DIMM_F_VALID, 274 .ud_width = UMC_DIMM_W_X4, 275 .ud_kind = UMC_DIMM_K_RDIMM, 276 .ud_dimmno = 1, 277 .ud_cs = { { 278 .ucs_base = { 279 .udb_base = 0x40000, 280 .udb_valid = B_TRUE 281 }, 282 .ucs_base_mask = 0x1ffff9ffff, 283 .ucs_nbanks = 0x4, 284 .ucs_ncol = 0xa, 285 .ucs_nrow_lo = 0x12, 286 .ucs_nbank_groups = 0x2, 287 .ucs_row_hi_bit = 0x18, 288 .ucs_row_low_bit = 0x13, 289 .ucs_bank_bits = { 0xd, 0xe, 0xf, 290 0x10 }, 291 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 292 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 293 }, { 294 .ucs_base = { 295 .udb_base = 0x60000, 296 .udb_valid = B_TRUE 297 }, 298 .ucs_base_mask = 0x1ffff9ffff, 299 .ucs_nbanks = 0x4, 300 .ucs_ncol = 0xa, 301 .ucs_nrow_lo = 0x12, 302 .ucs_nbank_groups = 0x2, 303 .ucs_row_hi_bit = 0x18, 304 .ucs_row_low_bit = 0x13, 305 .ucs_bank_bits = { 0xd, 0xe, 0xf, 306 0x10 }, 307 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 308 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 309 } } 310 } } 311 } } 312 } } 313 }; 314 315 /* 316 * This sets up a CS hash across all 4 ranks. The actual values here are 317 * representative of a set up we've seen on the CPU. 318 */ 319 static const zen_umc_t zen_umc_chan_ilv_cs_hash = { 320 .umc_tom = 4ULL * 1024ULL * 1024ULL * 1024ULL, 321 .umc_tom2 = 128ULL * 1024ULL * 1024ULL * 1024ULL, 322 .umc_df_rev = DF_REV_3, 323 /* Per milan_decomp */ 324 .umc_decomp = { 325 .dfd_sock_mask = 0x01, 326 .dfd_die_mask = 0x00, 327 .dfd_node_mask = 0x20, 328 .dfd_comp_mask = 0x1f, 329 .dfd_sock_shift = 0, 330 .dfd_die_shift = 0, 331 .dfd_node_shift = 5, 332 .dfd_comp_shift = 0 333 }, 334 .umc_ndfs = 1, 335 .umc_dfs = { { 336 .zud_dfno = 0, 337 .zud_ccm_inst = 0, 338 .zud_dram_nrules = 1, 339 .zud_nchan = 1, 340 .zud_cs_nremap = 0, 341 .zud_hole_base = 0, 342 .zud_rules = { { 343 .ddr_flags = DF_DRAM_F_VALID, 344 .ddr_base = 0, 345 .ddr_limit = 128ULL * 1024ULL * 1024ULL * 1024ULL, 346 .ddr_dest_fabid = 1, 347 .ddr_sock_ileave_bits = 0, 348 .ddr_die_ileave_bits = 0, 349 .ddr_addr_start = 9, 350 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 351 } }, 352 .zud_chan = { { 353 .chan_flags = UMC_CHAN_F_ECC_EN, 354 .chan_fabid = 1, 355 .chan_instid = 1, 356 .chan_logid = 0, 357 .chan_nrules = 1, 358 .chan_type = UMC_DIMM_T_DDR4, 359 .chan_rules = { { 360 .ddr_flags = DF_DRAM_F_VALID, 361 .ddr_base = 0, 362 .ddr_limit = 128ULL * 1024ULL * 1024ULL * 363 1024ULL, 364 .ddr_dest_fabid = 1, 365 .ddr_sock_ileave_bits = 0, 366 .ddr_die_ileave_bits = 0, 367 .ddr_addr_start = 9, 368 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 369 } }, 370 .chan_dimms = { { 371 .ud_flags = UMC_DIMM_F_VALID, 372 .ud_width = UMC_DIMM_W_X4, 373 .ud_kind = UMC_DIMM_K_RDIMM, 374 .ud_dimmno = 0, 375 .ud_cs = { { 376 .ucs_base = { 377 .udb_base = 0, 378 .udb_valid = B_TRUE 379 }, 380 .ucs_base_mask = 0x1ffff9ffff, 381 .ucs_nbanks = 0x4, 382 .ucs_ncol = 0xa, 383 .ucs_nrow_lo = 0x12, 384 .ucs_nbank_groups = 0x2, 385 .ucs_row_hi_bit = 0x18, 386 .ucs_row_low_bit = 0x13, 387 .ucs_bank_bits = { 0xd, 0xe, 0xf, 388 0x10 }, 389 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 390 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 391 }, { 392 .ucs_base = { 393 .udb_base = 0x20000, 394 .udb_valid = B_TRUE 395 }, 396 .ucs_base_mask = 0x1ffff9ffff, 397 .ucs_nbanks = 0x4, 398 .ucs_ncol = 0xa, 399 .ucs_nrow_lo = 0x12, 400 .ucs_nbank_groups = 0x2, 401 .ucs_row_hi_bit = 0x18, 402 .ucs_row_low_bit = 0x13, 403 .ucs_bank_bits = { 0xd, 0xe, 0xf, 404 0x10 }, 405 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 406 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 407 } } 408 }, { 409 .ud_flags = UMC_DIMM_F_VALID, 410 .ud_width = UMC_DIMM_W_X4, 411 .ud_kind = UMC_DIMM_K_RDIMM, 412 .ud_dimmno = 1, 413 .ud_cs = { { 414 .ucs_base = { 415 .udb_base = 0x40000, 416 .udb_valid = B_TRUE 417 }, 418 .ucs_base_mask = 0x1ffff9ffff, 419 .ucs_nbanks = 0x4, 420 .ucs_ncol = 0xa, 421 .ucs_nrow_lo = 0x12, 422 .ucs_nbank_groups = 0x2, 423 .ucs_row_hi_bit = 0x18, 424 .ucs_row_low_bit = 0x13, 425 .ucs_bank_bits = { 0xd, 0xe, 0xf, 426 0x10 }, 427 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 428 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 429 }, { 430 .ucs_base = { 431 .udb_base = 0x60000, 432 .udb_valid = B_TRUE 433 }, 434 .ucs_base_mask = 0x1ffff9ffff, 435 .ucs_nbanks = 0x4, 436 .ucs_ncol = 0xa, 437 .ucs_nrow_lo = 0x12, 438 .ucs_nbank_groups = 0x2, 439 .ucs_row_hi_bit = 0x18, 440 .ucs_row_low_bit = 0x13, 441 .ucs_bank_bits = { 0xd, 0xe, 0xf, 442 0x10 }, 443 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 444 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 445 } } 446 } }, 447 .chan_hash = { 448 .uch_flags = UMC_CHAN_HASH_F_CS, 449 .uch_cs_hashes = { { 450 .uah_addr_xor = 0xaaaa80000, 451 .uah_en = B_TRUE 452 }, { 453 .uah_addr_xor = 0x1555500000, 454 .uah_en = B_TRUE 455 } } 456 } 457 } } 458 } } 459 }; 460 461 /* 462 * This enables bank hashing across both of the DIMMs in this configuration. The 463 * use of the row and not the column to select the bank is based on a CPU config 464 * seen in the wild. 465 */ 466 static const zen_umc_t zen_umc_chan_ilv_bank_hash = { 467 .umc_tom = 4ULL * 1024ULL * 1024ULL * 1024ULL, 468 .umc_tom2 = 128ULL * 1024ULL * 1024ULL * 1024ULL, 469 .umc_df_rev = DF_REV_3, 470 /* Per milan_decomp */ 471 .umc_decomp = { 472 .dfd_sock_mask = 0x01, 473 .dfd_die_mask = 0x00, 474 .dfd_node_mask = 0x20, 475 .dfd_comp_mask = 0x1f, 476 .dfd_sock_shift = 0, 477 .dfd_die_shift = 0, 478 .dfd_node_shift = 5, 479 .dfd_comp_shift = 0 480 }, 481 .umc_ndfs = 1, 482 .umc_dfs = { { 483 .zud_dfno = 0, 484 .zud_ccm_inst = 0, 485 .zud_dram_nrules = 1, 486 .zud_nchan = 1, 487 .zud_cs_nremap = 0, 488 .zud_hole_base = 0, 489 .zud_rules = { { 490 .ddr_flags = DF_DRAM_F_VALID, 491 .ddr_base = 0, 492 .ddr_limit = 128ULL * 1024ULL * 1024ULL * 1024ULL, 493 .ddr_dest_fabid = 1, 494 .ddr_sock_ileave_bits = 0, 495 .ddr_die_ileave_bits = 0, 496 .ddr_addr_start = 9, 497 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 498 } }, 499 .zud_chan = { { 500 .chan_flags = UMC_CHAN_F_ECC_EN, 501 .chan_fabid = 1, 502 .chan_instid = 1, 503 .chan_logid = 0, 504 .chan_nrules = 1, 505 .chan_type = UMC_DIMM_T_DDR4, 506 .chan_rules = { { 507 .ddr_flags = DF_DRAM_F_VALID, 508 .ddr_base = 0, 509 .ddr_limit = 128ULL * 1024ULL * 1024ULL * 510 1024ULL, 511 .ddr_dest_fabid = 1, 512 .ddr_sock_ileave_bits = 0, 513 .ddr_die_ileave_bits = 0, 514 .ddr_addr_start = 9, 515 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 516 } }, 517 .chan_dimms = { { 518 .ud_flags = UMC_DIMM_F_VALID, 519 .ud_width = UMC_DIMM_W_X4, 520 .ud_kind = UMC_DIMM_K_RDIMM, 521 .ud_dimmno = 0, 522 .ud_cs = { { 523 .ucs_base = { 524 .udb_base = 0, 525 .udb_valid = B_TRUE 526 }, 527 .ucs_base_mask = 0x1ffff9ffff, 528 .ucs_nbanks = 0x4, 529 .ucs_ncol = 0xa, 530 .ucs_nrow_lo = 0x12, 531 .ucs_nbank_groups = 0x2, 532 .ucs_row_hi_bit = 0x18, 533 .ucs_row_low_bit = 0x13, 534 .ucs_bank_bits = { 0xd, 0xe, 0xf, 535 0x10 }, 536 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 537 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 538 }, { 539 .ucs_base = { 540 .udb_base = 0x20000, 541 .udb_valid = B_TRUE 542 }, 543 .ucs_base_mask = 0x1ffff9ffff, 544 .ucs_nbanks = 0x4, 545 .ucs_ncol = 0xa, 546 .ucs_nrow_lo = 0x12, 547 .ucs_nbank_groups = 0x2, 548 .ucs_row_hi_bit = 0x18, 549 .ucs_row_low_bit = 0x13, 550 .ucs_bank_bits = { 0xd, 0xe, 0xf, 551 0x10 }, 552 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 553 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 554 } } 555 }, { 556 .ud_flags = UMC_DIMM_F_VALID, 557 .ud_width = UMC_DIMM_W_X4, 558 .ud_kind = UMC_DIMM_K_RDIMM, 559 .ud_dimmno = 1, 560 .ud_cs = { { 561 .ucs_base = { 562 .udb_base = 0x40000, 563 .udb_valid = B_TRUE 564 }, 565 .ucs_base_mask = 0x1ffff9ffff, 566 .ucs_nbanks = 0x4, 567 .ucs_ncol = 0xa, 568 .ucs_nrow_lo = 0x12, 569 .ucs_nbank_groups = 0x2, 570 .ucs_row_hi_bit = 0x18, 571 .ucs_row_low_bit = 0x13, 572 .ucs_bank_bits = { 0xd, 0xe, 0xf, 573 0x10 }, 574 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 575 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 576 }, { 577 .ucs_base = { 578 .udb_base = 0x60000, 579 .udb_valid = B_TRUE 580 }, 581 .ucs_base_mask = 0x1ffff9ffff, 582 .ucs_nbanks = 0x4, 583 .ucs_ncol = 0xa, 584 .ucs_nrow_lo = 0x12, 585 .ucs_nbank_groups = 0x2, 586 .ucs_row_hi_bit = 0x18, 587 .ucs_row_low_bit = 0x13, 588 .ucs_bank_bits = { 0xd, 0xe, 0xf, 589 0x10 }, 590 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 591 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 592 } } 593 } }, 594 .chan_hash = { 595 .uch_flags = UMC_CHAN_HASH_F_BANK, 596 .uch_bank_hashes = { { 597 .ubh_row_xor = 0x11111, 598 .ubh_col_xor = 0, 599 .ubh_en = B_TRUE 600 }, { 601 .ubh_row_xor = 0x22222, 602 .ubh_col_xor = 0, 603 .ubh_en = B_TRUE 604 }, { 605 .ubh_row_xor = 0x4444, 606 .ubh_col_xor = 0, 607 .ubh_en = B_TRUE 608 }, { 609 .ubh_row_xor = 0x8888, 610 .ubh_col_xor = 0, 611 .ubh_en = B_TRUE 612 } } 613 } 614 } } 615 } } 616 }; 617 618 /* 619 * Some configurations allow optional bank swaps where by the bits we use for 620 * the column and the bank are swapped around. Do one of these just to make sure 621 * we haven't built in any surprise dependencies. 622 */ 623 static const zen_umc_t zen_umc_chan_ilv_bank_swap = { 624 .umc_tom = 4ULL * 1024ULL * 1024ULL * 1024ULL, 625 .umc_tom2 = 128ULL * 1024ULL * 1024ULL * 1024ULL, 626 .umc_df_rev = DF_REV_3, 627 .umc_decomp = { 628 .dfd_sock_mask = 0x01, 629 .dfd_die_mask = 0x00, 630 .dfd_node_mask = 0x20, 631 .dfd_comp_mask = 0x1f, 632 .dfd_sock_shift = 0, 633 .dfd_die_shift = 0, 634 .dfd_node_shift = 5, 635 .dfd_comp_shift = 0 636 }, 637 .umc_ndfs = 1, 638 .umc_dfs = { { 639 .zud_dfno = 0, 640 .zud_ccm_inst = 0, 641 .zud_dram_nrules = 1, 642 .zud_nchan = 1, 643 .zud_cs_nremap = 0, 644 .zud_hole_base = 0, 645 .zud_rules = { { 646 .ddr_flags = DF_DRAM_F_VALID, 647 .ddr_base = 0, 648 .ddr_limit = 128ULL * 1024ULL * 1024ULL * 1024ULL, 649 .ddr_dest_fabid = 1, 650 .ddr_sock_ileave_bits = 0, 651 .ddr_die_ileave_bits = 0, 652 .ddr_addr_start = 9, 653 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 654 } }, 655 .zud_chan = { { 656 .chan_flags = UMC_CHAN_F_ECC_EN, 657 .chan_fabid = 1, 658 .chan_instid = 1, 659 .chan_logid = 0, 660 .chan_nrules = 1, 661 .chan_type = UMC_DIMM_T_DDR4, 662 .chan_rules = { { 663 .ddr_flags = DF_DRAM_F_VALID, 664 .ddr_base = 0, 665 .ddr_limit = 128ULL * 1024ULL * 1024ULL * 666 1024ULL, 667 .ddr_dest_fabid = 1, 668 .ddr_sock_ileave_bits = 0, 669 .ddr_die_ileave_bits = 0, 670 .ddr_addr_start = 9, 671 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 672 } }, 673 .chan_dimms = { { 674 .ud_flags = UMC_DIMM_F_VALID, 675 .ud_width = UMC_DIMM_W_X4, 676 .ud_kind = UMC_DIMM_K_RDIMM, 677 .ud_dimmno = 0, 678 .ud_cs = { { 679 .ucs_base = { 680 .udb_base = 0, 681 .udb_valid = B_TRUE 682 }, 683 .ucs_base_mask = 0x1ffff9ffff, 684 .ucs_nbanks = 0x4, 685 .ucs_ncol = 0xa, 686 .ucs_nrow_lo = 0x12, 687 .ucs_nbank_groups = 0x2, 688 .ucs_row_hi_bit = 0x18, 689 .ucs_row_low_bit = 0x13, 690 .ucs_bank_bits = { 0x9, 0xa, 0x6, 691 0xb }, 692 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x7, 693 0x8, 0xc, 0xd, 0xe, 0xf, 0x10 } 694 }, { 695 .ucs_base = { 696 .udb_base = 0x20000, 697 .udb_valid = B_TRUE 698 }, 699 .ucs_base_mask = 0x1ffff9ffff, 700 .ucs_nbanks = 0x4, 701 .ucs_ncol = 0xa, 702 .ucs_nrow_lo = 0x12, 703 .ucs_nbank_groups = 0x2, 704 .ucs_row_hi_bit = 0x18, 705 .ucs_row_low_bit = 0x13, 706 .ucs_bank_bits = { 0x9, 0xa, 0x6, 707 0xb }, 708 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x7, 709 0x8, 0xc, 0xd, 0xe, 0xf, 0x10 } 710 } } 711 }, { 712 .ud_flags = UMC_DIMM_F_VALID, 713 .ud_width = UMC_DIMM_W_X4, 714 .ud_kind = UMC_DIMM_K_RDIMM, 715 .ud_dimmno = 1, 716 .ud_cs = { { 717 .ucs_base = { 718 .udb_base = 0x40000, 719 .udb_valid = B_TRUE 720 }, 721 .ucs_base_mask = 0x1ffff9ffff, 722 .ucs_nbanks = 0x4, 723 .ucs_ncol = 0xa, 724 .ucs_nrow_lo = 0x12, 725 .ucs_nbank_groups = 0x2, 726 .ucs_row_hi_bit = 0x18, 727 .ucs_row_low_bit = 0x13, 728 .ucs_bank_bits = { 0x9, 0xa, 0x6, 729 0xb }, 730 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x7, 731 0x8, 0xc, 0xd, 0xe, 0xf, 0x10 } 732 }, { 733 .ucs_base = { 734 .udb_base = 0x60000, 735 .udb_valid = B_TRUE 736 }, 737 .ucs_base_mask = 0x1ffff9ffff, 738 .ucs_nbanks = 0x4, 739 .ucs_ncol = 0xa, 740 .ucs_nrow_lo = 0x12, 741 .ucs_nbank_groups = 0x2, 742 .ucs_row_hi_bit = 0x18, 743 .ucs_row_low_bit = 0x13, 744 .ucs_bank_bits = { 0x9, 0xa, 0x6, 745 0xb }, 746 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x7, 747 0x8, 0xc, 0xd, 0xe, 0xf, 0x10 } 748 } } 749 } } 750 } } 751 } } 752 }; 753 754 /* 755 * This is a basic DDR5 channel. We only use a single DIMM and set up a 756 * sub-channel on it. 757 */ 758 static const zen_umc_t zen_umc_chan_subchan_no_hash = { 759 .umc_tom = 4ULL * 1024ULL * 1024ULL * 1024ULL, 760 .umc_tom2 = 16ULL * 1024ULL * 1024ULL * 1024ULL, 761 .umc_df_rev = DF_REV_3, 762 .umc_decomp = { 763 .dfd_sock_mask = 0x01, 764 .dfd_die_mask = 0x00, 765 .dfd_node_mask = 0x20, 766 .dfd_comp_mask = 0x1f, 767 .dfd_sock_shift = 0, 768 .dfd_die_shift = 0, 769 .dfd_node_shift = 5, 770 .dfd_comp_shift = 0 771 }, 772 .umc_ndfs = 1, 773 .umc_dfs = { { 774 .zud_dfno = 0, 775 .zud_ccm_inst = 0, 776 .zud_dram_nrules = 1, 777 .zud_nchan = 1, 778 .zud_cs_nremap = 0, 779 .zud_hole_base = 0, 780 .zud_rules = { { 781 .ddr_flags = DF_DRAM_F_VALID, 782 .ddr_base = 0, 783 .ddr_limit = 16ULL * 1024ULL * 1024ULL * 1024ULL, 784 .ddr_dest_fabid = 1, 785 .ddr_sock_ileave_bits = 0, 786 .ddr_die_ileave_bits = 0, 787 .ddr_addr_start = 9, 788 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 789 } }, 790 .zud_chan = { { 791 .chan_flags = UMC_CHAN_F_ECC_EN, 792 .chan_fabid = 1, 793 .chan_instid = 1, 794 .chan_logid = 0, 795 .chan_nrules = 1, 796 .chan_type = UMC_DIMM_T_DDR5, 797 .chan_rules = { { 798 .ddr_flags = DF_DRAM_F_VALID, 799 .ddr_base = 0, 800 .ddr_limit = 16ULL * 1024ULL * 1024ULL * 801 1024ULL, 802 .ddr_dest_fabid = 1, 803 .ddr_sock_ileave_bits = 0, 804 .ddr_die_ileave_bits = 0, 805 .ddr_addr_start = 9, 806 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 807 } }, 808 .chan_dimms = { { 809 .ud_flags = UMC_DIMM_F_VALID, 810 .ud_width = UMC_DIMM_W_X4, 811 .ud_kind = UMC_DIMM_K_RDIMM, 812 .ud_dimmno = 0, 813 .ud_cs = { { 814 .ucs_base = { 815 .udb_base = 0, 816 .udb_valid = B_TRUE 817 }, 818 .ucs_base_mask = 0x3ffffffff, 819 .ucs_nbanks = 0x5, 820 .ucs_ncol = 0xa, 821 .ucs_nrow_lo = 0x10, 822 .ucs_nbank_groups = 0x3, 823 .ucs_row_low_bit = 0x12, 824 .ucs_bank_bits = { 0xf, 0x10, 0x11, 825 0xd, 0xe }, 826 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 827 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 828 .ucs_subchan = 0x6 829 } } 830 } } 831 } } 832 } } 833 }; 834 835 const umc_decode_test_t zen_umc_test_chans[] = { { 836 .udt_desc = "2 DPC 2R no ilv/hash (0)", 837 .udt_umc = &zen_umc_chan_no_hash, 838 .udt_pa = 0x0, 839 .udt_pass = B_TRUE, 840 .udt_norm_addr = 0x0, 841 .udt_sock = 0, 842 .udt_die = 0, 843 .udt_comp = 1, 844 .udt_dimm_no = 0, 845 .udt_dimm_col = 0, 846 .udt_dimm_row = 0, 847 .udt_dimm_bank = 0, 848 .udt_dimm_bank_group = 0, 849 .udt_dimm_subchan = UINT8_MAX, 850 .udt_dimm_rm = 0, 851 .udt_dimm_cs = 0 852 }, { 853 .udt_desc = "2 DPC 2R no ilv/hash (1)", 854 .udt_umc = &zen_umc_chan_no_hash, 855 .udt_pa = 0x800000000, 856 .udt_pass = B_TRUE, 857 .udt_norm_addr = 0x800000000, 858 .udt_sock = 0, 859 .udt_die = 0, 860 .udt_comp = 1, 861 .udt_dimm_no = 0, 862 .udt_dimm_col = 0, 863 .udt_dimm_row = 0, 864 .udt_dimm_bank = 0, 865 .udt_dimm_bank_group = 0, 866 .udt_dimm_subchan = UINT8_MAX, 867 .udt_dimm_rm = 0, 868 .udt_dimm_cs = 1 869 }, { 870 .udt_desc = "2 DPC 2R no ilv/hash (2)", 871 .udt_umc = &zen_umc_chan_no_hash, 872 .udt_pa = 0x1000000000, 873 .udt_pass = B_TRUE, 874 .udt_norm_addr = 0x1000000000, 875 .udt_sock = 0, 876 .udt_die = 0, 877 .udt_comp = 1, 878 .udt_dimm_no = 1, 879 .udt_dimm_col = 0, 880 .udt_dimm_row = 0, 881 .udt_dimm_bank = 0, 882 .udt_dimm_bank_group = 0, 883 .udt_dimm_subchan = UINT8_MAX, 884 .udt_dimm_rm = 0, 885 .udt_dimm_cs = 0 886 }, { 887 .udt_desc = "2 DPC 2R no ilv/hash (3)", 888 .udt_umc = &zen_umc_chan_no_hash, 889 .udt_pa = 0x1800000000, 890 .udt_pass = B_TRUE, 891 .udt_norm_addr = 0x1800000000, 892 .udt_sock = 0, 893 .udt_die = 0, 894 .udt_comp = 1, 895 .udt_dimm_no = 1, 896 .udt_dimm_col = 0, 897 .udt_dimm_row = 0, 898 .udt_dimm_bank = 0, 899 .udt_dimm_bank_group = 0, 900 .udt_dimm_subchan = UINT8_MAX, 901 .udt_dimm_rm = 0, 902 .udt_dimm_cs = 1 903 }, { 904 .udt_desc = "2 DPC 2R no ilv/hash (4)", 905 .udt_umc = &zen_umc_chan_no_hash, 906 .udt_pa = 0x0ff1ff120, 907 .udt_pass = B_TRUE, 908 .udt_norm_addr = 0x0ff1ff120, 909 .udt_sock = 0, 910 .udt_die = 0, 911 .udt_comp = 1, 912 .udt_dimm_no = 0, 913 .udt_dimm_col = 0x224, 914 .udt_dimm_row = 0x7f8f, 915 .udt_dimm_bank = 3, 916 .udt_dimm_bank_group = 3, 917 .udt_dimm_subchan = UINT8_MAX, 918 .udt_dimm_rm = 0, 919 .udt_dimm_cs = 0 920 }, { 921 .udt_desc = "2 DPC 2R no ilv/hash (5)", 922 .udt_umc = &zen_umc_chan_no_hash, 923 .udt_pa = 0x8ff4ff500, 924 .udt_pass = B_TRUE, 925 .udt_norm_addr = 0x8ff4ff500, 926 .udt_sock = 0, 927 .udt_die = 0, 928 .udt_comp = 1, 929 .udt_dimm_no = 0, 930 .udt_dimm_col = 0x2a0, 931 .udt_dimm_row = 0x7fa7, 932 .udt_dimm_bank = 3, 933 .udt_dimm_bank_group = 3, 934 .udt_dimm_subchan = UINT8_MAX, 935 .udt_dimm_rm = 0, 936 .udt_dimm_cs = 1 937 }, { 938 .udt_desc = "2 DPC 2R no ilv/hash (6)", 939 .udt_umc = &zen_umc_chan_no_hash, 940 .udt_pa = 0x10ff6ff700, 941 .udt_pass = B_TRUE, 942 .udt_norm_addr = 0x10ff6ff700, 943 .udt_sock = 0, 944 .udt_die = 0, 945 .udt_comp = 1, 946 .udt_dimm_no = 1, 947 .udt_dimm_col = 0x2e0, 948 .udt_dimm_row = 0x7fb7, 949 .udt_dimm_bank = 3, 950 .udt_dimm_bank_group = 3, 951 .udt_dimm_subchan = UINT8_MAX, 952 .udt_dimm_rm = 0, 953 .udt_dimm_cs = 0 954 }, { 955 .udt_desc = "2 DPC 2R no ilv/hash (7)", 956 .udt_umc = &zen_umc_chan_no_hash, 957 .udt_pa = 0x18ff8ff102, 958 .udt_pass = B_TRUE, 959 .udt_norm_addr = 0x18ff8ff102, 960 .udt_sock = 0, 961 .udt_die = 0, 962 .udt_comp = 1, 963 .udt_dimm_no = 1, 964 .udt_dimm_col = 0x220, 965 .udt_dimm_row = 0x7fc7, 966 .udt_dimm_bank = 3, 967 .udt_dimm_bank_group = 3, 968 .udt_dimm_subchan = UINT8_MAX, 969 .udt_dimm_rm = 0, 970 .udt_dimm_cs = 1 971 }, { 972 .udt_desc = "2 DPC 2R no hash, rank ilv (0)", 973 .udt_umc = &zen_umc_chan_ilv, 974 .udt_pa = 0x0, 975 .udt_pass = B_TRUE, 976 .udt_norm_addr = 0x0, 977 .udt_sock = 0, 978 .udt_die = 0, 979 .udt_comp = 1, 980 .udt_dimm_no = 0, 981 .udt_dimm_col = 0, 982 .udt_dimm_row = 0, 983 .udt_dimm_bank = 0, 984 .udt_dimm_bank_group = 0, 985 .udt_dimm_subchan = UINT8_MAX, 986 .udt_dimm_rm = 0, 987 .udt_dimm_cs = 0 988 }, { 989 .udt_desc = "2 DPC 2R no hash, rank ilv (1)", 990 .udt_umc = &zen_umc_chan_ilv, 991 .udt_pa = 0x20000, 992 .udt_pass = B_TRUE, 993 .udt_norm_addr = 0x20000, 994 .udt_sock = 0, 995 .udt_die = 0, 996 .udt_comp = 1, 997 .udt_dimm_no = 0, 998 .udt_dimm_col = 0, 999 .udt_dimm_row = 0, 1000 .udt_dimm_bank = 0, 1001 .udt_dimm_bank_group = 0, 1002 .udt_dimm_subchan = UINT8_MAX, 1003 .udt_dimm_rm = 0, 1004 .udt_dimm_cs = 1 1005 }, { 1006 .udt_desc = "2 DPC 2R no hash, rank ilv (2)", 1007 .udt_umc = &zen_umc_chan_ilv, 1008 .udt_pa = 0x40000, 1009 .udt_pass = B_TRUE, 1010 .udt_norm_addr = 0x40000, 1011 .udt_sock = 0, 1012 .udt_die = 0, 1013 .udt_comp = 1, 1014 .udt_dimm_no = 1, 1015 .udt_dimm_col = 0, 1016 .udt_dimm_row = 0, 1017 .udt_dimm_bank = 0, 1018 .udt_dimm_bank_group = 0, 1019 .udt_dimm_subchan = UINT8_MAX, 1020 .udt_dimm_rm = 0, 1021 .udt_dimm_cs = 0 1022 }, { 1023 .udt_desc = "2 DPC 2R no hash, rank ilv (3)", 1024 .udt_umc = &zen_umc_chan_ilv, 1025 .udt_pa = 0x60000, 1026 .udt_pass = B_TRUE, 1027 .udt_norm_addr = 0x60000, 1028 .udt_sock = 0, 1029 .udt_die = 0, 1030 .udt_comp = 1, 1031 .udt_dimm_no = 1, 1032 .udt_dimm_col = 0, 1033 .udt_dimm_row = 0, 1034 .udt_dimm_bank = 0, 1035 .udt_dimm_bank_group = 0, 1036 .udt_dimm_subchan = UINT8_MAX, 1037 .udt_dimm_rm = 0, 1038 .udt_dimm_cs = 1 1039 }, { 1040 .udt_desc = "2 DPC 2R no hash, rank ilv (4)", 1041 .udt_umc = &zen_umc_chan_ilv, 1042 .udt_pa = 0xe1be12e00, 1043 .udt_pass = B_TRUE, 1044 .udt_norm_addr = 0xe1be12e00, 1045 .udt_sock = 0, 1046 .udt_die = 0, 1047 .udt_comp = 1, 1048 .udt_dimm_no = 0, 1049 .udt_dimm_col = 0x1c0, 1050 .udt_dimm_row = 0x1c37c, 1051 .udt_dimm_bank = 2, 1052 .udt_dimm_bank_group = 1, 1053 .udt_dimm_subchan = UINT8_MAX, 1054 .udt_dimm_rm = 0, 1055 .udt_dimm_cs = 0 1056 }, { 1057 .udt_desc = "2 DPC 2R no hash, rank ilv (5)", 1058 .udt_umc = &zen_umc_chan_ilv, 1059 .udt_pa = 0x1fffffffff, 1060 .udt_pass = B_TRUE, 1061 .udt_norm_addr = 0x1fffffffff, 1062 .udt_sock = 0, 1063 .udt_die = 0, 1064 .udt_comp = 1, 1065 .udt_dimm_no = 1, 1066 .udt_dimm_col = 0x3ff, 1067 .udt_dimm_row = 0x3ffff, 1068 .udt_dimm_bank = 3, 1069 .udt_dimm_bank_group = 3, 1070 .udt_dimm_subchan = UINT8_MAX, 1071 .udt_dimm_rm = 0, 1072 .udt_dimm_cs = 1 1073 }, 1074 /* 1075 * Test the CS hashing by first going back and using bits that aren't part of 1076 * the CS hash modification, e.g. the same 4 interleaving case that we hit 1077 * earlier. Next, we go through and tweak things that would normally go to a 1078 * given CS originally by tweaking the bits that would be used in a hash and 1079 * prove that they go elsewhere. 1080 */ 1081 { 1082 .udt_desc = "2 DPC 2R cs hash, rank ilv (0)", 1083 .udt_umc = &zen_umc_chan_ilv_cs_hash, 1084 .udt_pa = 0x0, 1085 .udt_pass = B_TRUE, 1086 .udt_norm_addr = 0x0, 1087 .udt_sock = 0, 1088 .udt_die = 0, 1089 .udt_comp = 1, 1090 .udt_dimm_no = 0, 1091 .udt_dimm_col = 0, 1092 .udt_dimm_row = 0, 1093 .udt_dimm_bank = 0, 1094 .udt_dimm_bank_group = 0, 1095 .udt_dimm_subchan = UINT8_MAX, 1096 .udt_dimm_rm = 0, 1097 .udt_dimm_cs = 0 1098 }, { 1099 .udt_desc = "2 DPC 2R cs hash, rank ilv (1)", 1100 .udt_umc = &zen_umc_chan_ilv_cs_hash, 1101 .udt_pa = 0x20000, 1102 .udt_pass = B_TRUE, 1103 .udt_norm_addr = 0x20000, 1104 .udt_sock = 0, 1105 .udt_die = 0, 1106 .udt_comp = 1, 1107 .udt_dimm_no = 0, 1108 .udt_dimm_col = 0, 1109 .udt_dimm_row = 0, 1110 .udt_dimm_bank = 0, 1111 .udt_dimm_bank_group = 0, 1112 .udt_dimm_subchan = UINT8_MAX, 1113 .udt_dimm_rm = 0, 1114 .udt_dimm_cs = 1 1115 }, { 1116 .udt_desc = "2 DPC 2R cs hash, rank ilv (2)", 1117 .udt_umc = &zen_umc_chan_ilv_cs_hash, 1118 .udt_pa = 0x40000, 1119 .udt_pass = B_TRUE, 1120 .udt_norm_addr = 0x40000, 1121 .udt_sock = 0, 1122 .udt_die = 0, 1123 .udt_comp = 1, 1124 .udt_dimm_no = 1, 1125 .udt_dimm_col = 0, 1126 .udt_dimm_row = 0, 1127 .udt_dimm_bank = 0, 1128 .udt_dimm_bank_group = 0, 1129 .udt_dimm_subchan = UINT8_MAX, 1130 .udt_dimm_rm = 0, 1131 .udt_dimm_cs = 0 1132 }, { 1133 .udt_desc = "2 DPC 2R cs hash, rank ilv (3)", 1134 .udt_umc = &zen_umc_chan_ilv_cs_hash, 1135 .udt_pa = 0x60000, 1136 .udt_pass = B_TRUE, 1137 .udt_norm_addr = 0x60000, 1138 .udt_sock = 0, 1139 .udt_die = 0, 1140 .udt_comp = 1, 1141 .udt_dimm_no = 1, 1142 .udt_dimm_col = 0, 1143 .udt_dimm_row = 0, 1144 .udt_dimm_bank = 0, 1145 .udt_dimm_bank_group = 0, 1146 .udt_dimm_subchan = UINT8_MAX, 1147 .udt_dimm_rm = 0, 1148 .udt_dimm_cs = 1 1149 }, { 1150 .udt_desc = "2 DPC 2R cs hash, rank ilv (4)", 1151 .udt_umc = &zen_umc_chan_ilv_cs_hash, 1152 .udt_pa = 0x80000, 1153 .udt_pass = B_TRUE, 1154 .udt_norm_addr = 0x80000, 1155 .udt_sock = 0, 1156 .udt_die = 0, 1157 .udt_comp = 1, 1158 .udt_dimm_no = 0, 1159 .udt_dimm_col = 0, 1160 .udt_dimm_row = 1, 1161 .udt_dimm_bank = 0, 1162 .udt_dimm_bank_group = 0, 1163 .udt_dimm_subchan = UINT8_MAX, 1164 .udt_dimm_rm = 0, 1165 .udt_dimm_cs = 1 1166 }, { 1167 .udt_desc = "2 DPC 2R cs hash, rank ilv (5)", 1168 .udt_umc = &zen_umc_chan_ilv_cs_hash, 1169 .udt_pa = 0x180000, 1170 .udt_pass = B_TRUE, 1171 .udt_norm_addr = 0x180000, 1172 .udt_sock = 0, 1173 .udt_die = 0, 1174 .udt_comp = 1, 1175 .udt_dimm_no = 1, 1176 .udt_dimm_col = 0, 1177 .udt_dimm_row = 3, 1178 .udt_dimm_bank = 0, 1179 .udt_dimm_bank_group = 0, 1180 .udt_dimm_subchan = UINT8_MAX, 1181 .udt_dimm_rm = 0, 1182 .udt_dimm_cs = 1 1183 }, { 1184 .udt_desc = "2 DPC 2R cs hash, rank ilv (6)", 1185 .udt_umc = &zen_umc_chan_ilv_cs_hash, 1186 .udt_pa = 0x100000, 1187 .udt_pass = B_TRUE, 1188 .udt_norm_addr = 0x100000, 1189 .udt_sock = 0, 1190 .udt_die = 0, 1191 .udt_comp = 1, 1192 .udt_dimm_no = 1, 1193 .udt_dimm_col = 0, 1194 .udt_dimm_row = 2, 1195 .udt_dimm_bank = 0, 1196 .udt_dimm_bank_group = 0, 1197 .udt_dimm_subchan = UINT8_MAX, 1198 .udt_dimm_rm = 0, 1199 .udt_dimm_cs = 0 1200 }, { 1201 .udt_desc = "2 DPC 2R cs hash, rank ilv (7)", 1202 .udt_umc = &zen_umc_chan_ilv_cs_hash, 1203 .udt_pa = 0x18180000, 1204 .udt_pass = B_TRUE, 1205 .udt_norm_addr = 0x18180000, 1206 .udt_sock = 0, 1207 .udt_die = 0, 1208 .udt_comp = 1, 1209 .udt_dimm_no = 0, 1210 .udt_dimm_col = 0, 1211 .udt_dimm_row = 0x303, 1212 .udt_dimm_bank = 0, 1213 .udt_dimm_bank_group = 0, 1214 .udt_dimm_subchan = UINT8_MAX, 1215 .udt_dimm_rm = 0, 1216 .udt_dimm_cs = 0 1217 }, { 1218 .udt_desc = "2 DPC 2R cs hash, rank ilv (8)", 1219 .udt_umc = &zen_umc_chan_ilv_cs_hash, 1220 .udt_pa = 0x181a0000, 1221 .udt_pass = B_TRUE, 1222 .udt_norm_addr = 0x181a0000, 1223 .udt_sock = 0, 1224 .udt_die = 0, 1225 .udt_comp = 1, 1226 .udt_dimm_no = 0, 1227 .udt_dimm_col = 0, 1228 .udt_dimm_row = 0x303, 1229 .udt_dimm_bank = 0, 1230 .udt_dimm_bank_group = 0, 1231 .udt_dimm_subchan = UINT8_MAX, 1232 .udt_dimm_rm = 0, 1233 .udt_dimm_cs = 1 1234 }, { 1235 .udt_desc = "2 DPC 2R cs hash, rank ilv (9)", 1236 .udt_umc = &zen_umc_chan_ilv_cs_hash, 1237 .udt_pa = 0x181c0000, 1238 .udt_pass = B_TRUE, 1239 .udt_norm_addr = 0x181c0000, 1240 .udt_sock = 0, 1241 .udt_die = 0, 1242 .udt_comp = 1, 1243 .udt_dimm_no = 1, 1244 .udt_dimm_col = 0, 1245 .udt_dimm_row = 0x303, 1246 .udt_dimm_bank = 0, 1247 .udt_dimm_bank_group = 0, 1248 .udt_dimm_subchan = UINT8_MAX, 1249 .udt_dimm_rm = 0, 1250 .udt_dimm_cs = 0 1251 }, { 1252 .udt_desc = "2 DPC 2R cs hash, rank ilv (10)", 1253 .udt_umc = &zen_umc_chan_ilv_cs_hash, 1254 .udt_pa = 0x181e0000, 1255 .udt_pass = B_TRUE, 1256 .udt_norm_addr = 0x181e0000, 1257 .udt_sock = 0, 1258 .udt_die = 0, 1259 .udt_comp = 1, 1260 .udt_dimm_no = 1, 1261 .udt_dimm_col = 0, 1262 .udt_dimm_row = 0x303, 1263 .udt_dimm_bank = 0, 1264 .udt_dimm_bank_group = 0, 1265 .udt_dimm_subchan = UINT8_MAX, 1266 .udt_dimm_rm = 0, 1267 .udt_dimm_cs = 1 1268 }, 1269 /* 1270 * For the bank hash we first prove that we can target a given row/column in 1271 * each bank and bank group without hashing (this leads to a total of 16 1272 * combinations). We then later go back and start tweaking the row/column to 1273 * change which bank and group we end up in. 1274 */ 1275 { 1276 .udt_desc = "2 DPC 2R bank hash, rank ilv (0)", 1277 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1278 .udt_pa = 0x0, 1279 .udt_pass = B_TRUE, 1280 .udt_norm_addr = 0x0, 1281 .udt_sock = 0, 1282 .udt_die = 0, 1283 .udt_comp = 1, 1284 .udt_dimm_no = 0, 1285 .udt_dimm_col = 0, 1286 .udt_dimm_row = 0, 1287 .udt_dimm_bank = 0, 1288 .udt_dimm_bank_group = 0, 1289 .udt_dimm_subchan = UINT8_MAX, 1290 .udt_dimm_rm = 0, 1291 .udt_dimm_cs = 0 1292 }, { 1293 .udt_desc = "2 DPC 2R bank hash, rank ilv (1)", 1294 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1295 .udt_pa = 0x8000, 1296 .udt_pass = B_TRUE, 1297 .udt_norm_addr = 0x8000, 1298 .udt_sock = 0, 1299 .udt_die = 0, 1300 .udt_comp = 1, 1301 .udt_dimm_no = 0, 1302 .udt_dimm_col = 0, 1303 .udt_dimm_row = 0, 1304 .udt_dimm_bank = 1, 1305 .udt_dimm_bank_group = 0, 1306 .udt_dimm_subchan = UINT8_MAX, 1307 .udt_dimm_rm = 0, 1308 .udt_dimm_cs = 0 1309 }, { 1310 .udt_desc = "2 DPC 2R bank hash, rank ilv (2)", 1311 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1312 .udt_pa = 0x10000, 1313 .udt_pass = B_TRUE, 1314 .udt_norm_addr = 0x10000, 1315 .udt_sock = 0, 1316 .udt_die = 0, 1317 .udt_comp = 1, 1318 .udt_dimm_no = 0, 1319 .udt_dimm_col = 0, 1320 .udt_dimm_row = 0, 1321 .udt_dimm_bank = 2, 1322 .udt_dimm_bank_group = 0, 1323 .udt_dimm_subchan = UINT8_MAX, 1324 .udt_dimm_rm = 0, 1325 .udt_dimm_cs = 0 1326 }, { 1327 .udt_desc = "2 DPC 2R bank hash, rank ilv (3)", 1328 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1329 .udt_pa = 0x18000, 1330 .udt_pass = B_TRUE, 1331 .udt_norm_addr = 0x18000, 1332 .udt_sock = 0, 1333 .udt_die = 0, 1334 .udt_comp = 1, 1335 .udt_dimm_no = 0, 1336 .udt_dimm_col = 0, 1337 .udt_dimm_row = 0, 1338 .udt_dimm_bank = 3, 1339 .udt_dimm_bank_group = 0, 1340 .udt_dimm_subchan = UINT8_MAX, 1341 .udt_dimm_rm = 0, 1342 .udt_dimm_cs = 0 1343 }, { 1344 .udt_desc = "2 DPC 2R bank hash, rank ilv (4)", 1345 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1346 .udt_pa = 0x2000, 1347 .udt_pass = B_TRUE, 1348 .udt_norm_addr = 0x2000, 1349 .udt_sock = 0, 1350 .udt_die = 0, 1351 .udt_comp = 1, 1352 .udt_dimm_no = 0, 1353 .udt_dimm_col = 0, 1354 .udt_dimm_row = 0, 1355 .udt_dimm_bank = 0, 1356 .udt_dimm_bank_group = 1, 1357 .udt_dimm_subchan = UINT8_MAX, 1358 .udt_dimm_rm = 0, 1359 .udt_dimm_cs = 0 1360 }, { 1361 .udt_desc = "2 DPC 2R bank hash, rank ilv (5)", 1362 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1363 .udt_pa = 0xa000, 1364 .udt_pass = B_TRUE, 1365 .udt_norm_addr = 0xa000, 1366 .udt_sock = 0, 1367 .udt_die = 0, 1368 .udt_comp = 1, 1369 .udt_dimm_no = 0, 1370 .udt_dimm_col = 0, 1371 .udt_dimm_row = 0, 1372 .udt_dimm_bank = 1, 1373 .udt_dimm_bank_group = 1, 1374 .udt_dimm_subchan = UINT8_MAX, 1375 .udt_dimm_rm = 0, 1376 .udt_dimm_cs = 0 1377 }, { 1378 .udt_desc = "2 DPC 2R bank hash, rank ilv (6)", 1379 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1380 .udt_pa = 0x12000, 1381 .udt_pass = B_TRUE, 1382 .udt_norm_addr = 0x12000, 1383 .udt_sock = 0, 1384 .udt_die = 0, 1385 .udt_comp = 1, 1386 .udt_dimm_no = 0, 1387 .udt_dimm_col = 0, 1388 .udt_dimm_row = 0, 1389 .udt_dimm_bank = 2, 1390 .udt_dimm_bank_group = 1, 1391 .udt_dimm_subchan = UINT8_MAX, 1392 .udt_dimm_rm = 0, 1393 .udt_dimm_cs = 0 1394 }, { 1395 .udt_desc = "2 DPC 2R bank hash, rank ilv (7)", 1396 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1397 .udt_pa = 0x1a000, 1398 .udt_pass = B_TRUE, 1399 .udt_norm_addr = 0x1a000, 1400 .udt_sock = 0, 1401 .udt_die = 0, 1402 .udt_comp = 1, 1403 .udt_dimm_no = 0, 1404 .udt_dimm_col = 0, 1405 .udt_dimm_row = 0, 1406 .udt_dimm_bank = 3, 1407 .udt_dimm_bank_group = 1, 1408 .udt_dimm_subchan = UINT8_MAX, 1409 .udt_dimm_rm = 0, 1410 .udt_dimm_cs = 0 1411 }, { 1412 .udt_desc = "2 DPC 2R bank hash, rank ilv (8)", 1413 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1414 .udt_pa = 0x4000, 1415 .udt_pass = B_TRUE, 1416 .udt_norm_addr = 0x4000, 1417 .udt_sock = 0, 1418 .udt_die = 0, 1419 .udt_comp = 1, 1420 .udt_dimm_no = 0, 1421 .udt_dimm_col = 0, 1422 .udt_dimm_row = 0, 1423 .udt_dimm_bank = 0, 1424 .udt_dimm_bank_group = 2, 1425 .udt_dimm_subchan = UINT8_MAX, 1426 .udt_dimm_rm = 0, 1427 .udt_dimm_cs = 0 1428 }, { 1429 .udt_desc = "2 DPC 2R bank hash, rank ilv (9)", 1430 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1431 .udt_pa = 0xc000, 1432 .udt_pass = B_TRUE, 1433 .udt_norm_addr = 0xc000, 1434 .udt_sock = 0, 1435 .udt_die = 0, 1436 .udt_comp = 1, 1437 .udt_dimm_no = 0, 1438 .udt_dimm_col = 0, 1439 .udt_dimm_row = 0, 1440 .udt_dimm_bank = 1, 1441 .udt_dimm_bank_group = 2, 1442 .udt_dimm_subchan = UINT8_MAX, 1443 .udt_dimm_rm = 0, 1444 .udt_dimm_cs = 0 1445 }, { 1446 .udt_desc = "2 DPC 2R bank hash, rank ilv (10)", 1447 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1448 .udt_pa = 0x14000, 1449 .udt_pass = B_TRUE, 1450 .udt_norm_addr = 0x14000, 1451 .udt_sock = 0, 1452 .udt_die = 0, 1453 .udt_comp = 1, 1454 .udt_dimm_no = 0, 1455 .udt_dimm_col = 0, 1456 .udt_dimm_row = 0, 1457 .udt_dimm_bank = 2, 1458 .udt_dimm_bank_group = 2, 1459 .udt_dimm_subchan = UINT8_MAX, 1460 .udt_dimm_rm = 0, 1461 .udt_dimm_cs = 0 1462 }, { 1463 .udt_desc = "2 DPC 2R bank hash, rank ilv (11)", 1464 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1465 .udt_pa = 0x1c000, 1466 .udt_pass = B_TRUE, 1467 .udt_norm_addr = 0x1c000, 1468 .udt_sock = 0, 1469 .udt_die = 0, 1470 .udt_comp = 1, 1471 .udt_dimm_no = 0, 1472 .udt_dimm_col = 0, 1473 .udt_dimm_row = 0, 1474 .udt_dimm_bank = 3, 1475 .udt_dimm_bank_group = 2, 1476 .udt_dimm_subchan = UINT8_MAX, 1477 .udt_dimm_rm = 0, 1478 .udt_dimm_cs = 0 1479 }, { 1480 .udt_desc = "2 DPC 2R bank hash, rank ilv (12)", 1481 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1482 .udt_pa = 0x6000, 1483 .udt_pass = B_TRUE, 1484 .udt_norm_addr = 0x6000, 1485 .udt_sock = 0, 1486 .udt_die = 0, 1487 .udt_comp = 1, 1488 .udt_dimm_no = 0, 1489 .udt_dimm_col = 0, 1490 .udt_dimm_row = 0, 1491 .udt_dimm_bank = 0, 1492 .udt_dimm_bank_group = 3, 1493 .udt_dimm_subchan = UINT8_MAX, 1494 .udt_dimm_rm = 0, 1495 .udt_dimm_cs = 0 1496 }, { 1497 .udt_desc = "2 DPC 2R bank hash, rank ilv (13)", 1498 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1499 .udt_pa = 0xe000, 1500 .udt_pass = B_TRUE, 1501 .udt_norm_addr = 0xe000, 1502 .udt_sock = 0, 1503 .udt_die = 0, 1504 .udt_comp = 1, 1505 .udt_dimm_no = 0, 1506 .udt_dimm_col = 0, 1507 .udt_dimm_row = 0, 1508 .udt_dimm_bank = 1, 1509 .udt_dimm_bank_group = 3, 1510 .udt_dimm_subchan = UINT8_MAX, 1511 .udt_dimm_rm = 0, 1512 .udt_dimm_cs = 0 1513 }, { 1514 .udt_desc = "2 DPC 2R bank hash, rank ilv (14)", 1515 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1516 .udt_pa = 0x16000, 1517 .udt_pass = B_TRUE, 1518 .udt_norm_addr = 0x16000, 1519 .udt_sock = 0, 1520 .udt_die = 0, 1521 .udt_comp = 1, 1522 .udt_dimm_no = 0, 1523 .udt_dimm_col = 0, 1524 .udt_dimm_row = 0, 1525 .udt_dimm_bank = 2, 1526 .udt_dimm_bank_group = 3, 1527 .udt_dimm_subchan = UINT8_MAX, 1528 .udt_dimm_rm = 0, 1529 .udt_dimm_cs = 0 1530 }, { 1531 .udt_desc = "2 DPC 2R bank hash, rank ilv (15)", 1532 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1533 .udt_pa = 0x1e000, 1534 .udt_pass = B_TRUE, 1535 .udt_norm_addr = 0x1e000, 1536 .udt_sock = 0, 1537 .udt_die = 0, 1538 .udt_comp = 1, 1539 .udt_dimm_no = 0, 1540 .udt_dimm_col = 0, 1541 .udt_dimm_row = 0, 1542 .udt_dimm_bank = 3, 1543 .udt_dimm_bank_group = 3, 1544 .udt_dimm_subchan = UINT8_MAX, 1545 .udt_dimm_rm = 0, 1546 .udt_dimm_cs = 0 1547 }, { 1548 .udt_desc = "2 DPC 2R bank hash, rank ilv (16)", 1549 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1550 .udt_pa = 0x79c000, 1551 .udt_pass = B_TRUE, 1552 .udt_norm_addr = 0x79c000, 1553 .udt_sock = 0, 1554 .udt_die = 0, 1555 .udt_comp = 1, 1556 .udt_dimm_no = 0, 1557 .udt_dimm_col = 0, 1558 .udt_dimm_row = 0xf, 1559 .udt_dimm_bank = 0, 1560 .udt_dimm_bank_group = 1, 1561 .udt_dimm_subchan = UINT8_MAX, 1562 .udt_dimm_rm = 0, 1563 .udt_dimm_cs = 0 1564 }, { 1565 .udt_desc = "2 DPC 2R bank hash, rank ilv (17)", 1566 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1567 .udt_pa = 0x7f9c000, 1568 .udt_pass = B_TRUE, 1569 .udt_norm_addr = 0x7f9c000, 1570 .udt_sock = 0, 1571 .udt_die = 0, 1572 .udt_comp = 1, 1573 .udt_dimm_no = 0, 1574 .udt_dimm_col = 0, 1575 .udt_dimm_row = 0xff, 1576 .udt_dimm_bank = 3, 1577 .udt_dimm_bank_group = 2, 1578 .udt_dimm_subchan = UINT8_MAX, 1579 .udt_dimm_rm = 0, 1580 .udt_dimm_cs = 0 1581 }, { 1582 .udt_desc = "2 DPC 2R bank hash, rank ilv (18)", 1583 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1584 .udt_pa = 0x7ff9c000, 1585 .udt_pass = B_TRUE, 1586 .udt_norm_addr = 0x7ff9c000, 1587 .udt_sock = 0, 1588 .udt_die = 0, 1589 .udt_comp = 1, 1590 .udt_dimm_no = 0, 1591 .udt_dimm_col = 0, 1592 .udt_dimm_row = 0xfff, 1593 .udt_dimm_bank = 0, 1594 .udt_dimm_bank_group = 1, 1595 .udt_dimm_subchan = UINT8_MAX, 1596 .udt_dimm_rm = 0, 1597 .udt_dimm_cs = 0 1598 }, { 1599 .udt_desc = "2 DPC 2R bank hash, rank ilv (19)", 1600 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1601 .udt_pa = 0x71c000, 1602 .udt_pass = B_TRUE, 1603 .udt_norm_addr = 0x71c000, 1604 .udt_sock = 0, 1605 .udt_die = 0, 1606 .udt_comp = 1, 1607 .udt_dimm_no = 0, 1608 .udt_dimm_col = 0, 1609 .udt_dimm_row = 0xe, 1610 .udt_dimm_bank = 0, 1611 .udt_dimm_bank_group = 0, 1612 .udt_dimm_subchan = UINT8_MAX, 1613 .udt_dimm_rm = 0, 1614 .udt_dimm_cs = 0 1615 }, { 1616 .udt_desc = "2 DPC 2R bank hash, rank ilv (20)", 1617 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1618 .udt_pa = 0x71c118, 1619 .udt_pass = B_TRUE, 1620 .udt_norm_addr = 0x71c118, 1621 .udt_sock = 0, 1622 .udt_die = 0, 1623 .udt_comp = 1, 1624 .udt_dimm_no = 0, 1625 .udt_dimm_col = 0x23, 1626 .udt_dimm_row = 0xe, 1627 .udt_dimm_bank = 0, 1628 .udt_dimm_bank_group = 0, 1629 .udt_dimm_subchan = UINT8_MAX, 1630 .udt_dimm_rm = 0, 1631 .udt_dimm_cs = 0 1632 }, 1633 /* 1634 * Bank swapping. We basically do a few sanity tests on this just to make sure 1635 * the right bits are triggering things here in the first DIMM/rank. 1636 */ 1637 { 1638 .udt_desc = "2 DPC 2R bank swap, rank ilv (0)", 1639 .udt_umc = &zen_umc_chan_ilv_bank_swap, 1640 .udt_pa = 0x4247, 1641 .udt_pass = B_TRUE, 1642 .udt_norm_addr = 0x4247, 1643 .udt_sock = 0, 1644 .udt_die = 0, 1645 .udt_comp = 1, 1646 .udt_dimm_no = 0, 1647 .udt_dimm_col = 0x80, 1648 .udt_dimm_row = 0, 1649 .udt_dimm_bank = 1, 1650 .udt_dimm_bank_group = 1, 1651 .udt_dimm_subchan = UINT8_MAX, 1652 .udt_dimm_rm = 0, 1653 .udt_dimm_cs = 0 1654 }, { 1655 .udt_desc = "2 DPC 2R bank swap, rank ilv (1)", 1656 .udt_umc = &zen_umc_chan_ilv_bank_swap, 1657 .udt_pa = 0xff6214247, 1658 .udt_pass = B_TRUE, 1659 .udt_norm_addr = 0xff6214247, 1660 .udt_sock = 0, 1661 .udt_die = 0, 1662 .udt_comp = 1, 1663 .udt_dimm_no = 0, 1664 .udt_dimm_col = 0x280, 1665 .udt_dimm_row = 0x1fec4, 1666 .udt_dimm_bank = 1, 1667 .udt_dimm_bank_group = 1, 1668 .udt_dimm_subchan = UINT8_MAX, 1669 .udt_dimm_rm = 0, 1670 .udt_dimm_cs = 0 1671 }, { 1672 .udt_desc = "Basic DDR5 Sub-channel (0)", 1673 .udt_umc = &zen_umc_chan_subchan_no_hash, 1674 .udt_pa = 0x0, 1675 .udt_pass = B_TRUE, 1676 .udt_norm_addr = 0x0, 1677 .udt_sock = 0, 1678 .udt_die = 0, 1679 .udt_comp = 1, 1680 .udt_dimm_no = 0, 1681 .udt_dimm_col = 0x0, 1682 .udt_dimm_row = 0x0, 1683 .udt_dimm_bank = 0, 1684 .udt_dimm_bank_group = 0, 1685 .udt_dimm_subchan = 0, 1686 .udt_dimm_rm = 0, 1687 .udt_dimm_cs = 0 1688 }, { 1689 .udt_desc = "Basic DDR5 Sub-channel (1)", 1690 .udt_umc = &zen_umc_chan_subchan_no_hash, 1691 .udt_pa = 0x9999, 1692 .udt_pass = B_TRUE, 1693 .udt_norm_addr = 0x9999, 1694 .udt_sock = 0, 1695 .udt_die = 0, 1696 .udt_comp = 1, 1697 .udt_dimm_no = 0, 1698 .udt_dimm_col = 0x336, 1699 .udt_dimm_row = 0x0, 1700 .udt_dimm_bank = 0, 1701 .udt_dimm_bank_group = 1, 1702 .udt_dimm_subchan = 0, 1703 .udt_dimm_rm = 0, 1704 .udt_dimm_cs = 0 1705 }, { 1706 .udt_desc = "Basic DDR5 Sub-channel (2)", 1707 .udt_umc = &zen_umc_chan_subchan_no_hash, 1708 .udt_pa = 0x99d9, 1709 .udt_pass = B_TRUE, 1710 .udt_norm_addr = 0x99d9, 1711 .udt_sock = 0, 1712 .udt_die = 0, 1713 .udt_comp = 1, 1714 .udt_dimm_no = 0, 1715 .udt_dimm_col = 0x336, 1716 .udt_dimm_row = 0x0, 1717 .udt_dimm_bank = 0, 1718 .udt_dimm_bank_group = 1, 1719 .udt_dimm_subchan = 1, 1720 .udt_dimm_rm = 0, 1721 .udt_dimm_cs = 0 1722 }, { 1723 .udt_desc = NULL 1724 } }; 1725