1x86 FPU with 256-bit %ymm registers 2xcr0 0x7 3xfd 0x0 4xstate_bv 0x7 5xcomp_bv 0x0 6 7%ymm0 [255:128] 0x1190045d 1190045c 1190045b 1190045a 8%xmm0 [127:0] 0x11900459 11900458 11900457 11900456 9 10%ymm1 [255:128] 0x11900465 11900464 11900463 11900462 11%xmm1 [127:0] 0x11900461 11900460 1190045f 1190045e 12 13%ymm2 [255:128] 0x1190046d 1190046c 1190046b 1190046a 14%xmm2 [127:0] 0x11900469 11900468 11900467 11900466 15 16%ymm3 [255:128] 0x11900475 11900474 11900473 11900472 17%xmm3 [127:0] 0x11900471 11900470 1190046f 1190046e 18 19%ymm4 [255:128] 0x1190047d 1190047c 1190047b 1190047a 20%xmm4 [127:0] 0x11900479 11900478 11900477 11900476 21 22%ymm5 [255:128] 0x11900485 11900484 11900483 11900482 23%xmm5 [127:0] 0x11900481 11900480 1190047f 1190047e 24 25%ymm6 [255:128] 0x1190048d 1190048c 1190048b 1190048a 26%xmm6 [127:0] 0x11900489 11900488 11900487 11900486 27 28%ymm7 [255:128] 0x11900495 11900494 11900493 11900492 29%xmm7 [127:0] 0x11900491 11900490 1190048f 1190048e 30 31%ymm8 [255:128] 0x1190049d 1190049c 1190049b 1190049a 32%xmm8 [127:0] 0x11900499 11900498 11900497 11900496 33 34%ymm9 [255:128] 0x119004a5 119004a4 119004a3 119004a2 35%xmm9 [127:0] 0x119004a1 119004a0 1190049f 1190049e 36 37%ymm10 [255:128] 0x119004ad 119004ac 119004ab 119004aa 38%xmm10 [127:0] 0x119004a9 119004a8 119004a7 119004a6 39 40%ymm11 [255:128] 0x119004b5 119004b4 119004b3 119004b2 41%xmm11 [127:0] 0x119004b1 119004b0 119004af 119004ae 42 43%ymm12 [255:128] 0x119004bd 119004bc 119004bb 119004ba 44%xmm12 [127:0] 0x119004b9 119004b8 119004b7 119004b6 45 46%ymm13 [255:128] 0x119004c5 119004c4 119004c3 119004c2 47%xmm13 [127:0] 0x119004c1 119004c0 119004bf 119004be 48 49%ymm14 [255:128] 0x119004cd 119004cc 119004cb 119004ca 50%xmm14 [127:0] 0x119004c9 119004c8 119004c7 119004c6 51 52%ymm15 [255:128] 0x119004d5 119004d4 119004d3 119004d2 53%xmm15 [127:0] 0x119004d1 119004d0 119004cf 119004ce 54 55387 and FP Control State 56cw 0x137f (IM|DM|ZM|OM|UM|PM|SIG64|RTN|A) 57sw 0x0000 (TOP=0t0) (0) 58xcp sw 0x0000 (0) 59 60fop 0x0 61rip 0x0 62rdp 0x0 63 64%st0 0x0000.0000000000000000 = +0.0000000000000000e+00 empty 65%st1 0x0000.0000000000000000 = +0.0000000000000000e+00 empty 66%st2 0x0000.0000000000000000 = +0.0000000000000000e+00 empty 67%st3 0x0000.0000000000000000 = +0.0000000000000000e+00 empty 68%st4 0x0000.0000000000000000 = +0.0000000000000000e+00 empty 69%st5 0x0000.0000000000000000 = +0.0000000000000000e+00 empty 70%st6 0x0000.0000000000000000 = +0.0000000000000000e+00 empty 71%st7 0x0000.0000000000000000 = +0.0000000000000000e+00 empty 72 73SSE Control State 74mxcsr 0x1f80 (IM|DM|ZM|OM|UM|PM|RTN) 75xcp 0x0000 (RTN) 76