1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2019 Joyent, Inc. 14 */ 15 16 #include "imc_test.h" 17 18 /* 19 * This tests various aspects of the target address decoder. 20 * 21 * o TAD rules with different channel interleaving 22 * o TAD rules with channel shifting (IVB->BRD) 23 * o TAD rules with channel hashing (IVB->BRD) 24 * o TAD rules with different granularities (SKX) 25 * o Channel rules with mod2/3 variants (SKX) 26 * 27 * We use the most basic of SAD rules and RIR rules when constructing these. 28 * Those are more generally exercised elsewhere. Basic socket granularity rules 29 * are tested in imc_test_sad.c. 30 * 31 * There are currently no tests for mirroring or lockstep mode as that's not 32 * more generally supported. 33 */ 34 35 static const imc_t imc_tad_1s_2cw = { 36 .imc_gen = IMC_GEN_SANDY, 37 .imc_nsockets = 1, 38 .imc_sockets[0] = { 39 .isock_valid = IMC_SOCKET_V_VALID, 40 .isock_sad = { 41 .isad_flags = 0, 42 .isad_valid = IMC_SAD_V_VALID, 43 .isad_tolm = 0x80000000, 44 .isad_tohm = 0, 45 .isad_nrules = 10, 46 .isad_rules[0] = { 47 .isr_enable = B_TRUE, 48 .isr_limit = 0x80000000, 49 .isr_imode = IMC_SAD_IMODE_8t6, 50 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 51 .isr_targets = { 0, 0, 0, 0, 0, 0, 0, 0 } 52 } 53 }, 54 .isock_ntad = 1, 55 .isock_tad[0] = { 56 .itad_flags = 0, 57 .itad_nrules = 12, 58 .itad_rules[0] = { 59 .itr_base = 0x0, 60 .itr_limit = 0x80000000, 61 .itr_sock_way = 1, 62 .itr_chan_way = 2, 63 .itr_sock_gran = IMC_TAD_GRAN_64B, 64 .itr_chan_gran = IMC_TAD_GRAN_64B, 65 .itr_ntargets = 4, 66 .itr_targets = { 0, 1, 0, 0 } 67 } 68 }, 69 .isock_nimc = 1, 70 .isock_imcs[0] = { 71 .icn_nchannels = 2, 72 .icn_dimm_type = IMC_DIMM_DDR3, 73 .icn_ecc = B_TRUE, 74 .icn_lockstep = B_FALSE, 75 .icn_closed = B_FALSE, 76 .icn_channels[0] = { 77 .ich_ndimms = 1, 78 .ich_dimms[0] = { 79 .idimm_present = B_TRUE, 80 .idimm_nbanks = 3, 81 .idimm_width = 8, 82 .idimm_density = 2, 83 .idimm_nranks = 2, 84 .idimm_nrows = 14, 85 .idimm_ncolumns = 10, 86 .idimm_size = 0x40000000 87 }, 88 .ich_ntad_offsets = 12, 89 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 90 0, 0 }, 91 .ich_nrankileaves = 8, 92 .ich_rankileaves[0] = { 93 .irle_enabled = B_TRUE, 94 .irle_nways = 1, 95 .irle_nwaysbits = 1, 96 .irle_limit = 0x40000000, 97 .irle_nentries = 8, 98 .irle_entries[0] = { 0x0, 0x0 }, 99 } 100 }, 101 .icn_channels[1] = { 102 .ich_ndimms = 1, 103 .ich_dimms[0] = { 104 .idimm_present = B_TRUE, 105 .idimm_nbanks = 3, 106 .idimm_width = 8, 107 .idimm_density = 2, 108 .idimm_nranks = 2, 109 .idimm_nrows = 14, 110 .idimm_ncolumns = 10, 111 .idimm_size = 0x40000000 112 }, 113 .ich_ntad_offsets = 12, 114 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 115 0, 0 }, 116 .ich_nrankileaves = 8, 117 .ich_rankileaves[0] = { 118 .irle_enabled = B_TRUE, 119 .irle_nways = 1, 120 .irle_nwaysbits = 1, 121 .irle_limit = 0x40000000, 122 .irle_nentries = 8, 123 .irle_entries[0] = { 0x0, 0x0 }, 124 } 125 } 126 } 127 } 128 }; 129 130 /* 131 * This IMC has the a7mode/McChanShiftUp set. This means that instead of using 132 * bits 0-6 for an address, it should use bits 0-7. 133 */ 134 static const imc_t imc_tad_1s_2cw_shiftup = { 135 .imc_gen = IMC_GEN_IVY, 136 .imc_nsockets = 1, 137 .imc_sockets[0] = { 138 .isock_valid = IMC_SOCKET_V_VALID, 139 .isock_sad = { 140 .isad_flags = 0, 141 .isad_valid = IMC_SAD_V_VALID, 142 .isad_tolm = 0x80000000, 143 .isad_tohm = 0, 144 .isad_nrules = 10, 145 .isad_rules[0] = { 146 .isr_enable = B_TRUE, 147 .isr_limit = 0x80000000, 148 .isr_imode = IMC_SAD_IMODE_8t6, 149 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 150 .isr_a7mode = B_TRUE, 151 .isr_targets = { 0, 0, 0, 0, 0, 0, 0, 0 } 152 } 153 }, 154 .isock_ntad = 1, 155 .isock_tad[0] = { 156 .itad_flags = IMC_TAD_FLAG_CHANSHIFT, 157 .itad_nrules = 12, 158 .itad_rules[0] = { 159 .itr_base = 0x0, 160 .itr_limit = 0x80000000, 161 .itr_sock_way = 1, 162 .itr_chan_way = 2, 163 .itr_sock_gran = IMC_TAD_GRAN_64B, 164 .itr_chan_gran = IMC_TAD_GRAN_64B, 165 .itr_ntargets = 4, 166 .itr_targets = { 0, 1, 0, 0 } 167 } 168 }, 169 .isock_nimc = 1, 170 .isock_imcs[0] = { 171 .icn_nchannels = 2, 172 .icn_dimm_type = IMC_DIMM_DDR3, 173 .icn_ecc = B_TRUE, 174 .icn_lockstep = B_FALSE, 175 .icn_closed = B_FALSE, 176 .icn_channels[0] = { 177 .ich_ndimms = 1, 178 .ich_dimms[0] = { 179 .idimm_present = B_TRUE, 180 .idimm_nbanks = 3, 181 .idimm_width = 8, 182 .idimm_density = 2, 183 .idimm_nranks = 2, 184 .idimm_nrows = 14, 185 .idimm_ncolumns = 10, 186 .idimm_size = 0x40000000 187 }, 188 .ich_ntad_offsets = 12, 189 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 190 0, 0 }, 191 .ich_nrankileaves = 8, 192 .ich_rankileaves[0] = { 193 .irle_enabled = B_TRUE, 194 .irle_nways = 1, 195 .irle_nwaysbits = 1, 196 .irle_limit = 0x40000000, 197 .irle_nentries = 8, 198 .irle_entries[0] = { 0x0, 0x0 }, 199 } 200 }, 201 .icn_channels[1] = { 202 .ich_ndimms = 1, 203 .ich_dimms[0] = { 204 .idimm_present = B_TRUE, 205 .idimm_nbanks = 3, 206 .idimm_width = 8, 207 .idimm_density = 2, 208 .idimm_nranks = 2, 209 .idimm_nrows = 14, 210 .idimm_ncolumns = 10, 211 .idimm_size = 0x40000000 212 }, 213 .ich_ntad_offsets = 12, 214 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 215 0, 0 }, 216 .ich_nrankileaves = 8, 217 .ich_rankileaves[0] = { 218 .irle_enabled = B_TRUE, 219 .irle_nways = 1, 220 .irle_nwaysbits = 1, 221 .irle_limit = 0x40000000, 222 .irle_nentries = 8, 223 .irle_entries[0] = { 0x0, 0x0 }, 224 } 225 } 226 } 227 } 228 }; 229 230 /* 231 * This IMC has the channel hashing mode set on all of the channels in question. 232 * This means that the TAD will hash the upper address bits into the channel 233 * determination. 234 */ 235 static const imc_t imc_tad_1s_2cw_chanhash = { 236 .imc_gen = IMC_GEN_HASWELL, 237 .imc_nsockets = 1, 238 .imc_sockets[0] = { 239 .isock_valid = IMC_SOCKET_V_VALID, 240 .isock_sad = { 241 .isad_flags = 0, 242 .isad_valid = IMC_SAD_V_VALID, 243 .isad_tolm = 0x80000000, 244 .isad_tohm = 0, 245 .isad_nrules = 10, 246 .isad_rules[0] = { 247 .isr_enable = B_TRUE, 248 .isr_limit = 0x80000000, 249 .isr_imode = IMC_SAD_IMODE_8t6, 250 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 251 .isr_targets = { 0, 0, 0, 0, 0, 0, 0, 0 } 252 } 253 }, 254 .isock_ntad = 1, 255 .isock_tad[0] = { 256 .itad_flags = IMC_TAD_FLAG_CHANHASH, 257 .itad_nrules = 12, 258 .itad_rules[0] = { 259 .itr_base = 0x0, 260 .itr_limit = 0x80000000, 261 .itr_sock_way = 1, 262 .itr_chan_way = 2, 263 .itr_sock_gran = IMC_TAD_GRAN_64B, 264 .itr_chan_gran = IMC_TAD_GRAN_64B, 265 .itr_ntargets = 4, 266 .itr_targets = { 0, 1, 0, 0 } 267 } 268 }, 269 .isock_nimc = 1, 270 .isock_imcs[0] = { 271 .icn_nchannels = 2, 272 .icn_dimm_type = IMC_DIMM_DDR3, 273 .icn_ecc = B_TRUE, 274 .icn_lockstep = B_FALSE, 275 .icn_closed = B_FALSE, 276 .icn_channels[0] = { 277 .ich_ndimms = 1, 278 .ich_dimms[0] = { 279 .idimm_present = B_TRUE, 280 .idimm_nbanks = 3, 281 .idimm_width = 8, 282 .idimm_density = 2, 283 .idimm_nranks = 2, 284 .idimm_nrows = 14, 285 .idimm_ncolumns = 10, 286 .idimm_size = 0x40000000 287 }, 288 .ich_ntad_offsets = 12, 289 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 290 0, 0 }, 291 .ich_nrankileaves = 8, 292 .ich_rankileaves[0] = { 293 .irle_enabled = B_TRUE, 294 .irle_nways = 1, 295 .irle_nwaysbits = 1, 296 .irle_limit = 0x40000000, 297 .irle_nentries = 8, 298 .irle_entries[0] = { 0x0, 0x0 }, 299 } 300 }, 301 .icn_channels[1] = { 302 .ich_ndimms = 1, 303 .ich_dimms[0] = { 304 .idimm_present = B_TRUE, 305 .idimm_nbanks = 3, 306 .idimm_width = 8, 307 .idimm_density = 2, 308 .idimm_nranks = 2, 309 .idimm_nrows = 14, 310 .idimm_ncolumns = 10, 311 .idimm_size = 0x40000000 312 }, 313 .ich_ntad_offsets = 12, 314 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 315 0, 0 }, 316 .ich_nrankileaves = 8, 317 .ich_rankileaves[0] = { 318 .irle_enabled = B_TRUE, 319 .irle_nways = 1, 320 .irle_nwaysbits = 1, 321 .irle_limit = 0x40000000, 322 .irle_nentries = 8, 323 .irle_entries[0] = { 0x0, 0x0 }, 324 } 325 } 326 } 327 } 328 }; 329 330 /* 331 * This IMC has different TAD rules that cover different ranges, which change 332 * how we interleave. The main goal is to make sure that we're always going to 333 * the right place. This also requires us to set TAD offsets on a 334 * per-channel/TAD rule basis. These are required to correctly make sure that we 335 * map things. The following is how the address space should in theory look. We 336 * have 2 GiB (0x80000000) of address space. We break that into 4 512 MiB 337 * chunks. The first and last are 2-way interleaved. The middle two are 1-way 338 * interleaved to a specific channel. 339 */ 340 static const imc_t imc_tad_1s_multirule = { 341 .imc_gen = IMC_GEN_BROADWELL, 342 .imc_nsockets = 1, 343 .imc_sockets[0] = { 344 .isock_valid = IMC_SOCKET_V_VALID, 345 .isock_sad = { 346 .isad_flags = 0, 347 .isad_valid = IMC_SAD_V_VALID, 348 .isad_tolm = 0x80000000, 349 .isad_tohm = 0, 350 .isad_nrules = 10, 351 .isad_rules[0] = { 352 .isr_enable = B_TRUE, 353 .isr_limit = 0x80000000, 354 .isr_imode = IMC_SAD_IMODE_8t6, 355 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 356 .isr_targets = { 0, 0, 0, 0, 0, 0, 0, 0 } 357 } 358 }, 359 .isock_ntad = 1, 360 .isock_tad[0] = { 361 .itad_flags = 0, 362 .itad_nrules = 12, 363 .itad_rules[0] = { 364 .itr_base = 0x0, 365 .itr_limit = 0x20000000, 366 .itr_sock_way = 1, 367 .itr_chan_way = 2, 368 .itr_sock_gran = IMC_TAD_GRAN_64B, 369 .itr_chan_gran = IMC_TAD_GRAN_64B, 370 .itr_ntargets = 4, 371 .itr_targets = { 0, 1, 0, 0 } 372 }, 373 .itad_rules[1] = { 374 .itr_base = 0x20000000, 375 .itr_limit = 0x40000000, 376 .itr_sock_way = 1, 377 .itr_chan_way = 1, 378 .itr_sock_gran = IMC_TAD_GRAN_64B, 379 .itr_chan_gran = IMC_TAD_GRAN_64B, 380 .itr_ntargets = 4, 381 .itr_targets = { 1, 1, 0, 0 } 382 }, 383 .itad_rules[2] = { 384 .itr_base = 0x40000000, 385 .itr_limit = 0x60000000, 386 .itr_sock_way = 1, 387 .itr_chan_way = 1, 388 .itr_sock_gran = IMC_TAD_GRAN_64B, 389 .itr_chan_gran = IMC_TAD_GRAN_64B, 390 .itr_ntargets = 4, 391 .itr_targets = { 0, 0, 0, 0 } 392 }, 393 .itad_rules[3] = { 394 .itr_base = 0x60000000, 395 .itr_limit = 0x80000000, 396 .itr_sock_way = 1, 397 .itr_chan_way = 2, 398 .itr_sock_gran = IMC_TAD_GRAN_64B, 399 .itr_chan_gran = IMC_TAD_GRAN_64B, 400 .itr_ntargets = 4, 401 .itr_targets = { 1, 0, 0, 0 } 402 } 403 }, 404 .isock_nimc = 1, 405 .isock_imcs[0] = { 406 .icn_nchannels = 2, 407 .icn_dimm_type = IMC_DIMM_DDR3, 408 .icn_ecc = B_TRUE, 409 .icn_lockstep = B_FALSE, 410 .icn_closed = B_FALSE, 411 .icn_channels[0] = { 412 .ich_ndimms = 1, 413 .ich_dimms[0] = { 414 .idimm_present = B_TRUE, 415 .idimm_nbanks = 3, 416 .idimm_width = 8, 417 .idimm_density = 2, 418 .idimm_nranks = 2, 419 .idimm_nrows = 14, 420 .idimm_ncolumns = 10, 421 .idimm_size = 0x40000000 422 }, 423 .ich_ntad_offsets = 12, 424 .ich_tad_offsets = { 0, 0, 0x30000000, 0, 0, 425 0, 0, 0, 0, 0, 0 }, 426 .ich_nrankileaves = 8, 427 .ich_rankileaves[0] = { 428 .irle_enabled = B_TRUE, 429 .irle_nways = 1, 430 .irle_nwaysbits = 1, 431 .irle_limit = 0x40000000, 432 .irle_nentries = 8, 433 .irle_entries[0] = { 0x0, 0x0 }, 434 } 435 }, 436 .icn_channels[1] = { 437 .ich_ndimms = 1, 438 .ich_dimms[0] = { 439 .idimm_present = B_TRUE, 440 .idimm_nbanks = 3, 441 .idimm_width = 8, 442 .idimm_density = 2, 443 .idimm_nranks = 2, 444 .idimm_nrows = 14, 445 .idimm_ncolumns = 10, 446 .idimm_size = 0x40000000 447 }, 448 .ich_ntad_offsets = 12, 449 .ich_tad_offsets = { 0, 0x10000000, 0, 0, 0, 0, 450 0, 0, 0, 0, 0 }, 451 .ich_nrankileaves = 8, 452 .ich_rankileaves[0] = { 453 .irle_enabled = B_TRUE, 454 .irle_nways = 1, 455 .irle_nwaysbits = 1, 456 .irle_limit = 0x40000000, 457 .irle_nentries = 8, 458 .irle_entries[0] = { 0x0, 0x0 }, 459 } 460 } 461 } 462 } 463 }; 464 465 /* 466 * The purpse of this IMC is to use a combination of both socket and channel 467 * interleaving. It employs a system with two sockets, each which have 2 IMCs. 468 * Each IMC has two channels. We have a 4-way socket interleave followed by a 469 * 2-way channel interleave. We use a simplified memory layout (TOLM = 4 GiB) to 470 * simplify other rules. 471 */ 472 static const imc_t imc_tad_2s_2cw_4sw = { 473 .imc_gen = IMC_GEN_IVY, 474 .imc_nsockets = 2, 475 .imc_sockets[0] = { 476 .isock_nodeid = 0, 477 .isock_valid = IMC_SOCKET_V_VALID, 478 .isock_sad = { 479 .isad_flags = 0, 480 .isad_valid = IMC_SAD_V_VALID, 481 .isad_tolm = 0x100000000ULL, 482 .isad_tohm = 0x200000000ULL, 483 .isad_nrules = 10, 484 .isad_rules[0] = { 485 .isr_enable = B_TRUE, 486 .isr_limit = 0x200000000ULL, 487 .isr_imode = IMC_SAD_IMODE_8t6, 488 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 489 .isr_targets = { 0, 4, 1, 5, 0, 4, 1, 5 } 490 } 491 }, 492 .isock_ntad = 2, 493 .isock_tad[0] = { 494 .itad_flags = 0, 495 .itad_nrules = 12, 496 .itad_rules[0] = { 497 .itr_base = 0x0, 498 .itr_limit = 0x200000000ULL, 499 .itr_sock_way = 4, 500 .itr_chan_way = 2, 501 .itr_sock_gran = IMC_TAD_GRAN_64B, 502 .itr_chan_gran = IMC_TAD_GRAN_64B, 503 .itr_ntargets = 4, 504 .itr_targets = { 0, 1, 0, 0 } 505 } 506 }, 507 .isock_tad[1] = { 508 .itad_flags = 0, 509 .itad_nrules = 12, 510 .itad_rules[0] = { 511 .itr_base = 0x0, 512 .itr_limit = 0x200000000ULL, 513 .itr_sock_way = 4, 514 .itr_chan_way = 2, 515 .itr_sock_gran = IMC_TAD_GRAN_64B, 516 .itr_chan_gran = IMC_TAD_GRAN_64B, 517 .itr_ntargets = 4, 518 .itr_targets = { 1, 0, 0, 0 } 519 } 520 }, 521 .isock_nimc = 2, 522 .isock_imcs[0] = { 523 .icn_nchannels = 2, 524 .icn_dimm_type = IMC_DIMM_DDR3, 525 .icn_ecc = B_TRUE, 526 .icn_lockstep = B_FALSE, 527 .icn_closed = B_FALSE, 528 .icn_channels[0] = { 529 .ich_ndimms = 1, 530 .ich_dimms[0] = { 531 .idimm_present = B_TRUE, 532 .idimm_nbanks = 3, 533 .idimm_width = 8, 534 .idimm_density = 2, 535 .idimm_nranks = 2, 536 .idimm_nrows = 14, 537 .idimm_ncolumns = 10, 538 .idimm_size = 0x40000000 539 }, 540 .ich_ntad_offsets = 12, 541 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 542 0, 0 }, 543 .ich_nrankileaves = 8, 544 .ich_rankileaves[0] = { 545 .irle_enabled = B_TRUE, 546 .irle_nways = 1, 547 .irle_nwaysbits = 1, 548 .irle_limit = 0x40000000, 549 .irle_nentries = 8, 550 .irle_entries[0] = { 0x0, 0x0 }, 551 } 552 }, 553 .icn_channels[1] = { 554 .ich_ndimms = 1, 555 .ich_dimms[0] = { 556 .idimm_present = B_TRUE, 557 .idimm_nbanks = 3, 558 .idimm_width = 8, 559 .idimm_density = 2, 560 .idimm_nranks = 2, 561 .idimm_nrows = 14, 562 .idimm_ncolumns = 10, 563 .idimm_size = 0x40000000 564 }, 565 .ich_ntad_offsets = 12, 566 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 567 0, 0 }, 568 .ich_nrankileaves = 8, 569 .ich_rankileaves[0] = { 570 .irle_enabled = B_TRUE, 571 .irle_nways = 1, 572 .irle_nwaysbits = 1, 573 .irle_limit = 0x40000000, 574 .irle_nentries = 8, 575 .irle_entries[0] = { 0x0, 0x0 }, 576 } 577 } 578 }, 579 .isock_imcs[1] = { 580 .icn_nchannels = 2, 581 .icn_dimm_type = IMC_DIMM_DDR3, 582 .icn_ecc = B_TRUE, 583 .icn_lockstep = B_FALSE, 584 .icn_closed = B_FALSE, 585 .icn_channels[0] = { 586 .ich_ndimms = 1, 587 .ich_dimms[0] = { 588 .idimm_present = B_TRUE, 589 .idimm_nbanks = 3, 590 .idimm_width = 8, 591 .idimm_density = 2, 592 .idimm_nranks = 2, 593 .idimm_nrows = 14, 594 .idimm_ncolumns = 10, 595 .idimm_size = 0x40000000 596 }, 597 .ich_ntad_offsets = 12, 598 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 599 0, 0 }, 600 .ich_nrankileaves = 8, 601 .ich_rankileaves[0] = { 602 .irle_enabled = B_TRUE, 603 .irle_nways = 1, 604 .irle_nwaysbits = 1, 605 .irle_limit = 0x40000000, 606 .irle_nentries = 8, 607 .irle_entries[0] = { 0x0, 0x0 }, 608 } 609 }, 610 .icn_channels[1] = { 611 .ich_ndimms = 1, 612 .ich_dimms[0] = { 613 .idimm_present = B_TRUE, 614 .idimm_nbanks = 3, 615 .idimm_width = 8, 616 .idimm_density = 2, 617 .idimm_nranks = 2, 618 .idimm_nrows = 14, 619 .idimm_ncolumns = 10, 620 .idimm_size = 0x40000000 621 }, 622 .ich_ntad_offsets = 12, 623 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 624 0, 0 }, 625 .ich_nrankileaves = 8, 626 .ich_rankileaves[0] = { 627 .irle_enabled = B_TRUE, 628 .irle_nways = 1, 629 .irle_nwaysbits = 1, 630 .irle_limit = 0x40000000, 631 .irle_nentries = 8, 632 .irle_entries[0] = { 0x0, 0x0 }, 633 } 634 } 635 } 636 }, 637 .imc_sockets[1] = { 638 .isock_nodeid = 1, 639 .isock_valid = IMC_SOCKET_V_VALID, 640 .isock_sad = { 641 .isad_flags = 0, 642 .isad_valid = IMC_SAD_V_VALID, 643 .isad_tolm = 0x80000000, 644 .isad_tohm = 0, 645 .isad_nrules = 10, 646 .isad_rules[0] = { 647 .isr_enable = B_TRUE, 648 .isr_limit = 0x80000000, 649 .isr_imode = IMC_SAD_IMODE_8t6, 650 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 651 .isr_targets = { 0, 4, 1, 5, 0, 4, 1, 5 } 652 } 653 }, 654 .isock_ntad = 2, 655 .isock_tad[0] = { 656 .itad_flags = 0, 657 .itad_nrules = 12, 658 .itad_rules[0] = { 659 .itr_base = 0x0, 660 .itr_limit = 0x200000000ULL, 661 .itr_sock_way = 4, 662 .itr_chan_way = 2, 663 .itr_sock_gran = IMC_TAD_GRAN_64B, 664 .itr_chan_gran = IMC_TAD_GRAN_64B, 665 .itr_ntargets = 4, 666 .itr_targets = { 1, 0, 0, 0 } 667 } 668 }, 669 .isock_tad[1] = { 670 .itad_flags = 0, 671 .itad_nrules = 12, 672 .itad_rules[0] = { 673 .itr_base = 0x0, 674 .itr_limit = 0x200000000ULL, 675 .itr_sock_way = 4, 676 .itr_chan_way = 2, 677 .itr_sock_gran = IMC_TAD_GRAN_64B, 678 .itr_chan_gran = IMC_TAD_GRAN_64B, 679 .itr_ntargets = 4, 680 .itr_targets = { 0, 1, 0, 0 } 681 } 682 }, 683 .isock_nimc = 2, 684 .isock_imcs[0] = { 685 .icn_nchannels = 2, 686 .icn_dimm_type = IMC_DIMM_DDR3, 687 .icn_ecc = B_TRUE, 688 .icn_lockstep = B_FALSE, 689 .icn_closed = B_FALSE, 690 .icn_channels[0] = { 691 .ich_ndimms = 1, 692 .ich_dimms[0] = { 693 .idimm_present = B_TRUE, 694 .idimm_nbanks = 3, 695 .idimm_width = 8, 696 .idimm_density = 2, 697 .idimm_nranks = 2, 698 .idimm_nrows = 14, 699 .idimm_ncolumns = 10, 700 .idimm_size = 0x40000000 701 }, 702 .ich_ntad_offsets = 12, 703 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 704 0, 0 }, 705 .ich_nrankileaves = 8, 706 .ich_rankileaves[0] = { 707 .irle_enabled = B_TRUE, 708 .irle_nways = 1, 709 .irle_nwaysbits = 1, 710 .irle_limit = 0x40000000, 711 .irle_nentries = 8, 712 .irle_entries[0] = { 0x0, 0x0 }, 713 } 714 }, 715 .icn_channels[1] = { 716 .ich_ndimms = 1, 717 .ich_dimms[0] = { 718 .idimm_present = B_TRUE, 719 .idimm_nbanks = 3, 720 .idimm_width = 8, 721 .idimm_density = 2, 722 .idimm_nranks = 2, 723 .idimm_nrows = 14, 724 .idimm_ncolumns = 10, 725 .idimm_size = 0x40000000 726 }, 727 .ich_ntad_offsets = 12, 728 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 729 0, 0 }, 730 .ich_nrankileaves = 8, 731 .ich_rankileaves[0] = { 732 .irle_enabled = B_TRUE, 733 .irle_nways = 1, 734 .irle_nwaysbits = 1, 735 .irle_limit = 0x40000000, 736 .irle_nentries = 8, 737 .irle_entries[0] = { 0x0, 0x0 }, 738 } 739 } 740 }, 741 .isock_imcs[1] = { 742 .icn_nchannels = 2, 743 .icn_dimm_type = IMC_DIMM_DDR3, 744 .icn_ecc = B_TRUE, 745 .icn_lockstep = B_FALSE, 746 .icn_closed = B_FALSE, 747 .icn_channels[0] = { 748 .ich_ndimms = 1, 749 .ich_dimms[0] = { 750 .idimm_present = B_TRUE, 751 .idimm_nbanks = 3, 752 .idimm_width = 8, 753 .idimm_density = 2, 754 .idimm_nranks = 2, 755 .idimm_nrows = 14, 756 .idimm_ncolumns = 10, 757 .idimm_size = 0x40000000 758 }, 759 .ich_ntad_offsets = 12, 760 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 761 0, 0 }, 762 .ich_nrankileaves = 8, 763 .ich_rankileaves[0] = { 764 .irle_enabled = B_TRUE, 765 .irle_nways = 1, 766 .irle_nwaysbits = 1, 767 .irle_limit = 0x40000000, 768 .irle_nentries = 8, 769 .irle_entries[0] = { 0x0, 0x0 }, 770 } 771 }, 772 .icn_channels[1] = { 773 .ich_ndimms = 1, 774 .ich_dimms[0] = { 775 .idimm_present = B_TRUE, 776 .idimm_nbanks = 3, 777 .idimm_width = 8, 778 .idimm_density = 2, 779 .idimm_nranks = 2, 780 .idimm_nrows = 14, 781 .idimm_ncolumns = 10, 782 .idimm_size = 0x40000000 783 }, 784 .ich_ntad_offsets = 12, 785 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 786 0, 0 }, 787 .ich_nrankileaves = 8, 788 .ich_rankileaves[0] = { 789 .irle_enabled = B_TRUE, 790 .irle_nways = 1, 791 .irle_nwaysbits = 1, 792 .irle_limit = 0x40000000, 793 .irle_nentries = 8, 794 .irle_entries[0] = { 0x0, 0x0 }, 795 } 796 } 797 } 798 } 799 }; 800 801 /* 802 * This IMC has a single socket with two IMCs and two channels. It uses the 803 * default granularities and sizes. This just serves as a basis for the 804 * subsequent tests. 805 */ 806 static const imc_t imc_skx_64b_gran = { 807 .imc_gen = IMC_GEN_SKYLAKE, 808 .imc_nsockets = 1, 809 .imc_sockets[0] = { 810 .isock_nodeid = 0, 811 .isock_valid = IMC_SOCKET_V_VALID, 812 .isock_sad = { 813 .isad_flags = 0, 814 .isad_valid = IMC_SAD_V_VALID, 815 .isad_tolm = 0x80000000, 816 .isad_tohm = 0, 817 .isad_nrules = 24, 818 .isad_rules[0] = { 819 .isr_enable = B_TRUE, 820 .isr_limit = 0x80000000, 821 .isr_imode = IMC_SAD_IMODE_8t6, 822 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 823 .isr_targets = { 8, 9, 8, 9, 8, 9, 8, 9 } 824 }, 825 .isad_mcroute = { 826 .ismc_nroutes = 6, 827 .ismc_mcroutes[0] = { 0, 0 }, 828 .ismc_mcroutes[1] = { 0, 1 } 829 } 830 }, 831 .isock_ntad = 1, 832 .isock_tad[0] = { 833 .itad_flags = 0, 834 .itad_nrules = 8, 835 .itad_rules[0] = { 836 .itr_base = 0x0, 837 .itr_limit = 0x80000000, 838 .itr_sock_way = 1, 839 .itr_chan_way = 2, 840 .itr_sock_gran = IMC_TAD_GRAN_64B, 841 .itr_chan_gran = IMC_TAD_GRAN_64B, 842 .itr_ntargets = 4, 843 .itr_targets = { 0, 0, 0, 0 } 844 } 845 }, 846 .isock_nimc = 1, 847 .isock_imcs[0] = { 848 .icn_nchannels = 2, 849 .icn_dimm_type = IMC_DIMM_DDR4, 850 .icn_ecc = B_TRUE, 851 .icn_lockstep = B_FALSE, 852 .icn_closed = B_FALSE, 853 .icn_channels[0] = { 854 .ich_ndimms = 1, 855 .ich_dimms[0] = { 856 .idimm_present = B_TRUE, 857 .idimm_nbanks = 3, 858 .idimm_width = 8, 859 .idimm_density = 2, 860 .idimm_nranks = 2, 861 .idimm_nrows = 14, 862 .idimm_ncolumns = 10, 863 .idimm_size = 0x40000000 864 }, 865 .ich_ntad_offsets = 12, 866 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 867 0, 0 }, 868 .ich_nrankileaves = 4, 869 .ich_rankileaves[0] = { 870 .irle_enabled = B_TRUE, 871 .irle_nways = 1, 872 .irle_nwaysbits = 1, 873 .irle_limit = 0x40000000, 874 .irle_nentries = 8, 875 .irle_entries[0] = { 0x0, 0x0 }, 876 } 877 }, 878 .icn_channels[1] = { 879 .ich_ndimms = 1, 880 .ich_dimms[0] = { 881 .idimm_present = B_TRUE, 882 .idimm_nbanks = 3, 883 .idimm_width = 8, 884 .idimm_density = 2, 885 .idimm_nranks = 2, 886 .idimm_nrows = 14, 887 .idimm_ncolumns = 10, 888 .idimm_size = 0x40000000 889 }, 890 .ich_ntad_offsets = 12, 891 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 892 0, 0 }, 893 .ich_nrankileaves = 4, 894 .ich_rankileaves[0] = { 895 .irle_enabled = B_TRUE, 896 .irle_nways = 1, 897 .irle_nwaysbits = 1, 898 .irle_limit = 0x40000000, 899 .irle_nentries = 8, 900 .irle_entries[0] = { 0x0, 0x0 }, 901 } 902 } 903 } 904 } 905 }; 906 907 /* 908 * This tests a different channel granularity. Note the channel and socket 909 * granulariites match at this point in time to simplify the test. 910 */ 911 static const imc_t imc_skx_256b_gran = { 912 .imc_gen = IMC_GEN_SKYLAKE, 913 .imc_nsockets = 1, 914 .imc_sockets[0] = { 915 .isock_nodeid = 0, 916 .isock_valid = IMC_SOCKET_V_VALID, 917 .isock_sad = { 918 .isad_flags = 0, 919 .isad_valid = IMC_SAD_V_VALID, 920 .isad_tolm = 0x80000000, 921 .isad_tohm = 0, 922 .isad_nrules = 24, 923 .isad_rules[0] = { 924 .isr_enable = B_TRUE, 925 .isr_limit = 0x80000000, 926 .isr_imode = IMC_SAD_IMODE_10t8, 927 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 928 .isr_targets = { 8, 9, 8, 9, 8, 9, 8, 9 } 929 }, 930 .isad_mcroute = { 931 .ismc_nroutes = 6, 932 .ismc_mcroutes[0] = { 0, 0 }, 933 .ismc_mcroutes[1] = { 0, 1 } 934 } 935 }, 936 .isock_ntad = 1, 937 .isock_tad[0] = { 938 .itad_flags = 0, 939 .itad_nrules = 8, 940 .itad_rules[0] = { 941 .itr_base = 0x0, 942 .itr_limit = 0x80000000, 943 .itr_sock_way = 1, 944 .itr_chan_way = 2, 945 .itr_sock_gran = IMC_TAD_GRAN_256B, 946 .itr_chan_gran = IMC_TAD_GRAN_256B, 947 .itr_ntargets = 4, 948 .itr_targets = { 0, 0, 0, 0 } 949 } 950 }, 951 .isock_nimc = 1, 952 .isock_imcs[0] = { 953 .icn_nchannels = 2, 954 .icn_dimm_type = IMC_DIMM_DDR4, 955 .icn_ecc = B_TRUE, 956 .icn_lockstep = B_FALSE, 957 .icn_closed = B_FALSE, 958 .icn_channels[0] = { 959 .ich_ndimms = 1, 960 .ich_dimms[0] = { 961 .idimm_present = B_TRUE, 962 .idimm_nbanks = 3, 963 .idimm_width = 8, 964 .idimm_density = 2, 965 .idimm_nranks = 2, 966 .idimm_nrows = 14, 967 .idimm_ncolumns = 10, 968 .idimm_size = 0x40000000 969 }, 970 .ich_ntad_offsets = 12, 971 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 972 0, 0 }, 973 .ich_nrankileaves = 4, 974 .ich_rankileaves[0] = { 975 .irle_enabled = B_TRUE, 976 .irle_nways = 1, 977 .irle_nwaysbits = 1, 978 .irle_limit = 0x40000000, 979 .irle_nentries = 8, 980 .irle_entries[0] = { 0x0, 0x0 }, 981 } 982 }, 983 .icn_channels[1] = { 984 .ich_ndimms = 1, 985 .ich_dimms[0] = { 986 .idimm_present = B_TRUE, 987 .idimm_nbanks = 3, 988 .idimm_width = 8, 989 .idimm_density = 2, 990 .idimm_nranks = 2, 991 .idimm_nrows = 14, 992 .idimm_ncolumns = 10, 993 .idimm_size = 0x40000000 994 }, 995 .ich_ntad_offsets = 12, 996 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 997 0, 0 }, 998 .ich_nrankileaves = 4, 999 .ich_rankileaves[0] = { 1000 .irle_enabled = B_TRUE, 1001 .irle_nways = 1, 1002 .irle_nwaysbits = 1, 1003 .irle_limit = 0x40000000, 1004 .irle_nentries = 8, 1005 .irle_entries[0] = { 0x0, 0x0 }, 1006 } 1007 } 1008 } 1009 } 1010 }; 1011 1012 /* 1013 * This time, use a 4k granularity. 1014 */ 1015 static const imc_t imc_skx_4k_gran = { 1016 .imc_gen = IMC_GEN_SKYLAKE, 1017 .imc_nsockets = 1, 1018 .imc_sockets[0] = { 1019 .isock_nodeid = 0, 1020 .isock_valid = IMC_SOCKET_V_VALID, 1021 .isock_sad = { 1022 .isad_flags = 0, 1023 .isad_valid = IMC_SAD_V_VALID, 1024 .isad_tolm = 0x80000000, 1025 .isad_tohm = 0, 1026 .isad_nrules = 24, 1027 .isad_rules[0] = { 1028 .isr_enable = B_TRUE, 1029 .isr_limit = 0x80000000, 1030 .isr_imode = IMC_SAD_IMODE_14t12, 1031 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 1032 .isr_targets = { 8, 9, 8, 9, 8, 9, 8, 9 } 1033 }, 1034 .isad_mcroute = { 1035 .ismc_nroutes = 6, 1036 .ismc_mcroutes[0] = { 0, 0 }, 1037 .ismc_mcroutes[1] = { 0, 1 } 1038 } 1039 }, 1040 .isock_ntad = 1, 1041 .isock_tad[0] = { 1042 .itad_flags = 0, 1043 .itad_nrules = 8, 1044 .itad_rules[0] = { 1045 .itr_base = 0x0, 1046 .itr_limit = 0x80000000, 1047 .itr_sock_way = 1, 1048 .itr_chan_way = 2, 1049 .itr_sock_gran = IMC_TAD_GRAN_4KB, 1050 .itr_chan_gran = IMC_TAD_GRAN_4KB, 1051 .itr_ntargets = 4, 1052 .itr_targets = { 0, 0, 0, 0 } 1053 } 1054 }, 1055 .isock_nimc = 1, 1056 .isock_imcs[0] = { 1057 .icn_nchannels = 2, 1058 .icn_dimm_type = IMC_DIMM_DDR4, 1059 .icn_ecc = B_TRUE, 1060 .icn_lockstep = B_FALSE, 1061 .icn_closed = B_FALSE, 1062 .icn_channels[0] = { 1063 .ich_ndimms = 1, 1064 .ich_dimms[0] = { 1065 .idimm_present = B_TRUE, 1066 .idimm_nbanks = 3, 1067 .idimm_width = 8, 1068 .idimm_density = 2, 1069 .idimm_nranks = 2, 1070 .idimm_nrows = 14, 1071 .idimm_ncolumns = 10, 1072 .idimm_size = 0x40000000 1073 }, 1074 .ich_ntad_offsets = 12, 1075 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1076 0, 0 }, 1077 .ich_nrankileaves = 4, 1078 .ich_rankileaves[0] = { 1079 .irle_enabled = B_TRUE, 1080 .irle_nways = 1, 1081 .irle_nwaysbits = 1, 1082 .irle_limit = 0x40000000, 1083 .irle_nentries = 8, 1084 .irle_entries[0] = { 0x0, 0x0 }, 1085 } 1086 }, 1087 .icn_channels[1] = { 1088 .ich_ndimms = 1, 1089 .ich_dimms[0] = { 1090 .idimm_present = B_TRUE, 1091 .idimm_nbanks = 3, 1092 .idimm_width = 8, 1093 .idimm_density = 2, 1094 .idimm_nranks = 2, 1095 .idimm_nrows = 14, 1096 .idimm_ncolumns = 10, 1097 .idimm_size = 0x40000000 1098 }, 1099 .ich_ntad_offsets = 12, 1100 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1101 0, 0 }, 1102 .ich_nrankileaves = 4, 1103 .ich_rankileaves[0] = { 1104 .irle_enabled = B_TRUE, 1105 .irle_nways = 1, 1106 .irle_nwaysbits = 1, 1107 .irle_limit = 0x40000000, 1108 .irle_nentries = 8, 1109 .irle_entries[0] = { 0x0, 0x0 }, 1110 } 1111 } 1112 } 1113 } 1114 }; 1115 1116 /* 1117 * Once more, with 1 GiB granularity. 1118 */ 1119 static const imc_t imc_skx_1g_gran = { 1120 .imc_gen = IMC_GEN_SKYLAKE, 1121 .imc_nsockets = 1, 1122 .imc_sockets[0] = { 1123 .isock_nodeid = 0, 1124 .isock_valid = IMC_SOCKET_V_VALID, 1125 .isock_sad = { 1126 .isad_flags = 0, 1127 .isad_valid = IMC_SAD_V_VALID, 1128 .isad_tolm = 0x80000000, 1129 .isad_tohm = 0, 1130 .isad_nrules = 24, 1131 .isad_rules[0] = { 1132 .isr_enable = B_TRUE, 1133 .isr_limit = 0x80000000, 1134 .isr_imode = IMC_SAD_IMODE_32t30, 1135 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 1136 .isr_targets = { 8, 9, 8, 9, 8, 9, 8, 9 } 1137 }, 1138 .isad_mcroute = { 1139 .ismc_nroutes = 6, 1140 .ismc_mcroutes[0] = { 0, 0 }, 1141 .ismc_mcroutes[1] = { 0, 1 } 1142 } 1143 }, 1144 .isock_ntad = 1, 1145 .isock_tad[0] = { 1146 .itad_flags = 0, 1147 .itad_nrules = 8, 1148 .itad_rules[0] = { 1149 .itr_base = 0x0, 1150 .itr_limit = 0x80000000, 1151 .itr_sock_way = 1, 1152 .itr_chan_way = 2, 1153 .itr_sock_gran = IMC_TAD_GRAN_1GB, 1154 .itr_chan_gran = IMC_TAD_GRAN_1GB, 1155 .itr_ntargets = 4, 1156 .itr_targets = { 0, 0, 0, 0 } 1157 } 1158 }, 1159 .isock_nimc = 1, 1160 .isock_imcs[0] = { 1161 .icn_nchannels = 2, 1162 .icn_dimm_type = IMC_DIMM_DDR4, 1163 .icn_ecc = B_TRUE, 1164 .icn_lockstep = B_FALSE, 1165 .icn_closed = B_FALSE, 1166 .icn_channels[0] = { 1167 .ich_ndimms = 1, 1168 .ich_dimms[0] = { 1169 .idimm_present = B_TRUE, 1170 .idimm_nbanks = 3, 1171 .idimm_width = 8, 1172 .idimm_density = 2, 1173 .idimm_nranks = 2, 1174 .idimm_nrows = 14, 1175 .idimm_ncolumns = 10, 1176 .idimm_size = 0x40000000 1177 }, 1178 .ich_ntad_offsets = 12, 1179 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1180 0, 0 }, 1181 .ich_nrankileaves = 4, 1182 .ich_rankileaves[0] = { 1183 .irle_enabled = B_TRUE, 1184 .irle_nways = 1, 1185 .irle_nwaysbits = 1, 1186 .irle_limit = 0x40000000, 1187 .irle_nentries = 8, 1188 .irle_entries[0] = { 0x0, 0x0 }, 1189 } 1190 }, 1191 .icn_channels[1] = { 1192 .ich_ndimms = 1, 1193 .ich_dimms[0] = { 1194 .idimm_present = B_TRUE, 1195 .idimm_nbanks = 3, 1196 .idimm_width = 8, 1197 .idimm_density = 2, 1198 .idimm_nranks = 2, 1199 .idimm_nrows = 14, 1200 .idimm_ncolumns = 10, 1201 .idimm_size = 0x40000000 1202 }, 1203 .ich_ntad_offsets = 12, 1204 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1205 0, 0 }, 1206 .ich_nrankileaves = 4, 1207 .ich_rankileaves[0] = { 1208 .irle_enabled = B_TRUE, 1209 .irle_nways = 1, 1210 .irle_nwaysbits = 1, 1211 .irle_limit = 0x40000000, 1212 .irle_nentries = 8, 1213 .irle_entries[0] = { 0x0, 0x0 }, 1214 } 1215 } 1216 } 1217 } 1218 }; 1219 1220 /* 1221 * This tests a 1 socket, 4 channel-way configuration. 1222 */ 1223 static const imc_t imc_tad_1s_4cw = { 1224 .imc_gen = IMC_GEN_SKYLAKE, 1225 .imc_nsockets = 1, 1226 .imc_sockets[0] = { 1227 .isock_nodeid = 0, 1228 .isock_valid = IMC_SOCKET_V_VALID, 1229 .isock_sad = { 1230 .isad_flags = 0, 1231 .isad_valid = IMC_SAD_V_VALID, 1232 .isad_tolm = 0x100000000ULL, 1233 .isad_tohm = 0, 1234 .isad_nrules = 24, 1235 .isad_rules[0] = { 1236 .isr_enable = B_TRUE, 1237 .isr_limit = 0x100000000ULL, 1238 .isr_imode = IMC_SAD_IMODE_8t6, 1239 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 1240 .isr_targets = { 8, 9, 0xa, 0xb, 8, 9, 0xa, 1241 0xb } 1242 }, 1243 .isad_mcroute = { 1244 .ismc_nroutes = 6, 1245 .ismc_mcroutes[0] = { 0, 0 }, 1246 .ismc_mcroutes[1] = { 0, 1 }, 1247 .ismc_mcroutes[2] = { 1, 1 }, 1248 .ismc_mcroutes[3] = { 1, 0 } 1249 } 1250 }, 1251 .isock_ntad = 2, 1252 .isock_tad[0] = { 1253 .itad_flags = 0, 1254 .itad_nrules = 8, 1255 .itad_rules[0] = { 1256 .itr_base = 0x0, 1257 .itr_limit = 0x100000000ULL, 1258 .itr_sock_way = 1, 1259 .itr_chan_way = 4, 1260 .itr_sock_gran = IMC_TAD_GRAN_64B, 1261 .itr_chan_gran = IMC_TAD_GRAN_64B, 1262 .itr_ntargets = 4, 1263 .itr_targets = { 0, 0, 0, 0 } 1264 } 1265 }, 1266 .isock_tad[1] = { 1267 .itad_flags = 0, 1268 .itad_nrules = 8, 1269 .itad_rules[0] = { 1270 .itr_base = 0x0, 1271 .itr_limit = 0x100000000ULL, 1272 .itr_sock_way = 1, 1273 .itr_chan_way = 4, 1274 .itr_sock_gran = IMC_TAD_GRAN_64B, 1275 .itr_chan_gran = IMC_TAD_GRAN_64B, 1276 .itr_ntargets = 4, 1277 .itr_targets = { 0, 0, 0, 0 } 1278 } 1279 }, 1280 .isock_nimc = 2, 1281 .isock_imcs[0] = { 1282 .icn_nchannels = 2, 1283 .icn_dimm_type = IMC_DIMM_DDR4, 1284 .icn_ecc = B_TRUE, 1285 .icn_lockstep = B_FALSE, 1286 .icn_closed = B_FALSE, 1287 .icn_channels[0] = { 1288 .ich_ndimms = 1, 1289 .ich_dimms[0] = { 1290 .idimm_present = B_TRUE, 1291 .idimm_nbanks = 3, 1292 .idimm_width = 8, 1293 .idimm_density = 2, 1294 .idimm_nranks = 2, 1295 .idimm_nrows = 14, 1296 .idimm_ncolumns = 10, 1297 .idimm_size = 0x40000000 1298 }, 1299 .ich_ntad_offsets = 12, 1300 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1301 0, 0 }, 1302 .ich_nrankileaves = 4, 1303 .ich_rankileaves[0] = { 1304 .irle_enabled = B_TRUE, 1305 .irle_nways = 1, 1306 .irle_nwaysbits = 1, 1307 .irle_limit = 0x40000000, 1308 .irle_nentries = 8, 1309 .irle_entries[0] = { 0x0, 0x0 }, 1310 } 1311 }, 1312 .icn_channels[1] = { 1313 .ich_ndimms = 1, 1314 .ich_dimms[0] = { 1315 .idimm_present = B_TRUE, 1316 .idimm_nbanks = 3, 1317 .idimm_width = 8, 1318 .idimm_density = 2, 1319 .idimm_nranks = 2, 1320 .idimm_nrows = 14, 1321 .idimm_ncolumns = 10, 1322 .idimm_size = 0x40000000 1323 }, 1324 .ich_ntad_offsets = 12, 1325 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1326 0, 0 }, 1327 .ich_nrankileaves = 4, 1328 .ich_rankileaves[0] = { 1329 .irle_enabled = B_TRUE, 1330 .irle_nways = 1, 1331 .irle_nwaysbits = 1, 1332 .irle_limit = 0x40000000, 1333 .irle_nentries = 8, 1334 .irle_entries[0] = { 0x0, 0x0 }, 1335 } 1336 } 1337 }, 1338 .isock_imcs[1] = { 1339 .icn_nchannels = 2, 1340 .icn_dimm_type = IMC_DIMM_DDR4, 1341 .icn_ecc = B_TRUE, 1342 .icn_lockstep = B_FALSE, 1343 .icn_closed = B_FALSE, 1344 .icn_channels[0] = { 1345 .ich_ndimms = 1, 1346 .ich_dimms[0] = { 1347 .idimm_present = B_TRUE, 1348 .idimm_nbanks = 3, 1349 .idimm_width = 8, 1350 .idimm_density = 2, 1351 .idimm_nranks = 2, 1352 .idimm_nrows = 14, 1353 .idimm_ncolumns = 10, 1354 .idimm_size = 0x40000000 1355 }, 1356 .ich_ntad_offsets = 12, 1357 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1358 0, 0 }, 1359 .ich_nrankileaves = 4, 1360 .ich_rankileaves[0] = { 1361 .irle_enabled = B_TRUE, 1362 .irle_nways = 1, 1363 .irle_nwaysbits = 1, 1364 .irle_limit = 0x40000000, 1365 .irle_nentries = 8, 1366 .irle_entries[0] = { 0x0, 0x0 }, 1367 } 1368 }, 1369 .icn_channels[1] = { 1370 .ich_ndimms = 1, 1371 .ich_dimms[0] = { 1372 .idimm_present = B_TRUE, 1373 .idimm_nbanks = 3, 1374 .idimm_width = 8, 1375 .idimm_density = 2, 1376 .idimm_nranks = 2, 1377 .idimm_nrows = 14, 1378 .idimm_ncolumns = 10, 1379 .idimm_size = 0x40000000 1380 }, 1381 .ich_ntad_offsets = 12, 1382 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1383 0, 0 }, 1384 .ich_nrankileaves = 4, 1385 .ich_rankileaves[0] = { 1386 .irle_enabled = B_TRUE, 1387 .irle_nways = 1, 1388 .irle_nwaysbits = 1, 1389 .irle_limit = 0x40000000, 1390 .irle_nentries = 8, 1391 .irle_entries[0] = { 0x0, 0x0 }, 1392 } 1393 } 1394 } 1395 } 1396 }; 1397 1398 /* 1399 * A variant on 1imc_tad_1s_4cw that uses Skylake mod3 rules to change how the 1400 * target channel is determined. While we have six channels here, technically 1401 * this configuration has wasted memory. This is on purpose to simplify the 1402 * rules below. 1403 */ 1404 static const imc_t imc_tad_skx_mod3_45t6 = { 1405 .imc_gen = IMC_GEN_SKYLAKE, 1406 .imc_nsockets = 1, 1407 .imc_sockets[0] = { 1408 .isock_nodeid = 0, 1409 .isock_valid = IMC_SOCKET_V_VALID, 1410 .isock_sad = { 1411 .isad_flags = 0, 1412 .isad_valid = IMC_SAD_V_VALID, 1413 .isad_tolm = 0x100000000ULL, 1414 .isad_tohm = 0, 1415 .isad_nrules = 24, 1416 .isad_rules[0] = { 1417 .isr_enable = B_TRUE, 1418 .isr_limit = 0x100000000ULL, 1419 .isr_imode = IMC_SAD_IMODE_8t6, 1420 .isr_need_mod3 = B_TRUE, 1421 .isr_mod_mode = IMC_SAD_MOD_MODE_45t6, 1422 .isr_mod_type = IMC_SAD_MOD_TYPE_MOD3, 1423 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 1424 .isr_targets = { 8, 9, 0xa, 0xb, 8, 9, 0xa, 1425 0xb } 1426 }, 1427 .isad_mcroute = { 1428 .ismc_nroutes = 6, 1429 .ismc_mcroutes[0] = { 0, 0 }, 1430 .ismc_mcroutes[1] = { 0, 1 }, 1431 .ismc_mcroutes[2] = { 0, 2 }, 1432 .ismc_mcroutes[3] = { 1, 2 }, 1433 .ismc_mcroutes[4] = { 1, 1 }, 1434 .ismc_mcroutes[5] = { 1, 0 } 1435 } 1436 }, 1437 .isock_ntad = 2, 1438 .isock_tad[0] = { 1439 .itad_flags = 0, 1440 .itad_nrules = 8, 1441 .itad_rules[0] = { 1442 .itr_base = 0x0, 1443 .itr_limit = 0x100000000ULL, 1444 .itr_sock_way = 1, 1445 .itr_chan_way = 4, 1446 .itr_sock_gran = IMC_TAD_GRAN_64B, 1447 .itr_chan_gran = IMC_TAD_GRAN_64B, 1448 .itr_ntargets = 4, 1449 .itr_targets = { 0, 0, 0, 0 } 1450 } 1451 }, 1452 .isock_tad[1] = { 1453 .itad_flags = 0, 1454 .itad_nrules = 8, 1455 .itad_rules[0] = { 1456 .itr_base = 0x0, 1457 .itr_limit = 0x100000000ULL, 1458 .itr_sock_way = 1, 1459 .itr_chan_way = 4, 1460 .itr_sock_gran = IMC_TAD_GRAN_64B, 1461 .itr_chan_gran = IMC_TAD_GRAN_64B, 1462 .itr_ntargets = 4, 1463 .itr_targets = { 0, 0, 0, 0 } 1464 } 1465 }, 1466 .isock_nimc = 2, 1467 .isock_imcs[0] = { 1468 .icn_nchannels = 3, 1469 .icn_dimm_type = IMC_DIMM_DDR4, 1470 .icn_ecc = B_TRUE, 1471 .icn_lockstep = B_FALSE, 1472 .icn_closed = B_FALSE, 1473 .icn_channels[0] = { 1474 .ich_ndimms = 1, 1475 .ich_dimms[0] = { 1476 .idimm_present = B_TRUE, 1477 .idimm_nbanks = 3, 1478 .idimm_width = 8, 1479 .idimm_density = 2, 1480 .idimm_nranks = 2, 1481 .idimm_nrows = 14, 1482 .idimm_ncolumns = 10, 1483 .idimm_size = 0x40000000 1484 }, 1485 .ich_ntad_offsets = 12, 1486 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1487 0, 0 }, 1488 .ich_nrankileaves = 4, 1489 .ich_rankileaves[0] = { 1490 .irle_enabled = B_TRUE, 1491 .irle_nways = 1, 1492 .irle_nwaysbits = 1, 1493 .irle_limit = 0x40000000, 1494 .irle_nentries = 8, 1495 .irle_entries[0] = { 0x0, 0x0 }, 1496 } 1497 }, 1498 .icn_channels[1] = { 1499 .ich_ndimms = 1, 1500 .ich_dimms[0] = { 1501 .idimm_present = B_TRUE, 1502 .idimm_nbanks = 3, 1503 .idimm_width = 8, 1504 .idimm_density = 2, 1505 .idimm_nranks = 2, 1506 .idimm_nrows = 14, 1507 .idimm_ncolumns = 10, 1508 .idimm_size = 0x40000000 1509 }, 1510 .ich_ntad_offsets = 12, 1511 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1512 0, 0 }, 1513 .ich_nrankileaves = 4, 1514 .ich_rankileaves[0] = { 1515 .irle_enabled = B_TRUE, 1516 .irle_nways = 1, 1517 .irle_nwaysbits = 1, 1518 .irle_limit = 0x40000000, 1519 .irle_nentries = 8, 1520 .irle_entries[0] = { 0x0, 0x0 }, 1521 } 1522 }, 1523 .icn_channels[2] = { 1524 .ich_ndimms = 1, 1525 .ich_dimms[0] = { 1526 .idimm_present = B_TRUE, 1527 .idimm_nbanks = 3, 1528 .idimm_width = 8, 1529 .idimm_density = 2, 1530 .idimm_nranks = 2, 1531 .idimm_nrows = 14, 1532 .idimm_ncolumns = 10, 1533 .idimm_size = 0x40000000 1534 }, 1535 .ich_ntad_offsets = 12, 1536 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1537 0, 0 }, 1538 .ich_nrankileaves = 4, 1539 .ich_rankileaves[0] = { 1540 .irle_enabled = B_TRUE, 1541 .irle_nways = 1, 1542 .irle_nwaysbits = 1, 1543 .irle_limit = 0x40000000, 1544 .irle_nentries = 8, 1545 .irle_entries[0] = { 0x0, 0x0 }, 1546 } 1547 } 1548 }, 1549 .isock_imcs[1] = { 1550 .icn_nchannels = 3, 1551 .icn_dimm_type = IMC_DIMM_DDR4, 1552 .icn_ecc = B_TRUE, 1553 .icn_lockstep = B_FALSE, 1554 .icn_closed = B_FALSE, 1555 .icn_channels[0] = { 1556 .ich_ndimms = 1, 1557 .ich_dimms[0] = { 1558 .idimm_present = B_TRUE, 1559 .idimm_nbanks = 3, 1560 .idimm_width = 8, 1561 .idimm_density = 2, 1562 .idimm_nranks = 2, 1563 .idimm_nrows = 14, 1564 .idimm_ncolumns = 10, 1565 .idimm_size = 0x40000000 1566 }, 1567 .ich_ntad_offsets = 12, 1568 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1569 0, 0 }, 1570 .ich_nrankileaves = 4, 1571 .ich_rankileaves[0] = { 1572 .irle_enabled = B_TRUE, 1573 .irle_nways = 1, 1574 .irle_nwaysbits = 1, 1575 .irle_limit = 0x40000000, 1576 .irle_nentries = 8, 1577 .irle_entries[0] = { 0x0, 0x0 }, 1578 } 1579 }, 1580 .icn_channels[1] = { 1581 .ich_ndimms = 1, 1582 .ich_dimms[0] = { 1583 .idimm_present = B_TRUE, 1584 .idimm_nbanks = 3, 1585 .idimm_width = 8, 1586 .idimm_density = 2, 1587 .idimm_nranks = 2, 1588 .idimm_nrows = 14, 1589 .idimm_ncolumns = 10, 1590 .idimm_size = 0x40000000 1591 }, 1592 .ich_ntad_offsets = 12, 1593 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1594 0, 0 }, 1595 .ich_nrankileaves = 4, 1596 .ich_rankileaves[0] = { 1597 .irle_enabled = B_TRUE, 1598 .irle_nways = 1, 1599 .irle_nwaysbits = 1, 1600 .irle_limit = 0x40000000, 1601 .irle_nentries = 8, 1602 .irle_entries[0] = { 0x0, 0x0 }, 1603 } 1604 }, 1605 .icn_channels[2] = { 1606 .ich_ndimms = 1, 1607 .ich_dimms[0] = { 1608 .idimm_present = B_TRUE, 1609 .idimm_nbanks = 3, 1610 .idimm_width = 8, 1611 .idimm_density = 2, 1612 .idimm_nranks = 2, 1613 .idimm_nrows = 14, 1614 .idimm_ncolumns = 10, 1615 .idimm_size = 0x40000000 1616 }, 1617 .ich_ntad_offsets = 12, 1618 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1619 0, 0 }, 1620 .ich_nrankileaves = 4, 1621 .ich_rankileaves[0] = { 1622 .irle_enabled = B_TRUE, 1623 .irle_nways = 1, 1624 .irle_nwaysbits = 1, 1625 .irle_limit = 0x40000000, 1626 .irle_nentries = 8, 1627 .irle_entries[0] = { 0x0, 0x0 }, 1628 } 1629 } 1630 } 1631 } 1632 }; 1633 1634 /* 1635 * A variant on imc_tad_skx_mod3_45t6, but here we test the 45t8 mod variant. 1636 */ 1637 static const imc_t imc_tad_skx_mod3_45t8 = { 1638 .imc_gen = IMC_GEN_SKYLAKE, 1639 .imc_nsockets = 1, 1640 .imc_sockets[0] = { 1641 .isock_nodeid = 0, 1642 .isock_valid = IMC_SOCKET_V_VALID, 1643 .isock_sad = { 1644 .isad_flags = 0, 1645 .isad_valid = IMC_SAD_V_VALID, 1646 .isad_tolm = 0x100000000ULL, 1647 .isad_tohm = 0, 1648 .isad_nrules = 24, 1649 .isad_rules[0] = { 1650 .isr_enable = B_TRUE, 1651 .isr_limit = 0x100000000ULL, 1652 .isr_imode = IMC_SAD_IMODE_8t6, 1653 .isr_need_mod3 = B_TRUE, 1654 .isr_mod_mode = IMC_SAD_MOD_MODE_45t8, 1655 .isr_mod_type = IMC_SAD_MOD_TYPE_MOD3, 1656 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 1657 .isr_targets = { 8, 9, 0xa, 0xb, 8, 9, 0xa, 1658 0xb } 1659 }, 1660 .isad_mcroute = { 1661 .ismc_nroutes = 6, 1662 .ismc_mcroutes[0] = { 0, 0 }, 1663 .ismc_mcroutes[1] = { 0, 1 }, 1664 .ismc_mcroutes[2] = { 0, 2 }, 1665 .ismc_mcroutes[3] = { 1, 2 }, 1666 .ismc_mcroutes[4] = { 1, 1 }, 1667 .ismc_mcroutes[5] = { 1, 0 } 1668 } 1669 }, 1670 .isock_ntad = 2, 1671 .isock_tad[0] = { 1672 .itad_flags = 0, 1673 .itad_nrules = 8, 1674 .itad_rules[0] = { 1675 .itr_base = 0x0, 1676 .itr_limit = 0x100000000ULL, 1677 .itr_sock_way = 1, 1678 .itr_chan_way = 4, 1679 .itr_sock_gran = IMC_TAD_GRAN_64B, 1680 .itr_chan_gran = IMC_TAD_GRAN_64B, 1681 .itr_ntargets = 4, 1682 .itr_targets = { 0, 0, 0, 0 } 1683 } 1684 }, 1685 .isock_tad[1] = { 1686 .itad_flags = 0, 1687 .itad_nrules = 8, 1688 .itad_rules[0] = { 1689 .itr_base = 0x0, 1690 .itr_limit = 0x100000000ULL, 1691 .itr_sock_way = 1, 1692 .itr_chan_way = 4, 1693 .itr_sock_gran = IMC_TAD_GRAN_64B, 1694 .itr_chan_gran = IMC_TAD_GRAN_64B, 1695 .itr_ntargets = 4, 1696 .itr_targets = { 0, 0, 0, 0 } 1697 } 1698 }, 1699 .isock_nimc = 2, 1700 .isock_imcs[0] = { 1701 .icn_nchannels = 3, 1702 .icn_dimm_type = IMC_DIMM_DDR4, 1703 .icn_ecc = B_TRUE, 1704 .icn_lockstep = B_FALSE, 1705 .icn_closed = B_FALSE, 1706 .icn_channels[0] = { 1707 .ich_ndimms = 1, 1708 .ich_dimms[0] = { 1709 .idimm_present = B_TRUE, 1710 .idimm_nbanks = 3, 1711 .idimm_width = 8, 1712 .idimm_density = 2, 1713 .idimm_nranks = 2, 1714 .idimm_nrows = 14, 1715 .idimm_ncolumns = 10, 1716 .idimm_size = 0x40000000 1717 }, 1718 .ich_ntad_offsets = 12, 1719 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1720 0, 0 }, 1721 .ich_nrankileaves = 4, 1722 .ich_rankileaves[0] = { 1723 .irle_enabled = B_TRUE, 1724 .irle_nways = 1, 1725 .irle_nwaysbits = 1, 1726 .irle_limit = 0x40000000, 1727 .irle_nentries = 8, 1728 .irle_entries[0] = { 0x0, 0x0 }, 1729 } 1730 }, 1731 .icn_channels[1] = { 1732 .ich_ndimms = 1, 1733 .ich_dimms[0] = { 1734 .idimm_present = B_TRUE, 1735 .idimm_nbanks = 3, 1736 .idimm_width = 8, 1737 .idimm_density = 2, 1738 .idimm_nranks = 2, 1739 .idimm_nrows = 14, 1740 .idimm_ncolumns = 10, 1741 .idimm_size = 0x40000000 1742 }, 1743 .ich_ntad_offsets = 12, 1744 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1745 0, 0 }, 1746 .ich_nrankileaves = 4, 1747 .ich_rankileaves[0] = { 1748 .irle_enabled = B_TRUE, 1749 .irle_nways = 1, 1750 .irle_nwaysbits = 1, 1751 .irle_limit = 0x40000000, 1752 .irle_nentries = 8, 1753 .irle_entries[0] = { 0x0, 0x0 }, 1754 } 1755 }, 1756 .icn_channels[2] = { 1757 .ich_ndimms = 1, 1758 .ich_dimms[0] = { 1759 .idimm_present = B_TRUE, 1760 .idimm_nbanks = 3, 1761 .idimm_width = 8, 1762 .idimm_density = 2, 1763 .idimm_nranks = 2, 1764 .idimm_nrows = 14, 1765 .idimm_ncolumns = 10, 1766 .idimm_size = 0x40000000 1767 }, 1768 .ich_ntad_offsets = 12, 1769 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1770 0, 0 }, 1771 .ich_nrankileaves = 4, 1772 .ich_rankileaves[0] = { 1773 .irle_enabled = B_TRUE, 1774 .irle_nways = 1, 1775 .irle_nwaysbits = 1, 1776 .irle_limit = 0x40000000, 1777 .irle_nentries = 8, 1778 .irle_entries[0] = { 0x0, 0x0 }, 1779 } 1780 } 1781 }, 1782 .isock_imcs[1] = { 1783 .icn_nchannels = 3, 1784 .icn_dimm_type = IMC_DIMM_DDR4, 1785 .icn_ecc = B_TRUE, 1786 .icn_lockstep = B_FALSE, 1787 .icn_closed = B_FALSE, 1788 .icn_channels[0] = { 1789 .ich_ndimms = 1, 1790 .ich_dimms[0] = { 1791 .idimm_present = B_TRUE, 1792 .idimm_nbanks = 3, 1793 .idimm_width = 8, 1794 .idimm_density = 2, 1795 .idimm_nranks = 2, 1796 .idimm_nrows = 14, 1797 .idimm_ncolumns = 10, 1798 .idimm_size = 0x40000000 1799 }, 1800 .ich_ntad_offsets = 12, 1801 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1802 0, 0 }, 1803 .ich_nrankileaves = 4, 1804 .ich_rankileaves[0] = { 1805 .irle_enabled = B_TRUE, 1806 .irle_nways = 1, 1807 .irle_nwaysbits = 1, 1808 .irle_limit = 0x40000000, 1809 .irle_nentries = 8, 1810 .irle_entries[0] = { 0x0, 0x0 }, 1811 } 1812 }, 1813 .icn_channels[1] = { 1814 .ich_ndimms = 1, 1815 .ich_dimms[0] = { 1816 .idimm_present = B_TRUE, 1817 .idimm_nbanks = 3, 1818 .idimm_width = 8, 1819 .idimm_density = 2, 1820 .idimm_nranks = 2, 1821 .idimm_nrows = 14, 1822 .idimm_ncolumns = 10, 1823 .idimm_size = 0x40000000 1824 }, 1825 .ich_ntad_offsets = 12, 1826 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1827 0, 0 }, 1828 .ich_nrankileaves = 4, 1829 .ich_rankileaves[0] = { 1830 .irle_enabled = B_TRUE, 1831 .irle_nways = 1, 1832 .irle_nwaysbits = 1, 1833 .irle_limit = 0x40000000, 1834 .irle_nentries = 8, 1835 .irle_entries[0] = { 0x0, 0x0 }, 1836 } 1837 }, 1838 .icn_channels[2] = { 1839 .ich_ndimms = 1, 1840 .ich_dimms[0] = { 1841 .idimm_present = B_TRUE, 1842 .idimm_nbanks = 3, 1843 .idimm_width = 8, 1844 .idimm_density = 2, 1845 .idimm_nranks = 2, 1846 .idimm_nrows = 14, 1847 .idimm_ncolumns = 10, 1848 .idimm_size = 0x40000000 1849 }, 1850 .ich_ntad_offsets = 12, 1851 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1852 0, 0 }, 1853 .ich_nrankileaves = 4, 1854 .ich_rankileaves[0] = { 1855 .irle_enabled = B_TRUE, 1856 .irle_nways = 1, 1857 .irle_nwaysbits = 1, 1858 .irle_limit = 0x40000000, 1859 .irle_nentries = 8, 1860 .irle_entries[0] = { 0x0, 0x0 }, 1861 } 1862 } 1863 } 1864 } 1865 }; 1866 1867 /* 1868 * A variant on imc_tad_skx_mod3_45t6, but here we test the 45t12 mod variant. 1869 */ 1870 static const imc_t imc_tad_skx_mod3_45t12 = { 1871 .imc_gen = IMC_GEN_SKYLAKE, 1872 .imc_nsockets = 1, 1873 .imc_sockets[0] = { 1874 .isock_nodeid = 0, 1875 .isock_valid = IMC_SOCKET_V_VALID, 1876 .isock_sad = { 1877 .isad_flags = 0, 1878 .isad_valid = IMC_SAD_V_VALID, 1879 .isad_tolm = 0x100000000ULL, 1880 .isad_tohm = 0, 1881 .isad_nrules = 24, 1882 .isad_rules[0] = { 1883 .isr_enable = B_TRUE, 1884 .isr_limit = 0x100000000ULL, 1885 .isr_imode = IMC_SAD_IMODE_8t6, 1886 .isr_need_mod3 = B_TRUE, 1887 .isr_mod_mode = IMC_SAD_MOD_MODE_45t12, 1888 .isr_mod_type = IMC_SAD_MOD_TYPE_MOD3, 1889 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 1890 .isr_targets = { 8, 9, 0xa, 0xb, 8, 9, 0xa, 1891 0xb } 1892 }, 1893 .isad_mcroute = { 1894 .ismc_nroutes = 6, 1895 .ismc_mcroutes[0] = { 0, 0 }, 1896 .ismc_mcroutes[1] = { 0, 1 }, 1897 .ismc_mcroutes[2] = { 0, 2 }, 1898 .ismc_mcroutes[3] = { 1, 2 }, 1899 .ismc_mcroutes[4] = { 1, 1 }, 1900 .ismc_mcroutes[5] = { 1, 0 } 1901 } 1902 }, 1903 .isock_ntad = 2, 1904 .isock_tad[0] = { 1905 .itad_flags = 0, 1906 .itad_nrules = 8, 1907 .itad_rules[0] = { 1908 .itr_base = 0x0, 1909 .itr_limit = 0x100000000ULL, 1910 .itr_sock_way = 1, 1911 .itr_chan_way = 4, 1912 .itr_sock_gran = IMC_TAD_GRAN_64B, 1913 .itr_chan_gran = IMC_TAD_GRAN_64B, 1914 .itr_ntargets = 4, 1915 .itr_targets = { 0, 0, 0, 0 } 1916 } 1917 }, 1918 .isock_tad[1] = { 1919 .itad_flags = 0, 1920 .itad_nrules = 8, 1921 .itad_rules[0] = { 1922 .itr_base = 0x0, 1923 .itr_limit = 0x100000000ULL, 1924 .itr_sock_way = 1, 1925 .itr_chan_way = 4, 1926 .itr_sock_gran = IMC_TAD_GRAN_64B, 1927 .itr_chan_gran = IMC_TAD_GRAN_64B, 1928 .itr_ntargets = 4, 1929 .itr_targets = { 0, 0, 0, 0 } 1930 } 1931 }, 1932 .isock_nimc = 2, 1933 .isock_imcs[0] = { 1934 .icn_nchannels = 3, 1935 .icn_dimm_type = IMC_DIMM_DDR4, 1936 .icn_ecc = B_TRUE, 1937 .icn_lockstep = B_FALSE, 1938 .icn_closed = B_FALSE, 1939 .icn_channels[0] = { 1940 .ich_ndimms = 1, 1941 .ich_dimms[0] = { 1942 .idimm_present = B_TRUE, 1943 .idimm_nbanks = 3, 1944 .idimm_width = 8, 1945 .idimm_density = 2, 1946 .idimm_nranks = 2, 1947 .idimm_nrows = 14, 1948 .idimm_ncolumns = 10, 1949 .idimm_size = 0x40000000 1950 }, 1951 .ich_ntad_offsets = 12, 1952 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1953 0, 0 }, 1954 .ich_nrankileaves = 4, 1955 .ich_rankileaves[0] = { 1956 .irle_enabled = B_TRUE, 1957 .irle_nways = 1, 1958 .irle_nwaysbits = 1, 1959 .irle_limit = 0x40000000, 1960 .irle_nentries = 8, 1961 .irle_entries[0] = { 0x0, 0x0 }, 1962 } 1963 }, 1964 .icn_channels[1] = { 1965 .ich_ndimms = 1, 1966 .ich_dimms[0] = { 1967 .idimm_present = B_TRUE, 1968 .idimm_nbanks = 3, 1969 .idimm_width = 8, 1970 .idimm_density = 2, 1971 .idimm_nranks = 2, 1972 .idimm_nrows = 14, 1973 .idimm_ncolumns = 10, 1974 .idimm_size = 0x40000000 1975 }, 1976 .ich_ntad_offsets = 12, 1977 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1978 0, 0 }, 1979 .ich_nrankileaves = 4, 1980 .ich_rankileaves[0] = { 1981 .irle_enabled = B_TRUE, 1982 .irle_nways = 1, 1983 .irle_nwaysbits = 1, 1984 .irle_limit = 0x40000000, 1985 .irle_nentries = 8, 1986 .irle_entries[0] = { 0x0, 0x0 }, 1987 } 1988 }, 1989 .icn_channels[2] = { 1990 .ich_ndimms = 1, 1991 .ich_dimms[0] = { 1992 .idimm_present = B_TRUE, 1993 .idimm_nbanks = 3, 1994 .idimm_width = 8, 1995 .idimm_density = 2, 1996 .idimm_nranks = 2, 1997 .idimm_nrows = 14, 1998 .idimm_ncolumns = 10, 1999 .idimm_size = 0x40000000 2000 }, 2001 .ich_ntad_offsets = 12, 2002 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 2003 0, 0 }, 2004 .ich_nrankileaves = 4, 2005 .ich_rankileaves[0] = { 2006 .irle_enabled = B_TRUE, 2007 .irle_nways = 1, 2008 .irle_nwaysbits = 1, 2009 .irle_limit = 0x40000000, 2010 .irle_nentries = 8, 2011 .irle_entries[0] = { 0x0, 0x0 }, 2012 } 2013 } 2014 }, 2015 .isock_imcs[1] = { 2016 .icn_nchannels = 3, 2017 .icn_dimm_type = IMC_DIMM_DDR4, 2018 .icn_ecc = B_TRUE, 2019 .icn_lockstep = B_FALSE, 2020 .icn_closed = B_FALSE, 2021 .icn_channels[0] = { 2022 .ich_ndimms = 1, 2023 .ich_dimms[0] = { 2024 .idimm_present = B_TRUE, 2025 .idimm_nbanks = 3, 2026 .idimm_width = 8, 2027 .idimm_density = 2, 2028 .idimm_nranks = 2, 2029 .idimm_nrows = 14, 2030 .idimm_ncolumns = 10, 2031 .idimm_size = 0x40000000 2032 }, 2033 .ich_ntad_offsets = 12, 2034 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 2035 0, 0 }, 2036 .ich_nrankileaves = 4, 2037 .ich_rankileaves[0] = { 2038 .irle_enabled = B_TRUE, 2039 .irle_nways = 1, 2040 .irle_nwaysbits = 1, 2041 .irle_limit = 0x40000000, 2042 .irle_nentries = 8, 2043 .irle_entries[0] = { 0x0, 0x0 }, 2044 } 2045 }, 2046 .icn_channels[1] = { 2047 .ich_ndimms = 1, 2048 .ich_dimms[0] = { 2049 .idimm_present = B_TRUE, 2050 .idimm_nbanks = 3, 2051 .idimm_width = 8, 2052 .idimm_density = 2, 2053 .idimm_nranks = 2, 2054 .idimm_nrows = 14, 2055 .idimm_ncolumns = 10, 2056 .idimm_size = 0x40000000 2057 }, 2058 .ich_ntad_offsets = 12, 2059 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 2060 0, 0 }, 2061 .ich_nrankileaves = 4, 2062 .ich_rankileaves[0] = { 2063 .irle_enabled = B_TRUE, 2064 .irle_nways = 1, 2065 .irle_nwaysbits = 1, 2066 .irle_limit = 0x40000000, 2067 .irle_nentries = 8, 2068 .irle_entries[0] = { 0x0, 0x0 }, 2069 } 2070 }, 2071 .icn_channels[2] = { 2072 .ich_ndimms = 1, 2073 .ich_dimms[0] = { 2074 .idimm_present = B_TRUE, 2075 .idimm_nbanks = 3, 2076 .idimm_width = 8, 2077 .idimm_density = 2, 2078 .idimm_nranks = 2, 2079 .idimm_nrows = 14, 2080 .idimm_ncolumns = 10, 2081 .idimm_size = 0x40000000 2082 }, 2083 .ich_ntad_offsets = 12, 2084 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 2085 0, 0 }, 2086 .ich_nrankileaves = 4, 2087 .ich_rankileaves[0] = { 2088 .irle_enabled = B_TRUE, 2089 .irle_nways = 1, 2090 .irle_nwaysbits = 1, 2091 .irle_limit = 0x40000000, 2092 .irle_nentries = 8, 2093 .irle_entries[0] = { 0x0, 0x0 }, 2094 } 2095 } 2096 } 2097 } 2098 }; 2099 2100 /* 2101 * A variant on imc_tad_skx_mod3_45t12, but instead of using mod3, we use the 2102 * mod2 variant that favors 0/1. This menas we can only output route entries, 0, 2103 * 1, 2, and 3. 2104 */ 2105 static const imc_t imc_tad_skx_mod2_01_45t12 = { 2106 .imc_gen = IMC_GEN_SKYLAKE, 2107 .imc_nsockets = 1, 2108 .imc_sockets[0] = { 2109 .isock_nodeid = 0, 2110 .isock_valid = IMC_SOCKET_V_VALID, 2111 .isock_sad = { 2112 .isad_flags = 0, 2113 .isad_valid = IMC_SAD_V_VALID, 2114 .isad_tolm = 0x100000000ULL, 2115 .isad_tohm = 0, 2116 .isad_nrules = 24, 2117 .isad_rules[0] = { 2118 .isr_enable = B_TRUE, 2119 .isr_limit = 0x100000000ULL, 2120 .isr_imode = IMC_SAD_IMODE_8t6, 2121 .isr_need_mod3 = B_TRUE, 2122 .isr_mod_mode = IMC_SAD_MOD_MODE_45t12, 2123 .isr_mod_type = IMC_SAD_MOD_TYPE_MOD2_01, 2124 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 2125 .isr_targets = { 8, 9, 0xa, 0xb, 8, 9, 0xa, 2126 0xb } 2127 }, 2128 .isad_mcroute = { 2129 .ismc_nroutes = 6, 2130 .ismc_mcroutes[0] = { 0, 0 }, 2131 .ismc_mcroutes[1] = { 0, 1 }, 2132 .ismc_mcroutes[2] = { 0, 2 }, 2133 .ismc_mcroutes[3] = { 1, 2 }, 2134 .ismc_mcroutes[4] = { 1, 1 }, 2135 .ismc_mcroutes[5] = { 1, 0 } 2136 } 2137 }, 2138 .isock_ntad = 2, 2139 .isock_tad[0] = { 2140 .itad_flags = 0, 2141 .itad_nrules = 8, 2142 .itad_rules[0] = { 2143 .itr_base = 0x0, 2144 .itr_limit = 0x100000000ULL, 2145 .itr_sock_way = 1, 2146 .itr_chan_way = 4, 2147 .itr_sock_gran = IMC_TAD_GRAN_64B, 2148 .itr_chan_gran = IMC_TAD_GRAN_64B, 2149 .itr_ntargets = 4, 2150 .itr_targets = { 0, 0, 0, 0 } 2151 } 2152 }, 2153 .isock_tad[1] = { 2154 .itad_flags = 0, 2155 .itad_nrules = 8, 2156 .itad_rules[0] = { 2157 .itr_base = 0x0, 2158 .itr_limit = 0x100000000ULL, 2159 .itr_sock_way = 1, 2160 .itr_chan_way = 4, 2161 .itr_sock_gran = IMC_TAD_GRAN_64B, 2162 .itr_chan_gran = IMC_TAD_GRAN_64B, 2163 .itr_ntargets = 4, 2164 .itr_targets = { 0, 0, 0, 0 } 2165 } 2166 }, 2167 .isock_nimc = 2, 2168 .isock_imcs[0] = { 2169 .icn_nchannels = 3, 2170 .icn_dimm_type = IMC_DIMM_DDR4, 2171 .icn_ecc = B_TRUE, 2172 .icn_lockstep = B_FALSE, 2173 .icn_closed = B_FALSE, 2174 .icn_channels[0] = { 2175 .ich_ndimms = 1, 2176 .ich_dimms[0] = { 2177 .idimm_present = B_TRUE, 2178 .idimm_nbanks = 3, 2179 .idimm_width = 8, 2180 .idimm_density = 2, 2181 .idimm_nranks = 2, 2182 .idimm_nrows = 14, 2183 .idimm_ncolumns = 10, 2184 .idimm_size = 0x40000000 2185 }, 2186 .ich_ntad_offsets = 12, 2187 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 2188 0, 0 }, 2189 .ich_nrankileaves = 4, 2190 .ich_rankileaves[0] = { 2191 .irle_enabled = B_TRUE, 2192 .irle_nways = 1, 2193 .irle_nwaysbits = 1, 2194 .irle_limit = 0x40000000, 2195 .irle_nentries = 8, 2196 .irle_entries[0] = { 0x0, 0x0 }, 2197 } 2198 }, 2199 .icn_channels[1] = { 2200 .ich_ndimms = 1, 2201 .ich_dimms[0] = { 2202 .idimm_present = B_TRUE, 2203 .idimm_nbanks = 3, 2204 .idimm_width = 8, 2205 .idimm_density = 2, 2206 .idimm_nranks = 2, 2207 .idimm_nrows = 14, 2208 .idimm_ncolumns = 10, 2209 .idimm_size = 0x40000000 2210 }, 2211 .ich_ntad_offsets = 12, 2212 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 2213 0, 0 }, 2214 .ich_nrankileaves = 4, 2215 .ich_rankileaves[0] = { 2216 .irle_enabled = B_TRUE, 2217 .irle_nways = 1, 2218 .irle_nwaysbits = 1, 2219 .irle_limit = 0x40000000, 2220 .irle_nentries = 8, 2221 .irle_entries[0] = { 0x0, 0x0 }, 2222 } 2223 }, 2224 .icn_channels[2] = { 2225 .ich_ndimms = 1, 2226 .ich_dimms[0] = { 2227 .idimm_present = B_TRUE, 2228 .idimm_nbanks = 3, 2229 .idimm_width = 8, 2230 .idimm_density = 2, 2231 .idimm_nranks = 2, 2232 .idimm_nrows = 14, 2233 .idimm_ncolumns = 10, 2234 .idimm_size = 0x40000000 2235 }, 2236 .ich_ntad_offsets = 12, 2237 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 2238 0, 0 }, 2239 .ich_nrankileaves = 4, 2240 .ich_rankileaves[0] = { 2241 .irle_enabled = B_TRUE, 2242 .irle_nways = 1, 2243 .irle_nwaysbits = 1, 2244 .irle_limit = 0x40000000, 2245 .irle_nentries = 8, 2246 .irle_entries[0] = { 0x0, 0x0 }, 2247 } 2248 } 2249 }, 2250 .isock_imcs[1] = { 2251 .icn_nchannels = 3, 2252 .icn_dimm_type = IMC_DIMM_DDR4, 2253 .icn_ecc = B_TRUE, 2254 .icn_lockstep = B_FALSE, 2255 .icn_closed = B_FALSE, 2256 .icn_channels[0] = { 2257 .ich_ndimms = 1, 2258 .ich_dimms[0] = { 2259 .idimm_present = B_TRUE, 2260 .idimm_nbanks = 3, 2261 .idimm_width = 8, 2262 .idimm_density = 2, 2263 .idimm_nranks = 2, 2264 .idimm_nrows = 14, 2265 .idimm_ncolumns = 10, 2266 .idimm_size = 0x40000000 2267 }, 2268 .ich_ntad_offsets = 12, 2269 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 2270 0, 0 }, 2271 .ich_nrankileaves = 4, 2272 .ich_rankileaves[0] = { 2273 .irle_enabled = B_TRUE, 2274 .irle_nways = 1, 2275 .irle_nwaysbits = 1, 2276 .irle_limit = 0x40000000, 2277 .irle_nentries = 8, 2278 .irle_entries[0] = { 0x0, 0x0 }, 2279 } 2280 }, 2281 .icn_channels[1] = { 2282 .ich_ndimms = 1, 2283 .ich_dimms[0] = { 2284 .idimm_present = B_TRUE, 2285 .idimm_nbanks = 3, 2286 .idimm_width = 8, 2287 .idimm_density = 2, 2288 .idimm_nranks = 2, 2289 .idimm_nrows = 14, 2290 .idimm_ncolumns = 10, 2291 .idimm_size = 0x40000000 2292 }, 2293 .ich_ntad_offsets = 12, 2294 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 2295 0, 0 }, 2296 .ich_nrankileaves = 4, 2297 .ich_rankileaves[0] = { 2298 .irle_enabled = B_TRUE, 2299 .irle_nways = 1, 2300 .irle_nwaysbits = 1, 2301 .irle_limit = 0x40000000, 2302 .irle_nentries = 8, 2303 .irle_entries[0] = { 0x0, 0x0 }, 2304 } 2305 }, 2306 .icn_channels[2] = { 2307 .ich_ndimms = 1, 2308 .ich_dimms[0] = { 2309 .idimm_present = B_TRUE, 2310 .idimm_nbanks = 3, 2311 .idimm_width = 8, 2312 .idimm_density = 2, 2313 .idimm_nranks = 2, 2314 .idimm_nrows = 14, 2315 .idimm_ncolumns = 10, 2316 .idimm_size = 0x40000000 2317 }, 2318 .ich_ntad_offsets = 12, 2319 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 2320 0, 0 }, 2321 .ich_nrankileaves = 4, 2322 .ich_rankileaves[0] = { 2323 .irle_enabled = B_TRUE, 2324 .irle_nways = 1, 2325 .irle_nwaysbits = 1, 2326 .irle_limit = 0x40000000, 2327 .irle_nentries = 8, 2328 .irle_entries[0] = { 0x0, 0x0 }, 2329 } 2330 } 2331 } 2332 } 2333 }; 2334 2335 /* 2336 * A variant on imc_tad_skx_mod3_45t12, but instead of using mod3, we use the 2337 * mod2 variant that favors 1/2. This menas we can only output route entries, 2, 2338 * 3, 4, and 5. 2339 */ 2340 static const imc_t imc_tad_skx_mod2_12_45t12 = { 2341 .imc_gen = IMC_GEN_SKYLAKE, 2342 .imc_nsockets = 1, 2343 .imc_sockets[0] = { 2344 .isock_nodeid = 0, 2345 .isock_valid = IMC_SOCKET_V_VALID, 2346 .isock_sad = { 2347 .isad_flags = 0, 2348 .isad_valid = IMC_SAD_V_VALID, 2349 .isad_tolm = 0x100000000ULL, 2350 .isad_tohm = 0, 2351 .isad_nrules = 24, 2352 .isad_rules[0] = { 2353 .isr_enable = B_TRUE, 2354 .isr_limit = 0x100000000ULL, 2355 .isr_imode = IMC_SAD_IMODE_8t6, 2356 .isr_need_mod3 = B_TRUE, 2357 .isr_mod_mode = IMC_SAD_MOD_MODE_45t12, 2358 .isr_mod_type = IMC_SAD_MOD_TYPE_MOD2_12, 2359 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 2360 .isr_targets = { 8, 9, 0xa, 0xb, 8, 9, 0xa, 2361 0xb } 2362 }, 2363 .isad_mcroute = { 2364 .ismc_nroutes = 6, 2365 .ismc_mcroutes[0] = { 0, 0 }, 2366 .ismc_mcroutes[1] = { 0, 1 }, 2367 .ismc_mcroutes[2] = { 0, 2 }, 2368 .ismc_mcroutes[3] = { 1, 2 }, 2369 .ismc_mcroutes[4] = { 1, 1 }, 2370 .ismc_mcroutes[5] = { 1, 0 } 2371 } 2372 }, 2373 .isock_ntad = 2, 2374 .isock_tad[0] = { 2375 .itad_flags = 0, 2376 .itad_nrules = 8, 2377 .itad_rules[0] = { 2378 .itr_base = 0x0, 2379 .itr_limit = 0x100000000ULL, 2380 .itr_sock_way = 1, 2381 .itr_chan_way = 4, 2382 .itr_sock_gran = IMC_TAD_GRAN_64B, 2383 .itr_chan_gran = IMC_TAD_GRAN_64B, 2384 .itr_ntargets = 4, 2385 .itr_targets = { 0, 0, 0, 0 } 2386 } 2387 }, 2388 .isock_tad[1] = { 2389 .itad_flags = 0, 2390 .itad_nrules = 8, 2391 .itad_rules[0] = { 2392 .itr_base = 0x0, 2393 .itr_limit = 0x100000000ULL, 2394 .itr_sock_way = 1, 2395 .itr_chan_way = 4, 2396 .itr_sock_gran = IMC_TAD_GRAN_64B, 2397 .itr_chan_gran = IMC_TAD_GRAN_64B, 2398 .itr_ntargets = 4, 2399 .itr_targets = { 0, 0, 0, 0 } 2400 } 2401 }, 2402 .isock_nimc = 2, 2403 .isock_imcs[0] = { 2404 .icn_nchannels = 3, 2405 .icn_dimm_type = IMC_DIMM_DDR4, 2406 .icn_ecc = B_TRUE, 2407 .icn_lockstep = B_FALSE, 2408 .icn_closed = B_FALSE, 2409 .icn_channels[0] = { 2410 .ich_ndimms = 1, 2411 .ich_dimms[0] = { 2412 .idimm_present = B_TRUE, 2413 .idimm_nbanks = 3, 2414 .idimm_width = 8, 2415 .idimm_density = 2, 2416 .idimm_nranks = 2, 2417 .idimm_nrows = 14, 2418 .idimm_ncolumns = 10, 2419 .idimm_size = 0x40000000 2420 }, 2421 .ich_ntad_offsets = 12, 2422 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 2423 0, 0 }, 2424 .ich_nrankileaves = 4, 2425 .ich_rankileaves[0] = { 2426 .irle_enabled = B_TRUE, 2427 .irle_nways = 1, 2428 .irle_nwaysbits = 1, 2429 .irle_limit = 0x40000000, 2430 .irle_nentries = 8, 2431 .irle_entries[0] = { 0x0, 0x0 }, 2432 } 2433 }, 2434 .icn_channels[1] = { 2435 .ich_ndimms = 1, 2436 .ich_dimms[0] = { 2437 .idimm_present = B_TRUE, 2438 .idimm_nbanks = 3, 2439 .idimm_width = 8, 2440 .idimm_density = 2, 2441 .idimm_nranks = 2, 2442 .idimm_nrows = 14, 2443 .idimm_ncolumns = 10, 2444 .idimm_size = 0x40000000 2445 }, 2446 .ich_ntad_offsets = 12, 2447 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 2448 0, 0 }, 2449 .ich_nrankileaves = 4, 2450 .ich_rankileaves[0] = { 2451 .irle_enabled = B_TRUE, 2452 .irle_nways = 1, 2453 .irle_nwaysbits = 1, 2454 .irle_limit = 0x40000000, 2455 .irle_nentries = 8, 2456 .irle_entries[0] = { 0x0, 0x0 }, 2457 } 2458 }, 2459 .icn_channels[2] = { 2460 .ich_ndimms = 1, 2461 .ich_dimms[0] = { 2462 .idimm_present = B_TRUE, 2463 .idimm_nbanks = 3, 2464 .idimm_width = 8, 2465 .idimm_density = 2, 2466 .idimm_nranks = 2, 2467 .idimm_nrows = 14, 2468 .idimm_ncolumns = 10, 2469 .idimm_size = 0x40000000 2470 }, 2471 .ich_ntad_offsets = 12, 2472 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 2473 0, 0 }, 2474 .ich_nrankileaves = 4, 2475 .ich_rankileaves[0] = { 2476 .irle_enabled = B_TRUE, 2477 .irle_nways = 1, 2478 .irle_nwaysbits = 1, 2479 .irle_limit = 0x40000000, 2480 .irle_nentries = 8, 2481 .irle_entries[0] = { 0x0, 0x0 }, 2482 } 2483 } 2484 }, 2485 .isock_imcs[1] = { 2486 .icn_nchannels = 3, 2487 .icn_dimm_type = IMC_DIMM_DDR4, 2488 .icn_ecc = B_TRUE, 2489 .icn_lockstep = B_FALSE, 2490 .icn_closed = B_FALSE, 2491 .icn_channels[0] = { 2492 .ich_ndimms = 1, 2493 .ich_dimms[0] = { 2494 .idimm_present = B_TRUE, 2495 .idimm_nbanks = 3, 2496 .idimm_width = 8, 2497 .idimm_density = 2, 2498 .idimm_nranks = 2, 2499 .idimm_nrows = 14, 2500 .idimm_ncolumns = 10, 2501 .idimm_size = 0x40000000 2502 }, 2503 .ich_ntad_offsets = 12, 2504 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 2505 0, 0 }, 2506 .ich_nrankileaves = 4, 2507 .ich_rankileaves[0] = { 2508 .irle_enabled = B_TRUE, 2509 .irle_nways = 1, 2510 .irle_nwaysbits = 1, 2511 .irle_limit = 0x40000000, 2512 .irle_nentries = 8, 2513 .irle_entries[0] = { 0x0, 0x0 }, 2514 } 2515 }, 2516 .icn_channels[1] = { 2517 .ich_ndimms = 1, 2518 .ich_dimms[0] = { 2519 .idimm_present = B_TRUE, 2520 .idimm_nbanks = 3, 2521 .idimm_width = 8, 2522 .idimm_density = 2, 2523 .idimm_nranks = 2, 2524 .idimm_nrows = 14, 2525 .idimm_ncolumns = 10, 2526 .idimm_size = 0x40000000 2527 }, 2528 .ich_ntad_offsets = 12, 2529 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 2530 0, 0 }, 2531 .ich_nrankileaves = 4, 2532 .ich_rankileaves[0] = { 2533 .irle_enabled = B_TRUE, 2534 .irle_nways = 1, 2535 .irle_nwaysbits = 1, 2536 .irle_limit = 0x40000000, 2537 .irle_nentries = 8, 2538 .irle_entries[0] = { 0x0, 0x0 }, 2539 } 2540 }, 2541 .icn_channels[2] = { 2542 .ich_ndimms = 1, 2543 .ich_dimms[0] = { 2544 .idimm_present = B_TRUE, 2545 .idimm_nbanks = 3, 2546 .idimm_width = 8, 2547 .idimm_density = 2, 2548 .idimm_nranks = 2, 2549 .idimm_nrows = 14, 2550 .idimm_ncolumns = 10, 2551 .idimm_size = 0x40000000 2552 }, 2553 .ich_ntad_offsets = 12, 2554 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 2555 0, 0 }, 2556 .ich_nrankileaves = 4, 2557 .ich_rankileaves[0] = { 2558 .irle_enabled = B_TRUE, 2559 .irle_nways = 1, 2560 .irle_nwaysbits = 1, 2561 .irle_limit = 0x40000000, 2562 .irle_nentries = 8, 2563 .irle_entries[0] = { 0x0, 0x0 }, 2564 } 2565 } 2566 } 2567 } 2568 }; 2569 2570 /* 2571 * A variant on imc_tad_skx_mod3_45t12, but instead of using mod3, we use the 2572 * mod2 variant that favors 0/2. This means we can only output route entries, 0, 2573 * 1, 4, and 5. 2574 */ 2575 static const imc_t imc_tad_skx_mod2_02_45t12 = { 2576 .imc_gen = IMC_GEN_SKYLAKE, 2577 .imc_nsockets = 1, 2578 .imc_sockets[0] = { 2579 .isock_nodeid = 0, 2580 .isock_valid = IMC_SOCKET_V_VALID, 2581 .isock_sad = { 2582 .isad_flags = 0, 2583 .isad_valid = IMC_SAD_V_VALID, 2584 .isad_tolm = 0x100000000ULL, 2585 .isad_tohm = 0, 2586 .isad_nrules = 24, 2587 .isad_rules[0] = { 2588 .isr_enable = B_TRUE, 2589 .isr_limit = 0x100000000ULL, 2590 .isr_imode = IMC_SAD_IMODE_8t6, 2591 .isr_need_mod3 = B_TRUE, 2592 .isr_mod_mode = IMC_SAD_MOD_MODE_45t12, 2593 .isr_mod_type = IMC_SAD_MOD_TYPE_MOD2_02, 2594 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 2595 .isr_targets = { 8, 9, 0xa, 0xb, 8, 9, 0xa, 2596 0xb } 2597 }, 2598 .isad_mcroute = { 2599 .ismc_nroutes = 6, 2600 .ismc_mcroutes[0] = { 0, 0 }, 2601 .ismc_mcroutes[1] = { 0, 1 }, 2602 .ismc_mcroutes[2] = { 0, 2 }, 2603 .ismc_mcroutes[3] = { 1, 2 }, 2604 .ismc_mcroutes[4] = { 1, 1 }, 2605 .ismc_mcroutes[5] = { 1, 0 } 2606 } 2607 }, 2608 .isock_ntad = 2, 2609 .isock_tad[0] = { 2610 .itad_flags = 0, 2611 .itad_nrules = 8, 2612 .itad_rules[0] = { 2613 .itr_base = 0x0, 2614 .itr_limit = 0x100000000ULL, 2615 .itr_sock_way = 1, 2616 .itr_chan_way = 4, 2617 .itr_sock_gran = IMC_TAD_GRAN_64B, 2618 .itr_chan_gran = IMC_TAD_GRAN_64B, 2619 .itr_ntargets = 4, 2620 .itr_targets = { 0, 0, 0, 0 } 2621 } 2622 }, 2623 .isock_tad[1] = { 2624 .itad_flags = 0, 2625 .itad_nrules = 8, 2626 .itad_rules[0] = { 2627 .itr_base = 0x0, 2628 .itr_limit = 0x100000000ULL, 2629 .itr_sock_way = 1, 2630 .itr_chan_way = 4, 2631 .itr_sock_gran = IMC_TAD_GRAN_64B, 2632 .itr_chan_gran = IMC_TAD_GRAN_64B, 2633 .itr_ntargets = 4, 2634 .itr_targets = { 0, 0, 0, 0 } 2635 } 2636 }, 2637 .isock_nimc = 2, 2638 .isock_imcs[0] = { 2639 .icn_nchannels = 3, 2640 .icn_dimm_type = IMC_DIMM_DDR4, 2641 .icn_ecc = B_TRUE, 2642 .icn_lockstep = B_FALSE, 2643 .icn_closed = B_FALSE, 2644 .icn_channels[0] = { 2645 .ich_ndimms = 1, 2646 .ich_dimms[0] = { 2647 .idimm_present = B_TRUE, 2648 .idimm_nbanks = 3, 2649 .idimm_width = 8, 2650 .idimm_density = 2, 2651 .idimm_nranks = 2, 2652 .idimm_nrows = 14, 2653 .idimm_ncolumns = 10, 2654 .idimm_size = 0x40000000 2655 }, 2656 .ich_ntad_offsets = 12, 2657 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 2658 0, 0 }, 2659 .ich_nrankileaves = 4, 2660 .ich_rankileaves[0] = { 2661 .irle_enabled = B_TRUE, 2662 .irle_nways = 1, 2663 .irle_nwaysbits = 1, 2664 .irle_limit = 0x40000000, 2665 .irle_nentries = 8, 2666 .irle_entries[0] = { 0x0, 0x0 }, 2667 } 2668 }, 2669 .icn_channels[1] = { 2670 .ich_ndimms = 1, 2671 .ich_dimms[0] = { 2672 .idimm_present = B_TRUE, 2673 .idimm_nbanks = 3, 2674 .idimm_width = 8, 2675 .idimm_density = 2, 2676 .idimm_nranks = 2, 2677 .idimm_nrows = 14, 2678 .idimm_ncolumns = 10, 2679 .idimm_size = 0x40000000 2680 }, 2681 .ich_ntad_offsets = 12, 2682 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 2683 0, 0 }, 2684 .ich_nrankileaves = 4, 2685 .ich_rankileaves[0] = { 2686 .irle_enabled = B_TRUE, 2687 .irle_nways = 1, 2688 .irle_nwaysbits = 1, 2689 .irle_limit = 0x40000000, 2690 .irle_nentries = 8, 2691 .irle_entries[0] = { 0x0, 0x0 }, 2692 } 2693 }, 2694 .icn_channels[2] = { 2695 .ich_ndimms = 1, 2696 .ich_dimms[0] = { 2697 .idimm_present = B_TRUE, 2698 .idimm_nbanks = 3, 2699 .idimm_width = 8, 2700 .idimm_density = 2, 2701 .idimm_nranks = 2, 2702 .idimm_nrows = 14, 2703 .idimm_ncolumns = 10, 2704 .idimm_size = 0x40000000 2705 }, 2706 .ich_ntad_offsets = 12, 2707 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 2708 0, 0 }, 2709 .ich_nrankileaves = 4, 2710 .ich_rankileaves[0] = { 2711 .irle_enabled = B_TRUE, 2712 .irle_nways = 1, 2713 .irle_nwaysbits = 1, 2714 .irle_limit = 0x40000000, 2715 .irle_nentries = 8, 2716 .irle_entries[0] = { 0x0, 0x0 }, 2717 } 2718 } 2719 }, 2720 .isock_imcs[1] = { 2721 .icn_nchannels = 3, 2722 .icn_dimm_type = IMC_DIMM_DDR4, 2723 .icn_ecc = B_TRUE, 2724 .icn_lockstep = B_FALSE, 2725 .icn_closed = B_FALSE, 2726 .icn_channels[0] = { 2727 .ich_ndimms = 1, 2728 .ich_dimms[0] = { 2729 .idimm_present = B_TRUE, 2730 .idimm_nbanks = 3, 2731 .idimm_width = 8, 2732 .idimm_density = 2, 2733 .idimm_nranks = 2, 2734 .idimm_nrows = 14, 2735 .idimm_ncolumns = 10, 2736 .idimm_size = 0x40000000 2737 }, 2738 .ich_ntad_offsets = 12, 2739 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 2740 0, 0 }, 2741 .ich_nrankileaves = 4, 2742 .ich_rankileaves[0] = { 2743 .irle_enabled = B_TRUE, 2744 .irle_nways = 1, 2745 .irle_nwaysbits = 1, 2746 .irle_limit = 0x40000000, 2747 .irle_nentries = 8, 2748 .irle_entries[0] = { 0x0, 0x0 }, 2749 } 2750 }, 2751 .icn_channels[1] = { 2752 .ich_ndimms = 1, 2753 .ich_dimms[0] = { 2754 .idimm_present = B_TRUE, 2755 .idimm_nbanks = 3, 2756 .idimm_width = 8, 2757 .idimm_density = 2, 2758 .idimm_nranks = 2, 2759 .idimm_nrows = 14, 2760 .idimm_ncolumns = 10, 2761 .idimm_size = 0x40000000 2762 }, 2763 .ich_ntad_offsets = 12, 2764 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 2765 0, 0 }, 2766 .ich_nrankileaves = 4, 2767 .ich_rankileaves[0] = { 2768 .irle_enabled = B_TRUE, 2769 .irle_nways = 1, 2770 .irle_nwaysbits = 1, 2771 .irle_limit = 0x40000000, 2772 .irle_nentries = 8, 2773 .irle_entries[0] = { 0x0, 0x0 }, 2774 } 2775 }, 2776 .icn_channels[2] = { 2777 .ich_ndimms = 1, 2778 .ich_dimms[0] = { 2779 .idimm_present = B_TRUE, 2780 .idimm_nbanks = 3, 2781 .idimm_width = 8, 2782 .idimm_density = 2, 2783 .idimm_nranks = 2, 2784 .idimm_nrows = 14, 2785 .idimm_ncolumns = 10, 2786 .idimm_size = 0x40000000 2787 }, 2788 .ich_ntad_offsets = 12, 2789 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 2790 0, 0 }, 2791 .ich_nrankileaves = 4, 2792 .ich_rankileaves[0] = { 2793 .irle_enabled = B_TRUE, 2794 .irle_nways = 1, 2795 .irle_nwaysbits = 1, 2796 .irle_limit = 0x40000000, 2797 .irle_nentries = 8, 2798 .irle_entries[0] = { 0x0, 0x0 }, 2799 } 2800 } 2801 } 2802 } 2803 }; 2804 2805 const imc_test_case_t imc_test_tad[] = { 2806 /* 2807 * These tests come in pairs. The first two verify that we can get the same 2808 * address on the channel and interleave. The second set verifies that we end up 2809 * in the same channel when we're within interleaving. The third set shows that 2810 * we interleave again and will be used as a point of comparison in the next 2811 * group of tests. The fourth set varies this and makes sure that we can end up 2812 * on the right channel at different address ranges. 2813 */ 2814 { 2815 .itc_desc = "1 Socket, 2 Channel way (1)", 2816 .itc_imc = &imc_tad_1s_2cw, 2817 .itc_pa = 0x33333333, 2818 .itc_pass = B_TRUE, 2819 .itc_nodeid = 0, 2820 .itc_tadid = 0, 2821 .itc_channelid = 0, 2822 .itc_chanaddr = 0x199999b3, 2823 .itc_dimmid = 0, 2824 .itc_rankid = 0, 2825 .itc_rankaddr = 0x199999b3 2826 }, { 2827 .itc_desc = "1 Socket, 2 Channel way (2)", 2828 .itc_imc = &imc_tad_1s_2cw, 2829 .itc_pa = 0x33333373, 2830 .itc_pass = B_TRUE, 2831 .itc_nodeid = 0, 2832 .itc_tadid = 0, 2833 .itc_channelid = 1, 2834 .itc_chanaddr = 0x199999b3, 2835 .itc_dimmid = 0, 2836 .itc_rankid = 0, 2837 .itc_rankaddr = 0x199999b3 2838 }, { 2839 .itc_desc = "1 Socket, 2 Channel way (3)", 2840 .itc_imc = &imc_tad_1s_2cw, 2841 .itc_pa = 0x3333331a, 2842 .itc_pass = B_TRUE, 2843 .itc_nodeid = 0, 2844 .itc_tadid = 0, 2845 .itc_channelid = 0, 2846 .itc_chanaddr = 0x1999999a, 2847 .itc_dimmid = 0, 2848 .itc_rankid = 0, 2849 .itc_rankaddr = 0x1999999a 2850 }, { 2851 .itc_desc = "1 Socket, 2 Channel way (4)", 2852 .itc_imc = &imc_tad_1s_2cw, 2853 .itc_pa = 0x33333342, 2854 .itc_pass = B_TRUE, 2855 .itc_nodeid = 0, 2856 .itc_tadid = 0, 2857 .itc_channelid = 1, 2858 .itc_chanaddr = 0x19999982, 2859 .itc_dimmid = 0, 2860 .itc_rankid = 0, 2861 .itc_rankaddr = 0x19999982 2862 }, { 2863 .itc_desc = "1 Socket, 2 Channel way (5)", 2864 .itc_imc = &imc_tad_1s_2cw, 2865 .itc_pa = 0x333333b3, 2866 .itc_pass = B_TRUE, 2867 .itc_nodeid = 0, 2868 .itc_tadid = 0, 2869 .itc_channelid = 0, 2870 .itc_chanaddr = 0x199999f3, 2871 .itc_dimmid = 0, 2872 .itc_rankid = 0, 2873 .itc_rankaddr = 0x199999f3 2874 }, { 2875 .itc_desc = "1 Socket, 2 Channel way (6)", 2876 .itc_imc = &imc_tad_1s_2cw, 2877 .itc_pa = 0x333333f3, 2878 .itc_pass = B_TRUE, 2879 .itc_nodeid = 0, 2880 .itc_tadid = 0, 2881 .itc_channelid = 1, 2882 .itc_chanaddr = 0x199999f3, 2883 .itc_dimmid = 0, 2884 .itc_rankid = 0, 2885 .itc_rankaddr = 0x199999f3 2886 }, { 2887 .itc_desc = "1 Socket, 2 Channel way (7)", 2888 .itc_imc = &imc_tad_1s_2cw, 2889 .itc_pa = 0x22222222, 2890 .itc_pass = B_TRUE, 2891 .itc_nodeid = 0, 2892 .itc_tadid = 0, 2893 .itc_channelid = 0, 2894 .itc_chanaddr = 0x11111122, 2895 .itc_dimmid = 0, 2896 .itc_rankid = 0, 2897 .itc_rankaddr = 0x11111122 2898 }, { 2899 .itc_desc = "1 Socket, 2 Channel way (8)", 2900 .itc_imc = &imc_tad_1s_2cw, 2901 .itc_pa = 0x77777777, 2902 .itc_pass = B_TRUE, 2903 .itc_nodeid = 0, 2904 .itc_tadid = 0, 2905 .itc_channelid = 1, 2906 .itc_chanaddr = 0x3bbbbbb7, 2907 .itc_dimmid = 0, 2908 .itc_rankid = 0, 2909 .itc_rankaddr = 0x3bbbbbb7 2910 }, 2911 /* 2912 * This next set of tests is similar to the previous one, except we have the 2913 * a7mode / McChanShiftUp enabled, which means that we use 7-bits to index into 2914 * the channel by default rather than 6. We have tests that compare this 2915 * behavior that would have varied in the previous case, but does not now. We do 2916 * this mostly by using the same initial set of addresses (tests 1-6 of the 2917 * previous set). 2918 */ 2919 { 2920 .itc_desc = "1 Socket, 2 Channel way, Shift Up (1)", 2921 .itc_imc = &imc_tad_1s_2cw_shiftup, 2922 .itc_pa = 0x33333333, 2923 .itc_pass = B_TRUE, 2924 .itc_nodeid = 0, 2925 .itc_tadid = 0, 2926 .itc_channelid = 0, 2927 .itc_chanaddr = 0x199999b3, 2928 .itc_dimmid = 0, 2929 .itc_rankid = 0, 2930 .itc_rankaddr = 0x199999b3 2931 }, { 2932 .itc_desc = "1 Socket, 2 Channel way, Shift Up (2)", 2933 .itc_imc = &imc_tad_1s_2cw_shiftup, 2934 .itc_pa = 0x33333373, 2935 .itc_pass = B_TRUE, 2936 .itc_nodeid = 0, 2937 .itc_tadid = 0, 2938 .itc_channelid = 0, 2939 .itc_chanaddr = 0x199999f3, 2940 .itc_dimmid = 0, 2941 .itc_rankid = 0, 2942 .itc_rankaddr = 0x199999f3 2943 }, { 2944 .itc_desc = "1 Socket, 2 Channel way, Shift Up (3)", 2945 .itc_imc = &imc_tad_1s_2cw_shiftup, 2946 .itc_pa = 0x3333331a, 2947 .itc_pass = B_TRUE, 2948 .itc_nodeid = 0, 2949 .itc_tadid = 0, 2950 .itc_channelid = 0, 2951 .itc_chanaddr = 0x1999999a, 2952 .itc_dimmid = 0, 2953 .itc_rankid = 0, 2954 .itc_rankaddr = 0x1999999a 2955 }, { 2956 .itc_desc = "1 Socket, 2 Channel way, Shift Up (4)", 2957 .itc_imc = &imc_tad_1s_2cw_shiftup, 2958 .itc_pa = 0x33333342, 2959 .itc_pass = B_TRUE, 2960 .itc_nodeid = 0, 2961 .itc_tadid = 0, 2962 .itc_channelid = 0, 2963 .itc_chanaddr = 0x199999c2, 2964 .itc_dimmid = 0, 2965 .itc_rankid = 0, 2966 .itc_rankaddr = 0x199999c2 2967 }, { 2968 .itc_desc = "1 Socket, 2 Channel way, Shift Up (5)", 2969 .itc_imc = &imc_tad_1s_2cw_shiftup, 2970 .itc_pa = 0x333333b3, 2971 .itc_pass = B_TRUE, 2972 .itc_nodeid = 0, 2973 .itc_tadid = 0, 2974 .itc_channelid = 1, 2975 .itc_chanaddr = 0x199999b3, 2976 .itc_dimmid = 0, 2977 .itc_rankid = 0, 2978 .itc_rankaddr = 0x199999b3 2979 }, { 2980 .itc_desc = "1 Socket, 2 Channel way, Shift Up (6)", 2981 .itc_imc = &imc_tad_1s_2cw_shiftup, 2982 .itc_pa = 0x333333f3, 2983 .itc_pass = B_TRUE, 2984 .itc_nodeid = 0, 2985 .itc_tadid = 0, 2986 .itc_channelid = 1, 2987 .itc_chanaddr = 0x199999f3, 2988 .itc_dimmid = 0, 2989 .itc_rankid = 0, 2990 .itc_rankaddr = 0x199999f3 2991 }, 2992 /* 2993 * This next set of tests focuses on channel hashing. This is when we take the 2994 * upper bits of the system addrses and use that to influence which channel 2995 * something should be directed to. To see this, we take addresses that have the 2996 * same base address (using bits 0-11) and see that they channels based on the 2997 * different upper bits, where as without channel hashing, we shouldn't expect 2998 * that. 2999 */ 3000 { 3001 .itc_desc = "1 Socket, 2 Channel way, Hashing (1)", 3002 .itc_imc = &imc_tad_1s_2cw_chanhash, 3003 .itc_pa = 0x00000bad, 3004 .itc_pass = B_TRUE, 3005 .itc_nodeid = 0, 3006 .itc_tadid = 0, 3007 .itc_channelid = 0, 3008 .itc_chanaddr = 0x000005ed, 3009 .itc_dimmid = 0, 3010 .itc_rankid = 0, 3011 .itc_rankaddr = 0x000005ed 3012 }, { 3013 .itc_desc = "1 Socket, 2 Channel way, Hashing (2)", 3014 .itc_imc = &imc_tad_1s_2cw_chanhash, 3015 .itc_pa = 0x00001bad, 3016 .itc_pass = B_TRUE, 3017 .itc_nodeid = 0, 3018 .itc_tadid = 0, 3019 .itc_channelid = 1, 3020 .itc_chanaddr = 0x00000ded, 3021 .itc_dimmid = 0, 3022 .itc_rankid = 0, 3023 .itc_rankaddr = 0x00000ded 3024 }, { 3025 .itc_desc = "1 Socket, 2 Channel way, Hashing (3)", 3026 .itc_imc = &imc_tad_1s_2cw_chanhash, 3027 .itc_pa = 0x00011bad, 3028 .itc_pass = B_TRUE, 3029 .itc_nodeid = 0, 3030 .itc_tadid = 0, 3031 .itc_channelid = 0, 3032 .itc_chanaddr = 0x00008ded, 3033 .itc_dimmid = 0, 3034 .itc_rankid = 0, 3035 .itc_rankaddr = 0x00008ded 3036 }, { 3037 .itc_desc = "1 Socket, 2 Channel way, Hashing (4)", 3038 .itc_imc = &imc_tad_1s_2cw_chanhash, 3039 .itc_pa = 0x00111bad, 3040 .itc_pass = B_TRUE, 3041 .itc_nodeid = 0, 3042 .itc_tadid = 0, 3043 .itc_channelid = 1, 3044 .itc_chanaddr = 0x00088ded, 3045 .itc_dimmid = 0, 3046 .itc_rankid = 0, 3047 .itc_rankaddr = 0x00088ded 3048 }, { 3049 /* The channel shouldn't change as it's not a bit we index on */ 3050 .itc_desc = "1 Socket, 2 Channel way, Hashing (5)", 3051 .itc_imc = &imc_tad_1s_2cw_chanhash, 3052 .itc_pa = 0x00311bad, 3053 .itc_pass = B_TRUE, 3054 .itc_nodeid = 0, 3055 .itc_tadid = 0, 3056 .itc_channelid = 1, 3057 .itc_chanaddr = 0x00188ded, 3058 .itc_dimmid = 0, 3059 .itc_rankid = 0, 3060 .itc_rankaddr = 0x00188ded 3061 }, { 3062 /* This one shouldn't change as the 1 is > bit 28 */ 3063 .itc_desc = "1 Socket, 2 Channel way, Hashing (6)", 3064 .itc_imc = &imc_tad_1s_2cw_chanhash, 3065 .itc_pa = 0x20111bad, 3066 .itc_pass = B_TRUE, 3067 .itc_nodeid = 0, 3068 .itc_tadid = 0, 3069 .itc_channelid = 1, 3070 .itc_chanaddr = 0x10088ded, 3071 .itc_dimmid = 0, 3072 .itc_rankid = 0, 3073 .itc_rankaddr = 0x10088ded 3074 }, { 3075 .itc_desc = "1 Socket, 2 Channel way, Hashing (7)", 3076 .itc_imc = &imc_tad_1s_2cw_chanhash, 3077 .itc_pa = 0x00000bed, 3078 .itc_pass = B_TRUE, 3079 .itc_nodeid = 0, 3080 .itc_tadid = 0, 3081 .itc_channelid = 1, 3082 .itc_chanaddr = 0x000005ed, 3083 .itc_dimmid = 0, 3084 .itc_rankid = 0, 3085 .itc_rankaddr = 0x000005ed 3086 }, { 3087 .itc_desc = "1 Socket, 2 Channel way, Hashing (8)", 3088 .itc_imc = &imc_tad_1s_2cw_chanhash, 3089 .itc_pa = 0x00100bed, 3090 .itc_pass = B_TRUE, 3091 .itc_nodeid = 0, 3092 .itc_tadid = 0, 3093 .itc_channelid = 0, 3094 .itc_chanaddr = 0x000805ed, 3095 .itc_dimmid = 0, 3096 .itc_rankid = 0, 3097 .itc_rankaddr = 0x000805ed 3098 }, { 3099 .itc_desc = "1 Socket, 2 Channel way, Hashing (9)", 3100 .itc_imc = &imc_tad_1s_2cw_chanhash, 3101 .itc_pa = 0x00300bed, 3102 .itc_pass = B_TRUE, 3103 .itc_nodeid = 0, 3104 .itc_tadid = 0, 3105 .itc_channelid = 0, 3106 .itc_chanaddr = 0x001805ed, 3107 .itc_dimmid = 0, 3108 .itc_rankid = 0, 3109 .itc_rankaddr = 0x001805ed 3110 }, { 3111 .itc_desc = "1 Socket, 2 Channel way, Hashing (10)", 3112 .itc_imc = &imc_tad_1s_2cw_chanhash, 3113 .itc_pa = 0x00500bed, 3114 .itc_pass = B_TRUE, 3115 .itc_nodeid = 0, 3116 .itc_tadid = 0, 3117 .itc_channelid = 1, 3118 .itc_chanaddr = 0x002805ed, 3119 .itc_dimmid = 0, 3120 .itc_rankid = 0, 3121 .itc_rankaddr = 0x002805ed 3122 }, 3123 /* 3124 * This range of tests basically checks how we interleave in the multi-rule 3125 * system that we've put together. We have regions that should be direct mapped 3126 * an others that should be interleaved. 3127 */ 3128 { 3129 .itc_desc = "1s Multi-rule (1)", 3130 .itc_imc = &imc_tad_1s_multirule, 3131 .itc_pa = 0x07654321, 3132 .itc_pass = B_TRUE, 3133 .itc_nodeid = 0, 3134 .itc_tadid = 0, 3135 .itc_channelid = 0, 3136 .itc_chanaddr = 0x03b2a1a1, 3137 .itc_dimmid = 0, 3138 .itc_rankid = 0, 3139 .itc_rankaddr = 0x03b2a1a1 3140 }, { 3141 .itc_desc = "1s Multi-rule (2)", 3142 .itc_imc = &imc_tad_1s_multirule, 3143 .itc_pa = 0x07654361, 3144 .itc_pass = B_TRUE, 3145 .itc_nodeid = 0, 3146 .itc_tadid = 0, 3147 .itc_channelid = 1, 3148 .itc_chanaddr = 0x03b2a1a1, 3149 .itc_dimmid = 0, 3150 .itc_rankid = 0, 3151 .itc_rankaddr = 0x03b2a1a1 3152 }, { 3153 .itc_desc = "1s Multi-rule (3)", 3154 .itc_imc = &imc_tad_1s_multirule, 3155 .itc_pa = 0x17654321, 3156 .itc_pass = B_TRUE, 3157 .itc_nodeid = 0, 3158 .itc_tadid = 0, 3159 .itc_channelid = 0, 3160 .itc_chanaddr = 0x0bb2a1a1, 3161 .itc_dimmid = 0, 3162 .itc_rankid = 0, 3163 .itc_rankaddr = 0x0bb2a1a1 3164 }, { 3165 .itc_desc = "1s Multi-rule (4)", 3166 .itc_imc = &imc_tad_1s_multirule, 3167 .itc_pa = 0x17654361, 3168 .itc_pass = B_TRUE, 3169 .itc_nodeid = 0, 3170 .itc_tadid = 0, 3171 .itc_channelid = 1, 3172 .itc_chanaddr = 0x0bb2a1a1, 3173 .itc_dimmid = 0, 3174 .itc_rankid = 0, 3175 .itc_rankaddr = 0x0bb2a1a1 3176 }, { 3177 .itc_desc = "1s Multi-rule (5)", 3178 .itc_imc = &imc_tad_1s_multirule, 3179 .itc_pa = 0x27654321, 3180 .itc_pass = B_TRUE, 3181 .itc_nodeid = 0, 3182 .itc_tadid = 0, 3183 .itc_channelid = 1, 3184 .itc_chanaddr = 0x17654321, 3185 .itc_dimmid = 0, 3186 .itc_rankid = 0, 3187 .itc_rankaddr = 0x17654321 3188 }, { 3189 .itc_desc = "1s Multi-rule (6)", 3190 .itc_imc = &imc_tad_1s_multirule, 3191 .itc_pa = 0x27654361, 3192 .itc_pass = B_TRUE, 3193 .itc_nodeid = 0, 3194 .itc_tadid = 0, 3195 .itc_channelid = 1, 3196 .itc_chanaddr = 0x17654361, 3197 .itc_dimmid = 0, 3198 .itc_rankid = 0, 3199 .itc_rankaddr = 0x17654361 3200 }, { 3201 .itc_desc = "1s Multi-rule (7)", 3202 .itc_imc = &imc_tad_1s_multirule, 3203 .itc_pa = 0x37654321, 3204 .itc_pass = B_TRUE, 3205 .itc_nodeid = 0, 3206 .itc_tadid = 0, 3207 .itc_channelid = 1, 3208 .itc_chanaddr = 0x27654321, 3209 .itc_dimmid = 0, 3210 .itc_rankid = 0, 3211 .itc_rankaddr = 0x27654321 3212 }, { 3213 .itc_desc = "1s Multi-rule (8)", 3214 .itc_imc = &imc_tad_1s_multirule, 3215 .itc_pa = 0x37654361, 3216 .itc_pass = B_TRUE, 3217 .itc_nodeid = 0, 3218 .itc_tadid = 0, 3219 .itc_channelid = 1, 3220 .itc_chanaddr = 0x27654361, 3221 .itc_dimmid = 0, 3222 .itc_rankid = 0, 3223 .itc_rankaddr = 0x27654361 3224 }, { 3225 .itc_desc = "1s Multi-rule (9)", 3226 .itc_imc = &imc_tad_1s_multirule, 3227 .itc_pa = 0x47654321, 3228 .itc_pass = B_TRUE, 3229 .itc_nodeid = 0, 3230 .itc_tadid = 0, 3231 .itc_channelid = 0, 3232 .itc_chanaddr = 0x17654321, 3233 .itc_dimmid = 0, 3234 .itc_rankid = 0, 3235 .itc_rankaddr = 0x17654321 3236 }, { 3237 .itc_desc = "1s Multi-rule (10)", 3238 .itc_imc = &imc_tad_1s_multirule, 3239 .itc_pa = 0x47654361, 3240 .itc_pass = B_TRUE, 3241 .itc_nodeid = 0, 3242 .itc_tadid = 0, 3243 .itc_channelid = 0, 3244 .itc_chanaddr = 0x17654361, 3245 .itc_dimmid = 0, 3246 .itc_rankid = 0, 3247 .itc_rankaddr = 0x17654361 3248 }, { 3249 .itc_desc = "1s Multi-rule (11)", 3250 .itc_imc = &imc_tad_1s_multirule, 3251 .itc_pa = 0x57654321, 3252 .itc_pass = B_TRUE, 3253 .itc_nodeid = 0, 3254 .itc_tadid = 0, 3255 .itc_channelid = 0, 3256 .itc_chanaddr = 0x27654321, 3257 .itc_dimmid = 0, 3258 .itc_rankid = 0, 3259 .itc_rankaddr = 0x27654321 3260 }, { 3261 .itc_desc = "1s Multi-rule (12)", 3262 .itc_imc = &imc_tad_1s_multirule, 3263 .itc_pa = 0x57654361, 3264 .itc_pass = B_TRUE, 3265 .itc_nodeid = 0, 3266 .itc_tadid = 0, 3267 .itc_channelid = 0, 3268 .itc_chanaddr = 0x27654361, 3269 .itc_dimmid = 0, 3270 .itc_rankid = 0, 3271 .itc_rankaddr = 0x27654361 3272 }, { 3273 .itc_desc = "1s Multi-rule (13)", 3274 .itc_imc = &imc_tad_1s_multirule, 3275 .itc_pa = 0x67654321, 3276 .itc_pass = B_TRUE, 3277 .itc_nodeid = 0, 3278 .itc_tadid = 0, 3279 .itc_channelid = 1, 3280 .itc_chanaddr = 0x33b2a1a1, 3281 .itc_dimmid = 0, 3282 .itc_rankid = 0, 3283 .itc_rankaddr = 0x33b2a1a1 3284 }, { 3285 .itc_desc = "1s Multi-rule (14)", 3286 .itc_imc = &imc_tad_1s_multirule, 3287 .itc_pa = 0x67654361, 3288 .itc_pass = B_TRUE, 3289 .itc_nodeid = 0, 3290 .itc_tadid = 0, 3291 .itc_channelid = 0, 3292 .itc_chanaddr = 0x33b2a1a1, 3293 .itc_dimmid = 0, 3294 .itc_rankid = 0, 3295 .itc_rankaddr = 0x33b2a1a1 3296 }, { 3297 .itc_desc = "1s Multi-rule (15)", 3298 .itc_imc = &imc_tad_1s_multirule, 3299 .itc_pa = 0x77654321, 3300 .itc_pass = B_TRUE, 3301 .itc_nodeid = 0, 3302 .itc_tadid = 0, 3303 .itc_channelid = 1, 3304 .itc_chanaddr = 0x3bb2a1a1, 3305 .itc_dimmid = 0, 3306 .itc_rankid = 0, 3307 .itc_rankaddr = 0x3bb2a1a1 3308 }, { 3309 .itc_desc = "1s Multi-rule (16)", 3310 .itc_imc = &imc_tad_1s_multirule, 3311 .itc_pa = 0x77654361, 3312 .itc_pass = B_TRUE, 3313 .itc_nodeid = 0, 3314 .itc_tadid = 0, 3315 .itc_channelid = 0, 3316 .itc_chanaddr = 0x3bb2a1a1, 3317 .itc_dimmid = 0, 3318 .itc_rankid = 0, 3319 .itc_rankaddr = 0x3bb2a1a1 3320 }, 3321 /* 3322 * This set of tests looks at using a combination of channel interleaving and 3323 * socket interleaving and makes sure that we handle that correctly when across 3324 * multiple IMCs and sockets. We have four tests per dimm. Two that show that we 3325 * are consistent within the cache line. Two that show that we are consistent 3326 * when we go to a different line. 3327 */ 3328 { 3329 .itc_desc = "2 socket, 4-sock way, 2-channel way (1)", 3330 .itc_imc = &imc_tad_2s_2cw_4sw, 3331 .itc_pa = 0x1ff60007, 3332 .itc_pass = B_TRUE, 3333 .itc_nodeid = 0, 3334 .itc_tadid = 0, 3335 .itc_channelid = 0, 3336 .itc_chanaddr = 0x03fec007, 3337 .itc_dimmid = 0, 3338 .itc_rankid = 0, 3339 .itc_rankaddr = 0x03fec007 3340 }, { 3341 .itc_desc = "2 socket, 4-sock way, 2-channel way (2)", 3342 .itc_imc = &imc_tad_2s_2cw_4sw, 3343 .itc_pa = 0x1ff60023, 3344 .itc_pass = B_TRUE, 3345 .itc_nodeid = 0, 3346 .itc_tadid = 0, 3347 .itc_channelid = 0, 3348 .itc_chanaddr = 0x03fec023, 3349 .itc_dimmid = 0, 3350 .itc_rankid = 0, 3351 .itc_rankaddr = 0x03fec023 3352 }, { 3353 .itc_desc = "2 socket, 4-sock way, 2-channel way (3)", 3354 .itc_imc = &imc_tad_2s_2cw_4sw, 3355 .itc_pa = 0x1ff150007ULL, 3356 .itc_pass = B_TRUE, 3357 .itc_nodeid = 0, 3358 .itc_tadid = 0, 3359 .itc_channelid = 0, 3360 .itc_chanaddr = 0x3fe2a007, 3361 .itc_dimmid = 0, 3362 .itc_rankid = 0, 3363 .itc_rankaddr = 0x3fe2a007 3364 }, { 3365 .itc_desc = "2 socket, 4-sock way, 2-channel way (4)", 3366 .itc_imc = &imc_tad_2s_2cw_4sw, 3367 .itc_pa = 0x1ff150023ULL, 3368 .itc_pass = B_TRUE, 3369 .itc_nodeid = 0, 3370 .itc_tadid = 0, 3371 .itc_channelid = 0, 3372 .itc_chanaddr = 0x3fe2a023, 3373 .itc_dimmid = 0, 3374 .itc_rankid = 0, 3375 .itc_rankaddr = 0x3fe2a023 3376 }, { 3377 .itc_desc = "2 socket, 4-sock way, 2-channel way (5)", 3378 .itc_imc = &imc_tad_2s_2cw_4sw, 3379 .itc_pa = 0x1ff60047, 3380 .itc_pass = B_TRUE, 3381 .itc_nodeid = 0, 3382 .itc_tadid = 1, 3383 .itc_channelid = 1, 3384 .itc_chanaddr = 0x03fec007, 3385 .itc_dimmid = 0, 3386 .itc_rankid = 0, 3387 .itc_rankaddr = 0x03fec007 3388 }, { 3389 .itc_desc = "2 socket, 4-sock way, 2-channel way (6)", 3390 .itc_imc = &imc_tad_2s_2cw_4sw, 3391 .itc_pa = 0x1ff60063, 3392 .itc_pass = B_TRUE, 3393 .itc_nodeid = 0, 3394 .itc_tadid = 1, 3395 .itc_channelid = 1, 3396 .itc_chanaddr = 0x03fec023, 3397 .itc_dimmid = 0, 3398 .itc_rankid = 0, 3399 .itc_rankaddr = 0x03fec023 3400 }, { 3401 .itc_desc = "2 socket, 4-sock way, 2-channel way (7)", 3402 .itc_imc = &imc_tad_2s_2cw_4sw, 3403 .itc_pa = 0x1ff150047ULL, 3404 .itc_pass = B_TRUE, 3405 .itc_nodeid = 0, 3406 .itc_tadid = 1, 3407 .itc_channelid = 1, 3408 .itc_chanaddr = 0x3fe2a007, 3409 .itc_dimmid = 0, 3410 .itc_rankid = 0, 3411 .itc_rankaddr = 0x3fe2a007 3412 }, { 3413 .itc_desc = "2 socket, 4-sock way, 2-channel way (8)", 3414 .itc_imc = &imc_tad_2s_2cw_4sw, 3415 .itc_pa = 0x1ff150063ULL, 3416 .itc_pass = B_TRUE, 3417 .itc_nodeid = 0, 3418 .itc_tadid = 1, 3419 .itc_channelid = 1, 3420 .itc_chanaddr = 0x3fe2a023, 3421 .itc_dimmid = 0, 3422 .itc_rankid = 0, 3423 .itc_rankaddr = 0x3fe2a023 3424 }, { 3425 .itc_desc = "2 socket, 4-sock way, 2-channel way (9)", 3426 .itc_imc = &imc_tad_2s_2cw_4sw, 3427 .itc_pa = 0x1ff60087, 3428 .itc_pass = B_TRUE, 3429 .itc_nodeid = 1, 3430 .itc_tadid = 0, 3431 .itc_channelid = 1, 3432 .itc_chanaddr = 0x03fec007, 3433 .itc_dimmid = 0, 3434 .itc_rankid = 0, 3435 .itc_rankaddr = 0x03fec007 3436 }, { 3437 .itc_desc = "2 socket, 4-sock way, 2-channel way (10)", 3438 .itc_imc = &imc_tad_2s_2cw_4sw, 3439 .itc_pa = 0x1ff600a3, 3440 .itc_pass = B_TRUE, 3441 .itc_nodeid = 1, 3442 .itc_tadid = 0, 3443 .itc_channelid = 1, 3444 .itc_chanaddr = 0x03fec023, 3445 .itc_dimmid = 0, 3446 .itc_rankid = 0, 3447 .itc_rankaddr = 0x03fec023 3448 }, { 3449 .itc_desc = "2 socket, 4-sock way, 2-channel way (11)", 3450 .itc_imc = &imc_tad_2s_2cw_4sw, 3451 .itc_pa = 0x1ff150087ULL, 3452 .itc_pass = B_TRUE, 3453 .itc_nodeid = 1, 3454 .itc_tadid = 0, 3455 .itc_channelid = 1, 3456 .itc_chanaddr = 0x3fe2a007, 3457 .itc_dimmid = 0, 3458 .itc_rankid = 0, 3459 .itc_rankaddr = 0x3fe2a007 3460 }, { 3461 .itc_desc = "2 socket, 4-sock way, 2-channel way (12)", 3462 .itc_imc = &imc_tad_2s_2cw_4sw, 3463 .itc_pa = 0x1ff1500a3ULL, 3464 .itc_pass = B_TRUE, 3465 .itc_nodeid = 1, 3466 .itc_tadid = 0, 3467 .itc_channelid = 1, 3468 .itc_chanaddr = 0x3fe2a023, 3469 .itc_dimmid = 0, 3470 .itc_rankid = 0, 3471 .itc_rankaddr = 0x3fe2a023 3472 }, { 3473 .itc_desc = "2 socket, 4-sock way, 2-channel way (13)", 3474 .itc_imc = &imc_tad_2s_2cw_4sw, 3475 .itc_pa = 0x1ff600c7, 3476 .itc_pass = B_TRUE, 3477 .itc_nodeid = 1, 3478 .itc_tadid = 1, 3479 .itc_channelid = 0, 3480 .itc_chanaddr = 0x03fec007, 3481 .itc_dimmid = 0, 3482 .itc_rankid = 0, 3483 .itc_rankaddr = 0x03fec007 3484 }, { 3485 .itc_desc = "2 socket, 4-sock way, 2-channel way (14)", 3486 .itc_imc = &imc_tad_2s_2cw_4sw, 3487 .itc_pa = 0x1ff600f3, 3488 .itc_pass = B_TRUE, 3489 .itc_nodeid = 1, 3490 .itc_tadid = 1, 3491 .itc_channelid = 0, 3492 .itc_chanaddr = 0x03fec033, 3493 .itc_dimmid = 0, 3494 .itc_rankid = 0, 3495 .itc_rankaddr = 0x03fec033 3496 }, { 3497 .itc_desc = "2 socket, 4-sock way, 2-channel way (15)", 3498 .itc_imc = &imc_tad_2s_2cw_4sw, 3499 .itc_pa = 0x1ff1500c7ULL, 3500 .itc_pass = B_TRUE, 3501 .itc_nodeid = 1, 3502 .itc_tadid = 1, 3503 .itc_channelid = 0, 3504 .itc_chanaddr = 0x3fe2a007, 3505 .itc_dimmid = 0, 3506 .itc_rankid = 0, 3507 .itc_rankaddr = 0x3fe2a007 3508 }, { 3509 .itc_desc = "2 socket, 4-sock way, 2-channel way (16)", 3510 .itc_imc = &imc_tad_2s_2cw_4sw, 3511 .itc_pa = 0x1ff1500f3ULL, 3512 .itc_pass = B_TRUE, 3513 .itc_nodeid = 1, 3514 .itc_tadid = 1, 3515 .itc_channelid = 0, 3516 .itc_chanaddr = 0x3fe2a033, 3517 .itc_dimmid = 0, 3518 .itc_rankid = 0, 3519 .itc_rankaddr = 0x3fe2a033 3520 }, { 3521 .itc_desc = "2 socket, 4-sock way, 2-channel way (17)", 3522 .itc_imc = &imc_tad_2s_2cw_4sw, 3523 .itc_pa = 0x1ff60107, 3524 .itc_pass = B_TRUE, 3525 .itc_nodeid = 0, 3526 .itc_tadid = 0, 3527 .itc_channelid = 1, 3528 .itc_chanaddr = 0x03fec007, 3529 .itc_dimmid = 0, 3530 .itc_rankid = 0, 3531 .itc_rankaddr = 0x03fec007 3532 }, { 3533 .itc_desc = "2 socket, 4-sock way, 2-channel way (18)", 3534 .itc_imc = &imc_tad_2s_2cw_4sw, 3535 .itc_pa = 0x1ff60123, 3536 .itc_pass = B_TRUE, 3537 .itc_nodeid = 0, 3538 .itc_tadid = 0, 3539 .itc_channelid = 1, 3540 .itc_chanaddr = 0x03fec023, 3541 .itc_dimmid = 0, 3542 .itc_rankid = 0, 3543 .itc_rankaddr = 0x03fec023 3544 }, { 3545 .itc_desc = "2 socket, 4-sock way, 2-channel way (19)", 3546 .itc_imc = &imc_tad_2s_2cw_4sw, 3547 .itc_pa = 0x1ff150107ULL, 3548 .itc_pass = B_TRUE, 3549 .itc_nodeid = 0, 3550 .itc_tadid = 0, 3551 .itc_channelid = 1, 3552 .itc_chanaddr = 0x3fe2a007, 3553 .itc_dimmid = 0, 3554 .itc_rankid = 0, 3555 .itc_rankaddr = 0x3fe2a007 3556 }, { 3557 .itc_desc = "2 socket, 4-sock way, 2-channel way (20)", 3558 .itc_imc = &imc_tad_2s_2cw_4sw, 3559 .itc_pa = 0x1ff150123ULL, 3560 .itc_pass = B_TRUE, 3561 .itc_nodeid = 0, 3562 .itc_tadid = 0, 3563 .itc_channelid = 1, 3564 .itc_chanaddr = 0x3fe2a023, 3565 .itc_dimmid = 0, 3566 .itc_rankid = 0, 3567 .itc_rankaddr = 0x3fe2a023 3568 }, { 3569 .itc_desc = "2 socket, 4-sock way, 2-channel way (21)", 3570 .itc_imc = &imc_tad_2s_2cw_4sw, 3571 .itc_pa = 0x1ff60147, 3572 .itc_pass = B_TRUE, 3573 .itc_nodeid = 0, 3574 .itc_tadid = 1, 3575 .itc_channelid = 0, 3576 .itc_chanaddr = 0x03fec007, 3577 .itc_dimmid = 0, 3578 .itc_rankid = 0, 3579 .itc_rankaddr = 0x03fec007 3580 }, { 3581 .itc_desc = "2 socket, 4-sock way, 2-channel way (22)", 3582 .itc_imc = &imc_tad_2s_2cw_4sw, 3583 .itc_pa = 0x1ff60163, 3584 .itc_pass = B_TRUE, 3585 .itc_nodeid = 0, 3586 .itc_tadid = 1, 3587 .itc_channelid = 0, 3588 .itc_chanaddr = 0x03fec023, 3589 .itc_dimmid = 0, 3590 .itc_rankid = 0, 3591 .itc_rankaddr = 0x03fec023 3592 }, { 3593 .itc_desc = "2 socket, 4-sock way, 2-channel way (23)", 3594 .itc_imc = &imc_tad_2s_2cw_4sw, 3595 .itc_pa = 0x1ff150147ULL, 3596 .itc_pass = B_TRUE, 3597 .itc_nodeid = 0, 3598 .itc_tadid = 1, 3599 .itc_channelid = 0, 3600 .itc_chanaddr = 0x3fe2a007, 3601 .itc_dimmid = 0, 3602 .itc_rankid = 0, 3603 .itc_rankaddr = 0x3fe2a007 3604 }, { 3605 .itc_desc = "2 socket, 4-sock way, 2-channel way (24)", 3606 .itc_imc = &imc_tad_2s_2cw_4sw, 3607 .itc_pa = 0x1ff150163ULL, 3608 .itc_pass = B_TRUE, 3609 .itc_nodeid = 0, 3610 .itc_tadid = 1, 3611 .itc_channelid = 0, 3612 .itc_chanaddr = 0x3fe2a023, 3613 .itc_dimmid = 0, 3614 .itc_rankid = 0, 3615 .itc_rankaddr = 0x3fe2a023 3616 }, { 3617 .itc_desc = "2 socket, 4-sock way, 2-channel way (25)", 3618 .itc_imc = &imc_tad_2s_2cw_4sw, 3619 .itc_pa = 0x1ff60187, 3620 .itc_pass = B_TRUE, 3621 .itc_nodeid = 1, 3622 .itc_tadid = 0, 3623 .itc_channelid = 0, 3624 .itc_chanaddr = 0x03fec007, 3625 .itc_dimmid = 0, 3626 .itc_rankid = 0, 3627 .itc_rankaddr = 0x03fec007 3628 }, { 3629 .itc_desc = "2 socket, 4-sock way, 2-channel way (26)", 3630 .itc_imc = &imc_tad_2s_2cw_4sw, 3631 .itc_pa = 0x1ff601a3, 3632 .itc_pass = B_TRUE, 3633 .itc_nodeid = 1, 3634 .itc_tadid = 0, 3635 .itc_channelid = 0, 3636 .itc_chanaddr = 0x03fec023, 3637 .itc_dimmid = 0, 3638 .itc_rankid = 0, 3639 .itc_rankaddr = 0x03fec023 3640 }, { 3641 .itc_desc = "2 socket, 4-sock way, 2-channel way (27)", 3642 .itc_imc = &imc_tad_2s_2cw_4sw, 3643 .itc_pa = 0x1ff150187ULL, 3644 .itc_pass = B_TRUE, 3645 .itc_nodeid = 1, 3646 .itc_tadid = 0, 3647 .itc_channelid = 0, 3648 .itc_chanaddr = 0x3fe2a007, 3649 .itc_dimmid = 0, 3650 .itc_rankid = 0, 3651 .itc_rankaddr = 0x3fe2a007 3652 }, { 3653 .itc_desc = "2 socket, 4-sock way, 2-channel way (28)", 3654 .itc_imc = &imc_tad_2s_2cw_4sw, 3655 .itc_pa = 0x1ff1501a3ULL, 3656 .itc_pass = B_TRUE, 3657 .itc_nodeid = 1, 3658 .itc_tadid = 0, 3659 .itc_channelid = 0, 3660 .itc_chanaddr = 0x3fe2a023, 3661 .itc_dimmid = 0, 3662 .itc_rankid = 0, 3663 .itc_rankaddr = 0x3fe2a023 3664 }, { 3665 .itc_desc = "2 socket, 4-sock way, 2-channel way (29)", 3666 .itc_imc = &imc_tad_2s_2cw_4sw, 3667 .itc_pa = 0x1ff601c7, 3668 .itc_pass = B_TRUE, 3669 .itc_nodeid = 1, 3670 .itc_tadid = 1, 3671 .itc_channelid = 1, 3672 .itc_chanaddr = 0x03fec007, 3673 .itc_dimmid = 0, 3674 .itc_rankid = 0, 3675 .itc_rankaddr = 0x03fec007 3676 }, { 3677 .itc_desc = "2 socket, 4-sock way, 2-channel way (30)", 3678 .itc_imc = &imc_tad_2s_2cw_4sw, 3679 .itc_pa = 0x1ff601f3, 3680 .itc_pass = B_TRUE, 3681 .itc_nodeid = 1, 3682 .itc_tadid = 1, 3683 .itc_channelid = 1, 3684 .itc_chanaddr = 0x03fec033, 3685 .itc_dimmid = 0, 3686 .itc_rankid = 0, 3687 .itc_rankaddr = 0x03fec033 3688 }, { 3689 .itc_desc = "2 socket, 4-sock way, 2-channel way (31)", 3690 .itc_imc = &imc_tad_2s_2cw_4sw, 3691 .itc_pa = 0x1ff1501c7ULL, 3692 .itc_pass = B_TRUE, 3693 .itc_nodeid = 1, 3694 .itc_tadid = 1, 3695 .itc_channelid = 1, 3696 .itc_chanaddr = 0x3fe2a007, 3697 .itc_dimmid = 0, 3698 .itc_rankid = 0, 3699 .itc_rankaddr = 0x3fe2a007 3700 }, { 3701 .itc_desc = "2 socket, 4-sock way, 2-channel way (32)", 3702 .itc_imc = &imc_tad_2s_2cw_4sw, 3703 .itc_pa = 0x1ff1501f3ULL, 3704 .itc_pass = B_TRUE, 3705 .itc_nodeid = 1, 3706 .itc_tadid = 1, 3707 .itc_channelid = 1, 3708 .itc_chanaddr = 0x3fe2a033, 3709 .itc_dimmid = 0, 3710 .itc_rankid = 0, 3711 .itc_rankaddr = 0x3fe2a033 3712 }, 3713 /* 3714 * This begins a series of tests related to Skylake channel granularities. 3715 */ 3716 { 3717 .itc_desc = "SKX 2ch 64b chan gran (1)", 3718 .itc_imc = &imc_skx_64b_gran, 3719 .itc_pa = 0x0c120000, 3720 .itc_pass = B_TRUE, 3721 .itc_nodeid = 0, 3722 .itc_tadid = 0, 3723 .itc_channelid = 0, 3724 .itc_chanaddr = 0x06090000, 3725 .itc_dimmid = 0, 3726 .itc_rankid = 0, 3727 .itc_rankaddr = 0x06090000 3728 }, { 3729 .itc_desc = "SKX 2ch 64b chan gran (2)", 3730 .itc_imc = &imc_skx_64b_gran, 3731 .itc_pa = 0x0c120040, 3732 .itc_pass = B_TRUE, 3733 .itc_nodeid = 0, 3734 .itc_tadid = 0, 3735 .itc_channelid = 1, 3736 .itc_chanaddr = 0x06090000, 3737 .itc_dimmid = 0, 3738 .itc_rankid = 0, 3739 .itc_rankaddr = 0x06090000 3740 }, { 3741 .itc_desc = "SKX 2ch 64b chan gran (3)", 3742 .itc_imc = &imc_skx_64b_gran, 3743 .itc_pa = 0x0c120023, 3744 .itc_pass = B_TRUE, 3745 .itc_nodeid = 0, 3746 .itc_tadid = 0, 3747 .itc_channelid = 0, 3748 .itc_chanaddr = 0x06090023, 3749 .itc_dimmid = 0, 3750 .itc_rankid = 0, 3751 .itc_rankaddr = 0x06090023 3752 }, { 3753 .itc_desc = "SKX 2ch 64b chan gran (4)", 3754 .itc_imc = &imc_skx_64b_gran, 3755 .itc_pa = 0x0c120068, 3756 .itc_pass = B_TRUE, 3757 .itc_nodeid = 0, 3758 .itc_tadid = 0, 3759 .itc_channelid = 1, 3760 .itc_chanaddr = 0x06090028, 3761 .itc_dimmid = 0, 3762 .itc_rankid = 0, 3763 .itc_rankaddr = 0x06090028 3764 }, 3765 /* 3766 * Move onto a 256 byte granularity and repeat. 3767 */ 3768 { 3769 .itc_desc = "SKX 2ch 256b chan gran (1)", 3770 .itc_imc = &imc_skx_256b_gran, 3771 .itc_pa = 0x0c120000, 3772 .itc_pass = B_TRUE, 3773 .itc_nodeid = 0, 3774 .itc_tadid = 0, 3775 .itc_channelid = 0, 3776 .itc_chanaddr = 0x06090000, 3777 .itc_dimmid = 0, 3778 .itc_rankid = 0, 3779 .itc_rankaddr = 0x06090000 3780 }, { 3781 .itc_desc = "SKX 2ch 256b chan gran (2)", 3782 .itc_imc = &imc_skx_256b_gran, 3783 .itc_pa = 0x0c120040, 3784 .itc_pass = B_TRUE, 3785 .itc_nodeid = 0, 3786 .itc_tadid = 0, 3787 .itc_channelid = 0, 3788 .itc_chanaddr = 0x06090040, 3789 .itc_dimmid = 0, 3790 .itc_rankid = 0, 3791 .itc_rankaddr = 0x06090040 3792 }, { 3793 .itc_desc = "SKX 2ch 256b chan gran (3)", 3794 .itc_imc = &imc_skx_256b_gran, 3795 .itc_pa = 0x0c120023, 3796 .itc_pass = B_TRUE, 3797 .itc_nodeid = 0, 3798 .itc_tadid = 0, 3799 .itc_channelid = 0, 3800 .itc_chanaddr = 0x06090023, 3801 .itc_dimmid = 0, 3802 .itc_rankid = 0, 3803 .itc_rankaddr = 0x06090023 3804 }, { 3805 .itc_desc = "SKX 2ch 256b chan gran (4)", 3806 .itc_imc = &imc_skx_256b_gran, 3807 .itc_pa = 0x0c120068, 3808 .itc_pass = B_TRUE, 3809 .itc_nodeid = 0, 3810 .itc_tadid = 0, 3811 .itc_channelid = 0, 3812 .itc_chanaddr = 0x06090068, 3813 .itc_dimmid = 0, 3814 .itc_rankid = 0, 3815 .itc_rankaddr = 0x06090068 3816 }, { 3817 .itc_desc = "SKX 2ch 256b chan gran (5)", 3818 .itc_imc = &imc_skx_256b_gran, 3819 .itc_pa = 0x0c120300, 3820 .itc_pass = B_TRUE, 3821 .itc_nodeid = 0, 3822 .itc_tadid = 0, 3823 .itc_channelid = 1, 3824 .itc_chanaddr = 0x06090100, 3825 .itc_dimmid = 0, 3826 .itc_rankid = 0, 3827 .itc_rankaddr = 0x06090100 3828 }, { 3829 .itc_desc = "SKX 2ch 256b chan gran (6)", 3830 .itc_imc = &imc_skx_256b_gran, 3831 .itc_pa = 0x0c120140, 3832 .itc_pass = B_TRUE, 3833 .itc_nodeid = 0, 3834 .itc_tadid = 0, 3835 .itc_channelid = 1, 3836 .itc_chanaddr = 0x06090040, 3837 .itc_dimmid = 0, 3838 .itc_rankid = 0, 3839 .itc_rankaddr = 0x06090040 3840 }, { 3841 .itc_desc = "SKX 2ch 256b chan gran (7)", 3842 .itc_imc = &imc_skx_256b_gran, 3843 .itc_pa = 0x0c120123, 3844 .itc_pass = B_TRUE, 3845 .itc_nodeid = 0, 3846 .itc_tadid = 0, 3847 .itc_channelid = 1, 3848 .itc_chanaddr = 0x06090023, 3849 .itc_dimmid = 0, 3850 .itc_rankid = 0, 3851 .itc_rankaddr = 0x06090023 3852 }, { 3853 .itc_desc = "SKX 2ch 256b chan gran (8)", 3854 .itc_imc = &imc_skx_256b_gran, 3855 .itc_pa = 0x0c120368, 3856 .itc_pass = B_TRUE, 3857 .itc_nodeid = 0, 3858 .itc_tadid = 0, 3859 .itc_channelid = 1, 3860 .itc_chanaddr = 0x06090168, 3861 .itc_dimmid = 0, 3862 .itc_rankid = 0, 3863 .itc_rankaddr = 0x06090168 3864 }, 3865 /* 3866 * Now, use 4k granularities. 3867 */ 3868 { 3869 .itc_desc = "SKX 2ch 4k chan gran (1)", 3870 .itc_imc = &imc_skx_4k_gran, 3871 .itc_pa = 0x0c120000, 3872 .itc_pass = B_TRUE, 3873 .itc_nodeid = 0, 3874 .itc_tadid = 0, 3875 .itc_channelid = 0, 3876 .itc_chanaddr = 0x06090000, 3877 .itc_dimmid = 0, 3878 .itc_rankid = 0, 3879 .itc_rankaddr = 0x06090000 3880 }, { 3881 .itc_desc = "SKX 2ch 4k chan gran (2)", 3882 .itc_imc = &imc_skx_4k_gran, 3883 .itc_pa = 0x0c120040, 3884 .itc_pass = B_TRUE, 3885 .itc_nodeid = 0, 3886 .itc_tadid = 0, 3887 .itc_channelid = 0, 3888 .itc_chanaddr = 0x06090040, 3889 .itc_dimmid = 0, 3890 .itc_rankid = 0, 3891 .itc_rankaddr = 0x06090040 3892 }, { 3893 .itc_desc = "SKX 2ch 4k chan gran (3)", 3894 .itc_imc = &imc_skx_4k_gran, 3895 .itc_pa = 0x0c120023, 3896 .itc_pass = B_TRUE, 3897 .itc_nodeid = 0, 3898 .itc_tadid = 0, 3899 .itc_channelid = 0, 3900 .itc_chanaddr = 0x06090023, 3901 .itc_dimmid = 0, 3902 .itc_rankid = 0, 3903 .itc_rankaddr = 0x06090023 3904 }, { 3905 .itc_desc = "SKX 2ch 4k chan gran (4)", 3906 .itc_imc = &imc_skx_4k_gran, 3907 .itc_pa = 0x0c120068, 3908 .itc_pass = B_TRUE, 3909 .itc_nodeid = 0, 3910 .itc_tadid = 0, 3911 .itc_channelid = 0, 3912 .itc_chanaddr = 0x06090068, 3913 .itc_dimmid = 0, 3914 .itc_rankid = 0, 3915 .itc_rankaddr = 0x06090068 3916 }, { 3917 .itc_desc = "SKX 2ch 4k chan gran (5)", 3918 .itc_imc = &imc_skx_4k_gran, 3919 .itc_pa = 0x0c120300, 3920 .itc_pass = B_TRUE, 3921 .itc_nodeid = 0, 3922 .itc_tadid = 0, 3923 .itc_channelid = 0, 3924 .itc_chanaddr = 0x06090300, 3925 .itc_dimmid = 0, 3926 .itc_rankid = 0, 3927 .itc_rankaddr = 0x06090300 3928 }, { 3929 .itc_desc = "SKX 2ch 4k chan gran (6)", 3930 .itc_imc = &imc_skx_4k_gran, 3931 .itc_pa = 0x0c120140, 3932 .itc_pass = B_TRUE, 3933 .itc_nodeid = 0, 3934 .itc_tadid = 0, 3935 .itc_channelid = 0, 3936 .itc_chanaddr = 0x06090140, 3937 .itc_dimmid = 0, 3938 .itc_rankid = 0, 3939 .itc_rankaddr = 0x06090140 3940 }, { 3941 .itc_desc = "SKX 2ch 4k chan gran (7)", 3942 .itc_imc = &imc_skx_4k_gran, 3943 .itc_pa = 0x0c120123, 3944 .itc_pass = B_TRUE, 3945 .itc_nodeid = 0, 3946 .itc_tadid = 0, 3947 .itc_channelid = 0, 3948 .itc_chanaddr = 0x06090123, 3949 .itc_dimmid = 0, 3950 .itc_rankid = 0, 3951 .itc_rankaddr = 0x06090123 3952 }, { 3953 .itc_desc = "SKX 2ch 4k chan gran (8)", 3954 .itc_imc = &imc_skx_4k_gran, 3955 .itc_pa = 0x0c120368, 3956 .itc_pass = B_TRUE, 3957 .itc_nodeid = 0, 3958 .itc_tadid = 0, 3959 .itc_channelid = 0, 3960 .itc_chanaddr = 0x06090368, 3961 .itc_dimmid = 0, 3962 .itc_rankid = 0, 3963 .itc_rankaddr = 0x06090368 3964 }, { 3965 .itc_desc = "SKX 2ch 4k chan gran (9)", 3966 .itc_imc = &imc_skx_4k_gran, 3967 .itc_pa = 0x0c121000, 3968 .itc_pass = B_TRUE, 3969 .itc_nodeid = 0, 3970 .itc_tadid = 0, 3971 .itc_channelid = 1, 3972 .itc_chanaddr = 0x06090000, 3973 .itc_dimmid = 0, 3974 .itc_rankid = 0, 3975 .itc_rankaddr = 0x06090000 3976 }, { 3977 .itc_desc = "SKX 2ch 4k chan gran (10)", 3978 .itc_imc = &imc_skx_4k_gran, 3979 .itc_pa = 0x0c123040, 3980 .itc_pass = B_TRUE, 3981 .itc_nodeid = 0, 3982 .itc_tadid = 0, 3983 .itc_channelid = 1, 3984 .itc_chanaddr = 0x06091040, 3985 .itc_dimmid = 0, 3986 .itc_rankid = 0, 3987 .itc_rankaddr = 0x06091040 3988 }, { 3989 .itc_desc = "SKX 2ch 4k chan gran (11)", 3990 .itc_imc = &imc_skx_4k_gran, 3991 .itc_pa = 0x0c121023, 3992 .itc_pass = B_TRUE, 3993 .itc_nodeid = 0, 3994 .itc_tadid = 0, 3995 .itc_channelid = 1, 3996 .itc_chanaddr = 0x06090023, 3997 .itc_dimmid = 0, 3998 .itc_rankid = 0, 3999 .itc_rankaddr = 0x06090023 4000 }, { 4001 .itc_desc = "SKX 2ch 4k chan gran (12)", 4002 .itc_imc = &imc_skx_4k_gran, 4003 .itc_pa = 0x0c121068, 4004 .itc_pass = B_TRUE, 4005 .itc_nodeid = 0, 4006 .itc_tadid = 0, 4007 .itc_channelid = 1, 4008 .itc_chanaddr = 0x06090068, 4009 .itc_dimmid = 0, 4010 .itc_rankid = 0, 4011 .itc_rankaddr = 0x06090068 4012 }, { 4013 .itc_desc = "SKX 2ch 4k chan gran (13)", 4014 .itc_imc = &imc_skx_4k_gran, 4015 .itc_pa = 0x0c121300, 4016 .itc_pass = B_TRUE, 4017 .itc_nodeid = 0, 4018 .itc_tadid = 0, 4019 .itc_channelid = 1, 4020 .itc_chanaddr = 0x06090300, 4021 .itc_dimmid = 0, 4022 .itc_rankid = 0, 4023 .itc_rankaddr = 0x06090300 4024 }, { 4025 .itc_desc = "SKX 2ch 4k chan gran (14)", 4026 .itc_imc = &imc_skx_4k_gran, 4027 .itc_pa = 0x0c121140, 4028 .itc_pass = B_TRUE, 4029 .itc_nodeid = 0, 4030 .itc_tadid = 0, 4031 .itc_channelid = 1, 4032 .itc_chanaddr = 0x06090140, 4033 .itc_dimmid = 0, 4034 .itc_rankid = 0, 4035 .itc_rankaddr = 0x06090140 4036 }, { 4037 .itc_desc = "SKX 2ch 4k chan gran (15)", 4038 .itc_imc = &imc_skx_4k_gran, 4039 .itc_pa = 0x0c123123, 4040 .itc_pass = B_TRUE, 4041 .itc_nodeid = 0, 4042 .itc_tadid = 0, 4043 .itc_channelid = 1, 4044 .itc_chanaddr = 0x06091123, 4045 .itc_dimmid = 0, 4046 .itc_rankid = 0, 4047 .itc_rankaddr = 0x06091123 4048 }, { 4049 .itc_desc = "SKX 2ch 4k chan gran (16)", 4050 .itc_imc = &imc_skx_4k_gran, 4051 .itc_pa = 0x0c121368, 4052 .itc_pass = B_TRUE, 4053 .itc_nodeid = 0, 4054 .itc_tadid = 0, 4055 .itc_channelid = 1, 4056 .itc_chanaddr = 0x06090368, 4057 .itc_dimmid = 0, 4058 .itc_rankid = 0, 4059 .itc_rankaddr = 0x06090368 4060 }, 4061 /* 4062 * Use a 1 GiB Interleaving next. 4063 */ 4064 { 4065 .itc_desc = "SKX 2ch 1g chan gran (1)", 4066 .itc_imc = &imc_skx_1g_gran, 4067 .itc_pa = 0x0c120000, 4068 .itc_pass = B_TRUE, 4069 .itc_nodeid = 0, 4070 .itc_tadid = 0, 4071 .itc_channelid = 0, 4072 .itc_chanaddr = 0x0c120000, 4073 .itc_dimmid = 0, 4074 .itc_rankid = 0, 4075 .itc_rankaddr = 0x0c120000 4076 }, { 4077 .itc_desc = "SKX 2ch 1g chan gran (2)", 4078 .itc_imc = &imc_skx_1g_gran, 4079 .itc_pa = 0x0c120040, 4080 .itc_pass = B_TRUE, 4081 .itc_nodeid = 0, 4082 .itc_tadid = 0, 4083 .itc_channelid = 0, 4084 .itc_chanaddr = 0x0c120040, 4085 .itc_dimmid = 0, 4086 .itc_rankid = 0, 4087 .itc_rankaddr = 0x0c120040 4088 }, { 4089 .itc_desc = "SKX 2ch 1g chan gran (3)", 4090 .itc_imc = &imc_skx_1g_gran, 4091 .itc_pa = 0x0c120023, 4092 .itc_pass = B_TRUE, 4093 .itc_nodeid = 0, 4094 .itc_tadid = 0, 4095 .itc_channelid = 0, 4096 .itc_chanaddr = 0x0c120023, 4097 .itc_dimmid = 0, 4098 .itc_rankid = 0, 4099 .itc_rankaddr = 0x0c120023 4100 }, { 4101 .itc_desc = "SKX 2ch 1g chan gran (4)", 4102 .itc_imc = &imc_skx_1g_gran, 4103 .itc_pa = 0x0c120068, 4104 .itc_pass = B_TRUE, 4105 .itc_nodeid = 0, 4106 .itc_tadid = 0, 4107 .itc_channelid = 0, 4108 .itc_chanaddr = 0x0c120068, 4109 .itc_dimmid = 0, 4110 .itc_rankid = 0, 4111 .itc_rankaddr = 0x0c120068 4112 }, { 4113 .itc_desc = "SKX 2ch 1g chan gran (5)", 4114 .itc_imc = &imc_skx_1g_gran, 4115 .itc_pa = 0x0c120300, 4116 .itc_pass = B_TRUE, 4117 .itc_nodeid = 0, 4118 .itc_tadid = 0, 4119 .itc_channelid = 0, 4120 .itc_chanaddr = 0x0c120300, 4121 .itc_dimmid = 0, 4122 .itc_rankid = 0, 4123 .itc_rankaddr = 0x0c120300 4124 }, { 4125 .itc_desc = "SKX 2ch 1g chan gran (6)", 4126 .itc_imc = &imc_skx_1g_gran, 4127 .itc_pa = 0x0c120140, 4128 .itc_pass = B_TRUE, 4129 .itc_nodeid = 0, 4130 .itc_tadid = 0, 4131 .itc_channelid = 0, 4132 .itc_chanaddr = 0x0c120140, 4133 .itc_dimmid = 0, 4134 .itc_rankid = 0, 4135 .itc_rankaddr = 0x0c120140 4136 }, { 4137 .itc_desc = "SKX 2ch 1g chan gran (7)", 4138 .itc_imc = &imc_skx_1g_gran, 4139 .itc_pa = 0x0c120123, 4140 .itc_pass = B_TRUE, 4141 .itc_nodeid = 0, 4142 .itc_tadid = 0, 4143 .itc_channelid = 0, 4144 .itc_chanaddr = 0x0c120123, 4145 .itc_dimmid = 0, 4146 .itc_rankid = 0, 4147 .itc_rankaddr = 0x0c120123 4148 }, { 4149 .itc_desc = "SKX 2ch 1g chan gran (8)", 4150 .itc_imc = &imc_skx_1g_gran, 4151 .itc_pa = 0x0c120368, 4152 .itc_pass = B_TRUE, 4153 .itc_nodeid = 0, 4154 .itc_tadid = 0, 4155 .itc_channelid = 0, 4156 .itc_chanaddr = 0x0c120368, 4157 .itc_dimmid = 0, 4158 .itc_rankid = 0, 4159 .itc_rankaddr = 0x0c120368 4160 }, { 4161 .itc_desc = "SKX 2ch 1g chan gran (9)", 4162 .itc_imc = &imc_skx_1g_gran, 4163 .itc_pa = 0x0c121000, 4164 .itc_pass = B_TRUE, 4165 .itc_nodeid = 0, 4166 .itc_tadid = 0, 4167 .itc_channelid = 0, 4168 .itc_chanaddr = 0x0c121000, 4169 .itc_dimmid = 0, 4170 .itc_rankid = 0, 4171 .itc_rankaddr = 0x0c121000 4172 }, { 4173 .itc_desc = "SKX 2ch 1g chan gran (10)", 4174 .itc_imc = &imc_skx_1g_gran, 4175 .itc_pa = 0x0c123040, 4176 .itc_pass = B_TRUE, 4177 .itc_nodeid = 0, 4178 .itc_tadid = 0, 4179 .itc_channelid = 0, 4180 .itc_chanaddr = 0x0c123040, 4181 .itc_dimmid = 0, 4182 .itc_rankid = 0, 4183 .itc_rankaddr = 0x0c123040 4184 }, { 4185 .itc_desc = "SKX 2ch 1g chan gran (11)", 4186 .itc_imc = &imc_skx_1g_gran, 4187 .itc_pa = 0x0c121023, 4188 .itc_pass = B_TRUE, 4189 .itc_nodeid = 0, 4190 .itc_tadid = 0, 4191 .itc_channelid = 0, 4192 .itc_chanaddr = 0x0c121023, 4193 .itc_dimmid = 0, 4194 .itc_rankid = 0, 4195 .itc_rankaddr = 0x0c121023 4196 }, { 4197 .itc_desc = "SKX 2ch 1g chan gran (12)", 4198 .itc_imc = &imc_skx_1g_gran, 4199 .itc_pa = 0x0c121068, 4200 .itc_pass = B_TRUE, 4201 .itc_nodeid = 0, 4202 .itc_tadid = 0, 4203 .itc_channelid = 0, 4204 .itc_chanaddr = 0x0c121068, 4205 .itc_dimmid = 0, 4206 .itc_rankid = 0, 4207 .itc_rankaddr = 0x0c121068 4208 }, { 4209 .itc_desc = "SKX 2ch 1g chan gran (13)", 4210 .itc_imc = &imc_skx_1g_gran, 4211 .itc_pa = 0x0c121300, 4212 .itc_pass = B_TRUE, 4213 .itc_nodeid = 0, 4214 .itc_tadid = 0, 4215 .itc_channelid = 0, 4216 .itc_chanaddr = 0x0c121300, 4217 .itc_dimmid = 0, 4218 .itc_rankid = 0, 4219 .itc_rankaddr = 0x0c121300 4220 }, { 4221 .itc_desc = "SKX 2ch 1g chan gran (14)", 4222 .itc_imc = &imc_skx_1g_gran, 4223 .itc_pa = 0x0c121140, 4224 .itc_pass = B_TRUE, 4225 .itc_nodeid = 0, 4226 .itc_tadid = 0, 4227 .itc_channelid = 0, 4228 .itc_chanaddr = 0x0c121140, 4229 .itc_dimmid = 0, 4230 .itc_rankid = 0, 4231 .itc_rankaddr = 0x0c121140 4232 }, { 4233 .itc_desc = "SKX 2ch 1g chan gran (15)", 4234 .itc_imc = &imc_skx_1g_gran, 4235 .itc_pa = 0x0c123123, 4236 .itc_pass = B_TRUE, 4237 .itc_nodeid = 0, 4238 .itc_tadid = 0, 4239 .itc_channelid = 0, 4240 .itc_chanaddr = 0x0c123123, 4241 .itc_dimmid = 0, 4242 .itc_rankid = 0, 4243 .itc_rankaddr = 0x0c123123 4244 }, { 4245 .itc_desc = "SKX 2ch 1g chan gran (16)", 4246 .itc_imc = &imc_skx_1g_gran, 4247 .itc_pa = 0x0c121368, 4248 .itc_pass = B_TRUE, 4249 .itc_nodeid = 0, 4250 .itc_tadid = 0, 4251 .itc_channelid = 0, 4252 .itc_chanaddr = 0x0c121368, 4253 .itc_dimmid = 0, 4254 .itc_rankid = 0, 4255 .itc_rankaddr = 0x0c121368 4256 }, { 4257 .itc_desc = "SKX 2ch 1g chan gran (1)", 4258 .itc_imc = &imc_skx_1g_gran, 4259 .itc_pa = 0x4c120000, 4260 .itc_pass = B_TRUE, 4261 .itc_nodeid = 0, 4262 .itc_tadid = 0, 4263 .itc_channelid = 1, 4264 .itc_chanaddr = 0x0c120000, 4265 .itc_dimmid = 0, 4266 .itc_rankid = 0, 4267 .itc_rankaddr = 0x0c120000 4268 }, { 4269 .itc_desc = "SKX 2ch 1g chan gran (2)", 4270 .itc_imc = &imc_skx_1g_gran, 4271 .itc_pa = 0x4c120040, 4272 .itc_pass = B_TRUE, 4273 .itc_nodeid = 0, 4274 .itc_tadid = 0, 4275 .itc_channelid = 1, 4276 .itc_chanaddr = 0x0c120040, 4277 .itc_dimmid = 0, 4278 .itc_rankid = 0, 4279 .itc_rankaddr = 0x0c120040 4280 }, { 4281 .itc_desc = "SKX 2ch 1g chan gran (3)", 4282 .itc_imc = &imc_skx_1g_gran, 4283 .itc_pa = 0x5c120023, 4284 .itc_pass = B_TRUE, 4285 .itc_nodeid = 0, 4286 .itc_tadid = 0, 4287 .itc_channelid = 1, 4288 .itc_chanaddr = 0x1c120023, 4289 .itc_dimmid = 0, 4290 .itc_rankid = 0, 4291 .itc_rankaddr = 0x1c120023 4292 }, { 4293 .itc_desc = "SKX 2ch 1g chan gran (4)", 4294 .itc_imc = &imc_skx_1g_gran, 4295 .itc_pa = 0x6c120068, 4296 .itc_pass = B_TRUE, 4297 .itc_nodeid = 0, 4298 .itc_tadid = 0, 4299 .itc_channelid = 1, 4300 .itc_chanaddr = 0x2c120068, 4301 .itc_dimmid = 0, 4302 .itc_rankid = 0, 4303 .itc_rankaddr = 0x2c120068 4304 }, { 4305 .itc_desc = "SKX 2ch 1g chan gran (5)", 4306 .itc_imc = &imc_skx_1g_gran, 4307 .itc_pa = 0x7c120300, 4308 .itc_pass = B_TRUE, 4309 .itc_nodeid = 0, 4310 .itc_tadid = 0, 4311 .itc_channelid = 1, 4312 .itc_chanaddr = 0x3c120300, 4313 .itc_dimmid = 0, 4314 .itc_rankid = 0, 4315 .itc_rankaddr = 0x3c120300 4316 }, { 4317 .itc_desc = "SKX 2ch 1g chan gran (6)", 4318 .itc_imc = &imc_skx_1g_gran, 4319 .itc_pa = 0x4c120140, 4320 .itc_pass = B_TRUE, 4321 .itc_nodeid = 0, 4322 .itc_tadid = 0, 4323 .itc_channelid = 1, 4324 .itc_chanaddr = 0x0c120140, 4325 .itc_dimmid = 0, 4326 .itc_rankid = 0, 4327 .itc_rankaddr = 0x0c120140 4328 }, { 4329 .itc_desc = "SKX 2ch 1g chan gran (7)", 4330 .itc_imc = &imc_skx_1g_gran, 4331 .itc_pa = 0x5c120123, 4332 .itc_pass = B_TRUE, 4333 .itc_nodeid = 0, 4334 .itc_tadid = 0, 4335 .itc_channelid = 1, 4336 .itc_chanaddr = 0x1c120123, 4337 .itc_dimmid = 0, 4338 .itc_rankid = 0, 4339 .itc_rankaddr = 0x1c120123 4340 }, { 4341 .itc_desc = "SKX 2ch 1g chan gran (8)", 4342 .itc_imc = &imc_skx_1g_gran, 4343 .itc_pa = 0x6c120368, 4344 .itc_pass = B_TRUE, 4345 .itc_nodeid = 0, 4346 .itc_tadid = 0, 4347 .itc_channelid = 1, 4348 .itc_chanaddr = 0x2c120368, 4349 .itc_dimmid = 0, 4350 .itc_rankid = 0, 4351 .itc_rankaddr = 0x2c120368 4352 }, { 4353 .itc_desc = "SKX 2ch 1g chan gran (9)", 4354 .itc_imc = &imc_skx_1g_gran, 4355 .itc_pa = 0x7c121000, 4356 .itc_pass = B_TRUE, 4357 .itc_nodeid = 0, 4358 .itc_tadid = 0, 4359 .itc_channelid = 1, 4360 .itc_chanaddr = 0x3c121000, 4361 .itc_dimmid = 0, 4362 .itc_rankid = 0, 4363 .itc_rankaddr = 0x3c121000 4364 }, { 4365 .itc_desc = "SKX 2ch 1g chan gran (10)", 4366 .itc_imc = &imc_skx_1g_gran, 4367 .itc_pa = 0x4c123040, 4368 .itc_pass = B_TRUE, 4369 .itc_nodeid = 0, 4370 .itc_tadid = 0, 4371 .itc_channelid = 1, 4372 .itc_chanaddr = 0x0c123040, 4373 .itc_dimmid = 0, 4374 .itc_rankid = 0, 4375 .itc_rankaddr = 0x0c123040 4376 }, { 4377 .itc_desc = "SKX 2ch 1g chan gran (11)", 4378 .itc_imc = &imc_skx_1g_gran, 4379 .itc_pa = 0x5c121023, 4380 .itc_pass = B_TRUE, 4381 .itc_nodeid = 0, 4382 .itc_tadid = 0, 4383 .itc_channelid = 1, 4384 .itc_chanaddr = 0x1c121023, 4385 .itc_dimmid = 0, 4386 .itc_rankid = 0, 4387 .itc_rankaddr = 0x1c121023 4388 }, { 4389 .itc_desc = "SKX 2ch 1g chan gran (12)", 4390 .itc_imc = &imc_skx_1g_gran, 4391 .itc_pa = 0x6c121068, 4392 .itc_pass = B_TRUE, 4393 .itc_nodeid = 0, 4394 .itc_tadid = 0, 4395 .itc_channelid = 1, 4396 .itc_chanaddr = 0x2c121068, 4397 .itc_dimmid = 0, 4398 .itc_rankid = 0, 4399 .itc_rankaddr = 0x2c121068 4400 }, { 4401 .itc_desc = "SKX 2ch 1g chan gran (13)", 4402 .itc_imc = &imc_skx_1g_gran, 4403 .itc_pa = 0x7c121300, 4404 .itc_pass = B_TRUE, 4405 .itc_nodeid = 0, 4406 .itc_tadid = 0, 4407 .itc_channelid = 1, 4408 .itc_chanaddr = 0x3c121300, 4409 .itc_dimmid = 0, 4410 .itc_rankid = 0, 4411 .itc_rankaddr = 0x3c121300 4412 }, { 4413 .itc_desc = "SKX 2ch 1g chan gran (14)", 4414 .itc_imc = &imc_skx_1g_gran, 4415 .itc_pa = 0x7c121140, 4416 .itc_pass = B_TRUE, 4417 .itc_nodeid = 0, 4418 .itc_tadid = 0, 4419 .itc_channelid = 1, 4420 .itc_chanaddr = 0x3c121140, 4421 .itc_dimmid = 0, 4422 .itc_rankid = 0, 4423 .itc_rankaddr = 0x3c121140 4424 }, { 4425 .itc_desc = "SKX 2ch 1g chan gran (15)", 4426 .itc_imc = &imc_skx_1g_gran, 4427 .itc_pa = 0x6c123123, 4428 .itc_pass = B_TRUE, 4429 .itc_nodeid = 0, 4430 .itc_tadid = 0, 4431 .itc_channelid = 1, 4432 .itc_chanaddr = 0x2c123123, 4433 .itc_dimmid = 0, 4434 .itc_rankid = 0, 4435 .itc_rankaddr = 0x2c123123 4436 }, { 4437 .itc_desc = "SKX 2ch 1g chan gran (16)", 4438 .itc_imc = &imc_skx_1g_gran, 4439 .itc_pa = 0x5c121368, 4440 .itc_pass = B_TRUE, 4441 .itc_nodeid = 0, 4442 .itc_tadid = 0, 4443 .itc_channelid = 1, 4444 .itc_chanaddr = 0x1c121368, 4445 .itc_dimmid = 0, 4446 .itc_rankid = 0, 4447 .itc_rankaddr = 0x1c121368 4448 }, 4449 /* 4450 * This round of tests puts together a 1 socekt configuration with 4 channel way 4451 * interleaving. This means that we're interleaving across two IMCs in the same 4452 * socket. 4453 */ 4454 { 4455 .itc_desc = "1 socket, 4-channel way (1)", 4456 .itc_imc = &imc_tad_1s_4cw, 4457 .itc_pa = 0x0ff13006, 4458 .itc_pass = B_TRUE, 4459 .itc_nodeid = 0, 4460 .itc_tadid = 0, 4461 .itc_channelid = 0, 4462 .itc_chanaddr = 0x03fc4c06, 4463 .itc_dimmid = 0, 4464 .itc_rankid = 0, 4465 .itc_rankaddr = 0x03fc4c06 4466 }, { 4467 .itc_desc = "1 socket, 4-channel way (2)", 4468 .itc_imc = &imc_tad_1s_4cw, 4469 .itc_pa = 0x0ff13046, 4470 .itc_pass = B_TRUE, 4471 .itc_nodeid = 0, 4472 .itc_tadid = 0, 4473 .itc_channelid = 1, 4474 .itc_chanaddr = 0x03fc4c06, 4475 .itc_dimmid = 0, 4476 .itc_rankid = 0, 4477 .itc_rankaddr = 0x03fc4c06 4478 }, { 4479 .itc_desc = "1 socket, 4-channel way (3)", 4480 .itc_imc = &imc_tad_1s_4cw, 4481 .itc_pa = 0x0ff13086, 4482 .itc_pass = B_TRUE, 4483 .itc_nodeid = 0, 4484 .itc_tadid = 1, 4485 .itc_channelid = 1, 4486 .itc_chanaddr = 0x03fc4c06, 4487 .itc_dimmid = 0, 4488 .itc_rankid = 0, 4489 .itc_rankaddr = 0x03fc4c06 4490 }, { 4491 .itc_desc = "1 socket, 4-channel way (4)", 4492 .itc_imc = &imc_tad_1s_4cw, 4493 .itc_pa = 0x0ff130c6, 4494 .itc_pass = B_TRUE, 4495 .itc_nodeid = 0, 4496 .itc_tadid = 1, 4497 .itc_channelid = 0, 4498 .itc_chanaddr = 0x03fc4c06, 4499 .itc_dimmid = 0, 4500 .itc_rankid = 0, 4501 .itc_rankaddr = 0x03fc4c06 4502 }, { 4503 .itc_desc = "1 socket, 4-channel way (5)", 4504 .itc_imc = &imc_tad_1s_4cw, 4505 .itc_pa = 0x0ff13026, 4506 .itc_pass = B_TRUE, 4507 .itc_nodeid = 0, 4508 .itc_tadid = 0, 4509 .itc_channelid = 0, 4510 .itc_chanaddr = 0x03fc4c26, 4511 .itc_dimmid = 0, 4512 .itc_rankid = 0, 4513 .itc_rankaddr = 0x03fc4c26 4514 }, { 4515 .itc_desc = "1 socket, 4-channel way (6)", 4516 .itc_imc = &imc_tad_1s_4cw, 4517 .itc_pa = 0x0ff13077, 4518 .itc_pass = B_TRUE, 4519 .itc_nodeid = 0, 4520 .itc_tadid = 0, 4521 .itc_channelid = 1, 4522 .itc_chanaddr = 0x03fc4c37, 4523 .itc_dimmid = 0, 4524 .itc_rankid = 0, 4525 .itc_rankaddr = 0x03fc4c37 4526 }, { 4527 .itc_desc = "1 socket, 4-channel way (7)", 4528 .itc_imc = &imc_tad_1s_4cw, 4529 .itc_pa = 0x0ff13099, 4530 .itc_pass = B_TRUE, 4531 .itc_nodeid = 0, 4532 .itc_tadid = 1, 4533 .itc_channelid = 1, 4534 .itc_chanaddr = 0x03fc4c19, 4535 .itc_dimmid = 0, 4536 .itc_rankid = 0, 4537 .itc_rankaddr = 0x03fc4c19 4538 }, { 4539 .itc_desc = "1 socket, 4-channel way (8)", 4540 .itc_imc = &imc_tad_1s_4cw, 4541 .itc_pa = 0x0ff130ff, 4542 .itc_pass = B_TRUE, 4543 .itc_nodeid = 0, 4544 .itc_tadid = 1, 4545 .itc_channelid = 0, 4546 .itc_chanaddr = 0x03fc4c3f, 4547 .itc_dimmid = 0, 4548 .itc_rankid = 0, 4549 .itc_rankaddr = 0x03fc4c3f 4550 }, { 4551 .itc_desc = "1 socket, 4-channel way (9)", 4552 .itc_imc = &imc_tad_1s_4cw, 4553 .itc_pa = 0x8ff13006, 4554 .itc_pass = B_TRUE, 4555 .itc_nodeid = 0, 4556 .itc_tadid = 0, 4557 .itc_channelid = 0, 4558 .itc_chanaddr = 0x23fc4c06, 4559 .itc_dimmid = 0, 4560 .itc_rankid = 0, 4561 .itc_rankaddr = 0x23fc4c06 4562 }, { 4563 .itc_desc = "1 socket, 4-channel way (10)", 4564 .itc_imc = &imc_tad_1s_4cw, 4565 .itc_pa = 0x3ff13046, 4566 .itc_pass = B_TRUE, 4567 .itc_nodeid = 0, 4568 .itc_tadid = 0, 4569 .itc_channelid = 1, 4570 .itc_chanaddr = 0x0ffc4c06, 4571 .itc_dimmid = 0, 4572 .itc_rankid = 0, 4573 .itc_rankaddr = 0x0ffc4c06 4574 }, { 4575 .itc_desc = "1 socket, 4-channel way (11)", 4576 .itc_imc = &imc_tad_1s_4cw, 4577 .itc_pa = 0x4ff13086, 4578 .itc_pass = B_TRUE, 4579 .itc_nodeid = 0, 4580 .itc_tadid = 1, 4581 .itc_channelid = 1, 4582 .itc_chanaddr = 0x13fc4c06, 4583 .itc_dimmid = 0, 4584 .itc_rankid = 0, 4585 .itc_rankaddr = 0x13fc4c06 4586 }, { 4587 .itc_desc = "1 socket, 4-channel way (12)", 4588 .itc_imc = &imc_tad_1s_4cw, 4589 .itc_pa = 0x9ff130c6, 4590 .itc_pass = B_TRUE, 4591 .itc_nodeid = 0, 4592 .itc_tadid = 1, 4593 .itc_channelid = 0, 4594 .itc_chanaddr = 0x27fc4c06, 4595 .itc_dimmid = 0, 4596 .itc_rankid = 0, 4597 .itc_rankaddr = 0x27fc4c06 4598 }, { 4599 .itc_desc = "1 socket, 4-channel way (13)", 4600 .itc_imc = &imc_tad_1s_4cw, 4601 .itc_pa = 0xdff13026, 4602 .itc_pass = B_TRUE, 4603 .itc_nodeid = 0, 4604 .itc_tadid = 0, 4605 .itc_channelid = 0, 4606 .itc_chanaddr = 0x37fc4c26, 4607 .itc_dimmid = 0, 4608 .itc_rankid = 0, 4609 .itc_rankaddr = 0x37fc4c26 4610 }, { 4611 .itc_desc = "1 socket, 4-channel way (14)", 4612 .itc_imc = &imc_tad_1s_4cw, 4613 .itc_pa = 0xeff13077, 4614 .itc_pass = B_TRUE, 4615 .itc_nodeid = 0, 4616 .itc_tadid = 0, 4617 .itc_channelid = 1, 4618 .itc_chanaddr = 0x3bfc4c37, 4619 .itc_dimmid = 0, 4620 .itc_rankid = 0, 4621 .itc_rankaddr = 0x3bfc4c37 4622 }, { 4623 .itc_desc = "1 socket, 4-channel way (15)", 4624 .itc_imc = &imc_tad_1s_4cw, 4625 .itc_pa = 0x4ff13099, 4626 .itc_pass = B_TRUE, 4627 .itc_nodeid = 0, 4628 .itc_tadid = 1, 4629 .itc_channelid = 1, 4630 .itc_chanaddr = 0x13fc4c19, 4631 .itc_dimmid = 0, 4632 .itc_rankid = 0, 4633 .itc_rankaddr = 0x13fc4c19 4634 }, { 4635 .itc_desc = "1 socket, 4-channel way (16)", 4636 .itc_imc = &imc_tad_1s_4cw, 4637 .itc_pa = 0x8ff130ff, 4638 .itc_pass = B_TRUE, 4639 .itc_nodeid = 0, 4640 .itc_tadid = 1, 4641 .itc_channelid = 0, 4642 .itc_chanaddr = 0x23fc4c3f, 4643 .itc_dimmid = 0, 4644 .itc_rankid = 0, 4645 .itc_rankaddr = 0x23fc4c3f 4646 }, 4647 /* 4648 * Test the first variation of mod3 rules. We basically try to find addresses 4649 * that map to all 6 channels and then do different variations thereof. We 4650 * mostly use the addresses from the previous test run to get a good random 4651 * smattering of addresses. 4652 */ 4653 { 4654 .itc_desc = "1s mod 3 45t6 (1)", 4655 .itc_imc = &imc_tad_skx_mod3_45t6, 4656 .itc_pa = 0x0ff13006, 4657 .itc_pass = B_TRUE, 4658 .itc_nodeid = 0, 4659 .itc_tadid = 0, 4660 .itc_channelid = 2, 4661 .itc_chanaddr = 0x03fc4c06, 4662 .itc_dimmid = 0, 4663 .itc_rankid = 0, 4664 .itc_rankaddr = 0x03fc4c06 4665 }, { 4666 .itc_desc = "1s mod 3 45t6 (2)", 4667 .itc_imc = &imc_tad_skx_mod3_45t6, 4668 .itc_pa = 0x0ff13046, 4669 .itc_pass = B_TRUE, 4670 .itc_nodeid = 0, 4671 .itc_tadid = 1, 4672 .itc_channelid = 0, 4673 .itc_chanaddr = 0x03fc4c06, 4674 .itc_dimmid = 0, 4675 .itc_rankid = 0, 4676 .itc_rankaddr = 0x03fc4c06 4677 }, { 4678 .itc_desc = "1s mod 3 45t6 (3)", 4679 .itc_imc = &imc_tad_skx_mod3_45t6, 4680 .itc_pa = 0x0ff13086, 4681 .itc_pass = B_TRUE, 4682 .itc_nodeid = 0, 4683 .itc_tadid = 0, 4684 .itc_channelid = 0, 4685 .itc_chanaddr = 0x03fc4c06, 4686 .itc_dimmid = 0, 4687 .itc_rankid = 0, 4688 .itc_rankaddr = 0x03fc4c06 4689 }, { 4690 .itc_desc = "1s mod 3 45t6 (4)", 4691 .itc_imc = &imc_tad_skx_mod3_45t6, 4692 .itc_pa = 0x0ff130c6, 4693 .itc_pass = B_TRUE, 4694 .itc_nodeid = 0, 4695 .itc_tadid = 1, 4696 .itc_channelid = 2, 4697 .itc_chanaddr = 0x03fc4c06, 4698 .itc_dimmid = 0, 4699 .itc_rankid = 0, 4700 .itc_rankaddr = 0x03fc4c06 4701 }, { 4702 .itc_desc = "1s mod 3 45t6 (5)", 4703 .itc_imc = &imc_tad_skx_mod3_45t6, 4704 .itc_pa = 0x0ff13026, 4705 .itc_pass = B_TRUE, 4706 .itc_nodeid = 0, 4707 .itc_tadid = 0, 4708 .itc_channelid = 2, 4709 .itc_chanaddr = 0x03fc4c26, 4710 .itc_dimmid = 0, 4711 .itc_rankid = 0, 4712 .itc_rankaddr = 0x03fc4c26 4713 }, { 4714 .itc_desc = "1s mod 3 45t6 (6)", 4715 .itc_imc = &imc_tad_skx_mod3_45t6, 4716 .itc_pa = 0x0ff13077, 4717 .itc_pass = B_TRUE, 4718 .itc_nodeid = 0, 4719 .itc_tadid = 1, 4720 .itc_channelid = 0, 4721 .itc_chanaddr = 0x03fc4c37, 4722 .itc_dimmid = 0, 4723 .itc_rankid = 0, 4724 .itc_rankaddr = 0x03fc4c37 4725 }, { 4726 .itc_desc = "1s mod 3 45t6 (7)", 4727 .itc_imc = &imc_tad_skx_mod3_45t6, 4728 .itc_pa = 0x0ff13099, 4729 .itc_pass = B_TRUE, 4730 .itc_nodeid = 0, 4731 .itc_tadid = 0, 4732 .itc_channelid = 0, 4733 .itc_chanaddr = 0x03fc4c19, 4734 .itc_dimmid = 0, 4735 .itc_rankid = 0, 4736 .itc_rankaddr = 0x03fc4c19 4737 }, { 4738 .itc_desc = "1s mod 3 45t6 (8)", 4739 .itc_imc = &imc_tad_skx_mod3_45t6, 4740 .itc_pa = 0x0ff130ff, 4741 .itc_pass = B_TRUE, 4742 .itc_nodeid = 0, 4743 .itc_tadid = 1, 4744 .itc_channelid = 2, 4745 .itc_chanaddr = 0x03fc4c3f, 4746 .itc_dimmid = 0, 4747 .itc_rankid = 0, 4748 .itc_rankaddr = 0x03fc4c3f 4749 }, { 4750 .itc_desc = "1s mod 3 45t6 (9)", 4751 .itc_imc = &imc_tad_skx_mod3_45t6, 4752 .itc_pa = 0x8ff13006, 4753 .itc_pass = B_TRUE, 4754 .itc_nodeid = 0, 4755 .itc_tadid = 0, 4756 .itc_channelid = 0, 4757 .itc_chanaddr = 0x23fc4c06, 4758 .itc_dimmid = 0, 4759 .itc_rankid = 0, 4760 .itc_rankaddr = 0x23fc4c06 4761 }, { 4762 .itc_desc = "1s mod 3 45t6 (10)", 4763 .itc_imc = &imc_tad_skx_mod3_45t6, 4764 .itc_pa = 0x3ff13046, 4765 .itc_pass = B_TRUE, 4766 .itc_nodeid = 0, 4767 .itc_tadid = 1, 4768 .itc_channelid = 0, 4769 .itc_chanaddr = 0x0ffc4c06, 4770 .itc_dimmid = 0, 4771 .itc_rankid = 0, 4772 .itc_rankaddr = 0x0ffc4c06 4773 }, { 4774 .itc_desc = "1s mod 3 45t6 (11)", 4775 .itc_imc = &imc_tad_skx_mod3_45t6, 4776 .itc_pa = 0x4ff13086, 4777 .itc_pass = B_TRUE, 4778 .itc_nodeid = 0, 4779 .itc_tadid = 0, 4780 .itc_channelid = 2, 4781 .itc_chanaddr = 0x13fc4c06, 4782 .itc_dimmid = 0, 4783 .itc_rankid = 0, 4784 .itc_rankaddr = 0x13fc4c06 4785 }, { 4786 .itc_desc = "1s mod 3 45t6 (12)", 4787 .itc_imc = &imc_tad_skx_mod3_45t6, 4788 .itc_pa = 0x9ff130c6, 4789 .itc_pass = B_TRUE, 4790 .itc_nodeid = 0, 4791 .itc_tadid = 1, 4792 .itc_channelid = 2, 4793 .itc_chanaddr = 0x27fc4c06, 4794 .itc_dimmid = 0, 4795 .itc_rankid = 0, 4796 .itc_rankaddr = 0x27fc4c06 4797 }, { 4798 .itc_desc = "1s mod 3 45t6 (13)", 4799 .itc_imc = &imc_tad_skx_mod3_45t6, 4800 .itc_pa = 0xdff13026, 4801 .itc_pass = B_TRUE, 4802 .itc_nodeid = 0, 4803 .itc_tadid = 1, 4804 .itc_channelid = 1, 4805 .itc_chanaddr = 0x37fc4c26, 4806 .itc_dimmid = 0, 4807 .itc_rankid = 0, 4808 .itc_rankaddr = 0x37fc4c26 4809 }, { 4810 .itc_desc = "1s mod 3 45t6 (14)", 4811 .itc_imc = &imc_tad_skx_mod3_45t6, 4812 .itc_pa = 0xeff13077, 4813 .itc_pass = B_TRUE, 4814 .itc_nodeid = 0, 4815 .itc_tadid = 1, 4816 .itc_channelid = 2, 4817 .itc_chanaddr = 0x3bfc4c37, 4818 .itc_dimmid = 0, 4819 .itc_rankid = 0, 4820 .itc_rankaddr = 0x3bfc4c37 4821 }, { 4822 .itc_desc = "1s mod 3 45t6 (15)", 4823 .itc_imc = &imc_tad_skx_mod3_45t6, 4824 .itc_pa = 0x4ff13099, 4825 .itc_pass = B_TRUE, 4826 .itc_nodeid = 0, 4827 .itc_tadid = 0, 4828 .itc_channelid = 2, 4829 .itc_chanaddr = 0x13fc4c19, 4830 .itc_dimmid = 0, 4831 .itc_rankid = 0, 4832 .itc_rankaddr = 0x13fc4c19 4833 }, { 4834 .itc_desc = "1s mod 3 45t6 (16)", 4835 .itc_imc = &imc_tad_skx_mod3_45t6, 4836 .itc_pa = 0x8ff130ff, 4837 .itc_pass = B_TRUE, 4838 .itc_nodeid = 0, 4839 .itc_tadid = 0, 4840 .itc_channelid = 1, 4841 .itc_chanaddr = 0x23fc4c3f, 4842 .itc_dimmid = 0, 4843 .itc_rankid = 0, 4844 .itc_rankaddr = 0x23fc4c3f 4845 }, 4846 /* 4847 * Now use PA bits 45:8 to determine the basic mod3 rule. We make sure that we 4848 * can construct addresses that hit every routing table entry. 4849 */ 4850 { 4851 .itc_desc = "1s mod 3 45t8 (1)", 4852 .itc_imc = &imc_tad_skx_mod3_45t8, 4853 .itc_pa = 0x00000000, 4854 .itc_pass = B_TRUE, 4855 .itc_nodeid = 0, 4856 .itc_tadid = 0, 4857 .itc_channelid = 0, 4858 .itc_chanaddr = 0x0, 4859 .itc_dimmid = 0, 4860 .itc_rankid = 0, 4861 .itc_rankaddr = 0x0 4862 }, { 4863 .itc_desc = "1s mod 3 45t8 (2)", 4864 .itc_imc = &imc_tad_skx_mod3_45t8, 4865 .itc_pa = 0x00000040, 4866 .itc_pass = B_TRUE, 4867 .itc_nodeid = 0, 4868 .itc_tadid = 0, 4869 .itc_channelid = 1, 4870 .itc_chanaddr = 0x0, 4871 .itc_dimmid = 0, 4872 .itc_rankid = 0, 4873 .itc_rankaddr = 0x0 4874 }, { 4875 .itc_desc = "1s mod 3 45t8 (3)", 4876 .itc_imc = &imc_tad_skx_mod3_45t8, 4877 .itc_pa = 0x00000100, 4878 .itc_pass = B_TRUE, 4879 .itc_nodeid = 0, 4880 .itc_tadid = 0, 4881 .itc_channelid = 2, 4882 .itc_chanaddr = 0x40, 4883 .itc_dimmid = 0, 4884 .itc_rankid = 0, 4885 .itc_rankaddr = 0x40 4886 }, { 4887 .itc_desc = "1s mod 3 45t8 (4)", 4888 .itc_imc = &imc_tad_skx_mod3_45t8, 4889 .itc_pa = 0x00000140, 4890 .itc_pass = B_TRUE, 4891 .itc_nodeid = 0, 4892 .itc_tadid = 1, 4893 .itc_channelid = 2, 4894 .itc_chanaddr = 0x40, 4895 .itc_dimmid = 0, 4896 .itc_rankid = 0, 4897 .itc_rankaddr = 0x40 4898 }, { 4899 .itc_desc = "1s mod 3 45t8 (5)", 4900 .itc_imc = &imc_tad_skx_mod3_45t8, 4901 .itc_pa = 0x00000280, 4902 .itc_pass = B_TRUE, 4903 .itc_nodeid = 0, 4904 .itc_tadid = 1, 4905 .itc_channelid = 1, 4906 .itc_chanaddr = 0x80, 4907 .itc_dimmid = 0, 4908 .itc_rankid = 0, 4909 .itc_rankaddr = 0x80 4910 }, { 4911 .itc_desc = "1s mod 3 45t8 (6)", 4912 .itc_imc = &imc_tad_skx_mod3_45t8, 4913 .itc_pa = 0x00000240, 4914 .itc_pass = B_TRUE, 4915 .itc_nodeid = 0, 4916 .itc_tadid = 1, 4917 .itc_channelid = 0, 4918 .itc_chanaddr = 0x80, 4919 .itc_dimmid = 0, 4920 .itc_rankid = 0, 4921 .itc_rankaddr = 0x80 4922 }, 4923 /* 4924 * Hit every valid routing table entry with a 45:12 rule. 4925 */ 4926 { 4927 .itc_desc = "1s mod 3 45t12 (1)", 4928 .itc_imc = &imc_tad_skx_mod3_45t12, 4929 .itc_pa = 0x00000000, 4930 .itc_pass = B_TRUE, 4931 .itc_nodeid = 0, 4932 .itc_tadid = 0, 4933 .itc_channelid = 0, 4934 .itc_chanaddr = 0x0, 4935 .itc_dimmid = 0, 4936 .itc_rankid = 0, 4937 .itc_rankaddr = 0x0 4938 }, { 4939 .itc_desc = "1s mod 3 45t12 (2)", 4940 .itc_imc = &imc_tad_skx_mod3_45t12, 4941 .itc_pa = 0x00000040, 4942 .itc_pass = B_TRUE, 4943 .itc_nodeid = 0, 4944 .itc_tadid = 0, 4945 .itc_channelid = 1, 4946 .itc_chanaddr = 0x0, 4947 .itc_dimmid = 0, 4948 .itc_rankid = 0, 4949 .itc_rankaddr = 0x0 4950 }, { 4951 .itc_desc = "1s mod 3 45t12 (3)", 4952 .itc_imc = &imc_tad_skx_mod3_45t12, 4953 .itc_pa = 0x00001000, 4954 .itc_pass = B_TRUE, 4955 .itc_nodeid = 0, 4956 .itc_tadid = 0, 4957 .itc_channelid = 2, 4958 .itc_chanaddr = 0x400, 4959 .itc_dimmid = 0, 4960 .itc_rankid = 0, 4961 .itc_rankaddr = 0x400 4962 }, { 4963 .itc_desc = "1s mod 3 45t12 (4)", 4964 .itc_imc = &imc_tad_skx_mod3_45t12, 4965 .itc_pa = 0x00001040, 4966 .itc_pass = B_TRUE, 4967 .itc_nodeid = 0, 4968 .itc_tadid = 1, 4969 .itc_channelid = 2, 4970 .itc_chanaddr = 0x400, 4971 .itc_dimmid = 0, 4972 .itc_rankid = 0, 4973 .itc_rankaddr = 0x400 4974 }, { 4975 .itc_desc = "1s mod 3 45t12 (5)", 4976 .itc_imc = &imc_tad_skx_mod3_45t12, 4977 .itc_pa = 0x00002080, 4978 .itc_pass = B_TRUE, 4979 .itc_nodeid = 0, 4980 .itc_tadid = 1, 4981 .itc_channelid = 1, 4982 .itc_chanaddr = 0x800, 4983 .itc_dimmid = 0, 4984 .itc_rankid = 0, 4985 .itc_rankaddr = 0x800 4986 }, { 4987 .itc_desc = "1s mod 3 45t12 (6)", 4988 .itc_imc = &imc_tad_skx_mod3_45t12, 4989 .itc_pa = 0x00002040, 4990 .itc_pass = B_TRUE, 4991 .itc_nodeid = 0, 4992 .itc_tadid = 1, 4993 .itc_channelid = 0, 4994 .itc_chanaddr = 0x800, 4995 .itc_dimmid = 0, 4996 .itc_rankid = 0, 4997 .itc_rankaddr = 0x800 4998 }, 4999 /* 5000 * Test to make sure we can trigger all variants of mod2 favoring 0/1. 5001 */ 5002 { 5003 .itc_desc = "1s mod2_01 45t12 (1)", 5004 .itc_imc = &imc_tad_skx_mod2_01_45t12, 5005 .itc_pa = 0x00000000, 5006 .itc_pass = B_TRUE, 5007 .itc_nodeid = 0, 5008 .itc_tadid = 0, 5009 .itc_channelid = 0, 5010 .itc_chanaddr = 0x0, 5011 .itc_dimmid = 0, 5012 .itc_rankid = 0, 5013 .itc_rankaddr = 0x0 5014 }, { 5015 .itc_desc = "1s mod2_01 45t12 (2)", 5016 .itc_imc = &imc_tad_skx_mod2_01_45t12, 5017 .itc_pa = 0x00000040, 5018 .itc_pass = B_TRUE, 5019 .itc_nodeid = 0, 5020 .itc_tadid = 0, 5021 .itc_channelid = 1, 5022 .itc_chanaddr = 0x0, 5023 .itc_dimmid = 0, 5024 .itc_rankid = 0, 5025 .itc_rankaddr = 0x0 5026 }, { 5027 .itc_desc = "1s mod2_01 45t12 (3)", 5028 .itc_imc = &imc_tad_skx_mod2_01_45t12, 5029 .itc_pa = 0x00001000, 5030 .itc_pass = B_TRUE, 5031 .itc_nodeid = 0, 5032 .itc_tadid = 0, 5033 .itc_channelid = 2, 5034 .itc_chanaddr = 0x400, 5035 .itc_dimmid = 0, 5036 .itc_rankid = 0, 5037 .itc_rankaddr = 0x400 5038 }, { 5039 .itc_desc = "1s mod2_01 45t12 (4)", 5040 .itc_imc = &imc_tad_skx_mod2_01_45t12, 5041 .itc_pa = 0x00001040, 5042 .itc_pass = B_TRUE, 5043 .itc_nodeid = 0, 5044 .itc_tadid = 1, 5045 .itc_channelid = 2, 5046 .itc_chanaddr = 0x400, 5047 .itc_dimmid = 0, 5048 .itc_rankid = 0, 5049 .itc_rankaddr = 0x400 5050 }, { 5051 .itc_desc = "1s mod2_01 45t12 (5)", 5052 .itc_imc = &imc_tad_skx_mod2_01_45t12, 5053 .itc_pa = 0x00002080, 5054 .itc_pass = B_TRUE, 5055 .itc_nodeid = 0, 5056 .itc_tadid = 0, 5057 .itc_channelid = 0, 5058 .itc_chanaddr = 0x800, 5059 .itc_dimmid = 0, 5060 .itc_rankid = 0, 5061 .itc_rankaddr = 0x800 5062 }, { 5063 .itc_desc = "1s mod2_01 45t12 (6)", 5064 .itc_imc = &imc_tad_skx_mod2_01_45t12, 5065 .itc_pa = 0x00002040, 5066 .itc_pass = B_TRUE, 5067 .itc_nodeid = 0, 5068 .itc_tadid = 0, 5069 .itc_channelid = 1, 5070 .itc_chanaddr = 0x800, 5071 .itc_dimmid = 0, 5072 .itc_rankid = 0, 5073 .itc_rankaddr = 0x800 5074 }, 5075 /* 5076 * Test to make sure we can trigger all variants of mod2 favoring 1/2. 5077 */ 5078 { 5079 .itc_desc = "1s mod2_12 45t12 (1)", 5080 .itc_imc = &imc_tad_skx_mod2_12_45t12, 5081 .itc_pa = 0x00000000, 5082 .itc_pass = B_TRUE, 5083 .itc_nodeid = 0, 5084 .itc_tadid = 0, 5085 .itc_channelid = 2, 5086 .itc_chanaddr = 0x0, 5087 .itc_dimmid = 0, 5088 .itc_rankid = 0, 5089 .itc_rankaddr = 0x0 5090 }, { 5091 .itc_desc = "1s mod2_12 45t12 (2)", 5092 .itc_imc = &imc_tad_skx_mod2_12_45t12, 5093 .itc_pa = 0x00000040, 5094 .itc_pass = B_TRUE, 5095 .itc_nodeid = 0, 5096 .itc_tadid = 1, 5097 .itc_channelid = 2, 5098 .itc_chanaddr = 0x0, 5099 .itc_dimmid = 0, 5100 .itc_rankid = 0, 5101 .itc_rankaddr = 0x0 5102 }, { 5103 .itc_desc = "1s mod2_12 45t12 (3)", 5104 .itc_imc = &imc_tad_skx_mod2_12_45t12, 5105 .itc_pa = 0x00001000, 5106 .itc_pass = B_TRUE, 5107 .itc_nodeid = 0, 5108 .itc_tadid = 1, 5109 .itc_channelid = 1, 5110 .itc_chanaddr = 0x400, 5111 .itc_dimmid = 0, 5112 .itc_rankid = 0, 5113 .itc_rankaddr = 0x400 5114 }, { 5115 .itc_desc = "1s mod2_12 45t12 (4)", 5116 .itc_imc = &imc_tad_skx_mod2_12_45t12, 5117 .itc_pa = 0x00001040, 5118 .itc_pass = B_TRUE, 5119 .itc_nodeid = 0, 5120 .itc_tadid = 1, 5121 .itc_channelid = 0, 5122 .itc_chanaddr = 0x400, 5123 .itc_dimmid = 0, 5124 .itc_rankid = 0, 5125 .itc_rankaddr = 0x400 5126 }, { 5127 .itc_desc = "1s mod2_12 45t12 (5)", 5128 .itc_imc = &imc_tad_skx_mod2_12_45t12, 5129 .itc_pa = 0x00002080, 5130 .itc_pass = B_TRUE, 5131 .itc_nodeid = 0, 5132 .itc_tadid = 0, 5133 .itc_channelid = 2, 5134 .itc_chanaddr = 0x800, 5135 .itc_dimmid = 0, 5136 .itc_rankid = 0, 5137 .itc_rankaddr = 0x800 5138 }, { 5139 .itc_desc = "1s mod2_12 45t12 (6)", 5140 .itc_imc = &imc_tad_skx_mod2_12_45t12, 5141 .itc_pa = 0x00002040, 5142 .itc_pass = B_TRUE, 5143 .itc_nodeid = 0, 5144 .itc_tadid = 1, 5145 .itc_channelid = 2, 5146 .itc_chanaddr = 0x800, 5147 .itc_dimmid = 0, 5148 .itc_rankid = 0, 5149 .itc_rankaddr = 0x800 5150 }, 5151 /* 5152 * Test to make sure we can trigger all variants of mod2 favoring 0/2. 5153 */ 5154 { 5155 .itc_desc = "1s mod2_02 45t12 (1)", 5156 .itc_imc = &imc_tad_skx_mod2_02_45t12, 5157 .itc_pa = 0x00000000, 5158 .itc_pass = B_TRUE, 5159 .itc_nodeid = 0, 5160 .itc_tadid = 0, 5161 .itc_channelid = 0, 5162 .itc_chanaddr = 0x0, 5163 .itc_dimmid = 0, 5164 .itc_rankid = 0, 5165 .itc_rankaddr = 0x0 5166 }, { 5167 .itc_desc = "1s mod2_02 45t12 (2)", 5168 .itc_imc = &imc_tad_skx_mod2_02_45t12, 5169 .itc_pa = 0x00000040, 5170 .itc_pass = B_TRUE, 5171 .itc_nodeid = 0, 5172 .itc_tadid = 0, 5173 .itc_channelid = 1, 5174 .itc_chanaddr = 0x0, 5175 .itc_dimmid = 0, 5176 .itc_rankid = 0, 5177 .itc_rankaddr = 0x0 5178 }, { 5179 .itc_desc = "1s mod2_02 45t12 (3)", 5180 .itc_imc = &imc_tad_skx_mod2_02_45t12, 5181 .itc_pa = 0x00001000, 5182 .itc_pass = B_TRUE, 5183 .itc_nodeid = 0, 5184 .itc_tadid = 1, 5185 .itc_channelid = 1, 5186 .itc_chanaddr = 0x400, 5187 .itc_dimmid = 0, 5188 .itc_rankid = 0, 5189 .itc_rankaddr = 0x400 5190 }, { 5191 .itc_desc = "1s mod2_02 45t12 (4)", 5192 .itc_imc = &imc_tad_skx_mod2_02_45t12, 5193 .itc_pa = 0x00001040, 5194 .itc_pass = B_TRUE, 5195 .itc_nodeid = 0, 5196 .itc_tadid = 1, 5197 .itc_channelid = 0, 5198 .itc_chanaddr = 0x400, 5199 .itc_dimmid = 0, 5200 .itc_rankid = 0, 5201 .itc_rankaddr = 0x400 5202 }, { 5203 .itc_desc = "1s mod2_02 45t12 (5)", 5204 .itc_imc = &imc_tad_skx_mod2_02_45t12, 5205 .itc_pa = 0x00002080, 5206 .itc_pass = B_TRUE, 5207 .itc_nodeid = 0, 5208 .itc_tadid = 0, 5209 .itc_channelid = 0, 5210 .itc_chanaddr = 0x800, 5211 .itc_dimmid = 0, 5212 .itc_rankid = 0, 5213 .itc_rankaddr = 0x800 5214 }, { 5215 .itc_desc = "1s mod2_02 45t12 (6)", 5216 .itc_imc = &imc_tad_skx_mod2_02_45t12, 5217 .itc_pa = 0x00002040, 5218 .itc_pass = B_TRUE, 5219 .itc_nodeid = 0, 5220 .itc_tadid = 0, 5221 .itc_channelid = 1, 5222 .itc_chanaddr = 0x800, 5223 .itc_dimmid = 0, 5224 .itc_rankid = 0, 5225 .itc_rankaddr = 0x800 5226 }, { 5227 .itc_desc = NULL 5228 } }; 5229