1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2019 Joyent, Inc. 14 */ 15 16 #include "imc_test.h" 17 18 /* 19 * This tests various aspects of the source address decoder. We need to test 20 * several of the following: 21 * 22 * o SAD rules with different interleave options 23 * - XOR (SNB->BRD) 24 * - 10t8, 14t12, 32t30 (SKX) 25 * o SAD rules with a7mode (IVB->BRD) 26 * - And XOR 27 * o Different SAD rules for different regions 28 */ 29 30 /* 31 * This tests basics SAD interleaving with a 2 socket system that has a single 32 * channel and DIMM. The other aspects are simplified to try and make life 33 * easier. 34 */ 35 36 static const imc_t imc_sad_2s_basic = { 37 .imc_gen = IMC_GEN_SANDY, 38 .imc_nsockets = 2, 39 .imc_sockets[0] = { 40 .isock_nodeid = 0, 41 .isock_valid = IMC_SOCKET_V_VALID, 42 .isock_sad = { 43 .isad_flags = 0, 44 .isad_valid = IMC_SAD_V_VALID, 45 .isad_tolm = 0x80000000, 46 .isad_tohm = 0, 47 .isad_nrules = 10, 48 .isad_rules[0] = { 49 .isr_enable = B_TRUE, 50 .isr_limit = 0x80000000, 51 .isr_imode = IMC_SAD_IMODE_8t6, 52 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 53 .isr_targets = { 0, 1, 0, 1, 0, 1, 0, 1 } 54 } 55 }, 56 .isock_ntad = 1, 57 .isock_tad[0] = { 58 .itad_flags = 0, 59 .itad_nrules = 12, 60 .itad_rules[0] = { 61 .itr_base = 0x0, 62 .itr_limit = 0x80000000, 63 .itr_sock_way = 2, 64 .itr_chan_way = 1, 65 .itr_sock_gran = IMC_TAD_GRAN_64B, 66 .itr_chan_gran = IMC_TAD_GRAN_64B, 67 .itr_ntargets = 4, 68 .itr_targets = { 0, 0, 0, 0 } 69 } 70 }, 71 .isock_nimc = 1, 72 .isock_imcs[0] = { 73 .icn_nchannels = 1, 74 .icn_dimm_type = IMC_DIMM_DDR3, 75 .icn_ecc = B_TRUE, 76 .icn_lockstep = B_FALSE, 77 .icn_closed = B_FALSE, 78 .icn_channels[0] = { 79 .ich_ndimms = 1, 80 .ich_dimms[0] = { 81 .idimm_present = B_TRUE, 82 .idimm_nbanks = 3, 83 .idimm_width = 8, 84 .idimm_density = 2, 85 .idimm_nranks = 2, 86 .idimm_nrows = 14, 87 .idimm_ncolumns = 10, 88 .idimm_size = 0x40000000 89 }, 90 .ich_ntad_offsets = 12, 91 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 92 0, 0 }, 93 .ich_nrankileaves = 8, 94 .ich_rankileaves[0] = { 95 .irle_enabled = B_TRUE, 96 .irle_nways = 1, 97 .irle_nwaysbits = 1, 98 .irle_limit = 0x40000000, 99 .irle_nentries = 8, 100 .irle_entries[0] = { 0x0, 0x0 }, 101 } 102 } 103 } 104 }, 105 .imc_sockets[1] = { 106 .isock_nodeid = 1, 107 .isock_valid = IMC_SOCKET_V_VALID, 108 .isock_sad = { 109 .isad_flags = 0, 110 .isad_valid = IMC_SAD_V_VALID, 111 .isad_tolm = 0x80000000, 112 .isad_tohm = 0, 113 .isad_nrules = 10, 114 .isad_rules[0] = { 115 .isr_enable = B_TRUE, 116 .isr_limit = 0x80000000, 117 .isr_imode = IMC_SAD_IMODE_8t6, 118 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 119 .isr_targets = { 0, 1, 0, 1, 0, 1, 0, 1 } 120 } 121 }, 122 .isock_ntad = 1, 123 .isock_tad[0] = { 124 .itad_flags = 0, 125 .itad_nrules = 12, 126 .itad_rules[0] = { 127 .itr_base = 0x0, 128 .itr_limit = 0x80000000, 129 .itr_sock_way = 2, 130 .itr_chan_way = 1, 131 .itr_sock_gran = IMC_TAD_GRAN_64B, 132 .itr_chan_gran = IMC_TAD_GRAN_64B, 133 .itr_ntargets = 4, 134 .itr_targets = { 0, 0, 0, 0 } 135 } 136 }, 137 .isock_nimc = 1, 138 .isock_imcs[0] = { 139 .icn_nchannels = 1, 140 .icn_dimm_type = IMC_DIMM_DDR3, 141 .icn_ecc = B_TRUE, 142 .icn_lockstep = B_FALSE, 143 .icn_closed = B_FALSE, 144 .icn_channels[0] = { 145 .ich_ndimms = 1, 146 .ich_dimms[0] = { 147 .idimm_present = B_TRUE, 148 .idimm_nbanks = 3, 149 .idimm_width = 8, 150 .idimm_density = 2, 151 .idimm_nranks = 2, 152 .idimm_nrows = 14, 153 .idimm_ncolumns = 10, 154 .idimm_size = 0x40000000 155 }, 156 .ich_ntad_offsets = 12, 157 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 158 0, 0 }, 159 .ich_nrankileaves = 8, 160 .ich_rankileaves[0] = { 161 .irle_enabled = B_TRUE, 162 .irle_nways = 1, 163 .irle_nwaysbits = 1, 164 .irle_limit = 0x40000000, 165 .irle_nentries = 8, 166 .irle_entries[0] = { 0x0, 0x0 }, 167 } 168 } 169 } 170 } 171 }; 172 173 /* 174 * This is a 4 socket variants of the previous one. Each DIMM now has a much 175 * smaller amount of memory in it. 176 */ 177 static const imc_t imc_sad_4s_basic = { 178 .imc_gen = IMC_GEN_SANDY, 179 .imc_nsockets = 4, 180 .imc_sockets[0] = { 181 .isock_nodeid = 0, 182 .isock_valid = IMC_SOCKET_V_VALID, 183 .isock_sad = { 184 .isad_flags = 0, 185 .isad_valid = IMC_SAD_V_VALID, 186 .isad_tolm = 0x80000000, 187 .isad_tohm = 0, 188 .isad_nrules = 10, 189 .isad_rules[0] = { 190 .isr_enable = B_TRUE, 191 .isr_limit = 0x80000000, 192 .isr_imode = IMC_SAD_IMODE_8t6, 193 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 194 .isr_targets = { 0, 1, 2, 3, 0, 1, 2, 3 } 195 } 196 }, 197 .isock_ntad = 1, 198 .isock_tad[0] = { 199 .itad_flags = 0, 200 .itad_nrules = 12, 201 .itad_rules[0] = { 202 .itr_base = 0x0, 203 .itr_limit = 0x80000000, 204 .itr_sock_way = 4, 205 .itr_chan_way = 1, 206 .itr_sock_gran = IMC_TAD_GRAN_64B, 207 .itr_chan_gran = IMC_TAD_GRAN_64B, 208 .itr_ntargets = 4, 209 .itr_targets = { 0, 0, 0, 0 } 210 } 211 }, 212 .isock_nimc = 1, 213 .isock_imcs[0] = { 214 .icn_nchannels = 1, 215 .icn_dimm_type = IMC_DIMM_DDR3, 216 .icn_ecc = B_TRUE, 217 .icn_lockstep = B_FALSE, 218 .icn_closed = B_FALSE, 219 .icn_channels[0] = { 220 .ich_ndimms = 1, 221 .ich_dimms[0] = { 222 .idimm_present = B_TRUE, 223 .idimm_nbanks = 3, 224 .idimm_width = 8, 225 .idimm_density = 2, 226 .idimm_nranks = 2, 227 .idimm_nrows = 14, 228 .idimm_ncolumns = 10, 229 .idimm_size = 0x20000000 230 }, 231 .ich_ntad_offsets = 12, 232 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 233 0, 0 }, 234 .ich_nrankileaves = 8, 235 .ich_rankileaves[0] = { 236 .irle_enabled = B_TRUE, 237 .irle_nways = 1, 238 .irle_nwaysbits = 1, 239 .irle_limit = 0x20000000, 240 .irle_nentries = 8, 241 .irle_entries[0] = { 0x0, 0x0 }, 242 } 243 } 244 } 245 }, 246 .imc_sockets[1] = { 247 .isock_nodeid = 1, 248 .isock_valid = IMC_SOCKET_V_VALID, 249 .isock_sad = { 250 .isad_flags = 0, 251 .isad_valid = IMC_SAD_V_VALID, 252 .isad_tolm = 0x80000000, 253 .isad_tohm = 0, 254 .isad_nrules = 10, 255 .isad_rules[0] = { 256 .isr_enable = B_TRUE, 257 .isr_limit = 0x80000000, 258 .isr_imode = IMC_SAD_IMODE_8t6, 259 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 260 .isr_targets = { 0, 1, 2, 3, 0, 1, 2, 3 } 261 } 262 }, 263 .isock_ntad = 1, 264 .isock_tad[0] = { 265 .itad_flags = 0, 266 .itad_nrules = 12, 267 .itad_rules[0] = { 268 .itr_base = 0x0, 269 .itr_limit = 0x80000000, 270 .itr_sock_way = 4, 271 .itr_chan_way = 1, 272 .itr_sock_gran = IMC_TAD_GRAN_64B, 273 .itr_chan_gran = IMC_TAD_GRAN_64B, 274 .itr_ntargets = 4, 275 .itr_targets = { 0, 0, 0, 0 } 276 } 277 }, 278 .isock_nimc = 1, 279 .isock_imcs[0] = { 280 .icn_nchannels = 1, 281 .icn_dimm_type = IMC_DIMM_DDR3, 282 .icn_ecc = B_TRUE, 283 .icn_lockstep = B_FALSE, 284 .icn_closed = B_FALSE, 285 .icn_channels[0] = { 286 .ich_ndimms = 1, 287 .ich_dimms[0] = { 288 .idimm_present = B_TRUE, 289 .idimm_nbanks = 3, 290 .idimm_width = 8, 291 .idimm_density = 2, 292 .idimm_nranks = 2, 293 .idimm_nrows = 14, 294 .idimm_ncolumns = 10, 295 .idimm_size = 0x20000000 296 }, 297 .ich_ntad_offsets = 12, 298 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 299 0, 0 }, 300 .ich_nrankileaves = 8, 301 .ich_rankileaves[0] = { 302 .irle_enabled = B_TRUE, 303 .irle_nways = 1, 304 .irle_nwaysbits = 1, 305 .irle_limit = 0x20000000, 306 .irle_nentries = 8, 307 .irle_entries[0] = { 0x0, 0x0 }, 308 } 309 } 310 } 311 }, 312 .imc_sockets[2] = { 313 .isock_nodeid = 2, 314 .isock_valid = IMC_SOCKET_V_VALID, 315 .isock_sad = { 316 .isad_flags = 0, 317 .isad_valid = IMC_SAD_V_VALID, 318 .isad_tolm = 0x80000000, 319 .isad_tohm = 0, 320 .isad_nrules = 10, 321 .isad_rules[0] = { 322 .isr_enable = B_TRUE, 323 .isr_limit = 0x80000000, 324 .isr_imode = IMC_SAD_IMODE_8t6, 325 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 326 .isr_targets = { 0, 1, 2, 3, 0, 1, 2, 3 } 327 } 328 }, 329 .isock_ntad = 1, 330 .isock_tad[0] = { 331 .itad_flags = 0, 332 .itad_nrules = 12, 333 .itad_rules[0] = { 334 .itr_base = 0x0, 335 .itr_limit = 0x80000000, 336 .itr_sock_way = 4, 337 .itr_chan_way = 1, 338 .itr_sock_gran = IMC_TAD_GRAN_64B, 339 .itr_chan_gran = IMC_TAD_GRAN_64B, 340 .itr_ntargets = 4, 341 .itr_targets = { 0, 0, 0, 0 } 342 } 343 }, 344 .isock_nimc = 1, 345 .isock_imcs[0] = { 346 .icn_nchannels = 1, 347 .icn_dimm_type = IMC_DIMM_DDR3, 348 .icn_ecc = B_TRUE, 349 .icn_lockstep = B_FALSE, 350 .icn_closed = B_FALSE, 351 .icn_channels[0] = { 352 .ich_ndimms = 1, 353 .ich_dimms[0] = { 354 .idimm_present = B_TRUE, 355 .idimm_nbanks = 3, 356 .idimm_width = 8, 357 .idimm_density = 2, 358 .idimm_nranks = 2, 359 .idimm_nrows = 14, 360 .idimm_ncolumns = 10, 361 .idimm_size = 0x20000000 362 }, 363 .ich_ntad_offsets = 12, 364 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 365 0, 0 }, 366 .ich_nrankileaves = 8, 367 .ich_rankileaves[0] = { 368 .irle_enabled = B_TRUE, 369 .irle_nways = 1, 370 .irle_nwaysbits = 1, 371 .irle_limit = 0x20000000, 372 .irle_nentries = 8, 373 .irle_entries[0] = { 0x0, 0x0 }, 374 } 375 } 376 } 377 }, 378 .imc_sockets[3] = { 379 .isock_nodeid = 3, 380 .isock_valid = IMC_SOCKET_V_VALID, 381 .isock_sad = { 382 .isad_flags = 0, 383 .isad_valid = IMC_SAD_V_VALID, 384 .isad_tolm = 0x80000000, 385 .isad_tohm = 0, 386 .isad_nrules = 10, 387 .isad_rules[0] = { 388 .isr_enable = B_TRUE, 389 .isr_limit = 0x80000000, 390 .isr_imode = IMC_SAD_IMODE_8t6, 391 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 392 .isr_targets = { 0, 1, 2, 3, 0, 1, 2, 3 } 393 } 394 }, 395 .isock_ntad = 1, 396 .isock_tad[0] = { 397 .itad_flags = 0, 398 .itad_nrules = 12, 399 .itad_rules[0] = { 400 .itr_base = 0x0, 401 .itr_limit = 0x80000000, 402 .itr_sock_way = 4, 403 .itr_chan_way = 1, 404 .itr_sock_gran = IMC_TAD_GRAN_64B, 405 .itr_chan_gran = IMC_TAD_GRAN_64B, 406 .itr_ntargets = 4, 407 .itr_targets = { 0, 0, 0, 0 } 408 } 409 }, 410 .isock_nimc = 1, 411 .isock_imcs[0] = { 412 .icn_nchannels = 1, 413 .icn_dimm_type = IMC_DIMM_DDR3, 414 .icn_ecc = B_TRUE, 415 .icn_lockstep = B_FALSE, 416 .icn_closed = B_FALSE, 417 .icn_channels[0] = { 418 .ich_ndimms = 1, 419 .ich_dimms[0] = { 420 .idimm_present = B_TRUE, 421 .idimm_nbanks = 3, 422 .idimm_width = 8, 423 .idimm_density = 2, 424 .idimm_nranks = 2, 425 .idimm_nrows = 14, 426 .idimm_ncolumns = 10, 427 .idimm_size = 0x20000000 428 }, 429 .ich_ntad_offsets = 12, 430 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 431 0, 0 }, 432 .ich_nrankileaves = 8, 433 .ich_rankileaves[0] = { 434 .irle_enabled = B_TRUE, 435 .irle_nways = 1, 436 .irle_nwaysbits = 1, 437 .irle_limit = 0x20000000, 438 .irle_nentries = 8, 439 .irle_entries[0] = { 0x0, 0x0 }, 440 } 441 } 442 } 443 } 444 }; 445 446 /* 447 * This is similar to imc_sad_2s_basic; however, it enables the XOR mode. 448 */ 449 static const imc_t imc_sad_2s_xor = { 450 .imc_gen = IMC_GEN_IVY, 451 .imc_nsockets = 2, 452 .imc_sockets[0] = { 453 .isock_nodeid = 0, 454 .isock_valid = IMC_SOCKET_V_VALID, 455 .isock_sad = { 456 .isad_flags = 0, 457 .isad_valid = IMC_SAD_V_VALID, 458 .isad_tolm = 0x80000000, 459 .isad_tohm = 0, 460 .isad_nrules = 10, 461 .isad_rules[0] = { 462 .isr_enable = B_TRUE, 463 .isr_limit = 0x80000000, 464 .isr_imode = IMC_SAD_IMODE_8t6XOR, 465 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 466 .isr_targets = { 0, 1, 0, 1, 0, 1, 0, 1 } 467 } 468 }, 469 .isock_ntad = 1, 470 .isock_tad[0] = { 471 .itad_flags = 0, 472 .itad_nrules = 12, 473 .itad_rules[0] = { 474 .itr_base = 0x0, 475 .itr_limit = 0x80000000, 476 .itr_sock_way = 2, 477 .itr_chan_way = 1, 478 .itr_sock_gran = IMC_TAD_GRAN_64B, 479 .itr_chan_gran = IMC_TAD_GRAN_64B, 480 .itr_ntargets = 4, 481 .itr_targets = { 0, 0, 0, 0 } 482 } 483 }, 484 .isock_nimc = 1, 485 .isock_imcs[0] = { 486 .icn_nchannels = 1, 487 .icn_dimm_type = IMC_DIMM_DDR3, 488 .icn_ecc = B_TRUE, 489 .icn_lockstep = B_FALSE, 490 .icn_closed = B_FALSE, 491 .icn_channels[0] = { 492 .ich_ndimms = 1, 493 .ich_dimms[0] = { 494 .idimm_present = B_TRUE, 495 .idimm_nbanks = 3, 496 .idimm_width = 8, 497 .idimm_density = 2, 498 .idimm_nranks = 2, 499 .idimm_nrows = 14, 500 .idimm_ncolumns = 10, 501 .idimm_size = 0x40000000 502 }, 503 .ich_ntad_offsets = 12, 504 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 505 0, 0 }, 506 .ich_nrankileaves = 8, 507 .ich_rankileaves[0] = { 508 .irle_enabled = B_TRUE, 509 .irle_nways = 1, 510 .irle_nwaysbits = 1, 511 .irle_limit = 0x40000000, 512 .irle_nentries = 8, 513 .irle_entries[0] = { 0x0, 0x0 }, 514 } 515 } 516 } 517 }, 518 .imc_sockets[1] = { 519 .isock_nodeid = 1, 520 .isock_valid = IMC_SOCKET_V_VALID, 521 .isock_sad = { 522 .isad_flags = 0, 523 .isad_valid = IMC_SAD_V_VALID, 524 .isad_tolm = 0x80000000, 525 .isad_tohm = 0, 526 .isad_nrules = 10, 527 .isad_rules[0] = { 528 .isr_enable = B_TRUE, 529 .isr_limit = 0x80000000, 530 .isr_imode = IMC_SAD_IMODE_8t6XOR, 531 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 532 .isr_targets = { 0, 1, 0, 1, 0, 1, 0, 1 } 533 } 534 }, 535 .isock_ntad = 1, 536 .isock_tad[0] = { 537 .itad_flags = 0, 538 .itad_nrules = 12, 539 .itad_rules[0] = { 540 .itr_base = 0x0, 541 .itr_limit = 0x80000000, 542 .itr_sock_way = 2, 543 .itr_chan_way = 1, 544 .itr_sock_gran = IMC_TAD_GRAN_64B, 545 .itr_chan_gran = IMC_TAD_GRAN_64B, 546 .itr_ntargets = 4, 547 .itr_targets = { 0, 0, 0, 0 } 548 } 549 }, 550 .isock_nimc = 1, 551 .isock_imcs[0] = { 552 .icn_nchannels = 1, 553 .icn_dimm_type = IMC_DIMM_DDR3, 554 .icn_ecc = B_TRUE, 555 .icn_lockstep = B_FALSE, 556 .icn_closed = B_FALSE, 557 .icn_channels[0] = { 558 .ich_ndimms = 1, 559 .ich_dimms[0] = { 560 .idimm_present = B_TRUE, 561 .idimm_nbanks = 3, 562 .idimm_width = 8, 563 .idimm_density = 2, 564 .idimm_nranks = 2, 565 .idimm_nrows = 14, 566 .idimm_ncolumns = 10, 567 .idimm_size = 0x40000000 568 }, 569 .ich_ntad_offsets = 12, 570 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 571 0, 0 }, 572 .ich_nrankileaves = 8, 573 .ich_rankileaves[0] = { 574 .irle_enabled = B_TRUE, 575 .irle_nways = 1, 576 .irle_nwaysbits = 1, 577 .irle_limit = 0x40000000, 578 .irle_nentries = 8, 579 .irle_entries[0] = { 0x0, 0x0 }, 580 } 581 } 582 } 583 } 584 }; 585 586 static const imc_t imc_sad_2s_a7 = { 587 .imc_gen = IMC_GEN_IVY, 588 .imc_nsockets = 2, 589 .imc_sockets[0] = { 590 .isock_nodeid = 0, 591 .isock_valid = IMC_SOCKET_V_VALID, 592 .isock_sad = { 593 .isad_flags = 0, 594 .isad_valid = IMC_SAD_V_VALID, 595 .isad_tolm = 0x80000000, 596 .isad_tohm = 0, 597 .isad_nrules = 10, 598 .isad_rules[0] = { 599 .isr_enable = B_TRUE, 600 .isr_limit = 0x80000000, 601 .isr_imode = IMC_SAD_IMODE_8t6, 602 .isr_a7mode = B_TRUE, 603 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 604 .isr_targets = { 0, 1, 0, 1, 0, 1, 0, 1 } 605 } 606 }, 607 .isock_ntad = 1, 608 .isock_tad[0] = { 609 .itad_flags = IMC_TAD_FLAG_CHANSHIFT, 610 .itad_nrules = 12, 611 .itad_rules[0] = { 612 .itr_base = 0x0, 613 .itr_limit = 0x80000000, 614 .itr_sock_way = 2, 615 .itr_chan_way = 1, 616 .itr_sock_gran = IMC_TAD_GRAN_64B, 617 .itr_chan_gran = IMC_TAD_GRAN_64B, 618 .itr_ntargets = 4, 619 .itr_targets = { 0, 0, 0, 0 } 620 } 621 }, 622 .isock_nimc = 1, 623 .isock_imcs[0] = { 624 .icn_nchannels = 1, 625 .icn_dimm_type = IMC_DIMM_DDR3, 626 .icn_ecc = B_TRUE, 627 .icn_lockstep = B_FALSE, 628 .icn_closed = B_FALSE, 629 .icn_channels[0] = { 630 .ich_ndimms = 1, 631 .ich_dimms[0] = { 632 .idimm_present = B_TRUE, 633 .idimm_nbanks = 3, 634 .idimm_width = 8, 635 .idimm_density = 2, 636 .idimm_nranks = 2, 637 .idimm_nrows = 14, 638 .idimm_ncolumns = 10, 639 .idimm_size = 0x40000000 640 }, 641 .ich_ntad_offsets = 12, 642 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 643 0, 0 }, 644 .ich_nrankileaves = 8, 645 .ich_rankileaves[0] = { 646 .irle_enabled = B_TRUE, 647 .irle_nways = 1, 648 .irle_nwaysbits = 1, 649 .irle_limit = 0x40000000, 650 .irle_nentries = 8, 651 .irle_entries[0] = { 0x0, 0x0 }, 652 } 653 } 654 } 655 }, 656 .imc_sockets[1] = { 657 .isock_nodeid = 1, 658 .isock_valid = IMC_SOCKET_V_VALID, 659 .isock_sad = { 660 .isad_flags = 0, 661 .isad_valid = IMC_SAD_V_VALID, 662 .isad_tolm = 0x80000000, 663 .isad_tohm = 0, 664 .isad_nrules = 10, 665 .isad_rules[0] = { 666 .isr_enable = B_TRUE, 667 .isr_limit = 0x80000000, 668 .isr_imode = IMC_SAD_IMODE_8t6, 669 .isr_a7mode = B_TRUE, 670 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 671 .isr_targets = { 0, 1, 0, 1, 0, 1, 0, 1 } 672 } 673 }, 674 .isock_ntad = 1, 675 .isock_tad[0] = { 676 .itad_flags = IMC_TAD_FLAG_CHANSHIFT, 677 .itad_nrules = 12, 678 .itad_rules[0] = { 679 .itr_base = 0x0, 680 .itr_limit = 0x80000000, 681 .itr_sock_way = 2, 682 .itr_chan_way = 1, 683 .itr_sock_gran = IMC_TAD_GRAN_64B, 684 .itr_chan_gran = IMC_TAD_GRAN_64B, 685 .itr_ntargets = 4, 686 .itr_targets = { 0, 0, 0, 0 } 687 } 688 }, 689 .isock_nimc = 1, 690 .isock_imcs[0] = { 691 .icn_nchannels = 1, 692 .icn_dimm_type = IMC_DIMM_DDR3, 693 .icn_ecc = B_TRUE, 694 .icn_lockstep = B_FALSE, 695 .icn_closed = B_FALSE, 696 .icn_channels[0] = { 697 .ich_ndimms = 1, 698 .ich_dimms[0] = { 699 .idimm_present = B_TRUE, 700 .idimm_nbanks = 3, 701 .idimm_width = 8, 702 .idimm_density = 2, 703 .idimm_nranks = 2, 704 .idimm_nrows = 14, 705 .idimm_ncolumns = 10, 706 .idimm_size = 0x40000000 707 }, 708 .ich_ntad_offsets = 12, 709 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 710 0, 0 }, 711 .ich_nrankileaves = 8, 712 .ich_rankileaves[0] = { 713 .irle_enabled = B_TRUE, 714 .irle_nways = 1, 715 .irle_nwaysbits = 1, 716 .irle_limit = 0x40000000, 717 .irle_nentries = 8, 718 .irle_entries[0] = { 0x0, 0x0 }, 719 } 720 } 721 } 722 } 723 }; 724 725 /* 726 * This is a 4 socket variants of the previous one. Each DIMM now has a much 727 * smaller amount of memory in it. 728 */ 729 static const imc_t imc_sad_4s_a7 = { 730 .imc_gen = IMC_GEN_HASWELL, 731 .imc_nsockets = 4, 732 .imc_sockets[0] = { 733 .isock_nodeid = 0, 734 .isock_valid = IMC_SOCKET_V_VALID, 735 .isock_sad = { 736 .isad_flags = 0, 737 .isad_valid = IMC_SAD_V_VALID, 738 .isad_tolm = 0x80000000, 739 .isad_tohm = 0, 740 .isad_nrules = 10, 741 .isad_rules[0] = { 742 .isr_enable = B_TRUE, 743 .isr_limit = 0x80000000, 744 .isr_imode = IMC_SAD_IMODE_8t6, 745 .isr_a7mode = B_TRUE, 746 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 747 .isr_targets = { 0, 1, 2, 3, 0, 1, 2, 3 } 748 } 749 }, 750 .isock_ntad = 1, 751 .isock_tad[0] = { 752 .itad_flags = IMC_TAD_FLAG_CHANSHIFT, 753 .itad_nrules = 12, 754 .itad_rules[0] = { 755 .itr_base = 0x0, 756 .itr_limit = 0x80000000, 757 .itr_sock_way = 4, 758 .itr_chan_way = 1, 759 .itr_sock_gran = IMC_TAD_GRAN_64B, 760 .itr_chan_gran = IMC_TAD_GRAN_64B, 761 .itr_ntargets = 4, 762 .itr_targets = { 0, 0, 0, 0 } 763 } 764 }, 765 .isock_nimc = 1, 766 .isock_imcs[0] = { 767 .icn_nchannels = 1, 768 .icn_dimm_type = IMC_DIMM_DDR3, 769 .icn_ecc = B_TRUE, 770 .icn_lockstep = B_FALSE, 771 .icn_closed = B_FALSE, 772 .icn_channels[0] = { 773 .ich_ndimms = 1, 774 .ich_dimms[0] = { 775 .idimm_present = B_TRUE, 776 .idimm_nbanks = 3, 777 .idimm_width = 8, 778 .idimm_density = 2, 779 .idimm_nranks = 2, 780 .idimm_nrows = 14, 781 .idimm_ncolumns = 10, 782 .idimm_size = 0x20000000 783 }, 784 .ich_ntad_offsets = 12, 785 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 786 0, 0 }, 787 .ich_nrankileaves = 8, 788 .ich_rankileaves[0] = { 789 .irle_enabled = B_TRUE, 790 .irle_nways = 1, 791 .irle_nwaysbits = 1, 792 .irle_limit = 0x20000000, 793 .irle_nentries = 8, 794 .irle_entries[0] = { 0x0, 0x0 }, 795 } 796 } 797 } 798 }, 799 .imc_sockets[1] = { 800 .isock_nodeid = 1, 801 .isock_valid = IMC_SOCKET_V_VALID, 802 .isock_sad = { 803 .isad_flags = 0, 804 .isad_valid = IMC_SAD_V_VALID, 805 .isad_tolm = 0x80000000, 806 .isad_tohm = 0, 807 .isad_nrules = 10, 808 .isad_rules[0] = { 809 .isr_enable = B_TRUE, 810 .isr_limit = 0x80000000, 811 .isr_imode = IMC_SAD_IMODE_8t6, 812 .isr_a7mode = B_TRUE, 813 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 814 .isr_targets = { 0, 1, 2, 3, 0, 1, 2, 3 } 815 } 816 }, 817 .isock_ntad = 1, 818 .isock_tad[0] = { 819 .itad_flags = IMC_TAD_FLAG_CHANSHIFT, 820 .itad_nrules = 12, 821 .itad_rules[0] = { 822 .itr_base = 0x0, 823 .itr_limit = 0x80000000, 824 .itr_sock_way = 4, 825 .itr_chan_way = 1, 826 .itr_sock_gran = IMC_TAD_GRAN_64B, 827 .itr_chan_gran = IMC_TAD_GRAN_64B, 828 .itr_ntargets = 4, 829 .itr_targets = { 0, 0, 0, 0 } 830 } 831 }, 832 .isock_nimc = 1, 833 .isock_imcs[0] = { 834 .icn_nchannels = 1, 835 .icn_dimm_type = IMC_DIMM_DDR3, 836 .icn_ecc = B_TRUE, 837 .icn_lockstep = B_FALSE, 838 .icn_closed = B_FALSE, 839 .icn_channels[0] = { 840 .ich_ndimms = 1, 841 .ich_dimms[0] = { 842 .idimm_present = B_TRUE, 843 .idimm_nbanks = 3, 844 .idimm_width = 8, 845 .idimm_density = 2, 846 .idimm_nranks = 2, 847 .idimm_nrows = 14, 848 .idimm_ncolumns = 10, 849 .idimm_size = 0x20000000 850 }, 851 .ich_ntad_offsets = 12, 852 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 853 0, 0 }, 854 .ich_nrankileaves = 8, 855 .ich_rankileaves[0] = { 856 .irle_enabled = B_TRUE, 857 .irle_nways = 1, 858 .irle_nwaysbits = 1, 859 .irle_limit = 0x20000000, 860 .irle_nentries = 8, 861 .irle_entries[0] = { 0x0, 0x0 }, 862 } 863 } 864 } 865 }, 866 .imc_sockets[2] = { 867 .isock_nodeid = 2, 868 .isock_valid = IMC_SOCKET_V_VALID, 869 .isock_sad = { 870 .isad_flags = 0, 871 .isad_valid = IMC_SAD_V_VALID, 872 .isad_tolm = 0x80000000, 873 .isad_tohm = 0, 874 .isad_nrules = 10, 875 .isad_rules[0] = { 876 .isr_enable = B_TRUE, 877 .isr_limit = 0x80000000, 878 .isr_imode = IMC_SAD_IMODE_8t6, 879 .isr_a7mode = B_TRUE, 880 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 881 .isr_targets = { 0, 1, 2, 3, 0, 1, 2, 3 } 882 } 883 }, 884 .isock_ntad = 1, 885 .isock_tad[0] = { 886 .itad_flags = IMC_TAD_FLAG_CHANSHIFT, 887 .itad_nrules = 12, 888 .itad_rules[0] = { 889 .itr_base = 0x0, 890 .itr_limit = 0x80000000, 891 .itr_sock_way = 4, 892 .itr_chan_way = 1, 893 .itr_sock_gran = IMC_TAD_GRAN_64B, 894 .itr_chan_gran = IMC_TAD_GRAN_64B, 895 .itr_ntargets = 4, 896 .itr_targets = { 0, 0, 0, 0 } 897 } 898 }, 899 .isock_nimc = 1, 900 .isock_imcs[0] = { 901 .icn_nchannels = 1, 902 .icn_dimm_type = IMC_DIMM_DDR3, 903 .icn_ecc = B_TRUE, 904 .icn_lockstep = B_FALSE, 905 .icn_closed = B_FALSE, 906 .icn_channels[0] = { 907 .ich_ndimms = 1, 908 .ich_dimms[0] = { 909 .idimm_present = B_TRUE, 910 .idimm_nbanks = 3, 911 .idimm_width = 8, 912 .idimm_density = 2, 913 .idimm_nranks = 2, 914 .idimm_nrows = 14, 915 .idimm_ncolumns = 10, 916 .idimm_size = 0x20000000 917 }, 918 .ich_ntad_offsets = 12, 919 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 920 0, 0 }, 921 .ich_nrankileaves = 8, 922 .ich_rankileaves[0] = { 923 .irle_enabled = B_TRUE, 924 .irle_nways = 1, 925 .irle_nwaysbits = 1, 926 .irle_limit = 0x20000000, 927 .irle_nentries = 8, 928 .irle_entries[0] = { 0x0, 0x0 }, 929 } 930 } 931 } 932 }, 933 .imc_sockets[3] = { 934 .isock_nodeid = 3, 935 .isock_valid = IMC_SOCKET_V_VALID, 936 .isock_sad = { 937 .isad_flags = 0, 938 .isad_valid = IMC_SAD_V_VALID, 939 .isad_tolm = 0x80000000, 940 .isad_tohm = 0, 941 .isad_nrules = 10, 942 .isad_rules[0] = { 943 .isr_enable = B_TRUE, 944 .isr_limit = 0x80000000, 945 .isr_imode = IMC_SAD_IMODE_8t6, 946 .isr_a7mode = B_TRUE, 947 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 948 .isr_targets = { 0, 1, 2, 3, 0, 1, 2, 3 } 949 } 950 }, 951 .isock_ntad = 1, 952 .isock_tad[0] = { 953 .itad_flags = IMC_TAD_FLAG_CHANSHIFT, 954 .itad_nrules = 12, 955 .itad_rules[0] = { 956 .itr_base = 0x0, 957 .itr_limit = 0x80000000, 958 .itr_sock_way = 4, 959 .itr_chan_way = 1, 960 .itr_sock_gran = IMC_TAD_GRAN_64B, 961 .itr_chan_gran = IMC_TAD_GRAN_64B, 962 .itr_ntargets = 4, 963 .itr_targets = { 0, 0, 0, 0 } 964 } 965 }, 966 .isock_nimc = 1, 967 .isock_imcs[0] = { 968 .icn_nchannels = 1, 969 .icn_dimm_type = IMC_DIMM_DDR3, 970 .icn_ecc = B_TRUE, 971 .icn_lockstep = B_FALSE, 972 .icn_closed = B_FALSE, 973 .icn_channels[0] = { 974 .ich_ndimms = 1, 975 .ich_dimms[0] = { 976 .idimm_present = B_TRUE, 977 .idimm_nbanks = 3, 978 .idimm_width = 8, 979 .idimm_density = 2, 980 .idimm_nranks = 2, 981 .idimm_nrows = 14, 982 .idimm_ncolumns = 10, 983 .idimm_size = 0x20000000 984 }, 985 .ich_ntad_offsets = 12, 986 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 987 0, 0 }, 988 .ich_nrankileaves = 8, 989 .ich_rankileaves[0] = { 990 .irle_enabled = B_TRUE, 991 .irle_nways = 1, 992 .irle_nwaysbits = 1, 993 .irle_limit = 0x20000000, 994 .irle_nentries = 8, 995 .irle_entries[0] = { 0x0, 0x0 }, 996 } 997 } 998 } 999 } 1000 }; 1001 1002 /* 1003 * This is similar to imc_sad_2s_basic; however, it enables the XOR mode. 1004 */ 1005 static const imc_t imc_sad_2s_a7_xor = { 1006 .imc_gen = IMC_GEN_BROADWELL, 1007 .imc_nsockets = 2, 1008 .imc_sockets[0] = { 1009 .isock_nodeid = 0, 1010 .isock_valid = IMC_SOCKET_V_VALID, 1011 .isock_sad = { 1012 .isad_flags = 0, 1013 .isad_valid = IMC_SAD_V_VALID, 1014 .isad_tolm = 0x80000000, 1015 .isad_tohm = 0, 1016 .isad_nrules = 10, 1017 .isad_rules[0] = { 1018 .isr_enable = B_TRUE, 1019 .isr_limit = 0x80000000, 1020 .isr_imode = IMC_SAD_IMODE_8t6XOR, 1021 .isr_a7mode = B_TRUE, 1022 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 1023 .isr_targets = { 0, 1, 0, 1, 0, 1, 0, 1 } 1024 } 1025 }, 1026 .isock_ntad = 1, 1027 .isock_tad[0] = { 1028 .itad_flags = IMC_TAD_FLAG_CHANSHIFT, 1029 .itad_nrules = 12, 1030 .itad_rules[0] = { 1031 .itr_base = 0x0, 1032 .itr_limit = 0x80000000, 1033 .itr_sock_way = 2, 1034 .itr_chan_way = 1, 1035 .itr_sock_gran = IMC_TAD_GRAN_64B, 1036 .itr_chan_gran = IMC_TAD_GRAN_64B, 1037 .itr_ntargets = 4, 1038 .itr_targets = { 0, 0, 0, 0 } 1039 } 1040 }, 1041 .isock_nimc = 1, 1042 .isock_imcs[0] = { 1043 .icn_nchannels = 1, 1044 .icn_dimm_type = IMC_DIMM_DDR3, 1045 .icn_ecc = B_TRUE, 1046 .icn_lockstep = B_FALSE, 1047 .icn_closed = B_FALSE, 1048 .icn_channels[0] = { 1049 .ich_ndimms = 1, 1050 .ich_dimms[0] = { 1051 .idimm_present = B_TRUE, 1052 .idimm_nbanks = 3, 1053 .idimm_width = 8, 1054 .idimm_density = 2, 1055 .idimm_nranks = 2, 1056 .idimm_nrows = 14, 1057 .idimm_ncolumns = 10, 1058 .idimm_size = 0x40000000 1059 }, 1060 .ich_ntad_offsets = 12, 1061 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1062 0, 0 }, 1063 .ich_nrankileaves = 8, 1064 .ich_rankileaves[0] = { 1065 .irle_enabled = B_TRUE, 1066 .irle_nways = 1, 1067 .irle_nwaysbits = 1, 1068 .irle_limit = 0x40000000, 1069 .irle_nentries = 8, 1070 .irle_entries[0] = { 0x0, 0x0 }, 1071 } 1072 } 1073 } 1074 }, 1075 .imc_sockets[1] = { 1076 .isock_nodeid = 1, 1077 .isock_valid = IMC_SOCKET_V_VALID, 1078 .isock_sad = { 1079 .isad_flags = 0, 1080 .isad_valid = IMC_SAD_V_VALID, 1081 .isad_tolm = 0x80000000, 1082 .isad_tohm = 0, 1083 .isad_nrules = 10, 1084 .isad_rules[0] = { 1085 .isr_enable = B_TRUE, 1086 .isr_limit = 0x80000000, 1087 .isr_imode = IMC_SAD_IMODE_8t6XOR, 1088 .isr_a7mode = B_TRUE, 1089 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 1090 .isr_targets = { 0, 1, 0, 1, 0, 1, 0, 1 } 1091 } 1092 }, 1093 .isock_ntad = 1, 1094 .isock_tad[0] = { 1095 .itad_flags = IMC_TAD_FLAG_CHANSHIFT, 1096 .itad_nrules = 12, 1097 .itad_rules[0] = { 1098 .itr_base = 0x0, 1099 .itr_limit = 0x80000000, 1100 .itr_sock_way = 2, 1101 .itr_chan_way = 1, 1102 .itr_sock_gran = IMC_TAD_GRAN_64B, 1103 .itr_chan_gran = IMC_TAD_GRAN_64B, 1104 .itr_ntargets = 4, 1105 .itr_targets = { 0, 0, 0, 0 } 1106 } 1107 }, 1108 .isock_nimc = 1, 1109 .isock_imcs[0] = { 1110 .icn_nchannels = 1, 1111 .icn_dimm_type = IMC_DIMM_DDR3, 1112 .icn_ecc = B_TRUE, 1113 .icn_lockstep = B_FALSE, 1114 .icn_closed = B_FALSE, 1115 .icn_channels[0] = { 1116 .ich_ndimms = 1, 1117 .ich_dimms[0] = { 1118 .idimm_present = B_TRUE, 1119 .idimm_nbanks = 3, 1120 .idimm_width = 8, 1121 .idimm_density = 2, 1122 .idimm_nranks = 2, 1123 .idimm_nrows = 14, 1124 .idimm_ncolumns = 10, 1125 .idimm_size = 0x40000000 1126 }, 1127 .ich_ntad_offsets = 12, 1128 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1129 0, 0 }, 1130 .ich_nrankileaves = 8, 1131 .ich_rankileaves[0] = { 1132 .irle_enabled = B_TRUE, 1133 .irle_nways = 1, 1134 .irle_nwaysbits = 1, 1135 .irle_limit = 0x40000000, 1136 .irle_nentries = 8, 1137 .irle_entries[0] = { 0x0, 0x0 }, 1138 } 1139 } 1140 } 1141 } 1142 }; 1143 1144 /* 1145 * This constructs an IMC that has multiple SAD rules that change how we 1146 * interleave across different regions of memory. 1147 */ 1148 static const imc_t imc_sad_2s_multirule = { 1149 .imc_gen = IMC_GEN_SANDY, 1150 .imc_nsockets = 2, 1151 .imc_sockets[0] = { 1152 .isock_nodeid = 0, 1153 .isock_valid = IMC_SOCKET_V_VALID, 1154 .isock_sad = { 1155 .isad_flags = 0, 1156 .isad_valid = IMC_SAD_V_VALID, 1157 .isad_tolm = 0x80000000, 1158 .isad_tohm = 0, 1159 .isad_nrules = 10, 1160 .isad_rules[0] = { 1161 .isr_enable = B_TRUE, 1162 .isr_limit = 0x20000000, 1163 .isr_imode = IMC_SAD_IMODE_8t6, 1164 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 1165 .isr_targets = { 0, 1, 0, 1, 0, 1, 0, 1 } 1166 }, 1167 .isad_rules[1] = { 1168 .isr_enable = B_TRUE, 1169 .isr_limit = 0x40000000, 1170 .isr_imode = IMC_SAD_IMODE_8t6, 1171 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 1172 .isr_targets = { 1, 1, 1, 1, 1, 1, 1, 1 } 1173 }, 1174 .isad_rules[2] = { 1175 .isr_enable = B_TRUE, 1176 .isr_limit = 0x60000000, 1177 .isr_imode = IMC_SAD_IMODE_8t6, 1178 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 1179 .isr_targets = { 0, 0, 0, 0, 0, 0, 0, 0 } 1180 }, 1181 .isad_rules[3] = { 1182 .isr_enable = B_TRUE, 1183 .isr_limit = 0x80000000, 1184 .isr_imode = IMC_SAD_IMODE_8t6, 1185 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 1186 .isr_targets = { 1, 0, 1, 0, 1, 0, 1, 0 } 1187 } 1188 }, 1189 .isock_ntad = 1, 1190 .isock_tad[0] = { 1191 .itad_flags = 0, 1192 .itad_nrules = 12, 1193 .itad_rules[0] = { 1194 .itr_base = 0x0, 1195 .itr_limit = 0x20000000, 1196 .itr_sock_way = 2, 1197 .itr_chan_way = 1, 1198 .itr_sock_gran = IMC_TAD_GRAN_64B, 1199 .itr_chan_gran = IMC_TAD_GRAN_64B, 1200 .itr_ntargets = 4, 1201 .itr_targets = { 0, 0, 0, 0 } 1202 }, 1203 .itad_rules[1] = { 1204 .itr_base = 0x20000000, 1205 .itr_limit = 0x60000000, 1206 .itr_sock_way = 1, 1207 .itr_chan_way = 1, 1208 .itr_sock_gran = IMC_TAD_GRAN_64B, 1209 .itr_chan_gran = IMC_TAD_GRAN_64B, 1210 .itr_ntargets = 4, 1211 .itr_targets = { 0, 0, 0, 0 } 1212 }, 1213 .itad_rules[2] = { 1214 .itr_base = 0x60000000, 1215 .itr_limit = 0x80000000, 1216 .itr_sock_way = 2, 1217 .itr_chan_way = 1, 1218 .itr_sock_gran = IMC_TAD_GRAN_64B, 1219 .itr_chan_gran = IMC_TAD_GRAN_64B, 1220 .itr_ntargets = 4, 1221 .itr_targets = { 0, 0, 0, 0 } 1222 } 1223 }, 1224 .isock_nimc = 1, 1225 .isock_imcs[0] = { 1226 .icn_nchannels = 1, 1227 .icn_dimm_type = IMC_DIMM_DDR3, 1228 .icn_ecc = B_TRUE, 1229 .icn_lockstep = B_FALSE, 1230 .icn_closed = B_FALSE, 1231 .icn_channels[0] = { 1232 .ich_ndimms = 1, 1233 .ich_dimms[0] = { 1234 .idimm_present = B_TRUE, 1235 .idimm_nbanks = 3, 1236 .idimm_width = 8, 1237 .idimm_density = 2, 1238 .idimm_nranks = 2, 1239 .idimm_nrows = 14, 1240 .idimm_ncolumns = 10, 1241 .idimm_size = 0x40000000 1242 }, 1243 .ich_ntad_offsets = 12, 1244 .ich_tad_offsets = { 0, 0x30000000, 0, 0, 0, 0, 1245 0, 0, 0, 0, 0 }, 1246 .ich_nrankileaves = 8, 1247 .ich_rankileaves[0] = { 1248 .irle_enabled = B_TRUE, 1249 .irle_nways = 1, 1250 .irle_nwaysbits = 1, 1251 .irle_limit = 0x40000000, 1252 .irle_nentries = 8, 1253 .irle_entries[0] = { 0x0, 0x0 }, 1254 } 1255 } 1256 } 1257 }, 1258 .imc_sockets[1] = { 1259 .isock_nodeid = 1, 1260 .isock_valid = IMC_SOCKET_V_VALID, 1261 .isock_sad = { 1262 .isad_flags = 0, 1263 .isad_valid = IMC_SAD_V_VALID, 1264 .isad_tolm = 0x80000000, 1265 .isad_tohm = 0, 1266 .isad_nrules = 10, 1267 .isad_rules[0] = { 1268 .isr_enable = B_TRUE, 1269 .isr_limit = 0x20000000, 1270 .isr_imode = IMC_SAD_IMODE_8t6, 1271 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 1272 .isr_targets = { 0, 1, 0, 1, 0, 1, 0, 1 } 1273 }, 1274 .isad_rules[1] = { 1275 .isr_enable = B_TRUE, 1276 .isr_limit = 0x40000000, 1277 .isr_imode = IMC_SAD_IMODE_8t6, 1278 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 1279 .isr_targets = { 1, 1, 1, 1, 1, 1, 1, 1 } 1280 }, 1281 .isad_rules[2] = { 1282 .isr_enable = B_TRUE, 1283 .isr_limit = 0x60000000, 1284 .isr_imode = IMC_SAD_IMODE_8t6, 1285 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 1286 .isr_targets = { 0, 0, 0, 0, 0, 0, 0, 0 } 1287 }, 1288 .isad_rules[3] = { 1289 .isr_enable = B_TRUE, 1290 .isr_limit = 0x80000000, 1291 .isr_imode = IMC_SAD_IMODE_8t6, 1292 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 1293 .isr_targets = { 1, 0, 1, 0, 1, 0, 1, 0 } 1294 } 1295 }, 1296 .isock_ntad = 1, 1297 .isock_tad[0] = { 1298 .itad_flags = 0, 1299 .itad_nrules = 12, 1300 .itad_rules[0] = { 1301 .itr_base = 0x0, 1302 .itr_limit = 0x20000000, 1303 .itr_sock_way = 2, 1304 .itr_chan_way = 1, 1305 .itr_sock_gran = IMC_TAD_GRAN_64B, 1306 .itr_chan_gran = IMC_TAD_GRAN_64B, 1307 .itr_ntargets = 4, 1308 .itr_targets = { 0, 0, 0, 0 } 1309 }, 1310 .itad_rules[1] = { 1311 .itr_base = 0x20000000, 1312 .itr_limit = 0x60000000, 1313 .itr_sock_way = 1, 1314 .itr_chan_way = 1, 1315 .itr_sock_gran = IMC_TAD_GRAN_64B, 1316 .itr_chan_gran = IMC_TAD_GRAN_64B, 1317 .itr_ntargets = 4, 1318 .itr_targets = { 0, 0, 0, 0 } 1319 }, 1320 .itad_rules[2] = { 1321 .itr_base = 0x60000000, 1322 .itr_limit = 0x80000000, 1323 .itr_sock_way = 2, 1324 .itr_chan_way = 1, 1325 .itr_sock_gran = IMC_TAD_GRAN_64B, 1326 .itr_chan_gran = IMC_TAD_GRAN_64B, 1327 .itr_ntargets = 4, 1328 .itr_targets = { 0, 0, 0, 0 } 1329 } 1330 }, 1331 .isock_nimc = 1, 1332 .isock_imcs[0] = { 1333 .icn_nchannels = 1, 1334 .icn_dimm_type = IMC_DIMM_DDR3, 1335 .icn_ecc = B_TRUE, 1336 .icn_lockstep = B_FALSE, 1337 .icn_closed = B_FALSE, 1338 .icn_channels[0] = { 1339 .ich_ndimms = 1, 1340 .ich_dimms[0] = { 1341 .idimm_present = B_TRUE, 1342 .idimm_nbanks = 3, 1343 .idimm_width = 8, 1344 .idimm_density = 2, 1345 .idimm_nranks = 2, 1346 .idimm_nrows = 14, 1347 .idimm_ncolumns = 10, 1348 .idimm_size = 0x40000000 1349 }, 1350 .ich_ntad_offsets = 12, 1351 .ich_tad_offsets = { 0, 0x10000000, 0, 0, 0, 0, 1352 0, 0, 0, 0, 0 }, 1353 .ich_nrankileaves = 8, 1354 .ich_rankileaves[0] = { 1355 .irle_enabled = B_TRUE, 1356 .irle_nways = 1, 1357 .irle_nwaysbits = 1, 1358 .irle_limit = 0x40000000, 1359 .irle_nentries = 8, 1360 .irle_entries[0] = { 0x0, 0x0 }, 1361 } 1362 } 1363 } 1364 } 1365 }; 1366 1367 static const imc_t imc_sad_2s_skx_10t8 = { 1368 .imc_gen = IMC_GEN_SKYLAKE, 1369 .imc_nsockets = 2, 1370 .imc_sockets[0] = { 1371 .isock_nodeid = 0, 1372 .isock_valid = IMC_SOCKET_V_VALID, 1373 .isock_sad = { 1374 .isad_flags = 0, 1375 .isad_valid = IMC_SAD_V_VALID, 1376 .isad_tolm = 0x80000000, 1377 .isad_tohm = 0, 1378 .isad_nrules = 24, 1379 .isad_rules[0] = { 1380 .isr_enable = B_TRUE, 1381 .isr_limit = 0x80000000, 1382 .isr_imode = IMC_SAD_IMODE_10t8, 1383 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 1384 .isr_targets = { 8, 1, 8, 1, 8, 1, 8, 1 } 1385 }, 1386 .isad_mcroute = { 1387 .ismc_nroutes = 6, 1388 .ismc_mcroutes[0] = { 0, 0 } 1389 } 1390 }, 1391 .isock_ntad = 1, 1392 .isock_tad[0] = { 1393 .itad_flags = 0, 1394 .itad_nrules = 8, 1395 .itad_rules[0] = { 1396 .itr_base = 0x0, 1397 .itr_limit = 0x80000000, 1398 .itr_sock_way = 2, 1399 .itr_chan_way = 1, 1400 .itr_sock_gran = IMC_TAD_GRAN_256B, 1401 .itr_chan_gran = IMC_TAD_GRAN_64B, 1402 .itr_ntargets = 4, 1403 .itr_targets = { 0, 0, 0, 0 } 1404 } 1405 }, 1406 .isock_nimc = 1, 1407 .isock_imcs[0] = { 1408 .icn_nchannels = 1, 1409 .icn_dimm_type = IMC_DIMM_DDR4, 1410 .icn_ecc = B_TRUE, 1411 .icn_lockstep = B_FALSE, 1412 .icn_closed = B_FALSE, 1413 .icn_channels[0] = { 1414 .ich_ndimms = 1, 1415 .ich_dimms[0] = { 1416 .idimm_present = B_TRUE, 1417 .idimm_nbanks = 3, 1418 .idimm_width = 8, 1419 .idimm_density = 2, 1420 .idimm_nranks = 2, 1421 .idimm_nrows = 14, 1422 .idimm_ncolumns = 10, 1423 .idimm_size = 0x40000000 1424 }, 1425 .ich_ntad_offsets = 12, 1426 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1427 0, 0 }, 1428 .ich_nrankileaves = 4, 1429 .ich_rankileaves[0] = { 1430 .irle_enabled = B_TRUE, 1431 .irle_nways = 1, 1432 .irle_nwaysbits = 1, 1433 .irle_limit = 0x40000000, 1434 .irle_nentries = 8, 1435 .irle_entries[0] = { 0x0, 0x0 }, 1436 } 1437 } 1438 } 1439 }, 1440 .imc_sockets[1] = { 1441 .isock_nodeid = 1, 1442 .isock_valid = IMC_SOCKET_V_VALID, 1443 .isock_sad = { 1444 .isad_flags = 0, 1445 .isad_valid = IMC_SAD_V_VALID, 1446 .isad_tolm = 0x80000000, 1447 .isad_tohm = 0, 1448 .isad_nrules = 24, 1449 .isad_rules[0] = { 1450 .isr_enable = B_TRUE, 1451 .isr_limit = 0x80000000, 1452 .isr_imode = IMC_SAD_IMODE_10t8, 1453 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 1454 .isr_targets = { 0, 8, 0, 8, 0, 8, 0, 8 } 1455 }, 1456 .isad_mcroute = { 1457 .ismc_nroutes = 6, 1458 .ismc_mcroutes[0] = { 0, 0 } 1459 } 1460 }, 1461 .isock_ntad = 1, 1462 .isock_tad[0] = { 1463 .itad_flags = 0, 1464 .itad_nrules = 8, 1465 .itad_rules[0] = { 1466 .itr_base = 0x0, 1467 .itr_limit = 0x80000000, 1468 .itr_sock_way = 2, 1469 .itr_chan_way = 1, 1470 .itr_sock_gran = IMC_TAD_GRAN_256B, 1471 .itr_chan_gran = IMC_TAD_GRAN_64B, 1472 .itr_ntargets = 4, 1473 .itr_targets = { 0, 0, 0, 0 } 1474 } 1475 }, 1476 .isock_nimc = 1, 1477 .isock_imcs[0] = { 1478 .icn_nchannels = 1, 1479 .icn_dimm_type = IMC_DIMM_DDR4, 1480 .icn_ecc = B_TRUE, 1481 .icn_lockstep = B_FALSE, 1482 .icn_closed = B_FALSE, 1483 .icn_channels[0] = { 1484 .ich_ndimms = 1, 1485 .ich_dimms[0] = { 1486 .idimm_present = B_TRUE, 1487 .idimm_nbanks = 3, 1488 .idimm_width = 8, 1489 .idimm_density = 2, 1490 .idimm_nranks = 2, 1491 .idimm_nrows = 14, 1492 .idimm_ncolumns = 10, 1493 .idimm_size = 0x40000000 1494 }, 1495 .ich_ntad_offsets = 12, 1496 .ich_tad_offsets = { 0x100, 0, 0, 0, 0, 0, 0, 1497 0, 0, 0, 0 }, 1498 .ich_nrankileaves = 4, 1499 .ich_rankileaves[0] = { 1500 .irle_enabled = B_TRUE, 1501 .irle_nways = 1, 1502 .irle_nwaysbits = 1, 1503 .irle_limit = 0x40000000, 1504 .irle_nentries = 8, 1505 .irle_entries[0] = { 0x0, 0x0 }, 1506 } 1507 } 1508 } 1509 } 1510 }; 1511 1512 /* 1513 * This performs 2 way interleaving across memory controllers, rather than 1514 * across sockets. 1515 */ 1516 static const imc_t imc_sad_1s_skx_14t12 = { 1517 .imc_gen = IMC_GEN_SKYLAKE, 1518 .imc_nsockets = 1, 1519 .imc_sockets[0] = { 1520 .isock_nodeid = 0, 1521 .isock_valid = IMC_SOCKET_V_VALID, 1522 .isock_sad = { 1523 .isad_flags = 0, 1524 .isad_valid = IMC_SAD_V_VALID, 1525 .isad_tolm = 0x80000000, 1526 .isad_tohm = 0, 1527 .isad_nrules = 24, 1528 .isad_rules[0] = { 1529 .isr_enable = B_TRUE, 1530 .isr_limit = 0x80000000, 1531 .isr_imode = IMC_SAD_IMODE_14t12, 1532 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 1533 .isr_targets = { 8, 9, 8, 9, 8, 9, 8, 9 } 1534 }, 1535 .isad_mcroute = { 1536 .ismc_nroutes = 6, 1537 .ismc_mcroutes[0] = { 0, 0 }, 1538 .ismc_mcroutes[1] = { 1, 0 } 1539 } 1540 }, 1541 .isock_ntad = 2, 1542 .isock_tad[0] = { 1543 .itad_flags = 0, 1544 .itad_nrules = 8, 1545 .itad_rules[0] = { 1546 .itr_base = 0x0, 1547 .itr_limit = 0x80000000, 1548 .itr_sock_way = 2, 1549 .itr_chan_way = 1, 1550 .itr_sock_gran = IMC_TAD_GRAN_4KB, 1551 .itr_chan_gran = IMC_TAD_GRAN_64B, 1552 .itr_ntargets = 4, 1553 .itr_targets = { 0, 0, 0, 0 } 1554 } 1555 }, 1556 .isock_tad[1] = { 1557 .itad_flags = 0, 1558 .itad_nrules = 8, 1559 .itad_rules[0] = { 1560 .itr_base = 0x0, 1561 .itr_limit = 0x80000000, 1562 .itr_sock_way = 2, 1563 .itr_chan_way = 1, 1564 .itr_sock_gran = IMC_TAD_GRAN_4KB, 1565 .itr_chan_gran = IMC_TAD_GRAN_64B, 1566 .itr_ntargets = 4, 1567 .itr_targets = { 0, 0, 0, 0 } 1568 } 1569 }, 1570 .isock_nimc = 2, 1571 .isock_imcs[0] = { 1572 .icn_nchannels = 1, 1573 .icn_dimm_type = IMC_DIMM_DDR4, 1574 .icn_ecc = B_TRUE, 1575 .icn_lockstep = B_FALSE, 1576 .icn_closed = B_FALSE, 1577 .icn_channels[0] = { 1578 .ich_ndimms = 1, 1579 .ich_dimms[0] = { 1580 .idimm_present = B_TRUE, 1581 .idimm_nbanks = 3, 1582 .idimm_width = 8, 1583 .idimm_density = 2, 1584 .idimm_nranks = 2, 1585 .idimm_nrows = 14, 1586 .idimm_ncolumns = 10, 1587 .idimm_size = 0x40000000 1588 }, 1589 .ich_ntad_offsets = 12, 1590 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1591 0, 0 }, 1592 .ich_nrankileaves = 4, 1593 .ich_rankileaves[0] = { 1594 .irle_enabled = B_TRUE, 1595 .irle_nways = 1, 1596 .irle_nwaysbits = 1, 1597 .irle_limit = 0x40000000, 1598 .irle_nentries = 8, 1599 .irle_entries[0] = { 0x0, 0x0 }, 1600 } 1601 } 1602 }, 1603 .isock_imcs[1] = { 1604 .icn_nchannels = 1, 1605 .icn_dimm_type = IMC_DIMM_DDR4, 1606 .icn_ecc = B_TRUE, 1607 .icn_lockstep = B_FALSE, 1608 .icn_closed = B_FALSE, 1609 .icn_channels[0] = { 1610 .ich_ndimms = 1, 1611 .ich_dimms[0] = { 1612 .idimm_present = B_TRUE, 1613 .idimm_nbanks = 3, 1614 .idimm_width = 8, 1615 .idimm_density = 2, 1616 .idimm_nranks = 2, 1617 .idimm_nrows = 14, 1618 .idimm_ncolumns = 10, 1619 .idimm_size = 0x40000000 1620 }, 1621 .ich_ntad_offsets = 12, 1622 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1623 0, 0 }, 1624 .ich_nrankileaves = 4, 1625 .ich_rankileaves[0] = { 1626 .irle_enabled = B_TRUE, 1627 .irle_nways = 1, 1628 .irle_nwaysbits = 1, 1629 .irle_limit = 0x40000000, 1630 .irle_nentries = 8, 1631 .irle_entries[0] = { 0x0, 0x0 }, 1632 } 1633 } 1634 } 1635 }, 1636 }; 1637 1638 static const imc_t imc_sad_4s_8w_skx_32t30 = { 1639 .imc_gen = IMC_GEN_SKYLAKE, 1640 .imc_nsockets = 4, 1641 .imc_sockets[0] = { 1642 .isock_nodeid = 0, 1643 .isock_valid = IMC_SOCKET_V_VALID, 1644 .isock_sad = { 1645 .isad_flags = 0, 1646 .isad_valid = IMC_SAD_V_VALID, 1647 .isad_tolm = 0x80000000, 1648 .isad_tohm = 0x280000000ULL, 1649 .isad_nrules = 24, 1650 .isad_rules[0] = { 1651 .isr_enable = B_TRUE, 1652 .isr_limit = 0x80000000ULL, 1653 .isr_imode = IMC_SAD_IMODE_32t30, 1654 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 1655 .isr_targets = { 8, 9, 8, 9, 8, 9, 8, 9 } 1656 }, 1657 .isad_rules[1] = { 1658 .isr_enable = B_TRUE, 1659 .isr_limit = 0x280000000ULL, 1660 .isr_imode = IMC_SAD_IMODE_32t30, 1661 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 1662 .isr_targets = { 3, 3, 0, 0, 1, 1, 2, 2 } 1663 }, 1664 .isad_mcroute = { 1665 .ismc_nroutes = 6, 1666 .ismc_mcroutes[0] = { 0, 0 }, 1667 .ismc_mcroutes[1] = { 1, 0 } 1668 } 1669 }, 1670 .isock_ntad = 2, 1671 .isock_tad[0] = { 1672 .itad_flags = 0, 1673 .itad_nrules = 8, 1674 .itad_rules[0] = { 1675 .itr_base = 0x0, 1676 .itr_limit = 0x80000000, 1677 .itr_sock_way = 8, 1678 .itr_chan_way = 1, 1679 .itr_sock_gran = IMC_TAD_GRAN_1GB, 1680 .itr_chan_gran = IMC_TAD_GRAN_64B, 1681 .itr_ntargets = 4, 1682 .itr_targets = { 0, 0, 0, 0 } 1683 }, 1684 .itad_rules[1] = { 1685 .itr_base = 0x100000000ULL, 1686 .itr_limit = 0x280000000ULL, 1687 .itr_sock_way = 8, 1688 .itr_chan_way = 1, 1689 .itr_sock_gran = IMC_TAD_GRAN_1GB, 1690 .itr_chan_gran = IMC_TAD_GRAN_64B, 1691 .itr_ntargets = 4, 1692 .itr_targets = { 0, 0, 0, 0 } 1693 } 1694 1695 }, 1696 .isock_tad[1] = { 1697 .itad_flags = 0, 1698 .itad_nrules = 8, 1699 .itad_rules[0] = { 1700 .itr_base = 0x0, 1701 .itr_limit = 0x80000000, 1702 .itr_sock_way = 8, 1703 .itr_chan_way = 1, 1704 .itr_sock_gran = IMC_TAD_GRAN_1GB, 1705 .itr_chan_gran = IMC_TAD_GRAN_64B, 1706 .itr_ntargets = 4, 1707 .itr_targets = { 0, 0, 0, 0 } 1708 }, 1709 .itad_rules[1] = { 1710 .itr_base = 0x100000000ULL, 1711 .itr_limit = 0x280000000ULL, 1712 .itr_sock_way = 8, 1713 .itr_chan_way = 1, 1714 .itr_sock_gran = IMC_TAD_GRAN_1GB, 1715 .itr_chan_gran = IMC_TAD_GRAN_64B, 1716 .itr_ntargets = 4, 1717 .itr_targets = { 0, 0, 0, 0 } 1718 } 1719 }, 1720 .isock_nimc = 2, 1721 .isock_imcs[0] = { 1722 .icn_nchannels = 1, 1723 .icn_dimm_type = IMC_DIMM_DDR4, 1724 .icn_ecc = B_TRUE, 1725 .icn_lockstep = B_FALSE, 1726 .icn_closed = B_FALSE, 1727 .icn_channels[0] = { 1728 .ich_ndimms = 1, 1729 .ich_dimms[0] = { 1730 .idimm_present = B_TRUE, 1731 .idimm_nbanks = 3, 1732 .idimm_width = 8, 1733 .idimm_density = 2, 1734 .idimm_nranks = 2, 1735 .idimm_nrows = 14, 1736 .idimm_ncolumns = 10, 1737 .idimm_size = 0x40000000 1738 }, 1739 .ich_ntad_offsets = 12, 1740 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 1741 0, 0, 0, 0, 0 }, 1742 .ich_nrankileaves = 4, 1743 .ich_rankileaves[0] = { 1744 .irle_enabled = B_TRUE, 1745 .irle_nways = 1, 1746 .irle_nwaysbits = 1, 1747 .irle_limit = 0x40000000, 1748 .irle_nentries = 8, 1749 .irle_entries[0] = { 0x0, 0x0 }, 1750 } 1751 } 1752 }, 1753 .isock_imcs[1] = { 1754 .icn_nchannels = 1, 1755 .icn_dimm_type = IMC_DIMM_DDR4, 1756 .icn_ecc = B_TRUE, 1757 .icn_lockstep = B_FALSE, 1758 .icn_closed = B_FALSE, 1759 .icn_channels[0] = { 1760 .ich_ndimms = 1, 1761 .ich_dimms[0] = { 1762 .idimm_present = B_TRUE, 1763 .idimm_nbanks = 3, 1764 .idimm_width = 8, 1765 .idimm_density = 2, 1766 .idimm_nranks = 2, 1767 .idimm_nrows = 14, 1768 .idimm_ncolumns = 10, 1769 .idimm_size = 0x40000000 1770 }, 1771 .ich_ntad_offsets = 12, 1772 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 1773 0, 0, 0, 0, 0 }, 1774 .ich_nrankileaves = 4, 1775 .ich_rankileaves[0] = { 1776 .irle_enabled = B_TRUE, 1777 .irle_nways = 1, 1778 .irle_nwaysbits = 1, 1779 .irle_limit = 0x40000000, 1780 .irle_nentries = 8, 1781 .irle_entries[0] = { 0x0, 0x0 }, 1782 } 1783 } 1784 } 1785 }, 1786 .imc_sockets[1] = { 1787 .isock_nodeid = 1, 1788 .isock_valid = IMC_SOCKET_V_VALID, 1789 .isock_sad = { 1790 .isad_flags = 0, 1791 .isad_valid = IMC_SAD_V_VALID, 1792 .isad_tolm = 0x80000000, 1793 .isad_tohm = 0x280000000ULL, 1794 .isad_nrules = 24, 1795 .isad_rules[0] = { 1796 .isr_enable = B_TRUE, 1797 .isr_limit = 0x80000000ULL, 1798 .isr_imode = IMC_SAD_IMODE_32t30, 1799 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 1800 .isr_targets = { 0, 0, 0, 0, 0, 0, 0, 0 } 1801 }, 1802 .isad_rules[1] = { 1803 .isr_enable = B_TRUE, 1804 .isr_limit = 0x280000000ULL, 1805 .isr_imode = IMC_SAD_IMODE_32t30, 1806 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 1807 .isr_targets = { 3, 3, 0, 0, 8, 9, 2, 2 } 1808 }, 1809 .isad_mcroute = { 1810 .ismc_nroutes = 6, 1811 .ismc_mcroutes[0] = { 0, 0 }, 1812 .ismc_mcroutes[1] = { 1, 0 } 1813 } 1814 }, 1815 .isock_ntad = 2, 1816 .isock_tad[0] = { 1817 .itad_flags = 0, 1818 .itad_nrules = 8, 1819 .itad_rules[0] = { 1820 .itr_base = 0x0, 1821 .itr_limit = 0x80000000, 1822 .itr_sock_way = 8, 1823 .itr_chan_way = 1, 1824 .itr_sock_gran = IMC_TAD_GRAN_1GB, 1825 .itr_chan_gran = IMC_TAD_GRAN_64B, 1826 .itr_ntargets = 4, 1827 .itr_targets = { 0, 0, 0, 0 } 1828 }, 1829 .itad_rules[1] = { 1830 .itr_base = 0x100000000ULL, 1831 .itr_limit = 0x280000000ULL, 1832 .itr_sock_way = 8, 1833 .itr_chan_way = 1, 1834 .itr_sock_gran = IMC_TAD_GRAN_1GB, 1835 .itr_chan_gran = IMC_TAD_GRAN_64B, 1836 .itr_ntargets = 4, 1837 .itr_targets = { 0, 0, 0, 0 } 1838 } 1839 1840 }, 1841 .isock_tad[1] = { 1842 .itad_flags = 0, 1843 .itad_nrules = 8, 1844 .itad_rules[0] = { 1845 .itr_base = 0x0, 1846 .itr_limit = 0x80000000, 1847 .itr_sock_way = 8, 1848 .itr_chan_way = 1, 1849 .itr_sock_gran = IMC_TAD_GRAN_1GB, 1850 .itr_chan_gran = IMC_TAD_GRAN_64B, 1851 .itr_ntargets = 4, 1852 .itr_targets = { 0, 0, 0, 0 } 1853 }, 1854 .itad_rules[1] = { 1855 .itr_base = 0x100000000ULL, 1856 .itr_limit = 0x280000000ULL, 1857 .itr_sock_way = 8, 1858 .itr_chan_way = 1, 1859 .itr_sock_gran = IMC_TAD_GRAN_1GB, 1860 .itr_chan_gran = IMC_TAD_GRAN_64B, 1861 .itr_ntargets = 4, 1862 .itr_targets = { 0, 0, 0, 0 } 1863 } 1864 }, 1865 .isock_nimc = 2, 1866 .isock_imcs[0] = { 1867 .icn_nchannels = 1, 1868 .icn_dimm_type = IMC_DIMM_DDR4, 1869 .icn_ecc = B_TRUE, 1870 .icn_lockstep = B_FALSE, 1871 .icn_closed = B_FALSE, 1872 .icn_channels[0] = { 1873 .ich_ndimms = 1, 1874 .ich_dimms[0] = { 1875 .idimm_present = B_TRUE, 1876 .idimm_nbanks = 3, 1877 .idimm_width = 8, 1878 .idimm_density = 2, 1879 .idimm_nranks = 2, 1880 .idimm_nrows = 14, 1881 .idimm_ncolumns = 10, 1882 .idimm_size = 0x40000000 1883 }, 1884 .ich_ntad_offsets = 12, 1885 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 1886 0, 0, 0, 0, 0 }, 1887 .ich_nrankileaves = 4, 1888 .ich_rankileaves[0] = { 1889 .irle_enabled = B_TRUE, 1890 .irle_nways = 1, 1891 .irle_nwaysbits = 1, 1892 .irle_limit = 0x40000000, 1893 .irle_nentries = 8, 1894 .irle_entries[0] = { 0x0, 0x0 }, 1895 } 1896 } 1897 }, 1898 .isock_imcs[1] = { 1899 .icn_nchannels = 1, 1900 .icn_dimm_type = IMC_DIMM_DDR4, 1901 .icn_ecc = B_TRUE, 1902 .icn_lockstep = B_FALSE, 1903 .icn_closed = B_FALSE, 1904 .icn_channels[0] = { 1905 .ich_ndimms = 1, 1906 .ich_dimms[0] = { 1907 .idimm_present = B_TRUE, 1908 .idimm_nbanks = 3, 1909 .idimm_width = 8, 1910 .idimm_density = 2, 1911 .idimm_nranks = 2, 1912 .idimm_nrows = 14, 1913 .idimm_ncolumns = 10, 1914 .idimm_size = 0x40000000 1915 }, 1916 .ich_ntad_offsets = 12, 1917 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 1918 0, 0, 0, 0, 0 }, 1919 .ich_nrankileaves = 4, 1920 .ich_rankileaves[0] = { 1921 .irle_enabled = B_TRUE, 1922 .irle_nways = 1, 1923 .irle_nwaysbits = 1, 1924 .irle_limit = 0x40000000, 1925 .irle_nentries = 8, 1926 .irle_entries[0] = { 0x0, 0x0 }, 1927 } 1928 } 1929 } 1930 }, 1931 .imc_sockets[2] = { 1932 .isock_nodeid = 2, 1933 .isock_valid = IMC_SOCKET_V_VALID, 1934 .isock_sad = { 1935 .isad_flags = 0, 1936 .isad_valid = IMC_SAD_V_VALID, 1937 .isad_tolm = 0x80000000, 1938 .isad_tohm = 0x280000000ULL, 1939 .isad_nrules = 24, 1940 .isad_rules[0] = { 1941 .isr_enable = B_TRUE, 1942 .isr_limit = 0x80000000ULL, 1943 .isr_imode = IMC_SAD_IMODE_32t30, 1944 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 1945 .isr_targets = { 0, 0, 0, 0, 0, 0, 0, 0 } 1946 }, 1947 .isad_rules[1] = { 1948 .isr_enable = B_TRUE, 1949 .isr_limit = 0x280000000ULL, 1950 .isr_imode = IMC_SAD_IMODE_32t30, 1951 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 1952 .isr_targets = { 3, 3, 0, 0, 1, 1, 8, 9 } 1953 }, 1954 .isad_mcroute = { 1955 .ismc_nroutes = 6, 1956 .ismc_mcroutes[0] = { 0, 0 }, 1957 .ismc_mcroutes[1] = { 1, 0 } 1958 } 1959 }, 1960 .isock_ntad = 2, 1961 .isock_tad[0] = { 1962 .itad_flags = 0, 1963 .itad_nrules = 8, 1964 .itad_rules[0] = { 1965 .itr_base = 0x0, 1966 .itr_limit = 0x80000000, 1967 .itr_sock_way = 8, 1968 .itr_chan_way = 1, 1969 .itr_sock_gran = IMC_TAD_GRAN_1GB, 1970 .itr_chan_gran = IMC_TAD_GRAN_64B, 1971 .itr_ntargets = 4, 1972 .itr_targets = { 0, 0, 0, 0 } 1973 }, 1974 .itad_rules[1] = { 1975 .itr_base = 0x100000000ULL, 1976 .itr_limit = 0x280000000ULL, 1977 .itr_sock_way = 8, 1978 .itr_chan_way = 1, 1979 .itr_sock_gran = IMC_TAD_GRAN_1GB, 1980 .itr_chan_gran = IMC_TAD_GRAN_64B, 1981 .itr_ntargets = 4, 1982 .itr_targets = { 0, 0, 0, 0 } 1983 } 1984 1985 }, 1986 .isock_tad[1] = { 1987 .itad_flags = 0, 1988 .itad_nrules = 8, 1989 .itad_rules[0] = { 1990 .itr_base = 0x0, 1991 .itr_limit = 0x80000000, 1992 .itr_sock_way = 8, 1993 .itr_chan_way = 1, 1994 .itr_sock_gran = IMC_TAD_GRAN_1GB, 1995 .itr_chan_gran = IMC_TAD_GRAN_64B, 1996 .itr_ntargets = 4, 1997 .itr_targets = { 0, 0, 0, 0 } 1998 }, 1999 .itad_rules[1] = { 2000 .itr_base = 0x100000000ULL, 2001 .itr_limit = 0x280000000ULL, 2002 .itr_sock_way = 8, 2003 .itr_chan_way = 1, 2004 .itr_sock_gran = IMC_TAD_GRAN_1GB, 2005 .itr_chan_gran = IMC_TAD_GRAN_64B, 2006 .itr_ntargets = 4, 2007 .itr_targets = { 0, 0, 0, 0 } 2008 } 2009 }, 2010 .isock_nimc = 2, 2011 .isock_imcs[0] = { 2012 .icn_nchannels = 1, 2013 .icn_dimm_type = IMC_DIMM_DDR4, 2014 .icn_ecc = B_TRUE, 2015 .icn_lockstep = B_FALSE, 2016 .icn_closed = B_FALSE, 2017 .icn_channels[0] = { 2018 .ich_ndimms = 1, 2019 .ich_dimms[0] = { 2020 .idimm_present = B_TRUE, 2021 .idimm_nbanks = 3, 2022 .idimm_width = 8, 2023 .idimm_density = 2, 2024 .idimm_nranks = 2, 2025 .idimm_nrows = 14, 2026 .idimm_ncolumns = 10, 2027 .idimm_size = 0x40000000 2028 }, 2029 .ich_ntad_offsets = 12, 2030 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 2031 0, 0, 0, 0, 0 }, 2032 .ich_nrankileaves = 4, 2033 .ich_rankileaves[0] = { 2034 .irle_enabled = B_TRUE, 2035 .irle_nways = 1, 2036 .irle_nwaysbits = 1, 2037 .irle_limit = 0x40000000, 2038 .irle_nentries = 8, 2039 .irle_entries[0] = { 0x0, 0x0 }, 2040 } 2041 } 2042 }, 2043 .isock_imcs[1] = { 2044 .icn_nchannels = 1, 2045 .icn_dimm_type = IMC_DIMM_DDR4, 2046 .icn_ecc = B_TRUE, 2047 .icn_lockstep = B_FALSE, 2048 .icn_closed = B_FALSE, 2049 .icn_channels[0] = { 2050 .ich_ndimms = 1, 2051 .ich_dimms[0] = { 2052 .idimm_present = B_TRUE, 2053 .idimm_nbanks = 3, 2054 .idimm_width = 8, 2055 .idimm_density = 2, 2056 .idimm_nranks = 2, 2057 .idimm_nrows = 14, 2058 .idimm_ncolumns = 10, 2059 .idimm_size = 0x40000000 2060 }, 2061 .ich_ntad_offsets = 12, 2062 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 2063 0, 0, 0, 0, 0 }, 2064 .ich_nrankileaves = 4, 2065 .ich_rankileaves[0] = { 2066 .irle_enabled = B_TRUE, 2067 .irle_nways = 1, 2068 .irle_nwaysbits = 1, 2069 .irle_limit = 0x40000000, 2070 .irle_nentries = 8, 2071 .irle_entries[0] = { 0x0, 0x0 }, 2072 } 2073 } 2074 } 2075 }, 2076 .imc_sockets[3] = { 2077 .isock_nodeid = 3, 2078 .isock_valid = IMC_SOCKET_V_VALID, 2079 .isock_sad = { 2080 .isad_flags = 0, 2081 .isad_valid = IMC_SAD_V_VALID, 2082 .isad_tolm = 0x80000000, 2083 .isad_tohm = 0x280000000ULL, 2084 .isad_nrules = 24, 2085 .isad_rules[0] = { 2086 .isr_enable = B_TRUE, 2087 .isr_limit = 0x80000000ULL, 2088 .isr_imode = IMC_SAD_IMODE_32t30, 2089 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 2090 .isr_targets = { 0, 0, 0, 0, 0, 0, 0, 0 } 2091 }, 2092 .isad_rules[1] = { 2093 .isr_enable = B_TRUE, 2094 .isr_limit = 0x280000000ULL, 2095 .isr_imode = IMC_SAD_IMODE_32t30, 2096 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 2097 .isr_targets = { 8, 9, 0, 0, 1, 1, 2, 2 } 2098 }, 2099 .isad_mcroute = { 2100 .ismc_nroutes = 6, 2101 .ismc_mcroutes[0] = { 0, 0 }, 2102 .ismc_mcroutes[1] = { 1, 0 } 2103 } 2104 }, 2105 .isock_ntad = 2, 2106 .isock_tad[0] = { 2107 .itad_flags = 0, 2108 .itad_nrules = 8, 2109 .itad_rules[0] = { 2110 .itr_base = 0x0, 2111 .itr_limit = 0x80000000, 2112 .itr_sock_way = 8, 2113 .itr_chan_way = 1, 2114 .itr_sock_gran = IMC_TAD_GRAN_1GB, 2115 .itr_chan_gran = IMC_TAD_GRAN_64B, 2116 .itr_ntargets = 4, 2117 .itr_targets = { 0, 0, 0, 0 } 2118 }, 2119 .itad_rules[1] = { 2120 .itr_base = 0x100000000ULL, 2121 .itr_limit = 0x280000000ULL, 2122 .itr_sock_way = 8, 2123 .itr_chan_way = 1, 2124 .itr_sock_gran = IMC_TAD_GRAN_1GB, 2125 .itr_chan_gran = IMC_TAD_GRAN_64B, 2126 .itr_ntargets = 4, 2127 .itr_targets = { 0, 0, 0, 0 } 2128 } 2129 2130 }, 2131 .isock_tad[1] = { 2132 .itad_flags = 0, 2133 .itad_nrules = 8, 2134 .itad_rules[0] = { 2135 .itr_base = 0x0, 2136 .itr_limit = 0x80000000, 2137 .itr_sock_way = 8, 2138 .itr_chan_way = 1, 2139 .itr_sock_gran = IMC_TAD_GRAN_1GB, 2140 .itr_chan_gran = IMC_TAD_GRAN_64B, 2141 .itr_ntargets = 4, 2142 .itr_targets = { 0, 0, 0, 0 } 2143 }, 2144 .itad_rules[1] = { 2145 .itr_base = 0x100000000ULL, 2146 .itr_limit = 0x280000000ULL, 2147 .itr_sock_way = 8, 2148 .itr_chan_way = 1, 2149 .itr_sock_gran = IMC_TAD_GRAN_1GB, 2150 .itr_chan_gran = IMC_TAD_GRAN_64B, 2151 .itr_ntargets = 4, 2152 .itr_targets = { 0, 0, 0, 0 } 2153 } 2154 }, 2155 .isock_nimc = 2, 2156 .isock_imcs[0] = { 2157 .icn_nchannels = 1, 2158 .icn_dimm_type = IMC_DIMM_DDR4, 2159 .icn_ecc = B_TRUE, 2160 .icn_lockstep = B_FALSE, 2161 .icn_closed = B_FALSE, 2162 .icn_channels[0] = { 2163 .ich_ndimms = 1, 2164 .ich_dimms[0] = { 2165 .idimm_present = B_TRUE, 2166 .idimm_nbanks = 3, 2167 .idimm_width = 8, 2168 .idimm_density = 2, 2169 .idimm_nranks = 2, 2170 .idimm_nrows = 14, 2171 .idimm_ncolumns = 10, 2172 .idimm_size = 0x40000000 2173 }, 2174 .ich_ntad_offsets = 12, 2175 .ich_tad_offsets = { 0, 0x200000000ULL, 0, 0, 2176 0, 0, 0, 0, 0, 0, 0 }, 2177 .ich_nrankileaves = 4, 2178 .ich_rankileaves[0] = { 2179 .irle_enabled = B_TRUE, 2180 .irle_nways = 1, 2181 .irle_nwaysbits = 1, 2182 .irle_limit = 0x40000000, 2183 .irle_nentries = 8, 2184 .irle_entries[0] = { 0x0, 0x0 }, 2185 } 2186 } 2187 }, 2188 .isock_imcs[1] = { 2189 .icn_nchannels = 1, 2190 .icn_dimm_type = IMC_DIMM_DDR4, 2191 .icn_ecc = B_TRUE, 2192 .icn_lockstep = B_FALSE, 2193 .icn_closed = B_FALSE, 2194 .icn_channels[0] = { 2195 .ich_ndimms = 1, 2196 .ich_dimms[0] = { 2197 .idimm_present = B_TRUE, 2198 .idimm_nbanks = 3, 2199 .idimm_width = 8, 2200 .idimm_density = 2, 2201 .idimm_nranks = 2, 2202 .idimm_nrows = 14, 2203 .idimm_ncolumns = 10, 2204 .idimm_size = 0x40000000 2205 }, 2206 .ich_ntad_offsets = 12, 2207 .ich_tad_offsets = { 0, 0x240000000ULL, 0, 0, 2208 0, 0, 0, 0, 0, 0, 0 }, 2209 .ich_nrankileaves = 4, 2210 .ich_rankileaves[0] = { 2211 .irle_enabled = B_TRUE, 2212 .irle_nways = 1, 2213 .irle_nwaysbits = 1, 2214 .irle_limit = 0x40000000, 2215 .irle_nentries = 8, 2216 .irle_entries[0] = { 0x0, 0x0 }, 2217 } 2218 } 2219 } 2220 }, 2221 }; 2222 2223 const imc_test_case_t imc_test_sad[] = { 2224 /* 2225 * This first set of tests just makes sure that we properly handle SAD 2226 * interleaving rules and get routed to the right socket. 2227 */ 2228 { 2229 .itc_desc = "2 Socket SAD 8-6 Interleave (1)", 2230 .itc_imc = &imc_sad_2s_basic, 2231 .itc_pa = 0x0, 2232 .itc_pass = B_TRUE, 2233 .itc_nodeid = 0, 2234 .itc_tadid = 0, 2235 .itc_channelid = 0, 2236 .itc_chanaddr = 0x0, 2237 .itc_dimmid = 0, 2238 .itc_rankid = 0, 2239 .itc_rankaddr = 0x0 2240 }, { 2241 .itc_desc = "2 Socket SAD 8-6 Interleave (2)", 2242 .itc_imc = &imc_sad_2s_basic, 2243 .itc_pa = 0x12345678, 2244 .itc_pass = B_TRUE, 2245 .itc_nodeid = 1, 2246 .itc_tadid = 0, 2247 .itc_channelid = 0, 2248 .itc_chanaddr = 0x91a2b38, 2249 .itc_dimmid = 0, 2250 .itc_rankid = 0, 2251 .itc_rankaddr = 0x91a2b38 2252 }, { 2253 .itc_desc = "2 Socket SAD 8-6 Interleave (3)", 2254 .itc_imc = &imc_sad_2s_basic, 2255 .itc_pa = 0x12345638, 2256 .itc_pass = B_TRUE, 2257 .itc_nodeid = 0, 2258 .itc_tadid = 0, 2259 .itc_channelid = 0, 2260 .itc_chanaddr = 0x91a2b38, 2261 .itc_dimmid = 0, 2262 .itc_rankid = 0, 2263 .itc_rankaddr = 0x91a2b38 2264 }, 2265 /* 2266 * This is the same as above, but uses a 4-socket configuration instead. 2267 */ 2268 { 2269 .itc_desc = "4 Socket SAD 8-6 Interleave (1)", 2270 .itc_imc = &imc_sad_4s_basic, 2271 .itc_pa = 0x12345638, 2272 .itc_pass = B_TRUE, 2273 .itc_nodeid = 0, 2274 .itc_tadid = 0, 2275 .itc_channelid = 0, 2276 .itc_chanaddr = 0x48d15b8, 2277 .itc_dimmid = 0, 2278 .itc_rankid = 0, 2279 .itc_rankaddr = 0x48d15b8 2280 }, { 2281 .itc_desc = "4 Socket SAD 8-6 Interleave (2)", 2282 .itc_imc = &imc_sad_4s_basic, 2283 .itc_pa = 0x12345678, 2284 .itc_pass = B_TRUE, 2285 .itc_nodeid = 1, 2286 .itc_tadid = 0, 2287 .itc_channelid = 0, 2288 .itc_chanaddr = 0x48d15b8, 2289 .itc_dimmid = 0, 2290 .itc_rankid = 0, 2291 .itc_rankaddr = 0x48d15b8 2292 }, { 2293 .itc_desc = "4 Socket SAD 8-6 Interleave (3)", 2294 .itc_imc = &imc_sad_4s_basic, 2295 .itc_pa = 0x123456b8, 2296 .itc_pass = B_TRUE, 2297 .itc_nodeid = 2, 2298 .itc_tadid = 0, 2299 .itc_channelid = 0, 2300 .itc_chanaddr = 0x48d15b8, 2301 .itc_dimmid = 0, 2302 .itc_rankid = 0, 2303 .itc_rankaddr = 0x48d15b8 2304 }, { 2305 .itc_desc = "4 Socket SAD 8-6 Interleave (4)", 2306 .itc_imc = &imc_sad_4s_basic, 2307 .itc_pa = 0x123456f8, 2308 .itc_pass = B_TRUE, 2309 .itc_nodeid = 3, 2310 .itc_tadid = 0, 2311 .itc_channelid = 0, 2312 .itc_chanaddr = 0x48d15b8, 2313 .itc_dimmid = 0, 2314 .itc_rankid = 0, 2315 .itc_rankaddr = 0x48d15b8 2316 }, 2317 /* 2318 * This is a variant on the basic 2s tests. XOR mode is enabled, so we use that 2319 * to see that we actually have differences versus the basic 2s tests. 2320 */ 2321 { 2322 .itc_desc = "2 Socket SAD 8-6 XOR Interleave (1)", 2323 .itc_imc = &imc_sad_2s_xor, 2324 .itc_pa = 0x12345638, 2325 .itc_pass = B_TRUE, 2326 .itc_nodeid = 0, 2327 .itc_tadid = 0, 2328 .itc_channelid = 0, 2329 .itc_chanaddr = 0x91a2b38, 2330 .itc_dimmid = 0, 2331 .itc_rankid = 0, 2332 .itc_rankaddr = 0x91a2b38 2333 }, { 2334 .itc_desc = "2 Socket SAD 8-6 XOR Interleave (2)", 2335 .itc_imc = &imc_sad_2s_xor, 2336 .itc_pa = 0x12345678, 2337 .itc_pass = B_TRUE, 2338 .itc_nodeid = 1, 2339 .itc_tadid = 0, 2340 .itc_channelid = 0, 2341 .itc_chanaddr = 0x91a2b38, 2342 .itc_dimmid = 0, 2343 .itc_rankid = 0, 2344 .itc_rankaddr = 0x91a2b38 2345 }, { 2346 .itc_desc = "2 Socket SAD 8-6 XOR Interleave (3)", 2347 .itc_imc = &imc_sad_2s_xor, 2348 .itc_pa = 0x12355638, 2349 .itc_pass = B_TRUE, 2350 .itc_nodeid = 1, 2351 .itc_tadid = 0, 2352 .itc_channelid = 0, 2353 .itc_chanaddr = 0x91aab38, 2354 .itc_dimmid = 0, 2355 .itc_rankid = 0, 2356 .itc_rankaddr = 0x91aab38 2357 }, { 2358 .itc_desc = "2 Socket SAD 8-6 XOR Interleave (4)", 2359 .itc_imc = &imc_sad_2s_xor, 2360 .itc_pa = 0x12355678, 2361 .itc_pass = B_TRUE, 2362 .itc_nodeid = 0, 2363 .itc_tadid = 0, 2364 .itc_channelid = 0, 2365 .itc_chanaddr = 0x91aab38, 2366 .itc_dimmid = 0, 2367 .itc_rankid = 0, 2368 .itc_rankaddr = 0x91aab38 2369 }, { 2370 .itc_desc = "2 Socket SAD 8-6 XOR Interleave (5)", 2371 .itc_imc = &imc_sad_2s_xor, 2372 .itc_pa = 0x12365638, 2373 .itc_pass = B_TRUE, 2374 .itc_nodeid = 0, 2375 .itc_tadid = 0, 2376 .itc_channelid = 0, 2377 .itc_chanaddr = 0x91b2b38, 2378 .itc_dimmid = 0, 2379 .itc_rankid = 0, 2380 .itc_rankaddr = 0x91b2b38 2381 }, { 2382 .itc_desc = "2 Socket SAD 8-6 XOR Interleave (6)", 2383 .itc_imc = &imc_sad_2s_xor, 2384 .itc_pa = 0x12365678, 2385 .itc_pass = B_TRUE, 2386 .itc_nodeid = 1, 2387 .itc_tadid = 0, 2388 .itc_channelid = 0, 2389 .itc_chanaddr = 0x91b2b38, 2390 .itc_dimmid = 0, 2391 .itc_rankid = 0, 2392 .itc_rankaddr = 0x91b2b38 2393 }, { 2394 .itc_desc = "2 Socket SAD 8-6 XOR Interleave (7)", 2395 .itc_imc = &imc_sad_2s_xor, 2396 .itc_pa = 0x12375638, 2397 .itc_pass = B_TRUE, 2398 .itc_nodeid = 1, 2399 .itc_tadid = 0, 2400 .itc_channelid = 0, 2401 .itc_chanaddr = 0x91bab38, 2402 .itc_dimmid = 0, 2403 .itc_rankid = 0, 2404 .itc_rankaddr = 0x91bab38 2405 }, { 2406 .itc_desc = "2 Socket SAD 8-6 XOR Interleave (8)", 2407 .itc_imc = &imc_sad_2s_xor, 2408 .itc_pa = 0x12375678, 2409 .itc_pass = B_TRUE, 2410 .itc_nodeid = 0, 2411 .itc_tadid = 0, 2412 .itc_channelid = 0, 2413 .itc_chanaddr = 0x91bab38, 2414 .itc_dimmid = 0, 2415 .itc_rankid = 0, 2416 .itc_rankaddr = 0x91bab38 2417 }, 2418 /* 2419 * Next, we're going to repeat the same initial set of tests that we had, but 2420 * we're also going to turn on a7 mode. First up is the 2 socket case. 2421 */ 2422 { 2423 .itc_desc = "2 Socket SAD 8-6 A7 Interleave (1)", 2424 .itc_imc = &imc_sad_2s_a7, 2425 .itc_pa = 0x2342000f, 2426 .itc_pass = B_TRUE, 2427 .itc_nodeid = 0, 2428 .itc_tadid = 0, 2429 .itc_channelid = 0, 2430 .itc_chanaddr = 0x11a1000f, 2431 .itc_dimmid = 0, 2432 .itc_rankid = 0, 2433 .itc_rankaddr = 0x11a1000f 2434 }, { 2435 .itc_desc = "2 Socket SAD 8-6 A7 Interleave (2)", 2436 .itc_imc = &imc_sad_2s_a7, 2437 .itc_pa = 0x2342004f, 2438 .itc_pass = B_TRUE, 2439 .itc_nodeid = 0, 2440 .itc_tadid = 0, 2441 .itc_channelid = 0, 2442 .itc_chanaddr = 0x11a1004f, 2443 .itc_dimmid = 0, 2444 .itc_rankid = 0, 2445 .itc_rankaddr = 0x11a1004f 2446 }, { 2447 .itc_desc = "2 Socket SAD 8-6 A7 Interleave (3)", 2448 .itc_imc = &imc_sad_2s_a7, 2449 .itc_pa = 0x2342020f, 2450 .itc_pass = B_TRUE, 2451 .itc_nodeid = 1, 2452 .itc_tadid = 0, 2453 .itc_channelid = 0, 2454 .itc_chanaddr = 0x11a1010f, 2455 .itc_dimmid = 0, 2456 .itc_rankid = 0, 2457 .itc_rankaddr = 0x11a1010f 2458 }, { 2459 .itc_desc = "2 Socket SAD 8-6 A7 Interleave (4)", 2460 .itc_imc = &imc_sad_2s_a7, 2461 .itc_pa = 0x2342024f, 2462 .itc_pass = B_TRUE, 2463 .itc_nodeid = 1, 2464 .itc_tadid = 0, 2465 .itc_channelid = 0, 2466 .itc_chanaddr = 0x11a1014f, 2467 .itc_dimmid = 0, 2468 .itc_rankid = 0, 2469 .itc_rankaddr = 0x11a1014f 2470 }, 2471 /* 2472 * Next, we're going to repeat the same initial set of tests that we had, but 2473 * we're also going to turn on a7 mode. First up is the 4 socket case. 2474 */ 2475 { 2476 .itc_desc = "4 Socket SAD 8-6 A7 (1)", 2477 .itc_imc = &imc_sad_4s_a7, 2478 .itc_pa = 0x2342000f, 2479 .itc_pass = B_TRUE, 2480 .itc_nodeid = 0, 2481 .itc_tadid = 0, 2482 .itc_channelid = 0, 2483 .itc_chanaddr = 0x08d0800f, 2484 .itc_dimmid = 0, 2485 .itc_rankid = 0, 2486 .itc_rankaddr = 0x08d0800f 2487 }, { 2488 .itc_desc = "4 Socket SAD 8-6 A7 (2)", 2489 .itc_imc = &imc_sad_4s_a7, 2490 .itc_pa = 0x2342008f, 2491 .itc_pass = B_TRUE, 2492 .itc_nodeid = 2, 2493 .itc_tadid = 0, 2494 .itc_channelid = 0, 2495 .itc_chanaddr = 0x08d0800f, 2496 .itc_dimmid = 0, 2497 .itc_rankid = 0, 2498 .itc_rankaddr = 0x08d0800f 2499 }, { 2500 .itc_desc = "4 Socket SAD 8-6 A7 (3)", 2501 .itc_imc = &imc_sad_4s_a7, 2502 .itc_pa = 0x2342020f, 2503 .itc_pass = B_TRUE, 2504 .itc_nodeid = 1, 2505 .itc_tadid = 0, 2506 .itc_channelid = 0, 2507 .itc_chanaddr = 0x08d0808f, 2508 .itc_dimmid = 0, 2509 .itc_rankid = 0, 2510 .itc_rankaddr = 0x08d0808f 2511 }, { 2512 .itc_desc = "4 Socket SAD 8-6 A7 (4)", 2513 .itc_imc = &imc_sad_4s_a7, 2514 .itc_pa = 0x2342028f, 2515 .itc_pass = B_TRUE, 2516 .itc_nodeid = 3, 2517 .itc_tadid = 0, 2518 .itc_channelid = 0, 2519 .itc_chanaddr = 0x08d0808f, 2520 .itc_dimmid = 0, 2521 .itc_rankid = 0, 2522 .itc_rankaddr = 0x08d0808f 2523 }, { 2524 .itc_desc = "4 Socket SAD 8-6 A7 (5)", 2525 .itc_imc = &imc_sad_4s_a7, 2526 .itc_pa = 0x23420f8f, 2527 .itc_pass = B_TRUE, 2528 .itc_nodeid = 3, 2529 .itc_tadid = 0, 2530 .itc_channelid = 0, 2531 .itc_chanaddr = 0x08d0838f, 2532 .itc_dimmid = 0, 2533 .itc_rankid = 0, 2534 .itc_rankaddr = 0x08d0838f 2535 }, 2536 /* 2537 * 2 Socket 8-6 XOR mode, with a7 set. Here, we'll end up working through all of 2538 * the XOR permutations to make sure that we're in good shape. 2539 */ 2540 { 2541 .itc_desc = "2 Socket SAD 8-6 XOR A7 (1)", 2542 .itc_imc = &imc_sad_2s_a7_xor, 2543 .itc_pa = 0x4200000b, 2544 .itc_pass = B_TRUE, 2545 .itc_nodeid = 0, 2546 .itc_tadid = 0, 2547 .itc_channelid = 0, 2548 .itc_chanaddr = 0x2100000b, 2549 .itc_dimmid = 0, 2550 .itc_rankid = 0, 2551 .itc_rankaddr = 0x2100000b 2552 }, { 2553 .itc_desc = "2 Socket SAD 8-6 XOR A7 (2)", 2554 .itc_imc = &imc_sad_2s_a7_xor, 2555 .itc_pa = 0x4200020b, 2556 .itc_pass = B_TRUE, 2557 .itc_nodeid = 1, 2558 .itc_tadid = 0, 2559 .itc_channelid = 0, 2560 .itc_chanaddr = 0x2100010b, 2561 .itc_dimmid = 0, 2562 .itc_rankid = 0, 2563 .itc_rankaddr = 0x2100010b 2564 }, { 2565 .itc_desc = "2 Socket SAD 8-6 XOR A7 (3)", 2566 .itc_imc = &imc_sad_2s_a7_xor, 2567 .itc_pa = 0x4201000b, 2568 .itc_pass = B_TRUE, 2569 .itc_nodeid = 1, 2570 .itc_tadid = 0, 2571 .itc_channelid = 0, 2572 .itc_chanaddr = 0x2100800b, 2573 .itc_dimmid = 0, 2574 .itc_rankid = 0, 2575 .itc_rankaddr = 0x2100800b 2576 }, { 2577 .itc_desc = "2 Socket SAD 8-6 XOR A7 (4)", 2578 .itc_imc = &imc_sad_2s_a7_xor, 2579 .itc_pa = 0x4201020b, 2580 .itc_pass = B_TRUE, 2581 .itc_nodeid = 0, 2582 .itc_tadid = 0, 2583 .itc_channelid = 0, 2584 .itc_chanaddr = 0x2100810b, 2585 .itc_dimmid = 0, 2586 .itc_rankid = 0, 2587 .itc_rankaddr = 0x2100810b 2588 }, { 2589 .itc_desc = "2 Socket SAD 8-6 XOR A7 (5)", 2590 .itc_imc = &imc_sad_2s_a7_xor, 2591 .itc_pa = 0x4202000b, 2592 .itc_pass = B_TRUE, 2593 .itc_nodeid = 0, 2594 .itc_tadid = 0, 2595 .itc_channelid = 0, 2596 .itc_chanaddr = 0x2101000b, 2597 .itc_dimmid = 0, 2598 .itc_rankid = 0, 2599 .itc_rankaddr = 0x2101000b 2600 }, { 2601 .itc_desc = "2 Socket SAD 8-6 XOR A7 (6)", 2602 .itc_imc = &imc_sad_2s_a7_xor, 2603 .itc_pa = 0x4202020b, 2604 .itc_pass = B_TRUE, 2605 .itc_nodeid = 1, 2606 .itc_tadid = 0, 2607 .itc_channelid = 0, 2608 .itc_chanaddr = 0x2101010b, 2609 .itc_dimmid = 0, 2610 .itc_rankid = 0, 2611 .itc_rankaddr = 0x2101010b 2612 }, { 2613 .itc_desc = "2 Socket SAD 8-6 XOR A7 (7)", 2614 .itc_imc = &imc_sad_2s_a7_xor, 2615 .itc_pa = 0x4203000b, 2616 .itc_pass = B_TRUE, 2617 .itc_nodeid = 1, 2618 .itc_tadid = 0, 2619 .itc_channelid = 0, 2620 .itc_chanaddr = 0x2101800b, 2621 .itc_dimmid = 0, 2622 .itc_rankid = 0, 2623 .itc_rankaddr = 0x2101800b 2624 }, { 2625 .itc_desc = "2 Socket SAD 8-6 XOR A7 (8)", 2626 .itc_imc = &imc_sad_2s_a7_xor, 2627 .itc_pa = 0x4203020b, 2628 .itc_pass = B_TRUE, 2629 .itc_nodeid = 0, 2630 .itc_tadid = 0, 2631 .itc_channelid = 0, 2632 .itc_chanaddr = 0x2101810b, 2633 .itc_dimmid = 0, 2634 .itc_rankid = 0, 2635 .itc_rankaddr = 0x2101810b 2636 }, 2637 /* 2638 * This is a multi-rule SAD that alternates how we target socket interleaving 2639 * depending on which address range we're at. 2640 */ 2641 { 2642 .itc_desc = "SAD Multi-rule (1)", 2643 .itc_imc = &imc_sad_2s_multirule, 2644 .itc_pa = 0x0ff60003, 2645 .itc_pass = B_TRUE, 2646 .itc_nodeid = 0, 2647 .itc_tadid = 0, 2648 .itc_channelid = 0, 2649 .itc_chanaddr = 0x07fb0003, 2650 .itc_dimmid = 0, 2651 .itc_rankid = 0, 2652 .itc_rankaddr = 0x07fb0003 2653 }, { 2654 .itc_desc = "SAD Multi-rule (2)", 2655 .itc_imc = &imc_sad_2s_multirule, 2656 .itc_pa = 0x0ff60043, 2657 .itc_pass = B_TRUE, 2658 .itc_nodeid = 1, 2659 .itc_tadid = 0, 2660 .itc_channelid = 0, 2661 .itc_chanaddr = 0x07fb0003, 2662 .itc_dimmid = 0, 2663 .itc_rankid = 0, 2664 .itc_rankaddr = 0x07fb0003 2665 }, { 2666 .itc_desc = "SAD Multi-rule (3)", 2667 .itc_imc = &imc_sad_2s_multirule, 2668 .itc_pa = 0x1ff60003, 2669 .itc_pass = B_TRUE, 2670 .itc_nodeid = 0, 2671 .itc_tadid = 0, 2672 .itc_channelid = 0, 2673 .itc_chanaddr = 0x0ffb0003, 2674 .itc_dimmid = 0, 2675 .itc_rankid = 0, 2676 .itc_rankaddr = 0x0ffb0003 2677 }, { 2678 .itc_desc = "SAD Multi-rule (4)", 2679 .itc_imc = &imc_sad_2s_multirule, 2680 .itc_pa = 0x1ff60043, 2681 .itc_pass = B_TRUE, 2682 .itc_nodeid = 1, 2683 .itc_tadid = 0, 2684 .itc_channelid = 0, 2685 .itc_chanaddr = 0x0ffb0003, 2686 .itc_dimmid = 0, 2687 .itc_rankid = 0, 2688 .itc_rankaddr = 0x0ffb0003 2689 }, { 2690 .itc_desc = "SAD Multi-rule (5)", 2691 .itc_imc = &imc_sad_2s_multirule, 2692 .itc_pa = 0x2ff60003, 2693 .itc_pass = B_TRUE, 2694 .itc_nodeid = 1, 2695 .itc_tadid = 0, 2696 .itc_channelid = 0, 2697 .itc_chanaddr = 0x1ff60003, 2698 .itc_dimmid = 0, 2699 .itc_rankid = 0, 2700 .itc_rankaddr = 0x1ff60003 2701 }, 2702 { 2703 .itc_desc = "SAD Multi-rule (6)", 2704 .itc_imc = &imc_sad_2s_multirule, 2705 .itc_pa = 0x2ff60043, 2706 .itc_pass = B_TRUE, 2707 .itc_nodeid = 1, 2708 .itc_tadid = 0, 2709 .itc_channelid = 0, 2710 .itc_chanaddr = 0x1ff60043, 2711 .itc_dimmid = 0, 2712 .itc_rankid = 0, 2713 .itc_rankaddr = 0x1ff60043 2714 }, { 2715 .itc_desc = "SAD Multi-rule (7)", 2716 .itc_imc = &imc_sad_2s_multirule, 2717 .itc_pa = 0x3ff60003, 2718 .itc_pass = B_TRUE, 2719 .itc_nodeid = 1, 2720 .itc_tadid = 0, 2721 .itc_channelid = 0, 2722 .itc_chanaddr = 0x2ff60003, 2723 .itc_dimmid = 0, 2724 .itc_rankid = 0, 2725 .itc_rankaddr = 0x2ff60003 2726 }, { 2727 .itc_desc = "SAD Multi-rule (8)", 2728 .itc_imc = &imc_sad_2s_multirule, 2729 .itc_pa = 0x3ff60043, 2730 .itc_pass = B_TRUE, 2731 .itc_nodeid = 1, 2732 .itc_tadid = 0, 2733 .itc_channelid = 0, 2734 .itc_chanaddr = 0x2ff60043, 2735 .itc_dimmid = 0, 2736 .itc_rankid = 0, 2737 .itc_rankaddr = 0x2ff60043 2738 }, { 2739 .itc_desc = "SAD Multi-rule (9)", 2740 .itc_imc = &imc_sad_2s_multirule, 2741 .itc_pa = 0x4ff60003, 2742 .itc_pass = B_TRUE, 2743 .itc_nodeid = 0, 2744 .itc_tadid = 0, 2745 .itc_channelid = 0, 2746 .itc_chanaddr = 0x1ff60003, 2747 .itc_dimmid = 0, 2748 .itc_rankid = 0, 2749 .itc_rankaddr = 0x1ff60003 2750 }, { 2751 .itc_desc = "SAD Multi-rule (10)", 2752 .itc_imc = &imc_sad_2s_multirule, 2753 .itc_pa = 0x4ff60043, 2754 .itc_pass = B_TRUE, 2755 .itc_nodeid = 0, 2756 .itc_tadid = 0, 2757 .itc_channelid = 0, 2758 .itc_chanaddr = 0x1ff60043, 2759 .itc_dimmid = 0, 2760 .itc_rankid = 0, 2761 .itc_rankaddr = 0x1ff60043 2762 }, { 2763 .itc_desc = "SAD Multi-rule (11)", 2764 .itc_imc = &imc_sad_2s_multirule, 2765 .itc_pa = 0x5ff60003, 2766 .itc_pass = B_TRUE, 2767 .itc_nodeid = 0, 2768 .itc_tadid = 0, 2769 .itc_channelid = 0, 2770 .itc_chanaddr = 0x2ff60003, 2771 .itc_dimmid = 0, 2772 .itc_rankid = 0, 2773 .itc_rankaddr = 0x2ff60003 2774 }, { 2775 .itc_desc = "SAD Multi-rule (12)", 2776 .itc_imc = &imc_sad_2s_multirule, 2777 .itc_pa = 0x5ff60043, 2778 .itc_pass = B_TRUE, 2779 .itc_nodeid = 0, 2780 .itc_tadid = 0, 2781 .itc_channelid = 0, 2782 .itc_chanaddr = 0x2ff60043, 2783 .itc_dimmid = 0, 2784 .itc_rankid = 0, 2785 .itc_rankaddr = 0x2ff60043 2786 }, { 2787 .itc_desc = "SAD Multi-rule (13)", 2788 .itc_imc = &imc_sad_2s_multirule, 2789 .itc_pa = 0x6ff60003, 2790 .itc_pass = B_TRUE, 2791 .itc_nodeid = 1, 2792 .itc_tadid = 0, 2793 .itc_channelid = 0, 2794 .itc_chanaddr = 0x37fb0003, 2795 .itc_dimmid = 0, 2796 .itc_rankid = 0, 2797 .itc_rankaddr = 0x37fb0003 2798 }, { 2799 .itc_desc = "SAD Multi-rule (14)", 2800 .itc_imc = &imc_sad_2s_multirule, 2801 .itc_pa = 0x6ff60043, 2802 .itc_pass = B_TRUE, 2803 .itc_nodeid = 0, 2804 .itc_tadid = 0, 2805 .itc_channelid = 0, 2806 .itc_chanaddr = 0x37fb0003, 2807 .itc_dimmid = 0, 2808 .itc_rankid = 0, 2809 .itc_rankaddr = 0x37fb0003 2810 }, { 2811 .itc_desc = "SAD Multi-rule (15)", 2812 .itc_imc = &imc_sad_2s_multirule, 2813 .itc_pa = 0x7ff60003, 2814 .itc_pass = B_TRUE, 2815 .itc_nodeid = 1, 2816 .itc_tadid = 0, 2817 .itc_channelid = 0, 2818 .itc_chanaddr = 0x3ffb0003, 2819 .itc_dimmid = 0, 2820 .itc_rankid = 0, 2821 .itc_rankaddr = 0x3ffb0003 2822 }, { 2823 .itc_desc = "SAD Multi-rule (16)", 2824 .itc_imc = &imc_sad_2s_multirule, 2825 .itc_pa = 0x7ff60043, 2826 .itc_pass = B_TRUE, 2827 .itc_nodeid = 0, 2828 .itc_tadid = 0, 2829 .itc_channelid = 0, 2830 .itc_chanaddr = 0x3ffb0003, 2831 .itc_dimmid = 0, 2832 .itc_rankid = 0, 2833 .itc_rankaddr = 0x3ffb0003 2834 }, 2835 /* 2836 * Verify that SAD interleaving at 10-8 works. 2837 */ 2838 { 2839 .itc_desc = "SAD 2s SKX 10-8 (1)", 2840 .itc_imc = &imc_sad_2s_skx_10t8, 2841 .itc_pa = 0x11220000, 2842 .itc_pass = B_TRUE, 2843 .itc_nodeid = 0, 2844 .itc_tadid = 0, 2845 .itc_channelid = 0, 2846 .itc_chanaddr = 0x08910000, 2847 .itc_dimmid = 0, 2848 .itc_rankid = 0, 2849 .itc_rankaddr = 0x08910000 2850 }, { 2851 .itc_desc = "SAD 2s SKX 10-8 (2)", 2852 .itc_imc = &imc_sad_2s_skx_10t8, 2853 .itc_pa = 0x11220100, 2854 .itc_pass = B_TRUE, 2855 .itc_nodeid = 1, 2856 .itc_tadid = 0, 2857 .itc_channelid = 0, 2858 .itc_chanaddr = 0x08910000, 2859 .itc_dimmid = 0, 2860 .itc_rankid = 0, 2861 .itc_rankaddr = 0x08910000 2862 }, { 2863 .itc_desc = "SAD 2s SKX 10-8 (3)", 2864 .itc_imc = &imc_sad_2s_skx_10t8, 2865 .itc_pa = 0x112200ff, 2866 .itc_pass = B_TRUE, 2867 .itc_nodeid = 0, 2868 .itc_tadid = 0, 2869 .itc_channelid = 0, 2870 .itc_chanaddr = 0x089100ff, 2871 .itc_dimmid = 0, 2872 .itc_rankid = 0, 2873 .itc_rankaddr = 0x089100ff 2874 }, { 2875 .itc_desc = "SAD 2s SKX 10-8 (4)", 2876 .itc_imc = &imc_sad_2s_skx_10t8, 2877 .itc_pa = 0x112201ff, 2878 .itc_pass = B_TRUE, 2879 .itc_nodeid = 1, 2880 .itc_tadid = 0, 2881 .itc_channelid = 0, 2882 .itc_chanaddr = 0x089100ff, 2883 .itc_dimmid = 0, 2884 .itc_rankid = 0, 2885 .itc_rankaddr = 0x089100ff 2886 }, { 2887 .itc_desc = "SAD 2s SKX 10-8 (5)", 2888 .itc_imc = &imc_sad_2s_skx_10t8, 2889 .itc_pa = 0x7ffffeff, 2890 .itc_pass = B_TRUE, 2891 .itc_nodeid = 0, 2892 .itc_tadid = 0, 2893 .itc_channelid = 0, 2894 .itc_chanaddr = 0x3fffffff, 2895 .itc_dimmid = 0, 2896 .itc_rankid = 0, 2897 .itc_rankaddr = 0x3fffffff 2898 }, { 2899 .itc_desc = "SAD 2s SKX 10-8 (6)", 2900 .itc_imc = &imc_sad_2s_skx_10t8, 2901 .itc_pa = 0x7fffffff, 2902 .itc_pass = B_TRUE, 2903 .itc_nodeid = 1, 2904 .itc_tadid = 0, 2905 .itc_channelid = 0, 2906 .itc_chanaddr = 0x3fffffff, 2907 .itc_dimmid = 0, 2908 .itc_rankid = 0, 2909 .itc_rankaddr = 0x3fffffff 2910 }, 2911 /* 2912 * Again with SKX; however, now with 15-12. 2913 */ 2914 { 2915 .itc_desc = "SAD 2s SKX 14-12 (1)", 2916 .itc_imc = &imc_sad_1s_skx_14t12, 2917 .itc_pa = 0x11220000, 2918 .itc_pass = B_TRUE, 2919 .itc_nodeid = 0, 2920 .itc_tadid = 0, 2921 .itc_channelid = 0, 2922 .itc_chanaddr = 0x08910000, 2923 .itc_dimmid = 0, 2924 .itc_rankid = 0, 2925 .itc_rankaddr = 0x08910000 2926 }, { 2927 .itc_desc = "SAD 2s SKX 14-12 (2)", 2928 .itc_imc = &imc_sad_1s_skx_14t12, 2929 .itc_pa = 0x11220100, 2930 .itc_pass = B_TRUE, 2931 .itc_nodeid = 0, 2932 .itc_tadid = 0, 2933 .itc_channelid = 0, 2934 .itc_chanaddr = 0x08910100, 2935 .itc_dimmid = 0, 2936 .itc_rankid = 0, 2937 .itc_rankaddr = 0x08910100 2938 }, { 2939 .itc_desc = "SAD 2s SKX 14-12 (3)", 2940 .itc_imc = &imc_sad_1s_skx_14t12, 2941 .itc_pa = 0x112200ff, 2942 .itc_pass = B_TRUE, 2943 .itc_nodeid = 0, 2944 .itc_tadid = 0, 2945 .itc_channelid = 0, 2946 .itc_chanaddr = 0x089100ff, 2947 .itc_dimmid = 0, 2948 .itc_rankid = 0, 2949 .itc_rankaddr = 0x089100ff 2950 }, { 2951 .itc_desc = "SAD 2s SKX 14-12 (4)", 2952 .itc_imc = &imc_sad_1s_skx_14t12, 2953 .itc_pa = 0x112201ff, 2954 .itc_pass = B_TRUE, 2955 .itc_nodeid = 0, 2956 .itc_tadid = 0, 2957 .itc_channelid = 0, 2958 .itc_chanaddr = 0x089101ff, 2959 .itc_dimmid = 0, 2960 .itc_rankid = 0, 2961 .itc_rankaddr = 0x089101ff 2962 }, { 2963 .itc_desc = "SAD 2s SKX 14-12 (5)", 2964 .itc_imc = &imc_sad_1s_skx_14t12, 2965 .itc_pa = 0x11221000, 2966 .itc_pass = B_TRUE, 2967 .itc_nodeid = 0, 2968 .itc_tadid = 1, 2969 .itc_channelid = 0, 2970 .itc_chanaddr = 0x08910000, 2971 .itc_dimmid = 0, 2972 .itc_rankid = 0, 2973 .itc_rankaddr = 0x08910000 2974 }, { 2975 .itc_desc = "SAD 2s SKX 14-12 (6)", 2976 .itc_imc = &imc_sad_1s_skx_14t12, 2977 .itc_pa = 0x11221100, 2978 .itc_pass = B_TRUE, 2979 .itc_nodeid = 0, 2980 .itc_tadid = 1, 2981 .itc_channelid = 0, 2982 .itc_chanaddr = 0x08910100, 2983 .itc_dimmid = 0, 2984 .itc_rankid = 0, 2985 .itc_rankaddr = 0x08910100 2986 }, { 2987 .itc_desc = "SAD 2s SKX 14-12 (7)", 2988 .itc_imc = &imc_sad_1s_skx_14t12, 2989 .itc_pa = 0x112210ff, 2990 .itc_pass = B_TRUE, 2991 .itc_nodeid = 0, 2992 .itc_tadid = 1, 2993 .itc_channelid = 0, 2994 .itc_chanaddr = 0x089100ff, 2995 .itc_dimmid = 0, 2996 .itc_rankid = 0, 2997 .itc_rankaddr = 0x089100ff 2998 }, { 2999 .itc_desc = "SAD 2s SKX 14-12 (8)", 3000 .itc_imc = &imc_sad_1s_skx_14t12, 3001 .itc_pa = 0x112211ff, 3002 .itc_pass = B_TRUE, 3003 .itc_nodeid = 0, 3004 .itc_tadid = 1, 3005 .itc_channelid = 0, 3006 .itc_chanaddr = 0x089101ff, 3007 .itc_dimmid = 0, 3008 .itc_rankid = 0, 3009 .itc_rankaddr = 0x089101ff 3010 }, 3011 /* 3012 * This set covers using an 8-way socket granularity on Skylake. This means that 3013 * we have two IMCs per socket as well. We're also using 1 GiB granularity here. 3014 * So we want to verify that is working as well. 3015 */ 3016 { 3017 .itc_desc = "SAD 4s 8-way SKX 32-30 (1)", 3018 .itc_imc = &imc_sad_4s_8w_skx_32t30, 3019 .itc_pa = 0x0badcafe, 3020 .itc_pass = B_TRUE, 3021 .itc_nodeid = 0, 3022 .itc_tadid = 0, 3023 .itc_channelid = 0, 3024 .itc_chanaddr = 0x0badcafe, 3025 .itc_dimmid = 0, 3026 .itc_rankid = 0, 3027 .itc_rankaddr = 0x0badcafe 3028 }, { 3029 .itc_desc = "SAD 4s 8-way SKX 32-30 (2)", 3030 .itc_imc = &imc_sad_4s_8w_skx_32t30, 3031 .itc_pa = 0x4badcafe, 3032 .itc_pass = B_TRUE, 3033 .itc_nodeid = 0, 3034 .itc_tadid = 1, 3035 .itc_channelid = 0, 3036 .itc_chanaddr = 0x0badcafe, 3037 .itc_dimmid = 0, 3038 .itc_rankid = 0, 3039 .itc_rankaddr = 0x0badcafe 3040 }, { 3041 .itc_desc = "SAD 4s 8-way SKX 32-30 (3)", 3042 .itc_imc = &imc_sad_4s_8w_skx_32t30, 3043 .itc_pa = 0x10badcafeULL, 3044 .itc_pass = B_TRUE, 3045 .itc_nodeid = 1, 3046 .itc_tadid = 0, 3047 .itc_channelid = 0, 3048 .itc_chanaddr = 0x0badcafe, 3049 .itc_dimmid = 0, 3050 .itc_rankid = 0, 3051 .itc_rankaddr = 0x0badcafe 3052 }, { 3053 .itc_desc = "SAD 4s 8-way SKX 32-30 (4)", 3054 .itc_imc = &imc_sad_4s_8w_skx_32t30, 3055 .itc_pa = 0x14badcafeULL, 3056 .itc_pass = B_TRUE, 3057 .itc_nodeid = 1, 3058 .itc_tadid = 1, 3059 .itc_channelid = 0, 3060 .itc_chanaddr = 0x0badcafe, 3061 .itc_dimmid = 0, 3062 .itc_rankid = 0, 3063 .itc_rankaddr = 0x0badcafe 3064 }, { 3065 .itc_desc = "SAD 4s 8-way SKX 32-30 (5)", 3066 .itc_imc = &imc_sad_4s_8w_skx_32t30, 3067 .itc_pa = 0x18badcafeULL, 3068 .itc_pass = B_TRUE, 3069 .itc_nodeid = 2, 3070 .itc_tadid = 0, 3071 .itc_channelid = 0, 3072 .itc_chanaddr = 0x0badcafe, 3073 .itc_dimmid = 0, 3074 .itc_rankid = 0, 3075 .itc_rankaddr = 0x0badcafe 3076 }, { 3077 .itc_desc = "SAD 4s 8-way SKX 32-30 (6)", 3078 .itc_imc = &imc_sad_4s_8w_skx_32t30, 3079 .itc_pa = 0x1cbadcafeULL, 3080 .itc_pass = B_TRUE, 3081 .itc_nodeid = 2, 3082 .itc_tadid = 1, 3083 .itc_channelid = 0, 3084 .itc_chanaddr = 0x0badcafe, 3085 .itc_dimmid = 0, 3086 .itc_rankid = 0, 3087 .itc_rankaddr = 0x0badcafe 3088 }, { 3089 .itc_desc = "SAD 4s 8-way SKX 32-30 (7)", 3090 .itc_imc = &imc_sad_4s_8w_skx_32t30, 3091 .itc_pa = 0x20badcafeULL, 3092 .itc_pass = B_TRUE, 3093 .itc_nodeid = 3, 3094 .itc_tadid = 0, 3095 .itc_channelid = 0, 3096 .itc_chanaddr = 0x0badcafe, 3097 .itc_dimmid = 0, 3098 .itc_rankid = 0, 3099 .itc_rankaddr = 0x0badcafe 3100 }, { 3101 .itc_desc = "SAD 4s 8-way SKX 32-30 (8)", 3102 .itc_imc = &imc_sad_4s_8w_skx_32t30, 3103 .itc_pa = 0x24badcafeULL, 3104 .itc_pass = B_TRUE, 3105 .itc_nodeid = 3, 3106 .itc_tadid = 1, 3107 .itc_channelid = 0, 3108 .itc_chanaddr = 0x0badcafe, 3109 .itc_dimmid = 0, 3110 .itc_rankid = 0, 3111 .itc_rankaddr = 0x0badcafe 3112 }, 3113 3114 { 3115 .itc_desc = "SAD 4s 8-way SKX 32-30 (9)", 3116 .itc_imc = &imc_sad_4s_8w_skx_32t30, 3117 .itc_pa = 0x0badca77, 3118 .itc_pass = B_TRUE, 3119 .itc_nodeid = 0, 3120 .itc_tadid = 0, 3121 .itc_channelid = 0, 3122 .itc_chanaddr = 0x0badca77, 3123 .itc_dimmid = 0, 3124 .itc_rankid = 0, 3125 .itc_rankaddr = 0x0badca77 3126 }, { 3127 .itc_desc = "SAD 4s 8-way SKX 32-30 (10)", 3128 .itc_imc = &imc_sad_4s_8w_skx_32t30, 3129 .itc_pa = 0x4badca77, 3130 .itc_pass = B_TRUE, 3131 .itc_nodeid = 0, 3132 .itc_tadid = 1, 3133 .itc_channelid = 0, 3134 .itc_chanaddr = 0x0badca77, 3135 .itc_dimmid = 0, 3136 .itc_rankid = 0, 3137 .itc_rankaddr = 0x0badca77 3138 }, { 3139 .itc_desc = "SAD 4s 8-way SKX 32-30 (11)", 3140 .itc_imc = &imc_sad_4s_8w_skx_32t30, 3141 .itc_pa = 0x10badca77ULL, 3142 .itc_pass = B_TRUE, 3143 .itc_nodeid = 1, 3144 .itc_tadid = 0, 3145 .itc_channelid = 0, 3146 .itc_chanaddr = 0x0badca77, 3147 .itc_dimmid = 0, 3148 .itc_rankid = 0, 3149 .itc_rankaddr = 0x0badca77 3150 }, { 3151 .itc_desc = "SAD 4s 8-way SKX 32-30 (12)", 3152 .itc_imc = &imc_sad_4s_8w_skx_32t30, 3153 .itc_pa = 0x14badca77ULL, 3154 .itc_pass = B_TRUE, 3155 .itc_nodeid = 1, 3156 .itc_tadid = 1, 3157 .itc_channelid = 0, 3158 .itc_chanaddr = 0x0badca77, 3159 .itc_dimmid = 0, 3160 .itc_rankid = 0, 3161 .itc_rankaddr = 0x0badca77 3162 }, { 3163 .itc_desc = "SAD 4s 8-way SKX 32-30 (13)", 3164 .itc_imc = &imc_sad_4s_8w_skx_32t30, 3165 .itc_pa = 0x18badca77ULL, 3166 .itc_pass = B_TRUE, 3167 .itc_nodeid = 2, 3168 .itc_tadid = 0, 3169 .itc_channelid = 0, 3170 .itc_chanaddr = 0x0badca77, 3171 .itc_dimmid = 0, 3172 .itc_rankid = 0, 3173 .itc_rankaddr = 0x0badca77 3174 }, { 3175 .itc_desc = "SAD 4s 8-way SKX 32-30 (14)", 3176 .itc_imc = &imc_sad_4s_8w_skx_32t30, 3177 .itc_pa = 0x1cbadca77ULL, 3178 .itc_pass = B_TRUE, 3179 .itc_nodeid = 2, 3180 .itc_tadid = 1, 3181 .itc_channelid = 0, 3182 .itc_chanaddr = 0x0badca77, 3183 .itc_dimmid = 0, 3184 .itc_rankid = 0, 3185 .itc_rankaddr = 0x0badca77 3186 }, { 3187 .itc_desc = "SAD 4s 8-way SKX 32-30 (15)", 3188 .itc_imc = &imc_sad_4s_8w_skx_32t30, 3189 .itc_pa = 0x20badca77ULL, 3190 .itc_pass = B_TRUE, 3191 .itc_nodeid = 3, 3192 .itc_tadid = 0, 3193 .itc_channelid = 0, 3194 .itc_chanaddr = 0x0badca77, 3195 .itc_dimmid = 0, 3196 .itc_rankid = 0, 3197 .itc_rankaddr = 0x0badca77 3198 }, { 3199 .itc_desc = "SAD 4s 8-way SKX 32-30 (16)", 3200 .itc_imc = &imc_sad_4s_8w_skx_32t30, 3201 .itc_pa = 0x24badca77ULL, 3202 .itc_pass = B_TRUE, 3203 .itc_nodeid = 3, 3204 .itc_tadid = 1, 3205 .itc_channelid = 0, 3206 .itc_chanaddr = 0x0badca77, 3207 .itc_dimmid = 0, 3208 .itc_rankid = 0, 3209 .itc_rankaddr = 0x0badca77 3210 }, { 3211 .itc_desc = NULL 3212 } }; 3213