1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2019 Joyent, Inc. 14 */ 15 16 #include "imc_test.h" 17 18 /* 19 * Test various aspects of RIR decoding and rank interleaving. 20 * 21 * The first test series uses imc_rir_8w_4r_closed which basically tests our 22 * rank interleaving across a single DIMM/channel in a closed page 23 * configuration. Technically such a configuration has aliasing, so it 24 * shouldn't be used in the wild. This is to validate that we're doing 25 * interleaving with a single rule across closed pages. 26 * 27 * The second test set, imc_rir_4w_4r_open is similar; however, it uses open 28 * pages instead. 29 * 30 * The third test set, imc_rir_8w_4r_2dpc, is used to make sure that we can 31 * properly perform interleaving across two DIMMs in a single channel 32 * configuration. 33 * 34 * The fourth test set, imc_rir_2w_1r_3dpc, is used to make sure that we can use 35 * multiple rank interleaving rules to point us to different parts of a DIMM on 36 * a single channel. 37 */ 38 39 static const imc_t imc_rir_8w_4r_closed = { 40 .imc_gen = IMC_GEN_SANDY, 41 .imc_nsockets = 1, 42 .imc_sockets[0] = { 43 .isock_valid = IMC_SOCKET_V_VALID, 44 .isock_sad = { 45 .isad_flags = 0, 46 .isad_valid = IMC_SAD_V_VALID, 47 .isad_tolm = 0x80000000, 48 .isad_tohm = 0, 49 .isad_nrules = 10, 50 .isad_rules[0] = { 51 .isr_enable = B_TRUE, 52 .isr_limit = 0x80000000, 53 .isr_imode = IMC_SAD_IMODE_8t6, 54 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 55 .isr_targets = { 0, 0, 0, 0, 0, 0, 0, 0 } 56 } 57 }, 58 .isock_ntad = 1, 59 .isock_tad[0] = { 60 .itad_flags = 0, 61 .itad_nrules = 12, 62 .itad_rules[0] = { 63 .itr_base = 0x0, 64 .itr_limit = 0x80000000, 65 .itr_sock_way = 1, 66 .itr_chan_way = 1, 67 .itr_sock_gran = IMC_TAD_GRAN_64B, 68 .itr_chan_gran = IMC_TAD_GRAN_64B, 69 .itr_ntargets = 4, 70 .itr_targets = { 0, 0, 0, 0 } 71 } 72 }, 73 .isock_nimc = 1, 74 .isock_imcs[0] = { 75 .icn_nchannels = 1, 76 .icn_dimm_type = IMC_DIMM_DDR3, 77 .icn_ecc = B_TRUE, 78 .icn_lockstep = B_FALSE, 79 .icn_closed = B_TRUE, 80 .icn_channels[0] = { 81 .ich_ndimms = 1, 82 .ich_dimms[0] = { 83 .idimm_present = B_TRUE, 84 .idimm_nbanks = 3, 85 .idimm_width = 8, 86 .idimm_density = 2, 87 .idimm_nranks = 4, 88 .idimm_nrows = 14, 89 .idimm_ncolumns = 10, 90 .idimm_size = 0x80000000 91 }, 92 .ich_ntad_offsets = 12, 93 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 94 0, 0 }, 95 .ich_nrankileaves = 8, 96 .ich_rankileaves[0] = { 97 .irle_enabled = B_TRUE, 98 .irle_nways = 8, 99 .irle_nwaysbits = 3, 100 .irle_limit = 0x80000000, 101 .irle_nentries = 8, 102 .irle_entries[0] = { 0x3, 0x0 }, 103 .irle_entries[1] = { 0x2, 0x0 }, 104 .irle_entries[2] = { 0x1, 0x0 }, 105 .irle_entries[3] = { 0x0, 0x0 }, 106 .irle_entries[4] = { 0x2, 0x0 }, 107 .irle_entries[5] = { 0x3, 0x0 }, 108 .irle_entries[6] = { 0x0, 0x0 }, 109 .irle_entries[7] = { 0x1, 0x0 } 110 } 111 } 112 } 113 } 114 }; 115 116 static const imc_t imc_rir_4w_4r_open = { 117 .imc_gen = IMC_GEN_SANDY, 118 .imc_nsockets = 1, 119 .imc_sockets[0] = { 120 .isock_valid = IMC_SOCKET_V_VALID, 121 .isock_sad = { 122 .isad_flags = 0, 123 .isad_valid = IMC_SAD_V_VALID, 124 .isad_tolm = 0x80000000, 125 .isad_tohm = 0, 126 .isad_nrules = 10, 127 .isad_rules[0] = { 128 .isr_enable = B_TRUE, 129 .isr_limit = 0x80000000, 130 .isr_imode = IMC_SAD_IMODE_8t6, 131 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 132 .isr_targets = { 0, 0, 0, 0, 0, 0, 0, 0 } 133 } 134 }, 135 .isock_ntad = 1, 136 .isock_tad[0] = { 137 .itad_flags = 0, 138 .itad_nrules = 12, 139 .itad_rules[0] = { 140 .itr_base = 0x0, 141 .itr_limit = 0x80000000, 142 .itr_sock_way = 1, 143 .itr_chan_way = 1, 144 .itr_sock_gran = IMC_TAD_GRAN_64B, 145 .itr_chan_gran = IMC_TAD_GRAN_64B, 146 .itr_ntargets = 4, 147 .itr_targets = { 0, 0, 0, 0 } 148 } 149 }, 150 .isock_nimc = 1, 151 .isock_imcs[0] = { 152 .icn_nchannels = 1, 153 .icn_dimm_type = IMC_DIMM_DDR3, 154 .icn_ecc = B_TRUE, 155 .icn_lockstep = B_FALSE, 156 .icn_closed = B_FALSE, 157 .icn_channels[0] = { 158 .ich_ndimms = 1, 159 .ich_dimms[0] = { 160 .idimm_present = B_TRUE, 161 .idimm_nbanks = 3, 162 .idimm_width = 8, 163 .idimm_density = 2, 164 .idimm_nranks = 8, 165 .idimm_nrows = 14, 166 .idimm_ncolumns = 10, 167 .idimm_size = 0x80000000 168 }, 169 .ich_ntad_offsets = 12, 170 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 171 0, 0 }, 172 .ich_nrankileaves = 8, 173 .ich_rankileaves[0] = { 174 .irle_enabled = B_TRUE, 175 .irle_nways = 4, 176 .irle_nwaysbits = 2, 177 .irle_limit = 0x80000000, 178 .irle_nentries = 8, 179 .irle_entries[0] = { 0x2, 0x0 }, 180 .irle_entries[1] = { 0x0, 0x0 }, 181 .irle_entries[2] = { 0x3, 0x0 }, 182 .irle_entries[3] = { 0x1, 0x0 }, 183 } 184 } 185 } 186 } 187 }; 188 189 static const imc_t imc_rir_8w_4r_2dpc = { 190 .imc_gen = IMC_GEN_SANDY, 191 .imc_nsockets = 1, 192 .imc_sockets[0] = { 193 .isock_valid = IMC_SOCKET_V_VALID, 194 .isock_sad = { 195 .isad_flags = 0, 196 .isad_valid = IMC_SAD_V_VALID, 197 .isad_tolm = 0x100000000ULL, 198 .isad_tohm = 0, 199 .isad_nrules = 10, 200 .isad_rules[0] = { 201 .isr_enable = B_TRUE, 202 .isr_limit = 0x100000000ULL, 203 .isr_imode = IMC_SAD_IMODE_8t6, 204 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 205 .isr_targets = { 0, 0, 0, 0, 0, 0, 0, 0 } 206 } 207 }, 208 .isock_ntad = 1, 209 .isock_tad[0] = { 210 .itad_flags = 0, 211 .itad_nrules = 12, 212 .itad_rules[0] = { 213 .itr_base = 0x0, 214 .itr_limit = 0x100000000ULL, 215 .itr_sock_way = 1, 216 .itr_chan_way = 1, 217 .itr_sock_gran = IMC_TAD_GRAN_64B, 218 .itr_chan_gran = IMC_TAD_GRAN_64B, 219 .itr_ntargets = 4, 220 .itr_targets = { 0, 0, 0, 0 } 221 } 222 }, 223 .isock_nimc = 1, 224 .isock_imcs[0] = { 225 .icn_nchannels = 1, 226 .icn_dimm_type = IMC_DIMM_DDR3, 227 .icn_ecc = B_TRUE, 228 .icn_lockstep = B_FALSE, 229 .icn_closed = B_TRUE, 230 .icn_channels[0] = { 231 .ich_ndimms = 2, 232 .ich_dimms[0] = { 233 .idimm_present = B_TRUE, 234 .idimm_nbanks = 3, 235 .idimm_width = 8, 236 .idimm_density = 2, 237 .idimm_nranks = 4, 238 .idimm_nrows = 14, 239 .idimm_ncolumns = 10, 240 .idimm_size = 0x80000000 241 }, 242 .ich_dimms[1] = { 243 .idimm_present = B_TRUE, 244 .idimm_nbanks = 3, 245 .idimm_width = 8, 246 .idimm_density = 2, 247 .idimm_nranks = 4, 248 .idimm_nrows = 14, 249 .idimm_ncolumns = 10, 250 .idimm_size = 0x80000000 251 }, 252 .ich_ntad_offsets = 12, 253 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 254 0, 0 }, 255 .ich_nrankileaves = 8, 256 .ich_rankileaves[0] = { 257 .irle_enabled = B_TRUE, 258 .irle_nways = 8, 259 .irle_nwaysbits = 3, 260 .irle_limit = 0x100000000ULL, 261 .irle_nentries = 8, 262 .irle_entries[0] = { 0x0, 0x0 }, 263 .irle_entries[1] = { 0x4, 0x0 }, 264 .irle_entries[2] = { 0x1, 0x0 }, 265 .irle_entries[3] = { 0x5, 0x0 }, 266 .irle_entries[4] = { 0x2, 0x0 }, 267 .irle_entries[5] = { 0x6, 0x0 }, 268 .irle_entries[6] = { 0x3, 0x0 }, 269 .irle_entries[7] = { 0x7, 0x0 } 270 } 271 } 272 } 273 } 274 }; 275 276 static const imc_t imc_rir_2w_1r_3dpc = { 277 .imc_gen = IMC_GEN_HASWELL, 278 .imc_nsockets = 1, 279 .imc_sockets[0] = { 280 .isock_valid = IMC_SOCKET_V_VALID, 281 .isock_sad = { 282 .isad_flags = 0, 283 .isad_valid = IMC_SAD_V_VALID, 284 .isad_tolm = 0x180000000ULL, 285 .isad_tohm = 0, 286 .isad_nrules = 10, 287 .isad_rules[0] = { 288 .isr_enable = B_TRUE, 289 .isr_limit = 0x180000000ULL, 290 .isr_imode = IMC_SAD_IMODE_8t6, 291 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 292 .isr_targets = { 0, 0, 0, 0, 0, 0, 0, 0 } 293 } 294 }, 295 .isock_ntad = 1, 296 .isock_tad[0] = { 297 .itad_flags = 0, 298 .itad_nrules = 12, 299 .itad_rules[0] = { 300 .itr_base = 0x0, 301 .itr_limit = 0x180000000ULL, 302 .itr_sock_way = 1, 303 .itr_chan_way = 1, 304 .itr_sock_gran = IMC_TAD_GRAN_64B, 305 .itr_chan_gran = IMC_TAD_GRAN_64B, 306 .itr_ntargets = 4, 307 .itr_targets = { 0, 0, 0, 0 } 308 } 309 }, 310 .isock_nimc = 1, 311 .isock_imcs[0] = { 312 .icn_nchannels = 1, 313 .icn_dimm_type = IMC_DIMM_DDR3, 314 .icn_ecc = B_TRUE, 315 .icn_lockstep = B_FALSE, 316 .icn_closed = B_TRUE, 317 .icn_channels[0] = { 318 .ich_ndimms = 3, 319 .ich_dimms[0] = { 320 .idimm_present = B_TRUE, 321 .idimm_nbanks = 3, 322 .idimm_width = 8, 323 .idimm_density = 2, 324 .idimm_nranks = 1, 325 .idimm_nrows = 14, 326 .idimm_ncolumns = 10, 327 .idimm_size = 0x80000000 328 }, 329 .ich_dimms[1] = { 330 .idimm_present = B_TRUE, 331 .idimm_nbanks = 3, 332 .idimm_width = 8, 333 .idimm_density = 2, 334 .idimm_nranks = 1, 335 .idimm_nrows = 14, 336 .idimm_ncolumns = 10, 337 .idimm_size = 0x80000000 338 }, 339 .ich_dimms[2] = { 340 .idimm_present = B_TRUE, 341 .idimm_nbanks = 3, 342 .idimm_width = 8, 343 .idimm_density = 2, 344 .idimm_nranks = 1, 345 .idimm_nrows = 14, 346 .idimm_ncolumns = 10, 347 .idimm_size = 0x80000000 348 }, 349 .ich_ntad_offsets = 12, 350 .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 351 0, 0 }, 352 .ich_nrankileaves = 8, 353 .ich_rankileaves[0] = { 354 .irle_enabled = B_TRUE, 355 .irle_nways = 2, 356 .irle_nwaysbits = 1, 357 .irle_limit = 0x80000000, 358 .irle_nentries = 2, 359 .irle_entries[0] = { 0x4, 0x0 }, 360 .irle_entries[1] = { 0x0, 0x0 }, 361 }, 362 .ich_rankileaves[1] = { 363 .irle_enabled = B_TRUE, 364 .irle_nways = 2, 365 .irle_nwaysbits = 1, 366 .irle_limit = 0x100000000ULL, 367 .irle_nentries = 2, 368 .irle_entries[0] = { 0x8, 0x40000000 }, 369 .irle_entries[1] = { 0x4, 0x0 }, 370 }, 371 .ich_rankileaves[2] = { 372 .irle_enabled = B_TRUE, 373 .irle_nways = 2, 374 .irle_nwaysbits = 1, 375 .irle_limit = 0x180000000ULL, 376 .irle_nentries = 2, 377 .irle_entries[0] = { 0x8, 0x40000000 }, 378 .irle_entries[1] = { 0x0, 0x40000000 }, 379 } 380 } 381 } 382 } 383 }; 384 385 386 const imc_test_case_t imc_test_rir[] = { { 387 .itc_desc = "RIR target 0, 8-way/4-rank, closed (1)", 388 .itc_imc = &imc_rir_8w_4r_closed, 389 .itc_pa = 0x0, 390 .itc_pass = B_TRUE, 391 .itc_nodeid = 0, 392 .itc_tadid = 0, 393 .itc_channelid = 0, 394 .itc_chanaddr = 0, 395 .itc_dimmid = 0, 396 .itc_rankid = 3, 397 .itc_rankaddr = 0 398 }, { 399 .itc_desc = "RIR target 1, 8-way/4-rank, closed", 400 .itc_imc = &imc_rir_8w_4r_closed, 401 .itc_pa = 0x40, 402 .itc_pass = B_TRUE, 403 .itc_nodeid = 0, 404 .itc_tadid = 0, 405 .itc_channelid = 0, 406 .itc_chanaddr = 0x40, 407 .itc_dimmid = 0, 408 .itc_rankid = 2, 409 .itc_rankaddr = 0 410 }, { 411 .itc_desc = "RIR target 2, 8-way/4-rank, closed", 412 .itc_imc = &imc_rir_8w_4r_closed, 413 .itc_pa = 0x80, 414 .itc_pass = B_TRUE, 415 .itc_nodeid = 0, 416 .itc_tadid = 0, 417 .itc_channelid = 0, 418 .itc_chanaddr = 0x80, 419 .itc_dimmid = 0, 420 .itc_rankid = 1, 421 .itc_rankaddr = 0 422 }, { 423 .itc_desc = "RIR target 3, 8-way/4-rank, closed", 424 .itc_imc = &imc_rir_8w_4r_closed, 425 .itc_pa = 0xc0, 426 .itc_pass = B_TRUE, 427 .itc_nodeid = 0, 428 .itc_tadid = 0, 429 .itc_channelid = 0, 430 .itc_chanaddr = 0xc0, 431 .itc_dimmid = 0, 432 .itc_rankid = 0, 433 .itc_rankaddr = 0 434 }, { 435 .itc_desc = "RIR target 4, 8-way/4-rank, closed", 436 .itc_imc = &imc_rir_8w_4r_closed, 437 .itc_pa = 0x100, 438 .itc_pass = B_TRUE, 439 .itc_nodeid = 0, 440 .itc_tadid = 0, 441 .itc_channelid = 0, 442 .itc_chanaddr = 0x100, 443 .itc_dimmid = 0, 444 .itc_rankid = 2, 445 .itc_rankaddr = 0 446 }, { 447 .itc_desc = "RIR target 5, 8-way/4-rank, closed", 448 .itc_imc = &imc_rir_8w_4r_closed, 449 .itc_pa = 0x140, 450 .itc_pass = B_TRUE, 451 .itc_nodeid = 0, 452 .itc_tadid = 0, 453 .itc_channelid = 0, 454 .itc_chanaddr = 0x140, 455 .itc_dimmid = 0, 456 .itc_rankid = 3, 457 .itc_rankaddr = 0 458 }, { 459 .itc_desc = "RIR target 6, 8-way/4-rank, closed", 460 .itc_imc = &imc_rir_8w_4r_closed, 461 .itc_pa = 0x180, 462 .itc_pass = B_TRUE, 463 .itc_nodeid = 0, 464 .itc_tadid = 0, 465 .itc_channelid = 0, 466 .itc_chanaddr = 0x180, 467 .itc_dimmid = 0, 468 .itc_rankid = 0, 469 .itc_rankaddr = 0 470 }, { 471 .itc_desc = "RIR target 7, 8-way/4-rank, closed", 472 .itc_imc = &imc_rir_8w_4r_closed, 473 .itc_pa = 0x1c0, 474 .itc_pass = B_TRUE, 475 .itc_nodeid = 0, 476 .itc_tadid = 0, 477 .itc_channelid = 0, 478 .itc_chanaddr = 0x1c0, 479 .itc_dimmid = 0, 480 .itc_rankid = 1, 481 .itc_rankaddr = 0 482 }, { 483 .itc_desc = "8-way/4-rank misc, closed (1)", 484 .itc_imc = &imc_rir_8w_4r_closed, 485 .itc_pa = 0x4000012f, 486 .itc_pass = B_TRUE, 487 .itc_nodeid = 0, 488 .itc_tadid = 0, 489 .itc_channelid = 0, 490 .itc_chanaddr = 0x4000012f, 491 .itc_dimmid = 0, 492 .itc_rankid = 2, 493 .itc_rankaddr = 0x800002f 494 }, { 495 .itc_desc = "8-way/4-rank misc, closed (2)", 496 .itc_imc = &imc_rir_8w_4r_closed, 497 .itc_pa = 0x76543210, 498 .itc_pass = B_TRUE, 499 .itc_nodeid = 0, 500 .itc_tadid = 0, 501 .itc_channelid = 0, 502 .itc_chanaddr = 0x76543210, 503 .itc_dimmid = 0, 504 .itc_rankid = 3, 505 .itc_rankaddr = 0xeca8650 506 }, { 507 .itc_desc = "8-way/4-rank misc, closed (3)", 508 .itc_imc = &imc_rir_8w_4r_closed, 509 .itc_pa = 0x12345678, 510 .itc_pass = B_TRUE, 511 .itc_nodeid = 0, 512 .itc_tadid = 0, 513 .itc_channelid = 0, 514 .itc_chanaddr = 0x12345678, 515 .itc_dimmid = 0, 516 .itc_rankid = 2, 517 .itc_rankaddr = 0x2468af8 518 }, { 519 .itc_desc = "8-way/4-rank misc, closed (4)", 520 .itc_imc = &imc_rir_8w_4r_closed, 521 .itc_pa = 0x232023, 522 .itc_pass = B_TRUE, 523 .itc_nodeid = 0, 524 .itc_tadid = 0, 525 .itc_channelid = 0, 526 .itc_chanaddr = 0x232023, 527 .itc_dimmid = 0, 528 .itc_rankid = 3, 529 .itc_rankaddr = 0x46423, 530 }, { 531 .itc_desc = "8-way/4-rank misc, closed (5)", 532 .itc_imc = &imc_rir_8w_4r_closed, 533 .itc_pa = 0x232063, 534 .itc_pass = B_TRUE, 535 .itc_nodeid = 0, 536 .itc_tadid = 0, 537 .itc_channelid = 0, 538 .itc_chanaddr = 0x232063, 539 .itc_dimmid = 0, 540 .itc_rankid = 2, 541 .itc_rankaddr = 0x46423, 542 }, { 543 .itc_desc = "8-way/4-rank misc, closed (6)", 544 .itc_imc = &imc_rir_8w_4r_closed, 545 .itc_pa = 0x2320a3, 546 .itc_pass = B_TRUE, 547 .itc_nodeid = 0, 548 .itc_tadid = 0, 549 .itc_channelid = 0, 550 .itc_chanaddr = 0x2320a3, 551 .itc_dimmid = 0, 552 .itc_rankid = 1, 553 .itc_rankaddr = 0x46423, 554 }, { 555 .itc_desc = "8-way/4-rank misc, closed (7)", 556 .itc_imc = &imc_rir_8w_4r_closed, 557 .itc_pa = 0x2320e3, 558 .itc_pass = B_TRUE, 559 .itc_nodeid = 0, 560 .itc_tadid = 0, 561 .itc_channelid = 0, 562 .itc_chanaddr = 0x2320e3, 563 .itc_dimmid = 0, 564 .itc_rankid = 0, 565 .itc_rankaddr = 0x46423, 566 }, { 567 .itc_desc = "8-way/4-rank misc, closed (8)", 568 .itc_imc = &imc_rir_8w_4r_closed, 569 .itc_pa = 0x232123, 570 .itc_pass = B_TRUE, 571 .itc_nodeid = 0, 572 .itc_tadid = 0, 573 .itc_channelid = 0, 574 .itc_chanaddr = 0x232123, 575 .itc_dimmid = 0, 576 .itc_rankid = 2, 577 .itc_rankaddr = 0x46423, 578 }, { 579 .itc_desc = "8-way/4-rank misc, closed (9)", 580 .itc_imc = &imc_rir_8w_4r_closed, 581 .itc_pa = 0x232163, 582 .itc_pass = B_TRUE, 583 .itc_nodeid = 0, 584 .itc_tadid = 0, 585 .itc_channelid = 0, 586 .itc_chanaddr = 0x232163, 587 .itc_dimmid = 0, 588 .itc_rankid = 3, 589 .itc_rankaddr = 0x46423, 590 }, { 591 .itc_desc = "8-way/4-rank misc, closed (10)", 592 .itc_imc = &imc_rir_8w_4r_closed, 593 .itc_pa = 0x2321a3, 594 .itc_pass = B_TRUE, 595 .itc_nodeid = 0, 596 .itc_tadid = 0, 597 .itc_channelid = 0, 598 .itc_chanaddr = 0x2321a3, 599 .itc_dimmid = 0, 600 .itc_rankid = 0, 601 .itc_rankaddr = 0x46423, 602 }, { 603 .itc_desc = "8-way/4-rank misc, closed (11)", 604 .itc_imc = &imc_rir_8w_4r_closed, 605 .itc_pa = 0x2321e3, 606 .itc_pass = B_TRUE, 607 .itc_nodeid = 0, 608 .itc_tadid = 0, 609 .itc_channelid = 0, 610 .itc_chanaddr = 0x2321e3, 611 .itc_dimmid = 0, 612 .itc_rankid = 1, 613 .itc_rankaddr = 0x46423, 614 }, { 615 .itc_desc = "4-way/4-rank, open (1)", 616 .itc_imc = &imc_rir_4w_4r_open, 617 .itc_pa = 0x0, 618 .itc_pass = B_TRUE, 619 .itc_nodeid = 0, 620 .itc_tadid = 0, 621 .itc_channelid = 0, 622 .itc_chanaddr = 0x0, 623 .itc_dimmid = 0, 624 .itc_rankid = 2, 625 .itc_rankaddr = 0x0, 626 }, { 627 .itc_desc = "4-way/4-rank, open (2)", 628 .itc_imc = &imc_rir_4w_4r_open, 629 .itc_pa = 0x2000, 630 .itc_pass = B_TRUE, 631 .itc_nodeid = 0, 632 .itc_tadid = 0, 633 .itc_channelid = 0, 634 .itc_chanaddr = 0x2000, 635 .itc_dimmid = 0, 636 .itc_rankid = 0, 637 .itc_rankaddr = 0x0 638 }, { 639 .itc_desc = "4-way/4-rank, open (3)", 640 .itc_imc = &imc_rir_4w_4r_open, 641 .itc_pa = 0x4000, 642 .itc_pass = B_TRUE, 643 .itc_nodeid = 0, 644 .itc_tadid = 0, 645 .itc_channelid = 0, 646 .itc_chanaddr = 0x4000, 647 .itc_dimmid = 0, 648 .itc_rankid = 3, 649 .itc_rankaddr = 0x0 650 }, { 651 .itc_desc = "4-way/4-rank, open (4)", 652 .itc_imc = &imc_rir_4w_4r_open, 653 .itc_pa = 0x6000, 654 .itc_pass = B_TRUE, 655 .itc_nodeid = 0, 656 .itc_tadid = 0, 657 .itc_channelid = 0, 658 .itc_chanaddr = 0x6000, 659 .itc_dimmid = 0, 660 .itc_rankid = 1, 661 .itc_rankaddr = 0x0 662 }, { 663 .itc_desc = "4-way/4-rank, open (5)", 664 .itc_imc = &imc_rir_4w_4r_open, 665 .itc_pa = 0x1234567, 666 .itc_pass = B_TRUE, 667 .itc_nodeid = 0, 668 .itc_tadid = 0, 669 .itc_channelid = 0, 670 .itc_chanaddr = 0x1234567, 671 .itc_dimmid = 0, 672 .itc_rankid = 3, 673 .itc_rankaddr = 0x48c567 674 }, { 675 .itc_desc = "4-way/4-rank, open (6)", 676 .itc_imc = &imc_rir_4w_4r_open, 677 .itc_pa = 0x76543210, 678 .itc_pass = B_TRUE, 679 .itc_nodeid = 0, 680 .itc_tadid = 0, 681 .itc_channelid = 0, 682 .itc_chanaddr = 0x76543210, 683 .itc_dimmid = 0, 684 .itc_rankid = 0, 685 .itc_rankaddr = 0x1d951210 686 }, { 687 .itc_desc = "2DPC (1)", 688 .itc_imc = &imc_rir_8w_4r_2dpc, 689 .itc_pa = 0xecdabcfe, 690 .itc_pass = B_TRUE, 691 .itc_nodeid = 0, 692 .itc_tadid = 0, 693 .itc_channelid = 0, 694 .itc_chanaddr = 0xecdabcfe, 695 .itc_dimmid = 1, 696 .itc_rankid = 1, 697 .itc_rankaddr = 0x1d9b57be 698 }, { 699 .itc_desc = "2DPC (2)", 700 .itc_imc = &imc_rir_8w_4r_2dpc, 701 .itc_pa = 0xecdabd3e, 702 .itc_pass = B_TRUE, 703 .itc_nodeid = 0, 704 .itc_tadid = 0, 705 .itc_channelid = 0, 706 .itc_chanaddr = 0xecdabd3e, 707 .itc_dimmid = 0, 708 .itc_rankid = 2, 709 .itc_rankaddr = 0x1d9b57be, 710 }, { 711 .itc_desc = "2DPC (3)", 712 .itc_imc = &imc_rir_8w_4r_2dpc, 713 .itc_pa = 0xecdabd7e, 714 .itc_pass = B_TRUE, 715 .itc_nodeid = 0, 716 .itc_tadid = 0, 717 .itc_channelid = 0, 718 .itc_chanaddr = 0xecdabd7e, 719 .itc_dimmid = 1, 720 .itc_rankid = 2, 721 .itc_rankaddr = 0x1d9b57be 722 }, { 723 .itc_desc = "2DPC (4)", 724 .itc_imc = &imc_rir_8w_4r_2dpc, 725 .itc_pa = 0xecdabdbe, 726 .itc_pass = B_TRUE, 727 .itc_nodeid = 0, 728 .itc_tadid = 0, 729 .itc_channelid = 0, 730 .itc_chanaddr = 0xecdabdbe, 731 .itc_dimmid = 0, 732 .itc_rankid = 3, 733 .itc_rankaddr = 0x1d9b57be 734 }, { 735 .itc_desc = "2DPC (5)", 736 .itc_imc = &imc_rir_8w_4r_2dpc, 737 .itc_pa = 0xecdabdfe, 738 .itc_pass = B_TRUE, 739 .itc_nodeid = 0, 740 .itc_tadid = 0, 741 .itc_channelid = 0, 742 .itc_chanaddr = 0xecdabdfe, 743 .itc_dimmid = 1, 744 .itc_rankid = 3, 745 .itc_rankaddr = 0x1d9b57be 746 }, { 747 .itc_desc = "2DPC (6)", 748 .itc_imc = &imc_rir_8w_4r_2dpc, 749 .itc_pa = 0xecdabe3e, 750 .itc_pass = B_TRUE, 751 .itc_nodeid = 0, 752 .itc_tadid = 0, 753 .itc_channelid = 0, 754 .itc_chanaddr = 0xecdabe3e, 755 .itc_dimmid = 0, 756 .itc_rankid = 0, 757 .itc_rankaddr = 0x1d9b57fe 758 }, { 759 .itc_desc = "2DPC (7)", 760 .itc_imc = &imc_rir_8w_4r_2dpc, 761 .itc_pa = 0xecdabe7e, 762 .itc_pass = B_TRUE, 763 .itc_nodeid = 0, 764 .itc_tadid = 0, 765 .itc_channelid = 0, 766 .itc_chanaddr = 0xecdabe7e, 767 .itc_dimmid = 1, 768 .itc_rankid = 0, 769 .itc_rankaddr = 0x1d9b57fe 770 }, { 771 .itc_desc = "2DPC (8)", 772 .itc_imc = &imc_rir_8w_4r_2dpc, 773 .itc_pa = 0xecdabebe, 774 .itc_pass = B_TRUE, 775 .itc_nodeid = 0, 776 .itc_tadid = 0, 777 .itc_channelid = 0, 778 .itc_chanaddr = 0xecdabebe, 779 .itc_dimmid = 0, 780 .itc_rankid = 1, 781 .itc_rankaddr = 0x1d9b57fe 782 }, { 783 .itc_desc = "Multi-RIR 1R 3DPC (1)", 784 .itc_imc = &imc_rir_2w_1r_3dpc, 785 .itc_pa = 0x0, 786 .itc_pass = B_TRUE, 787 .itc_nodeid = 0, 788 .itc_tadid = 0, 789 .itc_channelid = 0, 790 .itc_chanaddr = 0x0, 791 .itc_dimmid = 1, 792 .itc_rankid = 0, 793 .itc_rankaddr = 0x0 794 }, { 795 .itc_desc = "Multi-RIR 1R 3DPC (2)", 796 .itc_imc = &imc_rir_2w_1r_3dpc, 797 .itc_pa = 0x80000000ULL, 798 .itc_pass = B_TRUE, 799 .itc_nodeid = 0, 800 .itc_tadid = 0, 801 .itc_channelid = 0, 802 .itc_chanaddr = 0x80000000ULL, 803 .itc_dimmid = 2, 804 .itc_rankid = 0, 805 .itc_rankaddr = 0x0 806 }, { 807 .itc_desc = "Multi-RIR 1R 3DPC (3)", 808 .itc_imc = &imc_rir_2w_1r_3dpc, 809 .itc_pa = 0x100000000ULL, 810 .itc_pass = B_TRUE, 811 .itc_nodeid = 0, 812 .itc_tadid = 0, 813 .itc_channelid = 0, 814 .itc_chanaddr = 0x100000000ULL, 815 .itc_dimmid = 2, 816 .itc_rankid = 0, 817 .itc_rankaddr = 0x40000000 818 }, { 819 .itc_desc = "Multi-RIR 1R 3DPC (4)", 820 .itc_imc = &imc_rir_2w_1r_3dpc, 821 .itc_pa = 0x654321f5, 822 .itc_pass = B_TRUE, 823 .itc_nodeid = 0, 824 .itc_tadid = 0, 825 .itc_channelid = 0, 826 .itc_chanaddr = 0x654321f5, 827 .itc_dimmid = 0, 828 .itc_rankid = 0, 829 .itc_rankaddr = 0x32a190f5 830 }, { 831 .itc_desc = "Multi-RIR 1R 3DPC (5)", 832 .itc_imc = &imc_rir_2w_1r_3dpc, 833 .itc_pa = 0xdaddadf5, 834 .itc_pass = B_TRUE, 835 .itc_nodeid = 0, 836 .itc_tadid = 0, 837 .itc_channelid = 0, 838 .itc_chanaddr = 0xdaddadf5, 839 .itc_dimmid = 1, 840 .itc_rankid = 0, 841 .itc_rankaddr = 0x6d6ed6f5 842 }, { 843 .itc_desc = "Multi-RIR 1R 3DPC (6)", 844 .itc_imc = &imc_rir_2w_1r_3dpc, 845 .itc_pa = 0x170ff6099ULL, 846 .itc_pass = B_TRUE, 847 .itc_nodeid = 0, 848 .itc_tadid = 0, 849 .itc_channelid = 0, 850 .itc_chanaddr = 0x170ff6099ULL, 851 .itc_dimmid = 2, 852 .itc_rankid = 0, 853 .itc_rankaddr = 0x787fb059 854 }, { 855 .itc_desc = NULL 856 } }; 857