1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2019 Joyent, Inc. 14 */ 15 16 #include "imc_test.h" 17 18 /* 19 * This file tests several different miscellaneous failure modes by using 20 * incomplete imc_t and imc_t with bad data. 21 */ 22 23 /* 24 * This IMC is a nominally valid IMC; however, it has flags indicate that the 25 * socket has bad data. 26 */ 27 static const imc_t imc_badsock = { 28 .imc_gen = IMC_GEN_SANDY, 29 .imc_nsockets = 1, 30 .imc_sockets[0] = { 31 .isock_valid = IMC_SOCKET_V_BAD_NODEID, 32 .isock_sad = { 33 .isad_flags = 0, 34 .isad_valid = IMC_SAD_V_VALID, 35 .isad_tolm = 0x80000000, /* 2 GiB */ 36 .isad_tohm = 0x280000000ULL, /* 10 GiB */ 37 .isad_nrules = 10, 38 .isad_rules[0] = { 39 .isr_enable = B_TRUE, 40 .isr_limit = 0x80000000, 41 .isr_imode = IMC_SAD_IMODE_8t6, 42 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 43 .isr_targets = { 0, 0, 0, 0, 0, 0, 0, 0 } 44 }, 45 .isad_rules[1] = { 46 .isr_enable = B_TRUE, 47 .isr_limit = 0x280000000ULL, 48 .isr_imode = IMC_SAD_IMODE_8t6, 49 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 50 .isr_targets = { 0, 0, 0, 0, 0, 0, 0, 0 } 51 } 52 }, 53 .isock_ntad = 1, 54 .isock_tad[0] = { 55 .itad_flags = 0, 56 .itad_nrules = 12, 57 .itad_rules[0] = { 58 .itr_base = 0x0, 59 .itr_limit = 0x80000000, 60 .itr_sock_way = 1, 61 .itr_chan_way = 1, 62 .itr_sock_gran = IMC_TAD_GRAN_64B, 63 .itr_chan_gran = IMC_TAD_GRAN_64B, 64 .itr_ntargets = 4, 65 .itr_targets = { 0, 0, 0, 0 } 66 }, 67 .itad_rules[1] = { 68 .itr_base = 0x80000000, 69 .itr_limit = 0x280000000ULL, 70 .itr_sock_way = 1, 71 .itr_chan_way = 1, 72 .itr_sock_gran = IMC_TAD_GRAN_64B, 73 .itr_chan_gran = IMC_TAD_GRAN_64B, 74 .itr_ntargets = 4, 75 .itr_targets = { 0, 0, 0, 0 } 76 } 77 }, 78 .isock_nimc = 1, 79 .isock_imcs[0] = { 80 .icn_nchannels = 1, 81 .icn_dimm_type = IMC_DIMM_DDR3, 82 .icn_ecc = B_TRUE, 83 .icn_lockstep = B_FALSE, 84 .icn_closed = B_FALSE, 85 .icn_channels[0] = { 86 .ich_ndimms = 1, 87 .ich_dimms[0] = { 88 .idimm_present = B_TRUE, 89 .idimm_nbanks = 3, 90 .idimm_width = 8, 91 .idimm_density = 2, 92 .idimm_nranks = 2, 93 .idimm_nrows = 14, 94 .idimm_ncolumns = 10, 95 .idimm_size = 0x80000000 96 }, 97 .ich_ntad_offsets = 12, 98 .ich_tad_offsets = { 0, 0x80000000, 0, 0, 0, 0, 99 0, 0, 0, 0, 0 }, 100 .ich_nrankileaves = 8, 101 .ich_rankileaves[0] = { 102 .irle_enabled = B_TRUE, 103 .irle_nways = 2, 104 .irle_nwaysbits = 1, 105 .irle_limit = 0x200000000ULL, 106 .irle_nentries = 5, 107 .irle_entries[0] = { 0x0, 0x0 }, 108 .irle_entries[1] = { 0x1, 0x0 } 109 } 110 } 111 } 112 } 113 }; 114 115 static const imc_t imc_invalid_sad = { 116 .imc_gen = IMC_GEN_SANDY, 117 .imc_nsockets = 1, 118 .imc_sockets[0] = { 119 .isock_valid = 0, 120 .isock_sad = { 121 .isad_flags = 0, 122 .isad_valid = IMC_SAD_V_BAD_DRAM_ATTR, 123 .isad_tolm = 0x80000000, /* 2 GiB */ 124 .isad_tohm = 0x280000000ULL, /* 10 GiB */ 125 .isad_nrules = 10, 126 .isad_rules[0] = { 127 .isr_enable = B_TRUE, 128 .isr_limit = 0x80000000, 129 .isr_imode = IMC_SAD_IMODE_8t6, 130 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 131 .isr_targets = { 0, 0, 0, 0, 0, 0, 0, 0 } 132 }, 133 .isad_rules[1] = { 134 .isr_enable = B_TRUE, 135 .isr_limit = 0x280000000ULL, 136 .isr_imode = IMC_SAD_IMODE_8t6, 137 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 138 .isr_targets = { 0, 0, 0, 0, 0, 0, 0, 0 } 139 } 140 } 141 } 142 }; 143 144 static const imc_t imc_invalid_sad_rule = { 145 .imc_gen = IMC_GEN_SANDY, 146 .imc_nsockets = 1, 147 .imc_sockets[0] = { 148 .isock_valid = 0, 149 .isock_sad = { 150 .isad_flags = 0, 151 .isad_valid = IMC_SAD_V_VALID, 152 .isad_tolm = 0x80000000, /* 2 GiB */ 153 .isad_tohm = 0x280000000ULL, /* 10 GiB */ 154 .isad_nrules = 10, 155 .isad_rules[0] = { 156 .isr_enable = B_TRUE, 157 .isr_limit = 0x34, 158 .isr_imode = IMC_SAD_IMODE_8t6, 159 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 160 .isr_targets = { 0, 0, 0, 0, 0, 0, 0, 0 } 161 }, 162 .isad_rules[1] = { 163 .isr_enable = B_TRUE, 164 .isr_limit = 0x42, 165 .isr_imode = IMC_SAD_IMODE_8t6, 166 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 167 .isr_targets = { 0, 0, 0, 0, 0, 0, 0, 0 } 168 } 169 } 170 } 171 }; 172 173 static const imc_t imc_invalid_sad_interleave = { 174 .imc_gen = IMC_GEN_SANDY, 175 .imc_nsockets = 1, 176 .imc_sockets[0] = { 177 .isock_valid = 0, 178 .isock_sad = { 179 .isad_flags = 0, 180 .isad_valid = IMC_SAD_V_VALID, 181 .isad_tolm = 0x80000000, /* 2 GiB */ 182 .isad_tohm = 0x280000000ULL, /* 10 GiB */ 183 .isad_nrules = 10, 184 .isad_rules[0] = { 185 .isr_enable = B_TRUE, 186 .isr_limit = 0x80000000, 187 .isr_imode = IMC_SAD_IMODE_8t6, 188 .isr_ntargets = 0 189 }, 190 .isad_rules[1] = { 191 .isr_enable = B_TRUE, 192 .isr_limit = 0x280000000ULL, 193 .isr_imode = IMC_SAD_IMODE_8t6, 194 .isr_ntargets = 0 195 } 196 } 197 } 198 }; 199 200 static const imc_t imc_invalid_sad_target = { 201 .imc_gen = IMC_GEN_SANDY, 202 .imc_nsockets = 1, 203 .imc_sockets[0] = { 204 .isock_valid = 0, 205 .isock_sad = { 206 .isad_flags = 0, 207 .isad_valid = IMC_SAD_V_VALID, 208 .isad_tolm = 0x80000000, /* 2 GiB */ 209 .isad_tohm = 0x280000000ULL, /* 10 GiB */ 210 .isad_nrules = 10, 211 .isad_rules[0] = { 212 .isr_enable = B_TRUE, 213 .isr_limit = 0x80000000, 214 .isr_imode = IMC_SAD_IMODE_8t6, 215 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 216 .isr_targets = { 9, 9, 9, 9, 9, 9, 9, 9 } 217 }, 218 .isad_rules[1] = { 219 .isr_enable = B_TRUE, 220 .isr_limit = 0x280000000ULL, 221 .isr_imode = IMC_SAD_IMODE_8t6, 222 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 223 .isr_targets = { 0, 0, 0, 0, 0, 0, 0, 0 } 224 } 225 } 226 } 227 }; 228 229 static const imc_t imc_bad_tad_rule = { 230 .imc_gen = IMC_GEN_SANDY, 231 .imc_nsockets = 1, 232 .imc_sockets[0] = { 233 .isock_valid = IMC_SOCKET_V_VALID, 234 .isock_sad = { 235 .isad_flags = 0, 236 .isad_valid = IMC_SAD_V_VALID, 237 .isad_tolm = 0x80000000, /* 2 GiB */ 238 .isad_tohm = 0x280000000ULL, /* 10 GiB */ 239 .isad_nrules = 10, 240 .isad_rules[0] = { 241 .isr_enable = B_TRUE, 242 .isr_limit = 0x80000000, 243 .isr_imode = IMC_SAD_IMODE_8t6, 244 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 245 .isr_targets = { 0, 0, 0, 0, 0, 0, 0, 0 } 246 }, 247 .isad_rules[1] = { 248 .isr_enable = B_TRUE, 249 .isr_limit = 0x280000000ULL, 250 .isr_imode = IMC_SAD_IMODE_8t6, 251 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 252 .isr_targets = { 0, 0, 0, 0, 0, 0, 0, 0 } 253 } 254 }, 255 .isock_ntad = 1, 256 .isock_tad[0] = { 257 .itad_flags = 0, 258 .itad_nrules = 12, 259 .itad_rules[0] = { 260 .itr_base = 0x0, 261 .itr_limit = 0x2, 262 .itr_sock_way = 1, 263 .itr_chan_way = 1, 264 .itr_sock_gran = IMC_TAD_GRAN_64B, 265 .itr_chan_gran = IMC_TAD_GRAN_64B, 266 .itr_ntargets = 4, 267 .itr_targets = { 0, 0, 0, 0 } 268 }, 269 .itad_rules[1] = { 270 .itr_base = 0x277777777ULL, 271 .itr_limit = 0x280000000ULL, 272 .itr_sock_way = 1, 273 .itr_chan_way = 1, 274 .itr_sock_gran = IMC_TAD_GRAN_64B, 275 .itr_chan_gran = IMC_TAD_GRAN_64B, 276 .itr_ntargets = 4, 277 .itr_targets = { 0, 0, 0, 0 } 278 } 279 } 280 } 281 }; 282 283 static const imc_t imc_bad_tad_3way = { 284 .imc_gen = IMC_GEN_SANDY, 285 .imc_nsockets = 1, 286 .imc_sockets[0] = { 287 .isock_valid = IMC_SOCKET_V_VALID, 288 .isock_sad = { 289 .isad_flags = 0, 290 .isad_valid = IMC_SAD_V_VALID, 291 .isad_tolm = 0x80000000, /* 2 GiB */ 292 .isad_tohm = 0x280000000ULL, /* 10 GiB */ 293 .isad_nrules = 10, 294 .isad_rules[0] = { 295 .isr_enable = B_TRUE, 296 .isr_limit = 0x80000000, 297 .isr_imode = IMC_SAD_IMODE_8t6, 298 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 299 .isr_targets = { 0, 0, 0, 0, 0, 0, 0, 0 } 300 }, 301 .isad_rules[1] = { 302 .isr_enable = B_TRUE, 303 .isr_limit = 0x280000000ULL, 304 .isr_imode = IMC_SAD_IMODE_8t6, 305 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 306 .isr_targets = { 0, 0, 0, 0, 0, 0, 0, 0 } 307 } 308 }, 309 .isock_ntad = 1, 310 .isock_tad[0] = { 311 .itad_flags = 0, 312 .itad_nrules = 12, 313 .itad_rules[0] = { 314 .itr_base = 0x0, 315 .itr_limit = 0x80000000, 316 .itr_sock_way = 1, 317 .itr_chan_way = 3, 318 .itr_sock_gran = IMC_TAD_GRAN_64B, 319 .itr_chan_gran = IMC_TAD_GRAN_64B, 320 .itr_ntargets = 4, 321 .itr_targets = { 0, 0, 0, 0 } 322 }, 323 .itad_rules[1] = { 324 .itr_base = 0x80000000, 325 .itr_limit = 0x280000000ULL, 326 .itr_sock_way = 1, 327 .itr_chan_way = 3, 328 .itr_sock_gran = IMC_TAD_GRAN_64B, 329 .itr_chan_gran = IMC_TAD_GRAN_64B, 330 .itr_ntargets = 4, 331 .itr_targets = { 0, 0, 0, 0 } 332 } 333 } 334 } 335 }; 336 337 static const imc_t imc_bad_tad_target = { 338 .imc_gen = IMC_GEN_SANDY, 339 .imc_nsockets = 1, 340 .imc_sockets[0] = { 341 .isock_valid = IMC_SOCKET_V_VALID, 342 .isock_sad = { 343 .isad_flags = 0, 344 .isad_valid = IMC_SAD_V_VALID, 345 .isad_tolm = 0x80000000, /* 2 GiB */ 346 .isad_tohm = 0x280000000ULL, /* 10 GiB */ 347 .isad_nrules = 10, 348 .isad_rules[0] = { 349 .isr_enable = B_TRUE, 350 .isr_limit = 0x80000000, 351 .isr_imode = IMC_SAD_IMODE_8t6, 352 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 353 .isr_targets = { 0, 0, 0, 0, 0, 0, 0, 0 } 354 }, 355 .isad_rules[1] = { 356 .isr_enable = B_TRUE, 357 .isr_limit = 0x280000000ULL, 358 .isr_imode = IMC_SAD_IMODE_8t6, 359 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 360 .isr_targets = { 0, 0, 0, 0, 0, 0, 0, 0 } 361 } 362 }, 363 .isock_ntad = 1, 364 .isock_tad[0] = { 365 .itad_flags = 0, 366 .itad_nrules = 12, 367 .itad_rules[0] = { 368 .itr_base = 0x0, 369 .itr_limit = 0x80000000, 370 .itr_sock_way = 1, 371 .itr_chan_way = 1, 372 .itr_sock_gran = IMC_TAD_GRAN_64B, 373 .itr_chan_gran = IMC_TAD_GRAN_64B, 374 .itr_ntargets = 0, 375 .itr_targets = { 0, 0, 0, 0 } 376 }, 377 .itad_rules[1] = { 378 .itr_base = 0x80000000, 379 .itr_limit = 0x280000000ULL, 380 .itr_sock_way = 1, 381 .itr_chan_way = 1, 382 .itr_sock_gran = IMC_TAD_GRAN_64B, 383 .itr_chan_gran = IMC_TAD_GRAN_64B, 384 .itr_ntargets = 0, 385 .itr_targets = { 0, 0, 0, 0 } 386 } 387 } 388 } 389 }; 390 391 static const imc_t imc_bad_tad_channelid = { 392 .imc_gen = IMC_GEN_SANDY, 393 .imc_nsockets = 1, 394 .imc_sockets[0] = { 395 .isock_valid = IMC_SOCKET_V_VALID, 396 .isock_sad = { 397 .isad_flags = 0, 398 .isad_valid = IMC_SAD_V_VALID, 399 .isad_tolm = 0x80000000, /* 2 GiB */ 400 .isad_tohm = 0x280000000ULL, /* 10 GiB */ 401 .isad_nrules = 10, 402 .isad_rules[0] = { 403 .isr_enable = B_TRUE, 404 .isr_limit = 0x80000000, 405 .isr_imode = IMC_SAD_IMODE_8t6, 406 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 407 .isr_targets = { 0, 0, 0, 0, 0, 0, 0, 0 } 408 }, 409 .isad_rules[1] = { 410 .isr_enable = B_TRUE, 411 .isr_limit = 0x280000000ULL, 412 .isr_imode = IMC_SAD_IMODE_8t6, 413 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 414 .isr_targets = { 0, 0, 0, 0, 0, 0, 0, 0 } 415 } 416 }, 417 .isock_ntad = 1, 418 .isock_tad[0] = { 419 .itad_flags = 0, 420 .itad_nrules = 12, 421 .itad_rules[0] = { 422 .itr_base = 0x0, 423 .itr_limit = 0x80000000, 424 .itr_sock_way = 1, 425 .itr_chan_way = 1, 426 .itr_sock_gran = IMC_TAD_GRAN_64B, 427 .itr_chan_gran = IMC_TAD_GRAN_64B, 428 .itr_ntargets = 4, 429 .itr_targets = { 17, 23, 42, 167 } 430 }, 431 .itad_rules[1] = { 432 .itr_base = 0x80000000, 433 .itr_limit = 0x280000000ULL, 434 .itr_sock_way = 1, 435 .itr_chan_way = 1, 436 .itr_sock_gran = IMC_TAD_GRAN_64B, 437 .itr_chan_gran = IMC_TAD_GRAN_64B, 438 .itr_ntargets = 4, 439 .itr_targets = { 17, 23, 42, 167 } 440 } 441 }, 442 .isock_nimc = 1, 443 .isock_imcs[0] = { 444 .icn_nchannels = 1, 445 .icn_dimm_type = IMC_DIMM_DDR3, 446 .icn_ecc = B_TRUE, 447 .icn_lockstep = B_FALSE, 448 .icn_closed = B_FALSE, 449 .icn_channels[0] = { 450 .ich_ndimms = 1, 451 .ich_dimms[0] = { 452 .idimm_present = B_TRUE, 453 .idimm_nbanks = 3, 454 .idimm_width = 8, 455 .idimm_density = 2, 456 .idimm_nranks = 2, 457 .idimm_nrows = 14, 458 .idimm_ncolumns = 10, 459 .idimm_size = 0x80000000 460 }, 461 .ich_ntad_offsets = 12, 462 .ich_tad_offsets = { 0, 0x80000000, 0, 0, 0, 0, 463 0, 0, 0, 0, 0 }, 464 .ich_nrankileaves = 8, 465 .ich_rankileaves[0] = { 466 .irle_enabled = B_TRUE, 467 .irle_nways = 2, 468 .irle_nwaysbits = 1, 469 .irle_limit = 0x200000000ULL, 470 .irle_nentries = 5, 471 .irle_entries[0] = { 0x0, 0x0 }, 472 .irle_entries[1] = { 0x1, 0x0 } 473 } 474 } 475 } 476 } 477 }; 478 479 static const imc_t imc_bad_channel_offset = { 480 .imc_gen = IMC_GEN_SANDY, 481 .imc_nsockets = 1, 482 .imc_sockets[0] = { 483 .isock_valid = IMC_SOCKET_V_VALID, 484 .isock_sad = { 485 .isad_flags = 0, 486 .isad_valid = IMC_SAD_V_VALID, 487 .isad_tolm = 0x80000000, /* 2 GiB */ 488 .isad_tohm = 0x280000000ULL, /* 10 GiB */ 489 .isad_nrules = 10, 490 .isad_rules[0] = { 491 .isr_enable = B_TRUE, 492 .isr_limit = 0x80000000, 493 .isr_imode = IMC_SAD_IMODE_8t6, 494 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 495 .isr_targets = { 0, 0, 0, 0, 0, 0, 0, 0 } 496 }, 497 .isad_rules[1] = { 498 .isr_enable = B_TRUE, 499 .isr_limit = 0x280000000ULL, 500 .isr_imode = IMC_SAD_IMODE_8t6, 501 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 502 .isr_targets = { 0, 0, 0, 0, 0, 0, 0, 0 } 503 } 504 }, 505 .isock_ntad = 1, 506 .isock_tad[0] = { 507 .itad_flags = 0, 508 .itad_nrules = 12, 509 .itad_rules[0] = { 510 .itr_base = 0x0, 511 .itr_limit = 0x80000000, 512 .itr_sock_way = 1, 513 .itr_chan_way = 1, 514 .itr_sock_gran = IMC_TAD_GRAN_64B, 515 .itr_chan_gran = IMC_TAD_GRAN_64B, 516 .itr_ntargets = 4, 517 .itr_targets = { 0, 0, 0, 0 } 518 }, 519 .itad_rules[1] = { 520 .itr_base = 0x80000000, 521 .itr_limit = 0x280000000ULL, 522 .itr_sock_way = 1, 523 .itr_chan_way = 1, 524 .itr_sock_gran = IMC_TAD_GRAN_64B, 525 .itr_chan_gran = IMC_TAD_GRAN_64B, 526 .itr_ntargets = 4, 527 .itr_targets = { 0, 0, 0, 0 } 528 } 529 }, 530 .isock_nimc = 1, 531 .isock_imcs[0] = { 532 .icn_nchannels = 1, 533 .icn_dimm_type = IMC_DIMM_DDR3, 534 .icn_ecc = B_TRUE, 535 .icn_lockstep = B_FALSE, 536 .icn_closed = B_FALSE, 537 .icn_channels[0] = { 538 .ich_ndimms = 1, 539 .ich_dimms[0] = { 540 .idimm_present = B_TRUE, 541 .idimm_nbanks = 3, 542 .idimm_width = 8, 543 .idimm_density = 2, 544 .idimm_nranks = 2, 545 .idimm_nrows = 14, 546 .idimm_ncolumns = 10, 547 .idimm_size = 0x80000000 548 }, 549 .ich_ntad_offsets = 0, 550 .ich_tad_offsets = { 0, 0x80000000, 0, 0, 0, 0, 551 0, 0, 0, 0, 0 }, 552 .ich_nrankileaves = 8, 553 .ich_rankileaves[0] = { 554 .irle_enabled = B_TRUE, 555 .irle_nways = 2, 556 .irle_nwaysbits = 1, 557 .irle_limit = 0x200000000ULL, 558 .irle_nentries = 5, 559 .irle_entries[0] = { 0x0, 0x0 }, 560 .irle_entries[1] = { 0x1, 0x0 } 561 } 562 } 563 } 564 } 565 }; 566 567 static const imc_t imc_bad_rir_rule = { 568 .imc_gen = IMC_GEN_SANDY, 569 .imc_nsockets = 1, 570 .imc_sockets[0] = { 571 .isock_valid = IMC_SOCKET_V_VALID, 572 .isock_sad = { 573 .isad_flags = 0, 574 .isad_valid = IMC_SAD_V_VALID, 575 .isad_tolm = 0x80000000, /* 2 GiB */ 576 .isad_tohm = 0x280000000ULL, /* 10 GiB */ 577 .isad_nrules = 10, 578 .isad_rules[0] = { 579 .isr_enable = B_TRUE, 580 .isr_limit = 0x80000000, 581 .isr_imode = IMC_SAD_IMODE_8t6, 582 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 583 .isr_targets = { 0, 0, 0, 0, 0, 0, 0, 0 } 584 }, 585 .isad_rules[1] = { 586 .isr_enable = B_TRUE, 587 .isr_limit = 0x280000000ULL, 588 .isr_imode = IMC_SAD_IMODE_8t6, 589 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 590 .isr_targets = { 0, 0, 0, 0, 0, 0, 0, 0 } 591 } 592 }, 593 .isock_ntad = 1, 594 .isock_tad[0] = { 595 .itad_flags = 0, 596 .itad_nrules = 12, 597 .itad_rules[0] = { 598 .itr_base = 0x0, 599 .itr_limit = 0x80000000, 600 .itr_sock_way = 1, 601 .itr_chan_way = 1, 602 .itr_sock_gran = IMC_TAD_GRAN_64B, 603 .itr_chan_gran = IMC_TAD_GRAN_64B, 604 .itr_ntargets = 4, 605 .itr_targets = { 0, 0, 0, 0 } 606 }, 607 .itad_rules[1] = { 608 .itr_base = 0x80000000, 609 .itr_limit = 0x280000000ULL, 610 .itr_sock_way = 1, 611 .itr_chan_way = 1, 612 .itr_sock_gran = IMC_TAD_GRAN_64B, 613 .itr_chan_gran = IMC_TAD_GRAN_64B, 614 .itr_ntargets = 4, 615 .itr_targets = { 0, 0, 0, 0 } 616 } 617 }, 618 .isock_nimc = 1, 619 .isock_imcs[0] = { 620 .icn_nchannels = 1, 621 .icn_dimm_type = IMC_DIMM_DDR3, 622 .icn_ecc = B_TRUE, 623 .icn_lockstep = B_FALSE, 624 .icn_closed = B_FALSE, 625 .icn_channels[0] = { 626 .ich_ndimms = 1, 627 .ich_dimms[0] = { 628 .idimm_present = B_TRUE, 629 .idimm_nbanks = 3, 630 .idimm_width = 8, 631 .idimm_density = 2, 632 .idimm_nranks = 2, 633 .idimm_nrows = 14, 634 .idimm_ncolumns = 10, 635 .idimm_size = 0x80000000 636 }, 637 .ich_ntad_offsets = 12, 638 .ich_tad_offsets = { 0, 0x80000000, 0, 0, 0, 0, 639 0, 0, 0, 0, 0 }, 640 .ich_nrankileaves = 8, 641 .ich_rankileaves[0] = { 642 .irle_enabled = B_TRUE, 643 .irle_nways = 2, 644 .irle_nwaysbits = 1, 645 .irle_limit = 0x1, 646 .irle_nentries = 5, 647 .irle_entries[0] = { 0x0, 0x0 }, 648 .irle_entries[1] = { 0x1, 0x0 } 649 } 650 } 651 } 652 } 653 }; 654 655 static const imc_t imc_bad_rir_ileave = { 656 .imc_gen = IMC_GEN_SANDY, 657 .imc_nsockets = 1, 658 .imc_sockets[0] = { 659 .isock_valid = IMC_SOCKET_V_VALID, 660 .isock_sad = { 661 .isad_flags = 0, 662 .isad_valid = IMC_SAD_V_VALID, 663 .isad_tolm = 0x80000000, /* 2 GiB */ 664 .isad_tohm = 0x280000000ULL, /* 10 GiB */ 665 .isad_nrules = 10, 666 .isad_rules[0] = { 667 .isr_enable = B_TRUE, 668 .isr_limit = 0x80000000, 669 .isr_imode = IMC_SAD_IMODE_8t6, 670 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 671 .isr_targets = { 0, 0, 0, 0, 0, 0, 0, 0 } 672 }, 673 .isad_rules[1] = { 674 .isr_enable = B_TRUE, 675 .isr_limit = 0x280000000ULL, 676 .isr_imode = IMC_SAD_IMODE_8t6, 677 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 678 .isr_targets = { 0, 0, 0, 0, 0, 0, 0, 0 } 679 } 680 }, 681 .isock_ntad = 1, 682 .isock_tad[0] = { 683 .itad_flags = 0, 684 .itad_nrules = 12, 685 .itad_rules[0] = { 686 .itr_base = 0x0, 687 .itr_limit = 0x80000000, 688 .itr_sock_way = 1, 689 .itr_chan_way = 1, 690 .itr_sock_gran = IMC_TAD_GRAN_64B, 691 .itr_chan_gran = IMC_TAD_GRAN_64B, 692 .itr_ntargets = 4, 693 .itr_targets = { 0, 0, 0, 0 } 694 }, 695 .itad_rules[1] = { 696 .itr_base = 0x80000000, 697 .itr_limit = 0x280000000ULL, 698 .itr_sock_way = 1, 699 .itr_chan_way = 1, 700 .itr_sock_gran = IMC_TAD_GRAN_64B, 701 .itr_chan_gran = IMC_TAD_GRAN_64B, 702 .itr_ntargets = 4, 703 .itr_targets = { 0, 0, 0, 0 } 704 } 705 }, 706 .isock_nimc = 1, 707 .isock_imcs[0] = { 708 .icn_nchannels = 1, 709 .icn_dimm_type = IMC_DIMM_DDR3, 710 .icn_ecc = B_TRUE, 711 .icn_lockstep = B_FALSE, 712 .icn_closed = B_FALSE, 713 .icn_channels[0] = { 714 .ich_ndimms = 1, 715 .ich_dimms[0] = { 716 .idimm_present = B_TRUE, 717 .idimm_nbanks = 3, 718 .idimm_width = 8, 719 .idimm_density = 2, 720 .idimm_nranks = 2, 721 .idimm_nrows = 14, 722 .idimm_ncolumns = 10, 723 .idimm_size = 0x80000000 724 }, 725 .ich_ntad_offsets = 12, 726 .ich_tad_offsets = { 0, 0x80000000, 0, 0, 0, 0, 727 0, 0, 0, 0, 0 }, 728 .ich_nrankileaves = 8, 729 .ich_rankileaves[0] = { 730 .irle_enabled = B_TRUE, 731 .irle_nways = 2, 732 .irle_nwaysbits = 1, 733 .irle_limit = 0x200000000ULL, 734 .irle_nentries = 0 735 } 736 } 737 } 738 } 739 }; 740 741 static const imc_t imc_bad_dimm_index = { 742 .imc_gen = IMC_GEN_SANDY, 743 .imc_nsockets = 1, 744 .imc_sockets[0] = { 745 .isock_valid = IMC_SOCKET_V_VALID, 746 .isock_sad = { 747 .isad_flags = 0, 748 .isad_valid = IMC_SAD_V_VALID, 749 .isad_tolm = 0x80000000, /* 2 GiB */ 750 .isad_tohm = 0x280000000ULL, /* 10 GiB */ 751 .isad_nrules = 10, 752 .isad_rules[0] = { 753 .isr_enable = B_TRUE, 754 .isr_limit = 0x80000000, 755 .isr_imode = IMC_SAD_IMODE_8t6, 756 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 757 .isr_targets = { 0, 0, 0, 0, 0, 0, 0, 0 } 758 }, 759 .isad_rules[1] = { 760 .isr_enable = B_TRUE, 761 .isr_limit = 0x280000000ULL, 762 .isr_imode = IMC_SAD_IMODE_8t6, 763 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 764 .isr_targets = { 0, 0, 0, 0, 0, 0, 0, 0 } 765 } 766 }, 767 .isock_ntad = 1, 768 .isock_tad[0] = { 769 .itad_flags = 0, 770 .itad_nrules = 12, 771 .itad_rules[0] = { 772 .itr_base = 0x0, 773 .itr_limit = 0x80000000, 774 .itr_sock_way = 1, 775 .itr_chan_way = 1, 776 .itr_sock_gran = IMC_TAD_GRAN_64B, 777 .itr_chan_gran = IMC_TAD_GRAN_64B, 778 .itr_ntargets = 4, 779 .itr_targets = { 0, 0, 0, 0 } 780 }, 781 .itad_rules[1] = { 782 .itr_base = 0x80000000, 783 .itr_limit = 0x280000000ULL, 784 .itr_sock_way = 1, 785 .itr_chan_way = 1, 786 .itr_sock_gran = IMC_TAD_GRAN_64B, 787 .itr_chan_gran = IMC_TAD_GRAN_64B, 788 .itr_ntargets = 4, 789 .itr_targets = { 0, 0, 0, 0 } 790 } 791 }, 792 .isock_nimc = 1, 793 .isock_imcs[0] = { 794 .icn_nchannels = 1, 795 .icn_dimm_type = IMC_DIMM_DDR3, 796 .icn_ecc = B_TRUE, 797 .icn_lockstep = B_FALSE, 798 .icn_closed = B_FALSE, 799 .icn_channels[0] = { 800 .ich_ndimms = 1, 801 .ich_dimms[0] = { 802 .idimm_present = B_TRUE, 803 .idimm_nbanks = 3, 804 .idimm_width = 8, 805 .idimm_density = 2, 806 .idimm_nranks = 2, 807 .idimm_nrows = 14, 808 .idimm_ncolumns = 10, 809 .idimm_size = 0x80000000 810 }, 811 .ich_ntad_offsets = 12, 812 .ich_tad_offsets = { 0, 0x80000000, 0, 0, 0, 0, 813 0, 0, 0, 0, 0 }, 814 .ich_nrankileaves = 8, 815 .ich_rankileaves[0] = { 816 .irle_enabled = B_TRUE, 817 .irle_nways = 2, 818 .irle_nwaysbits = 1, 819 .irle_limit = 0x200000000ULL, 820 .irle_nentries = 5, 821 .irle_entries[0] = { 0x23, 0x0 }, 822 .irle_entries[1] = { 0x42, 0x0 } 823 } 824 } 825 } 826 } 827 }; 828 829 static const imc_t imc_missing_dimm = { 830 .imc_gen = IMC_GEN_SANDY, 831 .imc_nsockets = 1, 832 .imc_sockets[0] = { 833 .isock_valid = IMC_SOCKET_V_VALID, 834 .isock_sad = { 835 .isad_flags = 0, 836 .isad_valid = IMC_SAD_V_VALID, 837 .isad_tolm = 0x80000000, /* 2 GiB */ 838 .isad_tohm = 0x280000000ULL, /* 10 GiB */ 839 .isad_nrules = 10, 840 .isad_rules[0] = { 841 .isr_enable = B_TRUE, 842 .isr_limit = 0x80000000, 843 .isr_imode = IMC_SAD_IMODE_8t6, 844 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 845 .isr_targets = { 0, 0, 0, 0, 0, 0, 0, 0 } 846 }, 847 .isad_rules[1] = { 848 .isr_enable = B_TRUE, 849 .isr_limit = 0x280000000ULL, 850 .isr_imode = IMC_SAD_IMODE_8t6, 851 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 852 .isr_targets = { 0, 0, 0, 0, 0, 0, 0, 0 } 853 } 854 }, 855 .isock_ntad = 1, 856 .isock_tad[0] = { 857 .itad_flags = 0, 858 .itad_nrules = 12, 859 .itad_rules[0] = { 860 .itr_base = 0x0, 861 .itr_limit = 0x80000000, 862 .itr_sock_way = 1, 863 .itr_chan_way = 1, 864 .itr_sock_gran = IMC_TAD_GRAN_64B, 865 .itr_chan_gran = IMC_TAD_GRAN_64B, 866 .itr_ntargets = 4, 867 .itr_targets = { 0, 0, 0, 0 } 868 }, 869 .itad_rules[1] = { 870 .itr_base = 0x80000000, 871 .itr_limit = 0x280000000ULL, 872 .itr_sock_way = 1, 873 .itr_chan_way = 1, 874 .itr_sock_gran = IMC_TAD_GRAN_64B, 875 .itr_chan_gran = IMC_TAD_GRAN_64B, 876 .itr_ntargets = 4, 877 .itr_targets = { 0, 0, 0, 0 } 878 } 879 }, 880 .isock_nimc = 1, 881 .isock_imcs[0] = { 882 .icn_nchannels = 1, 883 .icn_dimm_type = IMC_DIMM_DDR3, 884 .icn_ecc = B_TRUE, 885 .icn_lockstep = B_FALSE, 886 .icn_closed = B_FALSE, 887 .icn_channels[0] = { 888 .ich_ndimms = 1, 889 .ich_dimms[0] = { 890 .idimm_present = B_FALSE 891 }, 892 .ich_ntad_offsets = 12, 893 .ich_tad_offsets = { 0, 0x80000000, 0, 0, 0, 0, 894 0, 0, 0, 0, 0 }, 895 .ich_nrankileaves = 8, 896 .ich_rankileaves[0] = { 897 .irle_enabled = B_TRUE, 898 .irle_nways = 2, 899 .irle_nwaysbits = 1, 900 .irle_limit = 0x200000000ULL, 901 .irle_nentries = 5, 902 .irle_entries[0] = { 0x0, 0x0 }, 903 .irle_entries[1] = { 0x1, 0x0 } 904 } 905 } 906 } 907 } 908 }; 909 910 static const imc_t imc_bad_rank_index = { 911 .imc_gen = IMC_GEN_SANDY, 912 .imc_nsockets = 1, 913 .imc_sockets[0] = { 914 .isock_valid = IMC_SOCKET_V_VALID, 915 .isock_sad = { 916 .isad_flags = 0, 917 .isad_valid = IMC_SAD_V_VALID, 918 .isad_tolm = 0x80000000, /* 2 GiB */ 919 .isad_tohm = 0x280000000ULL, /* 10 GiB */ 920 .isad_nrules = 10, 921 .isad_rules[0] = { 922 .isr_enable = B_TRUE, 923 .isr_limit = 0x80000000, 924 .isr_imode = IMC_SAD_IMODE_8t6, 925 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 926 .isr_targets = { 0, 0, 0, 0, 0, 0, 0, 0 } 927 }, 928 .isad_rules[1] = { 929 .isr_enable = B_TRUE, 930 .isr_limit = 0x280000000ULL, 931 .isr_imode = IMC_SAD_IMODE_8t6, 932 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 933 .isr_targets = { 0, 0, 0, 0, 0, 0, 0, 0 } 934 } 935 }, 936 .isock_ntad = 1, 937 .isock_tad[0] = { 938 .itad_flags = 0, 939 .itad_nrules = 12, 940 .itad_rules[0] = { 941 .itr_base = 0x0, 942 .itr_limit = 0x80000000, 943 .itr_sock_way = 1, 944 .itr_chan_way = 1, 945 .itr_sock_gran = IMC_TAD_GRAN_64B, 946 .itr_chan_gran = IMC_TAD_GRAN_64B, 947 .itr_ntargets = 4, 948 .itr_targets = { 0, 0, 0, 0 } 949 }, 950 .itad_rules[1] = { 951 .itr_base = 0x80000000, 952 .itr_limit = 0x280000000ULL, 953 .itr_sock_way = 1, 954 .itr_chan_way = 1, 955 .itr_sock_gran = IMC_TAD_GRAN_64B, 956 .itr_chan_gran = IMC_TAD_GRAN_64B, 957 .itr_ntargets = 4, 958 .itr_targets = { 0, 0, 0, 0 } 959 } 960 }, 961 .isock_nimc = 1, 962 .isock_imcs[0] = { 963 .icn_nchannels = 1, 964 .icn_dimm_type = IMC_DIMM_DDR3, 965 .icn_ecc = B_TRUE, 966 .icn_lockstep = B_FALSE, 967 .icn_closed = B_FALSE, 968 .icn_channels[0] = { 969 .ich_ndimms = 1, 970 .ich_dimms[0] = { 971 .idimm_present = B_TRUE, 972 .idimm_nbanks = 3, 973 .idimm_width = 8, 974 .idimm_density = 2, 975 .idimm_nranks = 2, 976 .idimm_nrows = 14, 977 .idimm_ncolumns = 10, 978 .idimm_size = 0x80000000 979 }, 980 .ich_ntad_offsets = 12, 981 .ich_tad_offsets = { 0, 0x80000000, 0, 0, 0, 0, 982 0, 0, 0, 0, 0 }, 983 .ich_nrankileaves = 8, 984 .ich_rankileaves[0] = { 985 .irle_enabled = B_TRUE, 986 .irle_nways = 2, 987 .irle_nwaysbits = 1, 988 .irle_limit = 0x200000000ULL, 989 .irle_nentries = 5, 990 .irle_entries[0] = { 0x2, 0x0 }, 991 .irle_entries[1] = { 0x3, 0x0 } 992 } 993 } 994 } 995 } 996 }; 997 998 static const imc_t imc_chanoff_underflow = { 999 .imc_gen = IMC_GEN_SANDY, 1000 .imc_nsockets = 1, 1001 .imc_sockets[0] = { 1002 .isock_valid = IMC_SOCKET_V_VALID, 1003 .isock_sad = { 1004 .isad_flags = 0, 1005 .isad_valid = IMC_SAD_V_VALID, 1006 .isad_tolm = 0x80000000, /* 2 GiB */ 1007 .isad_tohm = 0x280000000ULL, /* 10 GiB */ 1008 .isad_nrules = 10, 1009 .isad_rules[0] = { 1010 .isr_enable = B_TRUE, 1011 .isr_limit = 0x80000000, 1012 .isr_imode = IMC_SAD_IMODE_8t6, 1013 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 1014 .isr_targets = { 0, 0, 0, 0, 0, 0, 0, 0 } 1015 }, 1016 .isad_rules[1] = { 1017 .isr_enable = B_TRUE, 1018 .isr_limit = 0x280000000ULL, 1019 .isr_imode = IMC_SAD_IMODE_8t6, 1020 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 1021 .isr_targets = { 0, 0, 0, 0, 0, 0, 0, 0 } 1022 } 1023 }, 1024 .isock_ntad = 1, 1025 .isock_tad[0] = { 1026 .itad_flags = 0, 1027 .itad_nrules = 12, 1028 .itad_rules[0] = { 1029 .itr_base = 0x0, 1030 .itr_limit = 0x80000000, 1031 .itr_sock_way = 1, 1032 .itr_chan_way = 1, 1033 .itr_sock_gran = IMC_TAD_GRAN_64B, 1034 .itr_chan_gran = IMC_TAD_GRAN_64B, 1035 .itr_ntargets = 4, 1036 .itr_targets = { 0, 0, 0, 0 } 1037 }, 1038 .itad_rules[1] = { 1039 .itr_base = 0x80000000, 1040 .itr_limit = 0x280000000ULL, 1041 .itr_sock_way = 1, 1042 .itr_chan_way = 1, 1043 .itr_sock_gran = IMC_TAD_GRAN_64B, 1044 .itr_chan_gran = IMC_TAD_GRAN_64B, 1045 .itr_ntargets = 4, 1046 .itr_targets = { 0, 0, 0, 0 } 1047 } 1048 }, 1049 .isock_nimc = 1, 1050 .isock_imcs[0] = { 1051 .icn_nchannels = 1, 1052 .icn_dimm_type = IMC_DIMM_DDR3, 1053 .icn_ecc = B_TRUE, 1054 .icn_lockstep = B_FALSE, 1055 .icn_closed = B_FALSE, 1056 .icn_channels[0] = { 1057 .ich_ndimms = 1, 1058 .ich_dimms[0] = { 1059 .idimm_present = B_TRUE, 1060 .idimm_nbanks = 3, 1061 .idimm_width = 8, 1062 .idimm_density = 2, 1063 .idimm_nranks = 2, 1064 .idimm_nrows = 14, 1065 .idimm_ncolumns = 10, 1066 .idimm_size = 0x80000000 1067 }, 1068 .ich_ntad_offsets = 12, 1069 .ich_tad_offsets = { 0x1000000000ULL, 1070 0x1000000000ULL, 1071 0x1000000000ULL, 1072 0x1000000000ULL, 1073 0x1000000000ULL, 1074 0x1000000000ULL, 1075 0x1000000000ULL, 1076 0x1000000000ULL, 1077 0x1000000000ULL, 1078 0x1000000000ULL, 1079 0x1000000000ULL, 1080 0x1000000000ULL 1081 }, 1082 .ich_nrankileaves = 8, 1083 .ich_rankileaves[0] = { 1084 .irle_enabled = B_TRUE, 1085 .irle_nways = 2, 1086 .irle_nwaysbits = 1, 1087 .irle_limit = 0x200000000ULL, 1088 .irle_nentries = 5, 1089 .irle_entries[0] = { 0x0, 0x0 }, 1090 .irle_entries[1] = { 0x1, 0x0 } 1091 } 1092 } 1093 } 1094 } 1095 }; 1096 1097 static const imc_t imc_riroff_underflow = { 1098 .imc_gen = IMC_GEN_SANDY, 1099 .imc_nsockets = 1, 1100 .imc_sockets[0] = { 1101 .isock_valid = IMC_SOCKET_V_VALID, 1102 .isock_sad = { 1103 .isad_flags = 0, 1104 .isad_valid = IMC_SAD_V_VALID, 1105 .isad_tolm = 0x80000000, /* 2 GiB */ 1106 .isad_tohm = 0x280000000ULL, /* 10 GiB */ 1107 .isad_nrules = 10, 1108 .isad_rules[0] = { 1109 .isr_enable = B_TRUE, 1110 .isr_limit = 0x80000000, 1111 .isr_imode = IMC_SAD_IMODE_8t6, 1112 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 1113 .isr_targets = { 0, 0, 0, 0, 0, 0, 0, 0 } 1114 }, 1115 .isad_rules[1] = { 1116 .isr_enable = B_TRUE, 1117 .isr_limit = 0x280000000ULL, 1118 .isr_imode = IMC_SAD_IMODE_8t6, 1119 .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 1120 .isr_targets = { 0, 0, 0, 0, 0, 0, 0, 0 } 1121 } 1122 }, 1123 .isock_ntad = 1, 1124 .isock_tad[0] = { 1125 .itad_flags = 0, 1126 .itad_nrules = 12, 1127 .itad_rules[0] = { 1128 .itr_base = 0x0, 1129 .itr_limit = 0x80000000, 1130 .itr_sock_way = 1, 1131 .itr_chan_way = 1, 1132 .itr_sock_gran = IMC_TAD_GRAN_64B, 1133 .itr_chan_gran = IMC_TAD_GRAN_64B, 1134 .itr_ntargets = 4, 1135 .itr_targets = { 0, 0, 0, 0 } 1136 }, 1137 .itad_rules[1] = { 1138 .itr_base = 0x80000000, 1139 .itr_limit = 0x280000000ULL, 1140 .itr_sock_way = 1, 1141 .itr_chan_way = 1, 1142 .itr_sock_gran = IMC_TAD_GRAN_64B, 1143 .itr_chan_gran = IMC_TAD_GRAN_64B, 1144 .itr_ntargets = 4, 1145 .itr_targets = { 0, 0, 0, 0 } 1146 } 1147 }, 1148 .isock_nimc = 1, 1149 .isock_imcs[0] = { 1150 .icn_nchannels = 1, 1151 .icn_dimm_type = IMC_DIMM_DDR3, 1152 .icn_ecc = B_TRUE, 1153 .icn_lockstep = B_FALSE, 1154 .icn_closed = B_FALSE, 1155 .icn_channels[0] = { 1156 .ich_ndimms = 1, 1157 .ich_dimms[0] = { 1158 .idimm_present = B_TRUE, 1159 .idimm_nbanks = 3, 1160 .idimm_width = 8, 1161 .idimm_density = 2, 1162 .idimm_nranks = 2, 1163 .idimm_nrows = 14, 1164 .idimm_ncolumns = 10, 1165 .idimm_size = 0x80000000 1166 }, 1167 .ich_ntad_offsets = 12, 1168 .ich_tad_offsets = { 0, 0x80000000, 0, 0, 0, 0, 1169 0, 0, 0, 0, 0 }, 1170 .ich_nrankileaves = 8, 1171 .ich_rankileaves[0] = { 1172 .irle_enabled = B_TRUE, 1173 .irle_nways = 2, 1174 .irle_nwaysbits = 1, 1175 .irle_limit = 0x200000000ULL, 1176 .irle_nentries = 5, 1177 .irle_entries[0] = { 0x0, 1178 0x100000000000ULL }, 1179 .irle_entries[1] = { 0x1, 1180 0x100000000000ULL } 1181 } 1182 } 1183 } 1184 } 1185 }; 1186 1187 const imc_test_case_t imc_test_fail[] = { { 1188 .itc_desc = "Bad Socket data (1)", 1189 .itc_imc = &imc_badsock, 1190 .itc_pa = 0x34, 1191 .itc_pass = B_FALSE, 1192 .itc_fail = IMC_DECODE_F_BAD_SOCKET 1193 }, { 1194 .itc_desc = "Bad Socket data (2)", 1195 .itc_imc = &imc_badsock, 1196 .itc_pa = 0x7fffff, 1197 .itc_pass = B_FALSE, 1198 .itc_fail = IMC_DECODE_F_BAD_SOCKET 1199 }, { 1200 .itc_desc = "Bad Socket data (3)", 1201 .itc_imc = &imc_badsock, 1202 .itc_pa = 0x123456789ULL, 1203 .itc_pass = B_FALSE, 1204 .itc_fail = IMC_DECODE_F_BAD_SOCKET 1205 }, { 1206 .itc_desc = "Bad SAD data (1)", 1207 .itc_imc = &imc_invalid_sad, 1208 .itc_pa = 0x34, 1209 .itc_pass = B_FALSE, 1210 .itc_fail = IMC_DECODE_F_BAD_SAD 1211 }, { 1212 .itc_desc = "Bad SAD data (2)", 1213 .itc_imc = &imc_invalid_sad, 1214 .itc_pa = 0x7fffff, 1215 .itc_pass = B_FALSE, 1216 .itc_fail = IMC_DECODE_F_BAD_SAD 1217 }, { 1218 .itc_desc = "Bad SAD data (3)", 1219 .itc_imc = &imc_invalid_sad, 1220 .itc_pa = 0x123456789ULL, 1221 .itc_pass = B_FALSE, 1222 .itc_fail = IMC_DECODE_F_BAD_SAD 1223 }, { 1224 .itc_desc = "Bad SAD rule (1)", 1225 .itc_imc = &imc_invalid_sad_rule, 1226 .itc_pa = 0x45, 1227 .itc_pass = B_FALSE, 1228 .itc_fail = IMC_DECODE_F_NO_SAD_RULE 1229 }, { 1230 .itc_desc = "Bad SAD rule (2)", 1231 .itc_imc = &imc_invalid_sad_rule, 1232 .itc_pa = 0x7fffff, 1233 .itc_pass = B_FALSE, 1234 .itc_fail = IMC_DECODE_F_NO_SAD_RULE 1235 }, { 1236 .itc_desc = "Bad SAD rule (3)", 1237 .itc_imc = &imc_invalid_sad_rule, 1238 .itc_pa = 0x123456789ULL, 1239 .itc_pass = B_FALSE, 1240 .itc_fail = IMC_DECODE_F_NO_SAD_RULE 1241 }, { 1242 .itc_desc = "Bad SAD interleave (1)", 1243 .itc_imc = &imc_invalid_sad_interleave, 1244 .itc_pa = 0x45, 1245 .itc_pass = B_FALSE, 1246 .itc_fail = IMC_DECODE_F_BAD_SAD_INTERLEAVE 1247 }, { 1248 .itc_desc = "Bad SAD interleave (2)", 1249 .itc_imc = &imc_invalid_sad_interleave, 1250 .itc_pa = 0x7fffff, 1251 .itc_pass = B_FALSE, 1252 .itc_fail = IMC_DECODE_F_BAD_SAD_INTERLEAVE 1253 }, { 1254 .itc_desc = "Bad SAD interleave (3)", 1255 .itc_imc = &imc_invalid_sad_interleave, 1256 .itc_pa = 0x123456789ULL, 1257 .itc_pass = B_FALSE, 1258 .itc_fail = IMC_DECODE_F_BAD_SAD_INTERLEAVE 1259 }, { 1260 .itc_desc = "Bad SAD TAD target (1)", 1261 .itc_imc = &imc_invalid_sad_target, 1262 .itc_pa = 0x45, 1263 .itc_pass = B_FALSE, 1264 .itc_fail = IMC_DECODE_F_SAD_BAD_SOCKET 1265 }, { 1266 .itc_desc = "Bad SAD TAD target (2)", 1267 .itc_imc = &imc_invalid_sad_target, 1268 .itc_pa = 0x7fffff, 1269 .itc_pass = B_FALSE, 1270 .itc_fail = IMC_DECODE_F_SAD_BAD_SOCKET 1271 }, { 1272 .itc_desc = "Bad SAD TAD target (3)", 1273 .itc_imc = &imc_invalid_sad_target, 1274 .itc_pa = 0x123456789ULL, 1275 .itc_pass = B_FALSE, 1276 .itc_fail = IMC_DECODE_F_SAD_BAD_TAD 1277 }, { 1278 .itc_desc = "Bad TAD rule (1)", 1279 .itc_imc = &imc_bad_tad_rule, 1280 .itc_pa = 0x45, 1281 .itc_pass = B_FALSE, 1282 .itc_fail = IMC_DECODE_F_NO_TAD_RULE 1283 }, { 1284 .itc_desc = "Bad TAD rule (2)", 1285 .itc_imc = &imc_bad_tad_rule, 1286 .itc_pa = 0x7fffff, 1287 .itc_pass = B_FALSE, 1288 .itc_fail = IMC_DECODE_F_NO_TAD_RULE 1289 }, { 1290 .itc_desc = "Bad TAD rule (3)", 1291 .itc_imc = &imc_bad_tad_rule, 1292 .itc_pa = 0x123456789ULL, 1293 .itc_pass = B_FALSE, 1294 .itc_fail = IMC_DECODE_F_NO_TAD_RULE 1295 }, { 1296 .itc_desc = "Unsupported 3 way interleave (1)", 1297 .itc_imc = &imc_bad_tad_3way, 1298 .itc_pa = 0x45, 1299 .itc_pass = B_FALSE, 1300 .itc_fail = IMC_DECODE_F_TAD_3_ILEAVE 1301 }, { 1302 .itc_desc = "Unsupported 3 way interleave (2)", 1303 .itc_imc = &imc_bad_tad_3way, 1304 .itc_pa = 0x7fffff, 1305 .itc_pass = B_FALSE, 1306 .itc_fail = IMC_DECODE_F_TAD_3_ILEAVE 1307 }, { 1308 .itc_desc = "Unsupported 3 way interleave (3)", 1309 .itc_imc = &imc_bad_tad_3way, 1310 .itc_pa = 0x123456789ULL, 1311 .itc_pass = B_FALSE, 1312 .itc_fail = IMC_DECODE_F_TAD_3_ILEAVE 1313 }, { 1314 .itc_desc = "Bad TAD target index (1)", 1315 .itc_imc = &imc_bad_tad_target, 1316 .itc_pa = 0x45, 1317 .itc_pass = B_FALSE, 1318 .itc_fail = IMC_DECODE_F_TAD_BAD_TARGET_INDEX 1319 }, { 1320 .itc_desc = "Bad TAD target index (2)", 1321 .itc_imc = &imc_bad_tad_target, 1322 .itc_pa = 0x7fffff, 1323 .itc_pass = B_FALSE, 1324 .itc_fail = IMC_DECODE_F_TAD_BAD_TARGET_INDEX 1325 }, { 1326 .itc_desc = "Bad TAD target index (3)", 1327 .itc_imc = &imc_bad_tad_target, 1328 .itc_pa = 0x123456789ULL, 1329 .itc_pass = B_FALSE, 1330 .itc_fail = IMC_DECODE_F_TAD_BAD_TARGET_INDEX 1331 }, { 1332 .itc_desc = "Bad TAD target channel (1)", 1333 .itc_imc = &imc_bad_tad_channelid, 1334 .itc_pa = 0x45, 1335 .itc_pass = B_FALSE, 1336 .itc_fail = IMC_DECODE_F_BAD_CHANNEL_ID 1337 }, { 1338 .itc_desc = "Bad TAD target channel (2)", 1339 .itc_imc = &imc_bad_tad_channelid, 1340 .itc_pa = 0x7fffff, 1341 .itc_pass = B_FALSE, 1342 .itc_fail = IMC_DECODE_F_BAD_CHANNEL_ID 1343 }, { 1344 .itc_desc = "Bad TAD target channel (3)", 1345 .itc_imc = &imc_bad_tad_channelid, 1346 .itc_pa = 0x123456789ULL, 1347 .itc_pass = B_FALSE, 1348 .itc_fail = IMC_DECODE_F_BAD_CHANNEL_ID 1349 }, { 1350 .itc_desc = "Bad channel offset target (1)", 1351 .itc_imc = &imc_bad_channel_offset, 1352 .itc_pa = 0x45, 1353 .itc_pass = B_FALSE, 1354 .itc_fail = IMC_DECODE_F_BAD_CHANNEL_TAD_OFFSET 1355 }, { 1356 .itc_desc = "Bad channel offset target (2)", 1357 .itc_imc = &imc_bad_channel_offset, 1358 .itc_pa = 0x7fffff, 1359 .itc_pass = B_FALSE, 1360 .itc_fail = IMC_DECODE_F_BAD_CHANNEL_TAD_OFFSET 1361 }, { 1362 .itc_desc = "Bad channel offset target (3)", 1363 .itc_imc = &imc_bad_channel_offset, 1364 .itc_pa = 0x123456789ULL, 1365 .itc_pass = B_FALSE, 1366 .itc_fail = IMC_DECODE_F_BAD_CHANNEL_TAD_OFFSET 1367 }, { 1368 .itc_desc = "Bad RIR rule (1)", 1369 .itc_imc = &imc_bad_rir_rule, 1370 .itc_pa = 0x45, 1371 .itc_pass = B_FALSE, 1372 .itc_fail = IMC_DECODE_F_NO_RIR_RULE 1373 }, { 1374 .itc_desc = "Bad RIR rule (2)", 1375 .itc_imc = &imc_bad_rir_rule, 1376 .itc_pa = 0x7fffff, 1377 .itc_pass = B_FALSE, 1378 .itc_fail = IMC_DECODE_F_NO_RIR_RULE 1379 }, { 1380 .itc_desc = "Bad RIR rule (3)", 1381 .itc_pa = 0x123456789ULL, 1382 .itc_imc = &imc_bad_rir_rule, 1383 .itc_fail = IMC_DECODE_F_NO_RIR_RULE 1384 }, { 1385 .itc_desc = "Bad RIR interleave target (1)", 1386 .itc_imc = &imc_bad_rir_ileave, 1387 .itc_pa = 0x45, 1388 .itc_pass = B_FALSE, 1389 .itc_fail = IMC_DECODE_F_BAD_RIR_ILEAVE_TARGET 1390 }, { 1391 .itc_desc = "Bad RIR interleave target (2)", 1392 .itc_imc = &imc_bad_rir_ileave, 1393 .itc_pa = 0x7fffff, 1394 .itc_pass = B_FALSE, 1395 .itc_fail = IMC_DECODE_F_BAD_RIR_ILEAVE_TARGET 1396 }, { 1397 .itc_desc = "Bad RIR interleave target (3)", 1398 .itc_imc = &imc_bad_rir_ileave, 1399 .itc_pa = 0x123456789ULL, 1400 .itc_pass = B_FALSE, 1401 .itc_fail = IMC_DECODE_F_BAD_RIR_ILEAVE_TARGET 1402 }, { 1403 .itc_desc = "Bad RIR DIMM target (1)", 1404 .itc_imc = &imc_bad_dimm_index, 1405 .itc_pa = 0x45, 1406 .itc_pass = B_FALSE, 1407 .itc_fail = IMC_DECODE_F_BAD_DIMM_INDEX 1408 }, { 1409 .itc_desc = "Bad RIR DIMM target (2)", 1410 .itc_imc = &imc_bad_dimm_index, 1411 .itc_pa = 0x7fffff, 1412 .itc_pass = B_FALSE, 1413 .itc_fail = IMC_DECODE_F_BAD_DIMM_INDEX 1414 }, { 1415 .itc_desc = "Bad RIR DIMM target (3)", 1416 .itc_imc = &imc_bad_dimm_index, 1417 .itc_pa = 0x123456789ULL, 1418 .itc_pass = B_FALSE, 1419 .itc_fail = IMC_DECODE_F_BAD_DIMM_INDEX 1420 }, { 1421 .itc_desc = "Bad RIR DIMM target (1)", 1422 .itc_imc = &imc_missing_dimm, 1423 .itc_pa = 0x45, 1424 .itc_pass = B_FALSE, 1425 .itc_fail = IMC_DECODE_F_DIMM_NOT_PRESENT 1426 }, { 1427 .itc_desc = "Bad RIR DIMM target (2)", 1428 .itc_imc = &imc_missing_dimm, 1429 .itc_pa = 0x7fffff, 1430 .itc_pass = B_FALSE, 1431 .itc_fail = IMC_DECODE_F_DIMM_NOT_PRESENT 1432 }, { 1433 .itc_desc = "Bad RIR DIMM target (3)", 1434 .itc_imc = &imc_missing_dimm, 1435 .itc_pa = 0x123456789ULL, 1436 .itc_pass = B_FALSE, 1437 .itc_fail = IMC_DECODE_F_DIMM_NOT_PRESENT 1438 }, { 1439 .itc_desc = "Bad RIR rank target (1)", 1440 .itc_imc = &imc_bad_rank_index, 1441 .itc_pa = 0x45, 1442 .itc_pass = B_FALSE, 1443 .itc_fail = IMC_DECODE_F_BAD_DIMM_RANK 1444 }, { 1445 .itc_desc = "Bad RIR rank target (2)", 1446 .itc_imc = &imc_bad_rank_index, 1447 .itc_pa = 0x7fffff, 1448 .itc_pass = B_FALSE, 1449 .itc_fail = IMC_DECODE_F_BAD_DIMM_RANK 1450 }, { 1451 .itc_desc = "Bad RIR rank target (3)", 1452 .itc_imc = &imc_bad_rank_index, 1453 .itc_pa = 0x123456789ULL, 1454 .itc_pass = B_FALSE, 1455 .itc_fail = IMC_DECODE_F_BAD_DIMM_RANK 1456 }, { 1457 .itc_desc = "Bad channel offset underflow (1)", 1458 .itc_imc = &imc_chanoff_underflow, 1459 .itc_pa = 0x45, 1460 .itc_pass = B_FALSE, 1461 .itc_fail = IMC_DECODE_F_CHANOFF_UNDERFLOW 1462 }, { 1463 .itc_desc = "Bad channel offset underflow (2)", 1464 .itc_imc = &imc_chanoff_underflow, 1465 .itc_pa = 0x7fffff, 1466 .itc_pass = B_FALSE, 1467 .itc_fail = IMC_DECODE_F_CHANOFF_UNDERFLOW 1468 }, { 1469 .itc_desc = "Bad channel offset underflow (3)", 1470 .itc_imc = &imc_chanoff_underflow, 1471 .itc_pa = 0x123456789ULL, 1472 .itc_pass = B_FALSE, 1473 .itc_fail = IMC_DECODE_F_CHANOFF_UNDERFLOW 1474 }, { 1475 .itc_desc = "Bad rank offset underflow (1)", 1476 .itc_imc = &imc_riroff_underflow, 1477 .itc_pa = 0x45, 1478 .itc_pass = B_FALSE, 1479 .itc_fail = IMC_DECODE_F_RANKOFF_UNDERFLOW 1480 }, { 1481 .itc_desc = "Bad rank offset underflow (2)", 1482 .itc_imc = &imc_riroff_underflow, 1483 .itc_pa = 0x7fffff, 1484 .itc_pass = B_FALSE, 1485 .itc_fail = IMC_DECODE_F_RANKOFF_UNDERFLOW 1486 }, { 1487 .itc_desc = "Bad rank offset underflow (3)", 1488 .itc_imc = &imc_riroff_underflow, 1489 .itc_pa = 0x123456789ULL, 1490 .itc_pass = B_FALSE, 1491 .itc_fail = IMC_DECODE_F_RANKOFF_UNDERFLOW 1492 }, { 1493 .itc_desc = NULL 1494 } }; 1495