1*eb00b1c8SRobert Mustacchi /* 2*eb00b1c8SRobert Mustacchi * This file and its contents are supplied under the terms of the 3*eb00b1c8SRobert Mustacchi * Common Development and Distribution License ("CDDL"), version 1.0. 4*eb00b1c8SRobert Mustacchi * You may only use this file in accordance with the terms of version 5*eb00b1c8SRobert Mustacchi * 1.0 of the CDDL. 6*eb00b1c8SRobert Mustacchi * 7*eb00b1c8SRobert Mustacchi * A full copy of the text of the CDDL should have accompanied this 8*eb00b1c8SRobert Mustacchi * source. A copy of the CDDL is also available via the Internet at 9*eb00b1c8SRobert Mustacchi * http://www.illumos.org/license/CDDL. 10*eb00b1c8SRobert Mustacchi */ 11*eb00b1c8SRobert Mustacchi 12*eb00b1c8SRobert Mustacchi /* 13*eb00b1c8SRobert Mustacchi * Copyright 2019 Joyent, Inc. 14*eb00b1c8SRobert Mustacchi */ 15*eb00b1c8SRobert Mustacchi 16*eb00b1c8SRobert Mustacchi #include "imc_test.h" 17*eb00b1c8SRobert Mustacchi 18*eb00b1c8SRobert Mustacchi /* 19*eb00b1c8SRobert Mustacchi * This represents a basic configuration with a single socket, channel, and 20*eb00b1c8SRobert Mustacchi * DIMM that is 2 GiB in size. This entirely punts on the fact that the legacy 21*eb00b1c8SRobert Mustacchi * ranges overlap here. 22*eb00b1c8SRobert Mustacchi */ 23*eb00b1c8SRobert Mustacchi static const imc_t imc_basic_snb = { 24*eb00b1c8SRobert Mustacchi .imc_gen = IMC_GEN_SANDY, 25*eb00b1c8SRobert Mustacchi .imc_nsockets = 1, 26*eb00b1c8SRobert Mustacchi .imc_sockets[0] = { 27*eb00b1c8SRobert Mustacchi .isock_valid = IMC_SOCKET_V_VALID, 28*eb00b1c8SRobert Mustacchi .isock_sad = { 29*eb00b1c8SRobert Mustacchi .isad_flags = 0, 30*eb00b1c8SRobert Mustacchi .isad_valid = IMC_SAD_V_VALID, 31*eb00b1c8SRobert Mustacchi .isad_tolm = 0x80000000, 32*eb00b1c8SRobert Mustacchi .isad_tohm = 0, 33*eb00b1c8SRobert Mustacchi .isad_nrules = 10, 34*eb00b1c8SRobert Mustacchi .isad_rules[0] = { 35*eb00b1c8SRobert Mustacchi .isr_enable = B_TRUE, 36*eb00b1c8SRobert Mustacchi .isr_limit = 0x80000000, 37*eb00b1c8SRobert Mustacchi .isr_imode = IMC_SAD_IMODE_8t6, 38*eb00b1c8SRobert Mustacchi .isr_ntargets = IMC_MAX_SAD_INTERLEAVE, 39*eb00b1c8SRobert Mustacchi .isr_targets = { 0, 0, 0, 0, 0, 0, 0, 0 } 40*eb00b1c8SRobert Mustacchi } 41*eb00b1c8SRobert Mustacchi }, 42*eb00b1c8SRobert Mustacchi .isock_ntad = 1, 43*eb00b1c8SRobert Mustacchi .isock_tad[0] = { 44*eb00b1c8SRobert Mustacchi .itad_flags = 0, 45*eb00b1c8SRobert Mustacchi .itad_nrules = 12, 46*eb00b1c8SRobert Mustacchi .itad_rules[0] = { 47*eb00b1c8SRobert Mustacchi .itr_base = 0x0, 48*eb00b1c8SRobert Mustacchi .itr_limit = 0x80000000, 49*eb00b1c8SRobert Mustacchi .itr_sock_way = 1, 50*eb00b1c8SRobert Mustacchi .itr_chan_way = 1, 51*eb00b1c8SRobert Mustacchi .itr_sock_gran = IMC_TAD_GRAN_64B, 52*eb00b1c8SRobert Mustacchi .itr_chan_gran = IMC_TAD_GRAN_64B, 53*eb00b1c8SRobert Mustacchi .itr_ntargets = 4, 54*eb00b1c8SRobert Mustacchi .itr_targets = { 0, 0, 0, 0 } 55*eb00b1c8SRobert Mustacchi } 56*eb00b1c8SRobert Mustacchi }, 57*eb00b1c8SRobert Mustacchi .isock_nimc = 1, 58*eb00b1c8SRobert Mustacchi .isock_imcs[0] = { 59*eb00b1c8SRobert Mustacchi .icn_nchannels = 1, 60*eb00b1c8SRobert Mustacchi .icn_dimm_type = IMC_DIMM_DDR3, 61*eb00b1c8SRobert Mustacchi .icn_ecc = B_TRUE, 62*eb00b1c8SRobert Mustacchi .icn_lockstep = B_FALSE, 63*eb00b1c8SRobert Mustacchi .icn_closed = B_TRUE, 64*eb00b1c8SRobert Mustacchi .icn_channels[0] = { 65*eb00b1c8SRobert Mustacchi .ich_ndimms = 1, 66*eb00b1c8SRobert Mustacchi .ich_dimms[0] = { 67*eb00b1c8SRobert Mustacchi .idimm_present = B_TRUE, 68*eb00b1c8SRobert Mustacchi .idimm_nbanks = 3, 69*eb00b1c8SRobert Mustacchi .idimm_width = 8, 70*eb00b1c8SRobert Mustacchi .idimm_density = 2, 71*eb00b1c8SRobert Mustacchi .idimm_nranks = 2, 72*eb00b1c8SRobert Mustacchi .idimm_nrows = 14, 73*eb00b1c8SRobert Mustacchi .idimm_ncolumns = 10, 74*eb00b1c8SRobert Mustacchi .idimm_size = 0x80000000 75*eb00b1c8SRobert Mustacchi }, 76*eb00b1c8SRobert Mustacchi .ich_ntad_offsets = 12, 77*eb00b1c8SRobert Mustacchi .ich_tad_offsets = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 78*eb00b1c8SRobert Mustacchi 0, 0 }, 79*eb00b1c8SRobert Mustacchi .ich_nrankileaves = 8, 80*eb00b1c8SRobert Mustacchi .ich_rankileaves[0] = { 81*eb00b1c8SRobert Mustacchi .irle_enabled = B_TRUE, 82*eb00b1c8SRobert Mustacchi .irle_nways = 2, 83*eb00b1c8SRobert Mustacchi .irle_nwaysbits = 1, 84*eb00b1c8SRobert Mustacchi .irle_limit = 0x80000000, 85*eb00b1c8SRobert Mustacchi .irle_nentries = 5, 86*eb00b1c8SRobert Mustacchi .irle_entries[0] = { 0x0, 0x0 }, 87*eb00b1c8SRobert Mustacchi .irle_entries[1] = { 0x1, 0x0 } 88*eb00b1c8SRobert Mustacchi } 89*eb00b1c8SRobert Mustacchi } 90*eb00b1c8SRobert Mustacchi } 91*eb00b1c8SRobert Mustacchi } 92*eb00b1c8SRobert Mustacchi }; 93*eb00b1c8SRobert Mustacchi 94*eb00b1c8SRobert Mustacchi const imc_test_case_t imc_test_basics[] = { { 95*eb00b1c8SRobert Mustacchi .itc_desc = "decode basic single socket/channel/DIMM, dual rank (1)", 96*eb00b1c8SRobert Mustacchi .itc_imc = &imc_basic_snb, 97*eb00b1c8SRobert Mustacchi .itc_pa = 0x0, 98*eb00b1c8SRobert Mustacchi .itc_pass = B_TRUE, 99*eb00b1c8SRobert Mustacchi .itc_nodeid = 0, 100*eb00b1c8SRobert Mustacchi .itc_tadid = 0, 101*eb00b1c8SRobert Mustacchi .itc_channelid = 0, 102*eb00b1c8SRobert Mustacchi .itc_chanaddr = 0, 103*eb00b1c8SRobert Mustacchi .itc_dimmid = 0, 104*eb00b1c8SRobert Mustacchi .itc_rankid = 0, 105*eb00b1c8SRobert Mustacchi .itc_rankaddr = 0 106*eb00b1c8SRobert Mustacchi }, { 107*eb00b1c8SRobert Mustacchi .itc_desc = "decode basic single socket/channel/DIMM, dual rank (2)", 108*eb00b1c8SRobert Mustacchi .itc_imc = &imc_basic_snb, 109*eb00b1c8SRobert Mustacchi .itc_pa = 0x1000, 110*eb00b1c8SRobert Mustacchi .itc_pass = B_TRUE, 111*eb00b1c8SRobert Mustacchi .itc_nodeid = 0, 112*eb00b1c8SRobert Mustacchi .itc_tadid = 0, 113*eb00b1c8SRobert Mustacchi .itc_channelid = 0, 114*eb00b1c8SRobert Mustacchi .itc_chanaddr = 0x1000, 115*eb00b1c8SRobert Mustacchi .itc_dimmid = 0, 116*eb00b1c8SRobert Mustacchi .itc_rankid = 0, 117*eb00b1c8SRobert Mustacchi .itc_rankaddr = 0x800 118*eb00b1c8SRobert Mustacchi }, { 119*eb00b1c8SRobert Mustacchi .itc_desc = "decode basic single socket/channel/DIMM, dual rank (3)", 120*eb00b1c8SRobert Mustacchi .itc_imc = &imc_basic_snb, 121*eb00b1c8SRobert Mustacchi .itc_pa = 0x7fffffff, 122*eb00b1c8SRobert Mustacchi .itc_pass = B_TRUE, 123*eb00b1c8SRobert Mustacchi .itc_nodeid = 0, 124*eb00b1c8SRobert Mustacchi .itc_tadid = 0, 125*eb00b1c8SRobert Mustacchi .itc_channelid = 0, 126*eb00b1c8SRobert Mustacchi .itc_chanaddr = 0x7fffffff, 127*eb00b1c8SRobert Mustacchi .itc_dimmid = 0, 128*eb00b1c8SRobert Mustacchi .itc_rankid = 1, 129*eb00b1c8SRobert Mustacchi .itc_rankaddr = 0x3fffffff, 130*eb00b1c8SRobert Mustacchi }, { 131*eb00b1c8SRobert Mustacchi .itc_desc = NULL 132*eb00b1c8SRobert Mustacchi } }; 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