1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2023 Oxide Computer Company 14 */ 15 16 #ifndef _TEST_DEFS_H_ 17 #define _TEST_DEFS_H_ 18 19 #define IOP_PMTMR 0x408 20 #define IOP_ATPIT_C0 0x40 21 #define IOP_ATPIT_CMD 0x43 22 #define IOP_ATPIC_MCMD 0x20 23 #define IOP_ATPIC_MDATA 0x21 24 #define IOP_ATPIC_SCMD 0xa0 25 #define IOP_ATPIC_SDATA 0xa1 26 #define IOP_RTC_ADDR 0x70 27 #define IOP_RTC_DATA 0x71 28 29 #define MMIO_HPET_BASE 0xfed00000UL 30 #define MMIO_LAPIC_BASE 0xfee00000UL 31 32 #define PMTMR_FREQ 3579545 33 #define PMTMR_TARGET_TICKS (PMTMR_FREQ / 10) 34 35 #define HPET_FREQ (1 << 24) 36 #define HPET_TARGET_TICKS (HPET_FREQ / 10) 37 38 #define LAPIC_FREQ (128 * 1024 * 1024) 39 #define LAPIC_TARGET_TICKS (LAPIC_FREQ / 50) 40 41 #define ATPIT_FREQ 1193182 42 #define ATPIT_TARGET_TICKS (ATPIT_FREQ / 50) 43 44 #define TSC_TARGET_WRVAL 500000000000 45 46 #endif /* _TEST_DEFS_H_ */ 47