1*bbf21555SRichard Lowe.\" 2*bbf21555SRichard Lowe.\" This file and its contents are supplied under the terms of the 3*bbf21555SRichard Lowe.\" Common Development and Distribution License ("CDDL"), version 1.0. 4*bbf21555SRichard Lowe.\" You may only use this file in accordance with the terms of version 5*bbf21555SRichard Lowe.\" 1.0 of the CDDL. 6*bbf21555SRichard Lowe.\" 7*bbf21555SRichard Lowe.\" A full copy of the text of the CDDL should have accompanied this 8*bbf21555SRichard Lowe.\" source. A copy of the CDDL is also available via the Internet at 9*bbf21555SRichard Lowe.\" http://www.illumos.org/license/CDDL. 10*bbf21555SRichard Lowe.\" 11*bbf21555SRichard Lowe.\" 12*bbf21555SRichard Lowe.\" Copyright 2019 Joyent, Inc. 13*bbf21555SRichard Lowe.\" 14*bbf21555SRichard Lowe.Dd June 25, 2019 15*bbf21555SRichard Lowe.Dt IMC 4D 16*bbf21555SRichard Lowe.Os 17*bbf21555SRichard Lowe.Sh NAME 18*bbf21555SRichard Lowe.Nm imc 19*bbf21555SRichard Lowe.Nd Intel memory controller driver 20*bbf21555SRichard Lowe.Sh SYNOPSIS 21*bbf21555SRichard Lowe.Pa /dev/mc/mc* 22*bbf21555SRichard Lowe.Sh DESCRIPTION 23*bbf21555SRichard LoweThe 24*bbf21555SRichard Lowe.Nm 25*bbf21555SRichard Lowedriver interfaces with the memory controller found on certain 26*bbf21555SRichard Lowegenerations of Intel CPUs and provides a means for decoding physical 27*bbf21555SRichard Loweaddresses to the corresponding memory device. 28*bbf21555SRichard LoweThe 29*bbf21555SRichard Lowe.Nm 30*bbf21555SRichard Lowedriver plugs into the operating systems fault management framework 31*bbf21555SRichard Loweproviding additional details to the system about the memory topology and 32*bbf21555SRichard Lowethe ability to decode physical addresses into the corresponding portion 33*bbf21555SRichard Loweof the memory hierarchy. 34*bbf21555SRichard Lowe.Pp 35*bbf21555SRichard LoweThe 36*bbf21555SRichard Lowe.Nm 37*bbf21555SRichard Lowedriver is supported on the following Intel processors: 38*bbf21555SRichard Lowe.Bl -bullet -offset indent -width Sy 39*bbf21555SRichard Lowe.It 40*bbf21555SRichard LoweSandy Bridge E5 and E7 Xeon Processors 41*bbf21555SRichard Lowe.It 42*bbf21555SRichard LoweIvy Bridge E5 and E7 Xeon Processors 43*bbf21555SRichard Lowe.It 44*bbf21555SRichard LoweHaswell E5 and E7 Xeon Processors 45*bbf21555SRichard Lowe.It 46*bbf21555SRichard LoweBroadwell E5 and E7 Xeon Processors 47*bbf21555SRichard Lowe.It 48*bbf21555SRichard LoweSkylake Xeon Scalable Processors 49*bbf21555SRichard Lowe.It 50*bbf21555SRichard LoweCascade Lake Xeon Scalable Processors 51*bbf21555SRichard Lowe.It 52*bbf21555SRichard LoweBroadwell and Skylake Xeon-D processors 53*bbf21555SRichard Lowe.El 54*bbf21555SRichard Lowe.Pp 55*bbf21555SRichard LoweOther lines involving the above microarchitectures, such as Xeon E3 56*bbf21555SRichard Lowebranded processors, are not supported as they do not provide the 57*bbf21555SRichard Lowenecessary hardware support. 58*bbf21555SRichard Lowe.Pp 59*bbf21555SRichard LoweThe 60*bbf21555SRichard Lowe.Nm 61*bbf21555SRichard Lowedriver is a pseudo-device driver that amalgamates all of the different 62*bbf21555SRichard Lowe.Xr imcstub 4D 63*bbf21555SRichard Loweinstances into a coherent view. 64*bbf21555SRichard LoweThe 65*bbf21555SRichard Lowe.Xr imcstub 4D 66*bbf21555SRichard Lowedriver attaches to all of the different PCI devices that the processor 67*bbf21555SRichard Loweexposes. 68*bbf21555SRichard Lowe.Pp 69*bbf21555SRichard LoweOne challenge with the 70*bbf21555SRichard Lowe.Nm 71*bbf21555SRichard Lowedriver is the Intel Enhanced Machine Check Architecture v2 72*bbf21555SRichard Lowe.Pq EMCAv2 . 73*bbf21555SRichard LoweMany vendors use EMCAv2 to hide memory errors from the operating system. 74*bbf21555SRichard LoweSuch systems limit the effectiveness of the 75*bbf21555SRichard Lowe.Nm 76*bbf21555SRichard Lowedriver and the fault management architecture by hiding correctable and 77*bbf21555SRichard Loweuncorrectable DIMM errors from the operating system. 78*bbf21555SRichard Lowe.Pp 79*bbf21555SRichard LoweThe 80*bbf21555SRichard Lowe.Nm 81*bbf21555SRichard Lowedriver has a few limitations. 82*bbf21555SRichard LoweCurrently it does not always properly handle lockstep and mirroring 83*bbf21555SRichard Lowemode, particularly in variants that are common on Skylake and newer 84*bbf21555SRichard Lowesystems. 85*bbf21555SRichard LoweIt also does not properly handle cases where Intel Optane NVDIMMs are in 86*bbf21555SRichard Loweuse on the memory bus. 87*bbf21555SRichard Lowe.Sh ARCHITECTURE 88*bbf21555SRichard LoweThe 89*bbf21555SRichard Lowe.Nm 90*bbf21555SRichard Lowedriver is only supported on specific Intel 91*bbf21555SRichard Lowe.Sy x86 92*bbf21555SRichard Lowesystems. 93*bbf21555SRichard Lowe.Sh FILES 94*bbf21555SRichard Lowe.Bl -tag -width Pa 95*bbf21555SRichard Lowe.It Pa /platform/i86pc/kernel/drv/amd64/imc 96*bbf21555SRichard Lowe64-bit device driver (x86). 97*bbf21555SRichard Lowe.It Pa /platform/i86pc/kernel/drv/imc.conf 98*bbf21555SRichard LoweDriver configuration file. 99*bbf21555SRichard Lowe.El 100*bbf21555SRichard Lowe.Sh SEE ALSO 101*bbf21555SRichard Lowe.Xr imcstub 4D , 102*bbf21555SRichard Lowe.Xr fmadm 8 , 103*bbf21555SRichard Lowe.Xr fmdump 8 104