Copyright (c) 2009, Sun Microsystems, Inc. All Rights Reserved.
The contents of this file are subject to the terms of the Common Development and Distribution License (the "License"). You may not use this file except in compliance with the License.
You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE or http://www.opensolaris.org/os/licensing. See the License for the specific language governing permissions and limitations under the License.
When distributing Covered Code, include this CDDL HEADER in each file and include the License file at usr/src/OPENSOLARIS.LICENSE. If applicable, add the following below this CDDL HEADER, with the fields enclosed by brackets "[]" replaced with your own identifying information: Portions Copyright [yyyy] [name of copyright owner]
#include <atomic.h>
This collection of functions provides atomic memory operations. There are 8 different classes of atomic operations: atomic_add(3C)
These functions provide an atomic addition of a signed value to a variable.
These functions provide an atomic logical 'and' of a value to a variable.
These functions provide atomic bit setting and clearing within a variable.
These functions provide an atomic comparison of a value with a variable. If the comparison is equal, then swap in a new value for the variable, returning the old value of the variable in either case.
These functions provide an atomic decrement on a variable.
These functions provide an atomic increment on a variable.
These functions provide an atomic logical 'or' of a value to a variable.
These functions provide an atomic swap of a value with a variable, returning the old value of the variable.
See attributes(7) for descriptions of the following attributes:
ATTRIBUTE TYPE ATTRIBUTE VALUE |
Interface Stability Stable |
MT-Level MT-Safe |
atomic_add (3C), atomic_and (3C), atomic_bits (3C), atomic_cas (3C), atomic_dec (3C), atomic_inc (3C), atomic_or (3C), atomic_swap (3C), membar_ops (3C), attributes (7)
Atomic instructions ensure global visibility of atomically-modified variables on completion. In a relaxed store order system, this does not guarantee that the visibility of other variables will be synchronized with the completion of the atomic instruction. If such synchronization is required, memory barrier instructions must be used. See membar_ops(3C).
Atomic instructions can be expensive since they require synchronization to occur at a hardware level. This means they should be used with care to ensure that forcing hardware level synchronization occurs a minimum number of times. For example, if you have several variables that need to be incremented as a group, and each needs to be done atomically, then do so with a mutex lock protecting all of them being incremented rather than using the atomic_inc(3C) operation on each of them.