/usr/bin/make [-C directory] [-d] [-dd] [-D] [-DD] [-e]
 [-i] [-j maxjobs] [-k] [-m {serial | parallel}]
 [-n] [-p] [-P] [-q] [-r] [-s] [-S] [-t] [-V]
 [-f makefile]... [-K statefile]... [target]...
 [macro = value...]

/usr/bin/dmake [-C directory] [-d] [-dd] [-D] [-DD] [-e]
 [-i] [-j maxjobs] [-k] [-m {serial | parallel}]
 [-n] [-p] [-P] [-q] [-r] [-s] [-S] [-t] [-V]
 [-f makefile]... [-K statefile]... [target]...
 [macro = value...]

/usr/xpg4/bin/make [-d] [-dd] [-D] [-DD]
 [-e] [-i] [-j maxjobs] [-k] [-m {serial | parallel}]
 [-n] [-p] [-P] [-q] [-r] [-s] [-S] [-t] [-V]
 [-f makefile]... [target]... [macro = value...]

The make utility executes a list of shell commands associated with each target, typically to create or update a file of the same name. makefile contains entries that describe how to bring a target up to date with respect to those on which it depends, which are called dependencies. Since each dependency is a target, it can have dependencies of its own. Targets, dependencies, and sub-dependencies comprise a tree structure that make traces when deciding whether or not to rebuild a target.

The make utility recursively checks each target against its dependencies, beginning with the first target entry in makefile if no target argument is supplied on the command line. If, after processing all of its dependencies, a target file is found either to be missing, or to be older than any of its dependencies, make rebuilds it. Optionally with this version of make, a target can be treated as out-of-date when the commands used to generate it have changed since the last time the target was built.

To build a given target, make executes the list of commands, called a rule. This rule can be listed explicitly in the target's makefile entry, or it can be supplied implicitly by make.

If no target is specified on the command line, make uses the first target defined in makefile.

If a target has no makefile entry, or if its entry has no rule, make attempts to derive a rule by each of the following methods, in turn, until a suitable rule is found. Each method is described under Usage below.

If there is no makefile entry for a target, if no rule can be derived for building it, and if no file by that name is present, make issues an error message and halts.

The following options are supported: -C directory

The following operands are supported: target

The usage of make is described below:

When make first starts, it reads the MAKEFLAGS environment variable to obtain any of the following options specified present in its value: -C, -d, -D, -e, -i, -k, -n, -p, -q, -r, -s, -S, or -t. Due to the implementation of POSIX.2 (see POSIX.2(7), the MAKEFLAGS values contains a leading - character. The make utility then reads the command line for additional options, which also take effect.

Next, make reads in a default makefile that typically contains predefined macro definitions, target entries for implicit rules, and additional rules, such as the rule for retrieving SCCS files. If present, make uses the file make.rules in the current directory; otherwise it reads the file /usr/share/lib/make/make.rules, which contains the standard definitions and rules. Use the directive:

include /usr/share/lib/make/make.rules

in your local make.rules file to include them.

Next, make imports variables from the environment (unless the -e option is in effect), and treats them as defined macros. Because make uses the most recent definition it encounters, a macro definition in the makefile normally overrides an environment variable of the same name. When -e is in effect, however, environment variables are read in after all makefiles have been read. In that case, the environment variables take precedence over definitions in the makefile.

Next, make reads any makefiles you specify with -f, or one of makefile or Makefile as described above and then the state file, in the local directory if it exists. If the makefile contains a .KEEP_STATE_FILE target, then it reads the state file that follows the target. Refer to special target .KEEP_STATE_FILE for details.

Next (after reading the environment if -e is in effect), make reads in any macro definitions supplied as command line arguments. These override macro definitions in the makefile and the environment both, but only for the make command itself.

make exports environment variables, using the most recently defined value. Macro definitions supplied on the command line are not normally exported, unless the macro is also an environment variable.

make does not export macros defined in the makefile. If an environment variable is set, and a macro with the same name is defined on the command line, make exports its value as defined on the command line. Unless -e is in effect, macro definitions within the makefile take precedence over those imported from the environment.

The macros MAKEFLAGS, MAKE, SHELL, HOST_ARCH, HOST_MACH, and TARGET_MACH are special cases. See Special-Purpose Macros below for details.

A target entry has the following format:

 target [:|::] [dependency] ... [; command] ...
 [command]
 ...

The first line contains the name of a target, or a space-separated list of target names, terminated with a colon or double colon. If a list of targets is given, this is equivalent to having a separate entry of the same form for each target. The colon(s) can be followed by a dependency, or a dependency list. make checks this list before building the target. The dependency list can be terminated with a semicolon (;), which in turn can be followed by a single Bourne shell command. Subsequent lines in the target entry begin with a TAB and contain Bourne shell commands. These commands comprise the rule for building the target.

Shell commands can be continued across input lines by escaping the NEWLINE with a backslash (\e). The continuing line must also start with a TAB.

To rebuild a target, make expands macros, strips off initial TAB characters and either executes the command directly (if it contains no shell metacharacters), or passes each command line to a Bourne shell for execution.

The first non-empty line that does not begin with a TAB or # begins another target or macro definition.

Special characters are defined below.

{ }

When incorporated in a makefile, the following target names perform special-functions: .DEFAULT:

.MAKE_VERSION: VERSION-number

In this version of make, you can clear the definition of the following special targets by supplying entries for them with no dependencies and no rule:

.DEFAULT, .SCCS_GET, and .SUFFIXES

When the .KEEP_STATE: target is effective, make checks the command for building a target against the state file. If the command has changed since the last make run, make rebuilds the target.

When the .KEEP_STATE: target is effective, make reads reports from cpp(1) and other compilation processors for any "hidden" files, such as #include files. If the target is out of date with respect to any of these files, make rebuilds it.

Entries of the form

macro=value

define macros. macro is the name of the macro, and value, which consists of all characters up to a comment character or unescaped NEWLINE, is the value. make strips both leading and trailing white space in accepting the value.

Subsequent references to the macro, of the forms: $(name) or ${name} are replaced by value. The parentheses or brackets can be omitted in a reference to a macro with a single-character name.

Macro references can contain references to other macros, in which case nested references are expanded first.

Substitutions within macros can be made as follows:

 $(name:string1=string2)

where string1 is either a suffix, or a word to be replaced in the macro definition, and string2 is the replacement suffix or word. Words in a macro value are separated by SPACE, TAB, and escaped NEWLINE characters.

Pattern matching replacements can also be applied to macros, with a reference of the form:

 $(name: op%os= np%ns)

where op is the existing (old) prefix and os is the existing (old) suffix, np and ns are the new prefix and new suffix, respectively, and the pattern matched by % (a string of zero or more characters), is carried forward from the value being replaced. For example:

PROGRAM=fabricate
DEBUG= $(PROGRAM:%=tmp/%-g)

sets the value of DEBUG to tmp/fabricate-g.

Notice that pattern replacement macro references cannot be used in the dependency list of a pattern matching rule; the % characters are not evaluated independently. Also, any number of % metacharacters can appear after the equal-sign.

Words can be appended to macro values as follows:

 macro += word .\|.\|.

When the MAKEFLAGS variable is present in the environment, make takes options from it, in combination with options entered on the command line. make retains this combined value as the MAKEFLAGS macro, and exports it automatically to each command or shell it invokes.

Notice that flags passed by way of MAKEFLAGS are only displayed when the -d, or -dd options are in effect.

The MAKE macro is another special case. It has the value make by default, and temporarily overrides the -n option for any line in which it is referred to. This allows nested invocations of make written as:

 $(MAKE) .\|.\|.

to run recursively, with the -n flag in effect for all commands but make. This lets you use make -n to test an entire hierarchy of makefiles.

For compatibility with the 4.2 BSD make, the MFLAGS macro is set from the MAKEFLAGS variable by prepending a -. MFLAGS is not exported automatically.

The SHELL macro, when set to a single-word value such as /usr/bin/csh, indicates the name of an alternate shell to use. The default is /bin/sh. Notice that make executes commands that contain no shell metacharacters itself. Built-in commands, such as dirs in the C shell, are not recognized unless the command line includes a metacharacter (for instance, a semicolon). This macro is neither imported from, nor exported to the environment, regardless of -e. To be sure it is set properly, you must define this macro within every makefile that requires it.

The syntax of the VPATH macro is:

 VPATH = [ pathname [ : pathname ] ... ]

VPATH specifies a list of directories to search for the files, which are targets or dependencies, when make is executed. VPATH is also used in order to search for the include files mentioned in the particular makefile.

When processing a target or a dependency or an include directive, make checks the existence of the file with the same name in the current directory. If the file is found to be missing, make searches for this file in the list of directories presented in VPATH (like the PATH variable in the shell). Unlike the PATH variable, VPATH is used in order to search for the files with relative pathnames. When make attempts to apply implicit rules to the target, it also searches for the dependency files using VPATH.

When the file is found using VPATH, internal macros $@, @<, $?, $*, and their alternative forms (with D or F appended) are set in accordance with the name derived from VPATH. For instance, if the target subdir/foo.o is found in the directory /aaa/bbb using VPATH, then the value of the internal macro $@ for this target is /aaa/bbb/subdir/foo.o.

If a target or a dependency file is found using VPATH, then any occurrences of the word that is the same as the target name in the subsequent rules are replaced with the actual name of the target derived from VPATH.

For example:

VPATH=./subdir
file.o : file.c
 cc -c file.c -o file.o

If file.c is found in ./subdir, then the command

cc -c ./subdir/file.c -o file.o

are executed.

The following macros are provided for use with cross-compilation: HOST_ARCH

There are several dynamically maintained macros that are useful as abbreviations within rules. They are shown here as references; if you were to define them, make would simply override the definition. $*

To refer to the $@ dynamic macro within a dependency list, precede the reference with an additional $ character (as in, $$@). Because make assigns $< and $* as it would for implicit rules (according to the suffixes list and the directory contents), they can be unreliable when used within explicit target entries.

These macros can be modified to apply either to the filename part, or the directory part of the strings they stand for, by adding an upper case F or D, respectively (and enclosing the resulting name in parentheses or braces). Thus, $(@D) refers to the directory part of the string $@; if there is no directory part, . is assigned. $(@F) refers to the filename part.

A macro definition of the form:

target-list := macro = value

indicates that when processing any of the targets listed and their dependencies, macro is to be set to the value supplied. Notice that if a conditional macro is referred to in a dependency list, the $ must be delayed (use $$ instead). Also, target-list can contain a % pattern, in which case the macro is conditionally defined for all targets encountered that match the pattern. A pattern replacement reference can be used within the value.

You can temporarily append to a macros value with a conditional definition of the form:

target-list := macro += value

make supplies the macros shown in the table that follows for compilers and their options, host architectures, and other commands. Unless these macros are read in as environment variables, their values are not exported by make. If you run make with any of these set in the environment, it is a good idea to add commentary to the makefile to indicate what value each is expected to take. If -r is in effect, make does not read the default makefile (./make.rules or /usr/share/lib/make/make.rules) in which these macro definitions are supplied.

When a target has no entry in the makefile, make attempts to determine its class (if any) and apply the rule for that class. An implicit rule describes how to build any target of a given class, from an associated dependency file. The class of a target can be determined either by a pattern, or by a suffix; the corresponding dependency file (with the same basename) from which such a target might be built. In addition to a predefined set of implicit rules, make allows you to define your own, either by pattern, or by suffix.

A target entry of the form:

tp%ts:\|dp%ds
 rule

is a pattern matching rule, in which tp is a target prefix, ts is a target suffix, dp is a dependency prefix, and ds is a dependency suffix (any of which can be null). The % stands for a basename of zero or more characters that is matched in the target, and is used to construct the name of a dependency. When make encounters a match in its search for an implicit rule, it uses the rule in that target entry to build the target from the dependency file. Pattern-matching implicit rules typically make use of the $@ and $< dynamic macros as placeholders for the target and dependency names. Other, regular dependencies can occur in the dependency list; however, none of the regular dependencies can contain %. An entry of the form:

tp%ts:\|[dependency .\|.\|.\|] dp%ds\|[dependency .\|.\|.\|]
 rule

is a valid pattern matching rule.

When no pattern matching rule applies, make checks the target name to see if it ends with a suffix in the known suffixes list. If so, make checks for any suffix rules, as well as a dependency file with same root and another recognized suffix, from which to build it.

The target entry for a suffix rule takes the form:

DsTs: rule

where Ts is the suffix of the target, Ds is the suffix of the dependency file, and rule is the rule for building a target in the class. Both Ds and Ts must appear in the suffixes list. (A suffix need not begin with a . to be recognized.)

A suffix rule with only one suffix describes how to build a target having a null (or no) suffix from a dependency file with the indicated suffix. For instance, the .c rule could be used to build an executable program named file from a C source file named file.c. If a target with a null suffix has an explicit dependency, make omits the search for a suffix rule.

make reads in the standard set of implicit rules from the file /usr/share/lib/make/make.rules, unless -r is in effect, or there is a make.rules file in the local directory that does not include that file.

The suffixes list is given as the list of dependencies for the .SUFFIXES: special-function target. The default list is contained in the SUFFIXES macro (See Table of Predefined Macros for the standard list of suffixes). You can define additional .SUFFIXES: targets; a .SUFFIXES target with no dependencies clears the list of suffixes. Order is significant within the list; make selects a rule that corresponds to the target's suffix and the first dependency-file suffix found in the list. To place suffixes at the head of the list, clear the list and replace it with the new suffixes, followed by the default list:

 .SUFFIXES:
 .SUFFIXES: suffixes $(SUFFIXES)

A tilde (~) indicates that if a dependency file with the indicated suffix (minus the ~) is under SCCS its most recent version should be retrieved, if necessary, before the target is processed.

A target name of the form:

 lib(member ...)

refers to a member, or a space-separated list of members, in an ar(1) library.

The dependency of the library member on the corresponding file must be given as an explicit entry in the makefile. This can be handled by a pattern matching rule of the form:

 lib(%.s): %.s

where .s is the suffix of the member; this suffix is typically .o for object libraries.

A target name of the form:

 lib((symbol))

refers to the member of a randomized object library that defines the entry point named symbol.

Command lines are executed one at a time, each by its own process or shell. Shell commands, notably cd, are ineffectual across an unescaped NEWLINE in the makefile. A line is printed (after macro expansion) just before being executed. This is suppressed if it starts with a @, if there is a .SILENT: entry in the makefile, or if make is run with the -s option. Although the -n option specifies printing without execution, lines containing the macro $(MAKE) are executed regardless, and lines containing the @ special character are printed. The -t (touch) option updates the modification date of a file without executing any rules. This can be dangerous when sources are maintained by more than one person.

make invokes the shell with the -e (exit-on-errors) argument. Thus, with semicolon-separated command sequences, execution of the later commands depends on the success of the former. This behavior can be overridden by starting the command line with a \|-, or by writing a shell script that returns a non-zero status only as it finds appropriate.

To use the Bourne shell if control structure for branching, use a command line of the form:

if expression ; \e
then command ; \e
 ... ; \e
else command; \e
 ... ; \e
fi

Although composed of several input lines, the escaped NEWLINE characters insure that make treats them all as one (shell) command line.

To use the Bourne shell for control structure for loops, use a command line of the form:

for var in list ; \e
do command; \e
 ... ; \edone

To refer to a shell variable, use a double-dollar-sign ($$). This prevents expansion of the dollar-sign by make.

To incorporate the standard output of a shell command in a macro, use a definition of the form:

 MACRO\|:sh =command

The command is executed only once, standard error output is discarded, and NEWLINE characters are replaced with SPACEs. If the command has a non-zero exit status, make halts with an error.

To capture the output of a shell command in a macro reference, use a reference of the form:

$(MACRO\|:sh)

where MACRO is the name of a macro containing a valid Bourne shell command line. In this case, the command is executed whenever the reference is evaluated. As with shell command substitutions, the reference is replaced with the standard output of the command. If the command has a non-zero exit status, make halts with an error.

In contrast to commands in rules, the command is not subject for macro substitution; therefore, a dollar sign ($) need not be replaced with a double dollar sign ($$).

INT, SIGTERM, and QUIT signals received from the keyboard halt make and remove the target file being processed unless that target is in the dependency list for .PRECIOUS:.

Example 1 Defining dependencies

This makefile says that pgm depends on two files a.o and b.o, and that they in turn depend on their corresponding source files (a.c and b.c) along with a common file incl.h:

pgm: a.o b.o
 $(LINK.c) -o $@a.o b.o
a.o: incl.h a.c
 cc -c a.c
b.o: incl.h b.c
 cc -c b.c

Example 2 Using implicit rules

The following makefile uses implicit rules to express the same dependencies:

pgm: a.o b.o
 cc a.o b.o -o pgm
a.o b.o: incl.h

See environ(7) for descriptions of the following environment variables that affect the execution of make: LANG, LC_ALL, LC_CTYPE, LC_MESSAGES, and NLSPATH. DMAKE_MAX_JOBS

When the -q option is specified, the make utility exits with one of the following values: 0

When the -q option is not specified, the make utility exits with one of the following values: 0

Makefile

s.Makefile

SCCS/s.Makefile

See attributes(7) for descriptions of the following attributes:

ar (1), arch (1), cd (1), cpp (1), lex (1), mach (1), sccs-get (1), sh (1), sysV-make (1), yacc (1), wordexp (3C), passwd (5), POSIX.2 (7), attributes (7), environ (7), standards (7)

Solaris Advanced User's Guide

Could not open temporary statefile `file'
Could not delete old statefile `file'

Some commands return nonzero status inappropriately; to overcome this difficulty, prefix the offending command line in the rule with a -.

Filenames with the characters =, :, or @, do not work.

You cannot build file.o from lib(file.o).

Options supplied by MAKEFLAGS should be reported for nested make commands. Use the -d option to find out what options the nested command picks up from MAKEFLAGS.

This version of make is incompatible in certain respects with previous versions:

There is no guarantee that makefiles created for this version of make work with earlier versions.

If there is no make.rules file in the current directory, and the file /usr/share/lib/make/make.rules is missing, make stops before processing any targets. To force make to run anyway, create an empty make.rules file in the current directory.

Once a dependency is made, make assumes the dependency file is present for the remainder of the run. If a rule subsequently removes that file and future targets depend on its existence, unexpected errors can result.

When hidden dependency checking is in effect, the $? macro's value includes the names of hidden dependencies. This can lead to improper filename arguments to commands when $? is used in a rule.

Pattern replacement macro references cannot be used in the dependency list of a pattern matching rule.

Unlike previous versions, this version of make strips a leading ./ from the value of the $@ dynamic macro.

With automatic SCCS retrieval, this version of make does not support tilde suffix rules.

The only dynamic macro whose value is strictly determined when used in a dependency list is $@ (takes the form $$@).

make invokes the shell with the -e argument. This cannot be inferred from the syntax of the rule alone.