1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2024 Oxide Computer Company 14 */ 15 16 #ifndef _SPD_LP5_H 17 #define _SPD_LP5_H 18 19 /* 20 * Definitions for use in LPDDR5/LPDDR5X Serial Presence Detect decoding based 21 * on JEDEC standard JESD406-5 LPDDR5/5X Serial Presence Detect (SPD) Contents. 22 * Release 1.0. This does not cover DDR5. That is covered in spd_ddr5.h. 23 * 24 * LPDDR5/X modules are organized into a few main regions which is identical to 25 * DDR5; however, the contents vary: 26 * 27 * o Base Configuration, DRAM, and Module Parameters (0x00-0x7f) 28 * o Common Module Parameters (0xc0, 0xef) 29 * o Standard Module Parameters (0xf0-0x1bf) which vary on the specific DIMM 30 * type. 31 * o A CRC check for the first 510 bytes (0x1fe-0x1ff) 32 * o Manufacturing Information (0x200-0x27f) 33 * o Optional end-user programmable regions (0x280-0x3ff) 34 * 35 * This covers all LPDDR5/X variants other than NVDIMMs. 36 */ 37 38 #include <sys/bitext.h> 39 #include "spd_common.h" 40 41 #ifdef __cplusplus 42 extern "C" { 43 #endif 44 45 /* 46 * Number of Bytes in SPD Device and Beta Level 47 */ 48 #define SPD_LP5_NBYTES 0x00 49 #define SPD_LP5_NBYTES_BETAHI(r) bitx8(r, 7, 7) 50 #define SPD_LP5_NBYTES_TOTAL(r) bitx8(r, 6, 4) 51 #define SPD_LP5_NBYTES_TOTAL_UNDEF 0 52 #define SPD_LP5_NBYTES_TOTAL_256 1 53 #define SPD_LP5_NBYTES_TOTAL_512 2 54 #define SPD_LP5_NBYTES_TOTAL_1024 3 55 #define SPD_LP5_NBYTES_TOTAL_2048 4 56 #define SPD_LP5_NBYTES_BETA(r) bitx8(r, 3, 0) 57 58 /* 59 * SPD Revision for Base Configuration Parameters. This is the same as described 60 * in SPD_DDR4_SPD_REV as defined in spd_ddr4.h. 61 */ 62 #define SPD_LP5_SPD_REV 0x001 63 #define SPD_LP5_SPD_REV_ENC(r) bitx8(r, 7, 4) 64 #define SPD_LP5_SPD_REV_ADD(r) bitx8(r, 3, 0) 65 #define SPD_LP5_SPD_REV_V1 1 66 67 /* 68 * Key Byte / DRAM Device Type. This field identifies the type of DDR device and 69 * is actually consistent across all SPD versions. Known values are in the 70 * spd_dram_type_t enumeration. 71 */ 72 #define SPD_LP5_DRAM_TYPE 0x002 73 74 /* 75 * Key Byte / Module Type 76 */ 77 #define SPD_LP5_MOD_TYPE 0x003 78 #define SPD_LP5_MOD_TYPE_ISHYBRID(r) bitx8(r, 7, 7) 79 #define SPD_LP5_MOD_TYPE_HYBRID(r) bitx8(r, 6, 4) 80 #define SPD_LP5_MOD_TYPE_HYBRID_NONE 0 81 #define SPD_LP5_MOD_TYPE_HYBRID_NVDIMM_N 1 82 #define SPD_LP5_MOD_TYPE_HYBRID_NVDIMM_P 2 83 #define SPD_LP5_MOD_TYPE_TYPE(r) bitx8(r, 3, 0) 84 #define SPD_LP5_MOD_TYPE_TYPE_RDIMM 1 85 #define SPD_LP5_MOD_TYPE_TYPE_UDIMM 2 86 #define SPD_LP5_MOD_TYPE_TYPE_SODIMM 3 87 #define SPD_LP5_MOD_TYPE_TYPE_LRDIMM 4 88 #define SPD_LP5_MOD_TYPE_TYPE_CUDIMM 5 89 #define SPD_LP5_MOD_TYPE_TYPE_CSODIMM 6 90 #define SPD_LP5_MOD_TYPE_TYPE_MRDIMM 7 91 #define SPD_LP5_MOD_TYPE_TYPE_CAMM2 8 92 #define SPD_LP5_MOD_TYPE_TYPE_DDIMM 10 93 #define SPD_LP5_MOD_TYPE_TYPE_SOLDER 11 94 95 /* 96 * SDRAM Density and Banks 97 */ 98 #define SPD_LP5_DENSITY 0x004 99 #define SPD_LP5_DENSITY_NBG_BITS(r) bitx8(r, 7, 6) 100 #define SPD_LP5_DENSITY_NBG_BITS_MAX 2 101 #define SPD_LP5_DENSITY_NBA_BITS(r) bitx8(r, 5, 4) 102 #define SPD_LP5_DENSITY_NBA_BITS_BASE 2 103 #define SPD_LP5_DENSITY_NBA_BITS_MAX 4 104 #define SPD_LP5_DENSITY_DENSITY(r) bitx8(r, 3, 0) 105 #define SPD_LP5_DENSITY_DENSITY_1Gb 2 106 #define SPD_LP5_DENSITY_DENSITY_2Gb 3 107 #define SPD_LP5_DENSITY_DENSITY_4Gb 4 108 #define SPD_LP5_DENSITY_DENSITY_8Gb 5 109 #define SPD_LP5_DENSITY_DENSITY_16Gb 6 110 #define SPD_LP5_DENSITY_DENSITY_32Gb 7 111 #define SPD_LP5_DENSITY_DENSITY_12Gb 8 112 #define SPD_LP5_DENSITY_DENSITY_24Gb 9 113 #define SPD_LP5_DENSITY_DENSITY_3Gb 10 114 #define SPD_LP5_DENSITY_DENSITY_6Gb 11 115 116 /* 117 * SDRAM Addressing 118 * 119 * While the number of banks and bank groups is described above, the values for 120 * the number of columns is combined with the number of bank group and bank 121 * address bits. 122 */ 123 #define SPD_LP5_ADDRESS 0x005 124 #define SPD_LP5_ADDRESS_NROWS(x) bitx8(x, 5, 3) 125 #define SPD_LP5_ADDRESS_NROW_BASE 12 126 #define SPD_LP5_ADDRESS_NROW_MAX 18 127 #define SPD_LP5_ADDRESS_BCOL(x) bitx8(x, 2, 0) 128 #define SPD_LP5_ADDRESS_BCOL_3BA6C 0 129 #define SPD_LP5_ADDRESS_BCOL_4BA6C 1 130 131 /* 132 * SDRAM Package Type 133 */ 134 #define SPD_LP5_PKG 0x006 135 #define SPD_LP5_PKG_TYPE(r) bitx8(r, 7, 7) 136 #define SPD_LP5_PKG_TYPE_MONO 0 137 #define SPD_LP5_PKG_TYPE_NOT 1 138 #define SPD_LP5_PKG_DIE_CNT(r) bitx8(r, 6, 4) 139 #define SPD_LP5_DIE_CNT_1 0 140 #define SPD_LP5_DIE_CNT_2 1 141 #define SPD_LP5_DIE_CNT_3 2 142 #define SPD_LP5_DIE_CNT_4 3 143 #define SPD_LP5_DIE_CNT_5 4 144 #define SPD_LP5_DIE_CNT_6 5 145 #define SPD_LP5_DIE_CNT_16 6 146 #define SPD_LP5_DIE_CNT_8 7 147 #define SPD_LP5_PKG_DQSDW(r) bitx8(r, 3, 1) 148 #define SPD_LP5_PKG_DQSDW_1 0 149 #define SPD_LP5_PKG_DQSDW_16 1 150 #define SPD_LP5_PKG_DQSDW_2 2 151 #define SPD_LP5_PKG_DQSDW_4 4 152 #define SPD_LP5_PKG_DQSDW_8 8 153 #define SPD_LP5_PKG_SLIDX(r) bitx8(r, 1, 0) 154 #define SPD_LP5_PKG_SLIDX_UNSPEC 0 155 #define SPD_LP5_PKG_SLIDX_B16SLM1 1 156 157 /* 158 * Optional Features 159 */ 160 #define SPD_LP5_OPT_FEAT 0x009 161 #define SPD_LP5_OPT_FEAT_PPR(r) bitx8(r, 7, 6) 162 #define SPD_LP5_OPT_FEAT_PPR_NOTSUP 0 163 #define SPD_LP5_OPT_FEAT_PPR_SUP 1 164 #define SPD_LP5_OPT_FEAT_SOFT_PPR(r) bitx8(r, 5, 5) 165 166 /* 167 * Module Organization 168 */ 169 #define SPD_LP5_MOD_ORG 0x00c 170 #define SPD_LP5_MOD_ORG_IDENT(r) bitx8(r, 6, 6) 171 #define SPD_LP5_MOD_ORG_IDENT_STD 0 172 #define SPD_LP5_MOD_ORG_IDENT_BYTE 1 173 #define SPD_LP5_MOD_ORG_RANK(r) bitx8(r, 5, 3) 174 #define SPD_LP5_MOD_ORG_RANK_BASE 1 175 #define SPD_LP5_MOD_ORG_RANK_MAX 4 176 #define SPD_LP5_MOD_ORG_WIDTH(r) bitx8(r, 2, 0) 177 #define SPD_LP5_MOD_ORG_WIDTH_BASE 2 178 #define SPD_LP5_MOD_ORG_WIDTH_MAX 32 179 180 /* 181 * System Sub-Channel Bus Width 182 */ 183 #define SPD_LP5_WIDTH 0x00d 184 #define SPD_LP5_WIDTH_SUBCHAN(r) bitx8(r, 2, 0) 185 #define SP5_LP5_WIDTH_SUBCHAN_16b 1 186 #define SP5_LP5_WIDTH_SUBCHAN_32b 2 187 188 /* 189 * Signal Loading 190 * 191 * The values of the signal loading are dependent on the value found in the 192 * SPD_LP5_PKG (byte 6) register, The interpretation varies based on the value 193 * of SPD_LP5_PKG_SLIDX(). 194 */ 195 #define SPD_LP5_SIGLOAD 0x010 196 #define SPD_LP5_SIGLOAD1_DSM_LOAD(r) bitx8(r, 7, 6) 197 #define SPD_LP5_SIGLOAD1_DSM_LOAD_MAX 4 198 #define SPD_LP5_SIGLOAD1_CAC_LOAD(r) bitx8(r, 5, 3) 199 #define SPD_LP5_SIGLOAD1_CAC_LOAD_MAX 8 200 #define SPD_LP5_SIGLOAD1_CS_LOAD(r) bitx8(r, 2, 0) 201 #define SPD_LP5_SIGLOAD1_CS_LOAD_MAX 8 202 203 /* 204 * Timebases 205 * 206 * Like with DDR4, there are strictly speaking timebase values encoded in the 207 * registers that describe how to calculate other values. These are broken into 208 * the Medium and Fine timebases respectively which as of v1.0 have fixed 209 * values of 125ps and 1ps respectively. See the DDR4 version for more 210 * information. 211 */ 212 #define SPD_LP5_TIMEBASE 0x011 213 #define SPD_LP5_TIMEBASE_MTB(r) bitx8(r, 3, 2) 214 #define SPD_LP5_TIMEBASE_MTB_125ps 0 215 #define SPD_LP5_TIMEBASE_FTB(r) bitx8(r, 1, 0) 216 #define SPD_LP5_TIMEBASE_FTB_1ps 0 217 #define SPD_LP5_MTB_PS 125 218 #define SPD_LP5_FTB_PS 1 219 220 /* 221 * SDRAM Minimum Cycle Time t~ckavg~min. 222 * Fine Offset for ^ 223 * SDRAM Maximum Cycle Time t~ckavg~max. 224 * Fine Offset for ^ 225 */ 226 #define SPD_LP5_TCKAVG_MIN 0x012 227 #define SPD_LP5_TCKAVG_MIN_FINE 0x07d 228 #define SPD_LP5_TCKAVG_MAX 0x013 229 #define SPD_LP5_TCKAVG_MAX_FINE 0x07c 230 231 /* 232 * Minimum CAS Latency Time t~AA~min. This uses the MTB. 233 * Fine Offset for ^ 234 */ 235 #define SPD_LP5_TAA_MIN 0x018 236 #define SPD_LP5_TAA_MIN_FINE 0x07b 237 238 /* 239 * Minimum RAS to CAS Delay Time t~RCD~min. 240 * Fine Offset for ^ 241 */ 242 #define SPD_LP5_TRCD_MIN 0x01a 243 #define SPD_LP5_TRCD_MIN_FINE 0x07a 244 245 /* 246 * All Banks Minimum Row Precharge Delay Time t~RPab~min. 247 * Fine Offset for ^ 248 */ 249 #define SPD_LP5_TRPAB_MIN 0x01b 250 #define SPD_LP5_TRPAB_MIN_FINE 0x079 251 252 /* 253 * Per Bank Minimum Row Precharge Delay Time t~RPpb~min. 254 * Fine Offset for ^ 255 */ 256 #define SPD_LP5_TRPPB_MIN 0x01c 257 #define SPD_LP5_TRPPB_MIN_FINE 0x078 258 259 /* 260 * All Banks Minimum Refresh Recovery Delay Time t~RFCab~min. This is a 16-bit 261 * quantity that is split between a lower and upper value. Both registers are in 262 * terms of the medium time base. 263 */ 264 #define SPD_LP5_TRFCAB_MIN_LO 0x1d 265 #define SPD_LP5_TRFCAB_MIN_HI 0x1e 266 267 /* 268 * Per Bank Minimum Refresh Recovery Delay Time t~RFCpb~min. This is a 16-bit 269 * quantity that is split between a lower and upper value. Both registers are in 270 * terms of the medium time base. 271 */ 272 #define SPD_LP5_TRFCPB_MIN_LO 0x1f 273 #define SPD_LP5_TRFCPB_MIN_HI 0x20 274 275 /* 276 * DDR5 and LPDDR5/x share the common definitions for the module and 277 * manufacturer's information. The module-type specific overlays such as 278 * soldered down and CAMM2 are shared between all of them and are currently 279 * defined in the spd_ddr5.h header. 280 */ 281 282 #ifdef __cplusplus 283 } 284 #endif 285 286 #endif /* _SPD_LP5_H */ 287