1*8119dad8SRobert Mustacchi /* 2*8119dad8SRobert Mustacchi * This file and its contents are supplied under the terms of the 3*8119dad8SRobert Mustacchi * Common Development and Distribution License ("CDDL"), version 1.0. 4*8119dad8SRobert Mustacchi * You may only use this file in accordance with the terms of version 5*8119dad8SRobert Mustacchi * 1.0 of the CDDL. 6*8119dad8SRobert Mustacchi * 7*8119dad8SRobert Mustacchi * A full copy of the text of the CDDL should have accompanied this 8*8119dad8SRobert Mustacchi * source. A copy of the CDDL is also available via the Internet at 9*8119dad8SRobert Mustacchi * http://www.illumos.org/license/CDDL. 10*8119dad8SRobert Mustacchi */ 11*8119dad8SRobert Mustacchi 12*8119dad8SRobert Mustacchi /* 13*8119dad8SRobert Mustacchi * Copyright 2024 Oxide Computer Company 14*8119dad8SRobert Mustacchi */ 15*8119dad8SRobert Mustacchi 16*8119dad8SRobert Mustacchi #ifndef _SPD_LP5_H 17*8119dad8SRobert Mustacchi #define _SPD_LP5_H 18*8119dad8SRobert Mustacchi 19*8119dad8SRobert Mustacchi /* 20*8119dad8SRobert Mustacchi * Definitions for use in LPDDR5/LPDDR5X Serial Presence Detect decoding based 21*8119dad8SRobert Mustacchi * on JEDEC standard JESD406-5 LPDDR5/5X Serial Presence Detect (SPD) Contents. 22*8119dad8SRobert Mustacchi * Release 1.0. This does not cover DDR5. That is covered in spd_ddr5.h. 23*8119dad8SRobert Mustacchi * 24*8119dad8SRobert Mustacchi * LPDDR5/X modules are organized into a few main regions which is identical to 25*8119dad8SRobert Mustacchi * DDR5; however, the contents vary: 26*8119dad8SRobert Mustacchi * 27*8119dad8SRobert Mustacchi * o Base Configuration, DRAM, and Module Parameters (0x00-0x7f) 28*8119dad8SRobert Mustacchi * o Common Module Parameters (0xc0, 0xef) 29*8119dad8SRobert Mustacchi * o Standard Module Parameters (0xf0-0x1bf) which vary on the specific DIMM 30*8119dad8SRobert Mustacchi * type. 31*8119dad8SRobert Mustacchi * o A CRC check for the first 510 bytes (0x1fe-0x1ff) 32*8119dad8SRobert Mustacchi * o Manufacturing Information (0x200-0x27f) 33*8119dad8SRobert Mustacchi * o Optional end-user programmable regions (0x280-0x3ff) 34*8119dad8SRobert Mustacchi * 35*8119dad8SRobert Mustacchi * This covers all LPDDR5/X variants other than NVDIMMs. 36*8119dad8SRobert Mustacchi */ 37*8119dad8SRobert Mustacchi 38*8119dad8SRobert Mustacchi #include <sys/bitext.h> 39*8119dad8SRobert Mustacchi #include "spd_common.h" 40*8119dad8SRobert Mustacchi 41*8119dad8SRobert Mustacchi #ifdef __cplusplus 42*8119dad8SRobert Mustacchi extern "C" { 43*8119dad8SRobert Mustacchi #endif 44*8119dad8SRobert Mustacchi 45*8119dad8SRobert Mustacchi /* 46*8119dad8SRobert Mustacchi * Number of Bytes in SPD Device and Beta Level 47*8119dad8SRobert Mustacchi */ 48*8119dad8SRobert Mustacchi #define SPD_LP5_NBYTES 0x00 49*8119dad8SRobert Mustacchi #define SPD_LP5_NBYTES_BETAHI(r) bitx8(r, 7, 7) 50*8119dad8SRobert Mustacchi #define SPD_LP5_NBYTES_TOTAL(r) bitx8(r, 6, 4) 51*8119dad8SRobert Mustacchi #define SPD_LP5_NBYTES_TOTAL_UNDEF 0 52*8119dad8SRobert Mustacchi #define SPD_LP5_NBYTES_TOTAL_256 1 53*8119dad8SRobert Mustacchi #define SPD_LP5_NBYTES_TOTAL_512 2 54*8119dad8SRobert Mustacchi #define SPD_LP5_NBYTES_TOTAL_1024 3 55*8119dad8SRobert Mustacchi #define SPD_LP5_NBYTES_TOTAL_2048 4 56*8119dad8SRobert Mustacchi #define SPD_LP5_NBYTES_BETA(r) bitx8(r, 3, 0) 57*8119dad8SRobert Mustacchi 58*8119dad8SRobert Mustacchi /* 59*8119dad8SRobert Mustacchi * SPD Revision for Base Configuration Parameters. This is the same as described 60*8119dad8SRobert Mustacchi * in SPD_DDR4_SPD_REV as defined in spd_ddr4.h. 61*8119dad8SRobert Mustacchi */ 62*8119dad8SRobert Mustacchi #define SPD_LP5_SPD_REV 0x001 63*8119dad8SRobert Mustacchi #define SPD_LP5_SPD_REV_ENC(r) bitx8(r, 7, 4) 64*8119dad8SRobert Mustacchi #define SPD_LP5_SPD_REV_ADD(r) bitx8(r, 3, 0) 65*8119dad8SRobert Mustacchi #define SPD_LP5_SPD_REV_V1 1 66*8119dad8SRobert Mustacchi 67*8119dad8SRobert Mustacchi /* 68*8119dad8SRobert Mustacchi * Key Byte / DRAM Device Type. This field identifies the type of DDR device and 69*8119dad8SRobert Mustacchi * is actually consistent across all SPD versions. Known values are in the 70*8119dad8SRobert Mustacchi * spd_dram_type_t enumeration. 71*8119dad8SRobert Mustacchi */ 72*8119dad8SRobert Mustacchi #define SPD_LP5_DRAM_TYPE 0x002 73*8119dad8SRobert Mustacchi 74*8119dad8SRobert Mustacchi /* 75*8119dad8SRobert Mustacchi * Key Byte / Module Type 76*8119dad8SRobert Mustacchi */ 77*8119dad8SRobert Mustacchi #define SPD_LP5_MOD_TYPE 0x003 78*8119dad8SRobert Mustacchi #define SPD_LP5_MOD_TYPE_ISHYBRID(r) bitx8(r, 7, 7) 79*8119dad8SRobert Mustacchi #define SPD_LP5_MOD_TYPE_HYBRID(r) bitx8(r, 6, 4) 80*8119dad8SRobert Mustacchi #define SPD_LP5_MOD_TYPE_HYBRID_NONE 0 81*8119dad8SRobert Mustacchi #define SPD_LP5_MOD_TYPE_HYBRID_NVDIMM_N 1 82*8119dad8SRobert Mustacchi #define SPD_LP5_MOD_TYPE_HYBRID_NVDIMM_P 2 83*8119dad8SRobert Mustacchi #define SPD_LP5_MOD_TYPE_TYPE(r) bitx8(r, 3, 0) 84*8119dad8SRobert Mustacchi #define SPD_LP5_MOD_TYPE_TYPE_RDIMM 1 85*8119dad8SRobert Mustacchi #define SPD_LP5_MOD_TYPE_TYPE_UDIMM 2 86*8119dad8SRobert Mustacchi #define SPD_LP5_MOD_TYPE_TYPE_SODIMM 3 87*8119dad8SRobert Mustacchi #define SPD_LP5_MOD_TYPE_TYPE_LRDIMM 4 88*8119dad8SRobert Mustacchi #define SPD_LP5_MOD_TYPE_TYPE_CUDIMM 5 89*8119dad8SRobert Mustacchi #define SPD_LP5_MOD_TYPE_TYPE_CSODIMM 6 90*8119dad8SRobert Mustacchi #define SPD_LP5_MOD_TYPE_TYPE_MRDIMM 7 91*8119dad8SRobert Mustacchi #define SPD_LP5_MOD_TYPE_TYPE_CAMM2 8 92*8119dad8SRobert Mustacchi #define SPD_LP5_MOD_TYPE_TYPE_DDIMM 10 93*8119dad8SRobert Mustacchi #define SPD_LP5_MOD_TYPE_TYPE_SOLDER 11 94*8119dad8SRobert Mustacchi 95*8119dad8SRobert Mustacchi /* 96*8119dad8SRobert Mustacchi * SDRAM Density and Banks 97*8119dad8SRobert Mustacchi */ 98*8119dad8SRobert Mustacchi #define SPD_LP5_DENSITY 0x004 99*8119dad8SRobert Mustacchi #define SPD_LP5_DENSITY_NBG_BITS(r) bitx8(r, 7, 6) 100*8119dad8SRobert Mustacchi #define SPD_LP5_DENSITY_NBG_BITS_MAX 2 101*8119dad8SRobert Mustacchi #define SPD_LP5_DENSITY_NBA_BITS(r) bitx8(r, 5, 4) 102*8119dad8SRobert Mustacchi #define SPD_LP5_DENSITY_NBA_BITS_BASE 2 103*8119dad8SRobert Mustacchi #define SPD_LP5_DENSITY_NBA_BITS_MAX 4 104*8119dad8SRobert Mustacchi #define SPD_LP5_DENSITY_DENSITY(r) bitx8(r, 3, 0) 105*8119dad8SRobert Mustacchi #define SPD_LP5_DENSITY_DENSITY_1Gb 2 106*8119dad8SRobert Mustacchi #define SPD_LP5_DENSITY_DENSITY_2Gb 3 107*8119dad8SRobert Mustacchi #define SPD_LP5_DENSITY_DENSITY_4Gb 4 108*8119dad8SRobert Mustacchi #define SPD_LP5_DENSITY_DENSITY_8Gb 5 109*8119dad8SRobert Mustacchi #define SPD_LP5_DENSITY_DENSITY_16Gb 6 110*8119dad8SRobert Mustacchi #define SPD_LP5_DENSITY_DENSITY_32Gb 7 111*8119dad8SRobert Mustacchi #define SPD_LP5_DENSITY_DENSITY_12Gb 8 112*8119dad8SRobert Mustacchi #define SPD_LP5_DENSITY_DENSITY_24Gb 9 113*8119dad8SRobert Mustacchi #define SPD_LP5_DENSITY_DENSITY_3Gb 10 114*8119dad8SRobert Mustacchi #define SPD_LP5_DENSITY_DENSITY_6Gb 11 115*8119dad8SRobert Mustacchi 116*8119dad8SRobert Mustacchi /* 117*8119dad8SRobert Mustacchi * SDRAM Addressing 118*8119dad8SRobert Mustacchi * 119*8119dad8SRobert Mustacchi * While the number of banks and bank groups is described above, the values for 120*8119dad8SRobert Mustacchi * the number of columns is combined with the number of bank group and bank 121*8119dad8SRobert Mustacchi * address bits. 122*8119dad8SRobert Mustacchi */ 123*8119dad8SRobert Mustacchi #define SPD_LP5_ADDRESS 0x005 124*8119dad8SRobert Mustacchi #define SPD_LP5_ADDRESS_NROWS(x) bitx8(x, 5, 3) 125*8119dad8SRobert Mustacchi #define SPD_LP5_ADDRESS_NROW_BASE 12 126*8119dad8SRobert Mustacchi #define SPD_LP5_ADDRESS_NROW_MAX 18 127*8119dad8SRobert Mustacchi #define SPD_LP5_ADDRESS_BCOL(x) bitx8(x, 2, 0) 128*8119dad8SRobert Mustacchi #define SPD_LP5_ADDRESS_BCOL_3BA6C 0 129*8119dad8SRobert Mustacchi #define SPD_LP5_ADDRESS_BCOL_4BA6C 1 130*8119dad8SRobert Mustacchi 131*8119dad8SRobert Mustacchi /* 132*8119dad8SRobert Mustacchi * SDRAM Package Type 133*8119dad8SRobert Mustacchi */ 134*8119dad8SRobert Mustacchi #define SPD_LP5_PKG 0x006 135*8119dad8SRobert Mustacchi #define SPD_LP5_PKG_TYPE(r) bitx8(r, 7, 7) 136*8119dad8SRobert Mustacchi #define SPD_LP5_PKG_TYPE_MONO 0 137*8119dad8SRobert Mustacchi #define SPD_LP5_PKG_TYPE_NOT 1 138*8119dad8SRobert Mustacchi #define SPD_LP5_PKG_DIE_CNT(r) bitx8(r, 6, 4) 139*8119dad8SRobert Mustacchi #define SPD_LP5_DIE_CNT_1 0 140*8119dad8SRobert Mustacchi #define SPD_LP5_DIE_CNT_2 1 141*8119dad8SRobert Mustacchi #define SPD_LP5_DIE_CNT_3 2 142*8119dad8SRobert Mustacchi #define SPD_LP5_DIE_CNT_4 3 143*8119dad8SRobert Mustacchi #define SPD_LP5_DIE_CNT_5 4 144*8119dad8SRobert Mustacchi #define SPD_LP5_DIE_CNT_6 5 145*8119dad8SRobert Mustacchi #define SPD_LP5_DIE_CNT_16 6 146*8119dad8SRobert Mustacchi #define SPD_LP5_DIE_CNT_8 7 147*8119dad8SRobert Mustacchi #define SPD_LP5_PKG_DQSDW(r) bitx8(r, 3, 1) 148*8119dad8SRobert Mustacchi #define SPD_LP5_PKG_DQSDW_1 0 149*8119dad8SRobert Mustacchi #define SPD_LP5_PKG_DQSDW_16 1 150*8119dad8SRobert Mustacchi #define SPD_LP5_PKG_DQSDW_2 2 151*8119dad8SRobert Mustacchi #define SPD_LP5_PKG_DQSDW_4 4 152*8119dad8SRobert Mustacchi #define SPD_LP5_PKG_DQSDW_8 8 153*8119dad8SRobert Mustacchi #define SPD_LP5_PKG_SLIDX(r) bitx8(r, 1, 0) 154*8119dad8SRobert Mustacchi #define SPD_LP5_PKG_SLIDX_UNSPEC 0 155*8119dad8SRobert Mustacchi #define SPD_LP5_PKG_SLIDX_B16SLM1 1 156*8119dad8SRobert Mustacchi 157*8119dad8SRobert Mustacchi /* 158*8119dad8SRobert Mustacchi * Optional Features 159*8119dad8SRobert Mustacchi */ 160*8119dad8SRobert Mustacchi #define SPD_LP5_OPT_FEAT 0x009 161*8119dad8SRobert Mustacchi #define SPD_LP5_OPT_FEAT_PPR(r) bitx8(r, 7, 6) 162*8119dad8SRobert Mustacchi #define SPD_LP5_OPT_FEAT_PPR_NOTSUP 0 163*8119dad8SRobert Mustacchi #define SPD_LP5_OPT_FEAT_PPR_SUP 1 164*8119dad8SRobert Mustacchi #define SPD_LP5_OPT_FEAT_SOFT_PPR(r) bitx8(r, 5, 5) 165*8119dad8SRobert Mustacchi 166*8119dad8SRobert Mustacchi /* 167*8119dad8SRobert Mustacchi * Module Organization 168*8119dad8SRobert Mustacchi */ 169*8119dad8SRobert Mustacchi #define SPD_LP5_MOD_ORG 0x00c 170*8119dad8SRobert Mustacchi #define SPD_LP5_MOD_ORG_IDENT(r) bitx8(r, 6, 6) 171*8119dad8SRobert Mustacchi #define SPD_LP5_MOD_ORG_IDENT_STD 0 172*8119dad8SRobert Mustacchi #define SPD_LP5_MOD_ORG_IDENT_BYTE 1 173*8119dad8SRobert Mustacchi #define SPD_LP5_MOD_ORG_RANK(r) bitx8(r, 5, 3) 174*8119dad8SRobert Mustacchi #define SPD_LP5_MOD_ORG_RANK_BASE 1 175*8119dad8SRobert Mustacchi #define SPD_LP5_MOD_ORG_RANK_MAX 4 176*8119dad8SRobert Mustacchi #define SPD_LP5_MOD_ORG_WIDTH(r) bitx8(r, 2, 0) 177*8119dad8SRobert Mustacchi #define SPD_LP5_MOD_ORG_WIDTH_BASE 2 178*8119dad8SRobert Mustacchi #define SPD_LP5_MOD_ORG_WIDTH_MAX 32 179*8119dad8SRobert Mustacchi 180*8119dad8SRobert Mustacchi /* 181*8119dad8SRobert Mustacchi * System Sub-Channel Bus Width 182*8119dad8SRobert Mustacchi */ 183*8119dad8SRobert Mustacchi #define SPD_LP5_WIDTH 0x00d 184*8119dad8SRobert Mustacchi #define SPD_LP5_WIDTH_SUBCHAN(r) bitx8(r, 2, 0) 185*8119dad8SRobert Mustacchi #define SP5_LP5_WIDTH_SUBCHAN_16b 1 186*8119dad8SRobert Mustacchi #define SP5_LP5_WIDTH_SUBCHAN_32b 2 187*8119dad8SRobert Mustacchi 188*8119dad8SRobert Mustacchi /* 189*8119dad8SRobert Mustacchi * Signal Loading 190*8119dad8SRobert Mustacchi * 191*8119dad8SRobert Mustacchi * The values of the signal loading are dependent on the value found in the 192*8119dad8SRobert Mustacchi * SPD_LP5_PKG (byte 6) register, The interpretation varies based on the value 193*8119dad8SRobert Mustacchi * of SPD_LP5_PKG_SLIDX(). 194*8119dad8SRobert Mustacchi */ 195*8119dad8SRobert Mustacchi #define SPD_LP5_SIGLOAD 0x010 196*8119dad8SRobert Mustacchi #define SPD_LP5_SIGLOAD1_DSM_LOAD(r) bitx8(r, 7, 6) 197*8119dad8SRobert Mustacchi #define SPD_LP5_SIGLOAD1_DSM_LOAD_MAX 4 198*8119dad8SRobert Mustacchi #define SPD_LP5_SIGLOAD1_CAC_LOAD(r) bitx8(r, 5, 3) 199*8119dad8SRobert Mustacchi #define SPD_LP5_SIGLOAD1_CAC_LOAD_MAX 8 200*8119dad8SRobert Mustacchi #define SPD_LP5_SIGLOAD1_CS_LOAD(r) bitx8(r, 2, 0) 201*8119dad8SRobert Mustacchi #define SPD_LP5_SIGLOAD1_CS_LOAD_MAX 8 202*8119dad8SRobert Mustacchi 203*8119dad8SRobert Mustacchi /* 204*8119dad8SRobert Mustacchi * Timebases 205*8119dad8SRobert Mustacchi * 206*8119dad8SRobert Mustacchi * Like with DDR4, there are strictly speaking timebase values encoded in the 207*8119dad8SRobert Mustacchi * registers that describe how to calculate other values. These are broken into 208*8119dad8SRobert Mustacchi * the Medium and Fine timebases respectively which as of v1.0 have fixed 209*8119dad8SRobert Mustacchi * values of 125ps and 1ps respectively. See the DDR4 version for more 210*8119dad8SRobert Mustacchi * information. 211*8119dad8SRobert Mustacchi */ 212*8119dad8SRobert Mustacchi #define SPD_LP5_TIMEBASE 0x011 213*8119dad8SRobert Mustacchi #define SPD_LP5_TIMEBASE_MTB(r) bitx8(r, 3, 2) 214*8119dad8SRobert Mustacchi #define SPD_LP5_TIMEBASE_MTB_125ps 0 215*8119dad8SRobert Mustacchi #define SPD_LP5_TIMEBASE_FTB(r) bitx8(r, 1, 0) 216*8119dad8SRobert Mustacchi #define SPD_LP5_TIMEBASE_FTB_1ps 0 217*8119dad8SRobert Mustacchi #define SPD_LP5_MTB_PS 125 218*8119dad8SRobert Mustacchi #define SPD_LP5_FTB_PS 1 219*8119dad8SRobert Mustacchi 220*8119dad8SRobert Mustacchi /* 221*8119dad8SRobert Mustacchi * SDRAM Minimum Cycle Time t~ckavg~min. 222*8119dad8SRobert Mustacchi * Fine Offset for ^ 223*8119dad8SRobert Mustacchi * SDRAM Maximum Cycle Time t~ckavg~max. 224*8119dad8SRobert Mustacchi * Fine Offset for ^ 225*8119dad8SRobert Mustacchi */ 226*8119dad8SRobert Mustacchi #define SPD_LP5_TCKAVG_MIN 0x012 227*8119dad8SRobert Mustacchi #define SPD_LP5_TCKAVG_MIN_FINE 0x07d 228*8119dad8SRobert Mustacchi #define SPD_LP5_TCKAVG_MAX 0x013 229*8119dad8SRobert Mustacchi #define SPD_LP5_TCKAVG_MAX_FINE 0x07c 230*8119dad8SRobert Mustacchi 231*8119dad8SRobert Mustacchi /* 232*8119dad8SRobert Mustacchi * Minimum CAS Latency Time t~AA~min. This uses the MTB. 233*8119dad8SRobert Mustacchi * Fine Offset for ^ 234*8119dad8SRobert Mustacchi */ 235*8119dad8SRobert Mustacchi #define SPD_LP5_TAA_MIN 0x018 236*8119dad8SRobert Mustacchi #define SPD_LP5_TAA_MIN_FINE 0x07b 237*8119dad8SRobert Mustacchi 238*8119dad8SRobert Mustacchi /* 239*8119dad8SRobert Mustacchi * Minimum RAS to CAS Delay Time t~RCD~min. 240*8119dad8SRobert Mustacchi * Fine Offset for ^ 241*8119dad8SRobert Mustacchi */ 242*8119dad8SRobert Mustacchi #define SPD_LP5_TRCD_MIN 0x01a 243*8119dad8SRobert Mustacchi #define SPD_LP5_TRCD_MIN_FINE 0x07a 244*8119dad8SRobert Mustacchi 245*8119dad8SRobert Mustacchi /* 246*8119dad8SRobert Mustacchi * All Banks Minimum Row Precharge Delay Time t~RPab~min. 247*8119dad8SRobert Mustacchi * Fine Offset for ^ 248*8119dad8SRobert Mustacchi */ 249*8119dad8SRobert Mustacchi #define SPD_LP5_TRPAB_MIN 0x01b 250*8119dad8SRobert Mustacchi #define SPD_LP5_TRPAB_MIN_FINE 0x079 251*8119dad8SRobert Mustacchi 252*8119dad8SRobert Mustacchi /* 253*8119dad8SRobert Mustacchi * Per Bank Minimum Row Precharge Delay Time t~RPpb~min. 254*8119dad8SRobert Mustacchi * Fine Offset for ^ 255*8119dad8SRobert Mustacchi */ 256*8119dad8SRobert Mustacchi #define SPD_LP5_TRPPB_MIN 0x01c 257*8119dad8SRobert Mustacchi #define SPD_LP5_TRPPB_MIN_FINE 0x078 258*8119dad8SRobert Mustacchi 259*8119dad8SRobert Mustacchi /* 260*8119dad8SRobert Mustacchi * All Banks Minimum Refresh Recovery Delay Time t~RFCab~min. This is a 16-bit 261*8119dad8SRobert Mustacchi * quantity that is split between a lower and upper value. Both registers are in 262*8119dad8SRobert Mustacchi * terms of the medium time base. 263*8119dad8SRobert Mustacchi */ 264*8119dad8SRobert Mustacchi #define SPD_LP5_TRFCAB_MIN_LO 0x1d 265*8119dad8SRobert Mustacchi #define SPD_LP5_TRFCAB_MIN_HI 0x1e 266*8119dad8SRobert Mustacchi 267*8119dad8SRobert Mustacchi /* 268*8119dad8SRobert Mustacchi * Per Bank Minimum Refresh Recovery Delay Time t~RFCpb~min. This is a 16-bit 269*8119dad8SRobert Mustacchi * quantity that is split between a lower and upper value. Both registers are in 270*8119dad8SRobert Mustacchi * terms of the medium time base. 271*8119dad8SRobert Mustacchi */ 272*8119dad8SRobert Mustacchi #define SPD_LP5_TRFCPB_MIN_LO 0x1f 273*8119dad8SRobert Mustacchi #define SPD_LP5_TRFCPB_MIN_HI 0x20 274*8119dad8SRobert Mustacchi 275*8119dad8SRobert Mustacchi /* 276*8119dad8SRobert Mustacchi * DDR5 and LPDDR5/x share the common definitions for the module and 277*8119dad8SRobert Mustacchi * manufacturer's information. The module-type specific overlays such as 278*8119dad8SRobert Mustacchi * soldered down and CAMM2 are shared between all of them and are currently 279*8119dad8SRobert Mustacchi * defined in the spd_ddr5.h header. 280*8119dad8SRobert Mustacchi */ 281*8119dad8SRobert Mustacchi 282*8119dad8SRobert Mustacchi #ifdef __cplusplus 283*8119dad8SRobert Mustacchi } 284*8119dad8SRobert Mustacchi #endif 285*8119dad8SRobert Mustacchi 286*8119dad8SRobert Mustacchi #endif /* _SPD_LP5_H */ 287